[mirror_ubuntu-zesty-kernel.git] / drivers / rtc / rtc-sa1100.c

/*
 * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
 *
 * Copyright (c) 2000 Nils Faerber
 *
 * Based on rtc.c by Paul Gortmaker
 *
 * Original Driver by Nils Faerber <nils@kernelconcepts.de>
 *
 * Modifications from:
 *   CIH <cih@coventive.com>
 *   Nicolas Pitre <nico@fluxnic.net>
 *   Andrew Christian <andrew.christian@hp.com>
 *
 * Converted to the RTC subsystem and Driver Model
 *   by Richard Purdie <rpurdie@rpsys.net>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <asm/irq.h>

#define RTC_DEF_DIVIDER		(32768 - 1)
#define RTC_DEF_TRIM		0
#define RTC_FREQ		1024

#define RCNR		0x00	/* RTC Count Register */
#define RTAR		0x04	/* RTC Alarm Register */
#define RTSR		0x08	/* RTC Status Register */
#define RTTR		0x0c	/* RTC Timer Trim Register */

#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
#define RTSR_AL		(1 << 0)	/* RTC alarm detected */

#define rtc_readl(sa1100_rtc, reg)	\
	readl_relaxed((sa1100_rtc)->base + (reg))
#define rtc_writel(sa1100_rtc, reg, value)	\
	writel_relaxed((value), (sa1100_rtc)->base + (reg))

struct sa1100_rtc {
	struct resource		*ress;
	void __iomem		*base;
	struct clk		*clk;
	int			irq_1Hz;
	int			irq_Alrm;
	struct rtc_device	*rtc;
	spinlock_t		lock;		/* Protects this structure */
};
/*
 * Calculate the next alarm time given the requested alarm time mask
 * and the current time.
 */
static void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now,
	struct rtc_time *alrm)
{
	unsigned long next_time;
	unsigned long now_time;

	next->tm_year = now->tm_year;
	next->tm_mon = now->tm_mon;
	next->tm_mday = now->tm_mday;
	next->tm_hour = alrm->tm_hour;
	next->tm_min = alrm->tm_min;
	next->tm_sec = alrm->tm_sec;

	rtc_tm_to_time(now, &now_time);
	rtc_tm_to_time(next, &next_time);

	if (next_time < now_time) {
		/* Advance one day */
		next_time += 60 * 60 * 24;
		rtc_time_to_tm(next_time, next);
	}
}

static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = to_platform_device(dev_id);
	struct sa1100_rtc *sa1100_rtc = platform_get_drvdata(pdev);
	unsigned int rtsr;
	unsigned long events = 0;

	spin_lock(&sa1100_rtc->lock);

	/* clear interrupt sources */
	rtsr = rtc_readl(sa1100_rtc, RTSR);
	rtc_writel(sa1100_rtc, RTSR, 0);

	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
	 * See also the comments in sa1100_rtc_probe(). */
	if (rtsr & (RTSR_ALE | RTSR_HZE)) {
		/* This is the original code, before there was the if test
		 * above. This code does not clear interrupts that were not
		 * enabled. */
		rtc_writel(sa1100_rtc, RTSR, (RTSR_AL | RTSR_HZ) & (rtsr >> 2));
	} else {
		/* For some reason, it is possible to enter this routine
		 * without interruptions enabled, it has been tested with
		 * several units (Bug in SA11xx chip?).
		 *
		 * This situation leads to an infinite "loop" of interrupt
		 * routine calling and as a result the processor seems to
		 * lock on its first call to open(). */
		rtc_writel(sa1100_rtc, RTSR, (RTSR_AL | RTSR_HZ));
	}

	/* clear alarm interrupt if it has occurred */
	if (rtsr & RTSR_AL)
		rtsr &= ~RTSR_ALE;
	rtc_writel(sa1100_rtc, RTSR, rtsr & (RTSR_ALE | RTSR_HZE));

	/* update irq data & counter */
	if (rtsr & RTSR_AL)
		events |= RTC_AF | RTC_IRQF;
	if (rtsr & RTSR_HZ)
		events |= RTC_UF | RTC_IRQF;

	rtc_update_irq(sa1100_rtc->rtc, 1, events);

	spin_unlock(&sa1100_rtc->lock);

	return IRQ_HANDLED;
}

static int sa1100_rtc_open(struct device *dev)
{
	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
	int ret;

	ret = request_irq(sa1100_rtc->irq_1Hz, sa1100_rtc_interrupt,
				IRQF_DISABLED, "rtc 1Hz", dev);
	if (ret) {
		dev_err(dev, "IRQ %d already in use.\n", sa1100_rtc->irq_1Hz);
		goto fail_ui;
	}
	ret = request_irq(sa1100_rtc->irq_Alrm, sa1100_rtc_interrupt,
				IRQF_DISABLED, "rtc Alrm", dev);
	if (ret) {
		dev_err(dev, "IRQ %d already in use.\n", sa1100_rtc->irq_Alrm);
		goto fail_ai;
	}
	sa1100_rtc->rtc->max_user_freq = RTC_FREQ;
	rtc_irq_set_freq(sa1100_rtc->rtc, NULL, RTC_FREQ);

	return 0;

 fail_ai:
	free_irq(sa1100_rtc->irq_1Hz, dev);
 fail_ui:
	return ret;
}

static void sa1100_rtc_release(struct device *dev)
{
	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);

	spin_lock_irq(&sa1100_rtc->lock);
	rtc_writel(sa1100_rtc, RTSR, 0);
	spin_unlock_irq(&sa1100_rtc->lock);

	free_irq(sa1100_rtc->irq_Alrm, dev);
	free_irq(sa1100_rtc->irq_1Hz, dev);
}

static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
	unsigned int rtsr;

	spin_lock_irq(&sa1100_rtc->lock);

	rtsr = rtc_readl(sa1100_rtc, RTSR);
	if (enabled)
		rtsr |= RTSR_ALE;
	else
		rtsr &= ~RTSR_ALE;
	rtc_writel(sa1100_rtc, RTSR, rtsr);

	spin_unlock_irq(&sa1100_rtc->lock);
	return 0;
}

static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);

	rtc_time_to_tm(rtc_readl(sa1100_rtc, RCNR), tm);
	return 0;
}

static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
	unsigned long time;
	int ret;

	ret = rtc_tm_to_time(tm, &time);
	if (ret == 0)
		rtc_writel(sa1100_rtc, RCNR, time);
	return ret;
}

static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
	unsigned long time;
	unsigned int rtsr;

	time = rtc_readl(sa1100_rtc, RCNR);
	rtc_time_to_tm(time, &alrm->time);
	rtsr = rtc_readl(sa1100_rtc, RTSR);
	alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
	alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
	return 0;
}

static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
	struct rtc_time now_tm, alarm_tm;
	unsigned long time, alarm;
	unsigned int rtsr;

	spin_lock_irq(&sa1100_rtc->lock);

	time = rtc_readl(sa1100_rtc, RCNR);
	rtc_time_to_tm(time, &now_tm);
	rtc_next_alarm_time(&alarm_tm, &now_tm, &alrm->time);
	rtc_tm_to_time(&alarm_tm, &alarm);
	rtc_writel(sa1100_rtc, RTAR, alarm);

	rtsr = rtc_readl(sa1100_rtc, RTSR);
	if (alrm->enabled)
		rtsr |= RTSR_ALE;
	else
		rtsr &= ~RTSR_ALE;
	rtc_writel(sa1100_rtc, RTSR, rtsr);

	spin_unlock_irq(&sa1100_rtc->lock);

	return 0;
}

static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq)
{
	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);

	seq_printf(seq, "trim/divider\t\t: 0x%08x\n",
			rtc_readl(sa1100_rtc, RTTR));
	seq_printf(seq, "RTSR\t\t\t: 0x%08x\n",
			rtc_readl(sa1100_rtc, RTSR));
	return 0;
}

static const struct rtc_class_ops sa1100_rtc_ops = {
	.open = sa1100_rtc_open,
	.release = sa1100_rtc_release,
	.read_time = sa1100_rtc_read_time,
	.set_time = sa1100_rtc_set_time,
	.read_alarm = sa1100_rtc_read_alarm,
	.set_alarm = sa1100_rtc_set_alarm,
	.proc = sa1100_rtc_proc,
	.alarm_irq_enable = sa1100_rtc_alarm_irq_enable,
};

static int sa1100_rtc_probe(struct platform_device *pdev)
{
	struct sa1100_rtc *sa1100_rtc;
	unsigned int rttr;
	int ret;

	sa1100_rtc = kzalloc(sizeof(struct sa1100_rtc), GFP_KERNEL);
	if (!sa1100_rtc)
		return -ENOMEM;

	spin_lock_init(&sa1100_rtc->lock);
	platform_set_drvdata(pdev, sa1100_rtc);

	ret = -ENXIO;
	sa1100_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!sa1100_rtc->ress) {
		dev_err(&pdev->dev, "No I/O memory resource defined\n");
		goto err_ress;
	}

	sa1100_rtc->irq_1Hz = platform_get_irq(pdev, 0);
	if (sa1100_rtc->irq_1Hz < 0) {
		dev_err(&pdev->dev, "No 1Hz IRQ resource defined\n");
		goto err_ress;
	}
	sa1100_rtc->irq_Alrm = platform_get_irq(pdev, 1);
	if (sa1100_rtc->irq_Alrm < 0) {
		dev_err(&pdev->dev, "No alarm IRQ resource defined\n");
		goto err_ress;
	}

	ret = -ENOMEM;
	sa1100_rtc->base = ioremap(sa1100_rtc->ress->start,
				resource_size(sa1100_rtc->ress));
	if (!sa1100_rtc->base) {
		dev_err(&pdev->dev, "Unable to map pxa RTC I/O memory\n");
		goto err_map;
	}

	sa1100_rtc->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(sa1100_rtc->clk)) {
		dev_err(&pdev->dev, "failed to find rtc clock source\n");
		ret = PTR_ERR(sa1100_rtc->clk);
		goto err_clk;
	}
	clk_prepare(sa1100_rtc->clk);
	clk_enable(sa1100_rtc->clk);

	/*
	 * According to the manual we should be able to let RTTR be zero
	 * and then a default diviser for a 32.768KHz clock is used.
	 * Apparently this doesn't work, at least for my SA1110 rev 5.
	 * If the clock divider is uninitialized then reset it to the
	 * default value to get the 1Hz clock.
	 */
	if (rtc_readl(sa1100_rtc, RTTR) == 0) {
		rttr = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
		rtc_writel(sa1100_rtc, RTTR, rttr);
		dev_warn(&pdev->dev, "warning: initializing default clock"
			 " divider/trim value\n");
		/* The current RTC value probably doesn't make sense either */
		rtc_writel(sa1100_rtc, RCNR, 0);
	}

	device_init_wakeup(&pdev->dev, 1);

	sa1100_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
						&sa1100_rtc_ops, THIS_MODULE);
	if (IS_ERR(sa1100_rtc->rtc)) {
		dev_err(&pdev->dev, "Failed to register RTC device -> %d\n",
			ret);
		goto err_rtc_reg;
	}
	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
	 * See also the comments in sa1100_rtc_interrupt().
	 *
	 * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
	 * interrupt pending, even though interrupts were never enabled.
	 * In this case, this bit it must be reset before enabling
	 * interruptions to avoid a nonexistent interrupt to occur.
	 *
	 * In principle, the same problem would apply to bit 0, although it has
	 * never been observed to happen.
	 *
	 * This issue is addressed both here and in sa1100_rtc_interrupt().
	 * If the issue is not addressed here, in the times when the processor
	 * wakes up with the bit set there will be one spurious interrupt.
	 *
	 * The issue is also dealt with in sa1100_rtc_interrupt() to be on the
	 * safe side, once the condition that lead to this strange
	 * initialization is unknown and could in principle happen during
	 * normal processing.
	 *
	 * Notice that clearing bit 1 and 0 is accomplished by writting ONES to
	 * the corresponding bits in RTSR. */
	rtc_writel(sa1100_rtc, RTSR, (RTSR_AL | RTSR_HZ));

	return 0;

err_rtc_reg:
err_clk:
	iounmap(sa1100_rtc->base);
err_ress:
err_map:
	kfree(sa1100_rtc);
	return ret;
}

static int sa1100_rtc_remove(struct platform_device *pdev)
{
	struct sa1100_rtc *sa1100_rtc = platform_get_drvdata(pdev);

	rtc_device_unregister(sa1100_rtc->rtc);
	clk_disable(sa1100_rtc->clk);
	clk_unprepare(sa1100_rtc->clk);
	iounmap(sa1100_rtc->base);
	return 0;
}

#ifdef CONFIG_PM
static int sa1100_rtc_suspend(struct device *dev)
{
	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		enable_irq_wake(sa1100_rtc->irq_Alrm);
	return 0;
}

static int sa1100_rtc_resume(struct device *dev)
{
	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		disable_irq_wake(sa1100_rtc->irq_Alrm);
	return 0;
}

static const struct dev_pm_ops sa1100_rtc_pm_ops = {
	.suspend	= sa1100_rtc_suspend,
	.resume		= sa1100_rtc_resume,
};
#endif

static struct platform_driver sa1100_rtc_driver = {
	.probe		= sa1100_rtc_probe,
	.remove		= sa1100_rtc_remove,
	.driver		= {
		.name	= "sa1100-rtc",
#ifdef CONFIG_PM
		.pm	= &sa1100_rtc_pm_ops,
#endif
	},
};

module_platform_driver(sa1100_rtc_driver);

MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sa1100-rtc");
Commit	Line	Data
e842f1c8 RP	1	/*
	2	* Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
	3	*
	4	* Copyright (c) 2000 Nils Faerber
	5	*
	6	* Based on rtc.c by Paul Gortmaker
	7	*
	8	* Original Driver by Nils Faerber <nils@kernelconcepts.de>
	9	*
	10	* Modifications from:
	11	* CIH <cih@coventive.com>
2f82af08	12	* Nicolas Pitre <nico@fluxnic.net>
e842f1c8 RP	13	* Andrew Christian <andrew.christian@hp.com>
	14	*
	15	* Converted to the RTC subsystem and Driver Model
	16	* by Richard Purdie <rpurdie@rpsys.net>
	17	*
	18	* This program is free software; you can redistribute it and/or
	19	* modify it under the terms of the GNU General Public License
	20	* as published by the Free Software Foundation; either version
	21	* 2 of the License, or (at your option) any later version.
	22	*/
	23
	24	#include <linux/platform_device.h>
	25	#include <linux/module.h>
	26	#include <linux/rtc.h>
	27	#include <linux/init.h>
	28	#include <linux/fs.h>
	29	#include <linux/interrupt.h>
e842f1c8	30	#include <linux/pm.h>
7cea0065 JZ	31	#include <linux/slab.h>
	32	#include <linux/clk.h>
	33	#include <linux/io.h>
e842f1c8	34
a09e64fb	35	#include <mach/hardware.h>
e842f1c8	36	#include <asm/irq.h>
e842f1c8	37
a404ad1f	38	#define RTC_DEF_DIVIDER (32768 - 1)
e842f1c8	39	#define RTC_DEF_TRIM 0
7cea0065 JZ	40	#define RTC_FREQ 1024
	41
	42	#define RCNR 0x00 /* RTC Count Register */
	43	#define RTAR 0x04 /* RTC Alarm Register */
	44	#define RTSR 0x08 /* RTC Status Register */
	45	#define RTTR 0x0c /* RTC Timer Trim Register */
	46
	47	#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
	48	#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
	49	#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
	50	#define RTSR_AL (1 << 0) /* RTC alarm detected */
	51
	52	#define rtc_readl(sa1100_rtc, reg) \
	53	readl_relaxed((sa1100_rtc)->base + (reg))
	54	#define rtc_writel(sa1100_rtc, reg, value) \
	55	writel_relaxed((value), (sa1100_rtc)->base + (reg))
	56
	57	struct sa1100_rtc {
	58	struct resource *ress;
	59	void __iomem *base;
	60	struct clk *clk;
	61	int irq_1Hz;
	62	int irq_Alrm;
	63	struct rtc_device *rtc;
	64	spinlock_t lock; /* Protects this structure */
	65	};
797276ec RK	66	/*
	67	* Calculate the next alarm time given the requested alarm time mask
	68	* and the current time.
	69	*/
a404ad1f MRJ	70	static void rtc_next_alarm_time(struct rtc_time next, struct rtc_time now,
a404ad1f MRJ	71	struct rtc_time *alrm)
797276ec RK	72	{
	73	unsigned long next_time;
	74	unsigned long now_time;
	75
	76	next->tm_year = now->tm_year;
	77	next->tm_mon = now->tm_mon;
	78	next->tm_mday = now->tm_mday;
	79	next->tm_hour = alrm->tm_hour;
	80	next->tm_min = alrm->tm_min;
	81	next->tm_sec = alrm->tm_sec;
	82
	83	rtc_tm_to_time(now, &now_time);
	84	rtc_tm_to_time(next, &next_time);
	85
	86	if (next_time < now_time) {
	87	/* Advance one day */
	88	next_time += 60 * 60 * 24;
	89	rtc_time_to_tm(next_time, next);
	90	}
	91	}
	92
7d12e780	93	static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
e842f1c8 RP	94	{
e842f1c8 RP	95	struct platform_device *pdev = to_platform_device(dev_id);
7cea0065	96	struct sa1100_rtc *sa1100_rtc = platform_get_drvdata(pdev);
e842f1c8 RP	97	unsigned int rtsr;
	98	unsigned long events = 0;
	99
7cea0065	100	spin_lock(&sa1100_rtc->lock);
e842f1c8	101
e842f1c8	102	/* clear interrupt sources */
7cea0065 JZ	103	rtsr = rtc_readl(sa1100_rtc, RTSR);
	104	rtc_writel(sa1100_rtc, RTSR, 0);
	105
7decaa55 MRJ	106	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
	107	* See also the comments in sa1100_rtc_probe(). */
	108	if (rtsr & (RTSR_ALE \| RTSR_HZE)) {
	109	/* This is the original code, before there was the if test
	110	* above. This code does not clear interrupts that were not
	111	* enabled. */
7cea0065	112	rtc_writel(sa1100_rtc, RTSR, (RTSR_AL \| RTSR_HZ) & (rtsr >> 2));
7decaa55 MRJ	113	} else {
	114	/* For some reason, it is possible to enter this routine
	115	* without interruptions enabled, it has been tested with
	116	* several units (Bug in SA11xx chip?).
	117	*
	118	* This situation leads to an infinite "loop" of interrupt
	119	* routine calling and as a result the processor seems to
	120	* lock on its first call to open(). */
7cea0065	121	rtc_writel(sa1100_rtc, RTSR, (RTSR_AL \| RTSR_HZ));
7decaa55	122	}
e842f1c8 RP	123
	124	/* clear alarm interrupt if it has occurred */
	125	if (rtsr & RTSR_AL)
	126	rtsr &= ~RTSR_ALE;
7cea0065	127	rtc_writel(sa1100_rtc, RTSR, rtsr & (RTSR_ALE \| RTSR_HZE));
e842f1c8 RP	128
	129	/* update irq data & counter */
	130	if (rtsr & RTSR_AL)
	131	events \|= RTC_AF \| RTC_IRQF;
	132	if (rtsr & RTSR_HZ)
	133	events \|= RTC_UF \| RTC_IRQF;
	134
7cea0065	135	rtc_update_irq(sa1100_rtc->rtc, 1, events);
e842f1c8	136
7cea0065	137	spin_unlock(&sa1100_rtc->lock);
e842f1c8 RP	138
	139	return IRQ_HANDLED;
	140	}
	141
e842f1c8 RP	142	static int sa1100_rtc_open(struct device *dev)
e842f1c8 RP	143	{
7cea0065	144	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
e842f1c8 RP	145	int ret;
e842f1c8 RP	146
7cea0065 JZ	147	ret = request_irq(sa1100_rtc->irq_1Hz, sa1100_rtc_interrupt,
7cea0065 JZ	148	IRQF_DISABLED, "rtc 1Hz", dev);
e842f1c8	149	if (ret) {
7cea0065	150	dev_err(dev, "IRQ %d already in use.\n", sa1100_rtc->irq_1Hz);
e842f1c8 RP	151	goto fail_ui;
e842f1c8 RP	152	}
7cea0065 JZ	153	ret = request_irq(sa1100_rtc->irq_Alrm, sa1100_rtc_interrupt,
7cea0065 JZ	154	IRQF_DISABLED, "rtc Alrm", dev);
e842f1c8	155	if (ret) {
7cea0065	156	dev_err(dev, "IRQ %d already in use.\n", sa1100_rtc->irq_Alrm);
e842f1c8 RP	157	goto fail_ai;
e842f1c8 RP	158	}
7cea0065 JZ	159	sa1100_rtc->rtc->max_user_freq = RTC_FREQ;
7cea0065 JZ	160	rtc_irq_set_freq(sa1100_rtc->rtc, NULL, RTC_FREQ);
d2ccb52d	161
e842f1c8 RP	162	return 0;
e842f1c8 RP	163
e842f1c8	164	fail_ai:
7cea0065	165	free_irq(sa1100_rtc->irq_1Hz, dev);
e842f1c8 RP	166	fail_ui:
	167	return ret;
	168	}
	169
	170	static void sa1100_rtc_release(struct device *dev)
	171	{
7cea0065	172	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
e842f1c8	173
7cea0065 JZ	174	spin_lock_irq(&sa1100_rtc->lock);
	175	rtc_writel(sa1100_rtc, RTSR, 0);
	176	spin_unlock_irq(&sa1100_rtc->lock);
	177
	178	free_irq(sa1100_rtc->irq_Alrm, dev);
	179	free_irq(sa1100_rtc->irq_1Hz, dev);
e842f1c8 RP	180	}
e842f1c8 RP	181
16380c15 JS	182	static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
16380c15 JS	183	{
7cea0065 JZ	184	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
	185	unsigned int rtsr;
	186
	187	spin_lock_irq(&sa1100_rtc->lock);
	188
	189	rtsr = rtc_readl(sa1100_rtc, RTSR);
16380c15	190	if (enabled)
7cea0065	191	rtsr \|= RTSR_ALE;
16380c15	192	else
7cea0065 JZ	193	rtsr &= ~RTSR_ALE;
	194	rtc_writel(sa1100_rtc, RTSR, rtsr);
	195
	196	spin_unlock_irq(&sa1100_rtc->lock);
16380c15 JS	197	return 0;
	198	}
	199
e842f1c8 RP	200	static int sa1100_rtc_read_time(struct device dev, struct rtc_time tm)
e842f1c8 RP	201	{
7cea0065 JZ	202	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
	203
	204	rtc_time_to_tm(rtc_readl(sa1100_rtc, RCNR), tm);
e842f1c8 RP	205	return 0;
	206	}
	207
	208	static int sa1100_rtc_set_time(struct device dev, struct rtc_time tm)
	209	{
7cea0065	210	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
e842f1c8 RP	211	unsigned long time;
	212	int ret;
	213
	214	ret = rtc_tm_to_time(tm, &time);
	215	if (ret == 0)
7cea0065	216	rtc_writel(sa1100_rtc, RCNR, time);
e842f1c8 RP	217	return ret;
	218	}
	219
	220	static int sa1100_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	221	{
7cea0065 JZ	222	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
	223	unsigned long time;
	224	unsigned int rtsr;
32b49da4	225
7cea0065 JZ	226	time = rtc_readl(sa1100_rtc, RCNR);
	227	rtc_time_to_tm(time, &alrm->time);
	228	rtsr = rtc_readl(sa1100_rtc, RTSR);
32b49da4 DB	229	alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
32b49da4 DB	230	alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
e842f1c8 RP	231	return 0;
	232	}
	233
	234	static int sa1100_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	235	{
7cea0065	236	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
42874759	237	struct rtc_time now_tm, alarm_tm;
7cea0065 JZ	238	unsigned long time, alarm;
	239	unsigned int rtsr;
	240
	241	spin_lock_irq(&sa1100_rtc->lock);
e842f1c8	242
7cea0065 JZ	243	time = rtc_readl(sa1100_rtc, RCNR);
	244	rtc_time_to_tm(time, &now_tm);
	245	rtc_next_alarm_time(&alarm_tm, &now_tm, &alrm->time);
	246	rtc_tm_to_time(&alarm_tm, &alarm);
	247	rtc_writel(sa1100_rtc, RTAR, alarm);
42874759	248
7cea0065	249	rtsr = rtc_readl(sa1100_rtc, RTSR);
42874759	250	if (alrm->enabled)
7cea0065	251	rtsr \|= RTSR_ALE;
42874759	252	else
7cea0065 JZ	253	rtsr &= ~RTSR_ALE;
7cea0065 JZ	254	rtc_writel(sa1100_rtc, RTSR, rtsr);
42874759	255
7cea0065	256	spin_unlock_irq(&sa1100_rtc->lock);
e842f1c8	257
7cea0065	258	return 0;
e842f1c8 RP	259	}
	260
	261	static int sa1100_rtc_proc(struct device dev, struct seq_file seq)
	262	{
7cea0065	263	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
e842f1c8	264
7cea0065 JZ	265	seq_printf(seq, "trim/divider\t\t: 0x%08x\n",
	266	rtc_readl(sa1100_rtc, RTTR));
	267	seq_printf(seq, "RTSR\t\t\t: 0x%08x\n",
	268	rtc_readl(sa1100_rtc, RTSR));
e842f1c8 RP	269	return 0;
	270	}
	271
ff8371ac	272	static const struct rtc_class_ops sa1100_rtc_ops = {
e842f1c8	273	.open = sa1100_rtc_open,
e842f1c8	274	.release = sa1100_rtc_release,
e842f1c8 RP	275	.read_time = sa1100_rtc_read_time,
	276	.set_time = sa1100_rtc_set_time,
	277	.read_alarm = sa1100_rtc_read_alarm,
	278	.set_alarm = sa1100_rtc_set_alarm,
	279	.proc = sa1100_rtc_proc,
16380c15	280	.alarm_irq_enable = sa1100_rtc_alarm_irq_enable,
e842f1c8 RP	281	};
	282
	283	static int sa1100_rtc_probe(struct platform_device *pdev)
	284	{
7cea0065 JZ	285	struct sa1100_rtc *sa1100_rtc;
	286	unsigned int rttr;
	287	int ret;
	288
	289	sa1100_rtc = kzalloc(sizeof(struct sa1100_rtc), GFP_KERNEL);
	290	if (!sa1100_rtc)
	291	return -ENOMEM;
	292
	293	spin_lock_init(&sa1100_rtc->lock);
	294	platform_set_drvdata(pdev, sa1100_rtc);
	295
	296	ret = -ENXIO;
	297	sa1100_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	298	if (!sa1100_rtc->ress) {
	299	dev_err(&pdev->dev, "No I/O memory resource defined\n");
	300	goto err_ress;
	301	}
	302
	303	sa1100_rtc->irq_1Hz = platform_get_irq(pdev, 0);
	304	if (sa1100_rtc->irq_1Hz < 0) {
	305	dev_err(&pdev->dev, "No 1Hz IRQ resource defined\n");
	306	goto err_ress;
	307	}
	308	sa1100_rtc->irq_Alrm = platform_get_irq(pdev, 1);
	309	if (sa1100_rtc->irq_Alrm < 0) {
	310	dev_err(&pdev->dev, "No alarm IRQ resource defined\n");
	311	goto err_ress;
	312	}
	313
	314	ret = -ENOMEM;
	315	sa1100_rtc->base = ioremap(sa1100_rtc->ress->start,
	316	resource_size(sa1100_rtc->ress));
	317	if (!sa1100_rtc->base) {
	318	dev_err(&pdev->dev, "Unable to map pxa RTC I/O memory\n");
	319	goto err_map;
	320	}
	321
	322	sa1100_rtc->clk = clk_get(&pdev->dev, NULL);
	323	if (IS_ERR(sa1100_rtc->clk)) {
	324	dev_err(&pdev->dev, "failed to find rtc clock source\n");
	325	ret = PTR_ERR(sa1100_rtc->clk);
	326	goto err_clk;
	327	}
	328	clk_prepare(sa1100_rtc->clk);
	329	clk_enable(sa1100_rtc->clk);
e842f1c8 RP	330
	331	/*
	332	* According to the manual we should be able to let RTTR be zero
	333	* and then a default diviser for a 32.768KHz clock is used.
	334	* Apparently this doesn't work, at least for my SA1110 rev 5.
	335	* If the clock divider is uninitialized then reset it to the
	336	* default value to get the 1Hz clock.
	337	*/
7cea0065 JZ	338	if (rtc_readl(sa1100_rtc, RTTR) == 0) {
	339	rttr = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
	340	rtc_writel(sa1100_rtc, RTTR, rttr);
	341	dev_warn(&pdev->dev, "warning: initializing default clock"
	342	" divider/trim value\n");
e842f1c8	343	/* The current RTC value probably doesn't make sense either */
7cea0065	344	rtc_writel(sa1100_rtc, RCNR, 0);
e842f1c8 RP	345	}
e842f1c8 RP	346
e5a2c9cc UL	347	device_init_wakeup(&pdev->dev, 1);
e5a2c9cc UL	348
7cea0065 JZ	349	sa1100_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
	350	&sa1100_rtc_ops, THIS_MODULE);
	351	if (IS_ERR(sa1100_rtc->rtc)) {
	352	dev_err(&pdev->dev, "Failed to register RTC device -> %d\n",
	353	ret);
	354	goto err_rtc_reg;
	355	}
7decaa55 MRJ	356	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
	357	* See also the comments in sa1100_rtc_interrupt().
	358	*
	359	* Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
	360	* interrupt pending, even though interrupts were never enabled.
	361	* In this case, this bit it must be reset before enabling
	362	* interruptions to avoid a nonexistent interrupt to occur.
	363	*
	364	* In principle, the same problem would apply to bit 0, although it has
	365	* never been observed to happen.
	366	*
	367	* This issue is addressed both here and in sa1100_rtc_interrupt().
	368	* If the issue is not addressed here, in the times when the processor
	369	* wakes up with the bit set there will be one spurious interrupt.
	370	*
	371	* The issue is also dealt with in sa1100_rtc_interrupt() to be on the
	372	* safe side, once the condition that lead to this strange
	373	* initialization is unknown and could in principle happen during
	374	* normal processing.
	375	*
	376	* Notice that clearing bit 1 and 0 is accomplished by writting ONES to
	377	* the corresponding bits in RTSR. */
7cea0065	378	rtc_writel(sa1100_rtc, RTSR, (RTSR_AL \| RTSR_HZ));
7decaa55	379
e842f1c8	380	return 0;
7cea0065 JZ	381
	382	err_rtc_reg:
	383	err_clk:
	384	iounmap(sa1100_rtc->base);
	385	err_ress:
	386	err_map:
	387	kfree(sa1100_rtc);
	388	return ret;
e842f1c8 RP	389	}
	390
	391	static int sa1100_rtc_remove(struct platform_device *pdev)
	392	{
7cea0065	393	struct sa1100_rtc *sa1100_rtc = platform_get_drvdata(pdev);
e842f1c8	394
7cea0065 JZ	395	rtc_device_unregister(sa1100_rtc->rtc);
	396	clk_disable(sa1100_rtc->clk);
	397	clk_unprepare(sa1100_rtc->clk);
	398	iounmap(sa1100_rtc->base);
e842f1c8 RP	399	return 0;
	400	}
	401
6bc54e69	402	#ifdef CONFIG_PM
5d027cd2	403	static int sa1100_rtc_suspend(struct device *dev)
6bc54e69	404	{
7cea0065 JZ	405	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
7cea0065 JZ	406
5d027cd2	407	if (device_may_wakeup(dev))
7cea0065	408	enable_irq_wake(sa1100_rtc->irq_Alrm);
6bc54e69 RK	409	return 0;
	410	}
	411
5d027cd2	412	static int sa1100_rtc_resume(struct device *dev)
6bc54e69	413	{
7cea0065 JZ	414	struct sa1100_rtc *sa1100_rtc = dev_get_drvdata(dev);
7cea0065 JZ	415
5d027cd2	416	if (device_may_wakeup(dev))
7cea0065	417	disable_irq_wake(sa1100_rtc->irq_Alrm);
6bc54e69 RK	418	return 0;
6bc54e69 RK	419	}
5d027cd2	420
47145210	421	static const struct dev_pm_ops sa1100_rtc_pm_ops = {
5d027cd2 HZ	422	.suspend = sa1100_rtc_suspend,
	423	.resume = sa1100_rtc_resume,
	424	};
6bc54e69 RK	425	#endif
6bc54e69 RK	426
e842f1c8 RP	427	static struct platform_driver sa1100_rtc_driver = {
	428	.probe = sa1100_rtc_probe,
	429	.remove = sa1100_rtc_remove,
	430	.driver = {
5d027cd2 HZ	431	.name = "sa1100-rtc",
	432	#ifdef CONFIG_PM
	433	.pm = &sa1100_rtc_pm_ops,
	434	#endif
e842f1c8 RP	435	},
	436	};
	437
0c4eae66	438	module_platform_driver(sa1100_rtc_driver);
e842f1c8 RP	439
	440	MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
	441	MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
	442	MODULE_LICENSE("GPL");
ad28a07b	443	MODULE_ALIAS("platform:sa1100-rtc");