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Commit | Line | Data |
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317a6104 PM |
1 | /* |
2 | * SuperH On-Chip RTC Support | |
3 | * | |
063adc75 | 4 | * Copyright (C) 2006 - 2009 Paul Mundt |
1b73e6ae | 5 | * Copyright (C) 2006 Jamie Lenehan |
b420b1a7 | 6 | * Copyright (C) 2008 Angelo Castello |
317a6104 PM |
7 | * |
8 | * Based on the old arch/sh/kernel/cpu/rtc.c by: | |
9 | * | |
10 | * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> | |
11 | * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka | |
12 | * | |
13 | * This file is subject to the terms and conditions of the GNU General Public | |
14 | * License. See the file "COPYING" in the main directory of this archive | |
15 | * for more details. | |
16 | */ | |
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/bcd.h> | |
20 | #include <linux/rtc.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/seq_file.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/spinlock.h> | |
31ccb081 | 26 | #include <linux/io.h> |
5d2a5037 | 27 | #include <linux/log2.h> |
063adc75 | 28 | #include <linux/clk.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
ad89f87a | 30 | #include <asm/rtc.h> |
317a6104 | 31 | |
1b73e6ae | 32 | #define DRV_NAME "sh-rtc" |
5c9740a8 | 33 | #define DRV_VERSION "0.2.3" |
317a6104 PM |
34 | |
35 | #define RTC_REG(r) ((r) * rtc_reg_size) | |
36 | ||
31ccb081 | 37 | #define R64CNT RTC_REG(0) |
1b73e6ae JL |
38 | |
39 | #define RSECCNT RTC_REG(1) /* RTC sec */ | |
40 | #define RMINCNT RTC_REG(2) /* RTC min */ | |
41 | #define RHRCNT RTC_REG(3) /* RTC hour */ | |
42 | #define RWKCNT RTC_REG(4) /* RTC week */ | |
43 | #define RDAYCNT RTC_REG(5) /* RTC day */ | |
44 | #define RMONCNT RTC_REG(6) /* RTC month */ | |
45 | #define RYRCNT RTC_REG(7) /* RTC year */ | |
46 | #define RSECAR RTC_REG(8) /* ALARM sec */ | |
47 | #define RMINAR RTC_REG(9) /* ALARM min */ | |
48 | #define RHRAR RTC_REG(10) /* ALARM hour */ | |
49 | #define RWKAR RTC_REG(11) /* ALARM week */ | |
50 | #define RDAYAR RTC_REG(12) /* ALARM day */ | |
51 | #define RMONAR RTC_REG(13) /* ALARM month */ | |
52 | #define RCR1 RTC_REG(14) /* Control */ | |
53 | #define RCR2 RTC_REG(15) /* Control */ | |
54 | ||
ff1b7506 PM |
55 | /* |
56 | * Note on RYRAR and RCR3: Up until this point most of the register | |
57 | * definitions are consistent across all of the available parts. However, | |
58 | * the placement of the optional RYRAR and RCR3 (the RYRAR control | |
59 | * register used to control RYRCNT/RYRAR compare) varies considerably | |
60 | * across various parts, occasionally being mapped in to a completely | |
61 | * unrelated address space. For proper RYRAR support a separate resource | |
62 | * would have to be handed off, but as this is purely optional in | |
63 | * practice, we simply opt not to support it, thereby keeping the code | |
64 | * quite a bit more simplified. | |
65 | */ | |
66 | ||
1b73e6ae JL |
67 | /* ALARM Bits - or with BCD encoded value */ |
68 | #define AR_ENB 0x80 /* Enable for alarm cmp */ | |
317a6104 | 69 | |
b420b1a7 AC |
70 | /* Period Bits */ |
71 | #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */ | |
72 | #define PF_COUNT 0x200 /* Half periodic counter */ | |
73 | #define PF_OXS 0x400 /* Periodic One x Second */ | |
74 | #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */ | |
75 | #define PF_MASK 0xf00 | |
76 | ||
317a6104 PM |
77 | /* RCR1 Bits */ |
78 | #define RCR1_CF 0x80 /* Carry Flag */ | |
79 | #define RCR1_CIE 0x10 /* Carry Interrupt Enable */ | |
80 | #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */ | |
81 | #define RCR1_AF 0x01 /* Alarm Flag */ | |
82 | ||
83 | /* RCR2 Bits */ | |
84 | #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */ | |
85 | #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */ | |
86 | #define RCR2_RTCEN 0x08 /* ENable RTC */ | |
87 | #define RCR2_ADJ 0x04 /* ADJustment (30-second) */ | |
88 | #define RCR2_RESET 0x02 /* Reset bit */ | |
89 | #define RCR2_START 0x01 /* Start bit */ | |
90 | ||
91 | struct sh_rtc { | |
063adc75 PM |
92 | void __iomem *regbase; |
93 | unsigned long regsize; | |
94 | struct resource *res; | |
95 | int alarm_irq; | |
96 | int periodic_irq; | |
97 | int carry_irq; | |
98 | struct clk *clk; | |
99 | struct rtc_device *rtc_dev; | |
100 | spinlock_t lock; | |
101 | unsigned long capabilities; /* See asm/rtc.h for cap bits */ | |
102 | unsigned short periodic_freq; | |
317a6104 PM |
103 | }; |
104 | ||
5e084a15 | 105 | static int __sh_rtc_interrupt(struct sh_rtc *rtc) |
317a6104 | 106 | { |
5e084a15 | 107 | unsigned int tmp, pending; |
317a6104 PM |
108 | |
109 | tmp = readb(rtc->regbase + RCR1); | |
5e084a15 | 110 | pending = tmp & RCR1_CF; |
1b73e6ae | 111 | tmp &= ~RCR1_CF; |
317a6104 PM |
112 | writeb(tmp, rtc->regbase + RCR1); |
113 | ||
b420b1a7 | 114 | /* Users have requested One x Second IRQ */ |
5e084a15 | 115 | if (pending && rtc->periodic_freq & PF_OXS) |
b420b1a7 | 116 | rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF); |
317a6104 | 117 | |
5e084a15 | 118 | return pending; |
317a6104 PM |
119 | } |
120 | ||
5e084a15 | 121 | static int __sh_rtc_alarm(struct sh_rtc *rtc) |
1b73e6ae | 122 | { |
5e084a15 | 123 | unsigned int tmp, pending; |
1b73e6ae JL |
124 | |
125 | tmp = readb(rtc->regbase + RCR1); | |
5e084a15 | 126 | pending = tmp & RCR1_AF; |
b420b1a7 | 127 | tmp &= ~(RCR1_AF | RCR1_AIE); |
5e084a15 | 128 | writeb(tmp, rtc->regbase + RCR1); |
1b73e6ae | 129 | |
5e084a15 MD |
130 | if (pending) |
131 | rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); | |
b420b1a7 | 132 | |
5e084a15 | 133 | return pending; |
1b73e6ae JL |
134 | } |
135 | ||
5e084a15 | 136 | static int __sh_rtc_periodic(struct sh_rtc *rtc) |
317a6104 | 137 | { |
b420b1a7 | 138 | struct rtc_device *rtc_dev = rtc->rtc_dev; |
5e084a15 MD |
139 | struct rtc_task *irq_task; |
140 | unsigned int tmp, pending; | |
317a6104 | 141 | |
b420b1a7 | 142 | tmp = readb(rtc->regbase + RCR2); |
5e084a15 | 143 | pending = tmp & RCR2_PEF; |
b420b1a7 AC |
144 | tmp &= ~RCR2_PEF; |
145 | writeb(tmp, rtc->regbase + RCR2); | |
146 | ||
5e084a15 MD |
147 | if (!pending) |
148 | return 0; | |
149 | ||
b420b1a7 AC |
150 | /* Half period enabled than one skipped and the next notified */ |
151 | if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT)) | |
152 | rtc->periodic_freq &= ~PF_COUNT; | |
153 | else { | |
154 | if (rtc->periodic_freq & PF_HP) | |
155 | rtc->periodic_freq |= PF_COUNT; | |
156 | if (rtc->periodic_freq & PF_KOU) { | |
157 | spin_lock(&rtc_dev->irq_task_lock); | |
5e084a15 MD |
158 | irq_task = rtc_dev->irq_task; |
159 | if (irq_task) | |
160 | irq_task->func(irq_task->private_data); | |
b420b1a7 AC |
161 | spin_unlock(&rtc_dev->irq_task_lock); |
162 | } else | |
163 | rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF); | |
164 | } | |
317a6104 | 165 | |
5e084a15 MD |
166 | return pending; |
167 | } | |
168 | ||
169 | static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id) | |
170 | { | |
171 | struct sh_rtc *rtc = dev_id; | |
172 | int ret; | |
173 | ||
174 | spin_lock(&rtc->lock); | |
175 | ret = __sh_rtc_interrupt(rtc); | |
176 | spin_unlock(&rtc->lock); | |
177 | ||
178 | return IRQ_RETVAL(ret); | |
179 | } | |
180 | ||
181 | static irqreturn_t sh_rtc_alarm(int irq, void *dev_id) | |
182 | { | |
183 | struct sh_rtc *rtc = dev_id; | |
184 | int ret; | |
185 | ||
186 | spin_lock(&rtc->lock); | |
187 | ret = __sh_rtc_alarm(rtc); | |
188 | spin_unlock(&rtc->lock); | |
189 | ||
190 | return IRQ_RETVAL(ret); | |
191 | } | |
192 | ||
193 | static irqreturn_t sh_rtc_periodic(int irq, void *dev_id) | |
194 | { | |
195 | struct sh_rtc *rtc = dev_id; | |
196 | int ret; | |
197 | ||
198 | spin_lock(&rtc->lock); | |
199 | ret = __sh_rtc_periodic(rtc); | |
317a6104 PM |
200 | spin_unlock(&rtc->lock); |
201 | ||
5e084a15 MD |
202 | return IRQ_RETVAL(ret); |
203 | } | |
204 | ||
205 | static irqreturn_t sh_rtc_shared(int irq, void *dev_id) | |
206 | { | |
207 | struct sh_rtc *rtc = dev_id; | |
208 | int ret; | |
209 | ||
210 | spin_lock(&rtc->lock); | |
211 | ret = __sh_rtc_interrupt(rtc); | |
212 | ret |= __sh_rtc_alarm(rtc); | |
213 | ret |= __sh_rtc_periodic(rtc); | |
214 | spin_unlock(&rtc->lock); | |
215 | ||
216 | return IRQ_RETVAL(ret); | |
317a6104 PM |
217 | } |
218 | ||
5c9740a8 | 219 | static int sh_rtc_irq_set_state(struct device *dev, int enable) |
317a6104 PM |
220 | { |
221 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
222 | unsigned int tmp; | |
223 | ||
224 | spin_lock_irq(&rtc->lock); | |
225 | ||
226 | tmp = readb(rtc->regbase + RCR2); | |
227 | ||
228 | if (enable) { | |
5c9740a8 | 229 | rtc->periodic_freq |= PF_KOU; |
b420b1a7 AC |
230 | tmp &= ~RCR2_PEF; /* Clear PES bit */ |
231 | tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */ | |
5c9740a8 AZ |
232 | } else { |
233 | rtc->periodic_freq &= ~PF_KOU; | |
317a6104 | 234 | tmp &= ~(RCR2_PESMASK | RCR2_PEF); |
5c9740a8 | 235 | } |
317a6104 PM |
236 | |
237 | writeb(tmp, rtc->regbase + RCR2); | |
238 | ||
239 | spin_unlock_irq(&rtc->lock); | |
5c9740a8 AZ |
240 | |
241 | return 0; | |
317a6104 PM |
242 | } |
243 | ||
5c9740a8 | 244 | static int sh_rtc_irq_set_freq(struct device *dev, int freq) |
317a6104 PM |
245 | { |
246 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
b420b1a7 | 247 | int tmp, ret = 0; |
317a6104 PM |
248 | |
249 | spin_lock_irq(&rtc->lock); | |
b420b1a7 | 250 | tmp = rtc->periodic_freq & PF_MASK; |
317a6104 | 251 | |
b420b1a7 AC |
252 | switch (freq) { |
253 | case 0: | |
254 | rtc->periodic_freq = 0x00; | |
255 | break; | |
256 | case 1: | |
257 | rtc->periodic_freq = 0x60; | |
258 | break; | |
259 | case 2: | |
260 | rtc->periodic_freq = 0x50; | |
261 | break; | |
262 | case 4: | |
263 | rtc->periodic_freq = 0x40; | |
264 | break; | |
265 | case 8: | |
266 | rtc->periodic_freq = 0x30 | PF_HP; | |
267 | break; | |
268 | case 16: | |
269 | rtc->periodic_freq = 0x30; | |
270 | break; | |
271 | case 32: | |
272 | rtc->periodic_freq = 0x20 | PF_HP; | |
273 | break; | |
274 | case 64: | |
275 | rtc->periodic_freq = 0x20; | |
276 | break; | |
277 | case 128: | |
278 | rtc->periodic_freq = 0x10 | PF_HP; | |
279 | break; | |
280 | case 256: | |
281 | rtc->periodic_freq = 0x10; | |
282 | break; | |
283 | default: | |
284 | ret = -ENOTSUPP; | |
285 | } | |
317a6104 | 286 | |
1043bf5c | 287 | if (ret == 0) |
b420b1a7 | 288 | rtc->periodic_freq |= tmp; |
317a6104 PM |
289 | |
290 | spin_unlock_irq(&rtc->lock); | |
b420b1a7 | 291 | return ret; |
317a6104 PM |
292 | } |
293 | ||
b420b1a7 | 294 | static inline void sh_rtc_setaie(struct device *dev, unsigned int enable) |
317a6104 PM |
295 | { |
296 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
297 | unsigned int tmp; | |
317a6104 | 298 | |
b420b1a7 | 299 | spin_lock_irq(&rtc->lock); |
317a6104 | 300 | |
b420b1a7 | 301 | tmp = readb(rtc->regbase + RCR1); |
317a6104 | 302 | |
063adc75 | 303 | if (enable) |
b420b1a7 | 304 | tmp |= RCR1_AIE; |
063adc75 PM |
305 | else |
306 | tmp &= ~RCR1_AIE; | |
317a6104 | 307 | |
b420b1a7 | 308 | writeb(tmp, rtc->regbase + RCR1); |
317a6104 | 309 | |
b420b1a7 | 310 | spin_unlock_irq(&rtc->lock); |
317a6104 PM |
311 | } |
312 | ||
317a6104 PM |
313 | static int sh_rtc_proc(struct device *dev, struct seq_file *seq) |
314 | { | |
315 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
316 | unsigned int tmp; | |
317 | ||
318 | tmp = readb(rtc->regbase + RCR1); | |
b420b1a7 | 319 | seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no"); |
317a6104 PM |
320 | |
321 | tmp = readb(rtc->regbase + RCR2); | |
322 | seq_printf(seq, "periodic_IRQ\t: %s\n", | |
b420b1a7 | 323 | (tmp & RCR2_PESMASK) ? "yes" : "no"); |
317a6104 PM |
324 | |
325 | return 0; | |
326 | } | |
327 | ||
9cd88b90 MD |
328 | static inline void sh_rtc_setcie(struct device *dev, unsigned int enable) |
329 | { | |
330 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
331 | unsigned int tmp; | |
332 | ||
333 | spin_lock_irq(&rtc->lock); | |
334 | ||
335 | tmp = readb(rtc->regbase + RCR1); | |
336 | ||
337 | if (!enable) | |
338 | tmp &= ~RCR1_CIE; | |
339 | else | |
340 | tmp |= RCR1_CIE; | |
341 | ||
342 | writeb(tmp, rtc->regbase + RCR1); | |
343 | ||
344 | spin_unlock_irq(&rtc->lock); | |
345 | } | |
346 | ||
16380c15 JS |
347 | static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
348 | { | |
349 | sh_rtc_setaie(dev, enabled); | |
350 | return 0; | |
351 | } | |
352 | ||
317a6104 PM |
353 | static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm) |
354 | { | |
355 | struct platform_device *pdev = to_platform_device(dev); | |
356 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
357 | unsigned int sec128, sec2, yr, yr100, cf_bit; | |
358 | ||
359 | do { | |
360 | unsigned int tmp; | |
361 | ||
362 | spin_lock_irq(&rtc->lock); | |
363 | ||
364 | tmp = readb(rtc->regbase + RCR1); | |
365 | tmp &= ~RCR1_CF; /* Clear CF-bit */ | |
366 | tmp |= RCR1_CIE; | |
367 | writeb(tmp, rtc->regbase + RCR1); | |
368 | ||
369 | sec128 = readb(rtc->regbase + R64CNT); | |
370 | ||
fe20ba70 AB |
371 | tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT)); |
372 | tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT)); | |
373 | tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT)); | |
374 | tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT)); | |
375 | tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT)); | |
376 | tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1; | |
317a6104 | 377 | |
ad89f87a PM |
378 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
379 | yr = readw(rtc->regbase + RYRCNT); | |
fe20ba70 | 380 | yr100 = bcd2bin(yr >> 8); |
ad89f87a PM |
381 | yr &= 0xff; |
382 | } else { | |
383 | yr = readb(rtc->regbase + RYRCNT); | |
fe20ba70 | 384 | yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20); |
ad89f87a | 385 | } |
317a6104 | 386 | |
fe20ba70 | 387 | tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900; |
317a6104 PM |
388 | |
389 | sec2 = readb(rtc->regbase + R64CNT); | |
390 | cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF; | |
391 | ||
392 | spin_unlock_irq(&rtc->lock); | |
393 | } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0); | |
394 | ||
395 | #if RTC_BIT_INVERTED != 0 | |
396 | if ((sec128 & RTC_BIT_INVERTED)) | |
397 | tm->tm_sec--; | |
398 | #endif | |
399 | ||
9cd88b90 MD |
400 | /* only keep the carry interrupt enabled if UIE is on */ |
401 | if (!(rtc->periodic_freq & PF_OXS)) | |
402 | sh_rtc_setcie(dev, 0); | |
403 | ||
435c55d1 | 404 | dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " |
317a6104 | 405 | "mday=%d, mon=%d, year=%d, wday=%d\n", |
2a4e2b87 | 406 | __func__, |
317a6104 | 407 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
a1614796 | 408 | tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday); |
317a6104 | 409 | |
edf22477 | 410 | return rtc_valid_tm(tm); |
317a6104 PM |
411 | } |
412 | ||
413 | static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
414 | { | |
415 | struct platform_device *pdev = to_platform_device(dev); | |
416 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
417 | unsigned int tmp; | |
418 | int year; | |
419 | ||
420 | spin_lock_irq(&rtc->lock); | |
421 | ||
422 | /* Reset pre-scaler & stop RTC */ | |
423 | tmp = readb(rtc->regbase + RCR2); | |
424 | tmp |= RCR2_RESET; | |
699bc661 | 425 | tmp &= ~RCR2_START; |
317a6104 PM |
426 | writeb(tmp, rtc->regbase + RCR2); |
427 | ||
fe20ba70 AB |
428 | writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT); |
429 | writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT); | |
430 | writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT); | |
431 | writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT); | |
432 | writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT); | |
433 | writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT); | |
317a6104 | 434 | |
ad89f87a | 435 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
fe20ba70 AB |
436 | year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) | |
437 | bin2bcd(tm->tm_year % 100); | |
ad89f87a PM |
438 | writew(year, rtc->regbase + RYRCNT); |
439 | } else { | |
440 | year = tm->tm_year % 100; | |
fe20ba70 | 441 | writeb(bin2bcd(year), rtc->regbase + RYRCNT); |
ad89f87a | 442 | } |
317a6104 PM |
443 | |
444 | /* Start RTC */ | |
445 | tmp = readb(rtc->regbase + RCR2); | |
446 | tmp &= ~RCR2_RESET; | |
447 | tmp |= RCR2_RTCEN | RCR2_START; | |
448 | writeb(tmp, rtc->regbase + RCR2); | |
449 | ||
450 | spin_unlock_irq(&rtc->lock); | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
1b73e6ae JL |
455 | static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off) |
456 | { | |
457 | unsigned int byte; | |
458 | int value = 0xff; /* return 0xff for ignored values */ | |
459 | ||
460 | byte = readb(rtc->regbase + reg_off); | |
461 | if (byte & AR_ENB) { | |
462 | byte &= ~AR_ENB; /* strip the enable bit */ | |
fe20ba70 | 463 | value = bcd2bin(byte); |
1b73e6ae JL |
464 | } |
465 | ||
466 | return value; | |
467 | } | |
468 | ||
469 | static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
470 | { | |
471 | struct platform_device *pdev = to_platform_device(dev); | |
472 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
b420b1a7 | 473 | struct rtc_time *tm = &wkalrm->time; |
1b73e6ae JL |
474 | |
475 | spin_lock_irq(&rtc->lock); | |
476 | ||
477 | tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR); | |
478 | tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR); | |
479 | tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR); | |
480 | tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR); | |
481 | tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR); | |
482 | tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR); | |
483 | if (tm->tm_mon > 0) | |
484 | tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */ | |
485 | tm->tm_year = 0xffff; | |
486 | ||
0d103e90 DB |
487 | wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0; |
488 | ||
1b73e6ae JL |
489 | spin_unlock_irq(&rtc->lock); |
490 | ||
491 | return 0; | |
492 | } | |
493 | ||
494 | static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc, | |
495 | int value, int reg_off) | |
496 | { | |
497 | /* < 0 for a value that is ignored */ | |
498 | if (value < 0) | |
499 | writeb(0, rtc->regbase + reg_off); | |
500 | else | |
fe20ba70 | 501 | writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off); |
1b73e6ae JL |
502 | } |
503 | ||
b420b1a7 | 504 | static int sh_rtc_check_alarm(struct rtc_time *tm) |
1b73e6ae JL |
505 | { |
506 | /* | |
507 | * The original rtc says anything > 0xc0 is "don't care" or "match | |
508 | * all" - most users use 0xff but rtc-dev uses -1 for the same thing. | |
509 | * The original rtc doesn't support years - some things use -1 and | |
510 | * some 0xffff. We use -1 to make out tests easier. | |
511 | */ | |
512 | if (tm->tm_year == 0xffff) | |
513 | tm->tm_year = -1; | |
514 | if (tm->tm_mon >= 0xff) | |
515 | tm->tm_mon = -1; | |
516 | if (tm->tm_mday >= 0xff) | |
517 | tm->tm_mday = -1; | |
518 | if (tm->tm_wday >= 0xff) | |
519 | tm->tm_wday = -1; | |
520 | if (tm->tm_hour >= 0xff) | |
521 | tm->tm_hour = -1; | |
522 | if (tm->tm_min >= 0xff) | |
523 | tm->tm_min = -1; | |
524 | if (tm->tm_sec >= 0xff) | |
525 | tm->tm_sec = -1; | |
526 | ||
527 | if (tm->tm_year > 9999 || | |
528 | tm->tm_mon >= 12 || | |
529 | tm->tm_mday == 0 || tm->tm_mday >= 32 || | |
530 | tm->tm_wday >= 7 || | |
531 | tm->tm_hour >= 24 || | |
532 | tm->tm_min >= 60 || | |
533 | tm->tm_sec >= 60) | |
534 | return -EINVAL; | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
539 | static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
540 | { | |
541 | struct platform_device *pdev = to_platform_device(dev); | |
542 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
543 | unsigned int rcr1; | |
544 | struct rtc_time *tm = &wkalrm->time; | |
545 | int mon, err; | |
546 | ||
547 | err = sh_rtc_check_alarm(tm); | |
548 | if (unlikely(err < 0)) | |
549 | return err; | |
550 | ||
551 | spin_lock_irq(&rtc->lock); | |
552 | ||
15c945c3 | 553 | /* disable alarm interrupt and clear the alarm flag */ |
1b73e6ae | 554 | rcr1 = readb(rtc->regbase + RCR1); |
b420b1a7 | 555 | rcr1 &= ~(RCR1_AF | RCR1_AIE); |
15c945c3 | 556 | writeb(rcr1, rtc->regbase + RCR1); |
1b73e6ae | 557 | |
1b73e6ae JL |
558 | /* set alarm time */ |
559 | sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR); | |
560 | sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR); | |
561 | sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR); | |
562 | sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR); | |
563 | sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR); | |
564 | mon = tm->tm_mon; | |
565 | if (mon >= 0) | |
566 | mon += 1; | |
567 | sh_rtc_write_alarm_value(rtc, mon, RMONAR); | |
568 | ||
15c945c3 JL |
569 | if (wkalrm->enabled) { |
570 | rcr1 |= RCR1_AIE; | |
571 | writeb(rcr1, rtc->regbase + RCR1); | |
572 | } | |
1b73e6ae JL |
573 | |
574 | spin_unlock_irq(&rtc->lock); | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
317a6104 | 579 | static struct rtc_class_ops sh_rtc_ops = { |
317a6104 PM |
580 | .read_time = sh_rtc_read_time, |
581 | .set_time = sh_rtc_set_time, | |
1b73e6ae JL |
582 | .read_alarm = sh_rtc_read_alarm, |
583 | .set_alarm = sh_rtc_set_alarm, | |
317a6104 | 584 | .proc = sh_rtc_proc, |
16380c15 | 585 | .alarm_irq_enable = sh_rtc_alarm_irq_enable, |
317a6104 PM |
586 | }; |
587 | ||
5c9740a8 | 588 | static int __init sh_rtc_probe(struct platform_device *pdev) |
317a6104 PM |
589 | { |
590 | struct sh_rtc *rtc; | |
591 | struct resource *res; | |
edf22477 | 592 | struct rtc_time r; |
063adc75 PM |
593 | char clk_name[6]; |
594 | int clk_id, ret; | |
317a6104 | 595 | |
0209affa | 596 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); |
317a6104 PM |
597 | if (unlikely(!rtc)) |
598 | return -ENOMEM; | |
599 | ||
600 | spin_lock_init(&rtc->lock); | |
601 | ||
b420b1a7 | 602 | /* get periodic/carry/alarm irqs */ |
2641dc92 | 603 | ret = platform_get_irq(pdev, 0); |
2fac6674 | 604 | if (unlikely(ret <= 0)) { |
5e084a15 | 605 | dev_err(&pdev->dev, "No IRQ resource\n"); |
0209affa | 606 | return -ENOENT; |
317a6104 | 607 | } |
063adc75 | 608 | |
2641dc92 | 609 | rtc->periodic_irq = ret; |
5e084a15 MD |
610 | rtc->carry_irq = platform_get_irq(pdev, 1); |
611 | rtc->alarm_irq = platform_get_irq(pdev, 2); | |
317a6104 PM |
612 | |
613 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
614 | if (unlikely(res == NULL)) { | |
615 | dev_err(&pdev->dev, "No IO resource\n"); | |
0209affa | 616 | return -ENOENT; |
317a6104 PM |
617 | } |
618 | ||
063adc75 | 619 | rtc->regsize = resource_size(res); |
317a6104 | 620 | |
0209affa JH |
621 | rtc->res = devm_request_mem_region(&pdev->dev, res->start, |
622 | rtc->regsize, pdev->name); | |
623 | if (unlikely(!rtc->res)) | |
624 | return -EBUSY; | |
317a6104 | 625 | |
0209affa JH |
626 | rtc->regbase = devm_ioremap_nocache(&pdev->dev, rtc->res->start, |
627 | rtc->regsize); | |
628 | if (unlikely(!rtc->regbase)) | |
629 | return -EINVAL; | |
317a6104 | 630 | |
063adc75 PM |
631 | clk_id = pdev->id; |
632 | /* With a single device, the clock id is still "rtc0" */ | |
633 | if (clk_id < 0) | |
634 | clk_id = 0; | |
635 | ||
636 | snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id); | |
637 | ||
0209affa | 638 | rtc->clk = devm_clk_get(&pdev->dev, clk_name); |
063adc75 PM |
639 | if (IS_ERR(rtc->clk)) { |
640 | /* | |
641 | * No error handling for rtc->clk intentionally, not all | |
642 | * platforms will have a unique clock for the RTC, and | |
643 | * the clk API can handle the struct clk pointer being | |
644 | * NULL. | |
645 | */ | |
646 | rtc->clk = NULL; | |
647 | } | |
648 | ||
649 | clk_enable(rtc->clk); | |
650 | ||
ad89f87a PM |
651 | rtc->capabilities = RTC_DEF_CAPABILITIES; |
652 | if (pdev->dev.platform_data) { | |
653 | struct sh_rtc_platform_info *pinfo = pdev->dev.platform_data; | |
654 | ||
655 | /* | |
656 | * Some CPUs have special capabilities in addition to the | |
657 | * default set. Add those in here. | |
658 | */ | |
659 | rtc->capabilities |= pinfo->capabilities; | |
660 | } | |
661 | ||
5e084a15 MD |
662 | if (rtc->carry_irq <= 0) { |
663 | /* register shared periodic/carry/alarm irq */ | |
0209affa JH |
664 | ret = devm_request_irq(&pdev->dev, rtc->periodic_irq, |
665 | sh_rtc_shared, 0, "sh-rtc", rtc); | |
5e084a15 MD |
666 | if (unlikely(ret)) { |
667 | dev_err(&pdev->dev, | |
668 | "request IRQ failed with %d, IRQ %d\n", ret, | |
669 | rtc->periodic_irq); | |
670 | goto err_unmap; | |
671 | } | |
672 | } else { | |
673 | /* register periodic/carry/alarm irqs */ | |
0209affa JH |
674 | ret = devm_request_irq(&pdev->dev, rtc->periodic_irq, |
675 | sh_rtc_periodic, 0, "sh-rtc period", rtc); | |
5e084a15 MD |
676 | if (unlikely(ret)) { |
677 | dev_err(&pdev->dev, | |
678 | "request period IRQ failed with %d, IRQ %d\n", | |
679 | ret, rtc->periodic_irq); | |
680 | goto err_unmap; | |
681 | } | |
b420b1a7 | 682 | |
0209affa JH |
683 | ret = devm_request_irq(&pdev->dev, rtc->carry_irq, |
684 | sh_rtc_interrupt, 0, "sh-rtc carry", rtc); | |
5e084a15 MD |
685 | if (unlikely(ret)) { |
686 | dev_err(&pdev->dev, | |
687 | "request carry IRQ failed with %d, IRQ %d\n", | |
688 | ret, rtc->carry_irq); | |
5e084a15 MD |
689 | goto err_unmap; |
690 | } | |
b420b1a7 | 691 | |
0209affa JH |
692 | ret = devm_request_irq(&pdev->dev, rtc->alarm_irq, |
693 | sh_rtc_alarm, 0, "sh-rtc alarm", rtc); | |
5e084a15 MD |
694 | if (unlikely(ret)) { |
695 | dev_err(&pdev->dev, | |
696 | "request alarm IRQ failed with %d, IRQ %d\n", | |
697 | ret, rtc->alarm_irq); | |
5e084a15 MD |
698 | goto err_unmap; |
699 | } | |
b420b1a7 AC |
700 | } |
701 | ||
5c9740a8 AZ |
702 | platform_set_drvdata(pdev, rtc); |
703 | ||
9cd88b90 | 704 | /* everything disabled by default */ |
5c9740a8 AZ |
705 | sh_rtc_irq_set_freq(&pdev->dev, 0); |
706 | sh_rtc_irq_set_state(&pdev->dev, 0); | |
9cd88b90 MD |
707 | sh_rtc_setaie(&pdev->dev, 0); |
708 | sh_rtc_setcie(&pdev->dev, 0); | |
edf22477 | 709 | |
0209affa | 710 | rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, "sh", |
5c9740a8 AZ |
711 | &sh_rtc_ops, THIS_MODULE); |
712 | if (IS_ERR(rtc->rtc_dev)) { | |
713 | ret = PTR_ERR(rtc->rtc_dev); | |
5c9740a8 AZ |
714 | goto err_unmap; |
715 | } | |
716 | ||
717 | rtc->rtc_dev->max_user_freq = 256; | |
718 | ||
edf22477 MD |
719 | /* reset rtc to epoch 0 if time is invalid */ |
720 | if (rtc_read_time(rtc->rtc_dev, &r) < 0) { | |
721 | rtc_time_to_tm(0, &r); | |
722 | rtc_set_time(rtc->rtc_dev, &r); | |
723 | } | |
724 | ||
7a8fe8e3 | 725 | device_init_wakeup(&pdev->dev, 1); |
317a6104 PM |
726 | return 0; |
727 | ||
0305794c | 728 | err_unmap: |
063adc75 | 729 | clk_disable(rtc->clk); |
317a6104 PM |
730 | |
731 | return ret; | |
732 | } | |
733 | ||
5c9740a8 | 734 | static int __exit sh_rtc_remove(struct platform_device *pdev) |
317a6104 PM |
735 | { |
736 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
737 | ||
5c9740a8 | 738 | sh_rtc_irq_set_state(&pdev->dev, 0); |
317a6104 | 739 | |
317a6104 | 740 | sh_rtc_setaie(&pdev->dev, 0); |
9cd88b90 | 741 | sh_rtc_setcie(&pdev->dev, 0); |
317a6104 | 742 | |
063adc75 | 743 | clk_disable(rtc->clk); |
317a6104 PM |
744 | |
745 | return 0; | |
746 | } | |
faa9fa8e MD |
747 | |
748 | static void sh_rtc_set_irq_wake(struct device *dev, int enabled) | |
749 | { | |
750 | struct platform_device *pdev = to_platform_device(dev); | |
751 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
752 | ||
dced35ae | 753 | irq_set_irq_wake(rtc->periodic_irq, enabled); |
063adc75 | 754 | |
faa9fa8e | 755 | if (rtc->carry_irq > 0) { |
dced35ae TG |
756 | irq_set_irq_wake(rtc->carry_irq, enabled); |
757 | irq_set_irq_wake(rtc->alarm_irq, enabled); | |
faa9fa8e | 758 | } |
faa9fa8e MD |
759 | } |
760 | ||
0ed50544 | 761 | #ifdef CONFIG_PM_SLEEP |
faa9fa8e MD |
762 | static int sh_rtc_suspend(struct device *dev) |
763 | { | |
764 | if (device_may_wakeup(dev)) | |
765 | sh_rtc_set_irq_wake(dev, 1); | |
766 | ||
767 | return 0; | |
768 | } | |
769 | ||
770 | static int sh_rtc_resume(struct device *dev) | |
771 | { | |
772 | if (device_may_wakeup(dev)) | |
773 | sh_rtc_set_irq_wake(dev, 0); | |
774 | ||
775 | return 0; | |
776 | } | |
0ed50544 | 777 | #endif |
faa9fa8e | 778 | |
0ed50544 | 779 | static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume); |
faa9fa8e | 780 | |
317a6104 PM |
781 | static struct platform_driver sh_rtc_platform_driver = { |
782 | .driver = { | |
1b73e6ae | 783 | .name = DRV_NAME, |
317a6104 | 784 | .owner = THIS_MODULE, |
0ed50544 | 785 | .pm = &sh_rtc_pm_ops, |
317a6104 | 786 | }, |
5c9740a8 | 787 | .remove = __exit_p(sh_rtc_remove), |
317a6104 PM |
788 | }; |
789 | ||
deed5a9d | 790 | module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe); |
317a6104 PM |
791 | |
792 | MODULE_DESCRIPTION("SuperH on-chip RTC driver"); | |
1b73e6ae | 793 | MODULE_VERSION(DRV_VERSION); |
b420b1a7 AC |
794 | MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, " |
795 | "Jamie Lenehan <lenehan@twibble.org>, " | |
796 | "Angelo Castello <angelo.castello@st.com>"); | |
317a6104 | 797 | MODULE_LICENSE("GPL"); |
ad28a07b | 798 | MODULE_ALIAS("platform:" DRV_NAME); |