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rtc: ds1672: fix unintended sign extension
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317a6104
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1/*
2 * SuperH On-Chip RTC Support
3 *
063adc75 4 * Copyright (C) 2006 - 2009 Paul Mundt
1b73e6ae 5 * Copyright (C) 2006 Jamie Lenehan
b420b1a7 6 * Copyright (C) 2008 Angelo Castello
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7 *
8 * Based on the old arch/sh/kernel/cpu/rtc.c by:
9 *
10 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
11 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 */
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/bcd.h>
20#include <linux/rtc.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/seq_file.h>
24#include <linux/interrupt.h>
25#include <linux/spinlock.h>
31ccb081 26#include <linux/io.h>
5d2a5037 27#include <linux/log2.h>
063adc75 28#include <linux/clk.h>
5a0e3ad6 29#include <linux/slab.h>
dab5aec6 30#ifdef CONFIG_SUPERH
ad89f87a 31#include <asm/rtc.h>
dab5aec6
CB
32#else
33/* Default values for RZ/A RTC */
34#define rtc_reg_size sizeof(u16)
35#define RTC_BIT_INVERTED 0 /* no chip bugs */
36#define RTC_CAP_4_DIGIT_YEAR (1 << 0)
37#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
38#endif
317a6104 39
1b73e6ae 40#define DRV_NAME "sh-rtc"
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41
42#define RTC_REG(r) ((r) * rtc_reg_size)
43
31ccb081 44#define R64CNT RTC_REG(0)
1b73e6ae
JL
45
46#define RSECCNT RTC_REG(1) /* RTC sec */
47#define RMINCNT RTC_REG(2) /* RTC min */
48#define RHRCNT RTC_REG(3) /* RTC hour */
49#define RWKCNT RTC_REG(4) /* RTC week */
50#define RDAYCNT RTC_REG(5) /* RTC day */
51#define RMONCNT RTC_REG(6) /* RTC month */
52#define RYRCNT RTC_REG(7) /* RTC year */
53#define RSECAR RTC_REG(8) /* ALARM sec */
54#define RMINAR RTC_REG(9) /* ALARM min */
55#define RHRAR RTC_REG(10) /* ALARM hour */
56#define RWKAR RTC_REG(11) /* ALARM week */
57#define RDAYAR RTC_REG(12) /* ALARM day */
58#define RMONAR RTC_REG(13) /* ALARM month */
59#define RCR1 RTC_REG(14) /* Control */
60#define RCR2 RTC_REG(15) /* Control */
61
ff1b7506
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62/*
63 * Note on RYRAR and RCR3: Up until this point most of the register
64 * definitions are consistent across all of the available parts. However,
65 * the placement of the optional RYRAR and RCR3 (the RYRAR control
66 * register used to control RYRCNT/RYRAR compare) varies considerably
67 * across various parts, occasionally being mapped in to a completely
68 * unrelated address space. For proper RYRAR support a separate resource
69 * would have to be handed off, but as this is purely optional in
70 * practice, we simply opt not to support it, thereby keeping the code
71 * quite a bit more simplified.
72 */
73
1b73e6ae
JL
74/* ALARM Bits - or with BCD encoded value */
75#define AR_ENB 0x80 /* Enable for alarm cmp */
317a6104 76
b420b1a7
AC
77/* Period Bits */
78#define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
79#define PF_COUNT 0x200 /* Half periodic counter */
80#define PF_OXS 0x400 /* Periodic One x Second */
81#define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */
82#define PF_MASK 0xf00
83
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84/* RCR1 Bits */
85#define RCR1_CF 0x80 /* Carry Flag */
86#define RCR1_CIE 0x10 /* Carry Interrupt Enable */
87#define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
88#define RCR1_AF 0x01 /* Alarm Flag */
89
90/* RCR2 Bits */
91#define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
92#define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
93#define RCR2_RTCEN 0x08 /* ENable RTC */
94#define RCR2_ADJ 0x04 /* ADJustment (30-second) */
95#define RCR2_RESET 0x02 /* Reset bit */
96#define RCR2_START 0x01 /* Start bit */
97
98struct sh_rtc {
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99 void __iomem *regbase;
100 unsigned long regsize;
101 struct resource *res;
102 int alarm_irq;
103 int periodic_irq;
104 int carry_irq;
105 struct clk *clk;
106 struct rtc_device *rtc_dev;
107 spinlock_t lock;
108 unsigned long capabilities; /* See asm/rtc.h for cap bits */
109 unsigned short periodic_freq;
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110};
111
5e084a15 112static int __sh_rtc_interrupt(struct sh_rtc *rtc)
317a6104 113{
5e084a15 114 unsigned int tmp, pending;
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115
116 tmp = readb(rtc->regbase + RCR1);
5e084a15 117 pending = tmp & RCR1_CF;
1b73e6ae 118 tmp &= ~RCR1_CF;
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119 writeb(tmp, rtc->regbase + RCR1);
120
b420b1a7 121 /* Users have requested One x Second IRQ */
5e084a15 122 if (pending && rtc->periodic_freq & PF_OXS)
b420b1a7 123 rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
317a6104 124
5e084a15 125 return pending;
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126}
127
5e084a15 128static int __sh_rtc_alarm(struct sh_rtc *rtc)
1b73e6ae 129{
5e084a15 130 unsigned int tmp, pending;
1b73e6ae
JL
131
132 tmp = readb(rtc->regbase + RCR1);
5e084a15 133 pending = tmp & RCR1_AF;
b420b1a7 134 tmp &= ~(RCR1_AF | RCR1_AIE);
5e084a15 135 writeb(tmp, rtc->regbase + RCR1);
1b73e6ae 136
5e084a15
MD
137 if (pending)
138 rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
b420b1a7 139
5e084a15 140 return pending;
1b73e6ae
JL
141}
142
5e084a15 143static int __sh_rtc_periodic(struct sh_rtc *rtc)
317a6104 144{
b420b1a7 145 struct rtc_device *rtc_dev = rtc->rtc_dev;
5e084a15
MD
146 struct rtc_task *irq_task;
147 unsigned int tmp, pending;
317a6104 148
b420b1a7 149 tmp = readb(rtc->regbase + RCR2);
5e084a15 150 pending = tmp & RCR2_PEF;
b420b1a7
AC
151 tmp &= ~RCR2_PEF;
152 writeb(tmp, rtc->regbase + RCR2);
153
5e084a15
MD
154 if (!pending)
155 return 0;
156
b420b1a7
AC
157 /* Half period enabled than one skipped and the next notified */
158 if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
159 rtc->periodic_freq &= ~PF_COUNT;
160 else {
161 if (rtc->periodic_freq & PF_HP)
162 rtc->periodic_freq |= PF_COUNT;
163 if (rtc->periodic_freq & PF_KOU) {
164 spin_lock(&rtc_dev->irq_task_lock);
5e084a15
MD
165 irq_task = rtc_dev->irq_task;
166 if (irq_task)
167 irq_task->func(irq_task->private_data);
b420b1a7
AC
168 spin_unlock(&rtc_dev->irq_task_lock);
169 } else
170 rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
171 }
317a6104 172
5e084a15
MD
173 return pending;
174}
175
176static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
177{
178 struct sh_rtc *rtc = dev_id;
179 int ret;
180
181 spin_lock(&rtc->lock);
182 ret = __sh_rtc_interrupt(rtc);
183 spin_unlock(&rtc->lock);
184
185 return IRQ_RETVAL(ret);
186}
187
188static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
189{
190 struct sh_rtc *rtc = dev_id;
191 int ret;
192
193 spin_lock(&rtc->lock);
194 ret = __sh_rtc_alarm(rtc);
195 spin_unlock(&rtc->lock);
196
197 return IRQ_RETVAL(ret);
198}
199
200static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
201{
202 struct sh_rtc *rtc = dev_id;
203 int ret;
204
205 spin_lock(&rtc->lock);
206 ret = __sh_rtc_periodic(rtc);
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207 spin_unlock(&rtc->lock);
208
5e084a15
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209 return IRQ_RETVAL(ret);
210}
211
212static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
213{
214 struct sh_rtc *rtc = dev_id;
215 int ret;
216
217 spin_lock(&rtc->lock);
218 ret = __sh_rtc_interrupt(rtc);
219 ret |= __sh_rtc_alarm(rtc);
220 ret |= __sh_rtc_periodic(rtc);
221 spin_unlock(&rtc->lock);
222
223 return IRQ_RETVAL(ret);
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224}
225
5c9740a8 226static int sh_rtc_irq_set_state(struct device *dev, int enable)
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227{
228 struct sh_rtc *rtc = dev_get_drvdata(dev);
229 unsigned int tmp;
230
231 spin_lock_irq(&rtc->lock);
232
233 tmp = readb(rtc->regbase + RCR2);
234
235 if (enable) {
5c9740a8 236 rtc->periodic_freq |= PF_KOU;
b420b1a7
AC
237 tmp &= ~RCR2_PEF; /* Clear PES bit */
238 tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */
5c9740a8
AZ
239 } else {
240 rtc->periodic_freq &= ~PF_KOU;
317a6104 241 tmp &= ~(RCR2_PESMASK | RCR2_PEF);
5c9740a8 242 }
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243
244 writeb(tmp, rtc->regbase + RCR2);
245
246 spin_unlock_irq(&rtc->lock);
5c9740a8
AZ
247
248 return 0;
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249}
250
5c9740a8 251static int sh_rtc_irq_set_freq(struct device *dev, int freq)
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252{
253 struct sh_rtc *rtc = dev_get_drvdata(dev);
b420b1a7 254 int tmp, ret = 0;
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255
256 spin_lock_irq(&rtc->lock);
b420b1a7 257 tmp = rtc->periodic_freq & PF_MASK;
317a6104 258
b420b1a7
AC
259 switch (freq) {
260 case 0:
261 rtc->periodic_freq = 0x00;
262 break;
263 case 1:
264 rtc->periodic_freq = 0x60;
265 break;
266 case 2:
267 rtc->periodic_freq = 0x50;
268 break;
269 case 4:
270 rtc->periodic_freq = 0x40;
271 break;
272 case 8:
273 rtc->periodic_freq = 0x30 | PF_HP;
274 break;
275 case 16:
276 rtc->periodic_freq = 0x30;
277 break;
278 case 32:
279 rtc->periodic_freq = 0x20 | PF_HP;
280 break;
281 case 64:
282 rtc->periodic_freq = 0x20;
283 break;
284 case 128:
285 rtc->periodic_freq = 0x10 | PF_HP;
286 break;
287 case 256:
288 rtc->periodic_freq = 0x10;
289 break;
290 default:
291 ret = -ENOTSUPP;
292 }
317a6104 293
1043bf5c 294 if (ret == 0)
b420b1a7 295 rtc->periodic_freq |= tmp;
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296
297 spin_unlock_irq(&rtc->lock);
b420b1a7 298 return ret;
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299}
300
b420b1a7 301static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
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302{
303 struct sh_rtc *rtc = dev_get_drvdata(dev);
304 unsigned int tmp;
317a6104 305
b420b1a7 306 spin_lock_irq(&rtc->lock);
317a6104 307
b420b1a7 308 tmp = readb(rtc->regbase + RCR1);
317a6104 309
063adc75 310 if (enable)
b420b1a7 311 tmp |= RCR1_AIE;
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312 else
313 tmp &= ~RCR1_AIE;
317a6104 314
b420b1a7 315 writeb(tmp, rtc->regbase + RCR1);
317a6104 316
b420b1a7 317 spin_unlock_irq(&rtc->lock);
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318}
319
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320static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
321{
322 struct sh_rtc *rtc = dev_get_drvdata(dev);
323 unsigned int tmp;
324
325 tmp = readb(rtc->regbase + RCR1);
b420b1a7 326 seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
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327
328 tmp = readb(rtc->regbase + RCR2);
329 seq_printf(seq, "periodic_IRQ\t: %s\n",
b420b1a7 330 (tmp & RCR2_PESMASK) ? "yes" : "no");
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331
332 return 0;
333}
334
9cd88b90
MD
335static inline void sh_rtc_setcie(struct device *dev, unsigned int enable)
336{
337 struct sh_rtc *rtc = dev_get_drvdata(dev);
338 unsigned int tmp;
339
340 spin_lock_irq(&rtc->lock);
341
342 tmp = readb(rtc->regbase + RCR1);
343
344 if (!enable)
345 tmp &= ~RCR1_CIE;
346 else
347 tmp |= RCR1_CIE;
348
349 writeb(tmp, rtc->regbase + RCR1);
350
351 spin_unlock_irq(&rtc->lock);
352}
353
16380c15
JS
354static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
355{
356 sh_rtc_setaie(dev, enabled);
357 return 0;
358}
359
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360static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
361{
362 struct platform_device *pdev = to_platform_device(dev);
363 struct sh_rtc *rtc = platform_get_drvdata(pdev);
364 unsigned int sec128, sec2, yr, yr100, cf_bit;
365
366 do {
367 unsigned int tmp;
368
369 spin_lock_irq(&rtc->lock);
370
371 tmp = readb(rtc->regbase + RCR1);
372 tmp &= ~RCR1_CF; /* Clear CF-bit */
373 tmp |= RCR1_CIE;
374 writeb(tmp, rtc->regbase + RCR1);
375
376 sec128 = readb(rtc->regbase + R64CNT);
377
fe20ba70
AB
378 tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT));
379 tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT));
380 tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT));
381 tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT));
382 tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT));
383 tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1;
317a6104 384
ad89f87a
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385 if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
386 yr = readw(rtc->regbase + RYRCNT);
fe20ba70 387 yr100 = bcd2bin(yr >> 8);
ad89f87a
PM
388 yr &= 0xff;
389 } else {
390 yr = readb(rtc->regbase + RYRCNT);
fe20ba70 391 yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20);
ad89f87a 392 }
317a6104 393
fe20ba70 394 tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900;
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395
396 sec2 = readb(rtc->regbase + R64CNT);
397 cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
398
399 spin_unlock_irq(&rtc->lock);
400 } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);
401
402#if RTC_BIT_INVERTED != 0
403 if ((sec128 & RTC_BIT_INVERTED))
404 tm->tm_sec--;
405#endif
406
9cd88b90
MD
407 /* only keep the carry interrupt enabled if UIE is on */
408 if (!(rtc->periodic_freq & PF_OXS))
409 sh_rtc_setcie(dev, 0);
410
435c55d1 411 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
317a6104 412 "mday=%d, mon=%d, year=%d, wday=%d\n",
2a4e2b87 413 __func__,
317a6104 414 tm->tm_sec, tm->tm_min, tm->tm_hour,
a1614796 415 tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
317a6104 416
edf22477 417 return rtc_valid_tm(tm);
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418}
419
420static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
421{
422 struct platform_device *pdev = to_platform_device(dev);
423 struct sh_rtc *rtc = platform_get_drvdata(pdev);
424 unsigned int tmp;
425 int year;
426
427 spin_lock_irq(&rtc->lock);
428
429 /* Reset pre-scaler & stop RTC */
430 tmp = readb(rtc->regbase + RCR2);
431 tmp |= RCR2_RESET;
699bc661 432 tmp &= ~RCR2_START;
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433 writeb(tmp, rtc->regbase + RCR2);
434
fe20ba70
AB
435 writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT);
436 writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT);
437 writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT);
438 writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT);
439 writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT);
440 writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT);
317a6104 441
ad89f87a 442 if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
fe20ba70
AB
443 year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) |
444 bin2bcd(tm->tm_year % 100);
ad89f87a
PM
445 writew(year, rtc->regbase + RYRCNT);
446 } else {
447 year = tm->tm_year % 100;
fe20ba70 448 writeb(bin2bcd(year), rtc->regbase + RYRCNT);
ad89f87a 449 }
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450
451 /* Start RTC */
452 tmp = readb(rtc->regbase + RCR2);
453 tmp &= ~RCR2_RESET;
454 tmp |= RCR2_RTCEN | RCR2_START;
455 writeb(tmp, rtc->regbase + RCR2);
456
457 spin_unlock_irq(&rtc->lock);
458
459 return 0;
460}
461
1b73e6ae
JL
462static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
463{
464 unsigned int byte;
86de230d 465 int value = -1; /* return -1 for ignored values */
1b73e6ae
JL
466
467 byte = readb(rtc->regbase + reg_off);
468 if (byte & AR_ENB) {
469 byte &= ~AR_ENB; /* strip the enable bit */
fe20ba70 470 value = bcd2bin(byte);
1b73e6ae
JL
471 }
472
473 return value;
474}
475
476static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
477{
478 struct platform_device *pdev = to_platform_device(dev);
479 struct sh_rtc *rtc = platform_get_drvdata(pdev);
b420b1a7 480 struct rtc_time *tm = &wkalrm->time;
1b73e6ae
JL
481
482 spin_lock_irq(&rtc->lock);
483
484 tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR);
485 tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR);
486 tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR);
487 tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR);
488 tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR);
489 tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR);
490 if (tm->tm_mon > 0)
491 tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
1b73e6ae 492
0d103e90
DB
493 wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0;
494
1b73e6ae
JL
495 spin_unlock_irq(&rtc->lock);
496
497 return 0;
498}
499
500static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
501 int value, int reg_off)
502{
503 /* < 0 for a value that is ignored */
504 if (value < 0)
505 writeb(0, rtc->regbase + reg_off);
506 else
fe20ba70 507 writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off);
1b73e6ae
JL
508}
509
1b73e6ae
JL
510static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
511{
512 struct platform_device *pdev = to_platform_device(dev);
513 struct sh_rtc *rtc = platform_get_drvdata(pdev);
514 unsigned int rcr1;
515 struct rtc_time *tm = &wkalrm->time;
8441189e 516 int mon;
1b73e6ae
JL
517
518 spin_lock_irq(&rtc->lock);
519
15c945c3 520 /* disable alarm interrupt and clear the alarm flag */
1b73e6ae 521 rcr1 = readb(rtc->regbase + RCR1);
b420b1a7 522 rcr1 &= ~(RCR1_AF | RCR1_AIE);
15c945c3 523 writeb(rcr1, rtc->regbase + RCR1);
1b73e6ae 524
1b73e6ae
JL
525 /* set alarm time */
526 sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR);
527 sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR);
528 sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR);
529 sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR);
530 sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR);
531 mon = tm->tm_mon;
532 if (mon >= 0)
533 mon += 1;
534 sh_rtc_write_alarm_value(rtc, mon, RMONAR);
535
15c945c3
JL
536 if (wkalrm->enabled) {
537 rcr1 |= RCR1_AIE;
538 writeb(rcr1, rtc->regbase + RCR1);
539 }
1b73e6ae
JL
540
541 spin_unlock_irq(&rtc->lock);
542
543 return 0;
544}
545
8bc57e7f 546static const struct rtc_class_ops sh_rtc_ops = {
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547 .read_time = sh_rtc_read_time,
548 .set_time = sh_rtc_set_time,
1b73e6ae
JL
549 .read_alarm = sh_rtc_read_alarm,
550 .set_alarm = sh_rtc_set_alarm,
317a6104 551 .proc = sh_rtc_proc,
16380c15 552 .alarm_irq_enable = sh_rtc_alarm_irq_enable,
317a6104
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553};
554
5c9740a8 555static int __init sh_rtc_probe(struct platform_device *pdev)
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556{
557 struct sh_rtc *rtc;
558 struct resource *res;
edf22477 559 struct rtc_time r;
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560 char clk_name[6];
561 int clk_id, ret;
317a6104 562
0209affa 563 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
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564 if (unlikely(!rtc))
565 return -ENOMEM;
566
567 spin_lock_init(&rtc->lock);
568
b420b1a7 569 /* get periodic/carry/alarm irqs */
2641dc92 570 ret = platform_get_irq(pdev, 0);
2fac6674 571 if (unlikely(ret <= 0)) {
5e084a15 572 dev_err(&pdev->dev, "No IRQ resource\n");
0209affa 573 return -ENOENT;
317a6104 574 }
063adc75 575
2641dc92 576 rtc->periodic_irq = ret;
5e084a15
MD
577 rtc->carry_irq = platform_get_irq(pdev, 1);
578 rtc->alarm_irq = platform_get_irq(pdev, 2);
317a6104
PM
579
580 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
dab5aec6
CB
581 if (!res)
582 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
317a6104
PM
583 if (unlikely(res == NULL)) {
584 dev_err(&pdev->dev, "No IO resource\n");
0209affa 585 return -ENOENT;
317a6104
PM
586 }
587
063adc75 588 rtc->regsize = resource_size(res);
317a6104 589
0209affa
JH
590 rtc->res = devm_request_mem_region(&pdev->dev, res->start,
591 rtc->regsize, pdev->name);
592 if (unlikely(!rtc->res))
593 return -EBUSY;
317a6104 594
0209affa
JH
595 rtc->regbase = devm_ioremap_nocache(&pdev->dev, rtc->res->start,
596 rtc->regsize);
597 if (unlikely(!rtc->regbase))
598 return -EINVAL;
317a6104 599
dab5aec6
CB
600 if (!pdev->dev.of_node) {
601 clk_id = pdev->id;
602 /* With a single device, the clock id is still "rtc0" */
603 if (clk_id < 0)
604 clk_id = 0;
063adc75 605
dab5aec6
CB
606 snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id);
607 } else
608 snprintf(clk_name, sizeof(clk_name), "fck");
063adc75 609
0209affa 610 rtc->clk = devm_clk_get(&pdev->dev, clk_name);
063adc75
PM
611 if (IS_ERR(rtc->clk)) {
612 /*
613 * No error handling for rtc->clk intentionally, not all
614 * platforms will have a unique clock for the RTC, and
615 * the clk API can handle the struct clk pointer being
616 * NULL.
617 */
618 rtc->clk = NULL;
619 }
620
621 clk_enable(rtc->clk);
622
ad89f87a 623 rtc->capabilities = RTC_DEF_CAPABILITIES;
dab5aec6
CB
624
625#ifdef CONFIG_SUPERH
e58c18d4
JH
626 if (dev_get_platdata(&pdev->dev)) {
627 struct sh_rtc_platform_info *pinfo =
628 dev_get_platdata(&pdev->dev);
ad89f87a
PM
629
630 /*
631 * Some CPUs have special capabilities in addition to the
632 * default set. Add those in here.
633 */
634 rtc->capabilities |= pinfo->capabilities;
635 }
dab5aec6 636#endif
ad89f87a 637
5e084a15
MD
638 if (rtc->carry_irq <= 0) {
639 /* register shared periodic/carry/alarm irq */
0209affa
JH
640 ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
641 sh_rtc_shared, 0, "sh-rtc", rtc);
5e084a15
MD
642 if (unlikely(ret)) {
643 dev_err(&pdev->dev,
644 "request IRQ failed with %d, IRQ %d\n", ret,
645 rtc->periodic_irq);
646 goto err_unmap;
647 }
648 } else {
649 /* register periodic/carry/alarm irqs */
0209affa
JH
650 ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
651 sh_rtc_periodic, 0, "sh-rtc period", rtc);
5e084a15
MD
652 if (unlikely(ret)) {
653 dev_err(&pdev->dev,
654 "request period IRQ failed with %d, IRQ %d\n",
655 ret, rtc->periodic_irq);
656 goto err_unmap;
657 }
b420b1a7 658
0209affa
JH
659 ret = devm_request_irq(&pdev->dev, rtc->carry_irq,
660 sh_rtc_interrupt, 0, "sh-rtc carry", rtc);
5e084a15
MD
661 if (unlikely(ret)) {
662 dev_err(&pdev->dev,
663 "request carry IRQ failed with %d, IRQ %d\n",
664 ret, rtc->carry_irq);
5e084a15
MD
665 goto err_unmap;
666 }
b420b1a7 667
0209affa
JH
668 ret = devm_request_irq(&pdev->dev, rtc->alarm_irq,
669 sh_rtc_alarm, 0, "sh-rtc alarm", rtc);
5e084a15
MD
670 if (unlikely(ret)) {
671 dev_err(&pdev->dev,
672 "request alarm IRQ failed with %d, IRQ %d\n",
673 ret, rtc->alarm_irq);
5e084a15
MD
674 goto err_unmap;
675 }
b420b1a7
AC
676 }
677
5c9740a8
AZ
678 platform_set_drvdata(pdev, rtc);
679
9cd88b90 680 /* everything disabled by default */
5c9740a8
AZ
681 sh_rtc_irq_set_freq(&pdev->dev, 0);
682 sh_rtc_irq_set_state(&pdev->dev, 0);
9cd88b90
MD
683 sh_rtc_setaie(&pdev->dev, 0);
684 sh_rtc_setcie(&pdev->dev, 0);
edf22477 685
0209affa 686 rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, "sh",
5c9740a8
AZ
687 &sh_rtc_ops, THIS_MODULE);
688 if (IS_ERR(rtc->rtc_dev)) {
689 ret = PTR_ERR(rtc->rtc_dev);
5c9740a8
AZ
690 goto err_unmap;
691 }
692
693 rtc->rtc_dev->max_user_freq = 256;
694
edf22477
MD
695 /* reset rtc to epoch 0 if time is invalid */
696 if (rtc_read_time(rtc->rtc_dev, &r) < 0) {
697 rtc_time_to_tm(0, &r);
698 rtc_set_time(rtc->rtc_dev, &r);
699 }
700
7a8fe8e3 701 device_init_wakeup(&pdev->dev, 1);
317a6104
PM
702 return 0;
703
0305794c 704err_unmap:
063adc75 705 clk_disable(rtc->clk);
317a6104
PM
706
707 return ret;
708}
709
5c9740a8 710static int __exit sh_rtc_remove(struct platform_device *pdev)
317a6104
PM
711{
712 struct sh_rtc *rtc = platform_get_drvdata(pdev);
713
5c9740a8 714 sh_rtc_irq_set_state(&pdev->dev, 0);
317a6104 715
317a6104 716 sh_rtc_setaie(&pdev->dev, 0);
9cd88b90 717 sh_rtc_setcie(&pdev->dev, 0);
317a6104 718
063adc75 719 clk_disable(rtc->clk);
317a6104
PM
720
721 return 0;
722}
faa9fa8e
MD
723
724static void sh_rtc_set_irq_wake(struct device *dev, int enabled)
725{
726 struct platform_device *pdev = to_platform_device(dev);
727 struct sh_rtc *rtc = platform_get_drvdata(pdev);
728
dced35ae 729 irq_set_irq_wake(rtc->periodic_irq, enabled);
063adc75 730
faa9fa8e 731 if (rtc->carry_irq > 0) {
dced35ae
TG
732 irq_set_irq_wake(rtc->carry_irq, enabled);
733 irq_set_irq_wake(rtc->alarm_irq, enabled);
faa9fa8e 734 }
faa9fa8e
MD
735}
736
5d05e815 737static int __maybe_unused sh_rtc_suspend(struct device *dev)
faa9fa8e
MD
738{
739 if (device_may_wakeup(dev))
740 sh_rtc_set_irq_wake(dev, 1);
741
742 return 0;
743}
744
5d05e815 745static int __maybe_unused sh_rtc_resume(struct device *dev)
faa9fa8e
MD
746{
747 if (device_may_wakeup(dev))
748 sh_rtc_set_irq_wake(dev, 0);
749
750 return 0;
751}
752
0ed50544 753static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume);
faa9fa8e 754
dab5aec6
CB
755static const struct of_device_id sh_rtc_of_match[] = {
756 { .compatible = "renesas,sh-rtc", },
757 { /* sentinel */ }
758};
759MODULE_DEVICE_TABLE(of, sh_rtc_of_match);
760
317a6104
PM
761static struct platform_driver sh_rtc_platform_driver = {
762 .driver = {
1b73e6ae 763 .name = DRV_NAME,
0ed50544 764 .pm = &sh_rtc_pm_ops,
dab5aec6 765 .of_match_table = sh_rtc_of_match,
317a6104 766 },
5c9740a8 767 .remove = __exit_p(sh_rtc_remove),
317a6104
PM
768};
769
deed5a9d 770module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe);
317a6104
PM
771
772MODULE_DESCRIPTION("SuperH on-chip RTC driver");
b420b1a7
AC
773MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
774 "Jamie Lenehan <lenehan@twibble.org>, "
775 "Angelo Castello <angelo.castello@st.com>");
317a6104 776MODULE_LICENSE("GPL");
ad28a07b 777MODULE_ALIAS("platform:" DRV_NAME);