[mirror_ubuntu-jammy-kernel.git] / drivers / rtc / rtc-snvs.c

// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2011-2012 Freescale Semiconductor, Inc.

#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/rtc.h>
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#define SNVS_LPREGISTER_OFFSET	0x34

/* These register offsets are relative to LP (Low Power) range */
#define SNVS_LPCR		0x04
#define SNVS_LPSR		0x18
#define SNVS_LPSRTCMR		0x1c
#define SNVS_LPSRTCLR		0x20
#define SNVS_LPTAR		0x24
#define SNVS_LPPGDR		0x30

#define SNVS_LPCR_SRTC_ENV	(1 << 0)
#define SNVS_LPCR_LPTA_EN	(1 << 1)
#define SNVS_LPCR_LPWUI_EN	(1 << 3)
#define SNVS_LPSR_LPTA		(1 << 0)

#define SNVS_LPPGDR_INIT	0x41736166
#define CNTR_TO_SECS_SH		15

struct snvs_rtc_data {
	struct rtc_device *rtc;
	struct regmap *regmap;
	int offset;
	int irq;
	struct clk *clk;
};

/* Read 64 bit timer register, which could be in inconsistent state */
static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
{
	u32 msb, lsb;

	regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
	return (u64)msb << 32 | lsb;
}

/* Read the secure real time counter, taking care to deal with the cases of the
 * counter updating while being read.
 */
static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
{
	u64 read1, read2;
	unsigned int timeout = 100;

	/* As expected, the registers might update between the read of the LSB
	 * reg and the MSB reg.  It's also possible that one register might be
	 * in partially modified state as well.
	 */
	read1 = rtc_read_lpsrt(data);
	do {
		read2 = read1;
		read1 = rtc_read_lpsrt(data);
	} while (read1 != read2 && --timeout);
	if (!timeout)
		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");

	/* Convert 47-bit counter to 32-bit raw second count */
	return (u32) (read1 >> CNTR_TO_SECS_SH);
}

/* Just read the lsb from the counter, dealing with inconsistent state */
static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
{
	u32 count1, count2;
	unsigned int timeout = 100;

	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	do {
		count2 = count1;
		regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	} while (count1 != count2 && --timeout);
	if (!timeout) {
		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
		return -ETIMEDOUT;
	}

	*lsb = count1;
	return 0;
}

static int rtc_write_sync_lp(struct snvs_rtc_data *data)
{
	u32 count1, count2;
	u32 elapsed;
	unsigned int timeout = 1000;
	int ret;

	ret = rtc_read_lp_counter_lsb(data, &count1);
	if (ret)
		return ret;

	/* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
	do {
		ret = rtc_read_lp_counter_lsb(data, &count2);
		if (ret)
			return ret;
		elapsed = count2 - count1; /* wrap around _is_ handled! */
	} while (elapsed < 3 && --timeout);
	if (!timeout) {
		dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
		return -ETIMEDOUT;
	}
	return 0;
}

static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
{
	int timeout = 1000;
	u32 lpcr;

	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
			   enable ? SNVS_LPCR_SRTC_ENV : 0);

	while (--timeout) {
		regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);

		if (enable) {
			if (lpcr & SNVS_LPCR_SRTC_ENV)
				break;
		} else {
			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
				break;
		}
	}

	if (!timeout)
		return -ETIMEDOUT;

	return 0;
}

static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	unsigned long time;
	int ret;

	ret = clk_enable(data->clk);
	if (ret)
		return ret;

	time = rtc_read_lp_counter(data);
	rtc_time64_to_tm(time, tm);

	clk_disable(data->clk);

	return 0;
}

static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	unsigned long time = rtc_tm_to_time64(tm);
	int ret;

	ret = clk_enable(data->clk);
	if (ret)
		return ret;

	/* Disable RTC first */
	ret = snvs_rtc_enable(data, false);
	if (ret)
		return ret;

	/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
	regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
	regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));

	/* Enable RTC again */
	ret = snvs_rtc_enable(data, true);

	clk_disable(data->clk);

	return ret;
}

static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	u32 lptar, lpsr;
	int ret;

	ret = clk_enable(data->clk);
	if (ret)
		return ret;

	regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
	rtc_time64_to_tm(lptar, &alrm->time);

	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
	alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;

	clk_disable(data->clk);

	return 0;
}

static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	int ret;

	ret = clk_enable(data->clk);
	if (ret)
		return ret;

	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
			   (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
			   enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);

	ret = rtc_write_sync_lp(data);

	clk_disable(data->clk);

	return ret;
}

static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	unsigned long time = rtc_tm_to_time64(&alrm->time);
	int ret;

	ret = clk_enable(data->clk);
	if (ret)
		return ret;

	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
	ret = rtc_write_sync_lp(data);
	if (ret)
		return ret;
	regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);

	/* Clear alarm interrupt status bit */
	regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);

	clk_disable(data->clk);

	return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
}

static const struct rtc_class_ops snvs_rtc_ops = {
	.read_time = snvs_rtc_read_time,
	.set_time = snvs_rtc_set_time,
	.read_alarm = snvs_rtc_read_alarm,
	.set_alarm = snvs_rtc_set_alarm,
	.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
};

static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
{
	struct device *dev = dev_id;
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	u32 lpsr;
	u32 events = 0;

	clk_enable(data->clk);

	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);

	if (lpsr & SNVS_LPSR_LPTA) {
		events |= (RTC_AF | RTC_IRQF);

		/* RTC alarm should be one-shot */
		snvs_rtc_alarm_irq_enable(dev, 0);

		rtc_update_irq(data->rtc, 1, events);
	}

	/* clear interrupt status */
	regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);

	clk_disable(data->clk);

	return events ? IRQ_HANDLED : IRQ_NONE;
}

static const struct regmap_config snvs_rtc_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
};

static void snvs_rtc_action(void *data)
{
	clk_disable_unprepare(data);
}

static int snvs_rtc_probe(struct platform_device *pdev)
{
	struct snvs_rtc_data *data;
	int ret;
	void __iomem *mmio;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(data->rtc))
		return PTR_ERR(data->rtc);

	data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");

	if (IS_ERR(data->regmap)) {
		dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");

		mmio = devm_platform_ioremap_resource(pdev, 0);
		if (IS_ERR(mmio))
			return PTR_ERR(mmio);

		data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
	} else {
		data->offset = SNVS_LPREGISTER_OFFSET;
		of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
	}

	if (IS_ERR(data->regmap)) {
		dev_err(&pdev->dev, "Can't find snvs syscon\n");
		return -ENODEV;
	}

	data->irq = platform_get_irq(pdev, 0);
	if (data->irq < 0)
		return data->irq;

	data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
	if (IS_ERR(data->clk)) {
		data->clk = NULL;
	} else {
		ret = clk_prepare_enable(data->clk);
		if (ret) {
			dev_err(&pdev->dev,
				"Could not prepare or enable the snvs clock\n");
			return ret;
		}
	}

	ret = devm_add_action_or_reset(&pdev->dev, snvs_rtc_action, data->clk);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, data);

	/* Initialize glitch detect */
	regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);

	/* Clear interrupt status */
	regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);

	/* Enable RTC */
	ret = snvs_rtc_enable(data, true);
	if (ret) {
		dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
		return ret;
	}

	device_init_wakeup(&pdev->dev, true);
	ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
	if (ret)
		dev_err(&pdev->dev, "failed to enable irq wake\n");

	ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
			       IRQF_SHARED, "rtc alarm", &pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "failed to request irq %d: %d\n",
			data->irq, ret);
		return ret;
	}

	data->rtc->ops = &snvs_rtc_ops;
	data->rtc->range_max = U32_MAX;

	return devm_rtc_register_device(data->rtc);
}

static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);

	clk_disable(data->clk);

	return 0;
}

static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);

	if (data->clk)
		return clk_enable(data->clk);

	return 0;
}

static const struct dev_pm_ops snvs_rtc_pm_ops = {
	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
};

static const struct of_device_id snvs_dt_ids[] = {
	{ .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, snvs_dt_ids);

static struct platform_driver snvs_rtc_driver = {
	.driver = {
		.name	= "snvs_rtc",
		.pm	= &snvs_rtc_pm_ops,
		.of_match_table = snvs_dt_ids,
	},
	.probe		= snvs_rtc_probe,
};
module_platform_driver(snvs_rtc_driver);

MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
5874c7f1 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
179a502f SG	4
	5	#include <linux/init.h>
	6	#include <linux/io.h>
	7	#include <linux/kernel.h>
	8	#include <linux/module.h>
	9	#include <linux/of.h>
179a502f	10	#include <linux/platform_device.h>
e7afddb2	11	#include <linux/pm_wakeirq.h>
179a502f	12	#include <linux/rtc.h>
7f899399	13	#include <linux/clk.h>
d482893b FL	14	#include <linux/mfd/syscon.h>
	15	#include <linux/regmap.h>
	16
	17	#define SNVS_LPREGISTER_OFFSET 0x34
179a502f SG	18
	19	/* These register offsets are relative to LP (Low Power) range */
	20	#define SNVS_LPCR 0x04
	21	#define SNVS_LPSR 0x18
	22	#define SNVS_LPSRTCMR 0x1c
	23	#define SNVS_LPSRTCLR 0x20
	24	#define SNVS_LPTAR 0x24
	25	#define SNVS_LPPGDR 0x30
	26
	27	#define SNVS_LPCR_SRTC_ENV (1 << 0)
	28	#define SNVS_LPCR_LPTA_EN (1 << 1)
	29	#define SNVS_LPCR_LPWUI_EN (1 << 3)
	30	#define SNVS_LPSR_LPTA (1 << 0)
	31
	32	#define SNVS_LPPGDR_INIT 0x41736166
	33	#define CNTR_TO_SECS_SH 15
	34
	35	struct snvs_rtc_data {
	36	struct rtc_device *rtc;
d482893b FL	37	struct regmap *regmap;
d482893b FL	38	int offset;
179a502f	39	int irq;
7f899399	40	struct clk *clk;
179a502f SG	41	};
179a502f SG	42
cd7f3a24 TP	43	/* Read 64 bit timer register, which could be in inconsistent state */
	44	static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
	45	{
	46	u32 msb, lsb;
	47
	48	regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
	49	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
	50	return (u64)msb << 32 \| lsb;
	51	}
	52
	53	/* Read the secure real time counter, taking care to deal with the cases of the
	54	* counter updating while being read.
	55	*/
d482893b	56	static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
179a502f SG	57	{
179a502f SG	58	u64 read1, read2;
cd7f3a24	59	unsigned int timeout = 100;
179a502f	60
cd7f3a24 TP	61	/* As expected, the registers might update between the read of the LSB
	62	* reg and the MSB reg. It's also possible that one register might be
	63	* in partially modified state as well.
	64	*/
	65	read1 = rtc_read_lpsrt(data);
179a502f	66	do {
cd7f3a24 TP	67	read2 = read1;
	68	read1 = rtc_read_lpsrt(data);
	69	} while (read1 != read2 && --timeout);
	70	if (!timeout)
	71	dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
179a502f SG	72
	73	/* Convert 47-bit counter to 32-bit raw second count */
	74	return (u32) (read1 >> CNTR_TO_SECS_SH);
	75	}
	76
cd7f3a24 TP	77	/* Just read the lsb from the counter, dealing with inconsistent state */
cd7f3a24 TP	78	static int rtc_read_lp_counter_lsb(struct snvs_rtc_data data, u32 lsb)
179a502f	79	{
cd7f3a24 TP	80	u32 count1, count2;
	81	unsigned int timeout = 100;
	82
	83	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	84	do {
	85	count2 = count1;
	86	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	87	} while (count1 != count2 && --timeout);
	88	if (!timeout) {
	89	dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
	90	return -ETIMEDOUT;
179a502f	91	}
cd7f3a24 TP	92
	93	*lsb = count1;
	94	return 0;
	95	}
	96
	97	static int rtc_write_sync_lp(struct snvs_rtc_data *data)
	98	{
	99	u32 count1, count2;
	100	u32 elapsed;
	101	unsigned int timeout = 1000;
	102	int ret;
	103
	104	ret = rtc_read_lp_counter_lsb(data, &count1);
	105	if (ret)
	106	return ret;
	107
	108	/* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
	109	do {
	110	ret = rtc_read_lp_counter_lsb(data, &count2);
	111	if (ret)
	112	return ret;
	113	elapsed = count2 - count1; /* wrap around _is_ handled! */
	114	} while (elapsed < 3 && --timeout);
	115	if (!timeout) {
	116	dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
	117	return -ETIMEDOUT;
	118	}
	119	return 0;
179a502f SG	120	}
	121
	122	static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
	123	{
179a502f SG	124	int timeout = 1000;
	125	u32 lpcr;
	126
d482893b FL	127	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
d482893b FL	128	enable ? SNVS_LPCR_SRTC_ENV : 0);
179a502f SG	129
179a502f SG	130	while (--timeout) {
d482893b	131	regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
179a502f SG	132
	133	if (enable) {
	134	if (lpcr & SNVS_LPCR_SRTC_ENV)
	135	break;
	136	} else {
	137	if (!(lpcr & SNVS_LPCR_SRTC_ENV))
	138	break;
	139	}
	140	}
	141
	142	if (!timeout)
	143	return -ETIMEDOUT;
	144
	145	return 0;
	146	}
	147
	148	static int snvs_rtc_read_time(struct device dev, struct rtc_time tm)
	149	{
	150	struct snvs_rtc_data *data = dev_get_drvdata(dev);
4b957bde AH	151	unsigned long time;
	152	int ret;
	153
081e2500 XW	154	ret = clk_enable(data->clk);
	155	if (ret)
	156	return ret;
179a502f	157
4b957bde	158	time = rtc_read_lp_counter(data);
c59a9fc7	159	rtc_time64_to_tm(time, tm);
179a502f	160
081e2500	161	clk_disable(data->clk);
4b957bde	162
179a502f SG	163	return 0;
	164	}
	165
	166	static int snvs_rtc_set_time(struct device dev, struct rtc_time tm)
	167	{
	168	struct snvs_rtc_data *data = dev_get_drvdata(dev);
c59a9fc7	169	unsigned long time = rtc_tm_to_time64(tm);
1485991c	170	int ret;
179a502f	171
081e2500 XW	172	ret = clk_enable(data->clk);
	173	if (ret)
	174	return ret;
4b957bde	175
179a502f	176	/* Disable RTC first */
1485991c BD	177	ret = snvs_rtc_enable(data, false);
	178	if (ret)
	179	return ret;
179a502f SG	180
179a502f SG	181	/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
d482893b FL	182	regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
d482893b FL	183	regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
179a502f SG	184
179a502f SG	185	/* Enable RTC again */
1485991c	186	ret = snvs_rtc_enable(data, true);
179a502f	187
081e2500	188	clk_disable(data->clk);
4b957bde	189
1485991c	190	return ret;
179a502f SG	191	}
	192
	193	static int snvs_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	194	{
	195	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	196	u32 lptar, lpsr;
4b957bde AH	197	int ret;
4b957bde AH	198
081e2500 XW	199	ret = clk_enable(data->clk);
	200	if (ret)
	201	return ret;
179a502f	202
d482893b	203	regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
c59a9fc7	204	rtc_time64_to_tm(lptar, &alrm->time);
179a502f	205
d482893b	206	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
179a502f SG	207	alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
179a502f SG	208
081e2500	209	clk_disable(data->clk);
4b957bde	210
179a502f SG	211	return 0;
	212	}
	213
	214	static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
	215	{
	216	struct snvs_rtc_data *data = dev_get_drvdata(dev);
4b957bde AH	217	int ret;
4b957bde AH	218
081e2500 XW	219	ret = clk_enable(data->clk);
	220	if (ret)
	221	return ret;
179a502f	222
d482893b FL	223	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
	224	(SNVS_LPCR_LPTA_EN \| SNVS_LPCR_LPWUI_EN),
	225	enable ? (SNVS_LPCR_LPTA_EN \| SNVS_LPCR_LPWUI_EN) : 0);
179a502f	226
4b957bde AH	227	ret = rtc_write_sync_lp(data);
4b957bde AH	228
081e2500	229	clk_disable(data->clk);
4b957bde AH	230
4b957bde AH	231	return ret;
179a502f SG	232	}
	233
	234	static int snvs_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	235	{
	236	struct snvs_rtc_data *data = dev_get_drvdata(dev);
c59a9fc7	237	unsigned long time = rtc_tm_to_time64(&alrm->time);
cd7f3a24	238	int ret;
179a502f	239
081e2500 XW	240	ret = clk_enable(data->clk);
	241	if (ret)
	242	return ret;
4b957bde	243
d482893b	244	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
cd7f3a24 TP	245	ret = rtc_write_sync_lp(data);
	246	if (ret)
	247	return ret;
d482893b	248	regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
179a502f SG	249
179a502f SG	250	/* Clear alarm interrupt status bit */
d482893b	251	regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
179a502f	252
081e2500	253	clk_disable(data->clk);
4b957bde	254
179a502f SG	255	return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
	256	}
	257
	258	static const struct rtc_class_ops snvs_rtc_ops = {
	259	.read_time = snvs_rtc_read_time,
	260	.set_time = snvs_rtc_set_time,
	261	.read_alarm = snvs_rtc_read_alarm,
	262	.set_alarm = snvs_rtc_set_alarm,
	263	.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
	264	};
	265
	266	static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
	267	{
	268	struct device *dev = dev_id;
	269	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	270	u32 lpsr;
	271	u32 events = 0;
	272
081e2500	273	clk_enable(data->clk);
edb190cb	274
d482893b	275	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
179a502f SG	276
	277	if (lpsr & SNVS_LPSR_LPTA) {
	278	events \|= (RTC_AF \| RTC_IRQF);
	279
	280	/* RTC alarm should be one-shot */
	281	snvs_rtc_alarm_irq_enable(dev, 0);
	282
	283	rtc_update_irq(data->rtc, 1, events);
	284	}
	285
	286	/* clear interrupt status */
d482893b	287	regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
179a502f	288
081e2500	289	clk_disable(data->clk);
edb190cb	290
179a502f SG	291	return events ? IRQ_HANDLED : IRQ_NONE;
	292	}
	293
d482893b FL	294	static const struct regmap_config snvs_rtc_config = {
	295	.reg_bits = 32,
	296	.val_bits = 32,
	297	.reg_stride = 4,
	298	};
	299
7863bd07 AH	300	static void snvs_rtc_action(void *data)
7863bd07 AH	301	{
081e2500	302	clk_disable_unprepare(data);
7863bd07 AH	303	}
7863bd07 AH	304
5a167f45	305	static int snvs_rtc_probe(struct platform_device *pdev)
179a502f SG	306	{
179a502f SG	307	struct snvs_rtc_data *data;
179a502f	308	int ret;
d482893b	309	void __iomem *mmio;
179a502f SG	310
	311	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	312	if (!data)
	313	return -ENOMEM;
	314
6fd4fe9b AH	315	data->rtc = devm_rtc_allocate_device(&pdev->dev);
	316	if (IS_ERR(data->rtc))
	317	return PTR_ERR(data->rtc);
	318
d482893b FL	319	data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
	320
	321	if (IS_ERR(data->regmap)) {
	322	dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
d482893b	323
0c46b07c	324	mmio = devm_platform_ioremap_resource(pdev, 0);
d482893b FL	325	if (IS_ERR(mmio))
	326	return PTR_ERR(mmio);
	327
	328	data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
	329	} else {
	330	data->offset = SNVS_LPREGISTER_OFFSET;
	331	of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
	332	}
	333
75892900	334	if (IS_ERR(data->regmap)) {
d482893b FL	335	dev_err(&pdev->dev, "Can't find snvs syscon\n");
	336	return -ENODEV;
	337	}
179a502f SG	338
	339	data->irq = platform_get_irq(pdev, 0);
	340	if (data->irq < 0)
	341	return data->irq;
	342
7f899399 SM	343	data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
	344	if (IS_ERR(data->clk)) {
	345	data->clk = NULL;
	346	} else {
	347	ret = clk_prepare_enable(data->clk);
	348	if (ret) {
	349	dev_err(&pdev->dev,
	350	"Could not prepare or enable the snvs clock\n");
	351	return ret;
	352	}
	353	}
	354
7863bd07 AH	355	ret = devm_add_action_or_reset(&pdev->dev, snvs_rtc_action, data->clk);
	356	if (ret)
	357	return ret;
	358
179a502f SG	359	platform_set_drvdata(pdev, data);
179a502f SG	360
179a502f	361	/* Initialize glitch detect */
d482893b	362	regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
179a502f SG	363
179a502f SG	364	/* Clear interrupt status */
d482893b	365	regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
179a502f SG	366
179a502f SG	367	/* Enable RTC */
1485991c BD	368	ret = snvs_rtc_enable(data, true);
	369	if (ret) {
	370	dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
7863bd07	371	return ret;
1485991c	372	}
179a502f SG	373
179a502f SG	374	device_init_wakeup(&pdev->dev, true);
e7afddb2 AH	375	ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
	376	if (ret)
	377	dev_err(&pdev->dev, "failed to enable irq wake\n");
179a502f SG	378
	379	ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
	380	IRQF_SHARED, "rtc alarm", &pdev->dev);
	381	if (ret) {
	382	dev_err(&pdev->dev, "failed to request irq %d: %d\n",
	383	data->irq, ret);
7863bd07	384	return ret;
179a502f SG	385	}
179a502f SG	386
6fd4fe9b	387	data->rtc->ops = &snvs_rtc_ops;
79610340	388	data->rtc->range_max = U32_MAX;
7f899399	389
fdcfd854	390	return devm_rtc_register_device(data->rtc);
179a502f SG	391	}
179a502f SG	392
dacb6a40	393	static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
119434f4 SA	394	{
	395	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	396
081e2500	397	clk_disable(data->clk);
7f899399	398
179a502f SG	399	return 0;
	400	}
	401
dacb6a40	402	static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
119434f4 SA	403	{
	404	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	405
	406	if (data->clk)
20af6770	407	return clk_enable(data->clk);
7f899399	408
179a502f SG	409	return 0;
179a502f SG	410	}
179a502f	411
7654e9d4	412	static const struct dev_pm_ops snvs_rtc_pm_ops = {
dacb6a40	413	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
7654e9d4	414	};
179a502f	415
5a167f45	416	static const struct of_device_id snvs_dt_ids[] = {
179a502f SG	417	{ .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
	418	{ /* sentinel */ }
	419	};
	420	MODULE_DEVICE_TABLE(of, snvs_dt_ids);
	421
	422	static struct platform_driver snvs_rtc_driver = {
	423	.driver = {
	424	.name = "snvs_rtc",
dacb6a40	425	.pm = &snvs_rtc_pm_ops,
c39b3717	426	.of_match_table = snvs_dt_ids,
179a502f SG	427	},
179a502f SG	428	.probe = snvs_rtc_probe,
179a502f SG	429	};
	430	module_platform_driver(snvs_rtc_driver);
	431
	432	MODULE_AUTHOR("Freescale Semiconductor, Inc.");
	433	MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
	434	MODULE_LICENSE("GPL");