[mirror_ubuntu-bionic-kernel.git] / drivers / rtc / rtc-stmp3xxx.c

/*
 * Freescale STMP37XX/STMP378X Real Time Clock driver
 *
 * Copyright (c) 2007 Sigmatel, Inc.
 * Peter Hartley, <peter.hartley@sigmatel.com>
 *
 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 * Copyright 2011 Wolfram Sang, Pengutronix e.K.
 */

/*
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/stmp_device.h>
#include <linux/stmp3xxx_rtc_wdt.h>

#define STMP3XXX_RTC_CTRL			0x0
#define STMP3XXX_RTC_CTRL_SET			0x4
#define STMP3XXX_RTC_CTRL_CLR			0x8
#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN		0x00000001
#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN	0x00000002
#define STMP3XXX_RTC_CTRL_ALARM_IRQ		0x00000004
#define STMP3XXX_RTC_CTRL_WATCHDOGEN		0x00000010

#define STMP3XXX_RTC_STAT			0x10
#define STMP3XXX_RTC_STAT_STALE_SHIFT		16
#define STMP3XXX_RTC_STAT_RTC_PRESENT		0x80000000

#define STMP3XXX_RTC_SECONDS			0x30

#define STMP3XXX_RTC_ALARM			0x40

#define STMP3XXX_RTC_WATCHDOG			0x50

#define STMP3XXX_RTC_PERSISTENT0		0x60
#define STMP3XXX_RTC_PERSISTENT0_SET		0x64
#define STMP3XXX_RTC_PERSISTENT0_CLR		0x68
#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN	0x00000002
#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN	0x00000004
#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE	0x00000080

#define STMP3XXX_RTC_PERSISTENT1		0x70
/* missing bitmask in headers */
#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER	0x80000000

struct stmp3xxx_rtc_data {
	struct rtc_device *rtc;
	void __iomem *io;
	int irq_alarm;
};

#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
/**
 * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
 * @dev: the parent device of the watchdog (= the RTC)
 * @timeout: the desired value for the timeout register of the watchdog.
 *           0 disables the watchdog
 *
 * The watchdog needs one register and two bits which are in the RTC domain.
 * To handle the resource conflict, the RTC driver will create another
 * platform_device for the watchdog driver as a child of the RTC device.
 * The watchdog driver is passed the below accessor function via platform_data
 * to configure the watchdog. Locking is not needed because accessing SET/CLR
 * registers is atomic.
 */

static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	if (timeout) {
		writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
		writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
		       rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
		writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
		       rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
	} else {
		writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
		       rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
		writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
		       rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
	}
}

static struct stmp3xxx_wdt_pdata wdt_pdata = {
	.wdt_set_timeout = stmp3xxx_wdt_set_timeout,
};

static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
{
	struct platform_device *wdt_pdev =
		platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);

	if (wdt_pdev) {
		wdt_pdev->dev.parent = &rtc_pdev->dev;
		wdt_pdev->dev.platform_data = &wdt_pdata;
		platform_device_add(wdt_pdev);
	}
}
#else
static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
{
}
#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */

static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
{
	int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
	/*
	 * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
	 * states:
	 * | The order in which registers are updated is
	 * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
	 * | (This list is in bitfield order, from LSB to MSB, as they would
	 * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
	 * | register. For example, the Seconds register corresponds to
	 * | STALE_REGS or NEW_REGS containing 0x80.)
	 */
	do {
		if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
				(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
			return 0;
		udelay(1);
	} while (--timeout > 0);
	return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
		(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
}

/* Time read/write */
static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
{
	int ret;
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	ret = stmp3xxx_wait_time(rtc_data);
	if (ret)
		return ret;

	rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
	return 0;
}

static int stmp3xxx_rtc_set_mmss(struct device *dev, unsigned long t)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	writel(t, rtc_data->io + STMP3XXX_RTC_SECONDS);
	return stmp3xxx_wait_time(rtc_data);
}

/* interrupt(s) handler */
static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
	u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);

	if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
				rtc_data->io + STMP3XXX_RTC_CTRL_CLR);
		rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	if (enabled) {
		writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
				STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
				rtc_data->io + STMP3XXX_RTC_PERSISTENT0_SET);
		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
				rtc_data->io + STMP3XXX_RTC_CTRL_SET);
	} else {
		writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
				STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
				rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR);
		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
				rtc_data->io + STMP3XXX_RTC_CTRL_CLR);
	}
	return 0;
}

static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
	return 0;
}

static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	unsigned long t;
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	rtc_tm_to_time(&alm->time, &t);
	writel(t, rtc_data->io + STMP3XXX_RTC_ALARM);

	stmp3xxx_alarm_irq_enable(dev, alm->enabled);

	return 0;
}

static struct rtc_class_ops stmp3xxx_rtc_ops = {
	.alarm_irq_enable =
			  stmp3xxx_alarm_irq_enable,
	.read_time	= stmp3xxx_rtc_gettime,
	.set_mmss	= stmp3xxx_rtc_set_mmss,
	.read_alarm	= stmp3xxx_rtc_read_alarm,
	.set_alarm	= stmp3xxx_rtc_set_alarm,
};

static int stmp3xxx_rtc_remove(struct platform_device *pdev)
{
	struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);

	if (!rtc_data)
		return 0;

	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
			rtc_data->io + STMP3XXX_RTC_CTRL_CLR);

	return 0;
}

static int stmp3xxx_rtc_probe(struct platform_device *pdev)
{
	struct stmp3xxx_rtc_data *rtc_data;
	struct resource *r;
	int err;

	rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
	if (!rtc_data)
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		dev_err(&pdev->dev, "failed to get resource\n");
		return -ENXIO;
	}

	rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
	if (!rtc_data->io) {
		dev_err(&pdev->dev, "ioremap failed\n");
		return -EIO;
	}

	rtc_data->irq_alarm = platform_get_irq(pdev, 0);

	if (!(readl(STMP3XXX_RTC_STAT + rtc_data->io) &
			STMP3XXX_RTC_STAT_RTC_PRESENT)) {
		dev_err(&pdev->dev, "no device onboard\n");
		return -ENODEV;
	}

	platform_set_drvdata(pdev, rtc_data);

	err = stmp_reset_block(rtc_data->io);
	if (err) {
		dev_err(&pdev->dev, "stmp_reset_block failed: %d\n", err);
		return err;
	}

	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
			rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR);

	writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
			STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
			rtc_data->io + STMP3XXX_RTC_CTRL_CLR);

	rtc_data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
				&stmp3xxx_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc_data->rtc))
		return PTR_ERR(rtc_data->rtc);

	err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
			stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
	if (err) {
		dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
			rtc_data->irq_alarm);
		return err;
	}

	stmp3xxx_wdt_register(pdev);
	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int stmp3xxx_rtc_suspend(struct device *dev)
{
	return 0;
}

static int stmp3xxx_rtc_resume(struct device *dev)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	stmp_reset_block(rtc_data->io);
	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
			rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR);
	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
			stmp3xxx_rtc_resume);

static const struct of_device_id rtc_dt_ids[] = {
	{ .compatible = "fsl,stmp3xxx-rtc", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rtc_dt_ids);

static struct platform_driver stmp3xxx_rtcdrv = {
	.probe		= stmp3xxx_rtc_probe,
	.remove		= stmp3xxx_rtc_remove,
	.driver		= {
		.name	= "stmp3xxx-rtc",
		.owner	= THIS_MODULE,
		.pm	= &stmp3xxx_rtc_pm_ops,
		.of_match_table = of_match_ptr(rtc_dt_ids),
	},
};

module_platform_driver(stmp3xxx_rtcdrv);

MODULE_DESCRIPTION("STMP3xxx RTC Driver");
MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
		"Wolfram Sang <w.sang@pengutronix.de>");
MODULE_LICENSE("GPL");
Commit	Line	Data
df17f631	1	/*
	2	* Freescale STMP37XX/STMP378X Real Time Clock driver
	3	*
	4	* Copyright (c) 2007 Sigmatel, Inc.
	5	* Peter Hartley, <peter.hartley@sigmatel.com>
	6	*
	7	* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
	8	* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
7e794cb7	9	* Copyright 2011 Wolfram Sang, Pengutronix e.K.
df17f631	10	*/
	11
	12	/*
	13	* The code contained herein is licensed under the GNU General Public
	14	* License. You may obtain a copy of the GNU General Public License
	15	* Version 2 or later at the following locations:
	16	*
	17	* http://www.opensource.org/licenses/gpl-license.html
	18	* http://www.gnu.org/copyleft/gpl.html
	19	*/
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
b5167159	22	#include <linux/io.h>
df17f631	23	#include <linux/init.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/interrupt.h>
28a0c883	26	#include <linux/delay.h>
df17f631	27	#include <linux/rtc.h>
5a0e3ad6	28	#include <linux/slab.h>
dd8d20a3	29	#include <linux/of_device.h>
c8a6046e	30	#include <linux/of.h>
1a71fb84 WS	31	#include <linux/stmp_device.h>
1a71fb84 WS	32	#include <linux/stmp3xxx_rtc_wdt.h>
df17f631	33
47eac337	34	#define STMP3XXX_RTC_CTRL 0x0
b5167159 WS	35	#define STMP3XXX_RTC_CTRL_SET 0x4
b5167159 WS	36	#define STMP3XXX_RTC_CTRL_CLR 0x8
47eac337 WS	37	#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001
	38	#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
	39	#define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004
1a71fb84	40	#define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010
47eac337 WS	41
	42	#define STMP3XXX_RTC_STAT 0x10
	43	#define STMP3XXX_RTC_STAT_STALE_SHIFT 16
	44	#define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000
	45
	46	#define STMP3XXX_RTC_SECONDS 0x30
	47
	48	#define STMP3XXX_RTC_ALARM 0x40
	49
1a71fb84 WS	50	#define STMP3XXX_RTC_WATCHDOG 0x50
1a71fb84 WS	51
47eac337	52	#define STMP3XXX_RTC_PERSISTENT0 0x60
b5167159 WS	53	#define STMP3XXX_RTC_PERSISTENT0_SET 0x64
b5167159 WS	54	#define STMP3XXX_RTC_PERSISTENT0_CLR 0x68
47eac337 WS	55	#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
	56	#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN 0x00000004
	57	#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
df17f631	58
1a71fb84 WS	59	#define STMP3XXX_RTC_PERSISTENT1 0x70
	60	/* missing bitmask in headers */
	61	#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000
	62
df17f631	63	struct stmp3xxx_rtc_data {
df17f631	64	struct rtc_device *rtc;
df17f631	65	void __iomem *io;
7e794cb7	66	int irq_alarm;
df17f631	67	};
df17f631	68
1a71fb84 WS	69	#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
	70	/**
	71	* stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
	72	* @dev: the parent device of the watchdog (= the RTC)
	73	* @timeout: the desired value for the timeout register of the watchdog.
	74	* 0 disables the watchdog
	75	*
	76	* The watchdog needs one register and two bits which are in the RTC domain.
	77	* To handle the resource conflict, the RTC driver will create another
	78	* platform_device for the watchdog driver as a child of the RTC device.
	79	* The watchdog driver is passed the below accessor function via platform_data
	80	* to configure the watchdog. Locking is not needed because accessing SET/CLR
	81	* registers is atomic.
	82	*/
	83
	84	static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
	85	{
	86	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	87
	88	if (timeout) {
	89	writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
	90	writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
	91	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
	92	writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
	93	rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
	94	} else {
	95	writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
	96	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
	97	writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
	98	rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
	99	}
	100	}
	101
	102	static struct stmp3xxx_wdt_pdata wdt_pdata = {
	103	.wdt_set_timeout = stmp3xxx_wdt_set_timeout,
	104	};
	105
	106	static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
	107	{
	108	struct platform_device *wdt_pdev =
	109	platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
	110
	111	if (wdt_pdev) {
	112	wdt_pdev->dev.parent = &rtc_pdev->dev;
	113	wdt_pdev->dev.platform_data = &wdt_pdata;
	114	platform_device_add(wdt_pdev);
	115	}
	116	}
	117	#else
	118	static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
	119	{
	120	}
	121	#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
	122
28a0c883	123	static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
df17f631	124	{
28a0c883	125	int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
df17f631	126	/*
28a0c883 LW	127	* The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
	128	* states:
	129	* \| The order in which registers are updated is
	130	* \| Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
	131	* \| (This list is in bitfield order, from LSB to MSB, as they would
	132	* \| appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
	133	* \| register. For example, the Seconds register corresponds to
	134	* \| STALE_REGS or NEW_REGS containing 0x80.)
df17f631	135	*/
28a0c883 LW	136	do {
	137	if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
	138	(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
	139	return 0;
	140	udelay(1);
	141	} while (--timeout > 0);
	142	return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
	143	(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
df17f631	144	}
	145
	146	/* Time read/write */
	147	static int stmp3xxx_rtc_gettime(struct device dev, struct rtc_time rtc_tm)
	148	{
28a0c883	149	int ret;
df17f631	150	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	151
28a0c883 LW	152	ret = stmp3xxx_wait_time(rtc_data);
	153	if (ret)
	154	return ret;
	155
b5167159	156	rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
df17f631	157	return 0;
	158	}
	159
	160	static int stmp3xxx_rtc_set_mmss(struct device *dev, unsigned long t)
	161	{
	162	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	163
b5167159	164	writel(t, rtc_data->io + STMP3XXX_RTC_SECONDS);
28a0c883	165	return stmp3xxx_wait_time(rtc_data);
df17f631	166	}
	167
	168	/* interrupt(s) handler */
	169	static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
	170	{
	171	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
7e794cb7	172	u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
df17f631	173
47eac337	174	if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
b5167159 WS	175	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
b5167159 WS	176	rtc_data->io + STMP3XXX_RTC_CTRL_CLR);
7e794cb7 WS	177	rtc_update_irq(rtc_data->rtc, 1, RTC_AF \| RTC_IRQF);
7e794cb7 WS	178	return IRQ_HANDLED;
df17f631	179	}
df17f631	180
7e794cb7	181	return IRQ_NONE;
df17f631	182	}
	183
	184	static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
	185	{
	186	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	187
df17f631	188	if (enabled) {
b5167159 WS	189	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
	190	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
	191	rtc_data->io + STMP3XXX_RTC_PERSISTENT0_SET);
	192	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
	193	rtc_data->io + STMP3XXX_RTC_CTRL_SET);
df17f631	194	} else {
b5167159 WS	195	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
	196	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
	197	rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR);
	198	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
	199	rtc_data->io + STMP3XXX_RTC_CTRL_CLR);
df17f631	200	}
	201	return 0;
	202	}
	203
df17f631	204	static int stmp3xxx_rtc_read_alarm(struct device dev, struct rtc_wkalrm alm)
	205	{
	206	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	207
b5167159	208	rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
df17f631	209	return 0;
	210	}
	211
	212	static int stmp3xxx_rtc_set_alarm(struct device dev, struct rtc_wkalrm alm)
	213	{
	214	unsigned long t;
	215	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	216
	217	rtc_tm_to_time(&alm->time, &t);
b5167159	218	writel(t, rtc_data->io + STMP3XXX_RTC_ALARM);
7e794cb7 WS	219
	220	stmp3xxx_alarm_irq_enable(dev, alm->enabled);
	221
df17f631	222	return 0;
	223	}
	224
	225	static struct rtc_class_ops stmp3xxx_rtc_ops = {
	226	.alarm_irq_enable =
	227	stmp3xxx_alarm_irq_enable,
df17f631	228	.read_time = stmp3xxx_rtc_gettime,
	229	.set_mmss = stmp3xxx_rtc_set_mmss,
	230	.read_alarm = stmp3xxx_rtc_read_alarm,
	231	.set_alarm = stmp3xxx_rtc_set_alarm,
	232	};
	233
	234	static int stmp3xxx_rtc_remove(struct platform_device *pdev)
	235	{
	236	struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
	237
	238	if (!rtc_data)
	239	return 0;
	240
7e794cb7	241	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
b5167159	242	rtc_data->io + STMP3XXX_RTC_CTRL_CLR);
df17f631	243
	244	return 0;
	245	}
	246
	247	static int stmp3xxx_rtc_probe(struct platform_device *pdev)
	248	{
	249	struct stmp3xxx_rtc_data *rtc_data;
	250	struct resource *r;
	251	int err;
	252
87a81420	253	rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
df17f631	254	if (!rtc_data)
	255	return -ENOMEM;
	256
	257	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	258	if (!r) {
	259	dev_err(&pdev->dev, "failed to get resource\n");
87a81420	260	return -ENXIO;
df17f631	261	}
df17f631	262
87a81420	263	rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
df17f631	264	if (!rtc_data->io) {
df17f631	265	dev_err(&pdev->dev, "ioremap failed\n");
87a81420	266	return -EIO;
df17f631	267	}
	268
	269	rtc_data->irq_alarm = platform_get_irq(pdev, 0);
df17f631	270
b5167159	271	if (!(readl(STMP3XXX_RTC_STAT + rtc_data->io) &
47eac337	272	STMP3XXX_RTC_STAT_RTC_PRESENT)) {
df17f631	273	dev_err(&pdev->dev, "no device onboard\n");
87a81420	274	return -ENODEV;
df17f631	275	}
df17f631	276
a91d2bab WS	277	platform_set_drvdata(pdev, rtc_data);
a91d2bab WS	278
4e80b188 FE	279	err = stmp_reset_block(rtc_data->io);
	280	if (err) {
	281	dev_err(&pdev->dev, "stmp_reset_block failed: %d\n", err);
	282	return err;
	283	}
	284
b5167159	285	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
47eac337 WS	286	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN \|
47eac337 WS	287	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
b5167159	288	rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR);
a91d2bab	289
7e794cb7 WS	290	writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN \|
	291	STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
	292	rtc_data->io + STMP3XXX_RTC_CTRL_CLR);
	293
87a81420	294	rtc_data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
df17f631	295	&stmp3xxx_rtc_ops, THIS_MODULE);
dfd2a178 JH	296	if (IS_ERR(rtc_data->rtc))
dfd2a178 JH	297	return PTR_ERR(rtc_data->rtc);
df17f631	298
87a81420 JH	299	err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
87a81420 JH	300	stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
df17f631	301	if (err) {
	302	dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
	303	rtc_data->irq_alarm);
dfd2a178	304	return err;
df17f631	305	}
df17f631	306
1a71fb84	307	stmp3xxx_wdt_register(pdev);
df17f631	308	return 0;
df17f631	309	}
df17f631	310
ef69a7f0 JH	311	#ifdef CONFIG_PM_SLEEP
ef69a7f0 JH	312	static int stmp3xxx_rtc_suspend(struct device *dev)
df17f631	313	{
	314	return 0;
	315	}
	316
ef69a7f0	317	static int stmp3xxx_rtc_resume(struct device *dev)
df17f631	318	{
ef69a7f0	319	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	320
36d1da1d	321	stmp_reset_block(rtc_data->io);
b5167159	322	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
47eac337 WS	323	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN \|
47eac337 WS	324	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
b5167159	325	rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR);
df17f631	326	return 0;
df17f631	327	}
df17f631	328	#endif
df17f631	329
ef69a7f0 JH	330	static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
	331	stmp3xxx_rtc_resume);
	332
dd8d20a3 MV	333	static const struct of_device_id rtc_dt_ids[] = {
	334	{ .compatible = "fsl,stmp3xxx-rtc", },
	335	{ /* sentinel */ }
	336	};
	337	MODULE_DEVICE_TABLE(of, rtc_dt_ids);
	338
df17f631	339	static struct platform_driver stmp3xxx_rtcdrv = {
	340	.probe = stmp3xxx_rtc_probe,
	341	.remove = stmp3xxx_rtc_remove,
df17f631	342	.driver = {
	343	.name = "stmp3xxx-rtc",
	344	.owner = THIS_MODULE,
ef69a7f0	345	.pm = &stmp3xxx_rtc_pm_ops,
c8a6046e	346	.of_match_table = of_match_ptr(rtc_dt_ids),
df17f631	347	},
	348	};
	349
0c4eae66	350	module_platform_driver(stmp3xxx_rtcdrv);
df17f631	351
df17f631	352	MODULE_DESCRIPTION("STMP3xxx RTC Driver");
7e794cb7 WS	353	MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
7e794cb7 WS	354	"Wolfram Sang <w.sang@pengutronix.de>");
df17f631	355	MODULE_LICENSE("GPL");