[mirror_ubuntu-bionic-kernel.git] / drivers / rtc / rtc-sun6i.c

/*
 * An RTC driver for Allwinner A31/A23
 *
 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
 *
 * based on rtc-sunxi.c
 *
 * An RTC driver for Allwinner A10/A20
 *
 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/types.h>

/* Control register */
#define SUN6I_LOSC_CTRL				0x0000
#define SUN6I_LOSC_CTRL_KEY			(0x16aa << 16)
#define SUN6I_LOSC_CTRL_ALM_DHMS_ACC		BIT(9)
#define SUN6I_LOSC_CTRL_RTC_HMS_ACC		BIT(8)
#define SUN6I_LOSC_CTRL_RTC_YMD_ACC		BIT(7)
#define SUN6I_LOSC_CTRL_EXT_OSC			BIT(0)
#define SUN6I_LOSC_CTRL_ACC_MASK		GENMASK(9, 7)

#define SUN6I_LOSC_CLK_PRESCAL			0x0008

/* RTC */
#define SUN6I_RTC_YMD				0x0010
#define SUN6I_RTC_HMS				0x0014

/* Alarm 0 (counter) */
#define SUN6I_ALRM_COUNTER			0x0020
#define SUN6I_ALRM_CUR_VAL			0x0024
#define SUN6I_ALRM_EN				0x0028
#define SUN6I_ALRM_EN_CNT_EN			BIT(0)
#define SUN6I_ALRM_IRQ_EN			0x002c
#define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN		BIT(0)
#define SUN6I_ALRM_IRQ_STA			0x0030
#define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND		BIT(0)

/* Alarm 1 (wall clock) */
#define SUN6I_ALRM1_EN				0x0044
#define SUN6I_ALRM1_IRQ_EN			0x0048
#define SUN6I_ALRM1_IRQ_STA			0x004c
#define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND	BIT(0)

/* Alarm config */
#define SUN6I_ALARM_CONFIG			0x0050
#define SUN6I_ALARM_CONFIG_WAKEUP		BIT(0)

#define SUN6I_LOSC_OUT_GATING			0x0060
#define SUN6I_LOSC_OUT_GATING_EN_OFFSET		0

/*
 * Get date values
 */
#define SUN6I_DATE_GET_DAY_VALUE(x)		((x)  & 0x0000001f)
#define SUN6I_DATE_GET_MON_VALUE(x)		(((x) & 0x00000f00) >> 8)
#define SUN6I_DATE_GET_YEAR_VALUE(x)		(((x) & 0x003f0000) >> 16)
#define SUN6I_LEAP_GET_VALUE(x)			(((x) & 0x00400000) >> 22)

/*
 * Get time values
 */
#define SUN6I_TIME_GET_SEC_VALUE(x)		((x)  & 0x0000003f)
#define SUN6I_TIME_GET_MIN_VALUE(x)		(((x) & 0x00003f00) >> 8)
#define SUN6I_TIME_GET_HOUR_VALUE(x)		(((x) & 0x001f0000) >> 16)

/*
 * Set date values
 */
#define SUN6I_DATE_SET_DAY_VALUE(x)		((x)       & 0x0000001f)
#define SUN6I_DATE_SET_MON_VALUE(x)		((x) <<  8 & 0x00000f00)
#define SUN6I_DATE_SET_YEAR_VALUE(x)		((x) << 16 & 0x003f0000)
#define SUN6I_LEAP_SET_VALUE(x)			((x) << 22 & 0x00400000)

/*
 * Set time values
 */
#define SUN6I_TIME_SET_SEC_VALUE(x)		((x)       & 0x0000003f)
#define SUN6I_TIME_SET_MIN_VALUE(x)		((x) <<  8 & 0x00003f00)
#define SUN6I_TIME_SET_HOUR_VALUE(x)		((x) << 16 & 0x001f0000)

/*
 * The year parameter passed to the driver is usually an offset relative to
 * the year 1900. This macro is used to convert this offset to another one
 * relative to the minimum year allowed by the hardware.
 *
 * The year range is 1970 - 2033. This range is selected to match Allwinner's
 * driver, even though it is somewhat limited.
 */
#define SUN6I_YEAR_MIN				1970
#define SUN6I_YEAR_MAX				2033
#define SUN6I_YEAR_OFF				(SUN6I_YEAR_MIN - 1900)

struct sun6i_rtc_dev {
	struct rtc_device *rtc;
	struct device *dev;
	void __iomem *base;
	int irq;
	unsigned long alarm;

	struct clk_hw hw;
	struct clk_hw *int_osc;
	struct clk *losc;
	struct clk *ext_losc;

	spinlock_t lock;
};

static struct sun6i_rtc_dev *sun6i_rtc;

static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
					       unsigned long parent_rate)
{
	struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
	u32 val;

	val = readl(rtc->base + SUN6I_LOSC_CTRL);
	if (val & SUN6I_LOSC_CTRL_EXT_OSC)
		return parent_rate;

	val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
	val &= GENMASK(4, 0);

	return parent_rate / (val + 1);
}

static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
{
	struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);

	return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
}

static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
{
	struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
	unsigned long flags;
	u32 val;

	if (index > 1)
		return -EINVAL;

	spin_lock_irqsave(&rtc->lock, flags);
	val = readl(rtc->base + SUN6I_LOSC_CTRL);
	val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
	val |= SUN6I_LOSC_CTRL_KEY;
	val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
	writel(val, rtc->base + SUN6I_LOSC_CTRL);
	spin_unlock_irqrestore(&rtc->lock, flags);

	return 0;
}

static const struct clk_ops sun6i_rtc_osc_ops = {
	.recalc_rate	= sun6i_rtc_osc_recalc_rate,

	.get_parent	= sun6i_rtc_osc_get_parent,
	.set_parent	= sun6i_rtc_osc_set_parent,
};

static void __init sun6i_rtc_clk_init(struct device_node *node)
{
	struct clk_hw_onecell_data *clk_data;
	struct sun6i_rtc_dev *rtc;
	struct clk_init_data init = {
		.ops		= &sun6i_rtc_osc_ops,
	};
	const char *clkout_name = "osc32k-out";
	const char *parents[2];

	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
	if (!rtc)
		return;

	clk_data = kzalloc(sizeof(*clk_data) + (sizeof(*clk_data->hws) * 2),
			   GFP_KERNEL);
	if (!clk_data)
		return;

	spin_lock_init(&rtc->lock);

	rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
	if (IS_ERR(rtc->base)) {
		pr_crit("Can't map RTC registers");
		goto err;
	}

	/* Switch to the external, more precise, oscillator */
	writel(SUN6I_LOSC_CTRL_KEY | SUN6I_LOSC_CTRL_EXT_OSC,
	       rtc->base + SUN6I_LOSC_CTRL);

	/* Yes, I know, this is ugly. */
	sun6i_rtc = rtc;

	/* Deal with old DTs */
	if (!of_get_property(node, "clocks", NULL))
		goto err;

	rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
								"rtc-int-osc",
								NULL, 0,
								667000,
								300000000);
	if (IS_ERR(rtc->int_osc)) {
		pr_crit("Couldn't register the internal oscillator\n");
		return;
	}

	parents[0] = clk_hw_get_name(rtc->int_osc);
	parents[1] = of_clk_get_parent_name(node, 0);

	rtc->hw.init = &init;

	init.parent_names = parents;
	init.num_parents = of_clk_get_parent_count(node) + 1;
	of_property_read_string_index(node, "clock-output-names", 0,
				      &init.name);

	rtc->losc = clk_register(NULL, &rtc->hw);
	if (IS_ERR(rtc->losc)) {
		pr_crit("Couldn't register the LOSC clock\n");
		return;
	}

	of_property_read_string_index(node, "clock-output-names", 1,
				      &clkout_name);
	rtc->ext_losc = clk_register_gate(NULL, clkout_name, rtc->hw.init->name,
					  0, rtc->base + SUN6I_LOSC_OUT_GATING,
					  SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
					  &rtc->lock);
	if (IS_ERR(rtc->ext_losc)) {
		pr_crit("Couldn't register the LOSC external gate\n");
		return;
	}

	clk_data->num = 2;
	clk_data->hws[0] = &rtc->hw;
	clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
	of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
	return;

err:
	kfree(clk_data);
}
CLK_OF_DECLARE_DRIVER(sun6i_rtc_clk, "allwinner,sun6i-a31-rtc",
		      sun6i_rtc_clk_init);

static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
{
	struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
	irqreturn_t ret = IRQ_NONE;
	u32 val;

	spin_lock(&chip->lock);
	val = readl(chip->base + SUN6I_ALRM_IRQ_STA);

	if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
		val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
		writel(val, chip->base + SUN6I_ALRM_IRQ_STA);

		rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);

		ret = IRQ_HANDLED;
	}
	spin_unlock(&chip->lock);

	return ret;
}

static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
{
	u32 alrm_val = 0;
	u32 alrm_irq_val = 0;
	u32 alrm_wake_val = 0;
	unsigned long flags;

	if (to) {
		alrm_val = SUN6I_ALRM_EN_CNT_EN;
		alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
		alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
	} else {
		writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
		       chip->base + SUN6I_ALRM_IRQ_STA);
	}

	spin_lock_irqsave(&chip->lock, flags);
	writel(alrm_val, chip->base + SUN6I_ALRM_EN);
	writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
	writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
	spin_unlock_irqrestore(&chip->lock, flags);
}

static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
{
	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
	u32 date, time;

	/*
	 * read again in case it changes
	 */
	do {
		date = readl(chip->base + SUN6I_RTC_YMD);
		time = readl(chip->base + SUN6I_RTC_HMS);
	} while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
		 (time != readl(chip->base + SUN6I_RTC_HMS)));

	rtc_tm->tm_sec  = SUN6I_TIME_GET_SEC_VALUE(time);
	rtc_tm->tm_min  = SUN6I_TIME_GET_MIN_VALUE(time);
	rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);

	rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
	rtc_tm->tm_mon  = SUN6I_DATE_GET_MON_VALUE(date);
	rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);

	rtc_tm->tm_mon  -= 1;

	/*
	 * switch from (data_year->min)-relative offset to
	 * a (1900)-relative one
	 */
	rtc_tm->tm_year += SUN6I_YEAR_OFF;

	return rtc_valid_tm(rtc_tm);
}

static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
	unsigned long flags;
	u32 alrm_st;
	u32 alrm_en;

	spin_lock_irqsave(&chip->lock, flags);
	alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
	alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
	spin_unlock_irqrestore(&chip->lock, flags);

	wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
	wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
	rtc_time_to_tm(chip->alarm, &wkalrm->time);

	return 0;
}

static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
	struct rtc_time *alrm_tm = &wkalrm->time;
	struct rtc_time tm_now;
	unsigned long time_now = 0;
	unsigned long time_set = 0;
	unsigned long time_gap = 0;
	int ret = 0;

	ret = sun6i_rtc_gettime(dev, &tm_now);
	if (ret < 0) {
		dev_err(dev, "Error in getting time\n");
		return -EINVAL;
	}

	rtc_tm_to_time(alrm_tm, &time_set);
	rtc_tm_to_time(&tm_now, &time_now);
	if (time_set <= time_now) {
		dev_err(dev, "Date to set in the past\n");
		return -EINVAL;
	}

	time_gap = time_set - time_now;

	if (time_gap > U32_MAX) {
		dev_err(dev, "Date too far in the future\n");
		return -EINVAL;
	}

	sun6i_rtc_setaie(0, chip);
	writel(0, chip->base + SUN6I_ALRM_COUNTER);
	usleep_range(100, 300);

	writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
	chip->alarm = time_set;

	sun6i_rtc_setaie(wkalrm->enabled, chip);

	return 0;
}

static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
			  unsigned int mask, unsigned int ms_timeout)
{
	const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
	u32 reg;

	do {
		reg = readl(chip->base + offset);
		reg &= mask;

		if (!reg)
			return 0;

	} while (time_before(jiffies, timeout));

	return -ETIMEDOUT;
}

static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
{
	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
	u32 date = 0;
	u32 time = 0;
	int year;

	year = rtc_tm->tm_year + 1900;
	if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) {
		dev_err(dev, "rtc only supports year in range %d - %d\n",
			SUN6I_YEAR_MIN, SUN6I_YEAR_MAX);
		return -EINVAL;
	}

	rtc_tm->tm_year -= SUN6I_YEAR_OFF;
	rtc_tm->tm_mon += 1;

	date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
		SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon)  |
		SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);

	if (is_leap_year(year))
		date |= SUN6I_LEAP_SET_VALUE(1);

	time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec)  |
		SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min)  |
		SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);

	/* Check whether registers are writable */
	if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
			   SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
		dev_err(dev, "rtc is still busy.\n");
		return -EBUSY;
	}

	writel(time, chip->base + SUN6I_RTC_HMS);

	/*
	 * After writing the RTC HH-MM-SS register, the
	 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
	 * be cleared until the real writing operation is finished
	 */

	if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
			   SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
		dev_err(dev, "Failed to set rtc time.\n");
		return -ETIMEDOUT;
	}

	writel(date, chip->base + SUN6I_RTC_YMD);

	/*
	 * After writing the RTC YY-MM-DD register, the
	 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
	 * be cleared until the real writing operation is finished
	 */

	if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
			   SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
		dev_err(dev, "Failed to set rtc time.\n");
		return -ETIMEDOUT;
	}

	return 0;
}

static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);

	if (!enabled)
		sun6i_rtc_setaie(enabled, chip);

	return 0;
}

static const struct rtc_class_ops sun6i_rtc_ops = {
	.read_time		= sun6i_rtc_gettime,
	.set_time		= sun6i_rtc_settime,
	.read_alarm		= sun6i_rtc_getalarm,
	.set_alarm		= sun6i_rtc_setalarm,
	.alarm_irq_enable	= sun6i_rtc_alarm_irq_enable
};

static int sun6i_rtc_probe(struct platform_device *pdev)
{
	struct sun6i_rtc_dev *chip = sun6i_rtc;
	int ret;

	if (!chip)
		return -ENODEV;

	platform_set_drvdata(pdev, chip);
	chip->dev = &pdev->dev;

	chip->irq = platform_get_irq(pdev, 0);
	if (chip->irq < 0) {
		dev_err(&pdev->dev, "No IRQ resource\n");
		return chip->irq;
	}

	ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
			       0, dev_name(&pdev->dev), chip);
	if (ret) {
		dev_err(&pdev->dev, "Could not request IRQ\n");
		return ret;
	}

	/* clear the alarm counter value */
	writel(0, chip->base + SUN6I_ALRM_COUNTER);

	/* disable counter alarm */
	writel(0, chip->base + SUN6I_ALRM_EN);

	/* disable counter alarm interrupt */
	writel(0, chip->base + SUN6I_ALRM_IRQ_EN);

	/* disable week alarm */
	writel(0, chip->base + SUN6I_ALRM1_EN);

	/* disable week alarm interrupt */
	writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);

	/* clear counter alarm pending interrupts */
	writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
	       chip->base + SUN6I_ALRM_IRQ_STA);

	/* clear week alarm pending interrupts */
	writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
	       chip->base + SUN6I_ALRM1_IRQ_STA);

	/* disable alarm wakeup */
	writel(0, chip->base + SUN6I_ALARM_CONFIG);

	clk_prepare_enable(chip->losc);

	chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-sun6i",
					     &sun6i_rtc_ops, THIS_MODULE);
	if (IS_ERR(chip->rtc)) {
		dev_err(&pdev->dev, "unable to register device\n");
		return PTR_ERR(chip->rtc);
	}

	dev_info(&pdev->dev, "RTC enabled\n");

	return 0;
}

static const struct of_device_id sun6i_rtc_dt_ids[] = {
	{ .compatible = "allwinner,sun6i-a31-rtc" },
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);

static struct platform_driver sun6i_rtc_driver = {
	.probe		= sun6i_rtc_probe,
	.driver		= {
		.name		= "sun6i-rtc",
		.of_match_table = sun6i_rtc_dt_ids,
	},
};
builtin_platform_driver(sun6i_rtc_driver);
Commit	Line	Data
9765d2d9 CYT	1	/*
	2	* An RTC driver for Allwinner A31/A23
	3	*
	4	* Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
	5	*
	6	* based on rtc-sunxi.c
	7	*
	8	* An RTC driver for Allwinner A10/A20
	9	*
	10	* Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2 of the License, or
	15	* (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful, but WITHOUT
	18	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	19	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	20	* more details.
	21	*/
	22
3855c2c3 MR	23	#include <linux/clk.h>
3855c2c3 MR	24	#include <linux/clk-provider.h>
9765d2d9 CYT	25	#include <linux/delay.h>
	26	#include <linux/err.h>
	27	#include <linux/fs.h>
	28	#include <linux/init.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/io.h>
	31	#include <linux/kernel.h>
	32	#include <linux/module.h>
	33	#include <linux/of.h>
	34	#include <linux/of_address.h>
	35	#include <linux/of_device.h>
	36	#include <linux/platform_device.h>
	37	#include <linux/rtc.h>
3855c2c3	38	#include <linux/slab.h>
9765d2d9 CYT	39	#include <linux/types.h>
	40
	41	/* Control register */
	42	#define SUN6I_LOSC_CTRL 0x0000
fb61bb82	43	#define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
9765d2d9 CYT	44	#define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9)
	45	#define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8)
	46	#define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7)
fb61bb82	47	#define SUN6I_LOSC_CTRL_EXT_OSC BIT(0)
9765d2d9 CYT	48	#define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)
9765d2d9 CYT	49
3855c2c3 MR	50	#define SUN6I_LOSC_CLK_PRESCAL 0x0008
3855c2c3 MR	51
9765d2d9 CYT	52	/* RTC */
	53	#define SUN6I_RTC_YMD 0x0010
	54	#define SUN6I_RTC_HMS 0x0014
	55
	56	/* Alarm 0 (counter) */
	57	#define SUN6I_ALRM_COUNTER 0x0020
	58	#define SUN6I_ALRM_CUR_VAL 0x0024
	59	#define SUN6I_ALRM_EN 0x0028
	60	#define SUN6I_ALRM_EN_CNT_EN BIT(0)
	61	#define SUN6I_ALRM_IRQ_EN 0x002c
	62	#define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
	63	#define SUN6I_ALRM_IRQ_STA 0x0030
	64	#define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
	65
	66	/* Alarm 1 (wall clock) */
	67	#define SUN6I_ALRM1_EN 0x0044
	68	#define SUN6I_ALRM1_IRQ_EN 0x0048
	69	#define SUN6I_ALRM1_IRQ_STA 0x004c
	70	#define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0)
	71
	72	/* Alarm config */
	73	#define SUN6I_ALARM_CONFIG 0x0050
	74	#define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
	75
17ecd246	76	#define SUN6I_LOSC_OUT_GATING 0x0060
20de8707	77	#define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0
17ecd246	78
9765d2d9 CYT	79	/*
	80	* Get date values
	81	*/
	82	#define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f)
	83	#define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
	84	#define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16)
	85	#define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22)
	86
	87	/*
	88	* Get time values
	89	*/
	90	#define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f)
	91	#define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
	92	#define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
	93
	94	/*
	95	* Set date values
	96	*/
	97	#define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f)
	98	#define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00)
	99	#define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000)
	100	#define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000)
	101
	102	/*
	103	* Set time values
	104	*/
	105	#define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f)
	106	#define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00)
	107	#define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000)
	108
	109	/*
	110	* The year parameter passed to the driver is usually an offset relative to
	111	* the year 1900. This macro is used to convert this offset to another one
	112	* relative to the minimum year allowed by the hardware.
	113	*
	114	* The year range is 1970 - 2033. This range is selected to match Allwinner's
	115	* driver, even though it is somewhat limited.
	116	*/
	117	#define SUN6I_YEAR_MIN 1970
	118	#define SUN6I_YEAR_MAX 2033
	119	#define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900)
	120
	121	struct sun6i_rtc_dev {
	122	struct rtc_device *rtc;
	123	struct device *dev;
	124	void __iomem *base;
	125	int irq;
	126	unsigned long alarm;
a9422a19	127
3855c2c3 MR	128	struct clk_hw hw;
	129	struct clk_hw *int_osc;
	130	struct clk *losc;
17ecd246	131	struct clk *ext_losc;
3855c2c3	132
a9422a19	133	spinlock_t lock;
9765d2d9 CYT	134	};
9765d2d9 CYT	135
3855c2c3 MR	136	static struct sun6i_rtc_dev *sun6i_rtc;
	137
	138	static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
	139	unsigned long parent_rate)
	140	{
	141	struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
	142	u32 val;
	143
	144	val = readl(rtc->base + SUN6I_LOSC_CTRL);
	145	if (val & SUN6I_LOSC_CTRL_EXT_OSC)
	146	return parent_rate;
	147
	148	val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
	149	val &= GENMASK(4, 0);
	150
	151	return parent_rate / (val + 1);
	152	}
	153
	154	static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
	155	{
	156	struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
	157
	158	return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
	159	}
	160
	161	static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
	162	{
	163	struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
	164	unsigned long flags;
	165	u32 val;
	166
	167	if (index > 1)
	168	return -EINVAL;
	169
	170	spin_lock_irqsave(&rtc->lock, flags);
	171	val = readl(rtc->base + SUN6I_LOSC_CTRL);
	172	val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
	173	val \|= SUN6I_LOSC_CTRL_KEY;
	174	val \|= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
	175	writel(val, rtc->base + SUN6I_LOSC_CTRL);
	176	spin_unlock_irqrestore(&rtc->lock, flags);
	177
	178	return 0;
	179	}
	180
	181	static const struct clk_ops sun6i_rtc_osc_ops = {
	182	.recalc_rate = sun6i_rtc_osc_recalc_rate,
	183
	184	.get_parent = sun6i_rtc_osc_get_parent,
	185	.set_parent = sun6i_rtc_osc_set_parent,
	186	};
	187
	188	static void __init sun6i_rtc_clk_init(struct device_node *node)
	189	{
	190	struct clk_hw_onecell_data *clk_data;
	191	struct sun6i_rtc_dev *rtc;
	192	struct clk_init_data init = {
	193	.ops = &sun6i_rtc_osc_ops,
	194	};
17ecd246	195	const char *clkout_name = "osc32k-out";
3855c2c3 MR	196	const char *parents[2];
	197
	198	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
	199	if (!rtc)
	200	return;
3855c2c3	201
17ecd246	202	clk_data = kzalloc(sizeof(clk_data) + (sizeof(clk_data->hws) * 2),
3855c2c3 MR	203	GFP_KERNEL);
	204	if (!clk_data)
	205	return;
319ff835	206
3855c2c3 MR	207	spin_lock_init(&rtc->lock);
	208
	209	rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
aaa65a9c	210	if (IS_ERR(rtc->base)) {
3855c2c3	211	pr_crit("Can't map RTC registers");
1a37c348	212	goto err;
3855c2c3 MR	213	}
	214
	215	/* Switch to the external, more precise, oscillator */
	216	writel(SUN6I_LOSC_CTRL_KEY \| SUN6I_LOSC_CTRL_EXT_OSC,
	217	rtc->base + SUN6I_LOSC_CTRL);
	218
15829cf4 CYT	219	/* Yes, I know, this is ugly. */
	220	sun6i_rtc = rtc;
	221
3855c2c3 MR	222	/* Deal with old DTs */
3855c2c3 MR	223	if (!of_get_property(node, "clocks", NULL))
1a37c348	224	goto err;
3855c2c3 MR	225
	226	rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
	227	"rtc-int-osc",
	228	NULL, 0,
	229	667000,
	230	300000000);
	231	if (IS_ERR(rtc->int_osc)) {
	232	pr_crit("Couldn't register the internal oscillator\n");
	233	return;
	234	}
	235
	236	parents[0] = clk_hw_get_name(rtc->int_osc);
	237	parents[1] = of_clk_get_parent_name(node, 0);
	238
	239	rtc->hw.init = &init;
	240
	241	init.parent_names = parents;
	242	init.num_parents = of_clk_get_parent_count(node) + 1;
17ecd246 MR	243	of_property_read_string_index(node, "clock-output-names", 0,
17ecd246 MR	244	&init.name);
3855c2c3 MR	245
	246	rtc->losc = clk_register(NULL, &rtc->hw);
	247	if (IS_ERR(rtc->losc)) {
	248	pr_crit("Couldn't register the LOSC clock\n");
	249	return;
	250	}
	251
17ecd246 MR	252	of_property_read_string_index(node, "clock-output-names", 1,
	253	&clkout_name);
	254	rtc->ext_losc = clk_register_gate(NULL, clkout_name, rtc->hw.init->name,
	255	0, rtc->base + SUN6I_LOSC_OUT_GATING,
20de8707	256	SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
17ecd246 MR	257	&rtc->lock);
	258	if (IS_ERR(rtc->ext_losc)) {
	259	pr_crit("Couldn't register the LOSC external gate\n");
	260	return;
	261	}
	262
	263	clk_data->num = 2;
3855c2c3	264	clk_data->hws[0] = &rtc->hw;
17ecd246	265	clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
3855c2c3	266	of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1a37c348 CIK	267	return;
	268
	269	err:
	270	kfree(clk_data);
3855c2c3 MR	271	}
	272	CLK_OF_DECLARE_DRIVER(sun6i_rtc_clk, "allwinner,sun6i-a31-rtc",
	273	sun6i_rtc_clk_init);
	274
9765d2d9 CYT	275	static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
	276	{
	277	struct sun6i_rtc_dev chip = (struct sun6i_rtc_dev ) id;
a9422a19	278	irqreturn_t ret = IRQ_NONE;
9765d2d9 CYT	279	u32 val;
9765d2d9 CYT	280
a9422a19	281	spin_lock(&chip->lock);
9765d2d9 CYT	282	val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
	283
	284	if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
	285	val \|= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
	286	writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
	287
	288	rtc_update_irq(chip->rtc, 1, RTC_AF \| RTC_IRQF);
	289
a9422a19	290	ret = IRQ_HANDLED;
9765d2d9	291	}
a9422a19	292	spin_unlock(&chip->lock);
9765d2d9	293
a9422a19	294	return ret;
9765d2d9 CYT	295	}
	296
	297	static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
	298	{
	299	u32 alrm_val = 0;
	300	u32 alrm_irq_val = 0;
	301	u32 alrm_wake_val = 0;
a9422a19	302	unsigned long flags;
9765d2d9 CYT	303
	304	if (to) {
	305	alrm_val = SUN6I_ALRM_EN_CNT_EN;
	306	alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
	307	alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
	308	} else {
	309	writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
	310	chip->base + SUN6I_ALRM_IRQ_STA);
	311	}
	312
a9422a19	313	spin_lock_irqsave(&chip->lock, flags);
9765d2d9 CYT	314	writel(alrm_val, chip->base + SUN6I_ALRM_EN);
	315	writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
	316	writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
a9422a19	317	spin_unlock_irqrestore(&chip->lock, flags);
9765d2d9 CYT	318	}
	319
	320	static int sun6i_rtc_gettime(struct device dev, struct rtc_time rtc_tm)
	321	{
	322	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
	323	u32 date, time;
	324
	325	/*
	326	* read again in case it changes
	327	*/
	328	do {
	329	date = readl(chip->base + SUN6I_RTC_YMD);
	330	time = readl(chip->base + SUN6I_RTC_HMS);
	331	} while ((date != readl(chip->base + SUN6I_RTC_YMD)) \|\|
	332	(time != readl(chip->base + SUN6I_RTC_HMS)));
	333
	334	rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time);
	335	rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
	336	rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
	337
	338	rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
	339	rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date);
	340	rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
	341
	342	rtc_tm->tm_mon -= 1;
	343
	344	/*
	345	* switch from (data_year->min)-relative offset to
	346	* a (1900)-relative one
	347	*/
	348	rtc_tm->tm_year += SUN6I_YEAR_OFF;
	349
	350	return rtc_valid_tm(rtc_tm);
	351	}
	352
	353	static int sun6i_rtc_getalarm(struct device dev, struct rtc_wkalrm wkalrm)
	354	{
	355	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
a9422a19	356	unsigned long flags;
9765d2d9 CYT	357	u32 alrm_st;
	358	u32 alrm_en;
	359
a9422a19	360	spin_lock_irqsave(&chip->lock, flags);
9765d2d9 CYT	361	alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
9765d2d9 CYT	362	alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
a9422a19 MR	363	spin_unlock_irqrestore(&chip->lock, flags);
a9422a19 MR	364
9765d2d9 CYT	365	wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
	366	wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
	367	rtc_time_to_tm(chip->alarm, &wkalrm->time);
	368
	369	return 0;
	370	}
	371
	372	static int sun6i_rtc_setalarm(struct device dev, struct rtc_wkalrm wkalrm)
	373	{
	374	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
	375	struct rtc_time *alrm_tm = &wkalrm->time;
	376	struct rtc_time tm_now;
	377	unsigned long time_now = 0;
	378	unsigned long time_set = 0;
	379	unsigned long time_gap = 0;
	380	int ret = 0;
	381
	382	ret = sun6i_rtc_gettime(dev, &tm_now);
	383	if (ret < 0) {
	384	dev_err(dev, "Error in getting time\n");
	385	return -EINVAL;
	386	}
	387
	388	rtc_tm_to_time(alrm_tm, &time_set);
	389	rtc_tm_to_time(&tm_now, &time_now);
	390	if (time_set <= time_now) {
	391	dev_err(dev, "Date to set in the past\n");
	392	return -EINVAL;
	393	}
	394
	395	time_gap = time_set - time_now;
	396
	397	if (time_gap > U32_MAX) {
	398	dev_err(dev, "Date too far in the future\n");
	399	return -EINVAL;
	400	}
	401
	402	sun6i_rtc_setaie(0, chip);
	403	writel(0, chip->base + SUN6I_ALRM_COUNTER);
	404	usleep_range(100, 300);
	405
	406	writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
	407	chip->alarm = time_set;
	408
	409	sun6i_rtc_setaie(wkalrm->enabled, chip);
	410
	411	return 0;
	412	}
	413
	414	static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
	415	unsigned int mask, unsigned int ms_timeout)
	416	{
	417	const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
	418	u32 reg;
	419
	420	do {
	421	reg = readl(chip->base + offset);
	422	reg &= mask;
	423
	424	if (!reg)
	425	return 0;
	426
	427	} while (time_before(jiffies, timeout));
	428
429	return -ETIMEDOUT;
430	}
431
432	static int sun6i_rtc_settime(struct device dev, struct rtc_time rtc_tm)
433	{
434	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
435	u32 date = 0;
436	u32 time = 0;
437	int year;
438
439	year = rtc_tm->tm_year + 1900;
440	if (year < SUN6I_YEAR_MIN \|\| year > SUN6I_YEAR_MAX) {
441	dev_err(dev, "rtc only supports year in range %d - %d\n",
442	SUN6I_YEAR_MIN, SUN6I_YEAR_MAX);
443	return -EINVAL;
444	}
445
446	rtc_tm->tm_year -= SUN6I_YEAR_OFF;
447	rtc_tm->tm_mon += 1;
448
449	date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) \|
450	SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) \|
451	SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
452
453	if (is_leap_year(year))
454	date \|= SUN6I_LEAP_SET_VALUE(1);
455
456	time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) \|
457	SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) \|
458	SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
459
460	/* Check whether registers are writable */
461	if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
462	SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
463	dev_err(dev, "rtc is still busy.\n");
464	return -EBUSY;
465	}
466
467	writel(time, chip->base + SUN6I_RTC_HMS);
468
469	/*
470	* After writing the RTC HH-MM-SS register, the
471	* SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
472	* be cleared until the real writing operation is finished
473	*/
474
475	if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
476	SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
477	dev_err(dev, "Failed to set rtc time.\n");
478	return -ETIMEDOUT;
479	}
480
481	writel(date, chip->base + SUN6I_RTC_YMD);
482
483	/*
484	* After writing the RTC YY-MM-DD register, the
485	* SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
486	* be cleared until the real writing operation is finished
487	*/
488
489	if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
490	SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
491	dev_err(dev, "Failed to set rtc time.\n");
492	return -ETIMEDOUT;
493	}
494
495	return 0;
496	}
497
498	static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
499	{
500	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
501
502	if (!enabled)
503	sun6i_rtc_setaie(enabled, chip);
504
505	return 0;
506	}
507
508	static const struct rtc_class_ops sun6i_rtc_ops = {
509	.read_time = sun6i_rtc_gettime,
510	.set_time = sun6i_rtc_settime,
511	.read_alarm = sun6i_rtc_getalarm,
512	.set_alarm = sun6i_rtc_setalarm,
513	.alarm_irq_enable = sun6i_rtc_alarm_irq_enable
514	};
515
516	static int sun6i_rtc_probe(struct platform_device *pdev)
517	{
3855c2c3	518	struct sun6i_rtc_dev *chip = sun6i_rtc;
9765d2d9 CYT	519	int ret;
9765d2d9 CYT	520
9765d2d9	521	if (!chip)
3855c2c3	522	return -ENODEV;
9765d2d9 CYT	523
	524	platform_set_drvdata(pdev, chip);
	525	chip->dev = &pdev->dev;
	526
9765d2d9 CYT	527	chip->irq = platform_get_irq(pdev, 0);
	528	if (chip->irq < 0) {
	529	dev_err(&pdev->dev, "No IRQ resource\n");
	530	return chip->irq;
	531	}
	532
	533	ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
	534	0, dev_name(&pdev->dev), chip);
	535	if (ret) {
	536	dev_err(&pdev->dev, "Could not request IRQ\n");
	537	return ret;
	538	}
	539
	540	/* clear the alarm counter value */
	541	writel(0, chip->base + SUN6I_ALRM_COUNTER);
	542
	543	/* disable counter alarm */
	544	writel(0, chip->base + SUN6I_ALRM_EN);
	545
	546	/* disable counter alarm interrupt */
	547	writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
	548
	549	/* disable week alarm */
	550	writel(0, chip->base + SUN6I_ALRM1_EN);
	551
	552	/* disable week alarm interrupt */
	553	writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
	554
	555	/* clear counter alarm pending interrupts */
	556	writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
	557	chip->base + SUN6I_ALRM_IRQ_STA);
	558
	559	/* clear week alarm pending interrupts */
	560	writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
	561	chip->base + SUN6I_ALRM1_IRQ_STA);
	562
	563	/* disable alarm wakeup */
	564	writel(0, chip->base + SUN6I_ALARM_CONFIG);
	565
3855c2c3	566	clk_prepare_enable(chip->losc);
fb61bb82	567
5dff3a31 MR	568	chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-sun6i",
5dff3a31 MR	569	&sun6i_rtc_ops, THIS_MODULE);
9765d2d9 CYT	570	if (IS_ERR(chip->rtc)) {
	571	dev_err(&pdev->dev, "unable to register device\n");
	572	return PTR_ERR(chip->rtc);
	573	}
	574
	575	dev_info(&pdev->dev, "RTC enabled\n");
	576
	577	return 0;
	578	}
	579
9765d2d9 CYT	580	static const struct of_device_id sun6i_rtc_dt_ids[] = {
	581	{ .compatible = "allwinner,sun6i-a31-rtc" },
	582	{ /* sentinel */ },
	583	};
	584	MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
	585
	586	static struct platform_driver sun6i_rtc_driver = {
	587	.probe = sun6i_rtc_probe,
9765d2d9 CYT	588	.driver = {
	589	.name = "sun6i-rtc",
	590	.of_match_table = sun6i_rtc_dt_ids,
	591	},
	592	};
37539414	593	builtin_platform_driver(sun6i_rtc_driver);