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Commit | Line | Data |
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1da177e4 | 1 | /* |
8417eb7a | 2 | * Driver for NEC VR4100 series Real Time Clock unit. |
1da177e4 | 3 | * |
ada8e951 | 4 | * Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org> |
1da177e4 LT |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
bd076509 | 20 | #include <linux/err.h> |
1da177e4 LT |
21 | #include <linux/fs.h> |
22 | #include <linux/init.h> | |
23 | #include <linux/ioport.h> | |
bd076509 | 24 | #include <linux/interrupt.h> |
1da177e4 | 25 | #include <linux/module.h> |
8417eb7a | 26 | #include <linux/platform_device.h> |
1da177e4 LT |
27 | #include <linux/rtc.h> |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/types.h> | |
5d2a5037 | 30 | #include <linux/log2.h> |
1da177e4 LT |
31 | |
32 | #include <asm/div64.h> | |
33 | #include <asm/io.h> | |
1da177e4 | 34 | #include <asm/uaccess.h> |
1da177e4 | 35 | |
ada8e951 | 36 | MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>"); |
1da177e4 | 37 | MODULE_DESCRIPTION("NEC VR4100 series RTC driver"); |
4cad4431 | 38 | MODULE_LICENSE("GPL v2"); |
1da177e4 | 39 | |
1da177e4 LT |
40 | /* RTC 1 registers */ |
41 | #define ETIMELREG 0x00 | |
42 | #define ETIMEMREG 0x02 | |
43 | #define ETIMEHREG 0x04 | |
44 | /* RFU */ | |
45 | #define ECMPLREG 0x08 | |
46 | #define ECMPMREG 0x0a | |
47 | #define ECMPHREG 0x0c | |
48 | /* RFU */ | |
49 | #define RTCL1LREG 0x10 | |
50 | #define RTCL1HREG 0x12 | |
51 | #define RTCL1CNTLREG 0x14 | |
52 | #define RTCL1CNTHREG 0x16 | |
53 | #define RTCL2LREG 0x18 | |
54 | #define RTCL2HREG 0x1a | |
55 | #define RTCL2CNTLREG 0x1c | |
56 | #define RTCL2CNTHREG 0x1e | |
57 | ||
58 | /* RTC 2 registers */ | |
59 | #define TCLKLREG 0x00 | |
60 | #define TCLKHREG 0x02 | |
61 | #define TCLKCNTLREG 0x04 | |
62 | #define TCLKCNTHREG 0x06 | |
63 | /* RFU */ | |
64 | #define RTCINTREG 0x1e | |
65 | #define TCLOCK_INT 0x08 | |
66 | #define RTCLONG2_INT 0x04 | |
67 | #define RTCLONG1_INT 0x02 | |
68 | #define ELAPSEDTIME_INT 0x01 | |
69 | ||
70 | #define RTC_FREQUENCY 32768 | |
71 | #define MAX_PERIODIC_RATE 6553 | |
1da177e4 LT |
72 | |
73 | static void __iomem *rtc1_base; | |
74 | static void __iomem *rtc2_base; | |
75 | ||
76 | #define rtc1_read(offset) readw(rtc1_base + (offset)) | |
77 | #define rtc1_write(offset, value) writew((value), rtc1_base + (offset)) | |
78 | ||
79 | #define rtc2_read(offset) readw(rtc2_base + (offset)) | |
80 | #define rtc2_write(offset, value) writew((value), rtc2_base + (offset)) | |
81 | ||
82 | static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */ | |
83 | ||
34af946a | 84 | static DEFINE_SPINLOCK(rtc_lock); |
1da177e4 | 85 | static char rtc_name[] = "RTC"; |
1da177e4 | 86 | static unsigned long periodic_count; |
9b5ef64a | 87 | static unsigned int alarm_enabled; |
2fac6674 AV |
88 | static int aie_irq; |
89 | static int pie_irq; | |
1da177e4 | 90 | |
1da177e4 LT |
91 | static inline unsigned long read_elapsed_second(void) |
92 | { | |
8417eb7a | 93 | |
1da177e4 | 94 | unsigned long first_low, first_mid, first_high; |
8417eb7a | 95 | |
1da177e4 LT |
96 | unsigned long second_low, second_mid, second_high; |
97 | ||
98 | do { | |
99 | first_low = rtc1_read(ETIMELREG); | |
100 | first_mid = rtc1_read(ETIMEMREG); | |
101 | first_high = rtc1_read(ETIMEHREG); | |
102 | second_low = rtc1_read(ETIMELREG); | |
103 | second_mid = rtc1_read(ETIMEMREG); | |
104 | second_high = rtc1_read(ETIMEHREG); | |
105 | } while (first_low != second_low || first_mid != second_mid || | |
106 | first_high != second_high); | |
107 | ||
108 | return (first_high << 17) | (first_mid << 1) | (first_low >> 15); | |
109 | } | |
110 | ||
111 | static inline void write_elapsed_second(unsigned long sec) | |
112 | { | |
113 | spin_lock_irq(&rtc_lock); | |
114 | ||
115 | rtc1_write(ETIMELREG, (uint16_t)(sec << 15)); | |
116 | rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1)); | |
117 | rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17)); | |
118 | ||
119 | spin_unlock_irq(&rtc_lock); | |
120 | } | |
121 | ||
8417eb7a | 122 | static void vr41xx_rtc_release(struct device *dev) |
1da177e4 | 123 | { |
1da177e4 LT |
124 | |
125 | spin_lock_irq(&rtc_lock); | |
126 | ||
8417eb7a YY |
127 | rtc1_write(ECMPLREG, 0); |
128 | rtc1_write(ECMPMREG, 0); | |
129 | rtc1_write(ECMPHREG, 0); | |
130 | rtc1_write(RTCL1LREG, 0); | |
131 | rtc1_write(RTCL1HREG, 0); | |
1da177e4 LT |
132 | |
133 | spin_unlock_irq(&rtc_lock); | |
134 | ||
bd076509 YY |
135 | disable_irq(aie_irq); |
136 | disable_irq(pie_irq); | |
1da177e4 LT |
137 | } |
138 | ||
8417eb7a | 139 | static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time) |
1da177e4 LT |
140 | { |
141 | unsigned long epoch_sec, elapsed_sec; | |
142 | ||
143 | epoch_sec = mktime(epoch, 1, 1, 0, 0, 0); | |
144 | elapsed_sec = read_elapsed_second(); | |
145 | ||
8417eb7a YY |
146 | rtc_time_to_tm(epoch_sec + elapsed_sec, time); |
147 | ||
148 | return 0; | |
1da177e4 LT |
149 | } |
150 | ||
8417eb7a | 151 | static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time) |
1da177e4 LT |
152 | { |
153 | unsigned long epoch_sec, current_sec; | |
154 | ||
155 | epoch_sec = mktime(epoch, 1, 1, 0, 0, 0); | |
156 | current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday, | |
157 | time->tm_hour, time->tm_min, time->tm_sec); | |
158 | ||
159 | write_elapsed_second(current_sec - epoch_sec); | |
8417eb7a YY |
160 | |
161 | return 0; | |
1da177e4 LT |
162 | } |
163 | ||
8417eb7a | 164 | static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) |
1da177e4 | 165 | { |
8417eb7a YY |
166 | unsigned long low, mid, high; |
167 | struct rtc_time *time = &wkalrm->time; | |
1da177e4 | 168 | |
8417eb7a | 169 | spin_lock_irq(&rtc_lock); |
1da177e4 | 170 | |
8417eb7a YY |
171 | low = rtc1_read(ECMPLREG); |
172 | mid = rtc1_read(ECMPMREG); | |
173 | high = rtc1_read(ECMPHREG); | |
9b5ef64a | 174 | wkalrm->enabled = alarm_enabled; |
1da177e4 | 175 | |
8417eb7a | 176 | spin_unlock_irq(&rtc_lock); |
1da177e4 | 177 | |
8417eb7a | 178 | rtc_time_to_tm((high << 17) | (mid << 1) | (low >> 15), time); |
1da177e4 | 179 | |
8417eb7a YY |
180 | return 0; |
181 | } | |
1da177e4 | 182 | |
8417eb7a YY |
183 | static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) |
184 | { | |
185 | unsigned long alarm_sec; | |
186 | struct rtc_time *time = &wkalrm->time; | |
1da177e4 | 187 | |
8417eb7a YY |
188 | alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday, |
189 | time->tm_hour, time->tm_min, time->tm_sec); | |
1da177e4 | 190 | |
8417eb7a | 191 | spin_lock_irq(&rtc_lock); |
1da177e4 | 192 | |
9b5ef64a | 193 | if (alarm_enabled) |
bd076509 | 194 | disable_irq(aie_irq); |
9b5ef64a | 195 | |
8417eb7a YY |
196 | rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15)); |
197 | rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1)); | |
198 | rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17)); | |
1da177e4 | 199 | |
9b5ef64a | 200 | if (wkalrm->enabled) |
bd076509 | 201 | enable_irq(aie_irq); |
9b5ef64a YY |
202 | |
203 | alarm_enabled = wkalrm->enabled; | |
204 | ||
8417eb7a | 205 | spin_unlock_irq(&rtc_lock); |
1da177e4 LT |
206 | |
207 | return 0; | |
208 | } | |
209 | ||
4cad4431 | 210 | static int vr41xx_rtc_irq_set_freq(struct device *dev, int freq) |
1da177e4 | 211 | { |
61df3337 | 212 | u64 count; |
1da177e4 | 213 | |
5d2a5037 JC |
214 | if (!is_power_of_2(freq)) |
215 | return -EINVAL; | |
4cad4431 YY |
216 | count = RTC_FREQUENCY; |
217 | do_div(count, freq); | |
218 | ||
4cad4431 YY |
219 | spin_lock_irq(&rtc_lock); |
220 | ||
61df3337 YY |
221 | periodic_count = count; |
222 | rtc1_write(RTCL1LREG, periodic_count); | |
223 | rtc1_write(RTCL1HREG, periodic_count >> 16); | |
4cad4431 YY |
224 | |
225 | spin_unlock_irq(&rtc_lock); | |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
230 | static int vr41xx_rtc_irq_set_state(struct device *dev, int enabled) | |
231 | { | |
232 | if (enabled) | |
233 | enable_irq(pie_irq); | |
234 | else | |
235 | disable_irq(pie_irq); | |
236 | ||
237 | return 0; | |
238 | } | |
239 | ||
240 | static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | |
241 | { | |
1da177e4 LT |
242 | switch (cmd) { |
243 | case RTC_AIE_ON: | |
9b5ef64a YY |
244 | spin_lock_irq(&rtc_lock); |
245 | ||
246 | if (!alarm_enabled) { | |
bd076509 | 247 | enable_irq(aie_irq); |
9b5ef64a YY |
248 | alarm_enabled = 1; |
249 | } | |
250 | ||
251 | spin_unlock_irq(&rtc_lock); | |
1da177e4 LT |
252 | break; |
253 | case RTC_AIE_OFF: | |
9b5ef64a YY |
254 | spin_lock_irq(&rtc_lock); |
255 | ||
256 | if (alarm_enabled) { | |
bd076509 | 257 | disable_irq(aie_irq); |
9b5ef64a YY |
258 | alarm_enabled = 0; |
259 | } | |
260 | ||
1da177e4 LT |
261 | spin_unlock_irq(&rtc_lock); |
262 | break; | |
263 | case RTC_EPOCH_READ: | |
264 | return put_user(epoch, (unsigned long __user *)arg); | |
265 | case RTC_EPOCH_SET: | |
266 | /* Doesn't support before 1900 */ | |
267 | if (arg < 1900) | |
268 | return -EINVAL; | |
1da177e4 LT |
269 | epoch = arg; |
270 | break; | |
271 | default: | |
b3969e58 | 272 | return -ENOIOCTLCMD; |
1da177e4 LT |
273 | } |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
7d12e780 | 278 | static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id) |
1da177e4 | 279 | { |
8417eb7a YY |
280 | struct platform_device *pdev = (struct platform_device *)dev_id; |
281 | struct rtc_device *rtc = platform_get_drvdata(pdev); | |
1da177e4 | 282 | |
8417eb7a | 283 | rtc2_write(RTCINTREG, ELAPSEDTIME_INT); |
1da177e4 | 284 | |
ab6a2d70 | 285 | rtc_update_irq(rtc, 1, RTC_AF); |
1da177e4 LT |
286 | |
287 | return IRQ_HANDLED; | |
288 | } | |
289 | ||
7d12e780 | 290 | static irqreturn_t rtclong1_interrupt(int irq, void *dev_id) |
1da177e4 | 291 | { |
8417eb7a YY |
292 | struct platform_device *pdev = (struct platform_device *)dev_id; |
293 | struct rtc_device *rtc = platform_get_drvdata(pdev); | |
1da177e4 LT |
294 | unsigned long count = periodic_count; |
295 | ||
1da177e4 LT |
296 | rtc2_write(RTCINTREG, RTCLONG1_INT); |
297 | ||
298 | rtc1_write(RTCL1LREG, count); | |
299 | rtc1_write(RTCL1HREG, count >> 16); | |
300 | ||
ab6a2d70 | 301 | rtc_update_irq(rtc, 1, RTC_PF); |
1da177e4 LT |
302 | |
303 | return IRQ_HANDLED; | |
304 | } | |
305 | ||
ff8371ac | 306 | static const struct rtc_class_ops vr41xx_rtc_ops = { |
8417eb7a YY |
307 | .release = vr41xx_rtc_release, |
308 | .ioctl = vr41xx_rtc_ioctl, | |
309 | .read_time = vr41xx_rtc_read_time, | |
310 | .set_time = vr41xx_rtc_set_time, | |
311 | .read_alarm = vr41xx_rtc_read_alarm, | |
312 | .set_alarm = vr41xx_rtc_set_alarm, | |
4cad4431 YY |
313 | .irq_set_freq = vr41xx_rtc_irq_set_freq, |
314 | .irq_set_state = vr41xx_rtc_irq_set_state, | |
1da177e4 LT |
315 | }; |
316 | ||
d39b6cfe | 317 | static int __devinit rtc_probe(struct platform_device *pdev) |
1da177e4 | 318 | { |
bd076509 | 319 | struct resource *res; |
8417eb7a | 320 | struct rtc_device *rtc; |
1da177e4 LT |
321 | int retval; |
322 | ||
bd076509 | 323 | if (pdev->num_resources != 4) |
1da177e4 LT |
324 | return -EBUSY; |
325 | ||
bd076509 YY |
326 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
327 | if (!res) | |
1da177e4 LT |
328 | return -EBUSY; |
329 | ||
bd076509 YY |
330 | rtc1_base = ioremap(res->start, res->end - res->start + 1); |
331 | if (!rtc1_base) | |
1da177e4 | 332 | return -EBUSY; |
bd076509 YY |
333 | |
334 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
335 | if (!res) { | |
336 | retval = -EBUSY; | |
337 | goto err_rtc1_iounmap; | |
338 | } | |
339 | ||
340 | rtc2_base = ioremap(res->start, res->end - res->start + 1); | |
341 | if (!rtc2_base) { | |
342 | retval = -EBUSY; | |
343 | goto err_rtc1_iounmap; | |
1da177e4 LT |
344 | } |
345 | ||
8417eb7a YY |
346 | rtc = rtc_device_register(rtc_name, &pdev->dev, &vr41xx_rtc_ops, THIS_MODULE); |
347 | if (IS_ERR(rtc)) { | |
bd076509 YY |
348 | retval = PTR_ERR(rtc); |
349 | goto err_iounmap_all; | |
1da177e4 LT |
350 | } |
351 | ||
4cad4431 YY |
352 | rtc->max_user_freq = MAX_PERIODIC_RATE; |
353 | ||
1da177e4 LT |
354 | spin_lock_irq(&rtc_lock); |
355 | ||
356 | rtc1_write(ECMPLREG, 0); | |
357 | rtc1_write(ECMPMREG, 0); | |
358 | rtc1_write(ECMPHREG, 0); | |
359 | rtc1_write(RTCL1LREG, 0); | |
360 | rtc1_write(RTCL1HREG, 0); | |
361 | ||
1da177e4 LT |
362 | spin_unlock_irq(&rtc_lock); |
363 | ||
bd076509 | 364 | aie_irq = platform_get_irq(pdev, 0); |
2fac6674 | 365 | if (aie_irq <= 0) { |
bd076509 YY |
366 | retval = -EBUSY; |
367 | goto err_device_unregister; | |
1da177e4 LT |
368 | } |
369 | ||
bd076509 YY |
370 | retval = request_irq(aie_irq, elapsedtime_interrupt, IRQF_DISABLED, |
371 | "elapsed_time", pdev); | |
372 | if (retval < 0) | |
373 | goto err_device_unregister; | |
374 | ||
375 | pie_irq = platform_get_irq(pdev, 1); | |
2fac6674 | 376 | if (pie_irq <= 0) |
bd076509 YY |
377 | goto err_free_irq; |
378 | ||
379 | retval = request_irq(pie_irq, rtclong1_interrupt, IRQF_DISABLED, | |
380 | "rtclong1", pdev); | |
381 | if (retval < 0) | |
382 | goto err_free_irq; | |
1da177e4 | 383 | |
8417eb7a YY |
384 | platform_set_drvdata(pdev, rtc); |
385 | ||
bd076509 YY |
386 | disable_irq(aie_irq); |
387 | disable_irq(pie_irq); | |
1da177e4 | 388 | |
1da177e4 LT |
389 | printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n"); |
390 | ||
391 | return 0; | |
bd076509 YY |
392 | |
393 | err_free_irq: | |
394 | free_irq(aie_irq, pdev); | |
395 | ||
396 | err_device_unregister: | |
397 | rtc_device_unregister(rtc); | |
398 | ||
399 | err_iounmap_all: | |
400 | iounmap(rtc2_base); | |
401 | rtc2_base = NULL; | |
402 | ||
403 | err_rtc1_iounmap: | |
404 | iounmap(rtc1_base); | |
405 | rtc1_base = NULL; | |
406 | ||
407 | return retval; | |
1da177e4 LT |
408 | } |
409 | ||
8417eb7a | 410 | static int __devexit rtc_remove(struct platform_device *pdev) |
1da177e4 | 411 | { |
8417eb7a | 412 | struct rtc_device *rtc; |
1da177e4 | 413 | |
8417eb7a | 414 | rtc = platform_get_drvdata(pdev); |
bd076509 | 415 | if (rtc) |
8417eb7a YY |
416 | rtc_device_unregister(rtc); |
417 | ||
418 | platform_set_drvdata(pdev, NULL); | |
1da177e4 | 419 | |
bd076509 YY |
420 | free_irq(aie_irq, pdev); |
421 | free_irq(pie_irq, pdev); | |
422 | if (rtc1_base) | |
1da177e4 | 423 | iounmap(rtc1_base); |
bd076509 | 424 | if (rtc2_base) |
1da177e4 LT |
425 | iounmap(rtc2_base); |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
ad28a07b KS |
430 | /* work with hotplug and coldplug */ |
431 | MODULE_ALIAS("platform:RTC"); | |
432 | ||
8417eb7a | 433 | static struct platform_driver rtc_platform_driver = { |
1da177e4 | 434 | .probe = rtc_probe, |
d39b6cfe | 435 | .remove = __devexit_p(rtc_remove), |
3ae5eaec RK |
436 | .driver = { |
437 | .name = rtc_name, | |
d39b6cfe | 438 | .owner = THIS_MODULE, |
3ae5eaec | 439 | }, |
1da177e4 LT |
440 | }; |
441 | ||
d39b6cfe | 442 | static int __init vr41xx_rtc_init(void) |
1da177e4 | 443 | { |
bd076509 | 444 | return platform_driver_register(&rtc_platform_driver); |
1da177e4 LT |
445 | } |
446 | ||
d39b6cfe | 447 | static void __exit vr41xx_rtc_exit(void) |
1da177e4 | 448 | { |
8417eb7a | 449 | platform_driver_unregister(&rtc_platform_driver); |
1da177e4 LT |
450 | } |
451 | ||
452 | module_init(vr41xx_rtc_init); | |
453 | module_exit(vr41xx_rtc_exit); |