[mirror_ubuntu-artful-kernel.git] / drivers / rtc / rtc-vr41xx.c

/*
 *  Driver for NEC VR4100 series Real Time Clock unit.
 *
 *  Copyright (C) 2003-2006  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#include <asm/div64.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/vr41xx/irq.h>

MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
MODULE_LICENSE("GPL");

#define RTC1_TYPE1_START	0x0b0000c0UL
#define RTC1_TYPE1_END		0x0b0000dfUL
#define RTC2_TYPE1_START	0x0b0001c0UL
#define RTC2_TYPE1_END		0x0b0001dfUL

#define RTC1_TYPE2_START	0x0f000100UL
#define RTC1_TYPE2_END		0x0f00011fUL
#define RTC2_TYPE2_START	0x0f000120UL
#define RTC2_TYPE2_END		0x0f00013fUL

#define RTC1_SIZE		0x20
#define RTC2_SIZE		0x20

/* RTC 1 registers */
#define ETIMELREG		0x00
#define ETIMEMREG		0x02
#define ETIMEHREG		0x04
/* RFU */
#define ECMPLREG		0x08
#define ECMPMREG		0x0a
#define ECMPHREG		0x0c
/* RFU */
#define RTCL1LREG		0x10
#define RTCL1HREG		0x12
#define RTCL1CNTLREG		0x14
#define RTCL1CNTHREG		0x16
#define RTCL2LREG		0x18
#define RTCL2HREG		0x1a
#define RTCL2CNTLREG		0x1c
#define RTCL2CNTHREG		0x1e

/* RTC 2 registers */
#define TCLKLREG		0x00
#define TCLKHREG		0x02
#define TCLKCNTLREG		0x04
#define TCLKCNTHREG		0x06
/* RFU */
#define RTCINTREG		0x1e
 #define TCLOCK_INT		0x08
 #define RTCLONG2_INT		0x04
 #define RTCLONG1_INT		0x02
 #define ELAPSEDTIME_INT	0x01

#define RTC_FREQUENCY		32768
#define MAX_PERIODIC_RATE	6553

static void __iomem *rtc1_base;
static void __iomem *rtc2_base;

#define rtc1_read(offset)		readw(rtc1_base + (offset))
#define rtc1_write(offset, value)	writew((value), rtc1_base + (offset))

#define rtc2_read(offset)		readw(rtc2_base + (offset))
#define rtc2_write(offset, value)	writew((value), rtc2_base + (offset))

static unsigned long epoch = 1970;	/* Jan 1 1970 00:00:00 */

static DEFINE_SPINLOCK(rtc_lock);
static char rtc_name[] = "RTC";
static unsigned long periodic_frequency;
static unsigned long periodic_count;

struct resource rtc_resource[2] = {
	{	.name	= rtc_name,
		.flags	= IORESOURCE_MEM,	},
	{	.name	= rtc_name,
		.flags	= IORESOURCE_MEM,	},
};

static inline unsigned long read_elapsed_second(void)
{

	unsigned long first_low, first_mid, first_high;

	unsigned long second_low, second_mid, second_high;

	do {
		first_low = rtc1_read(ETIMELREG);
		first_mid = rtc1_read(ETIMEMREG);
		first_high = rtc1_read(ETIMEHREG);
		second_low = rtc1_read(ETIMELREG);
		second_mid = rtc1_read(ETIMEMREG);
		second_high = rtc1_read(ETIMEHREG);
	} while (first_low != second_low || first_mid != second_mid ||
	         first_high != second_high);

	return (first_high << 17) | (first_mid << 1) | (first_low >> 15);
}

static inline void write_elapsed_second(unsigned long sec)
{
	spin_lock_irq(&rtc_lock);

	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));

	spin_unlock_irq(&rtc_lock);
}

static void vr41xx_rtc_release(struct device *dev)
{

	spin_lock_irq(&rtc_lock);

	rtc1_write(ECMPLREG, 0);
	rtc1_write(ECMPMREG, 0);
	rtc1_write(ECMPHREG, 0);
	rtc1_write(RTCL1LREG, 0);
	rtc1_write(RTCL1HREG, 0);

	spin_unlock_irq(&rtc_lock);

	disable_irq(ELAPSEDTIME_IRQ);
	disable_irq(RTCLONG1_IRQ);
}

static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
{
	unsigned long epoch_sec, elapsed_sec;

	epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
	elapsed_sec = read_elapsed_second();

	rtc_time_to_tm(epoch_sec + elapsed_sec, time);

	return 0;
}

static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
{
	unsigned long epoch_sec, current_sec;

	epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
	current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
	                     time->tm_hour, time->tm_min, time->tm_sec);

	write_elapsed_second(current_sec - epoch_sec);

	return 0;
}

static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	unsigned long low, mid, high;
	struct rtc_time *time = &wkalrm->time;

	spin_lock_irq(&rtc_lock);

	low = rtc1_read(ECMPLREG);
	mid = rtc1_read(ECMPMREG);
	high = rtc1_read(ECMPHREG);

	spin_unlock_irq(&rtc_lock);

	rtc_time_to_tm((high << 17) | (mid << 1) | (low >> 15), time);

	return 0;
}

static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	unsigned long alarm_sec;
	struct rtc_time *time = &wkalrm->time;

	alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
	                   time->tm_hour, time->tm_min, time->tm_sec);

	spin_lock_irq(&rtc_lock);

	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));

	spin_unlock_irq(&rtc_lock);

	return 0;
}

static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
	unsigned long count;

	switch (cmd) {
	case RTC_AIE_ON:
		enable_irq(ELAPSEDTIME_IRQ);
		break;
	case RTC_AIE_OFF:
		disable_irq(ELAPSEDTIME_IRQ);
		break;
	case RTC_PIE_ON:
		enable_irq(RTCLONG1_IRQ);
		break;
	case RTC_PIE_OFF:
		disable_irq(RTCLONG1_IRQ);
		break;
	case RTC_IRQP_READ:
		return put_user(periodic_frequency, (unsigned long __user *)arg);
		break;
	case RTC_IRQP_SET:
		if (arg > MAX_PERIODIC_RATE)
			return -EINVAL;

		periodic_frequency = arg;

		count = RTC_FREQUENCY;
		do_div(count, arg);

		periodic_count = count;

		spin_lock_irq(&rtc_lock);

		rtc1_write(RTCL1LREG, count);
		rtc1_write(RTCL1HREG, count >> 16);

		spin_unlock_irq(&rtc_lock);
		break;
	case RTC_EPOCH_READ:
		return put_user(epoch, (unsigned long __user *)arg);
	case RTC_EPOCH_SET:
		/* Doesn't support before 1900 */
		if (arg < 1900)
			return -EINVAL;
		epoch = arg;
		break;
	default:
		return -ENOIOCTLCMD;
	}

	return 0;
}

static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	struct platform_device *pdev = (struct platform_device *)dev_id;
	struct rtc_device *rtc = platform_get_drvdata(pdev);

	rtc2_write(RTCINTREG, ELAPSEDTIME_INT);

	rtc_update_irq(&rtc->class_dev, 1, RTC_AF);

	return IRQ_HANDLED;
}

static irqreturn_t rtclong1_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	struct platform_device *pdev = (struct platform_device *)dev_id;
	struct rtc_device *rtc = platform_get_drvdata(pdev);
	unsigned long count = periodic_count;

	rtc2_write(RTCINTREG, RTCLONG1_INT);

	rtc1_write(RTCL1LREG, count);
	rtc1_write(RTCL1HREG, count >> 16);

	rtc_update_irq(&rtc->class_dev, 1, RTC_PF);

	return IRQ_HANDLED;
}

static const struct rtc_class_ops vr41xx_rtc_ops = {
	.release	= vr41xx_rtc_release,
	.ioctl		= vr41xx_rtc_ioctl,
	.read_time	= vr41xx_rtc_read_time,
	.set_time	= vr41xx_rtc_set_time,
	.read_alarm	= vr41xx_rtc_read_alarm,
	.set_alarm	= vr41xx_rtc_set_alarm,
};

static int __devinit rtc_probe(struct platform_device *pdev)
{
	struct rtc_device *rtc;
	unsigned int irq;
	int retval;

	if (pdev->num_resources != 2)
		return -EBUSY;

	rtc1_base = ioremap(pdev->resource[0].start, RTC1_SIZE);
	if (rtc1_base == NULL)
		return -EBUSY;

	rtc2_base = ioremap(pdev->resource[1].start, RTC2_SIZE);
	if (rtc2_base == NULL) {
		iounmap(rtc1_base);
		rtc1_base = NULL;
		return -EBUSY;
	}

	rtc = rtc_device_register(rtc_name, &pdev->dev, &vr41xx_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc)) {
		iounmap(rtc1_base);
		iounmap(rtc2_base);
		rtc1_base = NULL;
		rtc2_base = NULL;
		return PTR_ERR(rtc);
	}

	spin_lock_irq(&rtc_lock);

	rtc1_write(ECMPLREG, 0);
	rtc1_write(ECMPMREG, 0);
	rtc1_write(ECMPHREG, 0);
	rtc1_write(RTCL1LREG, 0);
	rtc1_write(RTCL1HREG, 0);

	spin_unlock_irq(&rtc_lock);

	irq = ELAPSEDTIME_IRQ;
	retval = request_irq(irq, elapsedtime_interrupt, IRQF_DISABLED,
	                     "elapsed_time", pdev);
	if (retval == 0) {
		irq = RTCLONG1_IRQ;
		retval = request_irq(irq, rtclong1_interrupt, IRQF_DISABLED,
		                     "rtclong1", pdev);
	}

	if (retval < 0) {
		printk(KERN_ERR "rtc: IRQ%d is busy\n", irq);
		rtc_device_unregister(rtc);
		if (irq == RTCLONG1_IRQ)
			free_irq(ELAPSEDTIME_IRQ, NULL);
		iounmap(rtc1_base);
		iounmap(rtc2_base);
		rtc1_base = NULL;
		rtc2_base = NULL;
		return retval;
	}

	platform_set_drvdata(pdev, rtc);

	disable_irq(ELAPSEDTIME_IRQ);
	disable_irq(RTCLONG1_IRQ);

	printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n");

	return 0;
}

static int __devexit rtc_remove(struct platform_device *pdev)
{
	struct rtc_device *rtc;

	rtc = platform_get_drvdata(pdev);
	if (rtc != NULL)
		rtc_device_unregister(rtc);

	platform_set_drvdata(pdev, NULL);

	free_irq(ELAPSEDTIME_IRQ, NULL);
	free_irq(RTCLONG1_IRQ, NULL);
	if (rtc1_base != NULL)
		iounmap(rtc1_base);
	if (rtc2_base != NULL)
		iounmap(rtc2_base);

	return 0;
}

static struct platform_device *rtc_platform_device;

static struct platform_driver rtc_platform_driver = {
	.probe		= rtc_probe,
	.remove		= __devexit_p(rtc_remove),
	.driver		= {
		.name	= rtc_name,
		.owner	= THIS_MODULE,
	},
};

static int __init vr41xx_rtc_init(void)
{
	int retval;

	switch (current_cpu_data.cputype) {
	case CPU_VR4111:
	case CPU_VR4121:
		rtc_resource[0].start = RTC1_TYPE1_START;
		rtc_resource[0].end = RTC1_TYPE1_END;
		rtc_resource[1].start = RTC2_TYPE1_START;
		rtc_resource[1].end = RTC2_TYPE1_END;
		break;
	case CPU_VR4122:
	case CPU_VR4131:
	case CPU_VR4133:
		rtc_resource[0].start = RTC1_TYPE2_START;
		rtc_resource[0].end = RTC1_TYPE2_END;
		rtc_resource[1].start = RTC2_TYPE2_START;
		rtc_resource[1].end = RTC2_TYPE2_END;
		break;
	default:
		return -ENODEV;
		break;
	}

	rtc_platform_device = platform_device_alloc("RTC", -1);
	if (rtc_platform_device == NULL)
		return -ENOMEM;

	retval = platform_device_add_resources(rtc_platform_device,
				rtc_resource, ARRAY_SIZE(rtc_resource));

	if (retval == 0)
		retval = platform_device_add(rtc_platform_device);

	if (retval < 0) {
		platform_device_put(rtc_platform_device);
		return retval;
	}

	retval = platform_driver_register(&rtc_platform_driver);
	if (retval < 0)
		platform_device_unregister(rtc_platform_device);

	return retval;
}

static void __exit vr41xx_rtc_exit(void)
{
	platform_driver_unregister(&rtc_platform_driver);
	platform_device_unregister(rtc_platform_device);
}

module_init(vr41xx_rtc_init);
module_exit(vr41xx_rtc_exit);
Commit	Line	Data
1da177e4	1	/*
8417eb7a	2	* Driver for NEC VR4100 series Real Time Clock unit.
1da177e4	3	*
8417eb7a	4	* Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
1da177e4 LT	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
1da177e4 LT	20	#include <linux/fs.h>
	21	#include <linux/init.h>
	22	#include <linux/ioport.h>
	23	#include <linux/irq.h>
1da177e4	24	#include <linux/module.h>
8417eb7a	25	#include <linux/platform_device.h>
1da177e4 LT	26	#include <linux/rtc.h>
	27	#include <linux/spinlock.h>
	28	#include <linux/types.h>
1da177e4 LT	29
	30	#include <asm/div64.h>
	31	#include <asm/io.h>
1da177e4	32	#include <asm/uaccess.h>
66151bbd	33	#include <asm/vr41xx/irq.h>
1da177e4	34
29ce2c76	35	MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
1da177e4 LT	36	MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
	37	MODULE_LICENSE("GPL");
	38
	39	#define RTC1_TYPE1_START 0x0b0000c0UL
	40	#define RTC1_TYPE1_END 0x0b0000dfUL
	41	#define RTC2_TYPE1_START 0x0b0001c0UL
	42	#define RTC2_TYPE1_END 0x0b0001dfUL
	43
	44	#define RTC1_TYPE2_START 0x0f000100UL
	45	#define RTC1_TYPE2_END 0x0f00011fUL
	46	#define RTC2_TYPE2_START 0x0f000120UL
	47	#define RTC2_TYPE2_END 0x0f00013fUL
	48
	49	#define RTC1_SIZE 0x20
	50	#define RTC2_SIZE 0x20
	51
	52	/* RTC 1 registers */
	53	#define ETIMELREG 0x00
	54	#define ETIMEMREG 0x02
	55	#define ETIMEHREG 0x04
	56	/* RFU */
	57	#define ECMPLREG 0x08
	58	#define ECMPMREG 0x0a
	59	#define ECMPHREG 0x0c
	60	/* RFU */
	61	#define RTCL1LREG 0x10
	62	#define RTCL1HREG 0x12
	63	#define RTCL1CNTLREG 0x14
	64	#define RTCL1CNTHREG 0x16
	65	#define RTCL2LREG 0x18
	66	#define RTCL2HREG 0x1a
	67	#define RTCL2CNTLREG 0x1c
	68	#define RTCL2CNTHREG 0x1e
	69
	70	/* RTC 2 registers */
	71	#define TCLKLREG 0x00
	72	#define TCLKHREG 0x02
	73	#define TCLKCNTLREG 0x04
	74	#define TCLKCNTHREG 0x06
	75	/* RFU */
	76	#define RTCINTREG 0x1e
	77	#define TCLOCK_INT 0x08
	78	#define RTCLONG2_INT 0x04
	79	#define RTCLONG1_INT 0x02
	80	#define ELAPSEDTIME_INT 0x01
	81
	82	#define RTC_FREQUENCY 32768
	83	#define MAX_PERIODIC_RATE 6553
1da177e4 LT	84
	85	static void __iomem *rtc1_base;
	86	static void __iomem *rtc2_base;
	87
	88	#define rtc1_read(offset) readw(rtc1_base + (offset))
	89	#define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
	90
	91	#define rtc2_read(offset) readw(rtc2_base + (offset))
	92	#define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
	93
	94	static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
	95
34af946a	96	static DEFINE_SPINLOCK(rtc_lock);
1da177e4 LT	97	static char rtc_name[] = "RTC";
	98	static unsigned long periodic_frequency;
	99	static unsigned long periodic_count;
	100
1da177e4 LT	101	struct resource rtc_resource[2] = {
	102	{ .name = rtc_name,
	103	.flags = IORESOURCE_MEM, },
	104	{ .name = rtc_name,
	105	.flags = IORESOURCE_MEM, },
	106	};
	107
1da177e4 LT	108	static inline unsigned long read_elapsed_second(void)
1da177e4 LT	109	{
8417eb7a	110
1da177e4	111	unsigned long first_low, first_mid, first_high;
8417eb7a	112
1da177e4 LT	113	unsigned long second_low, second_mid, second_high;
	114
	115	do {
	116	first_low = rtc1_read(ETIMELREG);
	117	first_mid = rtc1_read(ETIMEMREG);
	118	first_high = rtc1_read(ETIMEHREG);
	119	second_low = rtc1_read(ETIMELREG);
	120	second_mid = rtc1_read(ETIMEMREG);
	121	second_high = rtc1_read(ETIMEHREG);
	122	} while (first_low != second_low \|\| first_mid != second_mid \|\|
	123	first_high != second_high);
	124
	125	return (first_high << 17) \| (first_mid << 1) \| (first_low >> 15);
	126	}
	127
	128	static inline void write_elapsed_second(unsigned long sec)
	129	{
	130	spin_lock_irq(&rtc_lock);
	131
	132	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
	133	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
	134	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
	135
	136	spin_unlock_irq(&rtc_lock);
	137	}
	138
8417eb7a	139	static void vr41xx_rtc_release(struct device *dev)
1da177e4	140	{
1da177e4 LT	141
	142	spin_lock_irq(&rtc_lock);
	143
8417eb7a YY	144	rtc1_write(ECMPLREG, 0);
	145	rtc1_write(ECMPMREG, 0);
	146	rtc1_write(ECMPHREG, 0);
	147	rtc1_write(RTCL1LREG, 0);
	148	rtc1_write(RTCL1HREG, 0);
1da177e4 LT	149
	150	spin_unlock_irq(&rtc_lock);
	151
8417eb7a YY	152	disable_irq(ELAPSEDTIME_IRQ);
8417eb7a YY	153	disable_irq(RTCLONG1_IRQ);
1da177e4 LT	154	}
1da177e4 LT	155
8417eb7a	156	static int vr41xx_rtc_read_time(struct device dev, struct rtc_time time)
1da177e4 LT	157	{
	158	unsigned long epoch_sec, elapsed_sec;
	159
	160	epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
	161	elapsed_sec = read_elapsed_second();
	162
8417eb7a YY	163	rtc_time_to_tm(epoch_sec + elapsed_sec, time);
	164
	165	return 0;
1da177e4 LT	166	}
1da177e4 LT	167
8417eb7a	168	static int vr41xx_rtc_set_time(struct device dev, struct rtc_time time)
1da177e4 LT	169	{
	170	unsigned long epoch_sec, current_sec;
	171
	172	epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
	173	current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
	174	time->tm_hour, time->tm_min, time->tm_sec);
	175
	176	write_elapsed_second(current_sec - epoch_sec);
8417eb7a YY	177
8417eb7a YY	178	return 0;
1da177e4 LT	179	}
1da177e4 LT	180
8417eb7a	181	static int vr41xx_rtc_read_alarm(struct device dev, struct rtc_wkalrm wkalrm)
1da177e4	182	{
8417eb7a YY	183	unsigned long low, mid, high;
8417eb7a YY	184	struct rtc_time *time = &wkalrm->time;
1da177e4	185
8417eb7a	186	spin_lock_irq(&rtc_lock);
1da177e4	187
8417eb7a YY	188	low = rtc1_read(ECMPLREG);
	189	mid = rtc1_read(ECMPMREG);
	190	high = rtc1_read(ECMPHREG);
1da177e4	191
8417eb7a	192	spin_unlock_irq(&rtc_lock);
1da177e4	193
8417eb7a	194	rtc_time_to_tm((high << 17) \| (mid << 1) \| (low >> 15), time);
1da177e4	195
8417eb7a YY	196	return 0;
8417eb7a YY	197	}
1da177e4	198
8417eb7a YY	199	static int vr41xx_rtc_set_alarm(struct device dev, struct rtc_wkalrm wkalrm)
	200	{
	201	unsigned long alarm_sec;
	202	struct rtc_time *time = &wkalrm->time;
1da177e4	203
8417eb7a YY	204	alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
8417eb7a YY	205	time->tm_hour, time->tm_min, time->tm_sec);
1da177e4	206
8417eb7a	207	spin_lock_irq(&rtc_lock);
1da177e4	208
8417eb7a YY	209	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
	210	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
	211	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
1da177e4	212
8417eb7a	213	spin_unlock_irq(&rtc_lock);
1da177e4 LT	214
	215	return 0;
	216	}
	217
8417eb7a	218	static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
1da177e4	219	{
1da177e4 LT	220	unsigned long count;
	221
	222	switch (cmd) {
	223	case RTC_AIE_ON:
	224	enable_irq(ELAPSEDTIME_IRQ);
	225	break;
	226	case RTC_AIE_OFF:
	227	disable_irq(ELAPSEDTIME_IRQ);
	228	break;
	229	case RTC_PIE_ON:
	230	enable_irq(RTCLONG1_IRQ);
	231	break;
	232	case RTC_PIE_OFF:
	233	disable_irq(RTCLONG1_IRQ);
	234	break;
1da177e4 LT	235	case RTC_IRQP_READ:
	236	return put_user(periodic_frequency, (unsigned long __user *)arg);
	237	break;
	238	case RTC_IRQP_SET:
	239	if (arg > MAX_PERIODIC_RATE)
	240	return -EINVAL;
	241
1da177e4 LT	242	periodic_frequency = arg;
	243
	244	count = RTC_FREQUENCY;
	245	do_div(count, arg);
	246
	247	periodic_count = count;
	248
	249	spin_lock_irq(&rtc_lock);
	250
	251	rtc1_write(RTCL1LREG, count);
	252	rtc1_write(RTCL1HREG, count >> 16);
	253
	254	spin_unlock_irq(&rtc_lock);
	255	break;
	256	case RTC_EPOCH_READ:
	257	return put_user(epoch, (unsigned long __user *)arg);
	258	case RTC_EPOCH_SET:
	259	/* Doesn't support before 1900 */
	260	if (arg < 1900)
	261	return -EINVAL;
1da177e4 LT	262	epoch = arg;
	263	break;
	264	default:
b3969e58	265	return -ENOIOCTLCMD;
1da177e4 LT	266	}
	267
	268	return 0;
	269	}
	270
1da177e4 LT	271	static irqreturn_t elapsedtime_interrupt(int irq, void dev_id, struct pt_regs regs)
1da177e4 LT	272	{
8417eb7a YY	273	struct platform_device pdev = (struct platform_device )dev_id;
8417eb7a YY	274	struct rtc_device *rtc = platform_get_drvdata(pdev);
1da177e4	275
8417eb7a	276	rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
1da177e4	277
8417eb7a	278	rtc_update_irq(&rtc->class_dev, 1, RTC_AF);
1da177e4 LT	279
	280	return IRQ_HANDLED;
	281	}
	282
	283	static irqreturn_t rtclong1_interrupt(int irq, void dev_id, struct pt_regs regs)
	284	{
8417eb7a YY	285	struct platform_device pdev = (struct platform_device )dev_id;
8417eb7a YY	286	struct rtc_device *rtc = platform_get_drvdata(pdev);
1da177e4 LT	287	unsigned long count = periodic_count;
1da177e4 LT	288
1da177e4 LT	289	rtc2_write(RTCINTREG, RTCLONG1_INT);
	290
	291	rtc1_write(RTCL1LREG, count);
	292	rtc1_write(RTCL1HREG, count >> 16);
	293
8417eb7a	294	rtc_update_irq(&rtc->class_dev, 1, RTC_PF);
1da177e4 LT	295
	296	return IRQ_HANDLED;
	297	}
	298
ff8371ac	299	static const struct rtc_class_ops vr41xx_rtc_ops = {
8417eb7a YY	300	.release = vr41xx_rtc_release,
	301	.ioctl = vr41xx_rtc_ioctl,
	302	.read_time = vr41xx_rtc_read_time,
	303	.set_time = vr41xx_rtc_set_time,
	304	.read_alarm = vr41xx_rtc_read_alarm,
	305	.set_alarm = vr41xx_rtc_set_alarm,
1da177e4 LT	306	};
1da177e4 LT	307
d39b6cfe	308	static int __devinit rtc_probe(struct platform_device *pdev)
1da177e4	309	{
8417eb7a	310	struct rtc_device *rtc;
1da177e4 LT	311	unsigned int irq;
	312	int retval;
	313
1da177e4 LT	314	if (pdev->num_resources != 2)
	315	return -EBUSY;
	316
	317	rtc1_base = ioremap(pdev->resource[0].start, RTC1_SIZE);
	318	if (rtc1_base == NULL)
	319	return -EBUSY;
	320
	321	rtc2_base = ioremap(pdev->resource[1].start, RTC2_SIZE);
	322	if (rtc2_base == NULL) {
	323	iounmap(rtc1_base);
	324	rtc1_base = NULL;
	325	return -EBUSY;
	326	}
	327
8417eb7a YY	328	rtc = rtc_device_register(rtc_name, &pdev->dev, &vr41xx_rtc_ops, THIS_MODULE);
8417eb7a YY	329	if (IS_ERR(rtc)) {
1da177e4 LT	330	iounmap(rtc1_base);
	331	iounmap(rtc2_base);
	332	rtc1_base = NULL;
	333	rtc2_base = NULL;
8417eb7a	334	return PTR_ERR(rtc);
1da177e4 LT	335	}
	336
	337	spin_lock_irq(&rtc_lock);
	338
	339	rtc1_write(ECMPLREG, 0);
	340	rtc1_write(ECMPMREG, 0);
	341	rtc1_write(ECMPHREG, 0);
	342	rtc1_write(RTCL1LREG, 0);
	343	rtc1_write(RTCL1HREG, 0);
	344
1da177e4 LT	345	spin_unlock_irq(&rtc_lock);
1da177e4 LT	346
1da177e4	347	irq = ELAPSEDTIME_IRQ;
dace1453	348	retval = request_irq(irq, elapsedtime_interrupt, IRQF_DISABLED,
8417eb7a	349	"elapsed_time", pdev);
1da177e4 LT	350	if (retval == 0) {
1da177e4 LT	351	irq = RTCLONG1_IRQ;
dace1453	352	retval = request_irq(irq, rtclong1_interrupt, IRQF_DISABLED,
8417eb7a	353	"rtclong1", pdev);
1da177e4 LT	354	}
	355
	356	if (retval < 0) {
	357	printk(KERN_ERR "rtc: IRQ%d is busy\n", irq);
8417eb7a	358	rtc_device_unregister(rtc);
1da177e4 LT	359	if (irq == RTCLONG1_IRQ)
	360	free_irq(ELAPSEDTIME_IRQ, NULL);
	361	iounmap(rtc1_base);
	362	iounmap(rtc2_base);
	363	rtc1_base = NULL;
	364	rtc2_base = NULL;
	365	return retval;
	366	}
	367
8417eb7a YY	368	platform_set_drvdata(pdev, rtc);
8417eb7a YY	369
1da177e4 LT	370	disable_irq(ELAPSEDTIME_IRQ);
	371	disable_irq(RTCLONG1_IRQ);
	372
1da177e4 LT	373	printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n");
	374
	375	return 0;
	376	}
	377
8417eb7a	378	static int __devexit rtc_remove(struct platform_device *pdev)
1da177e4	379	{
8417eb7a	380	struct rtc_device *rtc;
1da177e4	381
8417eb7a YY	382	rtc = platform_get_drvdata(pdev);
	383	if (rtc != NULL)
	384	rtc_device_unregister(rtc);
	385
	386	platform_set_drvdata(pdev, NULL);
1da177e4 LT	387
	388	free_irq(ELAPSEDTIME_IRQ, NULL);
	389	free_irq(RTCLONG1_IRQ, NULL);
	390	if (rtc1_base != NULL)
	391	iounmap(rtc1_base);
	392	if (rtc2_base != NULL)
	393	iounmap(rtc2_base);
	394
	395	return 0;
	396	}
	397
	398	static struct platform_device *rtc_platform_device;
	399
8417eb7a	400	static struct platform_driver rtc_platform_driver = {
1da177e4	401	.probe = rtc_probe,
d39b6cfe	402	.remove = __devexit_p(rtc_remove),
3ae5eaec RK	403	.driver = {
3ae5eaec RK	404	.name = rtc_name,
d39b6cfe	405	.owner = THIS_MODULE,
3ae5eaec	406	},
1da177e4 LT	407	};
1da177e4 LT	408
d39b6cfe	409	static int __init vr41xx_rtc_init(void)
1da177e4 LT	410	{
	411	int retval;
	412
	413	switch (current_cpu_data.cputype) {
	414	case CPU_VR4111:
	415	case CPU_VR4121:
	416	rtc_resource[0].start = RTC1_TYPE1_START;
	417	rtc_resource[0].end = RTC1_TYPE1_END;
	418	rtc_resource[1].start = RTC2_TYPE1_START;
	419	rtc_resource[1].end = RTC2_TYPE1_END;
	420	break;
	421	case CPU_VR4122:
	422	case CPU_VR4131:
	423	case CPU_VR4133:
	424	rtc_resource[0].start = RTC1_TYPE2_START;
	425	rtc_resource[0].end = RTC1_TYPE2_END;
	426	rtc_resource[1].start = RTC2_TYPE2_START;
	427	rtc_resource[1].end = RTC2_TYPE2_END;
	428	break;
	429	default:
	430	return -ENODEV;
	431	break;
	432	}
	433
d39b6cfe	434	rtc_platform_device = platform_device_alloc("RTC", -1);
8417eb7a	435	if (rtc_platform_device == NULL)
d39b6cfe DT	436	return -ENOMEM;
	437
	438	retval = platform_device_add_resources(rtc_platform_device,
	439	rtc_resource, ARRAY_SIZE(rtc_resource));
	440
	441	if (retval == 0)
	442	retval = platform_device_add(rtc_platform_device);
	443
	444	if (retval < 0) {
	445	platform_device_put(rtc_platform_device);
	446	return retval;
	447	}
1da177e4	448
8417eb7a	449	retval = platform_driver_register(&rtc_platform_driver);
1da177e4 LT	450	if (retval < 0)
	451	platform_device_unregister(rtc_platform_device);
	452
	453	return retval;
	454	}
	455
d39b6cfe	456	static void __exit vr41xx_rtc_exit(void)
1da177e4	457	{
8417eb7a	458	platform_driver_unregister(&rtc_platform_driver);
1da177e4 LT	459	platform_device_unregister(rtc_platform_device);
	460	}
	461
	462	module_init(vr41xx_rtc_init);
	463	module_exit(vr41xx_rtc_exit);