[mirror_ubuntu-hirsute-kernel.git] / drivers / s390 / cio / qdio.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright IBM Corp. 2000, 2009
 * Author(s): Utz Bacher <utz.bacher@de.ibm.com>
 *	      Jan Glauber <jang@linux.vnet.ibm.com>
 */
#ifndef _CIO_QDIO_H
#define _CIO_QDIO_H

#include <asm/page.h>
#include <asm/schid.h>
#include <asm/debug.h>
#include "chsc.h"

#define QDIO_BUSY_BIT_PATIENCE		(100 << 12)	/* 100 microseconds */
#define QDIO_BUSY_BIT_RETRY_DELAY	10		/* 10 milliseconds */
#define QDIO_BUSY_BIT_RETRIES		1000		/* = 10s retry time */
#define QDIO_INPUT_THRESHOLD		(500 << 12)	/* 500 microseconds */

enum qdio_irq_states {
	QDIO_IRQ_STATE_INACTIVE,
	QDIO_IRQ_STATE_ESTABLISHED,
	QDIO_IRQ_STATE_ACTIVE,
	QDIO_IRQ_STATE_STOPPED,
	QDIO_IRQ_STATE_CLEANUP,
	QDIO_IRQ_STATE_ERR,
	NR_QDIO_IRQ_STATES,
};

/* used as intparm in do_IO */
#define QDIO_DOING_ESTABLISH	1
#define QDIO_DOING_ACTIVATE	2
#define QDIO_DOING_CLEANUP	3

#define SLSB_STATE_NOT_INIT	0x0
#define SLSB_STATE_EMPTY	0x1
#define SLSB_STATE_PRIMED	0x2
#define SLSB_STATE_PENDING	0x3
#define SLSB_STATE_HALTED	0xe
#define SLSB_STATE_ERROR	0xf
#define SLSB_TYPE_INPUT		0x0
#define SLSB_TYPE_OUTPUT	0x20
#define SLSB_OWNER_PROG		0x80
#define SLSB_OWNER_CU		0x40

#define SLSB_P_INPUT_NOT_INIT	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_NOT_INIT)  /* 0x80 */
#define SLSB_P_INPUT_ACK	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY)	   /* 0x81 */
#define SLSB_CU_INPUT_EMPTY	\
	(SLSB_OWNER_CU | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY)	   /* 0x41 */
#define SLSB_P_INPUT_PRIMED	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_PRIMED)	   /* 0x82 */
#define SLSB_P_INPUT_HALTED	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_HALTED)	   /* 0x8e */
#define SLSB_P_INPUT_ERROR	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_ERROR)	   /* 0x8f */
#define SLSB_P_OUTPUT_NOT_INIT	\
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_NOT_INIT) /* 0xa0 */
#define SLSB_P_OUTPUT_EMPTY	\
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_EMPTY)	   /* 0xa1 */
#define SLSB_P_OUTPUT_PENDING \
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_PENDING)  /* 0xa3 */
#define SLSB_CU_OUTPUT_PRIMED	\
	(SLSB_OWNER_CU | SLSB_TYPE_OUTPUT | SLSB_STATE_PRIMED)	   /* 0x62 */
#define SLSB_P_OUTPUT_HALTED	\
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_HALTED)   /* 0xae */
#define SLSB_P_OUTPUT_ERROR	\
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_ERROR)	   /* 0xaf */

#define SLSB_ERROR_DURING_LOOKUP  0xff

/* additional CIWs returned by extended Sense-ID */
#define CIW_TYPE_EQUEUE			0x3 /* establish QDIO queues */
#define CIW_TYPE_AQUEUE			0x4 /* activate QDIO queues */

/* flags for st qdio sch data */
#define CHSC_FLAG_QDIO_CAPABILITY	0x80
#define CHSC_FLAG_VALIDITY		0x40

/* SIGA flags */
#define QDIO_SIGA_WRITE		0x00
#define QDIO_SIGA_READ		0x01
#define QDIO_SIGA_SYNC		0x02
#define QDIO_SIGA_WRITEM	0x03
#define QDIO_SIGA_WRITEQ	0x04
#define QDIO_SIGA_QEBSM_FLAG	0x80

static inline int do_sqbs(u64 token, unsigned char state, int queue,
			  int *start, int *count)
{
	register unsigned long _ccq asm ("0") = *count;
	register unsigned long _token asm ("1") = token;
	unsigned long _queuestart = ((unsigned long)queue << 32) | *start;

	asm volatile(
		"	.insn	rsy,0xeb000000008A,%1,0,0(%2)"
		: "+d" (_ccq), "+d" (_queuestart)
		: "d" ((unsigned long)state), "d" (_token)
		: "memory", "cc");
	*count = _ccq & 0xff;
	*start = _queuestart & 0xff;

	return (_ccq >> 32) & 0xff;
}

static inline int do_eqbs(u64 token, unsigned char *state, int queue,
			  int *start, int *count, int ack)
{
	register unsigned long _ccq asm ("0") = *count;
	register unsigned long _token asm ("1") = token;
	unsigned long _queuestart = ((unsigned long)queue << 32) | *start;
	unsigned long _state = (unsigned long)ack << 63;

	asm volatile(
		"	.insn	rrf,0xB99c0000,%1,%2,0,0"
		: "+d" (_ccq), "+d" (_queuestart), "+d" (_state)
		: "d" (_token)
		: "memory", "cc");
	*count = _ccq & 0xff;
	*start = _queuestart & 0xff;
	*state = _state & 0xff;

	return (_ccq >> 32) & 0xff;
}

struct qdio_irq;

struct siga_flag {
	u8 input:1;
	u8 output:1;
	u8 sync:1;
	u8 sync_after_ai:1;
	u8 sync_out_after_pci:1;
	u8:3;
} __attribute__ ((packed));

struct qdio_dev_perf_stat {
	unsigned int adapter_int;
	unsigned int qdio_int;
	unsigned int pci_request_int;

	unsigned int tasklet_inbound;
	unsigned int tasklet_inbound_resched;
	unsigned int tasklet_inbound_resched2;
	unsigned int tasklet_outbound;

	unsigned int siga_read;
	unsigned int siga_write;
	unsigned int siga_sync;

	unsigned int inbound_call;
	unsigned int inbound_handler;
	unsigned int stop_polling;
	unsigned int inbound_queue_full;
	unsigned int outbound_call;
	unsigned int outbound_handler;
	unsigned int outbound_queue_full;
	unsigned int fast_requeue;
	unsigned int target_full;
	unsigned int eqbs;
	unsigned int eqbs_partial;
	unsigned int sqbs;
	unsigned int sqbs_partial;
	unsigned int int_discarded;
} ____cacheline_aligned;

struct qdio_queue_perf_stat {
	/*
	 * Sorted into order-2 buckets: 1, 2-3, 4-7, ... 64-127, 128.
	 * Since max. 127 SBALs are scanned reuse entry for 128 as queue full
	 * aka 127 SBALs found.
	 */
	unsigned int nr_sbals[8];
	unsigned int nr_sbal_error;
	unsigned int nr_sbal_nop;
	unsigned int nr_sbal_total;
};

enum qdio_queue_irq_states {
	QDIO_QUEUE_IRQS_DISABLED,
};

struct qdio_input_q {
	/* input buffer acknowledgement flag */
	int polling;
	/* first ACK'ed buffer */
	int ack_start;
	/* how much sbals are acknowledged with qebsm */
	int ack_count;
	/* last time of noticing incoming data */
	u64 timestamp;
	/* upper-layer polling flag */
	unsigned long queue_irq_state;
	/* callback to start upper-layer polling */
	void (*queue_start_poll) (struct ccw_device *, int, unsigned long);
};

struct qdio_output_q {
	/* PCIs are enabled for the queue */
	int pci_out_enabled;
	/* cq: use asynchronous output buffers */
	int use_cq;
	/* cq: aobs used for particual SBAL */
	struct qaob **aobs;
	/* cq: sbal state related to asynchronous operation */
	struct qdio_outbuf_state *sbal_state;
	/* timer to check for more outbound work */
	struct timer_list timer;
};

/*
 * Note on cache alignment: grouped slsb and write mostly data at the beginning
 * sbal[] is read-only and starts on a new cacheline followed by read mostly.
 */
struct qdio_q {
	struct slsb slsb;

	union {
		struct qdio_input_q in;
		struct qdio_output_q out;
	} u;

	/*
	 * inbound: next buffer the program should check for
	 * outbound: next buffer to check if adapter processed it
	 */
	int first_to_check;

	/* beginning position for calling the program */
	int first_to_kick;

	/* number of buffers in use by the adapter */
	atomic_t nr_buf_used;

	/* error condition during a data transfer */
	unsigned int qdio_error;

	/* last scan of the queue */
	u64 timestamp;

	struct tasklet_struct tasklet;
	struct qdio_queue_perf_stat q_stats;

	struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned;

	/* queue number */
	int nr;

	/* bitmask of queue number */
	int mask;

	/* input or output queue */
	int is_input_q;

	/* upper-layer program handler */
	qdio_handler_t (*handler);

	struct dentry *debugfs_q;
	struct qdio_irq *irq_ptr;
	struct sl *sl;
	/*
	 * A page is allocated under this pointer and used for slib and sl.
	 * slib is 2048 bytes big and sl points to offset PAGE_SIZE / 2.
	 */
	struct slib *slib;
} __attribute__ ((aligned(256)));

struct qdio_irq {
	struct qib qib;
	u32 *dsci;		/* address of device state change indicator */
	struct ccw_device *cdev;
	struct list_head entry;		/* list of thinint devices */
	struct dentry *debugfs_dev;
	struct dentry *debugfs_perf;

	unsigned long int_parm;
	struct subchannel_id schid;
	unsigned long sch_token;	/* QEBSM facility */

	enum qdio_irq_states state;

	struct siga_flag siga_flag;	/* siga sync information from qdioac */

	int nr_input_qs;
	int nr_output_qs;

	struct ccw1 ccw;
	struct ciw equeue;
	struct ciw aqueue;

	struct qdio_ssqd_desc ssqd_desc;
	void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *);

	unsigned int scan_threshold;	/* used SBALs before tasklet schedule */
	int perf_stat_enabled;

	struct qdr *qdr;
	unsigned long chsc_page;

	struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ];
	struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ];

	debug_info_t *debug_area;
	struct mutex setup_mutex;
	struct qdio_dev_perf_stat perf_stat;
};

/* helper functions */
#define queue_type(q)	q->irq_ptr->qib.qfmt
#define SCH_NO(q)	(q->irq_ptr->schid.sch_no)

#define is_thinint_irq(irq) \
	(irq->qib.qfmt == QDIO_IQDIO_QFMT || \
	 css_general_characteristics.aif_osa)

#define qperf(__qdev, __attr)	((__qdev)->perf_stat.(__attr))

#define QDIO_PERF_STAT_INC(__irq, __attr)				\
({									\
	struct qdio_irq *qdev = __irq;					\
	if (qdev->perf_stat_enabled)					\
		(qdev->perf_stat.__attr)++;				\
})

#define qperf_inc(__q, __attr)	QDIO_PERF_STAT_INC((__q)->irq_ptr, __attr)

static inline void account_sbals_error(struct qdio_q *q, int count)
{
	q->q_stats.nr_sbal_error += count;
	q->q_stats.nr_sbal_total += count;
}

/* the highest iqdio queue is used for multicast */
static inline int multicast_outbound(struct qdio_q *q)
{
	return (q->irq_ptr->nr_output_qs > 1) &&
	       (q->nr == q->irq_ptr->nr_output_qs - 1);
}

#define pci_out_supported(irq) ((irq)->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED)
#define is_qebsm(q)			(q->irq_ptr->sch_token != 0)

#define need_siga_in(q)			(q->irq_ptr->siga_flag.input)
#define need_siga_out(q)		(q->irq_ptr->siga_flag.output)
#define need_siga_sync(q)		(unlikely(q->irq_ptr->siga_flag.sync))
#define need_siga_sync_after_ai(q)	\
	(unlikely(q->irq_ptr->siga_flag.sync_after_ai))
#define need_siga_sync_out_after_pci(q)	\
	(unlikely(q->irq_ptr->siga_flag.sync_out_after_pci))

#define for_each_input_queue(irq_ptr, q, i)		\
	for (i = 0; i < irq_ptr->nr_input_qs &&		\
		({ q = irq_ptr->input_qs[i]; 1; }); i++)
#define for_each_output_queue(irq_ptr, q, i)		\
	for (i = 0; i < irq_ptr->nr_output_qs &&	\
		({ q = irq_ptr->output_qs[i]; 1; }); i++)

#define add_buf(bufnr, inc)	QDIO_BUFNR((bufnr) + (inc))
#define next_buf(bufnr)		add_buf(bufnr, 1)
#define sub_buf(bufnr, dec)	QDIO_BUFNR((bufnr) - (dec))
#define prev_buf(bufnr)		sub_buf(bufnr, 1)

#define queue_irqs_enabled(q)			\
	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) == 0)
#define queue_irqs_disabled(q)			\
	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) != 0)

extern u64 last_ai_time;

/* prototypes for thin interrupt */
void qdio_setup_thinint(struct qdio_irq *irq_ptr);
int qdio_establish_thinint(struct qdio_irq *irq_ptr);
void qdio_shutdown_thinint(struct qdio_irq *irq_ptr);
void tiqdio_add_device(struct qdio_irq *irq_ptr);
void tiqdio_remove_device(struct qdio_irq *irq_ptr);
void tiqdio_inbound_processing(unsigned long q);
int tiqdio_allocate_memory(void);
void tiqdio_free_memory(void);
int tiqdio_register_thinints(void);
void tiqdio_unregister_thinints(void);
void clear_nonshared_ind(struct qdio_irq *);
int test_nonshared_ind(struct qdio_irq *);

/* prototypes for setup */
void qdio_inbound_processing(unsigned long data);
void qdio_outbound_processing(unsigned long data);
void qdio_outbound_timer(struct timer_list *t);
void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm,
		      struct irb *irb);
int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs,
		     int nr_output_qs);
void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr);
int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr,
			struct subchannel_id *schid,
			struct qdio_ssqd_desc *data);
int qdio_setup_irq(struct qdio_initialize *init_data);
void qdio_print_subchannel_info(struct qdio_irq *irq_ptr,
				struct ccw_device *cdev);
void qdio_release_memory(struct qdio_irq *irq_ptr);
int qdio_setup_create_sysfs(struct ccw_device *cdev);
void qdio_setup_destroy_sysfs(struct ccw_device *cdev);
int qdio_setup_init(void);
void qdio_setup_exit(void);
int qdio_enable_async_operation(struct qdio_output_q *q);
void qdio_disable_async_operation(struct qdio_output_q *q);
struct qaob *qdio_allocate_aob(void);

int debug_get_buf_state(struct qdio_q *q, unsigned int bufnr,
			unsigned char *state);
#endif /* _CIO_QDIO_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
779e6e1c	2	/*
a53c8fab	3	* Copyright IBM Corp. 2000, 2009
779e6e1c JG	4	* Author(s): Utz Bacher <utz.bacher@de.ibm.com>
	5	* Jan Glauber <jang@linux.vnet.ibm.com>
	6	*/
1da177e4 LT	7	#ifndef _CIO_QDIO_H
	8	#define _CIO_QDIO_H
	9
0b642ede	10	#include <asm/page.h>
9d92a7e1	11	#include <asm/schid.h>
22f99347	12	#include <asm/debug.h>
779e6e1c	13	#include "chsc.h"
a8237fc4	14
3a601bfe	15	#define QDIO_BUSY_BIT_PATIENCE (100 << 12) /* 100 microseconds */
be8d97a5 JG	16	#define QDIO_BUSY_BIT_RETRY_DELAY 10 /* 10 milliseconds */
be8d97a5 JG	17	#define QDIO_BUSY_BIT_RETRIES 1000 /* = 10s retry time */
3a601bfe	18	#define QDIO_INPUT_THRESHOLD (500 << 12) /* 500 microseconds */
1da177e4 LT	19
	20	enum qdio_irq_states {
	21	QDIO_IRQ_STATE_INACTIVE,
	22	QDIO_IRQ_STATE_ESTABLISHED,
	23	QDIO_IRQ_STATE_ACTIVE,
	24	QDIO_IRQ_STATE_STOPPED,
	25	QDIO_IRQ_STATE_CLEANUP,
	26	QDIO_IRQ_STATE_ERR,
	27	NR_QDIO_IRQ_STATES,
	28	};
	29
779e6e1c JG	30	/* used as intparm in do_IO */
	31	#define QDIO_DOING_ESTABLISH 1
	32	#define QDIO_DOING_ACTIVATE 2
	33	#define QDIO_DOING_CLEANUP 3
	34
	35	#define SLSB_STATE_NOT_INIT 0x0
	36	#define SLSB_STATE_EMPTY 0x1
	37	#define SLSB_STATE_PRIMED 0x2
104ea556	38	#define SLSB_STATE_PENDING 0x3
779e6e1c JG	39	#define SLSB_STATE_HALTED 0xe
	40	#define SLSB_STATE_ERROR 0xf
	41	#define SLSB_TYPE_INPUT 0x0
	42	#define SLSB_TYPE_OUTPUT 0x20
	43	#define SLSB_OWNER_PROG 0x80
	44	#define SLSB_OWNER_CU 0x40
	45
	46	#define SLSB_P_INPUT_NOT_INIT \
	47	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_NOT_INIT) /* 0x80 */
	48	#define SLSB_P_INPUT_ACK \
	49	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_EMPTY) /* 0x81 */
	50	#define SLSB_CU_INPUT_EMPTY \
	51	(SLSB_OWNER_CU \| SLSB_TYPE_INPUT \| SLSB_STATE_EMPTY) /* 0x41 */
	52	#define SLSB_P_INPUT_PRIMED \
	53	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_PRIMED) /* 0x82 */
	54	#define SLSB_P_INPUT_HALTED \
	55	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_HALTED) /* 0x8e */
	56	#define SLSB_P_INPUT_ERROR \
	57	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_ERROR) /* 0x8f */
	58	#define SLSB_P_OUTPUT_NOT_INIT \
	59	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_NOT_INIT) /* 0xa0 */
	60	#define SLSB_P_OUTPUT_EMPTY \
	61	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_EMPTY) /* 0xa1 */
104ea556	62	#define SLSB_P_OUTPUT_PENDING \
104ea556	63	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_PENDING) /* 0xa3 */
779e6e1c JG	64	#define SLSB_CU_OUTPUT_PRIMED \
	65	(SLSB_OWNER_CU \| SLSB_TYPE_OUTPUT \| SLSB_STATE_PRIMED) /* 0x62 */
	66	#define SLSB_P_OUTPUT_HALTED \
	67	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_HALTED) /* 0xae */
	68	#define SLSB_P_OUTPUT_ERROR \
	69	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_ERROR) /* 0xaf */
	70
	71	#define SLSB_ERROR_DURING_LOOKUP 0xff
	72
	73	/* additional CIWs returned by extended Sense-ID */
	74	#define CIW_TYPE_EQUEUE 0x3 /* establish QDIO queues */
	75	#define CIW_TYPE_AQUEUE 0x4 /* activate QDIO queues */
1da177e4	76
779e6e1c JG	77	/* flags for st qdio sch data */
	78	#define CHSC_FLAG_QDIO_CAPABILITY 0x80
	79	#define CHSC_FLAG_VALIDITY 0x40
	80
958c0ba4 JG	81	/* SIGA flags */
	82	#define QDIO_SIGA_WRITE 0x00
	83	#define QDIO_SIGA_READ 0x01
	84	#define QDIO_SIGA_SYNC 0x02
b7f143d0	85	#define QDIO_SIGA_WRITEM 0x03
104ea556	86	#define QDIO_SIGA_WRITEQ 0x04
958c0ba4 JG	87	#define QDIO_SIGA_QEBSM_FLAG 0x80
958c0ba4 JG	88
779e6e1c JG	89	static inline int do_sqbs(u64 token, unsigned char state, int queue,
	90	int start, int count)
	91	{
	92	register unsigned long _ccq asm ("0") = *count;
	93	register unsigned long _token asm ("1") = token;
	94	unsigned long _queuestart = ((unsigned long)queue << 32) \| *start;
1da177e4	95
779e6e1c JG	96	asm volatile(
	97	" .insn rsy,0xeb000000008A,%1,0,0(%2)"
	98	: "+d" (_ccq), "+d" (_queuestart)
	99	: "d" ((unsigned long)state), "d" (_token)
	100	: "memory", "cc");
	101	*count = _ccq & 0xff;
	102	*start = _queuestart & 0xff;
8129ee16	103
779e6e1c	104	return (_ccq >> 32) & 0xff;
8129ee16 FP	105	}
8129ee16 FP	106
779e6e1c	107	static inline int do_eqbs(u64 token, unsigned char *state, int queue,
50f769df	108	int start, int count, int ack)
8129ee16	109	{
8129ee16	110	register unsigned long _ccq asm ("0") = *count;
779e6e1c	111	register unsigned long _token asm ("1") = token;
8129ee16	112	unsigned long _queuestart = ((unsigned long)queue << 32) \| *start;
50f769df	113	unsigned long _state = (unsigned long)ack << 63;
8129ee16	114
94c12cc7 MS	115	asm volatile(
	116	" .insn rrf,0xB99c0000,%1,%2,0,0"
	117	: "+d" (_ccq), "+d" (_queuestart), "+d" (_state)
779e6e1c JG	118	: "d" (_token)
779e6e1c JG	119	: "memory", "cc");
8129ee16 FP	120	*count = _ccq & 0xff;
	121	*start = _queuestart & 0xff;
	122	*state = _state & 0xff;
	123
	124	return (_ccq >> 32) & 0xff;
1da177e4	125	}
1da177e4	126
779e6e1c	127	struct qdio_irq;
1da177e4	128
779e6e1c JG	129	struct siga_flag {
	130	u8 input:1;
	131	u8 output:1;
	132	u8 sync:1;
90adac58 JG	133	u8 sync_after_ai:1;
	134	u8 sync_out_after_pci:1;
	135	u8:3;
779e6e1c	136	} __attribute__ ((packed));
1da177e4	137
6486cda6 JG	138	struct qdio_dev_perf_stat {
	139	unsigned int adapter_int;
	140	unsigned int qdio_int;
	141	unsigned int pci_request_int;
	142
	143	unsigned int tasklet_inbound;
	144	unsigned int tasklet_inbound_resched;
	145	unsigned int tasklet_inbound_resched2;
	146	unsigned int tasklet_outbound;
	147
	148	unsigned int siga_read;
	149	unsigned int siga_write;
	150	unsigned int siga_sync;
	151
	152	unsigned int inbound_call;
	153	unsigned int inbound_handler;
	154	unsigned int stop_polling;
	155	unsigned int inbound_queue_full;
	156	unsigned int outbound_call;
	157	unsigned int outbound_handler;
0195843b	158	unsigned int outbound_queue_full;
6486cda6 JG	159	unsigned int fast_requeue;
	160	unsigned int target_full;
	161	unsigned int eqbs;
	162	unsigned int eqbs_partial;
	163	unsigned int sqbs;
	164	unsigned int sqbs_partial;
d36deae7	165	unsigned int int_discarded;
432ac5e0	166	} ____cacheline_aligned;
6486cda6	167
d307297f JG	168	struct qdio_queue_perf_stat {
	169	/*
	170	* Sorted into order-2 buckets: 1, 2-3, 4-7, ... 64-127, 128.
	171	* Since max. 127 SBALs are scanned reuse entry for 128 as queue full
	172	* aka 127 SBALs found.
	173	*/
	174	unsigned int nr_sbals[8];
	175	unsigned int nr_sbal_error;
	176	unsigned int nr_sbal_nop;
	177	unsigned int nr_sbal_total;
	178	};
	179
d36deae7 JG	180	enum qdio_queue_irq_states {
	181	QDIO_QUEUE_IRQS_DISABLED,
	182	};
	183
779e6e1c JG	184	struct qdio_input_q {
	185	/* input buffer acknowledgement flag */
	186	int polling;
e85dea0e JG	187	/* first ACK'ed buffer */
e85dea0e JG	188	int ack_start;
50f769df JG	189	/* how much sbals are acknowledged with qebsm */
50f769df JG	190	int ack_count;
779e6e1c JG	191	/* last time of noticing incoming data */
779e6e1c JG	192	u64 timestamp;
d36deae7 JG	193	/* upper-layer polling flag */
	194	unsigned long queue_irq_state;
	195	/* callback to start upper-layer polling */
	196	void (queue_start_poll) (struct ccw_device , int, unsigned long);
1da177e4	197	};
1da177e4	198
779e6e1c	199	struct qdio_output_q {
779e6e1c JG	200	/* PCIs are enabled for the queue */
779e6e1c JG	201	int pci_out_enabled;
104ea556	202	/* cq: use asynchronous output buffers */
	203	int use_cq;
	204	/* cq: aobs used for particual SBAL */
	205	struct qaob **aobs;
	206	/* cq: sbal state related to asynchronous operation */
	207	struct qdio_outbuf_state *sbal_state;
779e6e1c JG	208	/* timer to check for more outbound work */
	209	struct timer_list timer;
	210	};
1da177e4	211
d307297f JG	212	/*
	213	* Note on cache alignment: grouped slsb and write mostly data at the beginning
	214	* sbal[] is read-only and starts on a new cacheline followed by read mostly.
	215	*/
1da177e4	216	struct qdio_q {
779e6e1c	217	struct slsb slsb;
d307297f	218
779e6e1c JG	219	union {
	220	struct qdio_input_q in;
	221	struct qdio_output_q out;
	222	} u;
1da177e4	223
779e6e1c JG	224	/*
779e6e1c JG	225	* inbound: next buffer the program should check for
d307297f	226	* outbound: next buffer to check if adapter processed it
779e6e1c JG	227	*/
779e6e1c JG	228	int first_to_check;
1da177e4	229
779e6e1c JG	230	/* beginning position for calling the program */
779e6e1c JG	231	int first_to_kick;
1da177e4	232
779e6e1c JG	233	/* number of buffers in use by the adapter */
779e6e1c JG	234	atomic_t nr_buf_used;
1da177e4	235
779e6e1c	236	/* error condition during a data transfer */
1da177e4	237	unsigned int qdio_error;
1da177e4	238
a2b86019 JG	239	/* last scan of the queue */
	240	u64 timestamp;
	241
d307297f JG	242	struct tasklet_struct tasklet;
	243	struct qdio_queue_perf_stat q_stats;
	244
	245	struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned;
	246
	247	/* queue number */
	248	int nr;
	249
	250	/* bitmask of queue number */
	251	int mask;
	252
	253	/* input or output queue */
	254	int is_input_q;
	255
d307297f JG	256	/* upper-layer program handler */
d307297f JG	257	qdio_handler_t (*handler);
779e6e1c	258
d307297f JG	259	struct dentry *debugfs_q;
	260	struct qdio_irq *irq_ptr;
	261	struct sl *sl;
779e6e1c	262	/*
5382fe11 JG	263	* A page is allocated under this pointer and used for slib and sl.
5382fe11 JG	264	* slib is 2048 bytes big and sl points to offset PAGE_SIZE / 2.
779e6e1c JG	265	*/
779e6e1c JG	266	struct slib *slib;
1da177e4 LT	267	} __attribute__ ((aligned(256)));
	268
	269	struct qdio_irq {
779e6e1c JG	270	struct qib qib;
	271	u32 dsci; / address of device state change indicator */
	272	struct ccw_device *cdev;
94c43bda	273	struct list_head entry; /* list of thinint devices */
3f09bb89	274	struct dentry *debugfs_dev;
6486cda6	275	struct dentry *debugfs_perf;
1da177e4 LT	276
1da177e4 LT	277	unsigned long int_parm;
a8237fc4	278	struct subchannel_id schid;
779e6e1c	279	unsigned long sch_token; /* QEBSM facility */
8129ee16	280
1da177e4 LT	281	enum qdio_irq_states state;
1da177e4 LT	282
779e6e1c	283	struct siga_flag siga_flag; /* siga sync information from qdioac */
1da177e4	284
779e6e1c JG	285	int nr_input_qs;
779e6e1c JG	286	int nr_output_qs;
1da177e4 LT	287
1da177e4 LT	288	struct ccw1 ccw;
1da177e4 LT	289	struct ciw equeue;
	290	struct ciw aqueue;
	291
779e6e1c	292	struct qdio_ssqd_desc ssqd_desc;
779e6e1c	293	void (orig_handler) (struct ccw_device , unsigned long, struct irb *);
1da177e4	294
313dc689	295	unsigned int scan_threshold; /* used SBALs before tasklet schedule */
6486cda6	296	int perf_stat_enabled;
432ac5e0	297
1da177e4	298	struct qdr *qdr;
779e6e1c JG	299	unsigned long chsc_page;
779e6e1c JG	300
1da177e4 LT	301	struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ];
1da177e4 LT	302	struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ];
779e6e1c	303
22f99347	304	debug_info_t *debug_area;
779e6e1c	305	struct mutex setup_mutex;
432ac5e0	306	struct qdio_dev_perf_stat perf_stat;
1da177e4	307	};
779e6e1c JG	308
	309	/* helper functions */
	310	#define queue_type(q) q->irq_ptr->qib.qfmt
22f99347	311	#define SCH_NO(q) (q->irq_ptr->schid.sch_no)
779e6e1c JG	312
	313	#define is_thinint_irq(irq) \
	314	(irq->qib.qfmt == QDIO_IQDIO_QFMT \|\| \
	315	css_general_characteristics.aif_osa)
	316
d307297f JG	317	#define qperf(__qdev, __attr) ((__qdev)->perf_stat.(__attr))
d307297f JG	318
46112810	319	#define QDIO_PERF_STAT_INC(__irq, __attr) \
d307297f	320	({ \
46112810	321	struct qdio_irq *qdev = __irq; \
d307297f JG	322	if (qdev->perf_stat_enabled) \
	323	(qdev->perf_stat.__attr)++; \
	324	})
	325
46112810 JW	326	#define qperf_inc(__q, __attr) QDIO_PERF_STAT_INC((__q)->irq_ptr, __attr)
46112810 JW	327
d307297f JG	328	static inline void account_sbals_error(struct qdio_q *q, int count)
	329	{
	330	q->q_stats.nr_sbal_error += count;
	331	q->q_stats.nr_sbal_total += count;
	332	}
6486cda6	333
779e6e1c JG	334	/* the highest iqdio queue is used for multicast */
	335	static inline int multicast_outbound(struct qdio_q *q)
	336	{
	337	return (q->irq_ptr->nr_output_qs > 1) &&
	338	(q->nr == q->irq_ptr->nr_output_qs - 1);
	339	}
	340
f85b2b29	341	#define pci_out_supported(irq) ((irq)->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED)
779e6e1c JG	342	#define is_qebsm(q) (q->irq_ptr->sch_token != 0)
779e6e1c JG	343
779e6e1c JG	344	#define need_siga_in(q) (q->irq_ptr->siga_flag.input)
779e6e1c JG	345	#define need_siga_out(q) (q->irq_ptr->siga_flag.output)
90adac58 JG	346	#define need_siga_sync(q) (unlikely(q->irq_ptr->siga_flag.sync))
	347	#define need_siga_sync_after_ai(q) \
	348	(unlikely(q->irq_ptr->siga_flag.sync_after_ai))
	349	#define need_siga_sync_out_after_pci(q) \
	350	(unlikely(q->irq_ptr->siga_flag.sync_out_after_pci))
779e6e1c	351
dbb0dd02 JA	352	#define for_each_input_queue(irq_ptr, q, i) \
	353	for (i = 0; i < irq_ptr->nr_input_qs && \
	354	({ q = irq_ptr->input_qs[i]; 1; }); i++)
	355	#define for_each_output_queue(irq_ptr, q, i) \
	356	for (i = 0; i < irq_ptr->nr_output_qs && \
	357	({ q = irq_ptr->output_qs[i]; 1; }); i++)
779e6e1c	358
a320412d JW	359	#define add_buf(bufnr, inc) QDIO_BUFNR((bufnr) + (inc))
	360	#define next_buf(bufnr) add_buf(bufnr, 1)
	361	#define sub_buf(bufnr, dec) QDIO_BUFNR((bufnr) - (dec))
	362	#define prev_buf(bufnr) sub_buf(bufnr, 1)
779e6e1c	363
d36deae7 JG	364	#define queue_irqs_enabled(q) \
	365	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) == 0)
	366	#define queue_irqs_disabled(q) \
	367	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) != 0)
	368
a2b86019 JG	369	extern u64 last_ai_time;
a2b86019 JG	370
779e6e1c	371	/* prototypes for thin interrupt */
779e6e1c JG	372	void qdio_setup_thinint(struct qdio_irq *irq_ptr);
	373	int qdio_establish_thinint(struct qdio_irq *irq_ptr);
	374	void qdio_shutdown_thinint(struct qdio_irq *irq_ptr);
94c43bda JW	375	void tiqdio_add_device(struct qdio_irq *irq_ptr);
94c43bda JW	376	void tiqdio_remove_device(struct qdio_irq *irq_ptr);
779e6e1c JG	377	void tiqdio_inbound_processing(unsigned long q);
	378	int tiqdio_allocate_memory(void);
	379	void tiqdio_free_memory(void);
	380	int tiqdio_register_thinints(void);
	381	void tiqdio_unregister_thinints(void);
5f4026f8 JG	382	void clear_nonshared_ind(struct qdio_irq *);
5f4026f8 JG	383	int test_nonshared_ind(struct qdio_irq *);
104ea556	384
779e6e1c JG	385	/* prototypes for setup */
	386	void qdio_inbound_processing(unsigned long data);
	387	void qdio_outbound_processing(unsigned long data);
cb9f780a	388	void qdio_outbound_timer(struct timer_list *t);
779e6e1c JG	389	void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm,
	390	struct irb *irb);
	391	int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs,
	392	int nr_output_qs);
	393	void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr);
bbd50e17 JG	394	int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr,
	395	struct subchannel_id *schid,
	396	struct qdio_ssqd_desc *data);
779e6e1c JG	397	int qdio_setup_irq(struct qdio_initialize *init_data);
	398	void qdio_print_subchannel_info(struct qdio_irq *irq_ptr,
	399	struct ccw_device *cdev);
	400	void qdio_release_memory(struct qdio_irq *irq_ptr);
50f769df JG	401	int qdio_setup_create_sysfs(struct ccw_device *cdev);
50f769df JG	402	void qdio_setup_destroy_sysfs(struct ccw_device *cdev);
779e6e1c JG	403	int qdio_setup_init(void);
779e6e1c JG	404	void qdio_setup_exit(void);
104ea556	405	int qdio_enable_async_operation(struct qdio_output_q *q);
	406	void qdio_disable_async_operation(struct qdio_output_q *q);
	407	struct qaob *qdio_allocate_aob(void);
779e6e1c	408
60b5df2f JG	409	int debug_get_buf_state(struct qdio_q *q, unsigned int bufnr,
60b5df2f JG	410	unsigned char *state);
779e6e1c	411	#endif /* _CIO_QDIO_H */