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scsi: aacraid: Added support to abort cmd and reset lun
[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / aacraid / src.c
CommitLineData
e8b12f0f
MR		 1/*
2 * Adaptec AAC series RAID controller driver
3 * (c) Copyright 2001 Red Hat Inc.
4 *
5 * based on the old aacraid driver that is..
6 * Adaptec aacraid device driver for Linux.
7 *
8 * Copyright (c) 2000-2010 Adaptec, Inc.
9 * 2010 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Module Name:
26 * src.c
27 *
28 * Abstract: Hardware Device Interface for PMC SRC based controllers
29 *
30 */
31
32#include <linux/kernel.h>
33#include <linux/init.h>
34#include <linux/types.h>
35#include <linux/pci.h>
36#include <linux/spinlock.h>
37#include <linux/slab.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
e8b12f0f
MR		 40#include <linux/completion.h>
41#include <linux/time.h>
42#include <linux/interrupt.h>
43#include <scsi/scsi_host.h>
44
45#include "aacraid.h"
46
495c0217
MR		 47static int aac_src_get_sync_status(struct aac_dev *dev);
48
305974fe 49static irqreturn_t aac_src_intr_message(int irq, void *dev_id)
e8b12f0f 50{
495c0217
MR		 51 struct aac_msix_ctx *ctx;
52 struct aac_dev *dev;
e8b12f0f 53 unsigned long bellbits, bellbits_shifted;
495c0217
MR		 54 int vector_no;
55 int isFastResponse, mode;
e8b12f0f
MR		 56 u32 index, handle;
57
495c0217
MR		 58 ctx = (struct aac_msix_ctx *)dev_id;
59 dev = ctx->dev;
60 vector_no = ctx->vector_no;
61
62 if (dev->msi_enabled) {
63 mode = AAC_INT_MODE_MSI;
64 if (vector_no == 0) {
65 bellbits = src_readl(dev, MUnit.ODR_MSI);
66 if (bellbits & 0x40000)
67 mode |= AAC_INT_MODE_AIF;
68 if (bellbits & 0x1000)
69 mode |= AAC_INT_MODE_SYNC;
e8b12f0f
MR		 70 }
71 } else {
495c0217
MR		 72 mode = AAC_INT_MODE_INTX;
73 bellbits = src_readl(dev, MUnit.ODR_R);
74 if (bellbits & PmDoorBellResponseSent) {
75 bellbits = PmDoorBellResponseSent;
76 src_writel(dev, MUnit.ODR_C, bellbits);
77 src_readl(dev, MUnit.ODR_C);
78 } else {
79 bellbits_shifted = (bellbits >> SRC_ODR_SHIFT);
85d22bbf
MR		 80 src_writel(dev, MUnit.ODR_C, bellbits);
81 src_readl(dev, MUnit.ODR_C);
85d22bbf 82
495c0217
MR		 83 if (bellbits_shifted & DoorBellAifPending)
84 mode |= AAC_INT_MODE_AIF;
85 else if (bellbits_shifted & OUTBOUNDDOORBELL_0)
86 mode |= AAC_INT_MODE_SYNC;
87 }
88 }
89
90 if (mode & AAC_INT_MODE_SYNC) {
91 unsigned long sflags;
92 struct list_head *entry;
93 int send_it = 0;
94 extern int aac_sync_mode;
95
96 if (!aac_sync_mode && !dev->msi_enabled) {
c5bebd82
MR		 97 src_writel(dev, MUnit.ODR_C, bellbits);
98 src_readl(dev, MUnit.ODR_C);
495c0217 99 }
c5bebd82 100
495c0217
MR		 101 if (dev->sync_fib) {
102 if (dev->sync_fib->callback)
103 dev->sync_fib->callback(dev->sync_fib->callback_data,
104 dev->sync_fib);
105 spin_lock_irqsave(&dev->sync_fib->event_lock, sflags);
106 if (dev->sync_fib->flags & FIB_CONTEXT_FLAG_WAIT) {
107 dev->management_fib_count--;
108 up(&dev->sync_fib->event_wait);
85d22bbf 109 }
495c0217
MR		 110 spin_unlock_irqrestore(&dev->sync_fib->event_lock,
111 sflags);
112 spin_lock_irqsave(&dev->sync_lock, sflags);
113 if (!list_empty(&dev->sync_fib_list)) {
114 entry = dev->sync_fib_list.next;
115 dev->sync_fib = list_entry(entry,
116 struct fib,
117 fiblink);
118 list_del(entry);
119 send_it = 1;
120 } else {
121 dev->sync_fib = NULL;
122 }
123 spin_unlock_irqrestore(&dev->sync_lock, sflags);
124 if (send_it) {
125 aac_adapter_sync_cmd(dev, SEND_SYNCHRONOUS_FIB,
126 (u32)dev->sync_fib->hw_fib_pa,
127 0, 0, 0, 0, 0,
128 NULL, NULL, NULL, NULL, NULL);
11604612 129 }
e8b12f0f 130 }
495c0217
MR		 131 if (!dev->msi_enabled)
132 mode = 0;
133
e8b12f0f
MR		 134 }
135
495c0217
MR		 136 if (mode & AAC_INT_MODE_AIF) {
137 /* handle AIF */
932cc3d3
RAR		 138 if (dev->sa_firmware) {
139 u32 events = src_readl(dev, MUnit.SCR0);
140
141 aac_intr_normal(dev, events, 1, 0, NULL);
142 writel(events, &dev->IndexRegs->Mailbox[0]);
143 src_writel(dev, MUnit.IDR, 1 << 23);
144 } else {
145 if (dev->aif_thread && dev->fsa_dev)
146 aac_intr_normal(dev, 0, 2, 0, NULL);
147 }
495c0217
MR		 148 if (dev->msi_enabled)
149 aac_src_access_devreg(dev, AAC_CLEAR_AIF_BIT);
150 mode = 0;
e8b12f0f 151 }
495c0217
MR		 152
153 if (mode) {
154 index = dev->host_rrq_idx[vector_no];
155
156 for (;;) {
157 isFastResponse = 0;
158 /* remove toggle bit (31) */
932cc3d3
RAR		 159 handle = le32_to_cpu((dev->host_rrq[index])
160 & 0x7fffffff);
161 /* check fast response bits (30, 1) */
495c0217
MR		 162 if (handle & 0x40000000)
163 isFastResponse = 1;
164 handle &= 0x0000ffff;
165 if (handle == 0)
166 break;
932cc3d3 167 handle >>= 2;
495c0217
MR		 168 if (dev->msi_enabled && dev->max_msix > 1)
169 atomic_dec(&dev->rrq_outstanding[vector_no]);
932cc3d3 170 aac_intr_normal(dev, handle, 0, isFastResponse, NULL);
495c0217
MR		 171 dev->host_rrq[index++] = 0;
172 if (index == (vector_no + 1) * dev->vector_cap)
173 index = vector_no * dev->vector_cap;
174 dev->host_rrq_idx[vector_no] = index;
175 }
176 mode = 0;
177 }
178
179 return IRQ_HANDLED;
e8b12f0f
MR		 180}
181
182/**
183 * aac_src_disable_interrupt - Disable interrupts
184 * @dev: Adapter
185 */
186
187static void aac_src_disable_interrupt(struct aac_dev *dev)
188{
189 src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
190}
191
192/**
193 * aac_src_enable_interrupt_message - Enable interrupts
194 * @dev: Adapter
195 */
196
197static void aac_src_enable_interrupt_message(struct aac_dev *dev)
198{
495c0217 199 aac_src_access_devreg(dev, AAC_ENABLE_INTERRUPT);
e8b12f0f
MR		 200}
201
202/**
203 * src_sync_cmd - send a command and wait
204 * @dev: Adapter
205 * @command: Command to execute
206 * @p1: first parameter
207 * @ret: adapter status
208 *
209 * This routine will send a synchronous command to the adapter and wait
210 * for its completion.
211 */
212
213static int src_sync_cmd(struct aac_dev *dev, u32 command,
214 u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6,
215 u32 *status, u32 * r1, u32 * r2, u32 * r3, u32 * r4)
216{
217 unsigned long start;
dafde947 218 unsigned long delay;
e8b12f0f
MR		 219 int ok;
220
221 /*
222 * Write the command into Mailbox 0
223 */
224 writel(command, &dev->IndexRegs->Mailbox[0]);
225 /*
226 * Write the parameters into Mailboxes 1 - 6
227 */
228 writel(p1, &dev->IndexRegs->Mailbox[1]);
229 writel(p2, &dev->IndexRegs->Mailbox[2]);
230 writel(p3, &dev->IndexRegs->Mailbox[3]);
231 writel(p4, &dev->IndexRegs->Mailbox[4]);
232
233 /*
234 * Clear the synch command doorbell to start on a clean slate.
235 */
495c0217
MR		 236 if (!dev->msi_enabled)
237 src_writel(dev,
238 MUnit.ODR_C,
239 OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
e8b12f0f
MR		 240
241 /*
242 * Disable doorbell interrupts
243 */
244 src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
245
246 /*
247 * Force the completion of the mask register write before issuing
248 * the interrupt.
249 */
250 src_readl(dev, MUnit.OIMR);
251
252 /*
253 * Signal that there is a new synch command
254 */
255 src_writel(dev, MUnit.IDR, INBOUNDDOORBELL_0 << SRC_IDR_SHIFT);
256
11604612
MR		 257 if (!dev->sync_mode || command != SEND_SYNCHRONOUS_FIB) {
258 ok = 0;
259 start = jiffies;
e8b12f0f 260
dafde947
MR		 261 if (command == IOP_RESET_ALWAYS) {
262 /* Wait up to 10 sec */
263 delay = 10*HZ;
264 } else {
265 /* Wait up to 5 minutes */
266 delay = 300*HZ;
267 }
268 while (time_before(jiffies, start+delay)) {
11604612
MR		 269 udelay(5); /* Delay 5 microseconds to let Mon960 get info. */
270 /*
271 * Mon960 will set doorbell0 bit when it has completed the command.
272 */
495c0217 273 if (aac_src_get_sync_status(dev) & OUTBOUNDDOORBELL_0) {
11604612
MR		 274 /*
275 * Clear the doorbell.
276 */
495c0217
MR		 277 if (dev->msi_enabled)
278 aac_src_access_devreg(dev,
279 AAC_CLEAR_SYNC_BIT);
280 else
281 src_writel(dev,
282 MUnit.ODR_C,
283 OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
11604612
MR		 284 ok = 1;
285 break;
286 }
287 /*
288 * Yield the processor in case we are slow
289 */
290 msleep(1);
e8b12f0f 291 }
11604612
MR		 292 if (unlikely(ok != 1)) {
293 /*
294 * Restore interrupt mask even though we timed out
295 */
296 aac_adapter_enable_int(dev);
297 return -ETIMEDOUT;
298 }
299 /*
300 * Pull the synch status from Mailbox 0.
301 */
302 if (status)
303 *status = readl(&dev->IndexRegs->Mailbox[0]);
304 if (r1)
305 *r1 = readl(&dev->IndexRegs->Mailbox[1]);
306 if (r2)
307 *r2 = readl(&dev->IndexRegs->Mailbox[2]);
308 if (r3)
309 *r3 = readl(&dev->IndexRegs->Mailbox[3]);
310 if (r4)
311 *r4 = readl(&dev->IndexRegs->Mailbox[4]);
495c0217
MR		 312 if (command == GET_COMM_PREFERRED_SETTINGS)
313 dev->max_msix =
314 readl(&dev->IndexRegs->Mailbox[5]) & 0xFFFF;
11604612
MR		 315 /*
316 * Clear the synch command doorbell.
317 */
495c0217
MR		 318 if (!dev->msi_enabled)
319 src_writel(dev,
320 MUnit.ODR_C,
321 OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
e8b12f0f
MR		 322 }
323
11604612
MR		 324 /*
325 * Restore interrupt mask
326 */
e8b12f0f
MR		 327 aac_adapter_enable_int(dev);
328 return 0;
e8b12f0f
MR		 329}
330
331/**
332 * aac_src_interrupt_adapter - interrupt adapter
333 * @dev: Adapter
334 *
335 * Send an interrupt to the i960 and breakpoint it.
336 */
337
338static void aac_src_interrupt_adapter(struct aac_dev *dev)
339{
340 src_sync_cmd(dev, BREAKPOINT_REQUEST,
341 0, 0, 0, 0, 0, 0,
342 NULL, NULL, NULL, NULL, NULL);
343}
344
345/**
346 * aac_src_notify_adapter - send an event to the adapter
347 * @dev: Adapter
348 * @event: Event to send
349 *
350 * Notify the i960 that something it probably cares about has
351 * happened.
352 */
353
354static void aac_src_notify_adapter(struct aac_dev *dev, u32 event)
355{
356 switch (event) {
357
358 case AdapNormCmdQue:
359 src_writel(dev, MUnit.ODR_C,
360 INBOUNDDOORBELL_1 << SRC_ODR_SHIFT);
361 break;
362 case HostNormRespNotFull:
363 src_writel(dev, MUnit.ODR_C,
364 INBOUNDDOORBELL_4 << SRC_ODR_SHIFT);
365 break;
366 case AdapNormRespQue:
367 src_writel(dev, MUnit.ODR_C,
368 INBOUNDDOORBELL_2 << SRC_ODR_SHIFT);
369 break;
370 case HostNormCmdNotFull:
371 src_writel(dev, MUnit.ODR_C,
372 INBOUNDDOORBELL_3 << SRC_ODR_SHIFT);
373 break;
374 case FastIo:
375 src_writel(dev, MUnit.ODR_C,
376 INBOUNDDOORBELL_6 << SRC_ODR_SHIFT);
377 break;
378 case AdapPrintfDone:
379 src_writel(dev, MUnit.ODR_C,
380 INBOUNDDOORBELL_5 << SRC_ODR_SHIFT);
381 break;
382 default:
383 BUG();
384 break;
385 }
386}
387
388/**
389 * aac_src_start_adapter - activate adapter
390 * @dev: Adapter
391 *
392 * Start up processing on an i960 based AAC adapter
393 */
394
395static void aac_src_start_adapter(struct aac_dev *dev)
396{
a1751cda 397 union aac_init *init;
495c0217 398 int i;
e8b12f0f 399
85d22bbf 400 /* reset host_rrq_idx first */
495c0217
MR		 401 for (i = 0; i < dev->max_msix; i++) {
402 dev->host_rrq_idx[i] = i * dev->vector_cap;
403 atomic_set(&dev->rrq_outstanding[i], 0);
404 }
932cc3d3 405 atomic_set(&dev->msix_counter, 0);
495c0217 406 dev->fibs_pushed_no = 0;
85d22bbf 407
e8b12f0f 408 init = dev->init;
a1751cda
RAR		 409 if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) {
410 init->r8.host_elapsed_seconds = cpu_to_le32(get_seconds());
411 src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS,
412 (u32)(ulong)dev->init_pa,
413 (u32)((ulong)dev->init_pa>>32),
414 sizeof(struct _r8) +
415 (AAC_MAX_HRRQ - 1) * sizeof(struct _rrq),
416 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
417 } else {
418 init->r7.host_elapsed_seconds = cpu_to_le32(get_seconds());
419 // We can only use a 32 bit address here
420 src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS,
421 (u32)(ulong)dev->init_pa, 0, 0, 0, 0, 0,
422 NULL, NULL, NULL, NULL, NULL);
423 }
e8b12f0f 424
e8b12f0f
MR		 425}
426
427/**
428 * aac_src_check_health
429 * @dev: device to check if healthy
430 *
431 * Will attempt to determine if the specified adapter is alive and
432 * capable of handling requests, returning 0 if alive.
433 */
434static int aac_src_check_health(struct aac_dev *dev)
435{
436 u32 status = src_readl(dev, MUnit.OMR);
437
438 /*
439 * Check to see if the board failed any self tests.
440 */
441 if (unlikely(status & SELF_TEST_FAILED))
442 return -1;
443
444 /*
445 * Check to see if the board panic'd.
446 */
447 if (unlikely(status & KERNEL_PANIC))
448 return (status >> 16) & 0xFF;
449 /*
450 * Wait for the adapter to be up and running.
451 */
452 if (unlikely(!(status & KERNEL_UP_AND_RUNNING)))
453 return -3;
454 /*
455 * Everything is OK
456 */
457 return 0;
458}
459
5a05cc7c
RAR		 460static inline u32 aac_get_vector(struct aac_dev *dev)
461{
462 return atomic_inc_return(&dev->msix_counter)%dev->max_msix;
463}
464
e8b12f0f
MR		 465/**
466 * aac_src_deliver_message
467 * @fib: fib to issue
468 *
469 * Will send a fib, returning 0 if successful.
470 */
471static int aac_src_deliver_message(struct fib *fib)
472{
473 struct aac_dev *dev = fib->dev;
474 struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue];
e8b12f0f 475 u32 fibsize;
b5f1758f 476 dma_addr_t address;
e8b12f0f 477 struct aac_fib_xporthdr *pFibX;
5a05cc7c 478 int native_hba;
c6992781
MR		 479#if !defined(writeq)
480 unsigned long flags;
481#endif
482
3f4ce057 483 u16 vector_no;
e8b12f0f 484
ef616233 485 atomic_inc(&q->numpending);
e8b12f0f 486
5a05cc7c
RAR		 487 native_hba = (fib->flags & FIB_CONTEXT_FLAG_NATIVE_HBA) ? 1 : 0;
488
489
490 if (dev->msi_enabled && dev->max_msix > 1 &&
491 (native_hba || fib->hw_fib_va->header.Command != AifRequest)) {
492
493 if ((dev->comm_interface == AAC_COMM_MESSAGE_TYPE3)
494 && dev->sa_firmware)
495 vector_no = aac_get_vector(dev);
496 else
497 vector_no = fib->vector_no;
498
499 if (native_hba) {
272919a8
RAR		 500 if (fib->flags & FIB_CONTEXT_FLAG_NATIVE_HBA_TMF) {
501 struct aac_hba_tm_req *tm_req;
502
503 tm_req = (struct aac_hba_tm_req *)
504 fib->hw_fib_va;
505 if (tm_req->iu_type ==
506 HBA_IU_TYPE_SCSI_TM_REQ) {
507 ((struct aac_hba_tm_req *)
508 fib->hw_fib_va)->reply_qid
509 = vector_no;
510 ((struct aac_hba_tm_req *)
511 fib->hw_fib_va)->request_id
512 += (vector_no << 16);
513 } else {
514 ((struct aac_hba_reset_req *)
515 fib->hw_fib_va)->reply_qid
516 = vector_no;
517 ((struct aac_hba_reset_req *)
518 fib->hw_fib_va)->request_id
519 += (vector_no << 16);
520 }
521 } else {
522 ((struct aac_hba_cmd_req *)
523 fib->hw_fib_va)->reply_qid
524 = vector_no;
525 ((struct aac_hba_cmd_req *)
526 fib->hw_fib_va)->request_id
527 += (vector_no << 16);
528 }
5a05cc7c
RAR		 529 } else {
530 fib->hw_fib_va->header.Handle += (vector_no << 16);
531 }
3f4ce057
RAR		 532 } else {
533 vector_no = 0;
495c0217
MR		 534 }
535
3f4ce057
RAR		 536 atomic_inc(&dev->rrq_outstanding[vector_no]);
537
5a05cc7c 538 if (native_hba) {
85d22bbf 539 address = fib->hw_fib_pa;
5a05cc7c
RAR		 540 fibsize = (fib->hbacmd_size + 127) / 128 - 1;
541 if (fibsize > 31)
542 fibsize = 31;
85d22bbf 543 address |= fibsize;
5a05cc7c
RAR		 544#if defined(writeq)
545 src_writeq(dev, MUnit.IQN_L, (u64)address);
546#else
547 spin_lock_irqsave(&fib->dev->iq_lock, flags);
548 src_writel(dev, MUnit.IQN_H,
549 upper_32_bits(address) & 0xffffffff);
550 src_writel(dev, MUnit.IQN_L, address & 0xffffffff);
551 spin_unlock_irqrestore(&fib->dev->iq_lock, flags);
552#endif
85d22bbf 553 } else {
5a05cc7c
RAR		 554 if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2 ||
555 dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) {
556 /* Calculate the amount to the fibsize bits */
557 fibsize = (le16_to_cpu(fib->hw_fib_va->header.Size)
558 + 127) / 128 - 1;
559 /* New FIB header, 32-bit */
560 address = fib->hw_fib_pa;
561 fib->hw_fib_va->header.StructType = FIB_MAGIC2;
562 fib->hw_fib_va->header.SenderFibAddress =
563 cpu_to_le32((u32)address);
564 fib->hw_fib_va->header.u.TimeStamp = 0;
565 WARN_ON(((u32)(((address) >> 16) >> 16)) != 0L);
566 } else {
567 /* Calculate the amount to the fibsize bits */
568 fibsize = (sizeof(struct aac_fib_xporthdr) +
569 le16_to_cpu(fib->hw_fib_va->header.Size)
570 + 127) / 128 - 1;
571 /* Fill XPORT header */
572 pFibX = (struct aac_fib_xporthdr *)
573 ((unsigned char *)fib->hw_fib_va -
574 sizeof(struct aac_fib_xporthdr));
575 pFibX->Handle = fib->hw_fib_va->header.Handle;
576 pFibX->HostAddress =
577 cpu_to_le64((u64)fib->hw_fib_pa);
578 pFibX->Size = cpu_to_le32(
579 le16_to_cpu(fib->hw_fib_va->header.Size));
580 address = fib->hw_fib_pa -
581 (u64)sizeof(struct aac_fib_xporthdr);
582 }
583 if (fibsize > 31)
584 fibsize = 31;
85d22bbf 585 address |= fibsize;
5a05cc7c 586
c6992781 587#if defined(writeq)
5a05cc7c 588 src_writeq(dev, MUnit.IQ_L, (u64)address);
c6992781 589#else
5a05cc7c
RAR		 590 spin_lock_irqsave(&fib->dev->iq_lock, flags);
591 src_writel(dev, MUnit.IQ_H,
592 upper_32_bits(address) & 0xffffffff);
593 src_writel(dev, MUnit.IQ_L, address & 0xffffffff);
594 spin_unlock_irqrestore(&fib->dev->iq_lock, flags);
c6992781 595#endif
5a05cc7c 596 }
e8b12f0f
MR		 597 return 0;
598}
599
600/**
601 * aac_src_ioremap
602 * @size: mapping resize request
603 *
604 */
605static int aac_src_ioremap(struct aac_dev *dev, u32 size)
606{
607 if (!size) {
71552505
TH		 608 iounmap(dev->regs.src.bar1);
609 dev->regs.src.bar1 = NULL;
e8b12f0f 610 iounmap(dev->regs.src.bar0);
11604612 611 dev->base = dev->regs.src.bar0 = NULL;
e8b12f0f
MR		 612 return 0;
613 }
614 dev->regs.src.bar1 = ioremap(pci_resource_start(dev->pdev, 2),
615 AAC_MIN_SRC_BAR1_SIZE);
616 dev->base = NULL;
617 if (dev->regs.src.bar1 == NULL)
618 return -1;
ff08784b 619 dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size);
e8b12f0f
MR		 620 if (dev->base == NULL) {
621 iounmap(dev->regs.src.bar1);
622 dev->regs.src.bar1 = NULL;
623 return -1;
624 }
625 dev->IndexRegs = &((struct src_registers __iomem *)
11604612
MR		 626 dev->base)->u.tupelo.IndexRegs;
627 return 0;
628}
629
630/**
631 * aac_srcv_ioremap
632 * @size: mapping resize request
633 *
634 */
635static int aac_srcv_ioremap(struct aac_dev *dev, u32 size)
636{
637 if (!size) {
638 iounmap(dev->regs.src.bar0);
639 dev->base = dev->regs.src.bar0 = NULL;
640 return 0;
641 }
932cc3d3
RAR		 642
643 dev->regs.src.bar1 =
644 ioremap(pci_resource_start(dev->pdev, 2), AAC_MIN_SRCV_BAR1_SIZE);
645 dev->base = NULL;
646 if (dev->regs.src.bar1 == NULL)
647 return -1;
ff08784b 648 dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size);
932cc3d3
RAR		 649 if (dev->base == NULL) {
650 iounmap(dev->regs.src.bar1);
651 dev->regs.src.bar1 = NULL;
11604612 652 return -1;
932cc3d3 653 }
11604612
MR		 654 dev->IndexRegs = &((struct src_registers __iomem *)
655 dev->base)->u.denali.IndexRegs;
e8b12f0f
MR		 656 return 0;
657}
658
659static int aac_src_restart_adapter(struct aac_dev *dev, int bled)
660{
661 u32 var, reset_mask;
662
663 if (bled >= 0) {
664 if (bled)
665 printk(KERN_ERR "%s%d: adapter kernel panic'd %x.\n",
666 dev->name, dev->id, bled);
dafde947 667 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
e8b12f0f
MR		 668 bled = aac_adapter_sync_cmd(dev, IOP_RESET_ALWAYS,
669 0, 0, 0, 0, 0, 0, &var, &reset_mask, NULL, NULL, NULL);
dafde947
MR		 670 if ((bled || (var != 0x00000001)) &&
671 !dev->doorbell_mask)
672 return -EINVAL;
673 else if (dev->doorbell_mask) {
674 reset_mask = dev->doorbell_mask;
675 bled = 0;
676 var = 0x00000001;
677 }
495c0217
MR		 678
679 if ((dev->pdev->device == PMC_DEVICE_S7 ||
680 dev->pdev->device == PMC_DEVICE_S8 ||
681 dev->pdev->device == PMC_DEVICE_S9) && dev->msi_enabled) {
682 aac_src_access_devreg(dev, AAC_ENABLE_INTX);
683 dev->msi_enabled = 0;
684 msleep(5000); /* Delay 5 seconds */
685 }
686
dafde947
MR		 687 if (!bled && (dev->supplement_adapter_info.SupportedOptions2 &
688 AAC_OPTION_DOORBELL_RESET)) {
e8b12f0f 689 src_writel(dev, MUnit.IDR, reset_mask);
495c0217 690 ssleep(45);
dafde947
MR		 691 } else {
692 src_writel(dev, MUnit.IDR, 0x100);
693 ssleep(45);
e8b12f0f
MR		 694 }
695 }
696
697 if (src_readl(dev, MUnit.OMR) & KERNEL_PANIC)
698 return -ENODEV;
699
700 if (startup_timeout < 300)
701 startup_timeout = 300;
702
703 return 0;
704}
705
706/**
707 * aac_src_select_comm - Select communications method
708 * @dev: Adapter
709 * @comm: communications method
710 */
a44199ee 711static int aac_src_select_comm(struct aac_dev *dev, int comm)
e8b12f0f
MR		 712{
713 switch (comm) {
714 case AAC_COMM_MESSAGE:
e8b12f0f
MR		 715 dev->a_ops.adapter_intr = aac_src_intr_message;
716 dev->a_ops.adapter_deliver = aac_src_deliver_message;
717 break;
718 default:
719 return 1;
720 }
721 return 0;
722}
723
724/**
725 * aac_src_init - initialize an Cardinal Frey Bar card
726 * @dev: device to configure
727 *
728 */
729
730int aac_src_init(struct aac_dev *dev)
731{
732 unsigned long start;
733 unsigned long status;
734 int restart = 0;
735 int instance = dev->id;
736 const char *name = dev->name;
737
738 dev->a_ops.adapter_ioremap = aac_src_ioremap;
739 dev->a_ops.adapter_comm = aac_src_select_comm;
740
741 dev->base_size = AAC_MIN_SRC_BAR0_SIZE;
742 if (aac_adapter_ioremap(dev, dev->base_size)) {
743 printk(KERN_WARNING "%s: unable to map adapter.\n", name);
744 goto error_iounmap;
745 }
746
747 /* Failure to reset here is an option ... */
748 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
749 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
750 if ((aac_reset_devices || reset_devices) &&
751 !aac_src_restart_adapter(dev, 0))
752 ++restart;
753 /*
754 * Check to see if the board panic'd while booting.
755 */
756 status = src_readl(dev, MUnit.OMR);
757 if (status & KERNEL_PANIC) {
758 if (aac_src_restart_adapter(dev, aac_src_check_health(dev)))
759 goto error_iounmap;
760 ++restart;
761 }
762 /*
763 * Check to see if the board failed any self tests.
764 */
765 status = src_readl(dev, MUnit.OMR);
766 if (status & SELF_TEST_FAILED) {
767 printk(KERN_ERR "%s%d: adapter self-test failed.\n",
768 dev->name, instance);
769 goto error_iounmap;
770 }
771 /*
772 * Check to see if the monitor panic'd while booting.
773 */
774 if (status & MONITOR_PANIC) {
775 printk(KERN_ERR "%s%d: adapter monitor panic.\n",
776 dev->name, instance);
777 goto error_iounmap;
778 }
779 start = jiffies;
780 /*
781 * Wait for the adapter to be up and running. Wait up to 3 minutes
782 */
783 while (!((status = src_readl(dev, MUnit.OMR)) &
784 KERNEL_UP_AND_RUNNING)) {
785 if ((restart &&
786 (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
787 time_after(jiffies, start+HZ*startup_timeout)) {
788 printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
789 dev->name, instance, status);
790 goto error_iounmap;
791 }
792 if (!restart &&
793 ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
794 time_after(jiffies, start + HZ *
795 ((startup_timeout > 60)
796 ? (startup_timeout - 60)
797 : (startup_timeout / 2))))) {
798 if (likely(!aac_src_restart_adapter(dev,
799 aac_src_check_health(dev))))
800 start = jiffies;
801 ++restart;
802 }
803 msleep(1);
804 }
805 if (restart && aac_commit)
806 aac_commit = 1;
807 /*
808 * Fill in the common function dispatch table.
809 */
810 dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter;
811 dev->a_ops.adapter_disable_int = aac_src_disable_interrupt;
dafde947 812 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
e8b12f0f
MR		 813 dev->a_ops.adapter_notify = aac_src_notify_adapter;
814 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
815 dev->a_ops.adapter_check_health = aac_src_check_health;
816 dev->a_ops.adapter_restart = aac_src_restart_adapter;
de665f28 817 dev->a_ops.adapter_start = aac_src_start_adapter;
e8b12f0f
MR		 818
819 /*
820 * First clear out all interrupts. Then enable the one's that we
821 * can handle.
822 */
823 aac_adapter_comm(dev, AAC_COMM_MESSAGE);
824 aac_adapter_disable_int(dev);
825 src_writel(dev, MUnit.ODR_C, 0xffffffff);
826 aac_adapter_enable_int(dev);
827
828 if (aac_init_adapter(dev) == NULL)
829 goto error_iounmap;
830 if (dev->comm_interface != AAC_COMM_MESSAGE_TYPE1)
831 goto error_iounmap;
832
9022d375 833 dev->msi = !pci_enable_msi(dev->pdev);
e8b12f0f 834
495c0217
MR		 835 dev->aac_msix[0].vector_no = 0;
836 dev->aac_msix[0].dev = dev;
837
e8b12f0f 838 if (request_irq(dev->pdev->irq, dev->a_ops.adapter_intr,
495c0217 839 IRQF_SHARED, "aacraid", &(dev->aac_msix[0])) < 0) {
e8b12f0f
MR		 840
841 if (dev->msi)
842 pci_disable_msi(dev->pdev);
843
844 printk(KERN_ERR "%s%d: Interrupt unavailable.\n",
845 name, instance);
846 goto error_iounmap;
847 }
848 dev->dbg_base = pci_resource_start(dev->pdev, 2);
849 dev->dbg_base_mapped = dev->regs.src.bar1;
850 dev->dbg_size = AAC_MIN_SRC_BAR1_SIZE;
dafde947 851 dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message;
e8b12f0f
MR		 852
853 aac_adapter_enable_int(dev);
11604612
MR		 854
855 if (!dev->sync_mode) {
856 /*
857 * Tell the adapter that all is configured, and it can
858 * start accepting requests
859 */
860 aac_src_start_adapter(dev);
861 }
862 return 0;
863
864error_iounmap:
865
866 return -1;
867}
868
869/**
870 * aac_srcv_init - initialize an SRCv card
871 * @dev: device to configure
872 *
873 */
874
875int aac_srcv_init(struct aac_dev *dev)
876{
877 unsigned long start;
878 unsigned long status;
879 int restart = 0;
880 int instance = dev->id;
881 const char *name = dev->name;
882
883 dev->a_ops.adapter_ioremap = aac_srcv_ioremap;
884 dev->a_ops.adapter_comm = aac_src_select_comm;
885
886 dev->base_size = AAC_MIN_SRCV_BAR0_SIZE;
887 if (aac_adapter_ioremap(dev, dev->base_size)) {
888 printk(KERN_WARNING "%s: unable to map adapter.\n", name);
889 goto error_iounmap;
890 }
891
892 /* Failure to reset here is an option ... */
893 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
894 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
895 if ((aac_reset_devices || reset_devices) &&
896 !aac_src_restart_adapter(dev, 0))
897 ++restart;
2c10cd43
MR		 898 /*
899 * Check to see if flash update is running.
900 * Wait for the adapter to be up and running. Wait up to 5 minutes
901 */
902 status = src_readl(dev, MUnit.OMR);
903 if (status & FLASH_UPD_PENDING) {
904 start = jiffies;
905 do {
906 status = src_readl(dev, MUnit.OMR);
907 if (time_after(jiffies, start+HZ*FWUPD_TIMEOUT)) {
908 printk(KERN_ERR "%s%d: adapter flash update failed.\n",
909 dev->name, instance);
910 goto error_iounmap;
911 }
912 } while (!(status & FLASH_UPD_SUCCESS) &&
913 !(status & FLASH_UPD_FAILED));
914 /* Delay 10 seconds.
915 * Because right now FW is doing a soft reset,
916 * do not read scratch pad register at this time
917 */
918 ssleep(10);
919 }
e8b12f0f 920 /*
11604612 921 * Check to see if the board panic'd while booting.
e8b12f0f 922 */
11604612
MR		 923 status = src_readl(dev, MUnit.OMR);
924 if (status & KERNEL_PANIC) {
925 if (aac_src_restart_adapter(dev, aac_src_check_health(dev)))
926 goto error_iounmap;
927 ++restart;
928 }
929 /*
930 * Check to see if the board failed any self tests.
931 */
932 status = src_readl(dev, MUnit.OMR);
933 if (status & SELF_TEST_FAILED) {
934 printk(KERN_ERR "%s%d: adapter self-test failed.\n", dev->name, instance);
935 goto error_iounmap;
936 }
937 /*
938 * Check to see if the monitor panic'd while booting.
939 */
940 if (status & MONITOR_PANIC) {
941 printk(KERN_ERR "%s%d: adapter monitor panic.\n", dev->name, instance);
942 goto error_iounmap;
943 }
944 start = jiffies;
945 /*
946 * Wait for the adapter to be up and running. Wait up to 3 minutes
947 */
2c10cd43
MR		 948 while (!((status = src_readl(dev, MUnit.OMR)) &
949 KERNEL_UP_AND_RUNNING) ||
950 status == 0xffffffff) {
11604612
MR		 951 if ((restart &&
952 (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
953 time_after(jiffies, start+HZ*startup_timeout)) {
954 printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
955 dev->name, instance, status);
956 goto error_iounmap;
957 }
958 if (!restart &&
959 ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
960 time_after(jiffies, start + HZ *
961 ((startup_timeout > 60)
962 ? (startup_timeout - 60)
963 : (startup_timeout / 2))))) {
964 if (likely(!aac_src_restart_adapter(dev, aac_src_check_health(dev))))
965 start = jiffies;
966 ++restart;
967 }
968 msleep(1);
969 }
970 if (restart && aac_commit)
971 aac_commit = 1;
972 /*
973 * Fill in the common function dispatch table.
974 */
975 dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter;
976 dev->a_ops.adapter_disable_int = aac_src_disable_interrupt;
dafde947 977 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
11604612
MR		 978 dev->a_ops.adapter_notify = aac_src_notify_adapter;
979 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
980 dev->a_ops.adapter_check_health = aac_src_check_health;
981 dev->a_ops.adapter_restart = aac_src_restart_adapter;
de665f28 982 dev->a_ops.adapter_start = aac_src_start_adapter;
11604612
MR		 983
984 /*
985 * First clear out all interrupts. Then enable the one's that we
986 * can handle.
987 */
988 aac_adapter_comm(dev, AAC_COMM_MESSAGE);
989 aac_adapter_disable_int(dev);
990 src_writel(dev, MUnit.ODR_C, 0xffffffff);
991 aac_adapter_enable_int(dev);
e8b12f0f 992
11604612
MR		 993 if (aac_init_adapter(dev) == NULL)
994 goto error_iounmap;
a1751cda
RAR		 995 if ((dev->comm_interface != AAC_COMM_MESSAGE_TYPE2) &&
996 (dev->comm_interface != AAC_COMM_MESSAGE_TYPE3))
11604612 997 goto error_iounmap;
495c0217
MR		 998 if (dev->msi_enabled)
999 aac_src_access_devreg(dev, AAC_ENABLE_MSIX);
8b1462e0
MR		 1000
1001 if (aac_acquire_irq(dev))
1002 goto error_iounmap;
1003
932cc3d3
RAR		 1004 dev->dbg_base = pci_resource_start(dev->pdev, 2);
1005 dev->dbg_base_mapped = dev->regs.src.bar1;
1006 dev->dbg_size = AAC_MIN_SRCV_BAR1_SIZE;
dafde947 1007 dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message;
11604612
MR		 1008
1009 aac_adapter_enable_int(dev);
1010
1011 if (!dev->sync_mode) {
1012 /*
1013 * Tell the adapter that all is configured, and it can
1014 * start accepting requests
1015 */
1016 aac_src_start_adapter(dev);
1017 }
e8b12f0f
MR		 1018 return 0;
1019
1020error_iounmap:
1021
1022 return -1;
1023}
11604612 1024
495c0217
MR		 1025void aac_src_access_devreg(struct aac_dev *dev, int mode)
1026{
1027 u_int32_t val;
1028
1029 switch (mode) {
1030 case AAC_ENABLE_INTERRUPT:
1031 src_writel(dev,
1032 MUnit.OIMR,
1033 dev->OIMR = (dev->msi_enabled ?
1034 AAC_INT_ENABLE_TYPE1_MSIX :
1035 AAC_INT_ENABLE_TYPE1_INTX));
1036 break;
1037
1038 case AAC_DISABLE_INTERRUPT:
1039 src_writel(dev,
1040 MUnit.OIMR,
1041 dev->OIMR = AAC_INT_DISABLE_ALL);
1042 break;
1043
1044 case AAC_ENABLE_MSIX:
1045 /* set bit 6 */
1046 val = src_readl(dev, MUnit.IDR);
1047 val |= 0x40;
1048 src_writel(dev, MUnit.IDR, val);
1049 src_readl(dev, MUnit.IDR);
1050 /* unmask int. */
1051 val = PMC_ALL_INTERRUPT_BITS;
1052 src_writel(dev, MUnit.IOAR, val);
1053 val = src_readl(dev, MUnit.OIMR);
1054 src_writel(dev,
1055 MUnit.OIMR,
1056 val & (~(PMC_GLOBAL_INT_BIT2 | PMC_GLOBAL_INT_BIT0)));
1057 break;
1058
1059 case AAC_DISABLE_MSIX:
1060 /* reset bit 6 */
1061 val = src_readl(dev, MUnit.IDR);
1062 val &= ~0x40;
1063 src_writel(dev, MUnit.IDR, val);
1064 src_readl(dev, MUnit.IDR);
1065 break;
1066
1067 case AAC_CLEAR_AIF_BIT:
1068 /* set bit 5 */
1069 val = src_readl(dev, MUnit.IDR);
1070 val |= 0x20;
1071 src_writel(dev, MUnit.IDR, val);
1072 src_readl(dev, MUnit.IDR);
1073 break;
1074
1075 case AAC_CLEAR_SYNC_BIT:
1076 /* set bit 4 */
1077 val = src_readl(dev, MUnit.IDR);
1078 val |= 0x10;
1079 src_writel(dev, MUnit.IDR, val);
1080 src_readl(dev, MUnit.IDR);
1081 break;
1082
1083 case AAC_ENABLE_INTX:
1084 /* set bit 7 */
1085 val = src_readl(dev, MUnit.IDR);
1086 val |= 0x80;
1087 src_writel(dev, MUnit.IDR, val);
1088 src_readl(dev, MUnit.IDR);
1089 /* unmask int. */
1090 val = PMC_ALL_INTERRUPT_BITS;
1091 src_writel(dev, MUnit.IOAR, val);
1092 src_readl(dev, MUnit.IOAR);
1093 val = src_readl(dev, MUnit.OIMR);
1094 src_writel(dev, MUnit.OIMR,
1095 val & (~(PMC_GLOBAL_INT_BIT2)));
1096 break;
1097
1098 default:
1099 break;
1100 }
1101}
1102
1103static int aac_src_get_sync_status(struct aac_dev *dev)
1104{
1105
1106 int val;
1107
1108 if (dev->msi_enabled)
1109 val = src_readl(dev, MUnit.ODR_MSI) & 0x1000 ? 1 : 0;
1110 else
1111 val = src_readl(dev, MUnit.ODR_R) >> SRC_ODR_SHIFT;
1112
1113 return val;
1114}
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