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e8b12f0f MR |
1 | /* |
2 | * Adaptec AAC series RAID controller driver | |
3 | * (c) Copyright 2001 Red Hat Inc. | |
4 | * | |
5 | * based on the old aacraid driver that is.. | |
6 | * Adaptec aacraid device driver for Linux. | |
7 | * | |
8 | * Copyright (c) 2000-2010 Adaptec, Inc. | |
9 | * 2010 PMC-Sierra, Inc. (aacraid@pmc-sierra.com) | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * Module Name: | |
26 | * src.c | |
27 | * | |
28 | * Abstract: Hardware Device Interface for PMC SRC based controllers | |
29 | * | |
30 | */ | |
31 | ||
32 | #include <linux/kernel.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/types.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/spinlock.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/blkdev.h> | |
39 | #include <linux/delay.h> | |
e8b12f0f MR |
40 | #include <linux/completion.h> |
41 | #include <linux/time.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <scsi/scsi_host.h> | |
44 | ||
45 | #include "aacraid.h" | |
46 | ||
495c0217 MR |
47 | static int aac_src_get_sync_status(struct aac_dev *dev); |
48 | ||
305974fe | 49 | static irqreturn_t aac_src_intr_message(int irq, void *dev_id) |
e8b12f0f | 50 | { |
495c0217 MR |
51 | struct aac_msix_ctx *ctx; |
52 | struct aac_dev *dev; | |
e8b12f0f | 53 | unsigned long bellbits, bellbits_shifted; |
495c0217 MR |
54 | int vector_no; |
55 | int isFastResponse, mode; | |
e8b12f0f MR |
56 | u32 index, handle; |
57 | ||
495c0217 MR |
58 | ctx = (struct aac_msix_ctx *)dev_id; |
59 | dev = ctx->dev; | |
60 | vector_no = ctx->vector_no; | |
61 | ||
62 | if (dev->msi_enabled) { | |
63 | mode = AAC_INT_MODE_MSI; | |
64 | if (vector_no == 0) { | |
65 | bellbits = src_readl(dev, MUnit.ODR_MSI); | |
66 | if (bellbits & 0x40000) | |
67 | mode |= AAC_INT_MODE_AIF; | |
68 | if (bellbits & 0x1000) | |
69 | mode |= AAC_INT_MODE_SYNC; | |
e8b12f0f MR |
70 | } |
71 | } else { | |
495c0217 MR |
72 | mode = AAC_INT_MODE_INTX; |
73 | bellbits = src_readl(dev, MUnit.ODR_R); | |
74 | if (bellbits & PmDoorBellResponseSent) { | |
75 | bellbits = PmDoorBellResponseSent; | |
76 | src_writel(dev, MUnit.ODR_C, bellbits); | |
77 | src_readl(dev, MUnit.ODR_C); | |
78 | } else { | |
79 | bellbits_shifted = (bellbits >> SRC_ODR_SHIFT); | |
85d22bbf MR |
80 | src_writel(dev, MUnit.ODR_C, bellbits); |
81 | src_readl(dev, MUnit.ODR_C); | |
85d22bbf | 82 | |
495c0217 MR |
83 | if (bellbits_shifted & DoorBellAifPending) |
84 | mode |= AAC_INT_MODE_AIF; | |
85 | else if (bellbits_shifted & OUTBOUNDDOORBELL_0) | |
86 | mode |= AAC_INT_MODE_SYNC; | |
87 | } | |
88 | } | |
89 | ||
90 | if (mode & AAC_INT_MODE_SYNC) { | |
91 | unsigned long sflags; | |
92 | struct list_head *entry; | |
93 | int send_it = 0; | |
94 | extern int aac_sync_mode; | |
95 | ||
96 | if (!aac_sync_mode && !dev->msi_enabled) { | |
c5bebd82 MR |
97 | src_writel(dev, MUnit.ODR_C, bellbits); |
98 | src_readl(dev, MUnit.ODR_C); | |
495c0217 | 99 | } |
c5bebd82 | 100 | |
495c0217 MR |
101 | if (dev->sync_fib) { |
102 | if (dev->sync_fib->callback) | |
103 | dev->sync_fib->callback(dev->sync_fib->callback_data, | |
104 | dev->sync_fib); | |
105 | spin_lock_irqsave(&dev->sync_fib->event_lock, sflags); | |
106 | if (dev->sync_fib->flags & FIB_CONTEXT_FLAG_WAIT) { | |
107 | dev->management_fib_count--; | |
108 | up(&dev->sync_fib->event_wait); | |
85d22bbf | 109 | } |
495c0217 MR |
110 | spin_unlock_irqrestore(&dev->sync_fib->event_lock, |
111 | sflags); | |
112 | spin_lock_irqsave(&dev->sync_lock, sflags); | |
113 | if (!list_empty(&dev->sync_fib_list)) { | |
114 | entry = dev->sync_fib_list.next; | |
115 | dev->sync_fib = list_entry(entry, | |
116 | struct fib, | |
117 | fiblink); | |
118 | list_del(entry); | |
119 | send_it = 1; | |
120 | } else { | |
121 | dev->sync_fib = NULL; | |
122 | } | |
123 | spin_unlock_irqrestore(&dev->sync_lock, sflags); | |
124 | if (send_it) { | |
125 | aac_adapter_sync_cmd(dev, SEND_SYNCHRONOUS_FIB, | |
126 | (u32)dev->sync_fib->hw_fib_pa, | |
127 | 0, 0, 0, 0, 0, | |
128 | NULL, NULL, NULL, NULL, NULL); | |
11604612 | 129 | } |
e8b12f0f | 130 | } |
495c0217 MR |
131 | if (!dev->msi_enabled) |
132 | mode = 0; | |
133 | ||
e8b12f0f MR |
134 | } |
135 | ||
495c0217 MR |
136 | if (mode & AAC_INT_MODE_AIF) { |
137 | /* handle AIF */ | |
138 | aac_intr_normal(dev, 0, 2, 0, NULL); | |
139 | if (dev->msi_enabled) | |
140 | aac_src_access_devreg(dev, AAC_CLEAR_AIF_BIT); | |
141 | mode = 0; | |
e8b12f0f | 142 | } |
495c0217 MR |
143 | |
144 | if (mode) { | |
145 | index = dev->host_rrq_idx[vector_no]; | |
146 | ||
147 | for (;;) { | |
148 | isFastResponse = 0; | |
149 | /* remove toggle bit (31) */ | |
150 | handle = (dev->host_rrq[index] & 0x7fffffff); | |
151 | /* check fast response bit (30) */ | |
152 | if (handle & 0x40000000) | |
153 | isFastResponse = 1; | |
154 | handle &= 0x0000ffff; | |
155 | if (handle == 0) | |
156 | break; | |
157 | if (dev->msi_enabled && dev->max_msix > 1) | |
158 | atomic_dec(&dev->rrq_outstanding[vector_no]); | |
159 | aac_intr_normal(dev, handle-1, 0, isFastResponse, NULL); | |
160 | dev->host_rrq[index++] = 0; | |
161 | if (index == (vector_no + 1) * dev->vector_cap) | |
162 | index = vector_no * dev->vector_cap; | |
163 | dev->host_rrq_idx[vector_no] = index; | |
164 | } | |
165 | mode = 0; | |
166 | } | |
167 | ||
168 | return IRQ_HANDLED; | |
e8b12f0f MR |
169 | } |
170 | ||
171 | /** | |
172 | * aac_src_disable_interrupt - Disable interrupts | |
173 | * @dev: Adapter | |
174 | */ | |
175 | ||
176 | static void aac_src_disable_interrupt(struct aac_dev *dev) | |
177 | { | |
178 | src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff); | |
179 | } | |
180 | ||
181 | /** | |
182 | * aac_src_enable_interrupt_message - Enable interrupts | |
183 | * @dev: Adapter | |
184 | */ | |
185 | ||
186 | static void aac_src_enable_interrupt_message(struct aac_dev *dev) | |
187 | { | |
495c0217 | 188 | aac_src_access_devreg(dev, AAC_ENABLE_INTERRUPT); |
e8b12f0f MR |
189 | } |
190 | ||
191 | /** | |
192 | * src_sync_cmd - send a command and wait | |
193 | * @dev: Adapter | |
194 | * @command: Command to execute | |
195 | * @p1: first parameter | |
196 | * @ret: adapter status | |
197 | * | |
198 | * This routine will send a synchronous command to the adapter and wait | |
199 | * for its completion. | |
200 | */ | |
201 | ||
202 | static int src_sync_cmd(struct aac_dev *dev, u32 command, | |
203 | u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, | |
204 | u32 *status, u32 * r1, u32 * r2, u32 * r3, u32 * r4) | |
205 | { | |
206 | unsigned long start; | |
dafde947 | 207 | unsigned long delay; |
e8b12f0f MR |
208 | int ok; |
209 | ||
210 | /* | |
211 | * Write the command into Mailbox 0 | |
212 | */ | |
213 | writel(command, &dev->IndexRegs->Mailbox[0]); | |
214 | /* | |
215 | * Write the parameters into Mailboxes 1 - 6 | |
216 | */ | |
217 | writel(p1, &dev->IndexRegs->Mailbox[1]); | |
218 | writel(p2, &dev->IndexRegs->Mailbox[2]); | |
219 | writel(p3, &dev->IndexRegs->Mailbox[3]); | |
220 | writel(p4, &dev->IndexRegs->Mailbox[4]); | |
221 | ||
222 | /* | |
223 | * Clear the synch command doorbell to start on a clean slate. | |
224 | */ | |
495c0217 MR |
225 | if (!dev->msi_enabled) |
226 | src_writel(dev, | |
227 | MUnit.ODR_C, | |
228 | OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT); | |
e8b12f0f MR |
229 | |
230 | /* | |
231 | * Disable doorbell interrupts | |
232 | */ | |
233 | src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff); | |
234 | ||
235 | /* | |
236 | * Force the completion of the mask register write before issuing | |
237 | * the interrupt. | |
238 | */ | |
239 | src_readl(dev, MUnit.OIMR); | |
240 | ||
241 | /* | |
242 | * Signal that there is a new synch command | |
243 | */ | |
244 | src_writel(dev, MUnit.IDR, INBOUNDDOORBELL_0 << SRC_IDR_SHIFT); | |
245 | ||
11604612 MR |
246 | if (!dev->sync_mode || command != SEND_SYNCHRONOUS_FIB) { |
247 | ok = 0; | |
248 | start = jiffies; | |
e8b12f0f | 249 | |
dafde947 MR |
250 | if (command == IOP_RESET_ALWAYS) { |
251 | /* Wait up to 10 sec */ | |
252 | delay = 10*HZ; | |
253 | } else { | |
254 | /* Wait up to 5 minutes */ | |
255 | delay = 300*HZ; | |
256 | } | |
257 | while (time_before(jiffies, start+delay)) { | |
11604612 MR |
258 | udelay(5); /* Delay 5 microseconds to let Mon960 get info. */ |
259 | /* | |
260 | * Mon960 will set doorbell0 bit when it has completed the command. | |
261 | */ | |
495c0217 | 262 | if (aac_src_get_sync_status(dev) & OUTBOUNDDOORBELL_0) { |
11604612 MR |
263 | /* |
264 | * Clear the doorbell. | |
265 | */ | |
495c0217 MR |
266 | if (dev->msi_enabled) |
267 | aac_src_access_devreg(dev, | |
268 | AAC_CLEAR_SYNC_BIT); | |
269 | else | |
270 | src_writel(dev, | |
271 | MUnit.ODR_C, | |
272 | OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT); | |
11604612 MR |
273 | ok = 1; |
274 | break; | |
275 | } | |
276 | /* | |
277 | * Yield the processor in case we are slow | |
278 | */ | |
279 | msleep(1); | |
e8b12f0f | 280 | } |
11604612 MR |
281 | if (unlikely(ok != 1)) { |
282 | /* | |
283 | * Restore interrupt mask even though we timed out | |
284 | */ | |
285 | aac_adapter_enable_int(dev); | |
286 | return -ETIMEDOUT; | |
287 | } | |
288 | /* | |
289 | * Pull the synch status from Mailbox 0. | |
290 | */ | |
291 | if (status) | |
292 | *status = readl(&dev->IndexRegs->Mailbox[0]); | |
293 | if (r1) | |
294 | *r1 = readl(&dev->IndexRegs->Mailbox[1]); | |
295 | if (r2) | |
296 | *r2 = readl(&dev->IndexRegs->Mailbox[2]); | |
297 | if (r3) | |
298 | *r3 = readl(&dev->IndexRegs->Mailbox[3]); | |
299 | if (r4) | |
300 | *r4 = readl(&dev->IndexRegs->Mailbox[4]); | |
495c0217 MR |
301 | if (command == GET_COMM_PREFERRED_SETTINGS) |
302 | dev->max_msix = | |
303 | readl(&dev->IndexRegs->Mailbox[5]) & 0xFFFF; | |
11604612 MR |
304 | /* |
305 | * Clear the synch command doorbell. | |
306 | */ | |
495c0217 MR |
307 | if (!dev->msi_enabled) |
308 | src_writel(dev, | |
309 | MUnit.ODR_C, | |
310 | OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT); | |
e8b12f0f MR |
311 | } |
312 | ||
11604612 MR |
313 | /* |
314 | * Restore interrupt mask | |
315 | */ | |
e8b12f0f MR |
316 | aac_adapter_enable_int(dev); |
317 | return 0; | |
e8b12f0f MR |
318 | } |
319 | ||
320 | /** | |
321 | * aac_src_interrupt_adapter - interrupt adapter | |
322 | * @dev: Adapter | |
323 | * | |
324 | * Send an interrupt to the i960 and breakpoint it. | |
325 | */ | |
326 | ||
327 | static void aac_src_interrupt_adapter(struct aac_dev *dev) | |
328 | { | |
329 | src_sync_cmd(dev, BREAKPOINT_REQUEST, | |
330 | 0, 0, 0, 0, 0, 0, | |
331 | NULL, NULL, NULL, NULL, NULL); | |
332 | } | |
333 | ||
334 | /** | |
335 | * aac_src_notify_adapter - send an event to the adapter | |
336 | * @dev: Adapter | |
337 | * @event: Event to send | |
338 | * | |
339 | * Notify the i960 that something it probably cares about has | |
340 | * happened. | |
341 | */ | |
342 | ||
343 | static void aac_src_notify_adapter(struct aac_dev *dev, u32 event) | |
344 | { | |
345 | switch (event) { | |
346 | ||
347 | case AdapNormCmdQue: | |
348 | src_writel(dev, MUnit.ODR_C, | |
349 | INBOUNDDOORBELL_1 << SRC_ODR_SHIFT); | |
350 | break; | |
351 | case HostNormRespNotFull: | |
352 | src_writel(dev, MUnit.ODR_C, | |
353 | INBOUNDDOORBELL_4 << SRC_ODR_SHIFT); | |
354 | break; | |
355 | case AdapNormRespQue: | |
356 | src_writel(dev, MUnit.ODR_C, | |
357 | INBOUNDDOORBELL_2 << SRC_ODR_SHIFT); | |
358 | break; | |
359 | case HostNormCmdNotFull: | |
360 | src_writel(dev, MUnit.ODR_C, | |
361 | INBOUNDDOORBELL_3 << SRC_ODR_SHIFT); | |
362 | break; | |
363 | case FastIo: | |
364 | src_writel(dev, MUnit.ODR_C, | |
365 | INBOUNDDOORBELL_6 << SRC_ODR_SHIFT); | |
366 | break; | |
367 | case AdapPrintfDone: | |
368 | src_writel(dev, MUnit.ODR_C, | |
369 | INBOUNDDOORBELL_5 << SRC_ODR_SHIFT); | |
370 | break; | |
371 | default: | |
372 | BUG(); | |
373 | break; | |
374 | } | |
375 | } | |
376 | ||
377 | /** | |
378 | * aac_src_start_adapter - activate adapter | |
379 | * @dev: Adapter | |
380 | * | |
381 | * Start up processing on an i960 based AAC adapter | |
382 | */ | |
383 | ||
384 | static void aac_src_start_adapter(struct aac_dev *dev) | |
385 | { | |
386 | struct aac_init *init; | |
495c0217 | 387 | int i; |
e8b12f0f | 388 | |
85d22bbf | 389 | /* reset host_rrq_idx first */ |
495c0217 MR |
390 | for (i = 0; i < dev->max_msix; i++) { |
391 | dev->host_rrq_idx[i] = i * dev->vector_cap; | |
392 | atomic_set(&dev->rrq_outstanding[i], 0); | |
393 | } | |
394 | dev->fibs_pushed_no = 0; | |
85d22bbf | 395 | |
e8b12f0f MR |
396 | init = dev->init; |
397 | init->HostElapsedSeconds = cpu_to_le32(get_seconds()); | |
398 | ||
399 | /* We can only use a 32 bit address here */ | |
400 | src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS, (u32)(ulong)dev->init_pa, | |
401 | 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL); | |
402 | } | |
403 | ||
404 | /** | |
405 | * aac_src_check_health | |
406 | * @dev: device to check if healthy | |
407 | * | |
408 | * Will attempt to determine if the specified adapter is alive and | |
409 | * capable of handling requests, returning 0 if alive. | |
410 | */ | |
411 | static int aac_src_check_health(struct aac_dev *dev) | |
412 | { | |
413 | u32 status = src_readl(dev, MUnit.OMR); | |
414 | ||
415 | /* | |
416 | * Check to see if the board failed any self tests. | |
417 | */ | |
418 | if (unlikely(status & SELF_TEST_FAILED)) | |
419 | return -1; | |
420 | ||
421 | /* | |
422 | * Check to see if the board panic'd. | |
423 | */ | |
424 | if (unlikely(status & KERNEL_PANIC)) | |
425 | return (status >> 16) & 0xFF; | |
426 | /* | |
427 | * Wait for the adapter to be up and running. | |
428 | */ | |
429 | if (unlikely(!(status & KERNEL_UP_AND_RUNNING))) | |
430 | return -3; | |
431 | /* | |
432 | * Everything is OK | |
433 | */ | |
434 | return 0; | |
435 | } | |
436 | ||
437 | /** | |
438 | * aac_src_deliver_message | |
439 | * @fib: fib to issue | |
440 | * | |
441 | * Will send a fib, returning 0 if successful. | |
442 | */ | |
443 | static int aac_src_deliver_message(struct fib *fib) | |
444 | { | |
445 | struct aac_dev *dev = fib->dev; | |
446 | struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue]; | |
e8b12f0f | 447 | u32 fibsize; |
b5f1758f | 448 | dma_addr_t address; |
e8b12f0f | 449 | struct aac_fib_xporthdr *pFibX; |
c6992781 MR |
450 | #if !defined(writeq) |
451 | unsigned long flags; | |
452 | #endif | |
453 | ||
b5f1758f | 454 | u16 hdr_size = le16_to_cpu(fib->hw_fib_va->header.Size); |
e8b12f0f | 455 | |
ef616233 | 456 | atomic_inc(&q->numpending); |
e8b12f0f | 457 | |
495c0217 MR |
458 | if (dev->msi_enabled && fib->hw_fib_va->header.Command != AifRequest && |
459 | dev->max_msix > 1) { | |
460 | u_int16_t vector_no, first_choice = 0xffff; | |
461 | ||
462 | vector_no = dev->fibs_pushed_no % dev->max_msix; | |
463 | do { | |
464 | vector_no += 1; | |
465 | if (vector_no == dev->max_msix) | |
466 | vector_no = 1; | |
467 | if (atomic_read(&dev->rrq_outstanding[vector_no]) < | |
468 | dev->vector_cap) | |
469 | break; | |
470 | if (0xffff == first_choice) | |
471 | first_choice = vector_no; | |
472 | else if (vector_no == first_choice) | |
473 | break; | |
474 | } while (1); | |
475 | if (vector_no == first_choice) | |
476 | vector_no = 0; | |
477 | atomic_inc(&dev->rrq_outstanding[vector_no]); | |
478 | if (dev->fibs_pushed_no == 0xffffffff) | |
479 | dev->fibs_pushed_no = 0; | |
480 | else | |
481 | dev->fibs_pushed_no++; | |
482 | fib->hw_fib_va->header.Handle += (vector_no << 16); | |
483 | } | |
484 | ||
85d22bbf MR |
485 | if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2) { |
486 | /* Calculate the amount to the fibsize bits */ | |
487 | fibsize = (hdr_size + 127) / 128 - 1; | |
488 | if (fibsize > (ALIGN32 - 1)) | |
489 | return -EMSGSIZE; | |
490 | /* New FIB header, 32-bit */ | |
491 | address = fib->hw_fib_pa; | |
492 | fib->hw_fib_va->header.StructType = FIB_MAGIC2; | |
493 | fib->hw_fib_va->header.SenderFibAddress = (u32)address; | |
494 | fib->hw_fib_va->header.u.TimeStamp = 0; | |
98f99a8a | 495 | BUG_ON(upper_32_bits(address) != 0L); |
85d22bbf MR |
496 | address |= fibsize; |
497 | } else { | |
498 | /* Calculate the amount to the fibsize bits */ | |
499 | fibsize = (sizeof(struct aac_fib_xporthdr) + hdr_size + 127) / 128 - 1; | |
500 | if (fibsize > (ALIGN32 - 1)) | |
501 | return -EMSGSIZE; | |
502 | ||
503 | /* Fill XPORT header */ | |
504 | pFibX = (void *)fib->hw_fib_va - sizeof(struct aac_fib_xporthdr); | |
505 | pFibX->Handle = cpu_to_le32(fib->hw_fib_va->header.Handle); | |
506 | pFibX->HostAddress = cpu_to_le64(fib->hw_fib_pa); | |
507 | pFibX->Size = cpu_to_le32(hdr_size); | |
b5f1758f | 508 | |
85d22bbf MR |
509 | /* |
510 | * The xport header has been 32-byte aligned for us so that fibsize | |
511 | * can be masked out of this address by hardware. -- BenC | |
512 | */ | |
513 | address = fib->hw_fib_pa - sizeof(struct aac_fib_xporthdr); | |
514 | if (address & (ALIGN32 - 1)) | |
515 | return -EINVAL; | |
516 | address |= fibsize; | |
517 | } | |
c6992781 MR |
518 | #if defined(writeq) |
519 | src_writeq(dev, MUnit.IQ_L, (u64)address); | |
520 | #else | |
521 | spin_lock_irqsave(&fib->dev->iq_lock, flags); | |
98f99a8a | 522 | src_writel(dev, MUnit.IQ_H, upper_32_bits(address) & 0xffffffff); |
b5f1758f | 523 | src_writel(dev, MUnit.IQ_L, address & 0xffffffff); |
c6992781 MR |
524 | spin_unlock_irqrestore(&fib->dev->iq_lock, flags); |
525 | #endif | |
e8b12f0f MR |
526 | return 0; |
527 | } | |
528 | ||
529 | /** | |
530 | * aac_src_ioremap | |
531 | * @size: mapping resize request | |
532 | * | |
533 | */ | |
534 | static int aac_src_ioremap(struct aac_dev *dev, u32 size) | |
535 | { | |
536 | if (!size) { | |
71552505 TH |
537 | iounmap(dev->regs.src.bar1); |
538 | dev->regs.src.bar1 = NULL; | |
e8b12f0f | 539 | iounmap(dev->regs.src.bar0); |
11604612 | 540 | dev->base = dev->regs.src.bar0 = NULL; |
e8b12f0f MR |
541 | return 0; |
542 | } | |
543 | dev->regs.src.bar1 = ioremap(pci_resource_start(dev->pdev, 2), | |
544 | AAC_MIN_SRC_BAR1_SIZE); | |
545 | dev->base = NULL; | |
546 | if (dev->regs.src.bar1 == NULL) | |
547 | return -1; | |
ff08784b | 548 | dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size); |
e8b12f0f MR |
549 | if (dev->base == NULL) { |
550 | iounmap(dev->regs.src.bar1); | |
551 | dev->regs.src.bar1 = NULL; | |
552 | return -1; | |
553 | } | |
554 | dev->IndexRegs = &((struct src_registers __iomem *) | |
11604612 MR |
555 | dev->base)->u.tupelo.IndexRegs; |
556 | return 0; | |
557 | } | |
558 | ||
559 | /** | |
560 | * aac_srcv_ioremap | |
561 | * @size: mapping resize request | |
562 | * | |
563 | */ | |
564 | static int aac_srcv_ioremap(struct aac_dev *dev, u32 size) | |
565 | { | |
566 | if (!size) { | |
567 | iounmap(dev->regs.src.bar0); | |
568 | dev->base = dev->regs.src.bar0 = NULL; | |
569 | return 0; | |
570 | } | |
ff08784b | 571 | dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size); |
11604612 MR |
572 | if (dev->base == NULL) |
573 | return -1; | |
574 | dev->IndexRegs = &((struct src_registers __iomem *) | |
575 | dev->base)->u.denali.IndexRegs; | |
e8b12f0f MR |
576 | return 0; |
577 | } | |
578 | ||
579 | static int aac_src_restart_adapter(struct aac_dev *dev, int bled) | |
580 | { | |
581 | u32 var, reset_mask; | |
582 | ||
583 | if (bled >= 0) { | |
584 | if (bled) | |
585 | printk(KERN_ERR "%s%d: adapter kernel panic'd %x.\n", | |
586 | dev->name, dev->id, bled); | |
dafde947 | 587 | dev->a_ops.adapter_enable_int = aac_src_disable_interrupt; |
e8b12f0f MR |
588 | bled = aac_adapter_sync_cmd(dev, IOP_RESET_ALWAYS, |
589 | 0, 0, 0, 0, 0, 0, &var, &reset_mask, NULL, NULL, NULL); | |
dafde947 MR |
590 | if ((bled || (var != 0x00000001)) && |
591 | !dev->doorbell_mask) | |
592 | return -EINVAL; | |
593 | else if (dev->doorbell_mask) { | |
594 | reset_mask = dev->doorbell_mask; | |
595 | bled = 0; | |
596 | var = 0x00000001; | |
597 | } | |
495c0217 MR |
598 | |
599 | if ((dev->pdev->device == PMC_DEVICE_S7 || | |
600 | dev->pdev->device == PMC_DEVICE_S8 || | |
601 | dev->pdev->device == PMC_DEVICE_S9) && dev->msi_enabled) { | |
602 | aac_src_access_devreg(dev, AAC_ENABLE_INTX); | |
603 | dev->msi_enabled = 0; | |
604 | msleep(5000); /* Delay 5 seconds */ | |
605 | } | |
606 | ||
dafde947 MR |
607 | if (!bled && (dev->supplement_adapter_info.SupportedOptions2 & |
608 | AAC_OPTION_DOORBELL_RESET)) { | |
e8b12f0f | 609 | src_writel(dev, MUnit.IDR, reset_mask); |
495c0217 | 610 | ssleep(45); |
dafde947 MR |
611 | } else { |
612 | src_writel(dev, MUnit.IDR, 0x100); | |
613 | ssleep(45); | |
e8b12f0f MR |
614 | } |
615 | } | |
616 | ||
617 | if (src_readl(dev, MUnit.OMR) & KERNEL_PANIC) | |
618 | return -ENODEV; | |
619 | ||
620 | if (startup_timeout < 300) | |
621 | startup_timeout = 300; | |
622 | ||
623 | return 0; | |
624 | } | |
625 | ||
626 | /** | |
627 | * aac_src_select_comm - Select communications method | |
628 | * @dev: Adapter | |
629 | * @comm: communications method | |
630 | */ | |
631 | int aac_src_select_comm(struct aac_dev *dev, int comm) | |
632 | { | |
633 | switch (comm) { | |
634 | case AAC_COMM_MESSAGE: | |
e8b12f0f MR |
635 | dev->a_ops.adapter_intr = aac_src_intr_message; |
636 | dev->a_ops.adapter_deliver = aac_src_deliver_message; | |
637 | break; | |
638 | default: | |
639 | return 1; | |
640 | } | |
641 | return 0; | |
642 | } | |
643 | ||
644 | /** | |
645 | * aac_src_init - initialize an Cardinal Frey Bar card | |
646 | * @dev: device to configure | |
647 | * | |
648 | */ | |
649 | ||
650 | int aac_src_init(struct aac_dev *dev) | |
651 | { | |
652 | unsigned long start; | |
653 | unsigned long status; | |
654 | int restart = 0; | |
655 | int instance = dev->id; | |
656 | const char *name = dev->name; | |
657 | ||
658 | dev->a_ops.adapter_ioremap = aac_src_ioremap; | |
659 | dev->a_ops.adapter_comm = aac_src_select_comm; | |
660 | ||
661 | dev->base_size = AAC_MIN_SRC_BAR0_SIZE; | |
662 | if (aac_adapter_ioremap(dev, dev->base_size)) { | |
663 | printk(KERN_WARNING "%s: unable to map adapter.\n", name); | |
664 | goto error_iounmap; | |
665 | } | |
666 | ||
667 | /* Failure to reset here is an option ... */ | |
668 | dev->a_ops.adapter_sync_cmd = src_sync_cmd; | |
669 | dev->a_ops.adapter_enable_int = aac_src_disable_interrupt; | |
670 | if ((aac_reset_devices || reset_devices) && | |
671 | !aac_src_restart_adapter(dev, 0)) | |
672 | ++restart; | |
673 | /* | |
674 | * Check to see if the board panic'd while booting. | |
675 | */ | |
676 | status = src_readl(dev, MUnit.OMR); | |
677 | if (status & KERNEL_PANIC) { | |
678 | if (aac_src_restart_adapter(dev, aac_src_check_health(dev))) | |
679 | goto error_iounmap; | |
680 | ++restart; | |
681 | } | |
682 | /* | |
683 | * Check to see if the board failed any self tests. | |
684 | */ | |
685 | status = src_readl(dev, MUnit.OMR); | |
686 | if (status & SELF_TEST_FAILED) { | |
687 | printk(KERN_ERR "%s%d: adapter self-test failed.\n", | |
688 | dev->name, instance); | |
689 | goto error_iounmap; | |
690 | } | |
691 | /* | |
692 | * Check to see if the monitor panic'd while booting. | |
693 | */ | |
694 | if (status & MONITOR_PANIC) { | |
695 | printk(KERN_ERR "%s%d: adapter monitor panic.\n", | |
696 | dev->name, instance); | |
697 | goto error_iounmap; | |
698 | } | |
699 | start = jiffies; | |
700 | /* | |
701 | * Wait for the adapter to be up and running. Wait up to 3 minutes | |
702 | */ | |
703 | while (!((status = src_readl(dev, MUnit.OMR)) & | |
704 | KERNEL_UP_AND_RUNNING)) { | |
705 | if ((restart && | |
706 | (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) || | |
707 | time_after(jiffies, start+HZ*startup_timeout)) { | |
708 | printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n", | |
709 | dev->name, instance, status); | |
710 | goto error_iounmap; | |
711 | } | |
712 | if (!restart && | |
713 | ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) || | |
714 | time_after(jiffies, start + HZ * | |
715 | ((startup_timeout > 60) | |
716 | ? (startup_timeout - 60) | |
717 | : (startup_timeout / 2))))) { | |
718 | if (likely(!aac_src_restart_adapter(dev, | |
719 | aac_src_check_health(dev)))) | |
720 | start = jiffies; | |
721 | ++restart; | |
722 | } | |
723 | msleep(1); | |
724 | } | |
725 | if (restart && aac_commit) | |
726 | aac_commit = 1; | |
727 | /* | |
728 | * Fill in the common function dispatch table. | |
729 | */ | |
730 | dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter; | |
731 | dev->a_ops.adapter_disable_int = aac_src_disable_interrupt; | |
dafde947 | 732 | dev->a_ops.adapter_enable_int = aac_src_disable_interrupt; |
e8b12f0f MR |
733 | dev->a_ops.adapter_notify = aac_src_notify_adapter; |
734 | dev->a_ops.adapter_sync_cmd = src_sync_cmd; | |
735 | dev->a_ops.adapter_check_health = aac_src_check_health; | |
736 | dev->a_ops.adapter_restart = aac_src_restart_adapter; | |
de665f28 | 737 | dev->a_ops.adapter_start = aac_src_start_adapter; |
e8b12f0f MR |
738 | |
739 | /* | |
740 | * First clear out all interrupts. Then enable the one's that we | |
741 | * can handle. | |
742 | */ | |
743 | aac_adapter_comm(dev, AAC_COMM_MESSAGE); | |
744 | aac_adapter_disable_int(dev); | |
745 | src_writel(dev, MUnit.ODR_C, 0xffffffff); | |
746 | aac_adapter_enable_int(dev); | |
747 | ||
748 | if (aac_init_adapter(dev) == NULL) | |
749 | goto error_iounmap; | |
750 | if (dev->comm_interface != AAC_COMM_MESSAGE_TYPE1) | |
751 | goto error_iounmap; | |
752 | ||
9022d375 | 753 | dev->msi = !pci_enable_msi(dev->pdev); |
e8b12f0f | 754 | |
495c0217 MR |
755 | dev->aac_msix[0].vector_no = 0; |
756 | dev->aac_msix[0].dev = dev; | |
757 | ||
e8b12f0f | 758 | if (request_irq(dev->pdev->irq, dev->a_ops.adapter_intr, |
495c0217 | 759 | IRQF_SHARED, "aacraid", &(dev->aac_msix[0])) < 0) { |
e8b12f0f MR |
760 | |
761 | if (dev->msi) | |
762 | pci_disable_msi(dev->pdev); | |
763 | ||
764 | printk(KERN_ERR "%s%d: Interrupt unavailable.\n", | |
765 | name, instance); | |
766 | goto error_iounmap; | |
767 | } | |
768 | dev->dbg_base = pci_resource_start(dev->pdev, 2); | |
769 | dev->dbg_base_mapped = dev->regs.src.bar1; | |
770 | dev->dbg_size = AAC_MIN_SRC_BAR1_SIZE; | |
dafde947 | 771 | dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message; |
e8b12f0f MR |
772 | |
773 | aac_adapter_enable_int(dev); | |
11604612 MR |
774 | |
775 | if (!dev->sync_mode) { | |
776 | /* | |
777 | * Tell the adapter that all is configured, and it can | |
778 | * start accepting requests | |
779 | */ | |
780 | aac_src_start_adapter(dev); | |
781 | } | |
782 | return 0; | |
783 | ||
784 | error_iounmap: | |
785 | ||
786 | return -1; | |
787 | } | |
788 | ||
789 | /** | |
790 | * aac_srcv_init - initialize an SRCv card | |
791 | * @dev: device to configure | |
792 | * | |
793 | */ | |
794 | ||
795 | int aac_srcv_init(struct aac_dev *dev) | |
796 | { | |
797 | unsigned long start; | |
798 | unsigned long status; | |
799 | int restart = 0; | |
800 | int instance = dev->id; | |
801 | const char *name = dev->name; | |
802 | ||
803 | dev->a_ops.adapter_ioremap = aac_srcv_ioremap; | |
804 | dev->a_ops.adapter_comm = aac_src_select_comm; | |
805 | ||
806 | dev->base_size = AAC_MIN_SRCV_BAR0_SIZE; | |
807 | if (aac_adapter_ioremap(dev, dev->base_size)) { | |
808 | printk(KERN_WARNING "%s: unable to map adapter.\n", name); | |
809 | goto error_iounmap; | |
810 | } | |
811 | ||
812 | /* Failure to reset here is an option ... */ | |
813 | dev->a_ops.adapter_sync_cmd = src_sync_cmd; | |
814 | dev->a_ops.adapter_enable_int = aac_src_disable_interrupt; | |
815 | if ((aac_reset_devices || reset_devices) && | |
816 | !aac_src_restart_adapter(dev, 0)) | |
817 | ++restart; | |
2c10cd43 MR |
818 | /* |
819 | * Check to see if flash update is running. | |
820 | * Wait for the adapter to be up and running. Wait up to 5 minutes | |
821 | */ | |
822 | status = src_readl(dev, MUnit.OMR); | |
823 | if (status & FLASH_UPD_PENDING) { | |
824 | start = jiffies; | |
825 | do { | |
826 | status = src_readl(dev, MUnit.OMR); | |
827 | if (time_after(jiffies, start+HZ*FWUPD_TIMEOUT)) { | |
828 | printk(KERN_ERR "%s%d: adapter flash update failed.\n", | |
829 | dev->name, instance); | |
830 | goto error_iounmap; | |
831 | } | |
832 | } while (!(status & FLASH_UPD_SUCCESS) && | |
833 | !(status & FLASH_UPD_FAILED)); | |
834 | /* Delay 10 seconds. | |
835 | * Because right now FW is doing a soft reset, | |
836 | * do not read scratch pad register at this time | |
837 | */ | |
838 | ssleep(10); | |
839 | } | |
e8b12f0f | 840 | /* |
11604612 | 841 | * Check to see if the board panic'd while booting. |
e8b12f0f | 842 | */ |
11604612 MR |
843 | status = src_readl(dev, MUnit.OMR); |
844 | if (status & KERNEL_PANIC) { | |
845 | if (aac_src_restart_adapter(dev, aac_src_check_health(dev))) | |
846 | goto error_iounmap; | |
847 | ++restart; | |
848 | } | |
849 | /* | |
850 | * Check to see if the board failed any self tests. | |
851 | */ | |
852 | status = src_readl(dev, MUnit.OMR); | |
853 | if (status & SELF_TEST_FAILED) { | |
854 | printk(KERN_ERR "%s%d: adapter self-test failed.\n", dev->name, instance); | |
855 | goto error_iounmap; | |
856 | } | |
857 | /* | |
858 | * Check to see if the monitor panic'd while booting. | |
859 | */ | |
860 | if (status & MONITOR_PANIC) { | |
861 | printk(KERN_ERR "%s%d: adapter monitor panic.\n", dev->name, instance); | |
862 | goto error_iounmap; | |
863 | } | |
864 | start = jiffies; | |
865 | /* | |
866 | * Wait for the adapter to be up and running. Wait up to 3 minutes | |
867 | */ | |
2c10cd43 MR |
868 | while (!((status = src_readl(dev, MUnit.OMR)) & |
869 | KERNEL_UP_AND_RUNNING) || | |
870 | status == 0xffffffff) { | |
11604612 MR |
871 | if ((restart && |
872 | (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) || | |
873 | time_after(jiffies, start+HZ*startup_timeout)) { | |
874 | printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n", | |
875 | dev->name, instance, status); | |
876 | goto error_iounmap; | |
877 | } | |
878 | if (!restart && | |
879 | ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) || | |
880 | time_after(jiffies, start + HZ * | |
881 | ((startup_timeout > 60) | |
882 | ? (startup_timeout - 60) | |
883 | : (startup_timeout / 2))))) { | |
884 | if (likely(!aac_src_restart_adapter(dev, aac_src_check_health(dev)))) | |
885 | start = jiffies; | |
886 | ++restart; | |
887 | } | |
888 | msleep(1); | |
889 | } | |
890 | if (restart && aac_commit) | |
891 | aac_commit = 1; | |
892 | /* | |
893 | * Fill in the common function dispatch table. | |
894 | */ | |
895 | dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter; | |
896 | dev->a_ops.adapter_disable_int = aac_src_disable_interrupt; | |
dafde947 | 897 | dev->a_ops.adapter_enable_int = aac_src_disable_interrupt; |
11604612 MR |
898 | dev->a_ops.adapter_notify = aac_src_notify_adapter; |
899 | dev->a_ops.adapter_sync_cmd = src_sync_cmd; | |
900 | dev->a_ops.adapter_check_health = aac_src_check_health; | |
901 | dev->a_ops.adapter_restart = aac_src_restart_adapter; | |
de665f28 | 902 | dev->a_ops.adapter_start = aac_src_start_adapter; |
11604612 MR |
903 | |
904 | /* | |
905 | * First clear out all interrupts. Then enable the one's that we | |
906 | * can handle. | |
907 | */ | |
908 | aac_adapter_comm(dev, AAC_COMM_MESSAGE); | |
909 | aac_adapter_disable_int(dev); | |
910 | src_writel(dev, MUnit.ODR_C, 0xffffffff); | |
911 | aac_adapter_enable_int(dev); | |
e8b12f0f | 912 | |
11604612 MR |
913 | if (aac_init_adapter(dev) == NULL) |
914 | goto error_iounmap; | |
85d22bbf | 915 | if (dev->comm_interface != AAC_COMM_MESSAGE_TYPE2) |
11604612 | 916 | goto error_iounmap; |
495c0217 MR |
917 | if (dev->msi_enabled) |
918 | aac_src_access_devreg(dev, AAC_ENABLE_MSIX); | |
8b1462e0 MR |
919 | |
920 | if (aac_acquire_irq(dev)) | |
921 | goto error_iounmap; | |
922 | ||
ff08784b | 923 | dev->dbg_base = dev->base_start; |
11604612 MR |
924 | dev->dbg_base_mapped = dev->base; |
925 | dev->dbg_size = dev->base_size; | |
dafde947 | 926 | dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message; |
11604612 MR |
927 | |
928 | aac_adapter_enable_int(dev); | |
929 | ||
930 | if (!dev->sync_mode) { | |
931 | /* | |
932 | * Tell the adapter that all is configured, and it can | |
933 | * start accepting requests | |
934 | */ | |
935 | aac_src_start_adapter(dev); | |
936 | } | |
e8b12f0f MR |
937 | return 0; |
938 | ||
939 | error_iounmap: | |
940 | ||
941 | return -1; | |
942 | } | |
11604612 | 943 | |
495c0217 MR |
944 | void aac_src_access_devreg(struct aac_dev *dev, int mode) |
945 | { | |
946 | u_int32_t val; | |
947 | ||
948 | switch (mode) { | |
949 | case AAC_ENABLE_INTERRUPT: | |
950 | src_writel(dev, | |
951 | MUnit.OIMR, | |
952 | dev->OIMR = (dev->msi_enabled ? | |
953 | AAC_INT_ENABLE_TYPE1_MSIX : | |
954 | AAC_INT_ENABLE_TYPE1_INTX)); | |
955 | break; | |
956 | ||
957 | case AAC_DISABLE_INTERRUPT: | |
958 | src_writel(dev, | |
959 | MUnit.OIMR, | |
960 | dev->OIMR = AAC_INT_DISABLE_ALL); | |
961 | break; | |
962 | ||
963 | case AAC_ENABLE_MSIX: | |
964 | /* set bit 6 */ | |
965 | val = src_readl(dev, MUnit.IDR); | |
966 | val |= 0x40; | |
967 | src_writel(dev, MUnit.IDR, val); | |
968 | src_readl(dev, MUnit.IDR); | |
969 | /* unmask int. */ | |
970 | val = PMC_ALL_INTERRUPT_BITS; | |
971 | src_writel(dev, MUnit.IOAR, val); | |
972 | val = src_readl(dev, MUnit.OIMR); | |
973 | src_writel(dev, | |
974 | MUnit.OIMR, | |
975 | val & (~(PMC_GLOBAL_INT_BIT2 | PMC_GLOBAL_INT_BIT0))); | |
976 | break; | |
977 | ||
978 | case AAC_DISABLE_MSIX: | |
979 | /* reset bit 6 */ | |
980 | val = src_readl(dev, MUnit.IDR); | |
981 | val &= ~0x40; | |
982 | src_writel(dev, MUnit.IDR, val); | |
983 | src_readl(dev, MUnit.IDR); | |
984 | break; | |
985 | ||
986 | case AAC_CLEAR_AIF_BIT: | |
987 | /* set bit 5 */ | |
988 | val = src_readl(dev, MUnit.IDR); | |
989 | val |= 0x20; | |
990 | src_writel(dev, MUnit.IDR, val); | |
991 | src_readl(dev, MUnit.IDR); | |
992 | break; | |
993 | ||
994 | case AAC_CLEAR_SYNC_BIT: | |
995 | /* set bit 4 */ | |
996 | val = src_readl(dev, MUnit.IDR); | |
997 | val |= 0x10; | |
998 | src_writel(dev, MUnit.IDR, val); | |
999 | src_readl(dev, MUnit.IDR); | |
1000 | break; | |
1001 | ||
1002 | case AAC_ENABLE_INTX: | |
1003 | /* set bit 7 */ | |
1004 | val = src_readl(dev, MUnit.IDR); | |
1005 | val |= 0x80; | |
1006 | src_writel(dev, MUnit.IDR, val); | |
1007 | src_readl(dev, MUnit.IDR); | |
1008 | /* unmask int. */ | |
1009 | val = PMC_ALL_INTERRUPT_BITS; | |
1010 | src_writel(dev, MUnit.IOAR, val); | |
1011 | src_readl(dev, MUnit.IOAR); | |
1012 | val = src_readl(dev, MUnit.OIMR); | |
1013 | src_writel(dev, MUnit.OIMR, | |
1014 | val & (~(PMC_GLOBAL_INT_BIT2))); | |
1015 | break; | |
1016 | ||
1017 | default: | |
1018 | break; | |
1019 | } | |
1020 | } | |
1021 | ||
1022 | static int aac_src_get_sync_status(struct aac_dev *dev) | |
1023 | { | |
1024 | ||
1025 | int val; | |
1026 | ||
1027 | if (dev->msi_enabled) | |
1028 | val = src_readl(dev, MUnit.ODR_MSI) & 0x1000 ? 1 : 0; | |
1029 | else | |
1030 | val = src_readl(dev, MUnit.ODR_R) >> SRC_ODR_SHIFT; | |
1031 | ||
1032 | return val; | |
1033 | } |