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1da177e4
LT		 1#define ASC_VERSION "3.3K" /* AdvanSys Driver Version */
2
3/*
4 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
5 *
6 * Copyright (c) 1995-2000 Advanced System Products, Inc.
7 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
8 * All Rights Reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that redistributions of source
12 * code retain the above copyright notice and this comment without
13 * modification.
14 *
15 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
16 * changed its name to ConnectCom Solutions, Inc.
17 *
18 */
19
20/*
21
22 Documentation for the AdvanSys Driver
23
24 A. Linux Kernels Supported by this Driver
25 B. Adapters Supported by this Driver
26 C. Linux source files modified by AdvanSys Driver
27 D. Source Comments
28 E. Driver Compile Time Options and Debugging
29 F. Driver LILO Option
30 G. Tests to run before releasing new driver
31 H. Release History
32 I. Known Problems/Fix List
33 J. Credits (Chronological Order)
34
35 A. Linux Kernels Supported by this Driver
36
37 This driver has been tested in the following Linux kernels: v2.2.18
38 v2.4.0. The driver is supported on v2.2 and v2.4 kernels and on x86,
39 alpha, and PowerPC platforms.
40
41 B. Adapters Supported by this Driver
42
43 AdvanSys (Advanced System Products, Inc.) manufactures the following
44 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
45 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
46 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
47 transfer) SCSI Host Adapters for the PCI bus.
48
49 The CDB counts below indicate the number of SCSI CDB (Command
50 Descriptor Block) requests that can be stored in the RISC chip
51 cache and board LRAM. A CDB is a single SCSI command. The driver
52 detect routine will display the number of CDBs available for each
53 adapter detected. The number of CDBs used by the driver can be
54 lowered in the BIOS by changing the 'Host Queue Size' adapter setting.
55
56 Laptop Products:
57 ABP-480 - Bus-Master CardBus (16 CDB) (2.4 kernel and greater)
58
59 Connectivity Products:
60 ABP510/5150 - Bus-Master ISA (240 CDB)
61 ABP5140 - Bus-Master ISA PnP (16 CDB)
62 ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
63 ABP902/3902 - Bus-Master PCI (16 CDB)
64 ABP3905 - Bus-Master PCI (16 CDB)
65 ABP915 - Bus-Master PCI (16 CDB)
66 ABP920 - Bus-Master PCI (16 CDB)
67 ABP3922 - Bus-Master PCI (16 CDB)
68 ABP3925 - Bus-Master PCI (16 CDB)
69 ABP930 - Bus-Master PCI (16 CDB)
70 ABP930U - Bus-Master PCI Ultra (16 CDB)
71 ABP930UA - Bus-Master PCI Ultra (16 CDB)
72 ABP960 - Bus-Master PCI MAC/PC (16 CDB)
73 ABP960U - Bus-Master PCI MAC/PC Ultra (16 CDB)
74
75 Single Channel Products:
76 ABP542 - Bus-Master ISA with floppy (240 CDB)
77 ABP742 - Bus-Master EISA (240 CDB)
78 ABP842 - Bus-Master VL (240 CDB)
79 ABP940 - Bus-Master PCI (240 CDB)
80 ABP940U - Bus-Master PCI Ultra (240 CDB)
81 ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
82 ABP970 - Bus-Master PCI MAC/PC (240 CDB)
83 ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
84 ABP3960UA - Bus-Master PCI MAC/PC Ultra (240 CDB)
85 ABP940UW/3940UW - Bus-Master PCI Ultra-Wide (253 CDB)
86 ABP970UW - Bus-Master PCI MAC/PC Ultra-Wide (253 CDB)
87 ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
88
89 Multi-Channel Products:
90 ABP752 - Dual Channel Bus-Master EISA (240 CDB Per Channel)
91 ABP852 - Dual Channel Bus-Master VL (240 CDB Per Channel)
92 ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
93 ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB Per Channel)
94 ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
95 ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
96 ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
97 ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide and Ultra-Wide (253 CDB)
98 ABP3950U3W - Bus-Master PCI Dual LVD2/Ultra3-Wide (253 CDB)
99
100 C. Linux source files modified by AdvanSys Driver
101
102 This section for historical purposes documents the changes
103 originally made to the Linux kernel source to add the advansys
104 driver. As Linux has changed some of these files have also
105 been modified.
106
107 1. linux/arch/i386/config.in:
108
109 bool 'AdvanSys SCSI support' CONFIG_SCSI_ADVANSYS y
110
111 2. linux/drivers/scsi/hosts.c:
112
113 #ifdef CONFIG_SCSI_ADVANSYS
114 #include "advansys.h"
115 #endif
116
d0be4a7d 117 and after "static struct scsi_host_template builtin_scsi_hosts[] =":
1da177e4
LT		 118
119 #ifdef CONFIG_SCSI_ADVANSYS
120 ADVANSYS,
121 #endif
122
123 3. linux/drivers/scsi/Makefile:
124
125 ifdef CONFIG_SCSI_ADVANSYS
126 SCSI_SRCS := $(SCSI_SRCS) advansys.c
127 SCSI_OBJS := $(SCSI_OBJS) advansys.o
128 else
129 SCSI_MODULE_OBJS := $(SCSI_MODULE_OBJS) advansys.o
130 endif
131
132 4. linux/init/main.c:
133
134 extern void advansys_setup(char *str, int *ints);
135
136 and add the following lines to the bootsetups[] array.
137
138 #ifdef CONFIG_SCSI_ADVANSYS
139 { "advansys=", advansys_setup },
140 #endif
141
142 D. Source Comments
143
144 1. Use tab stops set to 4 for the source files. For vi use 'se tabstops=4'.
145
146 2. This driver should be maintained in multiple files. But to make
147 it easier to include with Linux and to follow Linux conventions,
148 the whole driver is maintained in the source files advansys.h and
149 advansys.c. In this file logical sections of the driver begin with
150 a comment that contains '---'. The following are the logical sections
151 of the driver below.
152
153 --- Linux Version
154 --- Linux Include File
155 --- Driver Options
156 --- Debugging Header
157 --- Asc Library Constants and Macros
158 --- Adv Library Constants and Macros
159 --- Driver Constants and Macros
160 --- Driver Structures
161 --- Driver Data
162 --- Driver Function Prototypes
d0be4a7d 163 --- Linux 'struct scsi_host_template' and advansys_setup() Functions
1da177e4
LT		 164 --- Loadable Driver Support
165 --- Miscellaneous Driver Functions
166 --- Functions Required by the Asc Library
167 --- Functions Required by the Adv Library
168 --- Tracing and Debugging Functions
169 --- Asc Library Functions
170 --- Adv Library Functions
171
172 3. The string 'XXX' is used to flag code that needs to be re-written
173 or that contains a problem that needs to be addressed.
174
175 4. I have stripped comments from and reformatted the source for the
176 Asc Library and Adv Library to reduce the size of this file. This
177 source can be found under the following headings. The Asc Library
178 is used to support Narrow Boards. The Adv Library is used to
179 support Wide Boards.
180
181 --- Asc Library Constants and Macros
182 --- Adv Library Constants and Macros
183 --- Asc Library Functions
184 --- Adv Library Functions
185
186 E. Driver Compile Time Options and Debugging
187
188 In this source file the following constants can be defined. They are
189 defined in the source below. Both of these options are enabled by
190 default.
191
192 1. ADVANSYS_ASSERT - Enable driver assertions (Def: Enabled)
193
194 Enabling this option adds assertion logic statements to the
195 driver. If an assertion fails a message will be displayed to
196 the console, but the system will continue to operate. Any
197 assertions encountered should be reported to the person
198 responsible for the driver. Assertion statements may proactively
199 detect problems with the driver and facilitate fixing these
200 problems. Enabling assertions will add a small overhead to the
201 execution of the driver.
202
203 2. ADVANSYS_DEBUG - Enable driver debugging (Def: Disabled)
204
205 Enabling this option adds tracing functions to the driver and
206 the ability to set a driver tracing level at boot time. This
207 option will also export symbols not required outside the driver to
208 the kernel name space. This option is very useful for debugging
209 the driver, but it will add to the size of the driver execution
210 image and add overhead to the execution of the driver.
211
212 The amount of debugging output can be controlled with the global
213 variable 'asc_dbglvl'. The higher the number the more output. By
214 default the debug level is 0.
215
216 If the driver is loaded at boot time and the LILO Driver Option
217 is included in the system, the debug level can be changed by
218 specifying a 5th (ASC_NUM_IOPORT_PROBE + 1) I/O Port. The
219 first three hex digits of the pseudo I/O Port must be set to
220 'deb' and the fourth hex digit specifies the debug level: 0 - F.
221 The following command line will look for an adapter at 0x330
222 and set the debug level to 2.
223
224 linux advansys=0x330,0,0,0,0xdeb2
225
226 If the driver is built as a loadable module this variable can be
227 defined when the driver is loaded. The following insmod command
228 will set the debug level to one.
229
230 insmod advansys.o asc_dbglvl=1
231
232 Debugging Message Levels:
233 0: Errors Only
234 1: High-Level Tracing
235 2-N: Verbose Tracing
236
237 To enable debug output to console, please make sure that:
238
239 a. System and kernel logging is enabled (syslogd, klogd running).
240 b. Kernel messages are routed to console output. Check
241 /etc/syslog.conf for an entry similar to this:
242
243 kern.* /dev/console
244
245 c. klogd is started with the appropriate -c parameter
246 (e.g. klogd -c 8)
247
248 This will cause printk() messages to be be displayed on the
249 current console. Refer to the klogd(8) and syslogd(8) man pages
250 for details.
251
252 Alternatively you can enable printk() to console with this
253 program. However, this is not the 'official' way to do this.
254 Debug output is logged in /var/log/messages.
255
256 main()
257 {
258 syscall(103, 7, 0, 0);
259 }
260
261 Increasing LOG_BUF_LEN in kernel/printk.c to something like
262 40960 allows more debug messages to be buffered in the kernel
263 and written to the console or log file.
264
265 3. ADVANSYS_STATS - Enable statistics (Def: Enabled >= v1.3.0)
266
267 Enabling this option adds statistics collection and display
268 through /proc to the driver. The information is useful for
269 monitoring driver and device performance. It will add to the
270 size of the driver execution image and add minor overhead to
271 the execution of the driver.
272
273 Statistics are maintained on a per adapter basis. Driver entry
274 point call counts and transfer size counts are maintained.
275 Statistics are only available for kernels greater than or equal
276 to v1.3.0 with the CONFIG_PROC_FS (/proc) file system configured.
277
278 AdvanSys SCSI adapter files have the following path name format:
279
280 /proc/scsi/advansys/[0-(ASC_NUM_BOARD_SUPPORTED-1)]
281
282 This information can be displayed with cat. For example:
283
284 cat /proc/scsi/advansys/0
285
286 When ADVANSYS_STATS is not defined the AdvanSys /proc files only
287 contain adapter and device configuration information.
288
289 F. Driver LILO Option
290
291 If init/main.c is modified as described in the 'Directions for Adding
292 the AdvanSys Driver to Linux' section (B.4.) above, the driver will
293 recognize the 'advansys' LILO command line and /etc/lilo.conf option.
294 This option can be used to either disable I/O port scanning or to limit
295 scanning to 1 - 4 I/O ports. Regardless of the option setting EISA and
296 PCI boards will still be searched for and detected. This option only
297 affects searching for ISA and VL boards.
298
299 Examples:
300 1. Eliminate I/O port scanning:
301 boot: linux advansys=
302 or
303 boot: linux advansys=0x0
304 2. Limit I/O port scanning to one I/O port:
305 boot: linux advansys=0x110
306 3. Limit I/O port scanning to four I/O ports:
307 boot: linux advansys=0x110,0x210,0x230,0x330
308
309 For a loadable module the same effect can be achieved by setting
310 the 'asc_iopflag' variable and 'asc_ioport' array when loading
311 the driver, e.g.
312
313 insmod advansys.o asc_iopflag=1 asc_ioport=0x110,0x330
314
315 If ADVANSYS_DEBUG is defined a 5th (ASC_NUM_IOPORT_PROBE + 1)
316 I/O Port may be added to specify the driver debug level. Refer to
317 the 'Driver Compile Time Options and Debugging' section above for
318 more information.
319
320 G. Tests to run before releasing new driver
321
322 1. In the supported kernels verify there are no warning or compile
323 errors when the kernel is built as both a driver and as a module
324 and with the following options:
325
326 ADVANSYS_DEBUG - enabled and disabled
327 CONFIG_SMP - enabled and disabled
328 CONFIG_PROC_FS - enabled and disabled
329
330 2. Run tests on an x86, alpha, and PowerPC with at least one narrow
331 card and one wide card attached to a hard disk and CD-ROM drive:
332 fdisk, mkfs, fsck, bonnie, copy/compare test from the
333 CD-ROM to the hard drive.
334
335 H. Release History
336
337 BETA-1.0 (12/23/95):
338 First Release
339
340 BETA-1.1 (12/28/95):
341 1. Prevent advansys_detect() from being called twice.
342 2. Add LILO 0xdeb[0-f] option to set 'asc_dbglvl'.
343
344 1.2 (1/12/96):
345 1. Prevent re-entrancy in the interrupt handler which
346 resulted in the driver hanging Linux.
347 2. Fix problem that prevented ABP-940 cards from being
348 recognized on some PCI motherboards.
349 3. Add support for the ABP-5140 PnP ISA card.
350 4. Fix check condition return status.
351 5. Add conditionally compiled code for Linux v1.3.X.
352
353 1.3 (2/23/96):
354 1. Fix problem in advansys_biosparam() that resulted in the
355 wrong drive geometry being returned for drives > 1GB with
356 extended translation enabled.
357 2. Add additional tracing during device initialization.
358 3. Change code that only applies to ISA PnP adapter.
359 4. Eliminate 'make dep' warning.
360 5. Try to fix problem with handling resets by increasing their
361 timeout value.
362
363 1.4 (5/8/96):
364 1. Change definitions to eliminate conflicts with other subsystems.
365 2. Add versioning code for the shared interrupt changes.
366 3. Eliminate problem in asc_rmqueue() with iterating after removing
367 a request.
368 4. Remove reset request loop problem from the "Known Problems or
369 Issues" section. This problem was isolated and fixed in the
370 mid-level SCSI driver.
371
372 1.5 (8/8/96):
373 1. Add support for ABP-940U (PCI Ultra) adapter.
374 2. Add support for IRQ sharing by setting the SA_SHIRQ flag for
375 request_irq and supplying a dev_id pointer to both request_irq()
376 and free_irq().
377 3. In AscSearchIOPortAddr11() restore a call to check_region() which
378 should be used before I/O port probing.
379 4. Fix bug in asc_prt_hex() which resulted in the displaying
380 the wrong data.
381 5. Incorporate miscellaneous Asc Library bug fixes and new microcode.
382 6. Change driver versioning to be specific to each Linux sub-level.
383 7. Change statistics gathering to be per adapter instead of global
384 to the driver.
385 8. Add more information and statistics to the adapter /proc file:
386 /proc/scsi/advansys[0...].
387 9. Remove 'cmd_per_lun' from the "Known Problems or Issues" list.
388 This problem has been addressed with the SCSI mid-level changes
389 made in v1.3.89. The advansys_select_queue_depths() function
390 was added for the v1.3.89 changes.
391
392 1.6 (9/10/96):
393 1. Incorporate miscellaneous Asc Library bug fixes and new microcode.
394
395 1.7 (9/25/96):
396 1. Enable clustering and optimize the setting of the maximum number
397 of scatter gather elements for any particular board. Clustering
398 increases CPU utilization, but results in a relatively larger
399 increase in I/O throughput.
400 2. Improve the performance of the request queuing functions by
401 adding a last pointer to the queue structure.
402 3. Correct problems with reset and abort request handling that
403 could have hung or crashed Linux.
404 4. Add more information to the adapter /proc file:
405 /proc/scsi/advansys[0...].
406 5. Remove the request timeout issue form the driver issues list.
407 6. Miscellaneous documentation additions and changes.
408
409 1.8 (10/4/96):
410 1. Make changes to handle the new v2.1.0 kernel memory mapping
411 in which a kernel virtual address may not be equivalent to its
412 bus or DMA memory address.
413 2. Change abort and reset request handling to make it yet even
414 more robust.
415 3. Try to mitigate request starvation by sending ordered requests
416 to heavily loaded, tag queuing enabled devices.
417 4. Maintain statistics on request response time.
418 5. Add request response time statistics and other information to
419 the adapter /proc file: /proc/scsi/advansys[0...].
420
421 1.9 (10/21/96):
422 1. Add conditionally compiled code (ASC_QUEUE_FLOW_CONTROL) to
423 make use of mid-level SCSI driver device queue depth flow
424 control mechanism. This will eliminate aborts caused by a
425 device being unable to keep up with requests and eliminate
426 repeat busy or QUEUE FULL status returned by a device.
427 2. Incorporate miscellaneous Asc Library bug fixes.
428 3. To allow the driver to work in kernels with broken module
429 support set 'cmd_per_lun' if the driver is compiled as a
430 module. This change affects kernels v1.3.89 to present.
431 4. Remove PCI BIOS address from the driver banner. The PCI BIOS
432 is relocated by the motherboard BIOS and its new address can
433 not be determined by the driver.
434 5. Add mid-level SCSI queue depth information to the adapter
435 /proc file: /proc/scsi/advansys[0...].
436
437 2.0 (11/14/96):
438 1. Change allocation of global structures used for device
439 initialization to guarantee they are in DMA-able memory.
440 Previously when the driver was loaded as a module these
441 structures might not have been in DMA-able memory, causing
442 device initialization to fail.
443
444 2.1 (12/30/96):
445 1. In advansys_reset(), if the request is a synchronous reset
446 request, even if the request serial number has changed, then
447 complete the request.
448 2. Add Asc Library bug fixes including new microcode.
449 3. Clear inquiry buffer before using it.
450 4. Correct ifdef typo.
451
452 2.2 (1/15/97):
453 1. Add Asc Library bug fixes including new microcode.
454 2. Add synchronous data transfer rate information to the
455 adapter /proc file: /proc/scsi/advansys[0...].
456 3. Change ADVANSYS_DEBUG to be disabled by default. This
457 will reduce the size of the driver image, eliminate execution
458 overhead, and remove unneeded symbols from the kernel symbol
459 space that were previously added by the driver.
460 4. Add new compile-time option ADVANSYS_ASSERT for assertion
461 code that used to be defined within ADVANSYS_DEBUG. This
462 option is enabled by default.
463
464 2.8 (5/26/97):
465 1. Change version number to 2.8 to synchronize the Linux driver
466 version numbering with other AdvanSys drivers.
467 2. Reformat source files without tabs to present the same view
468 of the file to everyone regardless of the editor tab setting
469 being used.
470 3. Add Asc Library bug fixes.
471
472 3.1A (1/8/98):
473 1. Change version number to 3.1 to indicate that support for
474 Ultra-Wide adapters (ABP-940UW) is included in this release.
475 2. Add Asc Library (Narrow Board) bug fixes.
476 3. Report an underrun condition with the host status byte set
477 to DID_UNDERRUN. Currently DID_UNDERRUN is defined to 0 which
478 causes the underrun condition to be ignored. When Linux defines
479 its own DID_UNDERRUN the constant defined in this file can be
480 removed.
481 4. Add patch to AscWaitTixISRDone().
482 5. Add support for up to 16 different AdvanSys host adapter SCSI
483 channels in one system. This allows four cards with four channels
484 to be used in one system.
485
486 3.1B (1/9/98):
487 1. Handle that PCI register base addresses are not always page
488 aligned even though ioremap() requires that the address argument
489 be page aligned.
490
491 3.1C (1/10/98):
492 1. Update latest BIOS version checked for from the /proc file.
493 2. Don't set microcode SDTR variable at initialization. Instead
494 wait until device capabilities have been detected from an Inquiry
495 command.
496
497 3.1D (1/21/98):
498 1. Improve performance when the driver is compiled as module by
499 allowing up to 64 scatter-gather elements instead of 8.
500
501 3.1E (5/1/98):
502 1. Set time delay in AscWaitTixISRDone() to 1000 ms.
503 2. Include SMP locking changes.
504 3. For v2.1.93 and newer kernels use CONFIG_PCI and new PCI BIOS
505 access functions.
506 4. Update board serial number printing.
507 5. Try allocating an IRQ both with and without the SA_INTERRUPT
508 flag set to allow IRQ sharing with drivers that do not set
509 the SA_INTERRUPT flag. Also display a more descriptive error
510 message if request_irq() fails.
511 6. Update to latest Asc and Adv Libraries.
512
513 3.2A (7/22/99):
514 1. Update Adv Library to 4.16 which includes support for
515 the ASC38C0800 (Ultra2/LVD) IC.
516
517 3.2B (8/23/99):
518 1. Correct PCI compile time option for v2.1.93 and greater
519 kernels, advansys_info() string, and debug compile time
520 option.
521 2. Correct DvcSleepMilliSecond() for v2.1.0 and greater
522 kernels. This caused an LVD detection/BIST problem problem
523 among other things.
524 3. Sort PCI cards by PCI Bus, Slot, Function ascending order
525 to be consistent with the BIOS.
526 4. Update to Asc Library S121 and Adv Library 5.2.
527
528 3.2C (8/24/99):
529 1. Correct PCI card detection bug introduced in 3.2B that
530 prevented PCI cards from being detected in kernels older
531 than v2.1.93.
532
533 3.2D (8/26/99):
534 1. Correct /proc device synchronous speed information display.
535 Also when re-negotiation is pending for a target device
536 note this condition with an * and footnote.
537 2. Correct initialization problem with Ultra-Wide cards that
538 have a pre-3.2 BIOS. A microcode variable changed locations
539 in 3.2 and greater BIOSes which caused WDTR to be attempted
540 erroneously with drives that don't support WDTR.
541
542 3.2E (8/30/99):
543 1. Fix compile error caused by v2.3.13 PCI structure change.
544 2. Remove field from ASCEEP_CONFIG that resulted in an EEPROM
545 checksum error for ISA cards.
546 3. Remove ASC_QUEUE_FLOW_CONTROL conditional code. The mid-level
547 SCSI changes that it depended on were never included in Linux.
548
549 3.2F (9/3/99):
550 1. Handle new initial function code added in v2.3.16 for all
551 driver versions.
552
553 3.2G (9/8/99):
554 1. Fix PCI board detection in v2.3.13 and greater kernels.
555 2. Fix comiple errors in v2.3.X with debugging enabled.
556
557 3.2H (9/13/99):
558 1. Add 64-bit address, long support for Alpha and UltraSPARC.
559 The driver has been verified to work on an Alpha system.
560 2. Add partial byte order handling support for Power PC and
561 other big-endian platforms. This support has not yet been
562 completed or verified.
563 3. For wide boards replace block zeroing of request and
564 scatter-gather structures with individual field initialization
565 to improve performance.
566 4. Correct and clarify ROM BIOS version detection.
567
568 3.2I (10/8/99):
569 1. Update to Adv Library 5.4.
570 2. Add v2.3.19 underrun reporting to asc_isr_callback() and
571 adv_isr_callback(). Remove DID_UNDERRUN constant and other
572 no longer needed code that previously documented the lack
573 of underrun handling.
574
575 3.2J (10/14/99):
576 1. Eliminate compile errors for v2.0 and earlier kernels.
577
578 3.2K (11/15/99):
579 1. Correct debug compile error in asc_prt_adv_scsi_req_q().
580 2. Update Adv Library to 5.5.
581 3. Add ifdef handling for /proc changes added in v2.3.28.
582 4. Increase Wide board scatter-gather list maximum length to
583 255 when the driver is compiled into the kernel.
584
585 3.2L (11/18/99):
586 1. Fix bug in adv_get_sglist() that caused an assertion failure
587 at line 7475. The reqp->sgblkp pointer must be initialized
588 to NULL in adv_get_sglist().
589
590 3.2M (11/29/99):
591 1. Really fix bug in adv_get_sglist().
592 2. Incorporate v2.3.29 changes into driver.
593
594 3.2N (4/1/00):
595 1. Add CONFIG_ISA ifdef code.
596 2. Include advansys_interrupts_enabled name change patch.
597 3. For >= v2.3.28 use new SCSI error handling with new function
598 advansys_eh_bus_reset(). Don't include an abort function
599 because of base library limitations.
600 4. For >= v2.3.28 use per board lock instead of io_request_lock.
601 5. For >= v2.3.28 eliminate advansys_command() and
602 advansys_command_done().
603 6. Add some changes for PowerPC (Big Endian) support, but it isn't
604 working yet.
605 7. Fix "nonexistent resource free" problem that occurred on a module
606 unload for boards with an I/O space >= 255. The 'n_io_port' field
607 is only one byte and can not be used to hold an ioport length more
608 than 255.
609
610 3.3A (4/4/00):
611 1. Update to Adv Library 5.8.
612 2. For wide cards add support for CDBs up to 16 bytes.
613 3. Eliminate warnings when CONFIG_PROC_FS is not defined.
614
615 3.3B (5/1/00):
616 1. Support for PowerPC (Big Endian) wide cards. Narrow cards
617 still need work.
618 2. Change bitfields to shift and mask access for endian
619 portability.
620
621 3.3C (10/13/00):
622 1. Update for latest 2.4 kernel.
623 2. Test ABP-480 CardBus support in 2.4 kernel - works!
624 3. Update to Asc Library S123.
625 4. Update to Adv Library 5.12.
626
627 3.3D (11/22/00):
628 1. Update for latest 2.4 kernel.
629 2. Create patches for 2.2 and 2.4 kernels.
630
631 3.3E (1/9/01):
632 1. Now that 2.4 is released remove ifdef code for kernel versions
633 less than 2.2. The driver is now only supported in kernels 2.2,
634 2.4, and greater.
635 2. Add code to release and acquire the io_request_lock in
636 the driver entrypoint functions: advansys_detect and
637 advansys_queuecommand. In kernel 2.4 the SCSI mid-level driver
638 still holds the io_request_lock on entry to SCSI low-level drivers.
639 This was supposed to be removed before 2.4 was released but never
640 happened. When the mid-level SCSI driver is changed all references
641 to the io_request_lock should be removed from the driver.
642 3. Simplify error handling by removing advansys_abort(),
643 AscAbortSRB(), AscResetDevice(). SCSI bus reset requests are
644 now handled by resetting the SCSI bus and fully re-initializing
645 the chip. This simple method of error recovery has proven to work
646 most reliably after attempts at different methods. Also now only
647 support the "new" error handling method and remove the obsolete
648 error handling interface.
649 4. Fix debug build errors.
650
651 3.3F (1/24/01):
652 1. Merge with ConnectCom version from Andy Kellner which
653 updates Adv Library to 5.14.
654 2. Make PowerPC (Big Endian) work for narrow cards and
655 fix problems writing EEPROM for wide cards.
656 3. Remove interrupts_enabled assertion function.
657
658 3.3G (2/16/01):
659 1. Return an error from narrow boards if passed a 16 byte
660 CDB. The wide board can already handle 16 byte CDBs.
661
662 3.3GJ (4/15/02):
663 1. hacks for lk 2.5 series (D. Gilbert)
664
665 3.3GJD (10/14/02):
666 1. change select_queue_depths to slave_configure
667 2. make cmd_per_lun be sane again
668
669 3.3K [2004/06/24]:
670 1. continuing cleanup for lk 2.6 series
671 2. Fix problem in lk 2.6.7-bk2 that broke PCI wide cards
672 3. Fix problem that oopsed ISA cards
673
674 I. Known Problems/Fix List (XXX)
675
676 1. Need to add memory mapping workaround. Test the memory mapping.
677 If it doesn't work revert to I/O port access. Can a test be done
678 safely?
679 2. Handle an interrupt not working. Keep an interrupt counter in
680 the interrupt handler. In the timeout function if the interrupt
681 has not occurred then print a message and run in polled mode.
682 3. Allow bus type scanning order to be changed.
683 4. Need to add support for target mode commands, cf. CAM XPT.
684
685 J. Credits (Chronological Order)
686
687 Bob Frey <bfrey@turbolinux.com.cn> wrote the AdvanSys SCSI driver
688 and maintained it up to 3.3F. He continues to answer questions
689 and help maintain the driver.
690
691 Nathan Hartwell <mage@cdc3.cdc.net> provided the directions and
692 basis for the Linux v1.3.X changes which were included in the
693 1.2 release.
694
695 Thomas E Zerucha <zerucha@shell.portal.com> pointed out a bug
696 in advansys_biosparam() which was fixed in the 1.3 release.
697
698 Erik Ratcliffe <erik@caldera.com> has done testing of the
699 AdvanSys driver in the Caldera releases.
700
701 Rik van Riel <H.H.vanRiel@fys.ruu.nl> provided a patch to
702 AscWaitTixISRDone() which he found necessary to make the
703 driver work with a SCSI-1 disk.
704
705 Mark Moran <mmoran@mmoran.com> has helped test Ultra-Wide
706 support in the 3.1A driver.
707
708 Doug Gilbert <dgilbert@interlog.com> has made changes and
709 suggestions to improve the driver and done a lot of testing.
710
711 Ken Mort <ken@mort.net> reported a DEBUG compile bug fixed
712 in 3.2K.
713
714 Tom Rini <trini@kernel.crashing.org> provided the CONFIG_ISA
715 patch and helped with PowerPC wide and narrow board support.
716
717 Philip Blundell <philb@gnu.org> provided an
718 advansys_interrupts_enabled patch.
719
720 Dave Jones <dave@denial.force9.co.uk> reported the compiler
721 warnings generated when CONFIG_PROC_FS was not defined in
722 the 3.2M driver.
723
724 Jerry Quinn <jlquinn@us.ibm.com> fixed PowerPC support (endian
725 problems) for wide cards.
726
727 Bryan Henderson <bryanh@giraffe-data.com> helped debug narrow
728 card error handling.
729
730 Manuel Veloso <veloso@pobox.com> worked hard on PowerPC narrow
731 board support and fixed a bug in AscGetEEPConfig().
732
733 Arnaldo Carvalho de Melo <acme@conectiva.com.br> made
734 save_flags/restore_flags changes.
735
736 Andy Kellner <AKellner@connectcom.net> continues the Advansys SCSI
737 driver development for ConnectCom (Version > 3.3F).
738
739 K. ConnectCom (AdvanSys) Contact Information
740
741 Mail: ConnectCom Solutions, Inc.
742 1150 Ringwood Court
743 San Jose, CA 95131
744 Operator/Sales: 1-408-383-9400
745 FAX: 1-408-383-9612
746 Tech Support: 1-408-467-2930
747 Tech Support E-Mail: linux@connectcom.net
748 FTP Site: ftp.connectcom.net (login: anonymous)
749 Web Site: http://www.connectcom.net
750
751*/
752
753/*
754 * --- Linux Include Files
755 */
756
757#include <linux/config.h>
758#include <linux/module.h>
759
760#if defined(CONFIG_X86) && !defined(CONFIG_ISA)
761#define CONFIG_ISA
762#endif /* CONFIG_X86 && !CONFIG_ISA */
763
764#include <linux/string.h>
765#include <linux/kernel.h>
766#include <linux/types.h>
767#include <linux/ioport.h>
768#include <linux/interrupt.h>
769#include <linux/delay.h>
770#include <linux/slab.h>
771#include <linux/mm.h>
772#include <linux/proc_fs.h>
773#include <linux/init.h>
774#include <linux/blkdev.h>
775#include <linux/stat.h>
776#include <linux/spinlock.h>
777#include <linux/dma-mapping.h>
778
779#include <asm/io.h>
780#include <asm/system.h>
781#include <asm/dma.h>
782
783/* FIXME: (by jejb@steeleye.com) This warning is present for two
784 * reasons:
785 *
786 * 1) This driver badly needs converting to the correct driver model
787 * probing API
788 *
789 * 2) Although all of the necessary command mapping places have the
790 * appropriate dma_map.. APIs, the driver still processes its internal
791 * queue using bus_to_virt() and virt_to_bus() which are illegal under
792 * the API. The entire queue processing structure will need to be
793 * altered to fix this.
794 */
795#warning this driver is still not properly converted to the DMA API
796
797#include <scsi/scsi_cmnd.h>
798#include <scsi/scsi_device.h>
799#include <scsi/scsi_tcq.h>
800#include <scsi/scsi.h>
801#include <scsi/scsi_host.h>
802#include "advansys.h"
803#ifdef CONFIG_PCI
804#include <linux/pci.h>
805#endif /* CONFIG_PCI */
806
807
808/*
809 * --- Driver Options
810 */
811
812/* Enable driver assertions. */
813#define ADVANSYS_ASSERT
814
815/* Enable driver /proc statistics. */
816#define ADVANSYS_STATS
817
818/* Enable driver tracing. */
819/* #define ADVANSYS_DEBUG */
820
821
822/*
823 * --- Debugging Header
824 */
825
826#ifdef ADVANSYS_DEBUG
827#define STATIC
828#else /* ADVANSYS_DEBUG */
829#define STATIC static
830#endif /* ADVANSYS_DEBUG */
831
832
833/*
834 * --- Asc Library Constants and Macros
835 */
836
837#define ASC_LIB_VERSION_MAJOR 1
838#define ASC_LIB_VERSION_MINOR 24
839#define ASC_LIB_SERIAL_NUMBER 123
840
841/*
842 * Portable Data Types
843 *
844 * Any instance where a 32-bit long or pointer type is assumed
845 * for precision or HW defined structures, the following define
846 * types must be used. In Linux the char, short, and int types
847 * are all consistent at 8, 16, and 32 bits respectively. Pointers
848 * and long types are 64 bits on Alpha and UltraSPARC.
849 */
850#define ASC_PADDR __u32 /* Physical/Bus address data type. */
851#define ASC_VADDR __u32 /* Virtual address data type. */
852#define ASC_DCNT __u32 /* Unsigned Data count type. */
853#define ASC_SDCNT __s32 /* Signed Data count type. */
854
855/*
856 * These macros are used to convert a virtual address to a
857 * 32-bit value. This currently can be used on Linux Alpha
858 * which uses 64-bit virtual address but a 32-bit bus address.
859 * This is likely to break in the future, but doing this now
860 * will give us time to change the HW and FW to handle 64-bit
861 * addresses.
862 */
863#define ASC_VADDR_TO_U32 virt_to_bus
864#define ASC_U32_TO_VADDR bus_to_virt
865
866typedef unsigned char uchar;
867
868#ifndef TRUE
869#define TRUE (1)
870#endif
871#ifndef FALSE
872#define FALSE (0)
873#endif
874
875#define EOF (-1)
876#define ERR (-1)
877#define UW_ERR (uint)(0xFFFF)
878#define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
879#define AscPCIConfigVendorIDRegister 0x0000
880#define AscPCIConfigDeviceIDRegister 0x0002
881#define AscPCIConfigCommandRegister 0x0004
882#define AscPCIConfigStatusRegister 0x0006
883#define AscPCIConfigRevisionIDRegister 0x0008
884#define AscPCIConfigCacheSize 0x000C
885#define AscPCIConfigLatencyTimer 0x000D
886#define AscPCIIOBaseRegister 0x0010
887#define AscPCICmdRegBits_IOMemBusMaster 0x0007
888#define ASC_PCI_ID2BUS(id) ((id) & 0xFF)
889#define ASC_PCI_ID2DEV(id) (((id) >> 11) & 0x1F)
890#define ASC_PCI_ID2FUNC(id) (((id) >> 8) & 0x7)
891#define ASC_PCI_MKID(bus, dev, func) ((((dev) & 0x1F) << 11) | (((func) & 0x7) << 8) | ((bus) & 0xFF))
892#define ASC_PCI_VENDORID 0x10CD
893#define ASC_PCI_DEVICEID_1200A 0x1100
894#define ASC_PCI_DEVICEID_1200B 0x1200
895#define ASC_PCI_DEVICEID_ULTRA 0x1300
896#define ASC_PCI_REVISION_3150 0x02
897#define ASC_PCI_REVISION_3050 0x03
898
899#define ASC_DVCLIB_CALL_DONE (1)
900#define ASC_DVCLIB_CALL_FAILED (0)
901#define ASC_DVCLIB_CALL_ERROR (-1)
902
903/*
904 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
905 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
906 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
907 * SRB structure.
908 */
909#define CC_VERY_LONG_SG_LIST 0
910#define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
911
912#define PortAddr unsigned short /* port address size */
913#define inp(port) inb(port)
914#define outp(port, byte) outb((byte), (port))
915
916#define inpw(port) inw(port)
917#define outpw(port, word) outw((word), (port))
918
919#define ASC_MAX_SG_QUEUE 7
920#define ASC_MAX_SG_LIST 255
921
922#define ASC_CS_TYPE unsigned short
923
924#define ASC_IS_ISA (0x0001)
925#define ASC_IS_ISAPNP (0x0081)
926#define ASC_IS_EISA (0x0002)
927#define ASC_IS_PCI (0x0004)
928#define ASC_IS_PCI_ULTRA (0x0104)
929#define ASC_IS_PCMCIA (0x0008)
930#define ASC_IS_MCA (0x0020)
931#define ASC_IS_VL (0x0040)
932#define ASC_ISA_PNP_PORT_ADDR (0x279)
933#define ASC_ISA_PNP_PORT_WRITE (ASC_ISA_PNP_PORT_ADDR+0x800)
934#define ASC_IS_WIDESCSI_16 (0x0100)
935#define ASC_IS_WIDESCSI_32 (0x0200)
936#define ASC_IS_BIG_ENDIAN (0x8000)
937#define ASC_CHIP_MIN_VER_VL (0x01)
938#define ASC_CHIP_MAX_VER_VL (0x07)
939#define ASC_CHIP_MIN_VER_PCI (0x09)
940#define ASC_CHIP_MAX_VER_PCI (0x0F)
941#define ASC_CHIP_VER_PCI_BIT (0x08)
942#define ASC_CHIP_MIN_VER_ISA (0x11)
943#define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
944#define ASC_CHIP_MAX_VER_ISA (0x27)
945#define ASC_CHIP_VER_ISA_BIT (0x30)
946#define ASC_CHIP_VER_ISAPNP_BIT (0x20)
947#define ASC_CHIP_VER_ASYN_BUG (0x21)
948#define ASC_CHIP_VER_PCI 0x08
949#define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
950#define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
951#define ASC_CHIP_MIN_VER_EISA (0x41)
952#define ASC_CHIP_MAX_VER_EISA (0x47)
953#define ASC_CHIP_VER_EISA_BIT (0x40)
954#define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
955#define ASC_MAX_LIB_SUPPORTED_ISA_CHIP_VER 0x21
956#define ASC_MAX_LIB_SUPPORTED_PCI_CHIP_VER 0x0A
957#define ASC_MAX_VL_DMA_ADDR (0x07FFFFFFL)
958#define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
959#define ASC_MAX_PCI_DMA_ADDR (0xFFFFFFFFL)
960#define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
961#define ASC_MAX_ISA_DMA_ADDR (0x00FFFFFFL)
962#define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
963#define ASC_MAX_EISA_DMA_ADDR (0x07FFFFFFL)
964#define ASC_MAX_EISA_DMA_COUNT (0x07FFFFFFL)
965
966#define ASC_SCSI_ID_BITS 3
967#define ASC_SCSI_TIX_TYPE uchar
968#define ASC_ALL_DEVICE_BIT_SET 0xFF
969#define ASC_SCSI_BIT_ID_TYPE uchar
970#define ASC_MAX_TID 7
971#define ASC_MAX_LUN 7
972#define ASC_SCSI_WIDTH_BIT_SET 0xFF
973#define ASC_MAX_SENSE_LEN 32
974#define ASC_MIN_SENSE_LEN 14
975#define ASC_MAX_CDB_LEN 12
976#define ASC_SCSI_RESET_HOLD_TIME_US 60
977
978#define ADV_INQ_CLOCKING_ST_ONLY 0x0
979#define ADV_INQ_CLOCKING_DT_ONLY 0x1
980#define ADV_INQ_CLOCKING_ST_AND_DT 0x3
981
982/*
983 * Inquiry SPC-2 SPI Byte 1 EVPD (Enable Vital Product Data)
984 * and CmdDt (Command Support Data) field bit definitions.
985 */
986#define ADV_INQ_RTN_VPD_AND_CMDDT 0x3
987#define ADV_INQ_RTN_CMDDT_FOR_OP_CODE 0x2
988#define ADV_INQ_RTN_VPD_FOR_PG_CODE 0x1
989#define ADV_INQ_RTN_STD_INQUIRY_DATA 0x0
990
991#define ASC_SCSIDIR_NOCHK 0x00
992#define ASC_SCSIDIR_T2H 0x08
993#define ASC_SCSIDIR_H2T 0x10
994#define ASC_SCSIDIR_NODATA 0x18
995#define SCSI_ASC_NOMEDIA 0x3A
996#define ASC_SRB_HOST(x) ((uchar)((uchar)(x) >> 4))
997#define ASC_SRB_TID(x) ((uchar)((uchar)(x) & (uchar)0x0F))
998#define ASC_SRB_LUN(x) ((uchar)((uint)(x) >> 13))
999#define PUT_CDB1(x) ((uchar)((uint)(x) >> 8))
1000#define MS_CMD_DONE 0x00
1001#define MS_EXTEND 0x01
1002#define MS_SDTR_LEN 0x03
1003#define MS_SDTR_CODE 0x01
1004#define MS_WDTR_LEN 0x02
1005#define MS_WDTR_CODE 0x03
1006#define MS_MDP_LEN 0x05
1007#define MS_MDP_CODE 0x00
1008
1009/*
1010 * Inquiry data structure and bitfield macros
1011 *
1012 * Only quantities of more than 1 bit are shifted, since the others are
1013 * just tested for true or false. C bitfields aren't portable between big
1014 * and little-endian platforms so they are not used.
1015 */
1016
1017#define ASC_INQ_DVC_TYPE(inq) ((inq)->periph & 0x1f)
1018#define ASC_INQ_QUALIFIER(inq) (((inq)->periph & 0xe0) >> 5)
1019#define ASC_INQ_DVC_TYPE_MOD(inq) ((inq)->devtype & 0x7f)
1020#define ASC_INQ_REMOVABLE(inq) ((inq)->devtype & 0x80)
1021#define ASC_INQ_ANSI_VER(inq) ((inq)->ver & 0x07)
1022#define ASC_INQ_ECMA_VER(inq) (((inq)->ver & 0x38) >> 3)
1023#define ASC_INQ_ISO_VER(inq) (((inq)->ver & 0xc0) >> 6)
1024#define ASC_INQ_RESPONSE_FMT(inq) ((inq)->byte3 & 0x0f)
1025#define ASC_INQ_TERM_IO(inq) ((inq)->byte3 & 0x40)
1026#define ASC_INQ_ASYNC_NOTIF(inq) ((inq)->byte3 & 0x80)
1027#define ASC_INQ_SOFT_RESET(inq) ((inq)->flags & 0x01)
1028#define ASC_INQ_CMD_QUEUE(inq) ((inq)->flags & 0x02)
1029#define ASC_INQ_LINK_CMD(inq) ((inq)->flags & 0x08)
1030#define ASC_INQ_SYNC(inq) ((inq)->flags & 0x10)
1031#define ASC_INQ_WIDE16(inq) ((inq)->flags & 0x20)
1032#define ASC_INQ_WIDE32(inq) ((inq)->flags & 0x40)
1033#define ASC_INQ_REL_ADDR(inq) ((inq)->flags & 0x80)
1034#define ASC_INQ_INFO_UNIT(inq) ((inq)->info & 0x01)
1035#define ASC_INQ_QUICK_ARB(inq) ((inq)->info & 0x02)
1036#define ASC_INQ_CLOCKING(inq) (((inq)->info & 0x0c) >> 2)
1037
1038typedef struct {
1039 uchar periph;
1040 uchar devtype;
1041 uchar ver;
1042 uchar byte3;
1043 uchar add_len;
1044 uchar res1;
1045 uchar res2;
1046 uchar flags;
1047 uchar vendor_id[8];
1048 uchar product_id[16];
1049 uchar product_rev_level[4];
1050} ASC_SCSI_INQUIRY;
1051
1052#define ASC_SG_LIST_PER_Q 7
1053#define QS_FREE 0x00
1054#define QS_READY 0x01
1055#define QS_DISC1 0x02
1056#define QS_DISC2 0x04
1057#define QS_BUSY 0x08
1058#define QS_ABORTED 0x40
1059#define QS_DONE 0x80
1060#define QC_NO_CALLBACK 0x01
1061#define QC_SG_SWAP_QUEUE 0x02
1062#define QC_SG_HEAD 0x04
1063#define QC_DATA_IN 0x08
1064#define QC_DATA_OUT 0x10
1065#define QC_URGENT 0x20
1066#define QC_MSG_OUT 0x40
1067#define QC_REQ_SENSE 0x80
1068#define QCSG_SG_XFER_LIST 0x02
1069#define QCSG_SG_XFER_MORE 0x04
1070#define QCSG_SG_XFER_END 0x08
1071#define QD_IN_PROGRESS 0x00
1072#define QD_NO_ERROR 0x01
1073#define QD_ABORTED_BY_HOST 0x02
1074#define QD_WITH_ERROR 0x04
1075#define QD_INVALID_REQUEST 0x80
1076#define QD_INVALID_HOST_NUM 0x81
1077#define QD_INVALID_DEVICE 0x82
1078#define QD_ERR_INTERNAL 0xFF
1079#define QHSTA_NO_ERROR 0x00
1080#define QHSTA_M_SEL_TIMEOUT 0x11
1081#define QHSTA_M_DATA_OVER_RUN 0x12
1082#define QHSTA_M_DATA_UNDER_RUN 0x12
1083#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
1084#define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
1085#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
1086#define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
1087#define QHSTA_D_HOST_ABORT_FAILED 0x23
1088#define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
1089#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
1090#define QHSTA_D_ASPI_NO_BUF_POOL 0x26
1091#define QHSTA_M_WTM_TIMEOUT 0x41
1092#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
1093#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
1094#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
1095#define QHSTA_M_TARGET_STATUS_BUSY 0x45
1096#define QHSTA_M_BAD_TAG_CODE 0x46
1097#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
1098#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
1099#define QHSTA_D_LRAM_CMP_ERROR 0x81
1100#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
1101#define ASC_FLAG_SCSIQ_REQ 0x01
1102#define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
1103#define ASC_FLAG_BIOS_ASYNC_IO 0x04
1104#define ASC_FLAG_SRB_LINEAR_ADDR 0x08
1105#define ASC_FLAG_WIN16 0x10
1106#define ASC_FLAG_WIN32 0x20
1107#define ASC_FLAG_ISA_OVER_16MB 0x40
1108#define ASC_FLAG_DOS_VM_CALLBACK 0x80
1109#define ASC_TAG_FLAG_EXTRA_BYTES 0x10
1110#define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
1111#define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
1112#define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
1113#define ASC_SCSIQ_CPY_BEG 4
1114#define ASC_SCSIQ_SGHD_CPY_BEG 2
1115#define ASC_SCSIQ_B_FWD 0
1116#define ASC_SCSIQ_B_BWD 1
1117#define ASC_SCSIQ_B_STATUS 2
1118#define ASC_SCSIQ_B_QNO 3
1119#define ASC_SCSIQ_B_CNTL 4
1120#define ASC_SCSIQ_B_SG_QUEUE_CNT 5
1121#define ASC_SCSIQ_D_DATA_ADDR 8
1122#define ASC_SCSIQ_D_DATA_CNT 12
1123#define ASC_SCSIQ_B_SENSE_LEN 20
1124#define ASC_SCSIQ_DONE_INFO_BEG 22
1125#define ASC_SCSIQ_D_SRBPTR 22
1126#define ASC_SCSIQ_B_TARGET_IX 26
1127#define ASC_SCSIQ_B_CDB_LEN 28
1128#define ASC_SCSIQ_B_TAG_CODE 29
1129#define ASC_SCSIQ_W_VM_ID 30
1130#define ASC_SCSIQ_DONE_STATUS 32
1131#define ASC_SCSIQ_HOST_STATUS 33
1132#define ASC_SCSIQ_SCSI_STATUS 34
1133#define ASC_SCSIQ_CDB_BEG 36
1134#define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
1135#define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
1136#define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
1137#define ASC_SCSIQ_B_SG_WK_QP 49
1138#define ASC_SCSIQ_B_SG_WK_IX 50
1139#define ASC_SCSIQ_W_ALT_DC1 52
1140#define ASC_SCSIQ_B_LIST_CNT 6
1141#define ASC_SCSIQ_B_CUR_LIST_CNT 7
1142#define ASC_SGQ_B_SG_CNTL 4
1143#define ASC_SGQ_B_SG_HEAD_QP 5
1144#define ASC_SGQ_B_SG_LIST_CNT 6
1145#define ASC_SGQ_B_SG_CUR_LIST_CNT 7
1146#define ASC_SGQ_LIST_BEG 8
1147#define ASC_DEF_SCSI1_QNG 4
1148#define ASC_MAX_SCSI1_QNG 4
1149#define ASC_DEF_SCSI2_QNG 16
1150#define ASC_MAX_SCSI2_QNG 32
1151#define ASC_TAG_CODE_MASK 0x23
1152#define ASC_STOP_REQ_RISC_STOP 0x01
1153#define ASC_STOP_ACK_RISC_STOP 0x03
1154#define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
1155#define ASC_STOP_CLEAN_UP_DISC_Q 0x20
1156#define ASC_STOP_HOST_REQ_RISC_HALT 0x40
1157#define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
1158#define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
1159#define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
1160#define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
1161#define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
1162#define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
1163#define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
1164
1165typedef struct asc_scsiq_1 {
1166 uchar status;
1167 uchar q_no;
1168 uchar cntl;
1169 uchar sg_queue_cnt;
1170 uchar target_id;
1171 uchar target_lun;
1172 ASC_PADDR data_addr;
1173 ASC_DCNT data_cnt;
1174 ASC_PADDR sense_addr;
1175 uchar sense_len;
1176 uchar extra_bytes;
1177} ASC_SCSIQ_1;
1178
1179typedef struct asc_scsiq_2 {
1180 ASC_VADDR srb_ptr;
1181 uchar target_ix;
1182 uchar flag;
1183 uchar cdb_len;
1184 uchar tag_code;
1185 ushort vm_id;
1186} ASC_SCSIQ_2;
1187
1188typedef struct asc_scsiq_3 {
1189 uchar done_stat;
1190 uchar host_stat;
1191 uchar scsi_stat;
1192 uchar scsi_msg;
1193} ASC_SCSIQ_3;
1194
1195typedef struct asc_scsiq_4 {
1196 uchar cdb[ASC_MAX_CDB_LEN];
1197 uchar y_first_sg_list_qp;
1198 uchar y_working_sg_qp;
1199 uchar y_working_sg_ix;
1200 uchar y_res;
1201 ushort x_req_count;
1202 ushort x_reconnect_rtn;
1203 ASC_PADDR x_saved_data_addr;
1204 ASC_DCNT x_saved_data_cnt;
1205} ASC_SCSIQ_4;
1206
1207typedef struct asc_q_done_info {
1208 ASC_SCSIQ_2 d2;
1209 ASC_SCSIQ_3 d3;
1210 uchar q_status;
1211 uchar q_no;
1212 uchar cntl;
1213 uchar sense_len;
1214 uchar extra_bytes;
1215 uchar res;
1216 ASC_DCNT remain_bytes;
1217} ASC_QDONE_INFO;
1218
1219typedef struct asc_sg_list {
1220 ASC_PADDR addr;
1221 ASC_DCNT bytes;
1222} ASC_SG_LIST;
1223
1224typedef struct asc_sg_head {
1225 ushort entry_cnt;
1226 ushort queue_cnt;
1227 ushort entry_to_copy;
1228 ushort res;
1229 ASC_SG_LIST sg_list[ASC_MAX_SG_LIST];
1230} ASC_SG_HEAD;
1231
1232#define ASC_MIN_SG_LIST 2
1233
1234typedef struct asc_min_sg_head {
1235 ushort entry_cnt;
1236 ushort queue_cnt;
1237 ushort entry_to_copy;
1238 ushort res;
1239 ASC_SG_LIST sg_list[ASC_MIN_SG_LIST];
1240} ASC_MIN_SG_HEAD;
1241
1242#define QCX_SORT (0x0001)
1243#define QCX_COALEASE (0x0002)
1244
1245typedef struct asc_scsi_q {
1246 ASC_SCSIQ_1 q1;
1247 ASC_SCSIQ_2 q2;
1248 uchar *cdbptr;
1249 ASC_SG_HEAD *sg_head;
1250 ushort remain_sg_entry_cnt;
1251 ushort next_sg_index;
1252} ASC_SCSI_Q;
1253
1254typedef struct asc_scsi_req_q {
1255 ASC_SCSIQ_1 r1;
1256 ASC_SCSIQ_2 r2;
1257 uchar *cdbptr;
1258 ASC_SG_HEAD *sg_head;
1259 uchar *sense_ptr;
1260 ASC_SCSIQ_3 r3;
1261 uchar cdb[ASC_MAX_CDB_LEN];
1262 uchar sense[ASC_MIN_SENSE_LEN];
1263} ASC_SCSI_REQ_Q;
1264
1265typedef struct asc_scsi_bios_req_q {
1266 ASC_SCSIQ_1 r1;
1267 ASC_SCSIQ_2 r2;
1268 uchar *cdbptr;
1269 ASC_SG_HEAD *sg_head;
1270 uchar *sense_ptr;
1271 ASC_SCSIQ_3 r3;
1272 uchar cdb[ASC_MAX_CDB_LEN];
1273 uchar sense[ASC_MIN_SENSE_LEN];
1274} ASC_SCSI_BIOS_REQ_Q;
1275
1276typedef struct asc_risc_q {
1277 uchar fwd;
1278 uchar bwd;
1279 ASC_SCSIQ_1 i1;
1280 ASC_SCSIQ_2 i2;
1281 ASC_SCSIQ_3 i3;
1282 ASC_SCSIQ_4 i4;
1283} ASC_RISC_Q;
1284
1285typedef struct asc_sg_list_q {
1286 uchar seq_no;
1287 uchar q_no;
1288 uchar cntl;
1289 uchar sg_head_qp;
1290 uchar sg_list_cnt;
1291 uchar sg_cur_list_cnt;
1292} ASC_SG_LIST_Q;
1293
1294typedef struct asc_risc_sg_list_q {
1295 uchar fwd;
1296 uchar bwd;
1297 ASC_SG_LIST_Q sg;
1298 ASC_SG_LIST sg_list[7];
1299} ASC_RISC_SG_LIST_Q;
1300
1301#define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP 0x1000000UL
1302#define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP 1024
1303#define ASCQ_ERR_NO_ERROR 0
1304#define ASCQ_ERR_IO_NOT_FOUND 1
1305#define ASCQ_ERR_LOCAL_MEM 2
1306#define ASCQ_ERR_CHKSUM 3
1307#define ASCQ_ERR_START_CHIP 4
1308#define ASCQ_ERR_INT_TARGET_ID 5
1309#define ASCQ_ERR_INT_LOCAL_MEM 6
1310#define ASCQ_ERR_HALT_RISC 7
1311#define ASCQ_ERR_GET_ASPI_ENTRY 8
1312#define ASCQ_ERR_CLOSE_ASPI 9
1313#define ASCQ_ERR_HOST_INQUIRY 0x0A
1314#define ASCQ_ERR_SAVED_SRB_BAD 0x0B
1315#define ASCQ_ERR_QCNTL_SG_LIST 0x0C
1316#define ASCQ_ERR_Q_STATUS 0x0D
1317#define ASCQ_ERR_WR_SCSIQ 0x0E
1318#define ASCQ_ERR_PC_ADDR 0x0F
1319#define ASCQ_ERR_SYN_OFFSET 0x10
1320#define ASCQ_ERR_SYN_XFER_TIME 0x11
1321#define ASCQ_ERR_LOCK_DMA 0x12
1322#define ASCQ_ERR_UNLOCK_DMA 0x13
1323#define ASCQ_ERR_VDS_CHK_INSTALL 0x14
1324#define ASCQ_ERR_MICRO_CODE_HALT 0x15
1325#define ASCQ_ERR_SET_LRAM_ADDR 0x16
1326#define ASCQ_ERR_CUR_QNG 0x17
1327#define ASCQ_ERR_SG_Q_LINKS 0x18
1328#define ASCQ_ERR_SCSIQ_PTR 0x19
1329#define ASCQ_ERR_ISR_RE_ENTRY 0x1A
1330#define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
1331#define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
1332#define ASCQ_ERR_SG_LIST_ODD_ADDRESS 0x1D
1333#define ASCQ_ERR_XFER_ADDRESS_TOO_BIG 0x1E
1334#define ASCQ_ERR_SCSIQ_NULL_PTR 0x1F
1335#define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 0x20
1336#define ASCQ_ERR_GET_NUM_OF_FREE_Q 0x21
1337#define ASCQ_ERR_SEND_SCSI_Q 0x22
1338#define ASCQ_ERR_HOST_REQ_RISC_HALT 0x23
1339#define ASCQ_ERR_RESET_SDTR 0x24
1340
1341/*
1342 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
1343 */
1344#define ASC_WARN_NO_ERROR 0x0000
1345#define ASC_WARN_IO_PORT_ROTATE 0x0001
1346#define ASC_WARN_EEPROM_CHKSUM 0x0002
1347#define ASC_WARN_IRQ_MODIFIED 0x0004
1348#define ASC_WARN_AUTO_CONFIG 0x0008
1349#define ASC_WARN_CMD_QNG_CONFLICT 0x0010
1350#define ASC_WARN_EEPROM_RECOVER 0x0020
1351#define ASC_WARN_CFG_MSW_RECOVER 0x0040
1352#define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080
1353
1354/*
1355 * Error code values are set in ASC_DVC_VAR 'err_code'.
1356 */
1357#define ASC_IERR_WRITE_EEPROM 0x0001
1358#define ASC_IERR_MCODE_CHKSUM 0x0002
1359#define ASC_IERR_SET_PC_ADDR 0x0004
1360#define ASC_IERR_START_STOP_CHIP 0x0008
1361#define ASC_IERR_IRQ_NO 0x0010
1362#define ASC_IERR_SET_IRQ_NO 0x0020
1363#define ASC_IERR_CHIP_VERSION 0x0040
1364#define ASC_IERR_SET_SCSI_ID 0x0080
1365#define ASC_IERR_GET_PHY_ADDR 0x0100
1366#define ASC_IERR_BAD_SIGNATURE 0x0200
1367#define ASC_IERR_NO_BUS_TYPE 0x0400
1368#define ASC_IERR_SCAM 0x0800
1369#define ASC_IERR_SET_SDTR 0x1000
1370#define ASC_IERR_RW_LRAM 0x8000
1371
1372#define ASC_DEF_IRQ_NO 10
1373#define ASC_MAX_IRQ_NO 15
1374#define ASC_MIN_IRQ_NO 10
1375#define ASC_MIN_REMAIN_Q (0x02)
1376#define ASC_DEF_MAX_TOTAL_QNG (0xF0)
1377#define ASC_MIN_TAG_Q_PER_DVC (0x04)
1378#define ASC_DEF_TAG_Q_PER_DVC (0x04)
1379#define ASC_MIN_FREE_Q ASC_MIN_REMAIN_Q
1380#define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
1381#define ASC_MAX_TOTAL_QNG 240
1382#define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
1383#define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
1384#define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
1385#define ASC_MAX_INRAM_TAG_QNG 16
1386#define ASC_IOADR_TABLE_MAX_IX 11
1387#define ASC_IOADR_GAP 0x10
1388#define ASC_SEARCH_IOP_GAP 0x10
1389#define ASC_MIN_IOP_ADDR (PortAddr)0x0100
1390#define ASC_MAX_IOP_ADDR (PortAddr)0x3F0
1391#define ASC_IOADR_1 (PortAddr)0x0110
1392#define ASC_IOADR_2 (PortAddr)0x0130
1393#define ASC_IOADR_3 (PortAddr)0x0150
1394#define ASC_IOADR_4 (PortAddr)0x0190
1395#define ASC_IOADR_5 (PortAddr)0x0210
1396#define ASC_IOADR_6 (PortAddr)0x0230
1397#define ASC_IOADR_7 (PortAddr)0x0250
1398#define ASC_IOADR_8 (PortAddr)0x0330
1399#define ASC_IOADR_DEF ASC_IOADR_8
1400#define ASC_LIB_SCSIQ_WK_SP 256
1401#define ASC_MAX_SYN_XFER_NO 16
1402#define ASC_SYN_MAX_OFFSET 0x0F
1403#define ASC_DEF_SDTR_OFFSET 0x0F
1404#define ASC_DEF_SDTR_INDEX 0x00
1405#define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
1406#define SYN_XFER_NS_0 25
1407#define SYN_XFER_NS_1 30
1408#define SYN_XFER_NS_2 35
1409#define SYN_XFER_NS_3 40
1410#define SYN_XFER_NS_4 50
1411#define SYN_XFER_NS_5 60
1412#define SYN_XFER_NS_6 70
1413#define SYN_XFER_NS_7 85
1414#define SYN_ULTRA_XFER_NS_0 12
1415#define SYN_ULTRA_XFER_NS_1 19
1416#define SYN_ULTRA_XFER_NS_2 25
1417#define SYN_ULTRA_XFER_NS_3 32
1418#define SYN_ULTRA_XFER_NS_4 38
1419#define SYN_ULTRA_XFER_NS_5 44
1420#define SYN_ULTRA_XFER_NS_6 50
1421#define SYN_ULTRA_XFER_NS_7 57
1422#define SYN_ULTRA_XFER_NS_8 63
1423#define SYN_ULTRA_XFER_NS_9 69
1424#define SYN_ULTRA_XFER_NS_10 75
1425#define SYN_ULTRA_XFER_NS_11 82
1426#define SYN_ULTRA_XFER_NS_12 88
1427#define SYN_ULTRA_XFER_NS_13 94
1428#define SYN_ULTRA_XFER_NS_14 100
1429#define SYN_ULTRA_XFER_NS_15 107
1430
1431typedef struct ext_msg {
1432 uchar msg_type;
1433 uchar msg_len;
1434 uchar msg_req;
1435 union {
1436 struct {
1437 uchar sdtr_xfer_period;
1438 uchar sdtr_req_ack_offset;
1439 } sdtr;
1440 struct {
1441 uchar wdtr_width;
1442 } wdtr;
1443 struct {
1444 uchar mdp_b3;
1445 uchar mdp_b2;
1446 uchar mdp_b1;
1447 uchar mdp_b0;
1448 } mdp;
1449 } u_ext_msg;
1450 uchar res;
1451} EXT_MSG;
1452
1453#define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
1454#define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
1455#define wdtr_width u_ext_msg.wdtr.wdtr_width
1456#define mdp_b3 u_ext_msg.mdp_b3
1457#define mdp_b2 u_ext_msg.mdp_b2
1458#define mdp_b1 u_ext_msg.mdp_b1
1459#define mdp_b0 u_ext_msg.mdp_b0
1460
1461typedef struct asc_dvc_cfg {
1462 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
1463 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
1464 ASC_SCSI_BIT_ID_TYPE disc_enable;
1465 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
1466 uchar chip_scsi_id;
1467 uchar isa_dma_speed;
1468 uchar isa_dma_channel;
1469 uchar chip_version;
1470 ushort lib_serial_no;
1471 ushort lib_version;
1472 ushort mcode_date;
1473 ushort mcode_version;
1474 uchar max_tag_qng[ASC_MAX_TID + 1];
1475 uchar *overrun_buf;
1476 uchar sdtr_period_offset[ASC_MAX_TID + 1];
1477 ushort pci_slot_info;
1478 uchar adapter_info[6];
1479 struct device *dev;
1480} ASC_DVC_CFG;
1481
1482#define ASC_DEF_DVC_CNTL 0xFFFF
1483#define ASC_DEF_CHIP_SCSI_ID 7
1484#define ASC_DEF_ISA_DMA_SPEED 4
1485#define ASC_INIT_STATE_NULL 0x0000
1486#define ASC_INIT_STATE_BEG_GET_CFG 0x0001
1487#define ASC_INIT_STATE_END_GET_CFG 0x0002
1488#define ASC_INIT_STATE_BEG_SET_CFG 0x0004
1489#define ASC_INIT_STATE_END_SET_CFG 0x0008
1490#define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
1491#define ASC_INIT_STATE_END_LOAD_MC 0x0020
1492#define ASC_INIT_STATE_BEG_INQUIRY 0x0040
1493#define ASC_INIT_STATE_END_INQUIRY 0x0080
1494#define ASC_INIT_RESET_SCSI_DONE 0x0100
1495#define ASC_INIT_STATE_WITHOUT_EEP 0x8000
1496#define ASC_PCI_DEVICE_ID_REV_A 0x1100
1497#define ASC_PCI_DEVICE_ID_REV_B 0x1200
1498#define ASC_BUG_FIX_IF_NOT_DWB 0x0001
1499#define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
1500#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
1501#define ASC_MIN_TAGGED_CMD 7
1502#define ASC_MAX_SCSI_RESET_WAIT 30
1503
1504struct asc_dvc_var; /* Forward Declaration. */
1505
1506typedef void (* ASC_ISR_CALLBACK)(struct asc_dvc_var *, ASC_QDONE_INFO *);
1507typedef int (* ASC_EXE_CALLBACK)(struct asc_dvc_var *, ASC_SCSI_Q *);
1508
1509typedef struct asc_dvc_var {
1510 PortAddr iop_base;
1511 ushort err_code;
1512 ushort dvc_cntl;
1513 ushort bug_fix_cntl;
1514 ushort bus_type;
1515 ASC_ISR_CALLBACK isr_callback;
1516 ASC_EXE_CALLBACK exe_callback;
1517 ASC_SCSI_BIT_ID_TYPE init_sdtr;
1518 ASC_SCSI_BIT_ID_TYPE sdtr_done;
1519 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
1520 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
1521 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
1522 ASC_SCSI_BIT_ID_TYPE start_motor;
1523 uchar scsi_reset_wait;
1524 uchar chip_no;
1525 char is_in_int;
1526 uchar max_total_qng;
1527 uchar cur_total_qng;
1528 uchar in_critical_cnt;
1529 uchar irq_no;
1530 uchar last_q_shortage;
1531 ushort init_state;
1532 uchar cur_dvc_qng[ASC_MAX_TID + 1];
1533 uchar max_dvc_qng[ASC_MAX_TID + 1];
1534 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
1535 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
1536 uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
1537 ASC_DVC_CFG *cfg;
1538 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
1539 char redo_scam;
1540 ushort res2;
1541 uchar dos_int13_table[ASC_MAX_TID + 1];
1542 ASC_DCNT max_dma_count;
1543 ASC_SCSI_BIT_ID_TYPE no_scam;
1544 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
1545 uchar max_sdtr_index;
1546 uchar host_init_sdtr_index;
1547 struct asc_board *drv_ptr;
1548 ASC_DCNT uc_break;
1549} ASC_DVC_VAR;
1550
1551typedef struct asc_dvc_inq_info {
1552 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1553} ASC_DVC_INQ_INFO;
1554
1555typedef struct asc_cap_info {
1556 ASC_DCNT lba;
1557 ASC_DCNT blk_size;
1558} ASC_CAP_INFO;
1559
1560typedef struct asc_cap_info_array {
1561 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1562} ASC_CAP_INFO_ARRAY;
1563
1564#define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
1565#define ASC_MCNTL_NULL_TARGET (ushort)0x0002
1566#define ASC_CNTL_INITIATOR (ushort)0x0001
1567#define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
1568#define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
1569#define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
1570#define ASC_CNTL_NO_SCAM (ushort)0x0010
1571#define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
1572#define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
1573#define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
1574#define ASC_CNTL_RESET_SCSI (ushort)0x0200
1575#define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
1576#define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
1577#define ASC_CNTL_SCSI_PARITY (ushort)0x1000
1578#define ASC_CNTL_BURST_MODE (ushort)0x2000
1579#define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
1580#define ASC_EEP_DVC_CFG_BEG_VL 2
1581#define ASC_EEP_MAX_DVC_ADDR_VL 15
1582#define ASC_EEP_DVC_CFG_BEG 32
1583#define ASC_EEP_MAX_DVC_ADDR 45
1584#define ASC_EEP_DEFINED_WORDS 10
1585#define ASC_EEP_MAX_ADDR 63
1586#define ASC_EEP_RES_WORDS 0
1587#define ASC_EEP_MAX_RETRY 20
1588#define ASC_MAX_INIT_BUSY_RETRY 8
1589#define ASC_EEP_ISA_PNP_WSIZE 16
1590
1591/*
1592 * These macros keep the chip SCSI id and ISA DMA speed
1593 * bitfields in board order. C bitfields aren't portable
1594 * between big and little-endian platforms so they are
1595 * not used.
1596 */
1597
1598#define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
1599#define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
1600#define ASC_EEP_SET_CHIP_ID(cfg, sid) \
1601 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
1602#define ASC_EEP_SET_DMA_SPD(cfg, spd) \
1603 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
1604
1605typedef struct asceep_config {
1606 ushort cfg_lsw;
1607 ushort cfg_msw;
1608 uchar init_sdtr;
1609 uchar disc_enable;
1610 uchar use_cmd_qng;
1611 uchar start_motor;
1612 uchar max_total_qng;
1613 uchar max_tag_qng;
1614 uchar bios_scan;
1615 uchar power_up_wait;
1616 uchar no_scam;
1617 uchar id_speed; /* low order 4 bits is chip scsi id */
1618 /* high order 4 bits is isa dma speed */
1619 uchar dos_int13_table[ASC_MAX_TID + 1];
1620 uchar adapter_info[6];
1621 ushort cntl;
1622 ushort chksum;
1623} ASCEEP_CONFIG;
1624
1625#define ASC_PCI_CFG_LSW_SCSI_PARITY 0x0800
1626#define ASC_PCI_CFG_LSW_BURST_MODE 0x0080
1627#define ASC_PCI_CFG_LSW_INTR_ABLE 0x0020
1628
1629#define ASC_EEP_CMD_READ 0x80
1630#define ASC_EEP_CMD_WRITE 0x40
1631#define ASC_EEP_CMD_WRITE_ABLE 0x30
1632#define ASC_EEP_CMD_WRITE_DISABLE 0x00
1633#define ASC_OVERRUN_BSIZE 0x00000048UL
1634#define ASC_CTRL_BREAK_ONCE 0x0001
1635#define ASC_CTRL_BREAK_STAY_IDLE 0x0002
1636#define ASCV_MSGOUT_BEG 0x0000
1637#define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
1638#define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
1639#define ASCV_BREAK_SAVED_CODE (ushort)0x0006
1640#define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
1641#define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
1642#define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
1643#define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
1644#define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
1645#define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
1646#define ASCV_BREAK_ADDR (ushort)0x0028
1647#define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
1648#define ASCV_BREAK_CONTROL (ushort)0x002C
1649#define ASCV_BREAK_HIT_COUNT (ushort)0x002E
1650
1651#define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
1652#define ASCV_MCODE_CHKSUM_W (ushort)0x0032
1653#define ASCV_MCODE_SIZE_W (ushort)0x0034
1654#define ASCV_STOP_CODE_B (ushort)0x0036
1655#define ASCV_DVC_ERR_CODE_B (ushort)0x0037
1656#define ASCV_OVERRUN_PADDR_D (ushort)0x0038
1657#define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
1658#define ASCV_HALTCODE_W (ushort)0x0040
1659#define ASCV_CHKSUM_W (ushort)0x0042
1660#define ASCV_MC_DATE_W (ushort)0x0044
1661#define ASCV_MC_VER_W (ushort)0x0046
1662#define ASCV_NEXTRDY_B (ushort)0x0048
1663#define ASCV_DONENEXT_B (ushort)0x0049
1664#define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
1665#define ASCV_SCSIBUSY_B (ushort)0x004B
1666#define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
1667#define ASCV_CURCDB_B (ushort)0x004D
1668#define ASCV_RCLUN_B (ushort)0x004E
1669#define ASCV_BUSY_QHEAD_B (ushort)0x004F
1670#define ASCV_DISC1_QHEAD_B (ushort)0x0050
1671#define ASCV_DISC_ENABLE_B (ushort)0x0052
1672#define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
1673#define ASCV_HOSTSCSI_ID_B (ushort)0x0055
1674#define ASCV_MCODE_CNTL_B (ushort)0x0056
1675#define ASCV_NULL_TARGET_B (ushort)0x0057
1676#define ASCV_FREE_Q_HEAD_W (ushort)0x0058
1677#define ASCV_DONE_Q_TAIL_W (ushort)0x005A
1678#define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
1679#define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
1680#define ASCV_HOST_FLAG_B (ushort)0x005D
1681#define ASCV_TOTAL_READY_Q_B (ushort)0x0064
1682#define ASCV_VER_SERIAL_B (ushort)0x0065
1683#define ASCV_HALTCODE_SAVED_W (ushort)0x0066
1684#define ASCV_WTM_FLAG_B (ushort)0x0068
1685#define ASCV_RISC_FLAG_B (ushort)0x006A
1686#define ASCV_REQ_SG_LIST_QP (ushort)0x006B
1687#define ASC_HOST_FLAG_IN_ISR 0x01
1688#define ASC_HOST_FLAG_ACK_INT 0x02
1689#define ASC_RISC_FLAG_GEN_INT 0x01
1690#define ASC_RISC_FLAG_REQ_SG_LIST 0x02
1691#define IOP_CTRL (0x0F)
1692#define IOP_STATUS (0x0E)
1693#define IOP_INT_ACK IOP_STATUS
1694#define IOP_REG_IFC (0x0D)
1695#define IOP_SYN_OFFSET (0x0B)
1696#define IOP_EXTRA_CONTROL (0x0D)
1697#define IOP_REG_PC (0x0C)
1698#define IOP_RAM_ADDR (0x0A)
1699#define IOP_RAM_DATA (0x08)
1700#define IOP_EEP_DATA (0x06)
1701#define IOP_EEP_CMD (0x07)
1702#define IOP_VERSION (0x03)
1703#define IOP_CONFIG_HIGH (0x04)
1704#define IOP_CONFIG_LOW (0x02)
1705#define IOP_SIG_BYTE (0x01)
1706#define IOP_SIG_WORD (0x00)
1707#define IOP_REG_DC1 (0x0E)
1708#define IOP_REG_DC0 (0x0C)
1709#define IOP_REG_SB (0x0B)
1710#define IOP_REG_DA1 (0x0A)
1711#define IOP_REG_DA0 (0x08)
1712#define IOP_REG_SC (0x09)
1713#define IOP_DMA_SPEED (0x07)
1714#define IOP_REG_FLAG (0x07)
1715#define IOP_FIFO_H (0x06)
1716#define IOP_FIFO_L (0x04)
1717#define IOP_REG_ID (0x05)
1718#define IOP_REG_QP (0x03)
1719#define IOP_REG_IH (0x02)
1720#define IOP_REG_IX (0x01)
1721#define IOP_REG_AX (0x00)
1722#define IFC_REG_LOCK (0x00)
1723#define IFC_REG_UNLOCK (0x09)
1724#define IFC_WR_EN_FILTER (0x10)
1725#define IFC_RD_NO_EEPROM (0x10)
1726#define IFC_SLEW_RATE (0x20)
1727#define IFC_ACT_NEG (0x40)
1728#define IFC_INP_FILTER (0x80)
1729#define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
1730#define SC_SEL (uchar)(0x80)
1731#define SC_BSY (uchar)(0x40)
1732#define SC_ACK (uchar)(0x20)
1733#define SC_REQ (uchar)(0x10)
1734#define SC_ATN (uchar)(0x08)
1735#define SC_IO (uchar)(0x04)
1736#define SC_CD (uchar)(0x02)
1737#define SC_MSG (uchar)(0x01)
1738#define SEC_SCSI_CTL (uchar)(0x80)
1739#define SEC_ACTIVE_NEGATE (uchar)(0x40)
1740#define SEC_SLEW_RATE (uchar)(0x20)
1741#define SEC_ENABLE_FILTER (uchar)(0x10)
1742#define ASC_HALT_EXTMSG_IN (ushort)0x8000
1743#define ASC_HALT_CHK_CONDITION (ushort)0x8100
1744#define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
1745#define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
1746#define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
1747#define ASC_HALT_SDTR_REJECTED (ushort)0x4000
1748#define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
1749#define ASC_MAX_QNO 0xF8
1750#define ASC_DATA_SEC_BEG (ushort)0x0080
1751#define ASC_DATA_SEC_END (ushort)0x0080
1752#define ASC_CODE_SEC_BEG (ushort)0x0080
1753#define ASC_CODE_SEC_END (ushort)0x0080
1754#define ASC_QADR_BEG (0x4000)
1755#define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
1756#define ASC_QADR_END (ushort)0x7FFF
1757#define ASC_QLAST_ADR (ushort)0x7FC0
1758#define ASC_QBLK_SIZE 0x40
1759#define ASC_BIOS_DATA_QBEG 0xF8
1760#define ASC_MIN_ACTIVE_QNO 0x01
1761#define ASC_QLINK_END 0xFF
1762#define ASC_EEPROM_WORDS 0x10
1763#define ASC_MAX_MGS_LEN 0x10
1764#define ASC_BIOS_ADDR_DEF 0xDC00
1765#define ASC_BIOS_SIZE 0x3800
1766#define ASC_BIOS_RAM_OFF 0x3800
1767#define ASC_BIOS_RAM_SIZE 0x800
1768#define ASC_BIOS_MIN_ADDR 0xC000
1769#define ASC_BIOS_MAX_ADDR 0xEC00
1770#define ASC_BIOS_BANK_SIZE 0x0400
1771#define ASC_MCODE_START_ADDR 0x0080
1772#define ASC_CFG0_HOST_INT_ON 0x0020
1773#define ASC_CFG0_BIOS_ON 0x0040
1774#define ASC_CFG0_VERA_BURST_ON 0x0080
1775#define ASC_CFG0_SCSI_PARITY_ON 0x0800
1776#define ASC_CFG1_SCSI_TARGET_ON 0x0080
1777#define ASC_CFG1_LRAM_8BITS_ON 0x0800
1778#define ASC_CFG_MSW_CLR_MASK 0x3080
1779#define CSW_TEST1 (ASC_CS_TYPE)0x8000
1780#define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
1781#define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
1782#define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
1783#define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
1784#define CSW_TEST2 (ASC_CS_TYPE)0x0400
1785#define CSW_TEST3 (ASC_CS_TYPE)0x0200
1786#define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
1787#define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
1788#define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
1789#define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
1790#define CSW_HALTED (ASC_CS_TYPE)0x0010
1791#define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
1792#define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
1793#define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
1794#define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
1795#define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
1796#define CIW_INT_ACK (ASC_CS_TYPE)0x0100
1797#define CIW_TEST1 (ASC_CS_TYPE)0x0200
1798#define CIW_TEST2 (ASC_CS_TYPE)0x0400
1799#define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
1800#define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
1801#define CC_CHIP_RESET (uchar)0x80
1802#define CC_SCSI_RESET (uchar)0x40
1803#define CC_HALT (uchar)0x20
1804#define CC_SINGLE_STEP (uchar)0x10
1805#define CC_DMA_ABLE (uchar)0x08
1806#define CC_TEST (uchar)0x04
1807#define CC_BANK_ONE (uchar)0x02
1808#define CC_DIAG (uchar)0x01
1809#define ASC_1000_ID0W 0x04C1
1810#define ASC_1000_ID0W_FIX 0x00C1
1811#define ASC_1000_ID1B 0x25
1812#define ASC_EISA_BIG_IOP_GAP (0x1C30-0x0C50)
1813#define ASC_EISA_SMALL_IOP_GAP (0x0020)
1814#define ASC_EISA_MIN_IOP_ADDR (0x0C30)
1815#define ASC_EISA_MAX_IOP_ADDR (0xFC50)
1816#define ASC_EISA_REV_IOP_MASK (0x0C83)
1817#define ASC_EISA_PID_IOP_MASK (0x0C80)
1818#define ASC_EISA_CFG_IOP_MASK (0x0C86)
1819#define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
1820#define ASC_EISA_ID_740 0x01745004UL
1821#define ASC_EISA_ID_750 0x01755004UL
1822#define INS_HALTINT (ushort)0x6281
1823#define INS_HALT (ushort)0x6280
1824#define INS_SINT (ushort)0x6200
1825#define INS_RFLAG_WTM (ushort)0x7380
1826#define ASC_MC_SAVE_CODE_WSIZE 0x500
1827#define ASC_MC_SAVE_DATA_WSIZE 0x40
1828
1829typedef struct asc_mc_saved {
1830 ushort data[ASC_MC_SAVE_DATA_WSIZE];
1831 ushort code[ASC_MC_SAVE_CODE_WSIZE];
1832} ASC_MC_SAVED;
1833
1834#define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
1835#define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
1836#define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
1837#define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
1838#define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
1839#define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
1840#define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
1841#define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
1842#define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
1843#define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
1844#define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data));
1845#define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id));
1846#define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data);
1847#define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id));
1848#define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
1849#define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
1850#define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
1851#define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
1852#define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
1853#define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
1854#define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
1855#define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
1856#define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
1857#define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
1858#define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
1859#define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
1860#define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
1861#define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
1862#define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
1863#define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
1864#define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
1865#define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
1866#define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
1867#define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
1868#define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
1869#define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
1870#define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
1871#define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
1872#define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
1873#define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
1874#define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
1875#define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
1876#define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
1877#define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
1878#define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
1879#define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
1880#define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
1881#define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
1882#define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
1883#define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
1884#define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
1885#define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
1886#define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
1887#define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
1888#define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
1889#define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
1890#define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
1891#define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
1892#define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
1893#define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
1894#define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
1895#define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
1896#define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
1897#define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
1898#define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
1899#define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
1900#define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
1901#define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
1902
1903STATIC int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg);
1904STATIC int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg);
1905STATIC void AscWaitEEPRead(void);
1906STATIC void AscWaitEEPWrite(void);
1907STATIC ushort AscReadEEPWord(PortAddr, uchar);
1908STATIC ushort AscWriteEEPWord(PortAddr, uchar, ushort);
1909STATIC ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1910STATIC int AscSetEEPConfigOnce(PortAddr, ASCEEP_CONFIG *, ushort);
1911STATIC int AscSetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1912STATIC int AscStartChip(PortAddr);
1913STATIC int AscStopChip(PortAddr);
1914STATIC void AscSetChipIH(PortAddr, ushort);
1915STATIC int AscIsChipHalted(PortAddr);
1916STATIC void AscAckInterrupt(PortAddr);
1917STATIC void AscDisableInterrupt(PortAddr);
1918STATIC void AscEnableInterrupt(PortAddr);
1919STATIC void AscSetBank(PortAddr, uchar);
1920STATIC int AscResetChipAndScsiBus(ASC_DVC_VAR *);
1921#ifdef CONFIG_ISA
1922STATIC ushort AscGetIsaDmaChannel(PortAddr);
1923STATIC ushort AscSetIsaDmaChannel(PortAddr, ushort);
1924STATIC uchar AscSetIsaDmaSpeed(PortAddr, uchar);
1925STATIC uchar AscGetIsaDmaSpeed(PortAddr);
1926#endif /* CONFIG_ISA */
1927STATIC uchar AscReadLramByte(PortAddr, ushort);
1928STATIC ushort AscReadLramWord(PortAddr, ushort);
1929#if CC_VERY_LONG_SG_LIST
1930STATIC ASC_DCNT AscReadLramDWord(PortAddr, ushort);
1931#endif /* CC_VERY_LONG_SG_LIST */
1932STATIC void AscWriteLramWord(PortAddr, ushort, ushort);
1933STATIC void AscWriteLramByte(PortAddr, ushort, uchar);
1934STATIC ASC_DCNT AscMemSumLramWord(PortAddr, ushort, int);
1935STATIC void AscMemWordSetLram(PortAddr, ushort, ushort, int);
1936STATIC void AscMemWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1937STATIC void AscMemDWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1938STATIC void AscMemWordCopyPtrFromLram(PortAddr, ushort, uchar *, int);
1939STATIC ushort AscInitAscDvcVar(ASC_DVC_VAR *);
1940STATIC ushort AscInitFromEEP(ASC_DVC_VAR *);
1941STATIC ushort AscInitFromAscDvcVar(ASC_DVC_VAR *);
1942STATIC ushort AscInitMicroCodeVar(ASC_DVC_VAR *);
1943STATIC int AscTestExternalLram(ASC_DVC_VAR *);
1944STATIC uchar AscMsgOutSDTR(ASC_DVC_VAR *, uchar, uchar);
1945STATIC uchar AscCalSDTRData(ASC_DVC_VAR *, uchar, uchar);
1946STATIC void AscSetChipSDTR(PortAddr, uchar, uchar);
1947STATIC uchar AscGetSynPeriodIndex(ASC_DVC_VAR *, uchar);
1948STATIC uchar AscAllocFreeQueue(PortAddr, uchar);
1949STATIC uchar AscAllocMultipleFreeQueue(PortAddr, uchar, uchar);
1950STATIC int AscHostReqRiscHalt(PortAddr);
1951STATIC int AscStopQueueExe(PortAddr);
1952STATIC int AscSendScsiQueue(ASC_DVC_VAR *,
1953 ASC_SCSI_Q * scsiq,
1954 uchar n_q_required);
1955STATIC int AscPutReadyQueue(ASC_DVC_VAR *,
1956 ASC_SCSI_Q *, uchar);
1957STATIC int AscPutReadySgListQueue(ASC_DVC_VAR *,
1958 ASC_SCSI_Q *, uchar);
1959STATIC int AscSetChipSynRegAtID(PortAddr, uchar, uchar);
1960STATIC int AscSetRunChipSynRegAtID(PortAddr, uchar, uchar);
1961STATIC ushort AscInitLram(ASC_DVC_VAR *);
1962STATIC ushort AscInitQLinkVar(ASC_DVC_VAR *);
1963STATIC int AscSetLibErrorCode(ASC_DVC_VAR *, ushort);
1964STATIC int AscIsrChipHalted(ASC_DVC_VAR *);
1965STATIC uchar _AscCopyLramScsiDoneQ(PortAddr, ushort,
1966 ASC_QDONE_INFO *, ASC_DCNT);
1967STATIC int AscIsrQDone(ASC_DVC_VAR *);
1968STATIC int AscCompareString(uchar *, uchar *, int);
1969#ifdef CONFIG_ISA
1970STATIC ushort AscGetEisaChipCfg(PortAddr);
1971STATIC ASC_DCNT AscGetEisaProductID(PortAddr);
1972STATIC PortAddr AscSearchIOPortAddrEISA(PortAddr);
1973STATIC PortAddr AscSearchIOPortAddr11(PortAddr);
1974STATIC PortAddr AscSearchIOPortAddr(PortAddr, ushort);
1975STATIC void AscSetISAPNPWaitForKey(void);
1976#endif /* CONFIG_ISA */
1977STATIC uchar AscGetChipScsiCtrl(PortAddr);
1978STATIC uchar AscSetChipScsiID(PortAddr, uchar);
1979STATIC uchar AscGetChipVersion(PortAddr, ushort);
1980STATIC ushort AscGetChipBusType(PortAddr);
1981STATIC ASC_DCNT AscLoadMicroCode(PortAddr, ushort, uchar *, ushort);
1982STATIC int AscFindSignature(PortAddr);
1983STATIC void AscToggleIRQAct(PortAddr);
1984STATIC uchar AscGetChipIRQ(PortAddr, ushort);
1985STATIC uchar AscSetChipIRQ(PortAddr, uchar, ushort);
1986STATIC ushort AscGetChipBiosAddress(PortAddr, ushort);
1987STATIC inline ulong DvcEnterCritical(void);
1988STATIC inline void DvcLeaveCritical(ulong);
1989#ifdef CONFIG_PCI
1990STATIC uchar DvcReadPCIConfigByte(ASC_DVC_VAR *, ushort);
1991STATIC void DvcWritePCIConfigByte(ASC_DVC_VAR *,
1992 ushort, uchar);
1993#endif /* CONFIG_PCI */
1994STATIC ushort AscGetChipBiosAddress(PortAddr, ushort);
1995STATIC void DvcSleepMilliSecond(ASC_DCNT);
1996STATIC void DvcDelayNanoSecond(ASC_DVC_VAR *, ASC_DCNT);
1997STATIC void DvcPutScsiQ(PortAddr, ushort, uchar *, int);
1998STATIC void DvcGetQinfo(PortAddr, ushort, uchar *, int);
1999STATIC ushort AscInitGetConfig(ASC_DVC_VAR *);
2000STATIC ushort AscInitSetConfig(ASC_DVC_VAR *);
2001STATIC ushort AscInitAsc1000Driver(ASC_DVC_VAR *);
2002STATIC void AscAsyncFix(ASC_DVC_VAR *, uchar,
2003 ASC_SCSI_INQUIRY *);
2004STATIC int AscTagQueuingSafe(ASC_SCSI_INQUIRY *);
2005STATIC void AscInquiryHandling(ASC_DVC_VAR *,
2006 uchar, ASC_SCSI_INQUIRY *);
2007STATIC int AscExeScsiQueue(ASC_DVC_VAR *, ASC_SCSI_Q *);
2008STATIC int AscISR(ASC_DVC_VAR *);
2009STATIC uint AscGetNumOfFreeQueue(ASC_DVC_VAR *, uchar,
2010 uchar);
2011STATIC int AscSgListToQueue(int);
2012#ifdef CONFIG_ISA
2013STATIC void AscEnableIsaDma(uchar);
2014#endif /* CONFIG_ISA */
2015STATIC ASC_DCNT AscGetMaxDmaCount(ushort);
2016
2017
2018/*
2019 * --- Adv Library Constants and Macros
2020 */
2021
2022#define ADV_LIB_VERSION_MAJOR 5
2023#define ADV_LIB_VERSION_MINOR 14
2024
2025/*
2026 * Define Adv Library required special types.
2027 */
2028
2029/*
2030 * Portable Data Types
2031 *
2032 * Any instance where a 32-bit long or pointer type is assumed
2033 * for precision or HW defined structures, the following define
2034 * types must be used. In Linux the char, short, and int types
2035 * are all consistent at 8, 16, and 32 bits respectively. Pointers
2036 * and long types are 64 bits on Alpha and UltraSPARC.
2037 */
2038#define ADV_PADDR __u32 /* Physical address data type. */
2039#define ADV_VADDR __u32 /* Virtual address data type. */
2040#define ADV_DCNT __u32 /* Unsigned Data count type. */
2041#define ADV_SDCNT __s32 /* Signed Data count type. */
2042
2043/*
2044 * These macros are used to convert a virtual address to a
2045 * 32-bit value. This currently can be used on Linux Alpha
2046 * which uses 64-bit virtual address but a 32-bit bus address.
2047 * This is likely to break in the future, but doing this now
2048 * will give us time to change the HW and FW to handle 64-bit
2049 * addresses.
2050 */
2051#define ADV_VADDR_TO_U32 virt_to_bus
2052#define ADV_U32_TO_VADDR bus_to_virt
2053
2054#define AdvPortAddr ulong /* Virtual memory address size */
2055
2056/*
2057 * Define Adv Library required memory access macros.
2058 */
2059#define ADV_MEM_READB(addr) readb(addr)
2060#define ADV_MEM_READW(addr) readw(addr)
2061#define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
2062#define ADV_MEM_WRITEW(addr, word) writew(word, addr)
2063#define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
2064
2065#define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
2066
2067/*
2068 * For wide boards a CDB length maximum of 16 bytes
2069 * is supported.
2070 */
2071#define ADV_MAX_CDB_LEN 16
2072
2073/*
2074 * Define total number of simultaneous maximum element scatter-gather
2075 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
2076 * maximum number of outstanding commands per wide host adapter. Each
2077 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
2078 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
2079 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
2080 * structures or 255 scatter-gather elements.
2081 *
2082 */
2083#define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
2084
2085/*
2086 * Define Adv Library required maximum number of scatter-gather
2087 * elements per request.
2088 */
2089#define ADV_MAX_SG_LIST 255
2090
2091/* Number of SG blocks needed. */
2092#define ADV_NUM_SG_BLOCK \
2093 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
2094
2095/* Total contiguous memory needed for SG blocks. */
2096#define ADV_SG_TOTAL_MEM_SIZE \
2097 (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
2098
2099#define ADV_PAGE_SIZE PAGE_SIZE
2100
2101#define ADV_NUM_PAGE_CROSSING \
2102 ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
2103
2104/* a_condor.h */
2105#define ADV_PCI_VENDOR_ID 0x10CD
2106#define ADV_PCI_DEVICE_ID_REV_A 0x2300
2107#define ADV_PCI_DEVID_38C0800_REV1 0x2500
2108#define ADV_PCI_DEVID_38C1600_REV1 0x2700
2109
2110#define ADV_EEP_DVC_CFG_BEGIN (0x00)
2111#define ADV_EEP_DVC_CFG_END (0x15)
2112#define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
2113#define ADV_EEP_MAX_WORD_ADDR (0x1E)
2114
2115#define ADV_EEP_DELAY_MS 100
2116
2117#define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
2118#define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
2119/*
2120 * For the ASC3550 Bit 13 is Termination Polarity control bit.
2121 * For later ICs Bit 13 controls whether the CIS (Card Information
2122 * Service Section) is loaded from EEPROM.
2123 */
2124#define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
2125#define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
2126/*
2127 * ASC38C1600 Bit 11
2128 *
2129 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
2130 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
2131 * Function 0 will specify INT B.
2132 *
2133 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
2134 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
2135 * Function 1 will specify INT A.
2136 */
2137#define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
2138
2139typedef struct adveep_3550_config
2140{
2141 /* Word Offset, Description */
2142
2143 ushort cfg_lsw; /* 00 power up initialization */
2144 /* bit 13 set - Term Polarity Control */
2145 /* bit 14 set - BIOS Enable */
2146 /* bit 15 set - Big Endian Mode */
2147 ushort cfg_msw; /* 01 unused */
2148 ushort disc_enable; /* 02 disconnect enable */
2149 ushort wdtr_able; /* 03 Wide DTR able */
2150 ushort sdtr_able; /* 04 Synchronous DTR able */
2151 ushort start_motor; /* 05 send start up motor */
2152 ushort tagqng_able; /* 06 tag queuing able */
2153 ushort bios_scan; /* 07 BIOS device control */
2154 ushort scam_tolerant; /* 08 no scam */
2155
2156 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2157 uchar bios_boot_delay; /* power up wait */
2158
2159 uchar scsi_reset_delay; /* 10 reset delay */
2160 uchar bios_id_lun; /* first boot device scsi id & lun */
2161 /* high nibble is lun */
2162 /* low nibble is scsi id */
2163
2164 uchar termination; /* 11 0 - automatic */
2165 /* 1 - low off / high off */
2166 /* 2 - low off / high on */
2167 /* 3 - low on / high on */
2168 /* There is no low on / high off */
2169
2170 uchar reserved1; /* reserved byte (not used) */
2171
2172 ushort bios_ctrl; /* 12 BIOS control bits */
2173 /* bit 0 BIOS don't act as initiator. */
2174 /* bit 1 BIOS > 1 GB support */
2175 /* bit 2 BIOS > 2 Disk Support */
2176 /* bit 3 BIOS don't support removables */
2177 /* bit 4 BIOS support bootable CD */
2178 /* bit 5 BIOS scan enabled */
2179 /* bit 6 BIOS support multiple LUNs */
2180 /* bit 7 BIOS display of message */
2181 /* bit 8 SCAM disabled */
2182 /* bit 9 Reset SCSI bus during init. */
2183 /* bit 10 */
2184 /* bit 11 No verbose initialization. */
2185 /* bit 12 SCSI parity enabled */
2186 /* bit 13 */
2187 /* bit 14 */
2188 /* bit 15 */
2189 ushort ultra_able; /* 13 ULTRA speed able */
2190 ushort reserved2; /* 14 reserved */
2191 uchar max_host_qng; /* 15 maximum host queuing */
2192 uchar max_dvc_qng; /* maximum per device queuing */
2193 ushort dvc_cntl; /* 16 control bit for driver */
2194 ushort bug_fix; /* 17 control bit for bug fix */
2195 ushort serial_number_word1; /* 18 Board serial number word 1 */
2196 ushort serial_number_word2; /* 19 Board serial number word 2 */
2197 ushort serial_number_word3; /* 20 Board serial number word 3 */
2198 ushort check_sum; /* 21 EEP check sum */
2199 uchar oem_name[16]; /* 22 OEM name */
2200 ushort dvc_err_code; /* 30 last device driver error code */
2201 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2202 ushort adv_err_addr; /* 32 last uc error address */
2203 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2204 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2205 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2206 ushort num_of_err; /* 36 number of error */
2207} ADVEEP_3550_CONFIG;
2208
2209typedef struct adveep_38C0800_config
2210{
2211 /* Word Offset, Description */
2212
2213 ushort cfg_lsw; /* 00 power up initialization */
2214 /* bit 13 set - Load CIS */
2215 /* bit 14 set - BIOS Enable */
2216 /* bit 15 set - Big Endian Mode */
2217 ushort cfg_msw; /* 01 unused */
2218 ushort disc_enable; /* 02 disconnect enable */
2219 ushort wdtr_able; /* 03 Wide DTR able */
2220 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
2221 ushort start_motor; /* 05 send start up motor */
2222 ushort tagqng_able; /* 06 tag queuing able */
2223 ushort bios_scan; /* 07 BIOS device control */
2224 ushort scam_tolerant; /* 08 no scam */
2225
2226 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2227 uchar bios_boot_delay; /* power up wait */
2228
2229 uchar scsi_reset_delay; /* 10 reset delay */
2230 uchar bios_id_lun; /* first boot device scsi id & lun */
2231 /* high nibble is lun */
2232 /* low nibble is scsi id */
2233
2234 uchar termination_se; /* 11 0 - automatic */
2235 /* 1 - low off / high off */
2236 /* 2 - low off / high on */
2237 /* 3 - low on / high on */
2238 /* There is no low on / high off */
2239
2240 uchar termination_lvd; /* 11 0 - automatic */
2241 /* 1 - low off / high off */
2242 /* 2 - low off / high on */
2243 /* 3 - low on / high on */
2244 /* There is no low on / high off */
2245
2246 ushort bios_ctrl; /* 12 BIOS control bits */
2247 /* bit 0 BIOS don't act as initiator. */
2248 /* bit 1 BIOS > 1 GB support */
2249 /* bit 2 BIOS > 2 Disk Support */
2250 /* bit 3 BIOS don't support removables */
2251 /* bit 4 BIOS support bootable CD */
2252 /* bit 5 BIOS scan enabled */
2253 /* bit 6 BIOS support multiple LUNs */
2254 /* bit 7 BIOS display of message */
2255 /* bit 8 SCAM disabled */
2256 /* bit 9 Reset SCSI bus during init. */
2257 /* bit 10 */
2258 /* bit 11 No verbose initialization. */
2259 /* bit 12 SCSI parity enabled */
2260 /* bit 13 */
2261 /* bit 14 */
2262 /* bit 15 */
2263 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
2264 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
2265 uchar max_host_qng; /* 15 maximum host queueing */
2266 uchar max_dvc_qng; /* maximum per device queuing */
2267 ushort dvc_cntl; /* 16 control bit for driver */
2268 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
2269 ushort serial_number_word1; /* 18 Board serial number word 1 */
2270 ushort serial_number_word2; /* 19 Board serial number word 2 */
2271 ushort serial_number_word3; /* 20 Board serial number word 3 */
2272 ushort check_sum; /* 21 EEP check sum */
2273 uchar oem_name[16]; /* 22 OEM name */
2274 ushort dvc_err_code; /* 30 last device driver error code */
2275 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2276 ushort adv_err_addr; /* 32 last uc error address */
2277 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2278 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2279 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2280 ushort reserved36; /* 36 reserved */
2281 ushort reserved37; /* 37 reserved */
2282 ushort reserved38; /* 38 reserved */
2283 ushort reserved39; /* 39 reserved */
2284 ushort reserved40; /* 40 reserved */
2285 ushort reserved41; /* 41 reserved */
2286 ushort reserved42; /* 42 reserved */
2287 ushort reserved43; /* 43 reserved */
2288 ushort reserved44; /* 44 reserved */
2289 ushort reserved45; /* 45 reserved */
2290 ushort reserved46; /* 46 reserved */
2291 ushort reserved47; /* 47 reserved */
2292 ushort reserved48; /* 48 reserved */
2293 ushort reserved49; /* 49 reserved */
2294 ushort reserved50; /* 50 reserved */
2295 ushort reserved51; /* 51 reserved */
2296 ushort reserved52; /* 52 reserved */
2297 ushort reserved53; /* 53 reserved */
2298 ushort reserved54; /* 54 reserved */
2299 ushort reserved55; /* 55 reserved */
2300 ushort cisptr_lsw; /* 56 CIS PTR LSW */
2301 ushort cisprt_msw; /* 57 CIS PTR MSW */
2302 ushort subsysvid; /* 58 SubSystem Vendor ID */
2303 ushort subsysid; /* 59 SubSystem ID */
2304 ushort reserved60; /* 60 reserved */
2305 ushort reserved61; /* 61 reserved */
2306 ushort reserved62; /* 62 reserved */
2307 ushort reserved63; /* 63 reserved */
2308} ADVEEP_38C0800_CONFIG;
2309
2310typedef struct adveep_38C1600_config
2311{
2312 /* Word Offset, Description */
2313
2314 ushort cfg_lsw; /* 00 power up initialization */
2315 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
2316 /* clear - Func. 0 INTA, Func. 1 INTB */
2317 /* bit 13 set - Load CIS */
2318 /* bit 14 set - BIOS Enable */
2319 /* bit 15 set - Big Endian Mode */
2320 ushort cfg_msw; /* 01 unused */
2321 ushort disc_enable; /* 02 disconnect enable */
2322 ushort wdtr_able; /* 03 Wide DTR able */
2323 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
2324 ushort start_motor; /* 05 send start up motor */
2325 ushort tagqng_able; /* 06 tag queuing able */
2326 ushort bios_scan; /* 07 BIOS device control */
2327 ushort scam_tolerant; /* 08 no scam */
2328
2329 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2330 uchar bios_boot_delay; /* power up wait */
2331
2332 uchar scsi_reset_delay; /* 10 reset delay */
2333 uchar bios_id_lun; /* first boot device scsi id & lun */
2334 /* high nibble is lun */
2335 /* low nibble is scsi id */
2336
2337 uchar termination_se; /* 11 0 - automatic */
2338 /* 1 - low off / high off */
2339 /* 2 - low off / high on */
2340 /* 3 - low on / high on */
2341 /* There is no low on / high off */
2342
2343 uchar termination_lvd; /* 11 0 - automatic */
2344 /* 1 - low off / high off */
2345 /* 2 - low off / high on */
2346 /* 3 - low on / high on */
2347 /* There is no low on / high off */
2348
2349 ushort bios_ctrl; /* 12 BIOS control bits */
2350 /* bit 0 BIOS don't act as initiator. */
2351 /* bit 1 BIOS > 1 GB support */
2352 /* bit 2 BIOS > 2 Disk Support */
2353 /* bit 3 BIOS don't support removables */
2354 /* bit 4 BIOS support bootable CD */
2355 /* bit 5 BIOS scan enabled */
2356 /* bit 6 BIOS support multiple LUNs */
2357 /* bit 7 BIOS display of message */
2358 /* bit 8 SCAM disabled */
2359 /* bit 9 Reset SCSI bus during init. */
2360 /* bit 10 Basic Integrity Checking disabled */
2361 /* bit 11 No verbose initialization. */
2362 /* bit 12 SCSI parity enabled */
2363 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
2364 /* bit 14 */
2365 /* bit 15 */
2366 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
2367 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
2368 uchar max_host_qng; /* 15 maximum host queueing */
2369 uchar max_dvc_qng; /* maximum per device queuing */
2370 ushort dvc_cntl; /* 16 control bit for driver */
2371 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
2372 ushort serial_number_word1; /* 18 Board serial number word 1 */
2373 ushort serial_number_word2; /* 19 Board serial number word 2 */
2374 ushort serial_number_word3; /* 20 Board serial number word 3 */
2375 ushort check_sum; /* 21 EEP check sum */
2376 uchar oem_name[16]; /* 22 OEM name */
2377 ushort dvc_err_code; /* 30 last device driver error code */
2378 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2379 ushort adv_err_addr; /* 32 last uc error address */
2380 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2381 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2382 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2383 ushort reserved36; /* 36 reserved */
2384 ushort reserved37; /* 37 reserved */
2385 ushort reserved38; /* 38 reserved */
2386 ushort reserved39; /* 39 reserved */
2387 ushort reserved40; /* 40 reserved */
2388 ushort reserved41; /* 41 reserved */
2389 ushort reserved42; /* 42 reserved */
2390 ushort reserved43; /* 43 reserved */
2391 ushort reserved44; /* 44 reserved */
2392 ushort reserved45; /* 45 reserved */
2393 ushort reserved46; /* 46 reserved */
2394 ushort reserved47; /* 47 reserved */
2395 ushort reserved48; /* 48 reserved */
2396 ushort reserved49; /* 49 reserved */
2397 ushort reserved50; /* 50 reserved */
2398 ushort reserved51; /* 51 reserved */
2399 ushort reserved52; /* 52 reserved */
2400 ushort reserved53; /* 53 reserved */
2401 ushort reserved54; /* 54 reserved */
2402 ushort reserved55; /* 55 reserved */
2403 ushort cisptr_lsw; /* 56 CIS PTR LSW */
2404 ushort cisprt_msw; /* 57 CIS PTR MSW */
2405 ushort subsysvid; /* 58 SubSystem Vendor ID */
2406 ushort subsysid; /* 59 SubSystem ID */
2407 ushort reserved60; /* 60 reserved */
2408 ushort reserved61; /* 61 reserved */
2409 ushort reserved62; /* 62 reserved */
2410 ushort reserved63; /* 63 reserved */
2411} ADVEEP_38C1600_CONFIG;
2412
2413/*
2414 * EEPROM Commands
2415 */
2416#define ASC_EEP_CMD_DONE 0x0200
2417#define ASC_EEP_CMD_DONE_ERR 0x0001
2418
2419/* cfg_word */
2420#define EEP_CFG_WORD_BIG_ENDIAN 0x8000
2421
2422/* bios_ctrl */
2423#define BIOS_CTRL_BIOS 0x0001
2424#define BIOS_CTRL_EXTENDED_XLAT 0x0002
2425#define BIOS_CTRL_GT_2_DISK 0x0004
2426#define BIOS_CTRL_BIOS_REMOVABLE 0x0008
2427#define BIOS_CTRL_BOOTABLE_CD 0x0010
2428#define BIOS_CTRL_MULTIPLE_LUN 0x0040
2429#define BIOS_CTRL_DISPLAY_MSG 0x0080
2430#define BIOS_CTRL_NO_SCAM 0x0100
2431#define BIOS_CTRL_RESET_SCSI_BUS 0x0200
2432#define BIOS_CTRL_INIT_VERBOSE 0x0800
2433#define BIOS_CTRL_SCSI_PARITY 0x1000
2434#define BIOS_CTRL_AIPP_DIS 0x2000
2435
2436#define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
2437#define ADV_3550_IOLEN 0x40 /* I/O Port Range in bytes */
2438
2439#define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
2440#define ADV_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */
2441
2442/*
2443 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
2444 * a special 16K Adv Library and Microcode version. After the issue is
2445 * resolved, should restore 32K support.
2446 *
2447 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
2448 */
2449#define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
2450#define ADV_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */
2451#define ADV_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */
2452
2453/*
2454 * Byte I/O register address from base of 'iop_base'.
2455 */
2456#define IOPB_INTR_STATUS_REG 0x00
2457#define IOPB_CHIP_ID_1 0x01
2458#define IOPB_INTR_ENABLES 0x02
2459#define IOPB_CHIP_TYPE_REV 0x03
2460#define IOPB_RES_ADDR_4 0x04
2461#define IOPB_RES_ADDR_5 0x05
2462#define IOPB_RAM_DATA 0x06
2463#define IOPB_RES_ADDR_7 0x07
2464#define IOPB_FLAG_REG 0x08
2465#define IOPB_RES_ADDR_9 0x09
2466#define IOPB_RISC_CSR 0x0A
2467#define IOPB_RES_ADDR_B 0x0B
2468#define IOPB_RES_ADDR_C 0x0C
2469#define IOPB_RES_ADDR_D 0x0D
2470#define IOPB_SOFT_OVER_WR 0x0E
2471#define IOPB_RES_ADDR_F 0x0F
2472#define IOPB_MEM_CFG 0x10
2473#define IOPB_RES_ADDR_11 0x11
2474#define IOPB_GPIO_DATA 0x12
2475#define IOPB_RES_ADDR_13 0x13
2476#define IOPB_FLASH_PAGE 0x14
2477#define IOPB_RES_ADDR_15 0x15
2478#define IOPB_GPIO_CNTL 0x16
2479#define IOPB_RES_ADDR_17 0x17
2480#define IOPB_FLASH_DATA 0x18
2481#define IOPB_RES_ADDR_19 0x19
2482#define IOPB_RES_ADDR_1A 0x1A
2483#define IOPB_RES_ADDR_1B 0x1B
2484#define IOPB_RES_ADDR_1C 0x1C
2485#define IOPB_RES_ADDR_1D 0x1D
2486#define IOPB_RES_ADDR_1E 0x1E
2487#define IOPB_RES_ADDR_1F 0x1F
2488#define IOPB_DMA_CFG0 0x20
2489#define IOPB_DMA_CFG1 0x21
2490#define IOPB_TICKLE 0x22
2491#define IOPB_DMA_REG_WR 0x23
2492#define IOPB_SDMA_STATUS 0x24
2493#define IOPB_SCSI_BYTE_CNT 0x25
2494#define IOPB_HOST_BYTE_CNT 0x26
2495#define IOPB_BYTE_LEFT_TO_XFER 0x27
2496#define IOPB_BYTE_TO_XFER_0 0x28
2497#define IOPB_BYTE_TO_XFER_1 0x29
2498#define IOPB_BYTE_TO_XFER_2 0x2A
2499#define IOPB_BYTE_TO_XFER_3 0x2B
2500#define IOPB_ACC_GRP 0x2C
2501#define IOPB_RES_ADDR_2D 0x2D
2502#define IOPB_DEV_ID 0x2E
2503#define IOPB_RES_ADDR_2F 0x2F
2504#define IOPB_SCSI_DATA 0x30
2505#define IOPB_RES_ADDR_31 0x31
2506#define IOPB_RES_ADDR_32 0x32
2507#define IOPB_SCSI_DATA_HSHK 0x33
2508#define IOPB_SCSI_CTRL 0x34
2509#define IOPB_RES_ADDR_35 0x35
2510#define IOPB_RES_ADDR_36 0x36
2511#define IOPB_RES_ADDR_37 0x37
2512#define IOPB_RAM_BIST 0x38
2513#define IOPB_PLL_TEST 0x39
2514#define IOPB_PCI_INT_CFG 0x3A
2515#define IOPB_RES_ADDR_3B 0x3B
2516#define IOPB_RFIFO_CNT 0x3C
2517#define IOPB_RES_ADDR_3D 0x3D
2518#define IOPB_RES_ADDR_3E 0x3E
2519#define IOPB_RES_ADDR_3F 0x3F
2520
2521/*
2522 * Word I/O register address from base of 'iop_base'.
2523 */
2524#define IOPW_CHIP_ID_0 0x00 /* CID0 */
2525#define IOPW_CTRL_REG 0x02 /* CC */
2526#define IOPW_RAM_ADDR 0x04 /* LA */
2527#define IOPW_RAM_DATA 0x06 /* LD */
2528#define IOPW_RES_ADDR_08 0x08
2529#define IOPW_RISC_CSR 0x0A /* CSR */
2530#define IOPW_SCSI_CFG0 0x0C /* CFG0 */
2531#define IOPW_SCSI_CFG1 0x0E /* CFG1 */
2532#define IOPW_RES_ADDR_10 0x10
2533#define IOPW_SEL_MASK 0x12 /* SM */
2534#define IOPW_RES_ADDR_14 0x14
2535#define IOPW_FLASH_ADDR 0x16 /* FA */
2536#define IOPW_RES_ADDR_18 0x18
2537#define IOPW_EE_CMD 0x1A /* EC */
2538#define IOPW_EE_DATA 0x1C /* ED */
2539#define IOPW_SFIFO_CNT 0x1E /* SFC */
2540#define IOPW_RES_ADDR_20 0x20
2541#define IOPW_Q_BASE 0x22 /* QB */
2542#define IOPW_QP 0x24 /* QP */
2543#define IOPW_IX 0x26 /* IX */
2544#define IOPW_SP 0x28 /* SP */
2545#define IOPW_PC 0x2A /* PC */
2546#define IOPW_RES_ADDR_2C 0x2C
2547#define IOPW_RES_ADDR_2E 0x2E
2548#define IOPW_SCSI_DATA 0x30 /* SD */
2549#define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
2550#define IOPW_SCSI_CTRL 0x34 /* SC */
2551#define IOPW_HSHK_CFG 0x36 /* HCFG */
2552#define IOPW_SXFR_STATUS 0x36 /* SXS */
2553#define IOPW_SXFR_CNTL 0x38 /* SXL */
2554#define IOPW_SXFR_CNTH 0x3A /* SXH */
2555#define IOPW_RES_ADDR_3C 0x3C
2556#define IOPW_RFIFO_DATA 0x3E /* RFD */
2557
2558/*
2559 * Doubleword I/O register address from base of 'iop_base'.
2560 */
2561#define IOPDW_RES_ADDR_0 0x00
2562#define IOPDW_RAM_DATA 0x04
2563#define IOPDW_RES_ADDR_8 0x08
2564#define IOPDW_RES_ADDR_C 0x0C
2565#define IOPDW_RES_ADDR_10 0x10
2566#define IOPDW_COMMA 0x14
2567#define IOPDW_COMMB 0x18
2568#define IOPDW_RES_ADDR_1C 0x1C
2569#define IOPDW_SDMA_ADDR0 0x20
2570#define IOPDW_SDMA_ADDR1 0x24
2571#define IOPDW_SDMA_COUNT 0x28
2572#define IOPDW_SDMA_ERROR 0x2C
2573#define IOPDW_RDMA_ADDR0 0x30
2574#define IOPDW_RDMA_ADDR1 0x34
2575#define IOPDW_RDMA_COUNT 0x38
2576#define IOPDW_RDMA_ERROR 0x3C
2577
2578#define ADV_CHIP_ID_BYTE 0x25
2579#define ADV_CHIP_ID_WORD 0x04C1
2580
2581#define ADV_SC_SCSI_BUS_RESET 0x2000
2582
2583#define ADV_INTR_ENABLE_HOST_INTR 0x01
2584#define ADV_INTR_ENABLE_SEL_INTR 0x02
2585#define ADV_INTR_ENABLE_DPR_INTR 0x04
2586#define ADV_INTR_ENABLE_RTA_INTR 0x08
2587#define ADV_INTR_ENABLE_RMA_INTR 0x10
2588#define ADV_INTR_ENABLE_RST_INTR 0x20
2589#define ADV_INTR_ENABLE_DPE_INTR 0x40
2590#define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
2591
2592#define ADV_INTR_STATUS_INTRA 0x01
2593#define ADV_INTR_STATUS_INTRB 0x02
2594#define ADV_INTR_STATUS_INTRC 0x04
2595
2596#define ADV_RISC_CSR_STOP (0x0000)
2597#define ADV_RISC_TEST_COND (0x2000)
2598#define ADV_RISC_CSR_RUN (0x4000)
2599#define ADV_RISC_CSR_SINGLE_STEP (0x8000)
2600
2601#define ADV_CTRL_REG_HOST_INTR 0x0100
2602#define ADV_CTRL_REG_SEL_INTR 0x0200
2603#define ADV_CTRL_REG_DPR_INTR 0x0400
2604#define ADV_CTRL_REG_RTA_INTR 0x0800
2605#define ADV_CTRL_REG_RMA_INTR 0x1000
2606#define ADV_CTRL_REG_RES_BIT14 0x2000
2607#define ADV_CTRL_REG_DPE_INTR 0x4000
2608#define ADV_CTRL_REG_POWER_DONE 0x8000
2609#define ADV_CTRL_REG_ANY_INTR 0xFF00
2610
2611#define ADV_CTRL_REG_CMD_RESET 0x00C6
2612#define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
2613#define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
2614#define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
2615#define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
2616
2617#define ADV_TICKLE_NOP 0x00
2618#define ADV_TICKLE_A 0x01
2619#define ADV_TICKLE_B 0x02
2620#define ADV_TICKLE_C 0x03
2621
2622#define ADV_SCSI_CTRL_RSTOUT 0x2000
2623
2624#define AdvIsIntPending(port) \
2625 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
2626
2627/*
2628 * SCSI_CFG0 Register bit definitions
2629 */
2630#define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
2631#define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
2632#define EVEN_PARITY 0x1000 /* Select Even Parity */
2633#define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
2634#define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
2635#define PRIM_MODE 0x0100 /* Primitive SCSI mode */
2636#define SCAM_EN 0x0080 /* Enable SCAM selection */
2637#define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
2638#define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
2639#define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
2640#define OUR_ID 0x000F /* SCSI ID */
2641
2642/*
2643 * SCSI_CFG1 Register bit definitions
2644 */
2645#define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
2646#define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
2647#define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
2648#define FILTER_SEL 0x0C00 /* Filter Period Selection */
2649#define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
2650#define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
2651#define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
2652#define ACTIVE_DBL 0x0200 /* Disable Active Negation */
2653#define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
2654#define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
2655#define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
2656#define TERM_CTL 0x0030 /* External SCSI Termination Bits */
2657#define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
2658#define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
2659#define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
2660
2661/*
2662 * Addendum for ASC-38C0800 Chip
2663 *
2664 * The ASC-38C1600 Chip uses the same definitions except that the
2665 * bus mode override bits [12:10] have been moved to byte register
2666 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
2667 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
2668 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
2669 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
2670 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
2671 */
2672#define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
2673#define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
2674#define HVD 0x1000 /* HVD Device Detect */
2675#define LVD 0x0800 /* LVD Device Detect */
2676#define SE 0x0400 /* SE Device Detect */
2677#define TERM_LVD 0x00C0 /* LVD Termination Bits */
2678#define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
2679#define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
2680#define TERM_SE 0x0030 /* SE Termination Bits */
2681#define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
2682#define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
2683#define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
2684#define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
2685#define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
2686#define C_DET_SE 0x0003 /* SE Cable Detect Bits */
2687#define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
2688#define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
2689
2690
2691#define CABLE_ILLEGAL_A 0x7
2692 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
2693
2694#define CABLE_ILLEGAL_B 0xB
2695 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
2696
2697/*
2698 * MEM_CFG Register bit definitions
2699 */
2700#define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
2701#define FAST_EE_CLK 0x20 /* Diagnostic Bit */
2702#define RAM_SZ 0x1C /* Specify size of RAM to RISC */
2703#define RAM_SZ_2KB 0x00 /* 2 KB */
2704#define RAM_SZ_4KB 0x04 /* 4 KB */
2705#define RAM_SZ_8KB 0x08 /* 8 KB */
2706#define RAM_SZ_16KB 0x0C /* 16 KB */
2707#define RAM_SZ_32KB 0x10 /* 32 KB */
2708#define RAM_SZ_64KB 0x14 /* 64 KB */
2709
2710/*
2711 * DMA_CFG0 Register bit definitions
2712 *
2713 * This register is only accessible to the host.
2714 */
2715#define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
2716#define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
2717#define FIFO_THRESH_16B 0x00 /* 16 bytes */
2718#define FIFO_THRESH_32B 0x20 /* 32 bytes */
2719#define FIFO_THRESH_48B 0x30 /* 48 bytes */
2720#define FIFO_THRESH_64B 0x40 /* 64 bytes */
2721#define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
2722#define FIFO_THRESH_96B 0x60 /* 96 bytes */
2723#define FIFO_THRESH_112B 0x70 /* 112 bytes */
2724#define START_CTL 0x0C /* DMA start conditions */
2725#define START_CTL_TH 0x00 /* Wait threshold level (default) */
2726#define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
2727#define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
2728#define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
2729#define READ_CMD 0x03 /* Memory Read Method */
2730#define READ_CMD_MR 0x00 /* Memory Read */
2731#define READ_CMD_MRL 0x02 /* Memory Read Long */
2732#define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
2733
2734/*
2735 * ASC-38C0800 RAM BIST Register bit definitions
2736 */
2737#define RAM_TEST_MODE 0x80
2738#define PRE_TEST_MODE 0x40
2739#define NORMAL_MODE 0x00
2740#define RAM_TEST_DONE 0x10
2741#define RAM_TEST_STATUS 0x0F
2742#define RAM_TEST_HOST_ERROR 0x08
2743#define RAM_TEST_INTRAM_ERROR 0x04
2744#define RAM_TEST_RISC_ERROR 0x02
2745#define RAM_TEST_SCSI_ERROR 0x01
2746#define RAM_TEST_SUCCESS 0x00
2747#define PRE_TEST_VALUE 0x05
2748#define NORMAL_VALUE 0x00
2749
2750/*
2751 * ASC38C1600 Definitions
2752 *
2753 * IOPB_PCI_INT_CFG Bit Field Definitions
2754 */
2755
2756#define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
2757
2758/*
2759 * Bit 1 can be set to change the interrupt for the Function to operate in
2760 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
2761 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
2762 * mode, otherwise the operating mode is undefined.
2763 */
2764#define TOTEMPOLE 0x02
2765
2766/*
2767 * Bit 0 can be used to change the Int Pin for the Function. The value is
2768 * 0 by default for both Functions with Function 0 using INT A and Function
2769 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
2770 * INT A is used.
2771 *
2772 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
2773 * value specified in the PCI Configuration Space.
2774 */
2775#define INTAB 0x01
2776
2777/* a_advlib.h */
2778
2779/*
2780 * Adv Library Status Definitions
2781 */
2782#define ADV_TRUE 1
2783#define ADV_FALSE 0
2784#define ADV_NOERROR 1
2785#define ADV_SUCCESS 1
2786#define ADV_BUSY 0
2787#define ADV_ERROR (-1)
2788
2789
2790/*
2791 * ADV_DVC_VAR 'warn_code' values
2792 */
2793#define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
2794#define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
2795#define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
2796#define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */
2797#define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
2798
2799#define ADV_MAX_TID 15 /* max. target identifier */
2800#define ADV_MAX_LUN 7 /* max. logical unit number */
2801
2802/*
2803 * Error code values are set in ADV_DVC_VAR 'err_code'.
2804 */
2805#define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */
2806#define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
2807#define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */
2808#define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
2809#define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */
2810#define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
2811#define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */
2812#define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
2813#define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */
2814#define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */
2815#define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */
2816#define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */
2817#define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */
2818#define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */
2819
2820/*
2821 * Fixed locations of microcode operating variables.
2822 */
2823#define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
2824#define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
2825#define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
2826#define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
2827#define ASC_MC_VERSION_NUM 0x003A /* microcode number */
2828#define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
2829#define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
2830#define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
2831#define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
2832#define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
2833#define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
2834#define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
2835#define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
2836#define ASC_MC_CHIP_TYPE 0x009A
2837#define ASC_MC_INTRB_CODE 0x009B
2838#define ASC_MC_WDTR_ABLE 0x009C
2839#define ASC_MC_SDTR_ABLE 0x009E
2840#define ASC_MC_TAGQNG_ABLE 0x00A0
2841#define ASC_MC_DISC_ENABLE 0x00A2
2842#define ASC_MC_IDLE_CMD_STATUS 0x00A4
2843#define ASC_MC_IDLE_CMD 0x00A6
2844#define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
2845#define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
2846#define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
2847#define ASC_MC_DEFAULT_MEM_CFG 0x00B0
2848#define ASC_MC_DEFAULT_SEL_MASK 0x00B2
2849#define ASC_MC_SDTR_DONE 0x00B6
2850#define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
2851#define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
2852#define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
2853#define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
2854#define ASC_MC_WDTR_DONE 0x0124
2855#define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
2856#define ASC_MC_ICQ 0x0160
2857#define ASC_MC_IRQ 0x0164
2858#define ASC_MC_PPR_ABLE 0x017A
2859
2860/*
2861 * BIOS LRAM variable absolute offsets.
2862 */
2863#define BIOS_CODESEG 0x54
2864#define BIOS_CODELEN 0x56
2865#define BIOS_SIGNATURE 0x58
2866#define BIOS_VERSION 0x5A
2867
2868/*
2869 * Microcode Control Flags
2870 *
2871 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
2872 * and handled by the microcode.
2873 */
2874#define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
2875#define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
2876
2877/*
2878 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
2879 */
2880#define HSHK_CFG_WIDE_XFR 0x8000
2881#define HSHK_CFG_RATE 0x0F00
2882#define HSHK_CFG_OFFSET 0x001F
2883
2884#define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
2885#define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
2886#define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
2887#define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
2888
2889#define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
2890#define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
2891#define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
2892#define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
2893#define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
2894
2895#define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
2896#define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
2897#define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
2898#define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
2899#define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
2900/*
2901 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
2902 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
2903 */
2904#define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
2905#define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
2906
2907/*
2908 * All fields here are accessed by the board microcode and need to be
2909 * little-endian.
2910 */
2911typedef struct adv_carr_t
2912{
2913 ADV_VADDR carr_va; /* Carrier Virtual Address */
2914 ADV_PADDR carr_pa; /* Carrier Physical Address */
2915 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
2916 /*
2917 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
2918 *
2919 * next_vpa [3:1] Reserved Bits
2920 * next_vpa [0] Done Flag set in Response Queue.
2921 */
2922 ADV_VADDR next_vpa;
2923} ADV_CARR_T;
2924
2925/*
2926 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
2927 */
2928#define ASC_NEXT_VPA_MASK 0xFFFFFFF0
2929
2930#define ASC_RQ_DONE 0x00000001
2931#define ASC_RQ_GOOD 0x00000002
2932#define ASC_CQ_STOPPER 0x00000000
2933
2934#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
2935
2936#define ADV_CARRIER_NUM_PAGE_CROSSING \
2937 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
2938 (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
2939
2940#define ADV_CARRIER_BUFSIZE \
2941 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
2942
2943/*
2944 * ASC_SCSI_REQ_Q 'a_flag' definitions
2945 *
2946 * The Adv Library should limit use to the lower nibble (4 bits) of
2947 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
2948 */
2949#define ADV_POLL_REQUEST 0x01 /* poll for request completion */
2950#define ADV_SCSIQ_DONE 0x02 /* request done */
2951#define ADV_DONT_RETRY 0x08 /* don't do retry */
2952
2953#define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
2954#define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
2955#define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
2956
2957/*
2958 * Adapter temporary configuration structure
2959 *
2960 * This structure can be discarded after initialization. Don't add
2961 * fields here needed after initialization.
2962 *
2963 * Field naming convention:
2964 *
2965 * *_enable indicates the field enables or disables a feature. The
2966 * value of the field is never reset.
2967 */
2968typedef struct adv_dvc_cfg {
2969 ushort disc_enable; /* enable disconnection */
2970 uchar chip_version; /* chip version */
2971 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
2972 ushort lib_version; /* Adv Library version number */
2973 ushort control_flag; /* Microcode Control Flag */
2974 ushort mcode_date; /* Microcode date */
2975 ushort mcode_version; /* Microcode version */
2976 ushort pci_slot_info; /* high byte device/function number */
2977 /* bits 7-3 device num., bits 2-0 function num. */
2978 /* low byte bus num. */
2979 ushort serial1; /* EEPROM serial number word 1 */
2980 ushort serial2; /* EEPROM serial number word 2 */
2981 ushort serial3; /* EEPROM serial number word 3 */
2982 struct device *dev; /* pointer to the pci dev structure for this board */
2983} ADV_DVC_CFG;
2984
2985struct adv_dvc_var;
2986struct adv_scsi_req_q;
2987
2988typedef void (* ADV_ISR_CALLBACK)
2989 (struct adv_dvc_var *, struct adv_scsi_req_q *);
2990
2991typedef void (* ADV_ASYNC_CALLBACK)
2992 (struct adv_dvc_var *, uchar);
2993
2994/*
2995 * Adapter operation variable structure.
2996 *
2997 * One structure is required per host adapter.
2998 *
2999 * Field naming convention:
3000 *
3001 * *_able indicates both whether a feature should be enabled or disabled
3002 * and whether a device isi capable of the feature. At initialization
3003 * this field may be set, but later if a device is found to be incapable
3004 * of the feature, the field is cleared.
3005 */
3006typedef struct adv_dvc_var {
3007 AdvPortAddr iop_base; /* I/O port address */
3008 ushort err_code; /* fatal error code */
3009 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
3010 ADV_ISR_CALLBACK isr_callback;
3011 ADV_ASYNC_CALLBACK async_callback;
3012 ushort wdtr_able; /* try WDTR for a device */
3013 ushort sdtr_able; /* try SDTR for a device */
3014 ushort ultra_able; /* try SDTR Ultra speed for a device */
3015 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
3016 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
3017 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
3018 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
3019 ushort tagqng_able; /* try tagged queuing with a device */
3020 ushort ppr_able; /* PPR message capable per TID bitmask. */
3021 uchar max_dvc_qng; /* maximum number of tagged commands per device */
3022 ushort start_motor; /* start motor command allowed */
3023 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
3024 uchar chip_no; /* should be assigned by caller */
3025 uchar max_host_qng; /* maximum number of Q'ed command allowed */
3026 uchar irq_no; /* IRQ number */
3027 ushort no_scam; /* scam_tolerant of EEPROM */
3028 struct asc_board *drv_ptr; /* driver pointer to private structure */
3029 uchar chip_scsi_id; /* chip SCSI target ID */
3030 uchar chip_type;
3031 uchar bist_err_code;
3032 ADV_CARR_T *carrier_buf;
3033 ADV_CARR_T *carr_freelist; /* Carrier free list. */
3034 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
3035 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
3036 ushort carr_pending_cnt; /* Count of pending carriers. */
3037 /*
3038 * Note: The following fields will not be used after initialization. The
3039 * driver may discard the buffer after initialization is done.
3040 */
3041 ADV_DVC_CFG *cfg; /* temporary configuration structure */
3042} ADV_DVC_VAR;
3043
3044#define NO_OF_SG_PER_BLOCK 15
3045
3046typedef struct asc_sg_block {
3047 uchar reserved1;
3048 uchar reserved2;
3049 uchar reserved3;
3050 uchar sg_cnt; /* Valid entries in block. */
3051 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
3052 struct {
3053 ADV_PADDR sg_addr; /* SG element address. */
3054 ADV_DCNT sg_count; /* SG element count. */
3055 } sg_list[NO_OF_SG_PER_BLOCK];
3056} ADV_SG_BLOCK;
3057
3058/*
3059 * ADV_SCSI_REQ_Q - microcode request structure
3060 *
3061 * All fields in this structure up to byte 60 are used by the microcode.
3062 * The microcode makes assumptions about the size and ordering of fields
3063 * in this structure. Do not change the structure definition here without
3064 * coordinating the change with the microcode.
3065 *
3066 * All fields accessed by microcode must be maintained in little_endian
3067 * order.
3068 */
3069typedef struct adv_scsi_req_q {
3070 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
3071 uchar target_cmd;
3072 uchar target_id; /* Device target identifier. */
3073 uchar target_lun; /* Device target logical unit number. */
3074 ADV_PADDR data_addr; /* Data buffer physical address. */
3075 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
3076 ADV_PADDR sense_addr;
3077 ADV_PADDR carr_pa;
3078 uchar mflag;
3079 uchar sense_len;
3080 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
3081 uchar scsi_cntl;
3082 uchar done_status; /* Completion status. */
3083 uchar scsi_status; /* SCSI status byte. */
3084 uchar host_status; /* Ucode host status. */
3085 uchar sg_working_ix;
3086 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
3087 ADV_PADDR sg_real_addr; /* SG list physical address. */
3088 ADV_PADDR scsiq_rptr;
3089 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
3090 ADV_VADDR scsiq_ptr;
3091 ADV_VADDR carr_va;
3092 /*
3093 * End of microcode structure - 60 bytes. The rest of the structure
3094 * is used by the Adv Library and ignored by the microcode.
3095 */
3096 ADV_VADDR srb_ptr;
3097 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
3098 char *vdata_addr; /* Data buffer virtual address. */
3099 uchar a_flag;
3100 uchar pad[2]; /* Pad out to a word boundary. */
3101} ADV_SCSI_REQ_Q;
3102
3103/*
3104 * Microcode idle loop commands
3105 */
3106#define IDLE_CMD_COMPLETED 0
3107#define IDLE_CMD_STOP_CHIP 0x0001
3108#define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
3109#define IDLE_CMD_SEND_INT 0x0004
3110#define IDLE_CMD_ABORT 0x0008
3111#define IDLE_CMD_DEVICE_RESET 0x0010
3112#define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
3113#define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
3114#define IDLE_CMD_SCSIREQ 0x0080
3115
3116#define IDLE_CMD_STATUS_SUCCESS 0x0001
3117#define IDLE_CMD_STATUS_FAILURE 0x0002
3118
3119/*
3120 * AdvSendIdleCmd() flag definitions.
3121 */
3122#define ADV_NOWAIT 0x01
3123
3124/*
3125 * Wait loop time out values.
3126 */
3127#define SCSI_WAIT_10_SEC 10UL /* 10 seconds */
3128#define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
3129#define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
3130#define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */
3131#define SCSI_MAX_RETRY 10 /* retry count */
3132
3133#define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
3134#define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
3135#define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
3136#define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
3137
3138
3139#define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
3140
3141/*
3142 * Device drivers must define the following functions.
3143 */
3144STATIC inline ulong DvcEnterCritical(void);
3145STATIC inline void DvcLeaveCritical(ulong);
3146STATIC void DvcSleepMilliSecond(ADV_DCNT);
3147STATIC uchar DvcAdvReadPCIConfigByte(ADV_DVC_VAR *, ushort);
3148STATIC void DvcAdvWritePCIConfigByte(ADV_DVC_VAR *, ushort, uchar);
3149STATIC ADV_PADDR DvcGetPhyAddr(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *,
3150 uchar *, ASC_SDCNT *, int);
3151STATIC void DvcDelayMicroSecond(ADV_DVC_VAR *, ushort);
3152
3153/*
3154 * Adv Library functions available to drivers.
3155 */
3156STATIC int AdvExeScsiQueue(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
3157STATIC int AdvISR(ADV_DVC_VAR *);
3158STATIC int AdvInitGetConfig(ADV_DVC_VAR *);
3159STATIC int AdvInitAsc3550Driver(ADV_DVC_VAR *);
3160STATIC int AdvInitAsc38C0800Driver(ADV_DVC_VAR *);
3161STATIC int AdvInitAsc38C1600Driver(ADV_DVC_VAR *);
3162STATIC int AdvResetChipAndSB(ADV_DVC_VAR *);
3163STATIC int AdvResetSB(ADV_DVC_VAR *asc_dvc);
3164
3165/*
3166 * Internal Adv Library functions.
3167 */
3168STATIC int AdvSendIdleCmd(ADV_DVC_VAR *, ushort, ADV_DCNT);
3169STATIC void AdvInquiryHandling(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
3170STATIC int AdvInitFrom3550EEP(ADV_DVC_VAR *);
3171STATIC int AdvInitFrom38C0800EEP(ADV_DVC_VAR *);
3172STATIC int AdvInitFrom38C1600EEP(ADV_DVC_VAR *);
3173STATIC ushort AdvGet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
3174STATIC void AdvSet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
3175STATIC ushort AdvGet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
3176STATIC void AdvSet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
3177STATIC ushort AdvGet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
3178STATIC void AdvSet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
3179STATIC void AdvWaitEEPCmd(AdvPortAddr);
3180STATIC ushort AdvReadEEPWord(AdvPortAddr, int);
3181
3182/*
3183 * PCI Bus Definitions
3184 */
3185#define AscPCICmdRegBits_BusMastering 0x0007
3186#define AscPCICmdRegBits_ParErrRespCtrl 0x0040
3187
3188/* Read byte from a register. */
3189#define AdvReadByteRegister(iop_base, reg_off) \
3190 (ADV_MEM_READB((iop_base) + (reg_off)))
3191
3192/* Write byte to a register. */
3193#define AdvWriteByteRegister(iop_base, reg_off, byte) \
3194 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
3195
3196/* Read word (2 bytes) from a register. */
3197#define AdvReadWordRegister(iop_base, reg_off) \
3198 (ADV_MEM_READW((iop_base) + (reg_off)))
3199
3200/* Write word (2 bytes) to a register. */
3201#define AdvWriteWordRegister(iop_base, reg_off, word) \
3202 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
3203
3204/* Write dword (4 bytes) to a register. */
3205#define AdvWriteDWordRegister(iop_base, reg_off, dword) \
3206 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
3207
3208/* Read byte from LRAM. */
3209#define AdvReadByteLram(iop_base, addr, byte) \
3210do { \
3211 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
3212 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
3213} while (0)
3214
3215/* Write byte to LRAM. */
3216#define AdvWriteByteLram(iop_base, addr, byte) \
3217 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3218 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
3219
3220/* Read word (2 bytes) from LRAM. */
3221#define AdvReadWordLram(iop_base, addr, word) \
3222do { \
3223 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
3224 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
3225} while (0)
3226
3227/* Write word (2 bytes) to LRAM. */
3228#define AdvWriteWordLram(iop_base, addr, word) \
3229 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3230 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
3231
3232/* Write little-endian double word (4 bytes) to LRAM */
3233/* Because of unspecified C language ordering don't use auto-increment. */
3234#define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
3235 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3236 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
3237 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
3238 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
3239 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
3240 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
3241
3242/* Read word (2 bytes) from LRAM assuming that the address is already set. */
3243#define AdvReadWordAutoIncLram(iop_base) \
3244 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
3245
3246/* Write word (2 bytes) to LRAM assuming that the address is already set. */
3247#define AdvWriteWordAutoIncLram(iop_base, word) \
3248 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
3249
3250
3251/*
3252 * Define macro to check for Condor signature.
3253 *
3254 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
3255 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
3256 */
3257#define AdvFindSignature(iop_base) \
3258 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
3259 ADV_CHIP_ID_BYTE) && \
3260 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
3261 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
3262
3263/*
3264 * Define macro to Return the version number of the chip at 'iop_base'.
3265 *
3266 * The second parameter 'bus_type' is currently unused.
3267 */
3268#define AdvGetChipVersion(iop_base, bus_type) \
3269 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
3270
3271/*
3272 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
3273 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
3274 *
3275 * If the request has not yet been sent to the device it will simply be
3276 * aborted from RISC memory. If the request is disconnected it will be
3277 * aborted on reselection by sending an Abort Message to the target ID.
3278 *
3279 * Return value:
3280 * ADV_TRUE(1) - Queue was successfully aborted.
3281 * ADV_FALSE(0) - Queue was not found on the active queue list.
3282 */
3283#define AdvAbortQueue(asc_dvc, scsiq) \
3284 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
3285 (ADV_DCNT) (scsiq))
3286
3287/*
3288 * Send a Bus Device Reset Message to the specified target ID.
3289 *
3290 * All outstanding commands will be purged if sending the
3291 * Bus Device Reset Message is successful.
3292 *
3293 * Return Value:
3294 * ADV_TRUE(1) - All requests on the target are purged.
3295 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
3296 * are not purged.
3297 */
3298#define AdvResetDevice(asc_dvc, target_id) \
3299 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
3300 (ADV_DCNT) (target_id))
3301
3302/*
3303 * SCSI Wide Type definition.
3304 */
3305#define ADV_SCSI_BIT_ID_TYPE ushort
3306
3307/*
3308 * AdvInitScsiTarget() 'cntl_flag' options.
3309 */
3310#define ADV_SCAN_LUN 0x01
3311#define ADV_CAPINFO_NOLUN 0x02
3312
3313/*
3314 * Convert target id to target id bit mask.
3315 */
3316#define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
3317
3318/*
3319 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
3320 */
3321
3322#define QD_NO_STATUS 0x00 /* Request not completed yet. */
3323#define QD_NO_ERROR 0x01
3324#define QD_ABORTED_BY_HOST 0x02
3325#define QD_WITH_ERROR 0x04
3326
3327#define QHSTA_NO_ERROR 0x00
3328#define QHSTA_M_SEL_TIMEOUT 0x11
3329#define QHSTA_M_DATA_OVER_RUN 0x12
3330#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
3331#define QHSTA_M_QUEUE_ABORTED 0x15
3332#define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
3333#define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
3334#define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
3335#define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
3336#define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
3337#define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
3338#define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
3339/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
3340#define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
3341#define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
3342#define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
3343#define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
3344#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
3345#define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
3346#define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
3347#define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
3348#define QHSTA_M_WTM_TIMEOUT 0x41
3349#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
3350#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
3351#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
3352#define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
3353#define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
3354#define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
3355
3356
3357/*
3358 * Default EEPROM Configuration structure defined in a_init.c.
3359 */
3360static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config;
3361static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config;
3362static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config;
3363
3364/*
3365 * DvcGetPhyAddr() flag arguments
3366 */
3367#define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
3368#define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
3369#define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
3370#define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
3371#define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
3372#define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
3373
3374/* Return the address that is aligned at the next doubleword >= to 'addr'. */
3375#define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
3376#define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
3377#define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
3378
3379/*
3380 * Total contiguous memory needed for driver SG blocks.
3381 *
3382 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
3383 * number of scatter-gather elements the driver supports in a
3384 * single request.
3385 */
3386
3387#define ADV_SG_LIST_MAX_BYTE_SIZE \
3388 (sizeof(ADV_SG_BLOCK) * \
3389 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
3390
3391/*
3392 * Inquiry data structure and bitfield macros
3393 *
3394 * Using bitfields to access the subchar data isn't portable across
3395 * endianness, so instead mask and shift. Only quantities of more
3396 * than 1 bit are shifted, since the others are just tested for true
3397 * or false.
3398 */
3399
3400#define ADV_INQ_DVC_TYPE(inq) ((inq)->periph & 0x1f)
3401#define ADV_INQ_QUALIFIER(inq) (((inq)->periph & 0xe0) >> 5)
3402#define ADV_INQ_DVC_TYPE_MOD(inq) ((inq)->devtype & 0x7f)
3403#define ADV_INQ_REMOVABLE(inq) ((inq)->devtype & 0x80)
3404#define ADV_INQ_ANSI_VER(inq) ((inq)->ver & 0x07)
3405#define ADV_INQ_ECMA_VER(inq) (((inq)->ver & 0x38) >> 3)
3406#define ADV_INQ_ISO_VER(inq) (((inq)->ver & 0xc0) >> 6)
3407#define ADV_INQ_RESPONSE_FMT(inq) ((inq)->byte3 & 0x0f)
3408#define ADV_INQ_TERM_IO(inq) ((inq)->byte3 & 0x40)
3409#define ADV_INQ_ASYNC_NOTIF(inq) ((inq)->byte3 & 0x80)
3410#define ADV_INQ_SOFT_RESET(inq) ((inq)->flags & 0x01)
3411#define ADV_INQ_CMD_QUEUE(inq) ((inq)->flags & 0x02)
3412#define ADV_INQ_LINK_CMD(inq) ((inq)->flags & 0x08)
3413#define ADV_INQ_SYNC(inq) ((inq)->flags & 0x10)
3414#define ADV_INQ_WIDE16(inq) ((inq)->flags & 0x20)
3415#define ADV_INQ_WIDE32(inq) ((inq)->flags & 0x40)
3416#define ADV_INQ_REL_ADDR(inq) ((inq)->flags & 0x80)
3417#define ADV_INQ_INFO_UNIT(inq) ((inq)->info & 0x01)
3418#define ADV_INQ_QUICK_ARB(inq) ((inq)->info & 0x02)
3419#define ADV_INQ_CLOCKING(inq) (((inq)->info & 0x0c) >> 2)
3420
3421typedef struct {
3422 uchar periph; /* peripheral device type [0:4] */
3423 /* peripheral qualifier [5:7] */
3424 uchar devtype; /* device type modifier (for SCSI I) [0:6] */
3425 /* RMB - removable medium bit [7] */
3426 uchar ver; /* ANSI approved version [0:2] */
3427 /* ECMA version [3:5] */
3428 /* ISO version [6:7] */
3429 uchar byte3; /* response data format [0:3] */
3430 /* 0 SCSI 1 */
3431 /* 1 CCS */
3432 /* 2 SCSI-2 */
3433 /* 3-F reserved */
3434 /* reserved [4:5] */
3435 /* terminate I/O process bit (see 5.6.22) [6] */
3436 /* asynch. event notification (processor) [7] */
3437 uchar add_len; /* additional length */
3438 uchar res1; /* reserved */
3439 uchar res2; /* reserved */
3440 uchar flags; /* soft reset implemented [0] */
3441 /* command queuing [1] */
3442 /* reserved [2] */
3443 /* linked command for this logical unit [3] */
3444 /* synchronous data transfer [4] */
3445 /* wide bus 16 bit data transfer [5] */
3446 /* wide bus 32 bit data transfer [6] */
3447 /* relative addressing mode [7] */
3448 uchar vendor_id[8]; /* vendor identification */
3449 uchar product_id[16]; /* product identification */
3450 uchar product_rev_level[4]; /* product revision level */
3451 uchar vendor_specific[20]; /* vendor specific */
3452 uchar info; /* information unit supported [0] */
3453 /* quick arbitrate supported [1] */
3454 /* clocking field [2:3] */
3455 /* reserved [4:7] */
3456 uchar res3; /* reserved */
3457} ADV_SCSI_INQUIRY; /* 58 bytes */
3458
3459
3460/*
3461 * --- Driver Constants and Macros
3462 */
3463
3464#define ASC_NUM_BOARD_SUPPORTED 16
3465#define ASC_NUM_IOPORT_PROBE 4
3466#define ASC_NUM_BUS 4
3467
3468/* Reference Scsi_Host hostdata */
3469#define ASC_BOARDP(host) ((asc_board_t *) &((host)->hostdata))
3470
3471/* asc_board_t flags */
3472#define ASC_HOST_IN_RESET 0x01
3473#define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
3474#define ASC_SELECT_QUEUE_DEPTHS 0x08
3475
3476#define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
3477#define ASC_WIDE_BOARD(boardp) ((boardp)->flags & ASC_IS_WIDE_BOARD)
3478
3479#define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
3480
3481#define ASC_INFO_SIZE 128 /* advansys_info() line size */
3482
3483#ifdef CONFIG_PROC_FS
3484/* /proc/scsi/advansys/[0...] related definitions */
3485#define ASC_PRTBUF_SIZE 2048
3486#define ASC_PRTLINE_SIZE 160
3487
3488#define ASC_PRT_NEXT() \
3489 if (cp) { \
3490 totlen += len; \
3491 leftlen -= len; \
3492 if (leftlen == 0) { \
3493 return totlen; \
3494 } \
3495 cp += len; \
3496 }
3497#endif /* CONFIG_PROC_FS */
3498
3499/* Asc Library return codes */
3500#define ASC_TRUE 1
3501#define ASC_FALSE 0
3502#define ASC_NOERROR 1
3503#define ASC_BUSY 0
3504#define ASC_ERROR (-1)
3505
3506/* struct scsi_cmnd function return codes */
3507#define STATUS_BYTE(byte) (byte)
3508#define MSG_BYTE(byte) ((byte) << 8)
3509#define HOST_BYTE(byte) ((byte) << 16)
3510#define DRIVER_BYTE(byte) ((byte) << 24)
3511
3512/*
3513 * The following definitions and macros are OS independent interfaces to
3514 * the queue functions:
3515 * REQ - SCSI request structure
3516 * REQP - pointer to SCSI request structure
3517 * REQPTID(reqp) - reqp's target id
3518 * REQPNEXT(reqp) - reqp's next pointer
3519 * REQPNEXTP(reqp) - pointer to reqp's next pointer
3520 * REQPTIME(reqp) - reqp's time stamp value
3521 * REQTIMESTAMP() - system time stamp value
3522 */
3523typedef struct scsi_cmnd REQ, *REQP;
3524#define REQPNEXT(reqp) ((REQP) ((reqp)->host_scribble))
3525#define REQPNEXTP(reqp) ((REQP *) &((reqp)->host_scribble))
3526#define REQPTID(reqp) ((reqp)->device->id)
3527#define REQPTIME(reqp) ((reqp)->SCp.this_residual)
3528#define REQTIMESTAMP() (jiffies)
3529
3530#define REQTIMESTAT(function, ascq, reqp, tid) \
3531{ \
3532 /*
3533 * If the request time stamp is less than the system time stamp, then \
3534 * maybe the system time stamp wrapped. Set the request time to zero.\
3535 */ \
3536 if (REQPTIME(reqp) <= REQTIMESTAMP()) { \
3537 REQPTIME(reqp) = REQTIMESTAMP() - REQPTIME(reqp); \
3538 } else { \
3539 /* Indicate an error occurred with the assertion. */ \
3540 ASC_ASSERT(REQPTIME(reqp) <= REQTIMESTAMP()); \
3541 REQPTIME(reqp) = 0; \
3542 } \
3543 /* Handle first minimum time case without external initialization. */ \
3544 if (((ascq)->q_tot_cnt[tid] == 1) || \
3545 (REQPTIME(reqp) < (ascq)->q_min_tim[tid])) { \
3546 (ascq)->q_min_tim[tid] = REQPTIME(reqp); \
3547 ASC_DBG3(1, "%s: new q_min_tim[%d] %u\n", \
3548 (function), (tid), (ascq)->q_min_tim[tid]); \
3549 } \
3550 if (REQPTIME(reqp) > (ascq)->q_max_tim[tid]) { \
3551 (ascq)->q_max_tim[tid] = REQPTIME(reqp); \
3552 ASC_DBG3(1, "%s: new q_max_tim[%d] %u\n", \
3553 (function), tid, (ascq)->q_max_tim[tid]); \
3554 } \
3555 (ascq)->q_tot_tim[tid] += REQPTIME(reqp); \
3556 /* Reset the time stamp field. */ \
3557 REQPTIME(reqp) = 0; \
3558}
3559
3560/* asc_enqueue() flags */
3561#define ASC_FRONT 1
3562#define ASC_BACK 2
3563
3564/* asc_dequeue_list() argument */
3565#define ASC_TID_ALL (-1)
3566
3567/* Return non-zero, if the queue is empty. */
3568#define ASC_QUEUE_EMPTY(ascq) ((ascq)->q_tidmask == 0)
3569
3570#define PCI_MAX_SLOT 0x1F
3571#define PCI_MAX_BUS 0xFF
3572#define PCI_IOADDRESS_MASK 0xFFFE
3573#define ASC_PCI_VENDORID 0x10CD
3574#define ASC_PCI_DEVICE_ID_CNT 6 /* PCI Device ID count. */
3575#define ASC_PCI_DEVICE_ID_1100 0x1100
3576#define ASC_PCI_DEVICE_ID_1200 0x1200
3577#define ASC_PCI_DEVICE_ID_1300 0x1300
3578#define ASC_PCI_DEVICE_ID_2300 0x2300 /* ASC-3550 */
3579#define ASC_PCI_DEVICE_ID_2500 0x2500 /* ASC-38C0800 */
3580#define ASC_PCI_DEVICE_ID_2700 0x2700 /* ASC-38C1600 */
3581
3582#ifndef ADVANSYS_STATS
3583#define ASC_STATS(shp, counter)
3584#define ASC_STATS_ADD(shp, counter, count)
3585#else /* ADVANSYS_STATS */
3586#define ASC_STATS(shp, counter) \
3587 (ASC_BOARDP(shp)->asc_stats.counter++)
3588
3589#define ASC_STATS_ADD(shp, counter, count) \
3590 (ASC_BOARDP(shp)->asc_stats.counter += (count))
3591#endif /* ADVANSYS_STATS */
3592
3593#define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
3594
3595/* If the result wraps when calculating tenths, return 0. */
3596#define ASC_TENTHS(num, den) \
3597 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
3598 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
3599
3600/*
3601 * Display a message to the console.
3602 */
3603#define ASC_PRINT(s) \
3604 { \
3605 printk("advansys: "); \
3606 printk(s); \
3607 }
3608
3609#define ASC_PRINT1(s, a1) \
3610 { \
3611 printk("advansys: "); \
3612 printk((s), (a1)); \
3613 }
3614
3615#define ASC_PRINT2(s, a1, a2) \
3616 { \
3617 printk("advansys: "); \
3618 printk((s), (a1), (a2)); \
3619 }
3620
3621#define ASC_PRINT3(s, a1, a2, a3) \
3622 { \
3623 printk("advansys: "); \
3624 printk((s), (a1), (a2), (a3)); \
3625 }
3626
3627#define ASC_PRINT4(s, a1, a2, a3, a4) \
3628 { \
3629 printk("advansys: "); \
3630 printk((s), (a1), (a2), (a3), (a4)); \
3631 }
3632
3633
3634#ifndef ADVANSYS_DEBUG
3635
3636#define ASC_DBG(lvl, s)
3637#define ASC_DBG1(lvl, s, a1)
3638#define ASC_DBG2(lvl, s, a1, a2)
3639#define ASC_DBG3(lvl, s, a1, a2, a3)
3640#define ASC_DBG4(lvl, s, a1, a2, a3, a4)
3641#define ASC_DBG_PRT_SCSI_HOST(lvl, s)
3642#define ASC_DBG_PRT_SCSI_CMND(lvl, s)
3643#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
3644#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
3645#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
3646#define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
3647#define ASC_DBG_PRT_HEX(lvl, name, start, length)
3648#define ASC_DBG_PRT_CDB(lvl, cdb, len)
3649#define ASC_DBG_PRT_SENSE(lvl, sense, len)
3650#define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
3651
3652#else /* ADVANSYS_DEBUG */
3653
3654/*
3655 * Debugging Message Levels:
3656 * 0: Errors Only
3657 * 1: High-Level Tracing
3658 * 2-N: Verbose Tracing
3659 */
3660
3661#define ASC_DBG(lvl, s) \
3662 { \
3663 if (asc_dbglvl >= (lvl)) { \
3664 printk(s); \
3665 } \
3666 }
3667
3668#define ASC_DBG1(lvl, s, a1) \
3669 { \
3670 if (asc_dbglvl >= (lvl)) { \
3671 printk((s), (a1)); \
3672 } \
3673 }
3674
3675#define ASC_DBG2(lvl, s, a1, a2) \
3676 { \
3677 if (asc_dbglvl >= (lvl)) { \
3678 printk((s), (a1), (a2)); \
3679 } \
3680 }
3681
3682#define ASC_DBG3(lvl, s, a1, a2, a3) \
3683 { \
3684 if (asc_dbglvl >= (lvl)) { \
3685 printk((s), (a1), (a2), (a3)); \
3686 } \
3687 }
3688
3689#define ASC_DBG4(lvl, s, a1, a2, a3, a4) \
3690 { \
3691 if (asc_dbglvl >= (lvl)) { \
3692 printk((s), (a1), (a2), (a3), (a4)); \
3693 } \
3694 }
3695
3696#define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
3697 { \
3698 if (asc_dbglvl >= (lvl)) { \
3699 asc_prt_scsi_host(s); \
3700 } \
3701 }
3702
3703#define ASC_DBG_PRT_SCSI_CMND(lvl, s) \
3704 { \
3705 if (asc_dbglvl >= (lvl)) { \
3706 asc_prt_scsi_cmnd(s); \
3707 } \
3708 }
3709
3710#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
3711 { \
3712 if (asc_dbglvl >= (lvl)) { \
3713 asc_prt_asc_scsi_q(scsiqp); \
3714 } \
3715 }
3716
3717#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
3718 { \
3719 if (asc_dbglvl >= (lvl)) { \
3720 asc_prt_asc_qdone_info(qdone); \
3721 } \
3722 }
3723
3724#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
3725 { \
3726 if (asc_dbglvl >= (lvl)) { \
3727 asc_prt_adv_scsi_req_q(scsiqp); \
3728 } \
3729 }
3730
3731#define ASC_DBG_PRT_HEX(lvl, name, start, length) \
3732 { \
3733 if (asc_dbglvl >= (lvl)) { \
3734 asc_prt_hex((name), (start), (length)); \
3735 } \
3736 }
3737
3738#define ASC_DBG_PRT_CDB(lvl, cdb, len) \
3739 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
3740
3741#define ASC_DBG_PRT_SENSE(lvl, sense, len) \
3742 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
3743
3744#define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
3745 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
3746#endif /* ADVANSYS_DEBUG */
3747
3748#ifndef ADVANSYS_ASSERT
3749#define ASC_ASSERT(a)
3750#else /* ADVANSYS_ASSERT */
3751
3752#define ASC_ASSERT(a) \
3753 { \
3754 if (!(a)) { \
3755 printk("ASC_ASSERT() Failure: file %s, line %d\n", \
3756 __FILE__, __LINE__); \
3757 } \
3758 }
3759
3760#endif /* ADVANSYS_ASSERT */
3761
3762
3763/*
3764 * --- Driver Structures
3765 */
3766
3767#ifdef ADVANSYS_STATS
3768
3769/* Per board statistics structure */
3770struct asc_stats {
3771 /* Driver Entrypoint Statistics */
3772 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
3773 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
3774 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
3775 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
3776 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
3777 ADV_DCNT done; /* # calls to request's scsi_done function */
3778 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
3779 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
3780 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
3781 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
3782 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
3783 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
3784 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
3785 ADV_DCNT exe_unknown; /* # unknown returns. */
3786 /* Data Transfer Statistics */
3787 ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
3788 ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
3789 ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
3790 ADV_DCNT sg_elem; /* # scatter-gather elements */
3791 ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
3792};
3793#endif /* ADVANSYS_STATS */
3794
3795/*
3796 * Request queuing structure
3797 */
3798typedef struct asc_queue {
3799 ADV_SCSI_BIT_ID_TYPE q_tidmask; /* queue mask */
3800 REQP q_first[ADV_MAX_TID+1]; /* first queued request */
3801 REQP q_last[ADV_MAX_TID+1]; /* last queued request */
3802#ifdef ADVANSYS_STATS
3803 short q_cur_cnt[ADV_MAX_TID+1]; /* current queue count */
3804 short q_max_cnt[ADV_MAX_TID+1]; /* maximum queue count */
3805 ADV_DCNT q_tot_cnt[ADV_MAX_TID+1]; /* total enqueue count */
3806 ADV_DCNT q_tot_tim[ADV_MAX_TID+1]; /* total time queued */
3807 ushort q_max_tim[ADV_MAX_TID+1]; /* maximum time queued */
3808 ushort q_min_tim[ADV_MAX_TID+1]; /* minimum time queued */
3809#endif /* ADVANSYS_STATS */
3810} asc_queue_t;
3811
3812/*
3813 * Adv Library Request Structures
3814 *
3815 * The following two structures are used to process Wide Board requests.
3816 *
3817 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
3818 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
3819 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
3820 * Mid-Level SCSI request structure.
3821 *
3822 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
3823 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
3824 * up to 255 scatter-gather elements may be used per request or
3825 * ADV_SCSI_REQ_Q.
3826 *
3827 * Both structures must be 32 byte aligned.
3828 */
3829typedef struct adv_sgblk {
3830 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
3831 uchar align[32]; /* Sgblock structure padding. */
3832 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
3833} adv_sgblk_t;
3834
3835typedef struct adv_req {
3836 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
3837 uchar align[32]; /* Request structure padding. */
3838 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
3839 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
3840 struct adv_req *next_reqp; /* Next Request Structure. */
3841} adv_req_t;
3842
3843/*
3844 * Structure allocated for each board.
3845 *
3846 * This structure is allocated by scsi_register() at the end
3847 * of the 'Scsi_Host' structure starting at the 'hostdata'
3848 * field. It is guaranteed to be allocated from DMA-able memory.
3849 */
3850typedef struct asc_board {
3851 int id; /* Board Id */
3852 uint flags; /* Board flags */
3853 union {
3854 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
3855 ADV_DVC_VAR adv_dvc_var; /* Wide board */
3856 } dvc_var;
3857 union {
3858 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
3859 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
3860 } dvc_cfg;
3861 ushort asc_n_io_port; /* Number I/O ports. */
3862 asc_queue_t active; /* Active command queue */
3863 asc_queue_t waiting; /* Waiting command queue */
3864 asc_queue_t done; /* Done command queue */
3865 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
3866 struct scsi_device *device[ADV_MAX_TID+1]; /* Mid-Level Scsi Device */
3867 ushort reqcnt[ADV_MAX_TID+1]; /* Starvation request count */
3868 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
3869 ushort queue_full_cnt[ADV_MAX_TID+1]; /* Queue full count */
3870 union {
3871 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
3872 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
3873 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
3874 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
3875 } eep_config;
3876 ulong last_reset; /* Saved last reset time */
3877 spinlock_t lock; /* Board spinlock */
3878#ifdef CONFIG_PROC_FS
3879 /* /proc/scsi/advansys/[0...] */
3880 char *prtbuf; /* /proc print buffer */
3881#endif /* CONFIG_PROC_FS */
3882#ifdef ADVANSYS_STATS
3883 struct asc_stats asc_stats; /* Board statistics */
3884#endif /* ADVANSYS_STATS */
3885 /*
3886 * The following fields are used only for Narrow Boards.
3887 */
3888 /* The following three structures must be in DMA-able memory. */
3889 ASC_SCSI_REQ_Q scsireqq;
3890 ASC_CAP_INFO cap_info;
3891 ASC_SCSI_INQUIRY inquiry;
3892 uchar sdtr_data[ASC_MAX_TID+1]; /* SDTR information */
3893 /*
3894 * The following fields are used only for Wide Boards.
3895 */
3896 void *ioremap_addr; /* I/O Memory remap address. */
3897 ushort ioport; /* I/O Port address. */
3898 ADV_CARR_T *orig_carrp; /* ADV_CARR_T memory block. */
3899 adv_req_t *orig_reqp; /* adv_req_t memory block. */
3900 adv_req_t *adv_reqp; /* Request structures. */
3901 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
3902 ushort bios_signature; /* BIOS Signature. */
3903 ushort bios_version; /* BIOS Version. */
3904 ushort bios_codeseg; /* BIOS Code Segment. */
3905 ushort bios_codelen; /* BIOS Code Segment Length. */
3906} asc_board_t;
3907
3908/*
3909 * PCI configuration structures
3910 */
3911typedef struct _PCI_DATA_
3912{
3913 uchar type;
3914 uchar bus;
3915 uchar slot;
3916 uchar func;
3917 uchar offset;
3918} PCI_DATA;
3919
3920typedef struct _PCI_DEVICE_
3921{
3922 ushort vendorID;
3923 ushort deviceID;
3924 ushort slotNumber;
3925 ushort slotFound;
3926 uchar busNumber;
3927 uchar maxBusNumber;
3928 uchar devFunc;
3929 ushort startSlot;
3930 ushort endSlot;
3931 uchar bridge;
3932 uchar type;
3933} PCI_DEVICE;
3934
3935typedef struct _PCI_CONFIG_SPACE_
3936{
3937 ushort vendorID;
3938 ushort deviceID;
3939 ushort command;
3940 ushort status;
3941 uchar revision;
3942 uchar classCode[3];
3943 uchar cacheSize;
3944 uchar latencyTimer;
3945 uchar headerType;
3946 uchar bist;
3947 ADV_PADDR baseAddress[6];
3948 ushort reserved[4];
3949 ADV_PADDR optionRomAddr;
3950 ushort reserved2[4];
3951 uchar irqLine;
3952 uchar irqPin;
3953 uchar minGnt;
3954 uchar maxLatency;
3955} PCI_CONFIG_SPACE;
3956
3957
3958/*
3959 * --- Driver Data
3960 */
3961
3962/* Note: All driver global data should be initialized. */
3963
3964/* Number of boards detected in system. */
3965STATIC int asc_board_count = 0;
3966STATIC struct Scsi_Host *asc_host[ASC_NUM_BOARD_SUPPORTED] = { 0 };
3967
3968/* Overrun buffer used by all narrow boards. */
3969STATIC uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
3970
3971/*
3972 * Global structures required to issue a command.
3973 */
3974STATIC ASC_SCSI_Q asc_scsi_q = { { 0 } };
3975STATIC ASC_SG_HEAD asc_sg_head = { 0 };
3976
3977/* List of supported bus types. */
3978STATIC ushort asc_bus[ASC_NUM_BUS] __initdata = {
3979 ASC_IS_ISA,
3980 ASC_IS_VL,
3981 ASC_IS_EISA,
3982 ASC_IS_PCI,
3983};
3984
3985/*
3986 * Used with the LILO 'advansys' option to eliminate or
3987 * limit I/O port probing at boot time, cf. advansys_setup().
3988 */
3989STATIC int asc_iopflag = ASC_FALSE;
3990STATIC int asc_ioport[ASC_NUM_IOPORT_PROBE] = { 0, 0, 0, 0 };
3991
3992#ifdef ADVANSYS_DEBUG
3993STATIC char *
3994asc_bus_name[ASC_NUM_BUS] = {
3995 "ASC_IS_ISA",
3996 "ASC_IS_VL",
3997 "ASC_IS_EISA",
3998 "ASC_IS_PCI",
3999};
4000
4001STATIC int asc_dbglvl = 3;
4002#endif /* ADVANSYS_DEBUG */
4003
4004/* Declaration for Asc Library internal data referenced by driver. */
4005STATIC PortAddr _asc_def_iop_base[];
4006
4007
4008/*
4009 * --- Driver Function Prototypes
4010 *
4011 * advansys.h contains function prototypes for functions global to Linux.
4012 */
4013
4014STATIC irqreturn_t advansys_interrupt(int, void *, struct pt_regs *);
4015STATIC int advansys_slave_configure(struct scsi_device *);
4016STATIC void asc_scsi_done_list(struct scsi_cmnd *);
4017STATIC int asc_execute_scsi_cmnd(struct scsi_cmnd *);
4018STATIC int asc_build_req(asc_board_t *, struct scsi_cmnd *);
4019STATIC int adv_build_req(asc_board_t *, struct scsi_cmnd *, ADV_SCSI_REQ_Q **);
4020STATIC int adv_get_sglist(asc_board_t *, adv_req_t *, struct scsi_cmnd *, int);
4021STATIC void asc_isr_callback(ASC_DVC_VAR *, ASC_QDONE_INFO *);
4022STATIC void adv_isr_callback(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
4023STATIC void adv_async_callback(ADV_DVC_VAR *, uchar);
4024STATIC void asc_enqueue(asc_queue_t *, REQP, int);
4025STATIC REQP asc_dequeue(asc_queue_t *, int);
4026STATIC REQP asc_dequeue_list(asc_queue_t *, REQP *, int);
4027STATIC int asc_rmqueue(asc_queue_t *, REQP);
4028STATIC void asc_execute_queue(asc_queue_t *);
4029#ifdef CONFIG_PROC_FS
4030STATIC int asc_proc_copy(off_t, off_t, char *, int , char *, int);
4031STATIC int asc_prt_board_devices(struct Scsi_Host *, char *, int);
4032STATIC int asc_prt_adv_bios(struct Scsi_Host *, char *, int);
4033STATIC int asc_get_eeprom_string(ushort *serialnum, uchar *cp);
4034STATIC int asc_prt_asc_board_eeprom(struct Scsi_Host *, char *, int);
4035STATIC int asc_prt_adv_board_eeprom(struct Scsi_Host *, char *, int);
4036STATIC int asc_prt_driver_conf(struct Scsi_Host *, char *, int);
4037STATIC int asc_prt_asc_board_info(struct Scsi_Host *, char *, int);
4038STATIC int asc_prt_adv_board_info(struct Scsi_Host *, char *, int);
4039STATIC int asc_prt_line(char *, int, char *fmt, ...);
4040#endif /* CONFIG_PROC_FS */
4041
4042/* Declaration for Asc Library internal functions referenced by driver. */
4043STATIC int AscFindSignature(PortAddr);
4044STATIC ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
4045
4046/* Statistics function prototypes. */
4047#ifdef ADVANSYS_STATS
4048#ifdef CONFIG_PROC_FS
4049STATIC int asc_prt_board_stats(struct Scsi_Host *, char *, int);
4050STATIC int asc_prt_target_stats(struct Scsi_Host *, int, char *, int);
4051#endif /* CONFIG_PROC_FS */
4052#endif /* ADVANSYS_STATS */
4053
4054/* Debug function prototypes. */
4055#ifdef ADVANSYS_DEBUG
4056STATIC void asc_prt_scsi_host(struct Scsi_Host *);
4057STATIC void asc_prt_scsi_cmnd(struct scsi_cmnd *);
4058STATIC void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *);
4059STATIC void asc_prt_asc_dvc_var(ASC_DVC_VAR *);
4060STATIC void asc_prt_asc_scsi_q(ASC_SCSI_Q *);
4061STATIC void asc_prt_asc_qdone_info(ASC_QDONE_INFO *);
4062STATIC void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *);
4063STATIC void asc_prt_adv_dvc_var(ADV_DVC_VAR *);
4064STATIC void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *);
4065STATIC void asc_prt_adv_sgblock(int, ADV_SG_BLOCK *);
4066STATIC void asc_prt_hex(char *f, uchar *, int);
4067#endif /* ADVANSYS_DEBUG */
4068
4069
4070/*
d0be4a7d 4071 * --- Linux 'struct scsi_host_template' and advansys_setup() Functions
1da177e4
LT		 4072 */
4073
4074#ifdef CONFIG_PROC_FS
4075/*
4076 * advansys_proc_info() - /proc/scsi/advansys/[0-(ASC_NUM_BOARD_SUPPORTED-1)]
4077 *
4078 * *buffer: I/O buffer
4079 * **start: if inout == FALSE pointer into buffer where user read should start
4080 * offset: current offset into a /proc/scsi/advansys/[0...] file
4081 * length: length of buffer
4082 * hostno: Scsi_Host host_no
4083 * inout: TRUE - user is writing; FALSE - user is reading
4084 *
4085 * Return the number of bytes read from or written to a
4086 * /proc/scsi/advansys/[0...] file.
4087 *
4088 * Note: This function uses the per board buffer 'prtbuf' which is
4089 * allocated when the board is initialized in advansys_detect(). The
4090 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4091 * used to write to the buffer. The way asc_proc_copy() is written
4092 * if 'prtbuf' is too small it will not be overwritten. Instead the
4093 * user just won't get all the available statistics.
4094 */
4095int
4096advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4097 off_t offset, int length, int inout)
4098{
4099 struct Scsi_Host *shp;
4100 asc_board_t *boardp;
4101 int i;
4102 char *cp;
4103 int cplen;
4104 int cnt;
4105 int totcnt;
4106 int leftlen;
4107 char *curbuf;
4108 off_t advoffset;
4109#ifdef ADVANSYS_STATS
4110 int tgt_id;
4111#endif /* ADVANSYS_STATS */
4112
4113 ASC_DBG(1, "advansys_proc_info: begin\n");
4114
4115 /*
4116 * User write not supported.
4117 */
4118 if (inout == TRUE) {
4119 return(-ENOSYS);
4120 }
4121
4122 /*
4123 * User read of /proc/scsi/advansys/[0...] file.
4124 */
4125
4126 /* Find the specified board. */
4127 for (i = 0; i < asc_board_count; i++) {
4128 if (asc_host[i]->host_no == shost->host_no) {
4129 break;
4130 }
4131 }
4132 if (i == asc_board_count) {
4133 return(-ENOENT);
4134 }
4135
4136 shp = asc_host[i];
4137 boardp = ASC_BOARDP(shp);
4138
4139 /* Copy read data starting at the beginning of the buffer. */
4140 *start = buffer;
4141 curbuf = buffer;
4142 advoffset = 0;
4143 totcnt = 0;
4144 leftlen = length;
4145
4146 /*
4147 * Get board configuration information.
4148 *
4149 * advansys_info() returns the board string from its own static buffer.
4150 */
4151 cp = (char *) advansys_info(shp);
4152 strcat(cp, "\n");
4153 cplen = strlen(cp);
4154 /* Copy board information. */
4155 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4156 totcnt += cnt;
4157 leftlen -= cnt;
4158 if (leftlen == 0) {
4159 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4160 return totcnt;
4161 }
4162 advoffset += cplen;
4163 curbuf += cnt;
4164
4165 /*
4166 * Display Wide Board BIOS Information.
4167 */
4168 if (ASC_WIDE_BOARD(boardp)) {
4169 cp = boardp->prtbuf;
4170 cplen = asc_prt_adv_bios(shp, cp, ASC_PRTBUF_SIZE);
4171 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4172 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4173 totcnt += cnt;
4174 leftlen -= cnt;
4175 if (leftlen == 0) {
4176 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4177 return totcnt;
4178 }
4179 advoffset += cplen;
4180 curbuf += cnt;
4181 }
4182
4183 /*
4184 * Display driver information for each device attached to the board.
4185 */
4186 cp = boardp->prtbuf;
4187 cplen = asc_prt_board_devices(shp, cp, ASC_PRTBUF_SIZE);
4188 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4189 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4190 totcnt += cnt;
4191 leftlen -= cnt;
4192 if (leftlen == 0) {
4193 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4194 return totcnt;
4195 }
4196 advoffset += cplen;
4197 curbuf += cnt;
4198
4199 /*
4200 * Display EEPROM configuration for the board.
4201 */
4202 cp = boardp->prtbuf;
4203 if (ASC_NARROW_BOARD(boardp)) {
4204 cplen = asc_prt_asc_board_eeprom(shp, cp, ASC_PRTBUF_SIZE);
4205 } else {
4206 cplen = asc_prt_adv_board_eeprom(shp, cp, ASC_PRTBUF_SIZE);
4207 }
4208 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4209 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4210 totcnt += cnt;
4211 leftlen -= cnt;
4212 if (leftlen == 0) {
4213 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4214 return totcnt;
4215 }
4216 advoffset += cplen;
4217 curbuf += cnt;
4218
4219 /*
4220 * Display driver configuration and information for the board.
4221 */
4222 cp = boardp->prtbuf;
4223 cplen = asc_prt_driver_conf(shp, cp, ASC_PRTBUF_SIZE);
4224 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4225 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4226 totcnt += cnt;
4227 leftlen -= cnt;
4228 if (leftlen == 0) {
4229 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4230 return totcnt;
4231 }
4232 advoffset += cplen;
4233 curbuf += cnt;
4234
4235#ifdef ADVANSYS_STATS
4236 /*
4237 * Display driver statistics for the board.
4238 */
4239 cp = boardp->prtbuf;
4240 cplen = asc_prt_board_stats(shp, cp, ASC_PRTBUF_SIZE);
4241 ASC_ASSERT(cplen <= ASC_PRTBUF_SIZE);
4242 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4243 totcnt += cnt;
4244 leftlen -= cnt;
4245 if (leftlen == 0) {
4246 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4247 return totcnt;
4248 }
4249 advoffset += cplen;
4250 curbuf += cnt;
4251
4252 /*
4253 * Display driver statistics for each target.
4254 */
4255 for (tgt_id = 0; tgt_id <= ADV_MAX_TID; tgt_id++) {
4256 cp = boardp->prtbuf;
4257 cplen = asc_prt_target_stats(shp, tgt_id, cp, ASC_PRTBUF_SIZE);
4258 ASC_ASSERT(cplen <= ASC_PRTBUF_SIZE);
4259 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4260 totcnt += cnt;
4261 leftlen -= cnt;
4262 if (leftlen == 0) {
4263 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4264 return totcnt;
4265 }
4266 advoffset += cplen;
4267 curbuf += cnt;
4268 }
4269#endif /* ADVANSYS_STATS */
4270
4271 /*
4272 * Display Asc Library dynamic configuration information
4273 * for the board.
4274 */
4275 cp = boardp->prtbuf;
4276 if (ASC_NARROW_BOARD(boardp)) {
4277 cplen = asc_prt_asc_board_info(shp, cp, ASC_PRTBUF_SIZE);
4278 } else {
4279 cplen = asc_prt_adv_board_info(shp, cp, ASC_PRTBUF_SIZE);
4280 }
4281 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4282 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4283 totcnt += cnt;
4284 leftlen -= cnt;
4285 if (leftlen == 0) {
4286 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4287 return totcnt;
4288 }
4289 advoffset += cplen;
4290 curbuf += cnt;
4291
4292 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4293
4294 return totcnt;
4295}
4296#endif /* CONFIG_PROC_FS */
4297
4298/*
4299 * advansys_detect()
4300 *
4301 * Detect function for AdvanSys adapters.
4302 *
4303 * Argument is a pointer to the host driver's scsi_hosts entry.
4304 *
4305 * Return number of adapters found.
4306 *
4307 * Note: Because this function is called during system initialization
4308 * it must not call SCSI mid-level functions including scsi_malloc()
4309 * and scsi_free().
4310 */
4311int __init
4312advansys_detect(struct scsi_host_template *tpnt)
4313{
4314 static int detect_called = ASC_FALSE;
4315 int iop;
4316 int bus;
4317 struct Scsi_Host *shp = NULL;
4318 asc_board_t *boardp = NULL;
4319 ASC_DVC_VAR *asc_dvc_varp = NULL;
4320 ADV_DVC_VAR *adv_dvc_varp = NULL;
4321 adv_sgblk_t *sgp = NULL;
4322 int ioport = 0;
4323 int share_irq = FALSE;
4324 int iolen = 0;
4325 struct device *dev = NULL;
4326#ifdef CONFIG_PCI
4327 int pci_init_search = 0;
4328 struct pci_dev *pci_devicep[ASC_NUM_BOARD_SUPPORTED];
4329 int pci_card_cnt_max = 0;
4330 int pci_card_cnt = 0;
4331 struct pci_dev *pci_devp = NULL;
4332 int pci_device_id_cnt = 0;
4333 unsigned int pci_device_id[ASC_PCI_DEVICE_ID_CNT] = {
4334 ASC_PCI_DEVICE_ID_1100,
4335 ASC_PCI_DEVICE_ID_1200,
4336 ASC_PCI_DEVICE_ID_1300,
4337 ASC_PCI_DEVICE_ID_2300,
4338 ASC_PCI_DEVICE_ID_2500,
4339 ASC_PCI_DEVICE_ID_2700
4340 };
4341 ADV_PADDR pci_memory_address;
4342#endif /* CONFIG_PCI */
4343 int warn_code, err_code;
4344 int ret;
4345
4346 if (detect_called == ASC_FALSE) {
4347 detect_called = ASC_TRUE;
4348 } else {
4349 printk("AdvanSys SCSI: advansys_detect() multiple calls ignored\n");
4350 return 0;
4351 }
4352
4353 ASC_DBG(1, "advansys_detect: begin\n");
4354
4355 asc_board_count = 0;
4356
4357 /*
4358 * If I/O port probing has been modified, then verify and
4359 * clean-up the 'asc_ioport' list.
4360 */
4361 if (asc_iopflag == ASC_TRUE) {
4362 for (ioport = 0; ioport < ASC_NUM_IOPORT_PROBE; ioport++) {
4363 ASC_DBG2(1, "advansys_detect: asc_ioport[%d] 0x%x\n",
4364 ioport, asc_ioport[ioport]);
4365 if (asc_ioport[ioport] != 0) {
4366 for (iop = 0; iop < ASC_IOADR_TABLE_MAX_IX; iop++) {
4367 if (_asc_def_iop_base[iop] == asc_ioport[ioport]) {
4368 break;
4369 }
4370 }
4371 if (iop == ASC_IOADR_TABLE_MAX_IX) {
4372 printk(
4373"AdvanSys SCSI: specified I/O Port 0x%X is invalid\n",
4374 asc_ioport[ioport]);
4375 asc_ioport[ioport] = 0;
4376 }
4377 }
4378 }
4379 ioport = 0;
4380 }
4381
4382 for (bus = 0; bus < ASC_NUM_BUS; bus++) {
4383
4384 ASC_DBG2(1, "advansys_detect: bus search type %d (%s)\n",
4385 bus, asc_bus_name[bus]);
4386 iop = 0;
4387
4388 while (asc_board_count < ASC_NUM_BOARD_SUPPORTED) {
4389
4390 ASC_DBG1(2, "advansys_detect: asc_board_count %d\n",
4391 asc_board_count);
4392
4393 switch (asc_bus[bus]) {
4394 case ASC_IS_ISA:
4395 case ASC_IS_VL:
4396#ifdef CONFIG_ISA
4397 if (asc_iopflag == ASC_FALSE) {
4398 iop = AscSearchIOPortAddr(iop, asc_bus[bus]);
4399 } else {
4400 /*
4401 * ISA and VL I/O port scanning has either been
4402 * eliminated or limited to selected ports on
4403 * the LILO command line, /etc/lilo.conf, or
4404 * by setting variables when the module was loaded.
4405 */
4406 ASC_DBG(1, "advansys_detect: I/O port scanning modified\n");
4407 ioport_try_again:
4408 iop = 0;
4409 for (; ioport < ASC_NUM_IOPORT_PROBE; ioport++) {
4410 if ((iop = asc_ioport[ioport]) != 0) {
4411 break;
4412 }
4413 }
4414 if (iop) {
4415 ASC_DBG1(1,
4416 "advansys_detect: probing I/O port 0x%x...\n",
4417 iop);
4418 if (check_region(iop, ASC_IOADR_GAP) != 0) {
4419 printk(
4420"AdvanSys SCSI: specified I/O Port 0x%X is busy\n", iop);
4421 /* Don't try this I/O port twice. */
4422 asc_ioport[ioport] = 0;
4423 goto ioport_try_again;
4424 } else if (AscFindSignature(iop) == ASC_FALSE) {
4425 printk(
4426"AdvanSys SCSI: specified I/O Port 0x%X has no adapter\n", iop);
4427 /* Don't try this I/O port twice. */
4428 asc_ioport[ioport] = 0;
4429 goto ioport_try_again;
4430 } else {
4431 /*
4432 * If this isn't an ISA board, then it must be
4433 * a VL board. If currently looking an ISA
4434 * board is being looked for then try for
4435 * another ISA board in 'asc_ioport'.
4436 */
4437 if (asc_bus[bus] == ASC_IS_ISA &&
4438 (AscGetChipVersion(iop, ASC_IS_ISA) &
4439 ASC_CHIP_VER_ISA_BIT) == 0) {
4440 /*
4441 * Don't clear 'asc_ioport[ioport]'. Try
4442 * this board again for VL. Increment
4443 * 'ioport' past this board.
4444 */
4445 ioport++;
4446 goto ioport_try_again;
4447 }
4448 }
4449 /*
4450 * This board appears good, don't try the I/O port
4451 * again by clearing its value. Increment 'ioport'
4452 * for the next iteration.
4453 */
4454 asc_ioport[ioport++] = 0;
4455 }
4456 }
4457#endif /* CONFIG_ISA */
4458 break;
4459
4460 case ASC_IS_EISA:
4461#ifdef CONFIG_ISA
4462 iop = AscSearchIOPortAddr(iop, asc_bus[bus]);
4463#endif /* CONFIG_ISA */
4464 break;
4465
4466 case ASC_IS_PCI:
4467#ifdef CONFIG_PCI
4468 if (pci_init_search == 0) {
4469 int i, j;
4470
4471 pci_init_search = 1;
4472
4473 /* Find all PCI cards. */
4474 while (pci_device_id_cnt < ASC_PCI_DEVICE_ID_CNT) {
4475 if ((pci_devp = pci_find_device(ASC_PCI_VENDORID,
4476 pci_device_id[pci_device_id_cnt], pci_devp)) ==
4477 NULL) {
4478 pci_device_id_cnt++;
4479 } else {
4480 if (pci_enable_device(pci_devp) == 0) {
4481 pci_devicep[pci_card_cnt_max++] = pci_devp;
4482 }
4483 }
4484 }
4485
4486 /*
4487 * Sort PCI cards in ascending order by PCI Bus, Slot,
4488 * and Device Number.
4489 */
4490 for (i = 0; i < pci_card_cnt_max - 1; i++)
4491 {
4492 for (j = i + 1; j < pci_card_cnt_max; j++) {
4493 if ((pci_devicep[j]->bus->number <
4494 pci_devicep[i]->bus->number) ||
4495 ((pci_devicep[j]->bus->number ==
4496 pci_devicep[i]->bus->number) &&
4497 (pci_devicep[j]->devfn <
4498 pci_devicep[i]->devfn))) {
4499 pci_devp = pci_devicep[i];
4500 pci_devicep[i] = pci_devicep[j];
4501 pci_devicep[j] = pci_devp;
4502 }
4503 }
4504 }
4505
4506 pci_card_cnt = 0;
4507 } else {
4508 pci_card_cnt++;
4509 }
4510
4511 if (pci_card_cnt == pci_card_cnt_max) {
4512 iop = 0;
4513 } else {
4514 pci_devp = pci_devicep[pci_card_cnt];
4515
4516 ASC_DBG2(2,
4517 "advansys_detect: devfn %d, bus number %d\n",
4518 pci_devp->devfn, pci_devp->bus->number);
4519 iop = pci_resource_start(pci_devp, 0);
4520 ASC_DBG2(1,
4521 "advansys_detect: vendorID %X, deviceID %X\n",
4522 pci_devp->vendor, pci_devp->device);
4523 ASC_DBG2(2, "advansys_detect: iop %X, irqLine %d\n",
4524 iop, pci_devp->irq);
4525 }
4526 if(pci_devp)
4527 dev = &pci_devp->dev;
4528
4529#endif /* CONFIG_PCI */
4530 break;
4531
4532 default:
4533 ASC_PRINT1("advansys_detect: unknown bus type: %d\n",
4534 asc_bus[bus]);
4535 break;
4536 }
4537 ASC_DBG1(1, "advansys_detect: iop 0x%x\n", iop);
4538
4539 /*
4540 * Adapter not found, try next bus type.
4541 */
4542 if (iop == 0) {
4543 break;
4544 }
4545
4546 /*
4547 * Adapter found.
4548 *
4549 * Register the adapter, get its configuration, and
4550 * initialize it.
4551 */
4552 ASC_DBG(2, "advansys_detect: scsi_register()\n");
4553 shp = scsi_register(tpnt, sizeof(asc_board_t));
4554
4555 if (shp == NULL) {
4556 continue;
4557 }
4558
1da177e4
LT		 4559 /* Save a pointer to the Scsi_Host of each board found. */
4560 asc_host[asc_board_count++] = shp;
4561
4562 /* Initialize private per board data */
4563 boardp = ASC_BOARDP(shp);
4564 memset(boardp, 0, sizeof(asc_board_t));
4565 boardp->id = asc_board_count - 1;
4566
4567 /* Initialize spinlock. */
4568 spin_lock_init(&boardp->lock);
4569
4570 /*
4571 * Handle both narrow and wide boards.
4572 *
4573 * If a Wide board was detected, set the board structure
4574 * wide board flag. Set-up the board structure based on
4575 * the board type.
4576 */
4577#ifdef CONFIG_PCI
4578 if (asc_bus[bus] == ASC_IS_PCI &&
4579 (pci_devp->device == ASC_PCI_DEVICE_ID_2300 ||
4580 pci_devp->device == ASC_PCI_DEVICE_ID_2500 ||
4581 pci_devp->device == ASC_PCI_DEVICE_ID_2700))
4582 {
4583 boardp->flags |= ASC_IS_WIDE_BOARD;
4584 }
4585#endif /* CONFIG_PCI */
4586
4587 if (ASC_NARROW_BOARD(boardp)) {
4588 ASC_DBG(1, "advansys_detect: narrow board\n");
4589 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
4590 asc_dvc_varp->bus_type = asc_bus[bus];
4591 asc_dvc_varp->drv_ptr = boardp;
4592 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
4593 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
4594 asc_dvc_varp->iop_base = iop;
4595 asc_dvc_varp->isr_callback = asc_isr_callback;
4596 } else {
4597 ASC_DBG(1, "advansys_detect: wide board\n");
4598 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
4599 adv_dvc_varp->drv_ptr = boardp;
4600 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
4601 adv_dvc_varp->isr_callback = adv_isr_callback;
4602 adv_dvc_varp->async_callback = adv_async_callback;
4603#ifdef CONFIG_PCI
4604 if (pci_devp->device == ASC_PCI_DEVICE_ID_2300)
4605 {
4606 ASC_DBG(1, "advansys_detect: ASC-3550\n");
4607 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
4608 } else if (pci_devp->device == ASC_PCI_DEVICE_ID_2500)
4609 {
4610 ASC_DBG(1, "advansys_detect: ASC-38C0800\n");
4611 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
4612 } else
4613 {
4614 ASC_DBG(1, "advansys_detect: ASC-38C1600\n");
4615 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
4616 }
4617#endif /* CONFIG_PCI */
4618
4619 /*
4620 * Map the board's registers into virtual memory for
4621 * PCI slave access. Only memory accesses are used to
4622 * access the board's registers.
4623 *
4624 * Note: The PCI register base address is not always
4625 * page aligned, but the address passed to ioremap()
4626 * must be page aligned. It is guaranteed that the
4627 * PCI register base address will not cross a page
4628 * boundary.
4629 */
4630 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
4631 {
4632 iolen = ADV_3550_IOLEN;
4633 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
4634 {
4635 iolen = ADV_38C0800_IOLEN;
4636 } else
4637 {
4638 iolen = ADV_38C1600_IOLEN;
4639 }
4640#ifdef CONFIG_PCI
4641 pci_memory_address = pci_resource_start(pci_devp, 1);
4642 ASC_DBG1(1, "advansys_detect: pci_memory_address: 0x%lx\n",
4643 (ulong) pci_memory_address);
4644 if ((boardp->ioremap_addr =
4645 ioremap(pci_memory_address & PAGE_MASK,
4646 PAGE_SIZE)) == 0) {
4647 ASC_PRINT3(
4648"advansys_detect: board %d: ioremap(%x, %d) returned NULL\n",
4649 boardp->id, pci_memory_address, iolen);
4650 scsi_unregister(shp);
4651 asc_board_count--;
4652 continue;
4653 }
4654 ASC_DBG1(1, "advansys_detect: ioremap_addr: 0x%lx\n",
4655 (ulong) boardp->ioremap_addr);
4656 adv_dvc_varp->iop_base = (AdvPortAddr)
4657 (boardp->ioremap_addr +
4658 (pci_memory_address - (pci_memory_address & PAGE_MASK)));
4659 ASC_DBG1(1, "advansys_detect: iop_base: 0x%lx\n",
4660 adv_dvc_varp->iop_base);
4661#endif /* CONFIG_PCI */
4662
4663 /*
4664 * Even though it isn't used to access wide boards, other
4665 * than for the debug line below, save I/O Port address so
4666 * that it can be reported.
4667 */
4668 boardp->ioport = iop;
4669
4670 ASC_DBG2(1,
4671"advansys_detect: iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
4672 (ushort) inp(iop + 1), (ushort) inpw(iop));
4673 }
4674
4675#ifdef CONFIG_PROC_FS
4676 /*
4677 * Allocate buffer for printing information from
4678 * /proc/scsi/advansys/[0...].
4679 */
4680 if ((boardp->prtbuf =
4681 kmalloc(ASC_PRTBUF_SIZE, GFP_ATOMIC)) == NULL) {
4682 ASC_PRINT3(
4683"advansys_detect: board %d: kmalloc(%d, %d) returned NULL\n",
4684 boardp->id, ASC_PRTBUF_SIZE, GFP_ATOMIC);
4685 scsi_unregister(shp);
4686 asc_board_count--;
4687 continue;
4688 }
4689#endif /* CONFIG_PROC_FS */
4690
4691 if (ASC_NARROW_BOARD(boardp)) {
4692 asc_dvc_varp->cfg->dev = dev;
4693 /*
4694 * Set the board bus type and PCI IRQ before
4695 * calling AscInitGetConfig().
4696 */
4697 switch (asc_dvc_varp->bus_type) {
4698#ifdef CONFIG_ISA
4699 case ASC_IS_ISA:
4700 shp->unchecked_isa_dma = TRUE;
4701 share_irq = FALSE;
4702 break;
4703 case ASC_IS_VL:
4704 shp->unchecked_isa_dma = FALSE;
4705 share_irq = FALSE;
4706 break;
4707 case ASC_IS_EISA:
4708 shp->unchecked_isa_dma = FALSE;
4709 share_irq = TRUE;
4710 break;
4711#endif /* CONFIG_ISA */
4712#ifdef CONFIG_PCI
4713 case ASC_IS_PCI:
4714 shp->irq = asc_dvc_varp->irq_no = pci_devp->irq;
4715 asc_dvc_varp->cfg->pci_slot_info =
4716 ASC_PCI_MKID(pci_devp->bus->number,
4717 PCI_SLOT(pci_devp->devfn),
4718 PCI_FUNC(pci_devp->devfn));
4719 shp->unchecked_isa_dma = FALSE;
4720 share_irq = TRUE;
4721 break;
4722#endif /* CONFIG_PCI */
4723 default:
4724 ASC_PRINT2(
4725"advansys_detect: board %d: unknown adapter type: %d\n",
4726 boardp->id, asc_dvc_varp->bus_type);
4727 shp->unchecked_isa_dma = TRUE;
4728 share_irq = FALSE;
4729 break;
4730 }
4731 } else {
4732 adv_dvc_varp->cfg->dev = dev;
4733 /*
4734 * For Wide boards set PCI information before calling
4735 * AdvInitGetConfig().
4736 */
4737#ifdef CONFIG_PCI
4738 shp->irq = adv_dvc_varp->irq_no = pci_devp->irq;
4739 adv_dvc_varp->cfg->pci_slot_info =
4740 ASC_PCI_MKID(pci_devp->bus->number,
4741 PCI_SLOT(pci_devp->devfn),
4742 PCI_FUNC(pci_devp->devfn));
4743 shp->unchecked_isa_dma = FALSE;
4744 share_irq = TRUE;
4745#endif /* CONFIG_PCI */
4746 }
4747
4748 /*
4749 * Read the board configuration.
4750 */
4751 if (ASC_NARROW_BOARD(boardp)) {
4752 /*
4753 * NOTE: AscInitGetConfig() may change the board's
4754 * bus_type value. The asc_bus[bus] value should no
4755 * longer be used. If the bus_type field must be
4756 * referenced only use the bit-wise AND operator "&".
4757 */
4758 ASC_DBG(2, "advansys_detect: AscInitGetConfig()\n");
4759 switch(ret = AscInitGetConfig(asc_dvc_varp)) {
4760 case 0: /* No error */
4761 break;
4762 case ASC_WARN_IO_PORT_ROTATE:
4763 ASC_PRINT1(
4764"AscInitGetConfig: board %d: I/O port address modified\n",
4765 boardp->id);
4766 break;
4767 case ASC_WARN_AUTO_CONFIG:
4768 ASC_PRINT1(
4769"AscInitGetConfig: board %d: I/O port increment switch enabled\n",
4770 boardp->id);
4771 break;
4772 case ASC_WARN_EEPROM_CHKSUM:
4773 ASC_PRINT1(
4774"AscInitGetConfig: board %d: EEPROM checksum error\n",
4775 boardp->id);
4776 break;
4777 case ASC_WARN_IRQ_MODIFIED:
4778 ASC_PRINT1(
4779"AscInitGetConfig: board %d: IRQ modified\n",
4780 boardp->id);
4781 break;
4782 case ASC_WARN_CMD_QNG_CONFLICT:
4783 ASC_PRINT1(
4784"AscInitGetConfig: board %d: tag queuing enabled w/o disconnects\n",
4785 boardp->id);
4786 break;
4787 default:
4788 ASC_PRINT2(
4789"AscInitGetConfig: board %d: unknown warning: 0x%x\n",
4790 boardp->id, ret);
4791 break;
4792 }
4793 if ((err_code = asc_dvc_varp->err_code) != 0) {
4794 ASC_PRINT3(
4795"AscInitGetConfig: board %d error: init_state 0x%x, err_code 0x%x\n",
4796 boardp->id, asc_dvc_varp->init_state,
4797 asc_dvc_varp->err_code);
4798 }
4799 } else {
4800 ASC_DBG(2, "advansys_detect: AdvInitGetConfig()\n");
4801 if ((ret = AdvInitGetConfig(adv_dvc_varp)) != 0) {
4802 ASC_PRINT2("AdvInitGetConfig: board %d: warning: 0x%x\n",
4803 boardp->id, ret);
4804 }
4805 if ((err_code = adv_dvc_varp->err_code) != 0) {
4806 ASC_PRINT2(
4807"AdvInitGetConfig: board %d error: err_code 0x%x\n",
4808 boardp->id, adv_dvc_varp->err_code);
4809 }
4810 }
4811
4812 if (err_code != 0) {
4813#ifdef CONFIG_PROC_FS
4814 kfree(boardp->prtbuf);
4815#endif /* CONFIG_PROC_FS */
4816 scsi_unregister(shp);
4817 asc_board_count--;
4818 continue;
4819 }
4820
4821 /*
4822 * Save the EEPROM configuration so that it can be displayed
4823 * from /proc/scsi/advansys/[0...].
4824 */
4825 if (ASC_NARROW_BOARD(boardp)) {
4826
4827 ASCEEP_CONFIG *ep;
4828
4829 /*
4830 * Set the adapter's target id bit in the 'init_tidmask' field.
4831 */
4832 boardp->init_tidmask |=
4833 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
4834
4835 /*
4836 * Save EEPROM settings for the board.
4837 */
4838 ep = &boardp->eep_config.asc_eep;
4839
4840 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
4841 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
4842 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
4843 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
4844 ep->start_motor = asc_dvc_varp->start_motor;
4845 ep->cntl = asc_dvc_varp->dvc_cntl;
4846 ep->no_scam = asc_dvc_varp->no_scam;
4847 ep->max_total_qng = asc_dvc_varp->max_total_qng;
4848 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
4849 /* 'max_tag_qng' is set to the same value for every device. */
4850 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
4851 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
4852 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
4853 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
4854 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
4855 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
4856 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
4857
4858 /*
4859 * Modify board configuration.
4860 */
4861 ASC_DBG(2, "advansys_detect: AscInitSetConfig()\n");
4862 switch (ret = AscInitSetConfig(asc_dvc_varp)) {
4863 case 0: /* No error. */
4864 break;
4865 case ASC_WARN_IO_PORT_ROTATE:
4866 ASC_PRINT1(
4867"AscInitSetConfig: board %d: I/O port address modified\n",
4868 boardp->id);
4869 break;
4870 case ASC_WARN_AUTO_CONFIG:
4871 ASC_PRINT1(
4872"AscInitSetConfig: board %d: I/O port increment switch enabled\n",
4873 boardp->id);
4874 break;
4875 case ASC_WARN_EEPROM_CHKSUM:
4876 ASC_PRINT1(
4877"AscInitSetConfig: board %d: EEPROM checksum error\n",
4878 boardp->id);
4879 break;
4880 case ASC_WARN_IRQ_MODIFIED:
4881 ASC_PRINT1(
4882"AscInitSetConfig: board %d: IRQ modified\n",
4883 boardp->id);
4884 break;
4885 case ASC_WARN_CMD_QNG_CONFLICT:
4886 ASC_PRINT1(
4887"AscInitSetConfig: board %d: tag queuing w/o disconnects\n",
4888 boardp->id);
4889 break;
4890 default:
4891 ASC_PRINT2(
4892"AscInitSetConfig: board %d: unknown warning: 0x%x\n",
4893 boardp->id, ret);
4894 break;
4895 }
4896 if (asc_dvc_varp->err_code != 0) {
4897 ASC_PRINT3(
4898"AscInitSetConfig: board %d error: init_state 0x%x, err_code 0x%x\n",
4899 boardp->id, asc_dvc_varp->init_state,
4900 asc_dvc_varp->err_code);
4901#ifdef CONFIG_PROC_FS
4902 kfree(boardp->prtbuf);
4903#endif /* CONFIG_PROC_FS */
4904 scsi_unregister(shp);
4905 asc_board_count--;
4906 continue;
4907 }
4908
4909 /*
4910 * Finish initializing the 'Scsi_Host' structure.
4911 */
4912 /* AscInitSetConfig() will set the IRQ for non-PCI boards. */
4913 if ((asc_dvc_varp->bus_type & ASC_IS_PCI) == 0) {
4914 shp->irq = asc_dvc_varp->irq_no;
4915 }
4916 } else {
4917 ADVEEP_3550_CONFIG *ep_3550;
4918 ADVEEP_38C0800_CONFIG *ep_38C0800;
4919 ADVEEP_38C1600_CONFIG *ep_38C1600;
4920
4921 /*
4922 * Save Wide EEP Configuration Information.
4923 */
4924 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
4925 {
4926 ep_3550 = &boardp->eep_config.adv_3550_eep;
4927
4928 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4929 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
4930 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4931 ep_3550->termination = adv_dvc_varp->cfg->termination;
4932 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
4933 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
4934 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
4935 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
4936 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
4937 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
4938 ep_3550->start_motor = adv_dvc_varp->start_motor;
4939 ep_3550->scsi_reset_delay = adv_dvc_varp->scsi_reset_wait;
4940 ep_3550->serial_number_word1 =
4941 adv_dvc_varp->cfg->serial1;
4942 ep_3550->serial_number_word2 =
4943 adv_dvc_varp->cfg->serial2;
4944 ep_3550->serial_number_word3 =
4945 adv_dvc_varp->cfg->serial3;
4946 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
4947 {
4948 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
4949
4950 ep_38C0800->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4951 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
4952 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4953 ep_38C0800->termination_lvd =
4954 adv_dvc_varp->cfg->termination;
4955 ep_38C0800->disc_enable = adv_dvc_varp->cfg->disc_enable;
4956 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
4957 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
4958 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
4959 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
4960 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
4961 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
4962 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
4963 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
4964 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
4965 ep_38C0800->scsi_reset_delay =
4966 adv_dvc_varp->scsi_reset_wait;
4967 ep_38C0800->serial_number_word1 =
4968 adv_dvc_varp->cfg->serial1;
4969 ep_38C0800->serial_number_word2 =
4970 adv_dvc_varp->cfg->serial2;
4971 ep_38C0800->serial_number_word3 =
4972 adv_dvc_varp->cfg->serial3;
4973 } else
4974 {
4975 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
4976
4977 ep_38C1600->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4978 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
4979 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4980 ep_38C1600->termination_lvd =
4981 adv_dvc_varp->cfg->termination;
4982 ep_38C1600->disc_enable = adv_dvc_varp->cfg->disc_enable;
4983 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
4984 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
4985 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
4986 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
4987 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
4988 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
4989 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
4990 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
4991 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
4992 ep_38C1600->scsi_reset_delay =
4993 adv_dvc_varp->scsi_reset_wait;
4994 ep_38C1600->serial_number_word1 =
4995 adv_dvc_varp->cfg->serial1;
4996 ep_38C1600->serial_number_word2 =
4997 adv_dvc_varp->cfg->serial2;
4998 ep_38C1600->serial_number_word3 =
4999 adv_dvc_varp->cfg->serial3;
5000 }
5001
5002 /*
5003 * Set the adapter's target id bit in the 'init_tidmask' field.
5004 */
5005 boardp->init_tidmask |=
5006 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
5007
5008 /*
5009 * Finish initializing the 'Scsi_Host' structure.
5010 */
5011 shp->irq = adv_dvc_varp->irq_no;
5012 }
5013
5014 /*
5015 * Channels are numbered beginning with 0. For AdvanSys one host
5016 * structure supports one channel. Multi-channel boards have a
5017 * separate host structure for each channel.
5018 */
5019 shp->max_channel = 0;
5020 if (ASC_NARROW_BOARD(boardp)) {
5021 shp->max_id = ASC_MAX_TID + 1;
5022 shp->max_lun = ASC_MAX_LUN + 1;
5023
5024 shp->io_port = asc_dvc_varp->iop_base;
5025 boardp->asc_n_io_port = ASC_IOADR_GAP;
5026 shp->this_id = asc_dvc_varp->cfg->chip_scsi_id;
5027
5028 /* Set maximum number of queues the adapter can handle. */
5029 shp->can_queue = asc_dvc_varp->max_total_qng;
5030 } else {
5031 shp->max_id = ADV_MAX_TID + 1;
5032 shp->max_lun = ADV_MAX_LUN + 1;
5033
5034 /*
5035 * Save the I/O Port address and length even though
5036 * I/O ports are not used to access Wide boards.
5037 * Instead the Wide boards are accessed with
5038 * PCI Memory Mapped I/O.
5039 */
5040 shp->io_port = iop;
5041 boardp->asc_n_io_port = iolen;
5042
5043 shp->this_id = adv_dvc_varp->chip_scsi_id;
5044
5045 /* Set maximum number of queues the adapter can handle. */
5046 shp->can_queue = adv_dvc_varp->max_host_qng;
5047 }
5048
5049 /*
5050 * 'n_io_port' currently is one byte.
5051 *
5052 * Set a value to 'n_io_port', but never referenced it because
5053 * it may be truncated.
5054 */
5055 shp->n_io_port = boardp->asc_n_io_port <= 255 ?
5056 boardp->asc_n_io_port : 255;
5057
5058 /*
5059 * Following v1.3.89, 'cmd_per_lun' is no longer needed
5060 * and should be set to zero.
5061 *
5062 * But because of a bug introduced in v1.3.89 if the driver is
5063 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
5064 * SCSI function 'allocate_device' will panic. To allow the driver
5065 * to work as a module in these kernels set 'cmd_per_lun' to 1.
5066 *
5067 * Note: This is wrong. cmd_per_lun should be set to the depth
5068 * you want on untagged devices always.
5069#ifdef MODULE
5070 */
5071 shp->cmd_per_lun = 1;
5072/* #else
5073 shp->cmd_per_lun = 0;
5074#endif */
5075
5076 /*
5077 * Set the maximum number of scatter-gather elements the
5078 * adapter can handle.
5079 */
5080 if (ASC_NARROW_BOARD(boardp)) {
5081 /*
5082 * Allow two commands with 'sg_tablesize' scatter-gather
5083 * elements to be executed simultaneously. This value is
5084 * the theoretical hardware limit. It may be decreased
5085 * below.
5086 */
5087 shp->sg_tablesize =
5088 (((asc_dvc_varp->max_total_qng - 2) / 2) *
5089 ASC_SG_LIST_PER_Q) + 1;
5090 } else {
5091 shp->sg_tablesize = ADV_MAX_SG_LIST;
5092 }
5093
5094 /*
5095 * The value of 'sg_tablesize' can not exceed the SCSI
5096 * mid-level driver definition of SG_ALL. SG_ALL also
5097 * must not be exceeded, because it is used to define the
5098 * size of the scatter-gather table in 'struct asc_sg_head'.
5099 */
5100 if (shp->sg_tablesize > SG_ALL) {
5101 shp->sg_tablesize = SG_ALL;
5102 }
5103
5104 ASC_DBG1(1, "advansys_detect: sg_tablesize: %d\n",
5105 shp->sg_tablesize);
5106
5107 /* BIOS start address. */
5108 if (ASC_NARROW_BOARD(boardp)) {
5109 shp->base =
5110 ((ulong) AscGetChipBiosAddress(
5111 asc_dvc_varp->iop_base,
5112 asc_dvc_varp->bus_type));
5113 } else {
5114 /*
5115 * Fill-in BIOS board variables. The Wide BIOS saves
5116 * information in LRAM that is used by the driver.
5117 */
5118 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_SIGNATURE,
5119 boardp->bios_signature);
5120 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_VERSION,
5121 boardp->bios_version);
5122 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_CODESEG,
5123 boardp->bios_codeseg);
5124 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_CODELEN,
5125 boardp->bios_codelen);
5126
5127 ASC_DBG2(1,
5128 "advansys_detect: bios_signature 0x%x, bios_version 0x%x\n",
5129 boardp->bios_signature, boardp->bios_version);
5130
5131 ASC_DBG2(1,
5132 "advansys_detect: bios_codeseg 0x%x, bios_codelen 0x%x\n",
5133 boardp->bios_codeseg, boardp->bios_codelen);
5134
5135 /*
5136 * If the BIOS saved a valid signature, then fill in
5137 * the BIOS code segment base address.
5138 */
5139 if (boardp->bios_signature == 0x55AA) {
5140 /*
5141 * Convert x86 realmode code segment to a linear
5142 * address by shifting left 4.
5143 */
5144 shp->base = ((ulong) boardp->bios_codeseg << 4);
5145 } else {
5146 shp->base = 0;
5147 }
5148 }
5149
5150 /*
5151 * Register Board Resources - I/O Port, DMA, IRQ
5152 */
5153
5154 /*
5155 * Register I/O port range.
5156 *
5157 * For Wide boards the I/O ports are not used to access
5158 * the board, but request the region anyway.
5159 *
5160 * 'shp->n_io_port' is not referenced, because it may be truncated.
5161 */
5162 ASC_DBG2(2,
5163 "advansys_detect: request_region port 0x%lx, len 0x%x\n",
5164 (ulong) shp->io_port, boardp->asc_n_io_port);
5165 if (request_region(shp->io_port, boardp->asc_n_io_port,
5166 "advansys") == NULL) {
5167 ASC_PRINT3(
5168"advansys_detect: board %d: request_region() failed, port 0x%lx, len 0x%x\n",
5169 boardp->id, (ulong) shp->io_port, boardp->asc_n_io_port);
5170#ifdef CONFIG_PROC_FS
5171 kfree(boardp->prtbuf);
5172#endif /* CONFIG_PROC_FS */
5173 scsi_unregister(shp);
5174 asc_board_count--;
5175 continue;
5176 }
5177
5178 /* Register DMA Channel for Narrow boards. */
5179 shp->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
5180#ifdef CONFIG_ISA
5181 if (ASC_NARROW_BOARD(boardp)) {
5182 /* Register DMA channel for ISA bus. */
5183 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
5184 shp->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
5185 if ((ret =
5186 request_dma(shp->dma_channel, "advansys")) != 0) {
5187 ASC_PRINT3(
5188"advansys_detect: board %d: request_dma() %d failed %d\n",
5189 boardp->id, shp->dma_channel, ret);
5190 release_region(shp->io_port, boardp->asc_n_io_port);
5191#ifdef CONFIG_PROC_FS
5192 kfree(boardp->prtbuf);
5193#endif /* CONFIG_PROC_FS */
5194 scsi_unregister(shp);
5195 asc_board_count--;
5196 continue;
5197 }
5198 AscEnableIsaDma(shp->dma_channel);
5199 }
5200 }
5201#endif /* CONFIG_ISA */
5202
5203 /* Register IRQ Number. */
5204 ASC_DBG1(2, "advansys_detect: request_irq() %d\n", shp->irq);
5205 /*
5206 * If request_irq() fails with the SA_INTERRUPT flag set,
5207 * then try again without the SA_INTERRUPT flag set. This
5208 * allows IRQ sharing to work even with other drivers that
5209 * do not set the SA_INTERRUPT flag.
5210 *
5211 * If SA_INTERRUPT is not set, then interrupts are enabled
5212 * before the driver interrupt function is called.
5213 */
5214 if (((ret = request_irq(shp->irq, advansys_interrupt,
5215 SA_INTERRUPT | (share_irq == TRUE ? SA_SHIRQ : 0),
5216 "advansys", boardp)) != 0) &&
5217 ((ret = request_irq(shp->irq, advansys_interrupt,
5218 (share_irq == TRUE ? SA_SHIRQ : 0),
5219 "advansys", boardp)) != 0))
5220 {
5221 if (ret == -EBUSY) {
5222 ASC_PRINT2(
5223"advansys_detect: board %d: request_irq(): IRQ 0x%x already in use.\n",
5224 boardp->id, shp->irq);
5225 } else if (ret == -EINVAL) {
5226 ASC_PRINT2(
5227"advansys_detect: board %d: request_irq(): IRQ 0x%x not valid.\n",
5228 boardp->id, shp->irq);
5229 } else {
5230 ASC_PRINT3(
5231"advansys_detect: board %d: request_irq(): IRQ 0x%x failed with %d\n",
5232 boardp->id, shp->irq, ret);
5233 }
5234 release_region(shp->io_port, boardp->asc_n_io_port);
5235 iounmap(boardp->ioremap_addr);
5236 if (shp->dma_channel != NO_ISA_DMA) {
5237 free_dma(shp->dma_channel);
5238 }
5239#ifdef CONFIG_PROC_FS
5240 kfree(boardp->prtbuf);
5241#endif /* CONFIG_PROC_FS */
5242 scsi_unregister(shp);
5243 asc_board_count--;
5244 continue;
5245 }
5246
5247 /*
5248 * Initialize board RISC chip and enable interrupts.
5249 */
5250 if (ASC_NARROW_BOARD(boardp)) {
5251 ASC_DBG(2, "advansys_detect: AscInitAsc1000Driver()\n");
5252 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
5253 err_code = asc_dvc_varp->err_code;
5254
5255 if (warn_code || err_code) {
5256 ASC_PRINT4(
5257"advansys_detect: board %d error: init_state 0x%x, warn 0x%x, error 0x%x\n",
5258 boardp->id, asc_dvc_varp->init_state,
5259 warn_code, err_code);
5260 }
5261 } else {
5262 ADV_CARR_T *carrp;
5263 int req_cnt = 0;
5264 adv_req_t *reqp = NULL;
5265 int sg_cnt = 0;
5266
5267 /*
5268 * Allocate buffer carrier structures. The total size
5269 * is about 4 KB, so allocate all at once.
5270 */
5271 carrp =
5272 (ADV_CARR_T *) kmalloc(ADV_CARRIER_BUFSIZE, GFP_ATOMIC);
5273 ASC_DBG1(1, "advansys_detect: carrp 0x%lx\n", (ulong) carrp);
5274
5275 if (carrp == NULL) {
5276 goto kmalloc_error;
5277 }
5278
5279 /*
5280 * Allocate up to 'max_host_qng' request structures for
5281 * the Wide board. The total size is about 16 KB, so
5282 * allocate all at once. If the allocation fails decrement
5283 * and try again.
5284 */
5285 for (req_cnt = adv_dvc_varp->max_host_qng;
5286 req_cnt > 0; req_cnt--) {
5287
5288 reqp = (adv_req_t *)
5289 kmalloc(sizeof(adv_req_t) * req_cnt, GFP_ATOMIC);
5290
5291 ASC_DBG3(1,
5292 "advansys_detect: reqp 0x%lx, req_cnt %d, bytes %lu\n",
5293 (ulong) reqp, req_cnt,
5294 (ulong) sizeof(adv_req_t) * req_cnt);
5295
5296 if (reqp != NULL) {
5297 break;
5298 }
5299 }
5300 if (reqp == NULL)
5301 {
5302 goto kmalloc_error;
5303 }
5304
5305 /*
5306 * Allocate up to ADV_TOT_SG_BLOCK request structures for
5307 * the Wide board. Each structure is about 136 bytes.
5308 */
5309 boardp->adv_sgblkp = NULL;
5310 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
5311
5312 sgp = (adv_sgblk_t *)
5313 kmalloc(sizeof(adv_sgblk_t), GFP_ATOMIC);
5314
5315 if (sgp == NULL) {
5316 break;
5317 }
5318
5319 sgp->next_sgblkp = boardp->adv_sgblkp;
5320 boardp->adv_sgblkp = sgp;
5321
5322 }
5323 ASC_DBG3(1,
5324 "advansys_detect: sg_cnt %d * %u = %u bytes\n",
5325 sg_cnt, sizeof(adv_sgblk_t),
5326 (unsigned) (sizeof(adv_sgblk_t) * sg_cnt));
5327
5328 /*
5329 * If no request structures or scatter-gather structures could
5330 * be allocated, then return an error. Otherwise continue with
5331 * initialization.
5332 */
5333 kmalloc_error:
5334 if (carrp == NULL)
5335 {
5336 ASC_PRINT1(
5337"advansys_detect: board %d error: failed to kmalloc() carrier buffer.\n",
5338 boardp->id);
5339 err_code = ADV_ERROR;
5340 } else if (reqp == NULL) {
5341 kfree(carrp);
5342 ASC_PRINT1(
5343"advansys_detect: board %d error: failed to kmalloc() adv_req_t buffer.\n",
5344 boardp->id);
5345 err_code = ADV_ERROR;
5346 } else if (boardp->adv_sgblkp == NULL) {
5347 kfree(carrp);
5348 kfree(reqp);
5349 ASC_PRINT1(
5350"advansys_detect: board %d error: failed to kmalloc() adv_sgblk_t buffers.\n",
5351 boardp->id);
5352 err_code = ADV_ERROR;
5353 } else {
5354
5355 /* Save carrier buffer pointer. */
5356 boardp->orig_carrp = carrp;
5357
5358 /*
5359 * Save original pointer for kfree() in case the
5360 * driver is built as a module and can be unloaded.
5361 */
5362 boardp->orig_reqp = reqp;
5363
5364 adv_dvc_varp->carrier_buf = carrp;
5365
5366 /*
5367 * Point 'adv_reqp' to the request structures and
5368 * link them together.
5369 */
5370 req_cnt--;
5371 reqp[req_cnt].next_reqp = NULL;
5372 for (; req_cnt > 0; req_cnt--) {
5373 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
5374 }
5375 boardp->adv_reqp = &reqp[0];
5376
5377 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
5378 {
5379 ASC_DBG(2,
5380 "advansys_detect: AdvInitAsc3550Driver()\n");
5381 warn_code = AdvInitAsc3550Driver(adv_dvc_varp);
5382 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
5383 ASC_DBG(2,
5384 "advansys_detect: AdvInitAsc38C0800Driver()\n");
5385 warn_code = AdvInitAsc38C0800Driver(adv_dvc_varp);
5386 } else {
5387 ASC_DBG(2,
5388 "advansys_detect: AdvInitAsc38C1600Driver()\n");
5389 warn_code = AdvInitAsc38C1600Driver(adv_dvc_varp);
5390 }
5391 err_code = adv_dvc_varp->err_code;
5392
5393 if (warn_code || err_code) {
5394 ASC_PRINT3(
5395"advansys_detect: board %d error: warn 0x%x, error 0x%x\n",
5396 boardp->id, warn_code, err_code);
5397 }
5398 }
5399 }
5400
5401 if (err_code != 0) {
5402 release_region(shp->io_port, boardp->asc_n_io_port);
5403 if (ASC_WIDE_BOARD(boardp)) {
5404 iounmap(boardp->ioremap_addr);
c9475cb0
JJ		 5405 kfree(boardp->orig_carrp);
5406 boardp->orig_carrp = NULL;
1da177e4
LT		 5407 if (boardp->orig_reqp) {
5408 kfree(boardp->orig_reqp);
5409 boardp->orig_reqp = boardp->adv_reqp = NULL;
5410 }
5411 while ((sgp = boardp->adv_sgblkp) != NULL)
5412 {
5413 boardp->adv_sgblkp = sgp->next_sgblkp;
5414 kfree(sgp);
5415 }
5416 }
5417 if (shp->dma_channel != NO_ISA_DMA) {
5418 free_dma(shp->dma_channel);
5419 }
5420#ifdef CONFIG_PROC_FS
5421 kfree(boardp->prtbuf);
5422#endif /* CONFIG_PROC_FS */
5423 free_irq(shp->irq, boardp);
5424 scsi_unregister(shp);
5425 asc_board_count--;
5426 continue;
5427 }
5428 ASC_DBG_PRT_SCSI_HOST(2, shp);
5429 }
5430 }
5431
5432 ASC_DBG1(1, "advansys_detect: done: asc_board_count %d\n", asc_board_count);
5433 return asc_board_count;
5434}
5435
5436/*
5437 * advansys_release()
5438 *
5439 * Release resources allocated for a single AdvanSys adapter.
5440 */
5441int
5442advansys_release(struct Scsi_Host *shp)
5443{
5444 asc_board_t *boardp;
5445
5446 ASC_DBG(1, "advansys_release: begin\n");
5447 boardp = ASC_BOARDP(shp);
5448 free_irq(shp->irq, boardp);
5449 if (shp->dma_channel != NO_ISA_DMA) {
5450 ASC_DBG(1, "advansys_release: free_dma()\n");
5451 free_dma(shp->dma_channel);
5452 }
5453 release_region(shp->io_port, boardp->asc_n_io_port);
5454 if (ASC_WIDE_BOARD(boardp)) {
5455 adv_sgblk_t *sgp = NULL;
5456
5457 iounmap(boardp->ioremap_addr);
c9475cb0
JJ		 5458 kfree(boardp->orig_carrp);
5459 boardp->orig_carrp = NULL;
1da177e4
LT		 5460 if (boardp->orig_reqp) {
5461 kfree(boardp->orig_reqp);
5462 boardp->orig_reqp = boardp->adv_reqp = NULL;
5463 }
5464 while ((sgp = boardp->adv_sgblkp) != NULL)
5465 {
5466 boardp->adv_sgblkp = sgp->next_sgblkp;
5467 kfree(sgp);
5468 }
5469 }
5470#ifdef CONFIG_PROC_FS
5471 ASC_ASSERT(boardp->prtbuf != NULL);
5472 kfree(boardp->prtbuf);
5473#endif /* CONFIG_PROC_FS */
5474 scsi_unregister(shp);
5475 ASC_DBG(1, "advansys_release: end\n");
5476 return 0;
5477}
5478
5479/*
5480 * advansys_info()
5481 *
5482 * Return suitable for printing on the console with the argument
5483 * adapter's configuration information.
5484 *
5485 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
5486 * otherwise the static 'info' array will be overrun.
5487 */
5488const char *
5489advansys_info(struct Scsi_Host *shp)
5490{
5491 static char info[ASC_INFO_SIZE];
5492 asc_board_t *boardp;
5493 ASC_DVC_VAR *asc_dvc_varp;
5494 ADV_DVC_VAR *adv_dvc_varp;
5495 char *busname;
5496 int iolen;
5497 char *widename = NULL;
5498
5499 boardp = ASC_BOARDP(shp);
5500 if (ASC_NARROW_BOARD(boardp)) {
5501 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
5502 ASC_DBG(1, "advansys_info: begin\n");
5503 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
5504 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) == ASC_IS_ISAPNP) {
5505 busname = "ISA PnP";
5506 } else {
5507 busname = "ISA";
5508 }
5509 /* Don't reference 'shp->n_io_port'; It may be truncated. */
5510 sprintf(info,
5511"AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
5512 ASC_VERSION, busname,
5513 (ulong) shp->io_port,
5514 (ulong) shp->io_port + boardp->asc_n_io_port - 1,
5515 shp->irq, shp->dma_channel);
5516 } else {
5517 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
5518 busname = "VL";
5519 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
5520 busname = "EISA";
5521 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
5522 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
5523 == ASC_IS_PCI_ULTRA) {
5524 busname = "PCI Ultra";
5525 } else {
5526 busname = "PCI";
5527 }
5528 } else {
5529 busname = "?";
5530 ASC_PRINT2( "advansys_info: board %d: unknown bus type %d\n",
5531 boardp->id, asc_dvc_varp->bus_type);
5532 }
5533 /* Don't reference 'shp->n_io_port'; It may be truncated. */
5534 sprintf(info,
5535 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
5536 ASC_VERSION, busname,
5537 (ulong) shp->io_port,
5538 (ulong) shp->io_port + boardp->asc_n_io_port - 1,
5539 shp->irq);
5540 }
5541 } else {
5542 /*
5543 * Wide Adapter Information
5544 *
5545 * Memory-mapped I/O is used instead of I/O space to access
5546 * the adapter, but display the I/O Port range. The Memory
5547 * I/O address is displayed through the driver /proc file.
5548 */
5549 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
5550 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
5551 {
5552 iolen = ADV_3550_IOLEN;
5553 widename = "Ultra-Wide";
5554 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
5555 {
5556 iolen = ADV_38C0800_IOLEN;
5557 widename = "Ultra2-Wide";
5558 } else
5559 {
5560 iolen = ADV_38C1600_IOLEN;
5561 widename = "Ultra3-Wide";
5562 }
5563 sprintf(info, "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
5564 ASC_VERSION,
5565 widename,
5566 (ulong) adv_dvc_varp->iop_base,
5567 (ulong) adv_dvc_varp->iop_base + iolen - 1,
5568 shp->irq);
5569 }
5570 ASC_ASSERT(strlen(info) < ASC_INFO_SIZE);
5571 ASC_DBG(1, "advansys_info: end\n");
5572 return info;
5573}
5574
5575/*
5576 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
5577 *
5578 * This function always returns 0. Command return status is saved
5579 * in the 'scp' result field.
5580 */
5581int
5582advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
5583{
5584 struct Scsi_Host *shp;
5585 asc_board_t *boardp;
5586 ulong flags;
5587 struct scsi_cmnd *done_scp;
5588
5589 shp = scp->device->host;
5590 boardp = ASC_BOARDP(shp);
5591 ASC_STATS(shp, queuecommand);
5592
5593 /* host_lock taken by mid-level prior to call but need to protect */
5594 /* against own ISR */
5595 spin_lock_irqsave(&boardp->lock, flags);
5596
5597 /*
5598 * Block new commands while handling a reset or abort request.
5599 */
5600 if (boardp->flags & ASC_HOST_IN_RESET) {
5601 ASC_DBG1(1,
5602 "advansys_queuecommand: scp 0x%lx blocked for reset request\n",
5603 (ulong) scp);
5604 scp->result = HOST_BYTE(DID_RESET);
5605
5606 /*
5607 * Add blocked requests to the board's 'done' queue. The queued
5608 * requests will be completed at the end of the abort or reset
5609 * handling.
5610 */
5611 asc_enqueue(&boardp->done, scp, ASC_BACK);
5612 spin_unlock_irqrestore(&boardp->lock, flags);
5613 return 0;
5614 }
5615
5616 /*
5617 * Attempt to execute any waiting commands for the board.
5618 */
5619 if (!ASC_QUEUE_EMPTY(&boardp->waiting)) {
5620 ASC_DBG(1,
5621 "advansys_queuecommand: before asc_execute_queue() waiting\n");
5622 asc_execute_queue(&boardp->waiting);
5623 }
5624
5625 /*
5626 * Save the function pointer to Linux mid-level 'done' function
5627 * and attempt to execute the command.
5628 *
5629 * If ASC_NOERROR is returned the request has been added to the
5630 * board's 'active' queue and will be completed by the interrupt
5631 * handler.
5632 *
5633 * If ASC_BUSY is returned add the request to the board's per
5634 * target waiting list. This is the first time the request has
5635 * been tried. Add it to the back of the waiting list. It will be
5636 * retried later.
5637 *
5638 * If an error occurred, the request will have been placed on the
5639 * board's 'done' queue and must be completed before returning.
5640 */
5641 scp->scsi_done = done;
5642 switch (asc_execute_scsi_cmnd(scp)) {
5643 case ASC_NOERROR:
5644 break;
5645 case ASC_BUSY:
5646 asc_enqueue(&boardp->waiting, scp, ASC_BACK);
5647 break;
5648 case ASC_ERROR:
5649 default:
5650 done_scp = asc_dequeue_list(&boardp->done, NULL, ASC_TID_ALL);
5651 /* Interrupts could be enabled here. */
5652 asc_scsi_done_list(done_scp);
5653 break;
5654 }
5655 spin_unlock_irqrestore(&boardp->lock, flags);
5656
5657 return 0;
5658}
5659
5660/*
5661 * advansys_reset()
5662 *
5663 * Reset the bus associated with the command 'scp'.
5664 *
5665 * This function runs its own thread. Interrupts must be blocked but
5666 * sleeping is allowed and no locking other than for host structures is
5667 * required. Returns SUCCESS or FAILED.
5668 */
5669int
5670advansys_reset(struct scsi_cmnd *scp)
5671{
5672 struct Scsi_Host *shp;
5673 asc_board_t *boardp;
5674 ASC_DVC_VAR *asc_dvc_varp;
5675 ADV_DVC_VAR *adv_dvc_varp;
5676 ulong flags;
5677 struct scsi_cmnd *done_scp = NULL, *last_scp = NULL;
5678 struct scsi_cmnd *tscp, *new_last_scp;
5679 int status;
5680 int ret = SUCCESS;
5681
5682 ASC_DBG1(1, "advansys_reset: 0x%lx\n", (ulong) scp);
5683
5684#ifdef ADVANSYS_STATS
5685 if (scp->device->host != NULL) {
5686 ASC_STATS(scp->device->host, reset);
5687 }
5688#endif /* ADVANSYS_STATS */
5689
5690 if ((shp = scp->device->host) == NULL) {
5691 scp->result = HOST_BYTE(DID_ERROR);
5692 return FAILED;
5693 }
5694
5695 boardp = ASC_BOARDP(shp);
5696
5697 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset started...\n",
5698 boardp->id);
5699 /*
5700 * Check for re-entrancy.
5701 */
5702 spin_lock_irqsave(&boardp->lock, flags);
5703 if (boardp->flags & ASC_HOST_IN_RESET) {
5704 spin_unlock_irqrestore(&boardp->lock, flags);
5705 return FAILED;
5706 }
5707 boardp->flags |= ASC_HOST_IN_RESET;
5708 spin_unlock_irqrestore(&boardp->lock, flags);
5709
5710 if (ASC_NARROW_BOARD(boardp)) {
5711 /*
5712 * Narrow Board
5713 */
5714 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
5715
5716 /*
5717 * Reset the chip and SCSI bus.
5718 */
5719 ASC_DBG(1, "advansys_reset: before AscInitAsc1000Driver()\n");
5720 status = AscInitAsc1000Driver(asc_dvc_varp);
5721
5722 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
5723 if (asc_dvc_varp->err_code) {
5724 ASC_PRINT2(
5725 "advansys_reset: board %d: SCSI bus reset error: 0x%x\n",
5726 boardp->id, asc_dvc_varp->err_code);
5727 ret = FAILED;
5728 } else if (status) {
5729 ASC_PRINT2(
5730 "advansys_reset: board %d: SCSI bus reset warning: 0x%x\n",
5731 boardp->id, status);
5732 } else {
5733 ASC_PRINT1(
5734 "advansys_reset: board %d: SCSI bus reset successful.\n",
5735 boardp->id);
5736 }
5737
5738 ASC_DBG(1, "advansys_reset: after AscInitAsc1000Driver()\n");
5739 spin_lock_irqsave(&boardp->lock, flags);
5740
5741 } else {
5742 /*
5743 * Wide Board
5744 *
5745 * If the suggest reset bus flags are set, then reset the bus.
5746 * Otherwise only reset the device.
5747 */
5748 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
5749
5750 /*
5751 * Reset the target's SCSI bus.
5752 */
5753 ASC_DBG(1, "advansys_reset: before AdvResetChipAndSB()\n");
5754 switch (AdvResetChipAndSB(adv_dvc_varp)) {
5755 case ASC_TRUE:
5756 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset successful.\n",
5757 boardp->id);
5758 break;
5759 case ASC_FALSE:
5760 default:
5761 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset error.\n",
5762 boardp->id);
5763 ret = FAILED;
5764 break;
5765 }
5766 spin_lock_irqsave(&boardp->lock, flags);
5767 (void) AdvISR(adv_dvc_varp);
5768 }
5769 /* Board lock is held. */
5770
5771 /*
5772 * Dequeue all board 'done' requests. A pointer to the last request
5773 * is returned in 'last_scp'.
5774 */
5775 done_scp = asc_dequeue_list(&boardp->done, &last_scp, ASC_TID_ALL);
5776
5777 /*
5778 * Dequeue all board 'active' requests for all devices and set
5779 * the request status to DID_RESET. A pointer to the last request
5780 * is returned in 'last_scp'.
5781 */
5782 if (done_scp == NULL) {
5783 done_scp = asc_dequeue_list(&boardp->active, &last_scp, ASC_TID_ALL);
5784 for (tscp = done_scp; tscp; tscp = REQPNEXT(tscp)) {
5785 tscp->result = HOST_BYTE(DID_RESET);
5786 }
5787 } else {
5788 /* Append to 'done_scp' at the end with 'last_scp'. */
5789 ASC_ASSERT(last_scp != NULL);
5790 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
5791 &boardp->active, &new_last_scp, ASC_TID_ALL);
5792 if (new_last_scp != NULL) {
5793 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
5794 for (tscp = REQPNEXT(last_scp); tscp; tscp = REQPNEXT(tscp)) {
5795 tscp->result = HOST_BYTE(DID_RESET);
5796 }
5797 last_scp = new_last_scp;
5798 }
5799 }
5800
5801 /*
5802 * Dequeue all 'waiting' requests and set the request status
5803 * to DID_RESET.
5804 */
5805 if (done_scp == NULL) {
5806 done_scp = asc_dequeue_list(&boardp->waiting, &last_scp, ASC_TID_ALL);
5807 for (tscp = done_scp; tscp; tscp = REQPNEXT(tscp)) {
5808 tscp->result = HOST_BYTE(DID_RESET);
5809 }
5810 } else {
5811 /* Append to 'done_scp' at the end with 'last_scp'. */
5812 ASC_ASSERT(last_scp != NULL);
5813 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
5814 &boardp->waiting, &new_last_scp, ASC_TID_ALL);
5815 if (new_last_scp != NULL) {
5816 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
5817 for (tscp = REQPNEXT(last_scp); tscp; tscp = REQPNEXT(tscp)) {
5818 tscp->result = HOST_BYTE(DID_RESET);
5819 }
5820 last_scp = new_last_scp;
5821 }
5822 }
5823
5824 /* Save the time of the most recently completed reset. */
5825 boardp->last_reset = jiffies;
5826
5827 /* Clear reset flag. */
5828 boardp->flags &= ~ASC_HOST_IN_RESET;
5829 spin_unlock_irqrestore(&boardp->lock, flags);
5830
5831 /*
5832 * Complete all the 'done_scp' requests.
5833 */
5834 if (done_scp != NULL) {
5835 asc_scsi_done_list(done_scp);
5836 }
5837
5838 ASC_DBG1(1, "advansys_reset: ret %d\n", ret);
5839
5840 return ret;
5841}
5842
5843/*
5844 * advansys_biosparam()
5845 *
5846 * Translate disk drive geometry if the "BIOS greater than 1 GB"
5847 * support is enabled for a drive.
5848 *
5849 * ip (information pointer) is an int array with the following definition:
5850 * ip[0]: heads
5851 * ip[1]: sectors
5852 * ip[2]: cylinders
5853 */
5854int
5855advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
5856 sector_t capacity, int ip[])
5857{
5858 asc_board_t *boardp;
5859
5860 ASC_DBG(1, "advansys_biosparam: begin\n");
5861 ASC_STATS(sdev->host, biosparam);
5862 boardp = ASC_BOARDP(sdev->host);
5863 if (ASC_NARROW_BOARD(boardp)) {
5864 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
5865 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
5866 ip[0] = 255;
5867 ip[1] = 63;
5868 } else {
5869 ip[0] = 64;
5870 ip[1] = 32;
5871 }
5872 } else {
5873 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
5874 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
5875 ip[0] = 255;
5876 ip[1] = 63;
5877 } else {
5878 ip[0] = 64;
5879 ip[1] = 32;
5880 }
5881 }
5882 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
5883 ASC_DBG(1, "advansys_biosparam: end\n");
5884 return 0;
5885}
5886
5887/*
5888 * advansys_setup()
5889 *
5890 * This function is called from init/main.c at boot time.
5891 * It it passed LILO parameters that can be set from the
5892 * LILO command line or in /etc/lilo.conf.
5893 *
5894 * It is used by the AdvanSys driver to either disable I/O
5895 * port scanning or to limit scanning to 1 - 4 I/O ports.
5896 * Regardless of the option setting EISA and PCI boards
5897 * will still be searched for and detected. This option
5898 * only affects searching for ISA and VL boards.
5899 *
5900 * If ADVANSYS_DEBUG is defined the driver debug level may
5901 * be set using the 5th (ASC_NUM_IOPORT_PROBE + 1) I/O Port.
5902 *
5903 * Examples:
5904 * 1. Eliminate I/O port scanning:
5905 * boot: linux advansys=
5906 * or
5907 * boot: linux advansys=0x0
5908 * 2. Limit I/O port scanning to one I/O port:
5909 * boot: linux advansys=0x110
5910 * 3. Limit I/O port scanning to four I/O ports:
5911 * boot: linux advansys=0x110,0x210,0x230,0x330
5912 * 4. If ADVANSYS_DEBUG, limit I/O port scanning to four I/O ports and
5913 * set the driver debug level to 2.
5914 * boot: linux advansys=0x110,0x210,0x230,0x330,0xdeb2
5915 *
5916 * ints[0] - number of arguments
5917 * ints[1] - first argument
5918 * ints[2] - second argument
5919 * ...
5920 */
5921void __init
5922advansys_setup(char *str, int *ints)
5923{
5924 int i;
5925
5926 if (asc_iopflag == ASC_TRUE) {
5927 printk("AdvanSys SCSI: 'advansys' LILO option may appear only once\n");
5928 return;
5929 }
5930
5931 asc_iopflag = ASC_TRUE;
5932
5933 if (ints[0] > ASC_NUM_IOPORT_PROBE) {
5934#ifdef ADVANSYS_DEBUG
5935 if ((ints[0] == ASC_NUM_IOPORT_PROBE + 1) &&
5936 (ints[ASC_NUM_IOPORT_PROBE + 1] >> 4 == 0xdeb)) {
5937 asc_dbglvl = ints[ASC_NUM_IOPORT_PROBE + 1] & 0xf;
5938 } else {
5939#endif /* ADVANSYS_DEBUG */
5940 printk("AdvanSys SCSI: only %d I/O ports accepted\n",
5941 ASC_NUM_IOPORT_PROBE);
5942#ifdef ADVANSYS_DEBUG
5943 }
5944#endif /* ADVANSYS_DEBUG */
5945 }
5946
5947#ifdef ADVANSYS_DEBUG
5948 ASC_DBG1(1, "advansys_setup: ints[0] %d\n", ints[0]);
5949 for (i = 1; i < ints[0]; i++) {
5950 ASC_DBG2(1, " ints[%d] 0x%x", i, ints[i]);
5951 }
5952 ASC_DBG(1, "\n");
5953#endif /* ADVANSYS_DEBUG */
5954
5955 for (i = 1; i <= ints[0] && i <= ASC_NUM_IOPORT_PROBE; i++) {
5956 asc_ioport[i-1] = ints[i];
5957 ASC_DBG2(1, "advansys_setup: asc_ioport[%d] 0x%x\n",
5958 i - 1, asc_ioport[i-1]);
5959 }
5960}
5961
5962
5963/*
5964 * --- Loadable Driver Support
5965 */
5966
5967static struct scsi_host_template driver_template = {
5968 .proc_name = "advansys",
5969#ifdef CONFIG_PROC_FS
5970 .proc_info = advansys_proc_info,
5971#endif
5972 .name = "advansys",
5973 .detect = advansys_detect,
5974 .release = advansys_release,
5975 .info = advansys_info,
5976 .queuecommand = advansys_queuecommand,
5977 .eh_bus_reset_handler = advansys_reset,
5978 .bios_param = advansys_biosparam,
5979 .slave_configure = advansys_slave_configure,
5980 /*
5981 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
5982 * must be set. The flag will be cleared in advansys_detect for non-ISA
5983 * adapters. Refer to the comment in scsi_module.c for more information.
5984 */
5985 .unchecked_isa_dma = 1,
5986 /*
5987 * All adapters controlled by this driver are capable of large
5988 * scatter-gather lists. According to the mid-level SCSI documentation
5989 * this obviates any performance gain provided by setting
5990 * 'use_clustering'. But empirically while CPU utilization is increased
5991 * by enabling clustering, I/O throughput increases as well.
5992 */
5993 .use_clustering = ENABLE_CLUSTERING,
5994};
5995#include "scsi_module.c"
5996
5997
5998/*
5999 * --- Miscellaneous Driver Functions
6000 */
6001
6002/*
6003 * First-level interrupt handler.
6004 *
6005 * 'dev_id' is a pointer to the interrupting adapter's asc_board_t. Because
6006 * all boards are currently checked for interrupts on each interrupt, 'dev_id'
6007 * is not referenced. 'dev_id' could be used to identify an interrupt passed
6008 * to the AdvanSys driver which is for a device sharing an interrupt with
6009 * an AdvanSys adapter.
6010 */
6011STATIC irqreturn_t
6012advansys_interrupt(int irq, void *dev_id, struct pt_regs *regs)
6013{
6014 ulong flags;
6015 int i;
6016 asc_board_t *boardp;
6017 struct scsi_cmnd *done_scp = NULL, *last_scp = NULL;
6018 struct scsi_cmnd *new_last_scp;
6019 struct Scsi_Host *shp;
6020
6021 ASC_DBG(1, "advansys_interrupt: begin\n");
6022
6023 /*
6024 * Check for interrupts on all boards.
6025 * AscISR() will call asc_isr_callback().
6026 */
6027 for (i = 0; i < asc_board_count; i++) {
6028 shp = asc_host[i];
6029 boardp = ASC_BOARDP(shp);
6030 ASC_DBG2(2, "advansys_interrupt: i %d, boardp 0x%lx\n",
6031 i, (ulong) boardp);
6032 spin_lock_irqsave(&boardp->lock, flags);
6033 if (ASC_NARROW_BOARD(boardp)) {
6034 /*
6035 * Narrow Board
6036 */
6037 if (AscIsIntPending(shp->io_port)) {
6038 ASC_STATS(shp, interrupt);
6039 ASC_DBG(1, "advansys_interrupt: before AscISR()\n");
6040 AscISR(&boardp->dvc_var.asc_dvc_var);
6041 }
6042 } else {
6043 /*
6044 * Wide Board
6045 */
6046 ASC_DBG(1, "advansys_interrupt: before AdvISR()\n");
6047 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
6048 ASC_STATS(shp, interrupt);
6049 }
6050 }
6051
6052 /*
6053 * Start waiting requests and create a list of completed requests.
6054 *
6055 * If a reset request is being performed for the board, the reset
6056 * handler will complete pending requests after it has completed.
6057 */
6058 if ((boardp->flags & ASC_HOST_IN_RESET) == 0) {
6059 ASC_DBG2(1, "advansys_interrupt: done_scp 0x%lx, last_scp 0x%lx\n",
6060 (ulong) done_scp, (ulong) last_scp);
6061
6062 /* Start any waiting commands for the board. */
6063 if (!ASC_QUEUE_EMPTY(&boardp->waiting)) {
6064 ASC_DBG(1, "advansys_interrupt: before asc_execute_queue()\n");
6065 asc_execute_queue(&boardp->waiting);
6066 }
6067
6068 /*
6069 * Add to the list of requests that must be completed.
6070 *
6071 * 'done_scp' will always be NULL on the first iteration
6072 * of this loop. 'last_scp' is set at the same time as
6073 * 'done_scp'.
6074 */
6075 if (done_scp == NULL) {
6076 done_scp = asc_dequeue_list(&boardp->done, &last_scp,
6077 ASC_TID_ALL);
6078 } else {
6079 ASC_ASSERT(last_scp != NULL);
6080 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
6081 &boardp->done, &new_last_scp, ASC_TID_ALL);
6082 if (new_last_scp != NULL) {
6083 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
6084 last_scp = new_last_scp;
6085 }
6086 }
6087 }
6088 spin_unlock_irqrestore(&boardp->lock, flags);
6089 }
6090
6091 /*
6092 * If interrupts were enabled on entry, then they
6093 * are now enabled here.
6094 *
6095 * Complete all requests on the done list.
6096 */
6097
6098 asc_scsi_done_list(done_scp);
6099
6100 ASC_DBG(1, "advansys_interrupt: end\n");
6101 return IRQ_HANDLED;
6102}
6103
6104/*
6105 * Set the number of commands to queue per device for the
6106 * specified host adapter.
6107 */
6108STATIC int
6109advansys_slave_configure(struct scsi_device *device)
6110{
6111 asc_board_t *boardp;
6112
6113 boardp = ASC_BOARDP(device->host);
6114 boardp->flags |= ASC_SELECT_QUEUE_DEPTHS;
6115 /*
6116 * Save a pointer to the device and set its initial/maximum
6117 * queue depth. Only save the pointer for a lun0 dev though.
6118 */
6119 if(device->lun == 0)
6120 boardp->device[device->id] = device;
6121 if(device->tagged_supported) {
6122 if (ASC_NARROW_BOARD(boardp)) {
6123 scsi_adjust_queue_depth(device, MSG_ORDERED_TAG,
6124 boardp->dvc_var.asc_dvc_var.max_dvc_qng[device->id]);
6125 } else {
6126 scsi_adjust_queue_depth(device, MSG_ORDERED_TAG,
6127 boardp->dvc_var.adv_dvc_var.max_dvc_qng);
6128 }
6129 } else {
6130 scsi_adjust_queue_depth(device, 0, device->host->cmd_per_lun);
6131 }
6132 ASC_DBG4(1, "advansys_slave_configure: device 0x%lx, boardp 0x%lx, id %d, depth %d\n",
6133 (ulong) device, (ulong) boardp, device->id, device->queue_depth);
6134 return 0;
6135}
6136
6137/*
6138 * Complete all requests on the singly linked list pointed
6139 * to by 'scp'.
6140 *
6141 * Interrupts can be enabled on entry.
6142 */
6143STATIC void
6144asc_scsi_done_list(struct scsi_cmnd *scp)
6145{
6146 struct scsi_cmnd *tscp;
6147
6148 ASC_DBG(2, "asc_scsi_done_list: begin\n");
6149 while (scp != NULL) {
6150 asc_board_t *boardp;
6151 struct device *dev;
6152
6153 ASC_DBG1(3, "asc_scsi_done_list: scp 0x%lx\n", (ulong) scp);
6154 tscp = REQPNEXT(scp);
6155 scp->host_scribble = NULL;
6156
6157 boardp = ASC_BOARDP(scp->device->host);
6158
6159 if (ASC_NARROW_BOARD(boardp))
6160 dev = boardp->dvc_cfg.asc_dvc_cfg.dev;
6161 else
6162 dev = boardp->dvc_cfg.adv_dvc_cfg.dev;
6163
6164 if (scp->use_sg)
6165 dma_unmap_sg(dev, (struct scatterlist *)scp->request_buffer,
6166 scp->use_sg, scp->sc_data_direction);
6167 else if (scp->request_bufflen)
6168 dma_unmap_single(dev, scp->SCp.dma_handle,
6169 scp->request_bufflen, scp->sc_data_direction);
6170
6171 ASC_STATS(scp->device->host, done);
6172 ASC_ASSERT(scp->scsi_done != NULL);
6173
6174 scp->scsi_done(scp);
6175
6176 scp = tscp;
6177 }
6178 ASC_DBG(2, "asc_scsi_done_list: done\n");
6179 return;
6180}
6181
6182/*
6183 * Execute a single 'Scsi_Cmnd'.
6184 *
6185 * The function 'done' is called when the request has been completed.
6186 *
6187 * Scsi_Cmnd:
6188 *
6189 * host - board controlling device
6190 * device - device to send command
6191 * target - target of device
6192 * lun - lun of device
6193 * cmd_len - length of SCSI CDB
6194 * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
6195 * use_sg - if non-zero indicates scatter-gather request with use_sg elements
6196 *
6197 * if (use_sg == 0) {
6198 * request_buffer - buffer address for request
6199 * request_bufflen - length of request buffer
6200 * } else {
6201 * request_buffer - pointer to scatterlist structure
6202 * }
6203 *
6204 * sense_buffer - sense command buffer
6205 *
6206 * result (4 bytes of an int):
6207 * Byte Meaning
6208 * 0 SCSI Status Byte Code
6209 * 1 SCSI One Byte Message Code
6210 * 2 Host Error Code
6211 * 3 Mid-Level Error Code
6212 *
6213 * host driver fields:
6214 * SCp - Scsi_Pointer used for command processing status
6215 * scsi_done - used to save caller's done function
6216 * host_scribble - used for pointer to another struct scsi_cmnd
6217 *
6218 * If this function returns ASC_NOERROR the request has been enqueued
6219 * on the board's 'active' queue and will be completed from the
6220 * interrupt handler.
6221 *
6222 * If this function returns ASC_NOERROR the request has been enqueued
6223 * on the board's 'done' queue and must be completed by the caller.
6224 *
6225 * If ASC_BUSY is returned the request will be enqueued by the
6226 * caller on the target's waiting queue and re-tried later.
6227 */
6228STATIC int
6229asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
6230{
6231 asc_board_t *boardp;
6232 ASC_DVC_VAR *asc_dvc_varp;
6233 ADV_DVC_VAR *adv_dvc_varp;
6234 ADV_SCSI_REQ_Q *adv_scsiqp;
6235 struct scsi_device *device;
6236 int ret;
6237
6238 ASC_DBG2(1, "asc_execute_scsi_cmnd: scp 0x%lx, done 0x%lx\n",
6239 (ulong) scp, (ulong) scp->scsi_done);
6240
6241 boardp = ASC_BOARDP(scp->device->host);
6242 device = boardp->device[scp->device->id];
6243
6244 if (ASC_NARROW_BOARD(boardp)) {
6245 /*
6246 * Build and execute Narrow Board request.
6247 */
6248
6249 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
6250
6251 /*
6252 * Build Asc Library request structure using the
6253 * global structures 'asc_scsi_req' and 'asc_sg_head'.
6254 *
6255 * If an error is returned, then the request has been
6256 * queued on the board done queue. It will be completed
6257 * by the caller.
6258 *
6259 * asc_build_req() can not return ASC_BUSY.
6260 */
6261 if (asc_build_req(boardp, scp) == ASC_ERROR) {
6262 ASC_STATS(scp->device->host, build_error);
6263 return ASC_ERROR;
6264 }
6265
6266 /*
6267 * Execute the command. If there is no error, add the command
6268 * to the active queue.
6269 */
6270 switch (ret = AscExeScsiQueue(asc_dvc_varp, &asc_scsi_q)) {
6271 case ASC_NOERROR:
6272 ASC_STATS(scp->device->host, exe_noerror);
6273 /*
6274 * Increment monotonically increasing per device successful
6275 * request counter. Wrapping doesn't matter.
6276 */
6277 boardp->reqcnt[scp->device->id]++;
6278 asc_enqueue(&boardp->active, scp, ASC_BACK);
6279 ASC_DBG(1,
6280 "asc_execute_scsi_cmnd: AscExeScsiQueue(), ASC_NOERROR\n");
6281 break;
6282 case ASC_BUSY:
6283 /*
6284 * Caller will enqueue request on the target's waiting queue
6285 * and retry later.
6286 */
6287 ASC_STATS(scp->device->host, exe_busy);
6288 break;
6289 case ASC_ERROR:
6290 ASC_PRINT2(
6291"asc_execute_scsi_cmnd: board %d: AscExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
6292 boardp->id, asc_dvc_varp->err_code);
6293 ASC_STATS(scp->device->host, exe_error);
6294 scp->result = HOST_BYTE(DID_ERROR);
6295 asc_enqueue(&boardp->done, scp, ASC_BACK);
6296 break;
6297 default:
6298 ASC_PRINT2(
6299"asc_execute_scsi_cmnd: board %d: AscExeScsiQueue() unknown, err_code 0x%x\n",
6300 boardp->id, asc_dvc_varp->err_code);
6301 ASC_STATS(scp->device->host, exe_unknown);
6302 scp->result = HOST_BYTE(DID_ERROR);
6303 asc_enqueue(&boardp->done, scp, ASC_BACK);
6304 break;
6305 }
6306 } else {
6307 /*
6308 * Build and execute Wide Board request.
6309 */
6310 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
6311
6312 /*
6313 * Build and get a pointer to an Adv Library request structure.
6314 *
6315 * If the request is successfully built then send it below,
6316 * otherwise return with an error.
6317 */
6318 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
6319 case ASC_NOERROR:
6320 ASC_DBG(3, "asc_execute_scsi_cmnd: adv_build_req ASC_NOERROR\n");
6321 break;
6322 case ASC_BUSY:
6323 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req ASC_BUSY\n");
6324 /*
6325 * If busy is returned the request has not been enqueued.
6326 * It will be enqueued by the caller on the target's waiting
6327 * queue and retried later.
6328 *
6329 * The asc_stats fields 'adv_build_noreq' and 'adv_build_nosg'
6330 * count wide board busy conditions. They are updated in
6331 * adv_build_req and adv_get_sglist, respectively.
6332 */
6333 return ASC_BUSY;
6334 case ASC_ERROR:
6335 /*
6336 * If an error is returned, then the request has been
6337 * queued on the board done queue. It will be completed
6338 * by the caller.
6339 */
6340 default:
6341 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req ASC_ERROR\n");
6342 ASC_STATS(scp->device->host, build_error);
6343 return ASC_ERROR;
6344 }
6345
6346 /*
6347 * Execute the command. If there is no error, add the command
6348 * to the active queue.
6349 */
6350 switch (ret = AdvExeScsiQueue(adv_dvc_varp, adv_scsiqp)) {
6351 case ASC_NOERROR:
6352 ASC_STATS(scp->device->host, exe_noerror);
6353 /*
6354 * Increment monotonically increasing per device successful
6355 * request counter. Wrapping doesn't matter.
6356 */
6357 boardp->reqcnt[scp->device->id]++;
6358 asc_enqueue(&boardp->active, scp, ASC_BACK);
6359 ASC_DBG(1,
6360 "asc_execute_scsi_cmnd: AdvExeScsiQueue(), ASC_NOERROR\n");
6361 break;
6362 case ASC_BUSY:
6363 /*
6364 * Caller will enqueue request on the target's waiting queue
6365 * and retry later.
6366 */
6367 ASC_STATS(scp->device->host, exe_busy);
6368 break;
6369 case ASC_ERROR:
6370 ASC_PRINT2(
6371"asc_execute_scsi_cmnd: board %d: AdvExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
6372 boardp->id, adv_dvc_varp->err_code);
6373 ASC_STATS(scp->device->host, exe_error);
6374 scp->result = HOST_BYTE(DID_ERROR);
6375 asc_enqueue(&boardp->done, scp, ASC_BACK);
6376 break;
6377 default:
6378 ASC_PRINT2(
6379"asc_execute_scsi_cmnd: board %d: AdvExeScsiQueue() unknown, err_code 0x%x\n",
6380 boardp->id, adv_dvc_varp->err_code);
6381 ASC_STATS(scp->device->host, exe_unknown);
6382 scp->result = HOST_BYTE(DID_ERROR);
6383 asc_enqueue(&boardp->done, scp, ASC_BACK);
6384 break;
6385 }
6386 }
6387
6388 ASC_DBG(1, "asc_execute_scsi_cmnd: end\n");
6389 return ret;
6390}
6391
6392/*
6393 * Build a request structure for the Asc Library (Narrow Board).
6394 *
6395 * The global structures 'asc_scsi_q' and 'asc_sg_head' are
6396 * used to build the request.
6397 *
6398 * If an error occurs, then queue the request on the board done
6399 * queue and return ASC_ERROR.
6400 */
6401STATIC int
6402asc_build_req(asc_board_t *boardp, struct scsi_cmnd *scp)
6403{
6404 struct device *dev = boardp->dvc_cfg.asc_dvc_cfg.dev;
6405
6406 /*
6407 * Mutually exclusive access is required to 'asc_scsi_q' and
6408 * 'asc_sg_head' until after the request is started.
6409 */
6410 memset(&asc_scsi_q, 0, sizeof(ASC_SCSI_Q));
6411
6412 /*
6413 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
6414 */
6415 asc_scsi_q.q2.srb_ptr = ASC_VADDR_TO_U32(scp);
6416
6417 /*
6418 * Build the ASC_SCSI_Q request.
6419 *
6420 * For narrow boards a CDB length maximum of 12 bytes
6421 * is supported.
6422 */
6423 if (scp->cmd_len > ASC_MAX_CDB_LEN) {
6424 ASC_PRINT3(
6425"asc_build_req: board %d: cmd_len %d > ASC_MAX_CDB_LEN %d\n",
6426 boardp->id, scp->cmd_len, ASC_MAX_CDB_LEN);
6427 scp->result = HOST_BYTE(DID_ERROR);
6428 asc_enqueue(&boardp->done, scp, ASC_BACK);
6429 return ASC_ERROR;
6430 }
6431 asc_scsi_q.cdbptr = &scp->cmnd[0];
6432 asc_scsi_q.q2.cdb_len = scp->cmd_len;
6433 asc_scsi_q.q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
6434 asc_scsi_q.q1.target_lun = scp->device->lun;
6435 asc_scsi_q.q2.target_ix = ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
6436 asc_scsi_q.q1.sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
6437 asc_scsi_q.q1.sense_len = sizeof(scp->sense_buffer);
6438
6439 /*
6440 * If there are any outstanding requests for the current target,
6441 * then every 255th request send an ORDERED request. This heuristic
6442 * tries to retain the benefit of request sorting while preventing
6443 * request starvation. 255 is the max number of tags or pending commands
6444 * a device may have outstanding.
6445 *
6446 * The request count is incremented below for every successfully
6447 * started request.
6448 *
6449 */
6450 if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
6451 (boardp->reqcnt[scp->device->id] % 255) == 0) {
6452 asc_scsi_q.q2.tag_code = MSG_ORDERED_TAG;
6453 } else {
6454 asc_scsi_q.q2.tag_code = MSG_SIMPLE_TAG;
6455 }
6456
6457 /*
6458 * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
6459 * buffer command.
6460 */
6461 if (scp->use_sg == 0) {
6462 /*
6463 * CDB request of single contiguous buffer.
6464 */
6465 ASC_STATS(scp->device->host, cont_cnt);
6466 scp->SCp.dma_handle = scp->request_bufflen ?
6467 dma_map_single(dev, scp->request_buffer,
6468 scp->request_bufflen, scp->sc_data_direction) : 0;
6469 asc_scsi_q.q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
6470 asc_scsi_q.q1.data_cnt = cpu_to_le32(scp->request_bufflen);
6471 ASC_STATS_ADD(scp->device->host, cont_xfer,
6472 ASC_CEILING(scp->request_bufflen, 512));
6473 asc_scsi_q.q1.sg_queue_cnt = 0;
6474 asc_scsi_q.sg_head = NULL;
6475 } else {
6476 /*
6477 * CDB scatter-gather request list.
6478 */
6479 int sgcnt;
6480 int use_sg;
6481 struct scatterlist *slp;
6482
6483 slp = (struct scatterlist *)scp->request_buffer;
6484 use_sg = dma_map_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6485
6486 if (use_sg > scp->device->host->sg_tablesize) {
6487 ASC_PRINT3(
6488"asc_build_req: board %d: use_sg %d > sg_tablesize %d\n",
6489 boardp->id, use_sg, scp->device->host->sg_tablesize);
6490 dma_unmap_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6491 scp->result = HOST_BYTE(DID_ERROR);
6492 asc_enqueue(&boardp->done, scp, ASC_BACK);
6493 return ASC_ERROR;
6494 }
6495
6496 ASC_STATS(scp->device->host, sg_cnt);
6497
6498 /*
6499 * Use global ASC_SG_HEAD structure and set the ASC_SCSI_Q
6500 * structure to point to it.
6501 */
6502 memset(&asc_sg_head, 0, sizeof(ASC_SG_HEAD));
6503
6504 asc_scsi_q.q1.cntl |= QC_SG_HEAD;
6505 asc_scsi_q.sg_head = &asc_sg_head;
6506 asc_scsi_q.q1.data_cnt = 0;
6507 asc_scsi_q.q1.data_addr = 0;
6508 /* This is a byte value, otherwise it would need to be swapped. */
6509 asc_sg_head.entry_cnt = asc_scsi_q.q1.sg_queue_cnt = use_sg;
6510 ASC_STATS_ADD(scp->device->host, sg_elem, asc_sg_head.entry_cnt);
6511
6512 /*
6513 * Convert scatter-gather list into ASC_SG_HEAD list.
6514 */
6515 for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
6516 asc_sg_head.sg_list[sgcnt].addr = cpu_to_le32(sg_dma_address(slp));
6517 asc_sg_head.sg_list[sgcnt].bytes = cpu_to_le32(sg_dma_len(slp));
6518 ASC_STATS_ADD(scp->device->host, sg_xfer, ASC_CEILING(sg_dma_len(slp), 512));
6519 }
6520 }
6521
6522 ASC_DBG_PRT_ASC_SCSI_Q(2, &asc_scsi_q);
6523 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
6524
6525 return ASC_NOERROR;
6526}
6527
6528/*
6529 * Build a request structure for the Adv Library (Wide Board).
6530 *
6531 * If an adv_req_t can not be allocated to issue the request,
6532 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
6533 *
6534 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
6535 * microcode for DMA addresses or math operations are byte swapped
6536 * to little-endian order.
6537 */
6538STATIC int
6539adv_build_req(asc_board_t *boardp, struct scsi_cmnd *scp,
6540 ADV_SCSI_REQ_Q **adv_scsiqpp)
6541{
6542 adv_req_t *reqp;
6543 ADV_SCSI_REQ_Q *scsiqp;
6544 int i;
6545 int ret;
6546 struct device *dev = boardp->dvc_cfg.adv_dvc_cfg.dev;
6547
6548 /*
6549 * Allocate an adv_req_t structure from the board to execute
6550 * the command.
6551 */
6552 if (boardp->adv_reqp == NULL) {
6553 ASC_DBG(1, "adv_build_req: no free adv_req_t\n");
6554 ASC_STATS(scp->device->host, adv_build_noreq);
6555 return ASC_BUSY;
6556 } else {
6557 reqp = boardp->adv_reqp;
6558 boardp->adv_reqp = reqp->next_reqp;
6559 reqp->next_reqp = NULL;
6560 }
6561
6562 /*
6563 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
6564 */
6565 scsiqp = (ADV_SCSI_REQ_Q *) ADV_32BALIGN(&reqp->scsi_req_q);
6566
6567 /*
6568 * Initialize the structure.
6569 */
6570 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
6571
6572 /*
6573 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
6574 */
6575 scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
6576
6577 /*
6578 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
6579 */
6580 reqp->cmndp = scp;
6581
6582 /*
6583 * Build the ADV_SCSI_REQ_Q request.
6584 */
6585
6586 /*
6587 * Set CDB length and copy it to the request structure.
6588 * For wide boards a CDB length maximum of 16 bytes
6589 * is supported.
6590 */
6591 if (scp->cmd_len > ADV_MAX_CDB_LEN) {
6592 ASC_PRINT3(
6593"adv_build_req: board %d: cmd_len %d > ADV_MAX_CDB_LEN %d\n",
6594 boardp->id, scp->cmd_len, ADV_MAX_CDB_LEN);
6595 scp->result = HOST_BYTE(DID_ERROR);
6596 asc_enqueue(&boardp->done, scp, ASC_BACK);
6597 return ASC_ERROR;
6598 }
6599 scsiqp->cdb_len = scp->cmd_len;
6600 /* Copy first 12 CDB bytes to cdb[]. */
6601 for (i = 0; i < scp->cmd_len && i < 12; i++) {
6602 scsiqp->cdb[i] = scp->cmnd[i];
6603 }
6604 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
6605 for (; i < scp->cmd_len; i++) {
6606 scsiqp->cdb16[i - 12] = scp->cmnd[i];
6607 }
6608
6609 scsiqp->target_id = scp->device->id;
6610 scsiqp->target_lun = scp->device->lun;
6611
6612 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
6613 scsiqp->sense_len = sizeof(scp->sense_buffer);
6614
6615 /*
6616 * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
6617 * buffer command.
6618 */
6619
6620 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
6621 scsiqp->vdata_addr = scp->request_buffer;
6622 scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
6623
6624 if (scp->use_sg == 0) {
6625 /*
6626 * CDB request of single contiguous buffer.
6627 */
6628 reqp->sgblkp = NULL;
6629 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
6630 if (scp->request_bufflen) {
6631 scsiqp->vdata_addr = scp->request_buffer;
6632 scp->SCp.dma_handle =
6633 dma_map_single(dev, scp->request_buffer,
6634 scp->request_bufflen, scp->sc_data_direction);
6635 } else {
6636 scsiqp->vdata_addr = 0;
6637 scp->SCp.dma_handle = 0;
6638 }
6639 scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
6640 scsiqp->sg_list_ptr = NULL;
6641 scsiqp->sg_real_addr = 0;
6642 ASC_STATS(scp->device->host, cont_cnt);
6643 ASC_STATS_ADD(scp->device->host, cont_xfer,
6644 ASC_CEILING(scp->request_bufflen, 512));
6645 } else {
6646 /*
6647 * CDB scatter-gather request list.
6648 */
6649 struct scatterlist *slp;
6650 int use_sg;
6651
6652 slp = (struct scatterlist *)scp->request_buffer;
6653 use_sg = dma_map_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6654
6655 if (use_sg > ADV_MAX_SG_LIST) {
6656 ASC_PRINT3(
6657"adv_build_req: board %d: use_sg %d > ADV_MAX_SG_LIST %d\n",
6658 boardp->id, use_sg, scp->device->host->sg_tablesize);
6659 dma_unmap_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6660 scp->result = HOST_BYTE(DID_ERROR);
6661 asc_enqueue(&boardp->done, scp, ASC_BACK);
6662
6663 /*
6664 * Free the 'adv_req_t' structure by adding it back to the
6665 * board free list.
6666 */
6667 reqp->next_reqp = boardp->adv_reqp;
6668 boardp->adv_reqp = reqp;
6669
6670 return ASC_ERROR;
6671 }
6672
6673 if ((ret = adv_get_sglist(boardp, reqp, scp, use_sg)) != ADV_SUCCESS) {
6674 /*
6675 * Free the adv_req_t structure by adding it back to the
6676 * board free list.
6677 */
6678 reqp->next_reqp = boardp->adv_reqp;
6679 boardp->adv_reqp = reqp;
6680
6681 return ret;
6682 }
6683
6684 ASC_STATS(scp->device->host, sg_cnt);
6685 ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
6686 }
6687
6688 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6689 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
6690
6691 *adv_scsiqpp = scsiqp;
6692
6693 return ASC_NOERROR;
6694}
6695
6696/*
6697 * Build scatter-gather list for Adv Library (Wide Board).
6698 *
6699 * Additional ADV_SG_BLOCK structures will need to be allocated
6700 * if the total number of scatter-gather elements exceeds
6701 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
6702 * assumed to be physically contiguous.
6703 *
6704 * Return:
6705 * ADV_SUCCESS(1) - SG List successfully created
6706 * ADV_ERROR(-1) - SG List creation failed
6707 */
6708STATIC int
6709adv_get_sglist(asc_board_t *boardp, adv_req_t *reqp, struct scsi_cmnd *scp, int use_sg)
6710{
6711 adv_sgblk_t *sgblkp;
6712 ADV_SCSI_REQ_Q *scsiqp;
6713 struct scatterlist *slp;
6714 int sg_elem_cnt;
6715 ADV_SG_BLOCK *sg_block, *prev_sg_block;
6716 ADV_PADDR sg_block_paddr;
6717 int i;
6718
6719 scsiqp = (ADV_SCSI_REQ_Q *) ADV_32BALIGN(&reqp->scsi_req_q);
6720 slp = (struct scatterlist *) scp->request_buffer;
6721 sg_elem_cnt = use_sg;
6722 prev_sg_block = NULL;
6723 reqp->sgblkp = NULL;
6724
6725 do
6726 {
6727 /*
6728 * Allocate a 'adv_sgblk_t' structure from the board free
6729 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
6730 * (15) scatter-gather elements.
6731 */
6732 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
6733 ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n");
6734 ASC_STATS(scp->device->host, adv_build_nosg);
6735
6736 /*
6737 * Allocation failed. Free 'adv_sgblk_t' structures already
6738 * allocated for the request.
6739 */
6740 while ((sgblkp = reqp->sgblkp) != NULL)
6741 {
6742 /* Remove 'sgblkp' from the request list. */
6743 reqp->sgblkp = sgblkp->next_sgblkp;
6744
6745 /* Add 'sgblkp' to the board free list. */
6746 sgblkp->next_sgblkp = boardp->adv_sgblkp;
6747 boardp->adv_sgblkp = sgblkp;
6748 }
6749 return ASC_BUSY;
6750 } else {
6751 /* Complete 'adv_sgblk_t' board allocation. */
6752 boardp->adv_sgblkp = sgblkp->next_sgblkp;
6753 sgblkp->next_sgblkp = NULL;
6754
6755 /*
6756 * Get 8 byte aligned virtual and physical addresses for
6757 * the allocated ADV_SG_BLOCK structure.
6758 */
6759 sg_block = (ADV_SG_BLOCK *) ADV_8BALIGN(&sgblkp->sg_block);
6760 sg_block_paddr = virt_to_bus(sg_block);
6761
6762 /*
6763 * Check if this is the first 'adv_sgblk_t' for the request.
6764 */
6765 if (reqp->sgblkp == NULL)
6766 {
6767 /* Request's first scatter-gather block. */
6768 reqp->sgblkp = sgblkp;
6769
6770 /*
6771 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
6772 * address pointers.
6773 */
6774 scsiqp->sg_list_ptr = sg_block;
6775 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
6776 } else
6777 {
6778 /* Request's second or later scatter-gather block. */
6779 sgblkp->next_sgblkp = reqp->sgblkp;
6780 reqp->sgblkp = sgblkp;
6781
6782 /*
6783 * Point the previous ADV_SG_BLOCK structure to
6784 * the newly allocated ADV_SG_BLOCK structure.
6785 */
6786 ASC_ASSERT(prev_sg_block != NULL);
6787 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
6788 }
6789 }
6790
6791 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++)
6792 {
6793 sg_block->sg_list[i].sg_addr = cpu_to_le32(sg_dma_address(slp));
6794 sg_block->sg_list[i].sg_count = cpu_to_le32(sg_dma_len(slp));
6795 ASC_STATS_ADD(scp->device->host, sg_xfer, ASC_CEILING(sg_dma_len(slp), 512));
6796
6797 if (--sg_elem_cnt == 0)
6798 { /* Last ADV_SG_BLOCK and scatter-gather entry. */
6799 sg_block->sg_cnt = i + 1;
6800 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
6801 return ADV_SUCCESS;
6802 }
6803 slp++;
6804 }
6805 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
6806 prev_sg_block = sg_block;
6807 }
6808 while (1);
6809 /* NOTREACHED */
6810}
6811
6812/*
6813 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6814 *
6815 * Interrupt callback function for the Narrow SCSI Asc Library.
6816 */
6817STATIC void
6818asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6819{
6820 asc_board_t *boardp;
6821 struct scsi_cmnd *scp;
6822 struct Scsi_Host *shp;
6823 int i;
6824
6825 ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp 0x%lx, qdonep 0x%lx\n",
6826 (ulong) asc_dvc_varp, (ulong) qdonep);
6827 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6828
6829 /*
6830 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
6831 * command that has been completed.
6832 */
6833 scp = (struct scsi_cmnd *) ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
6834 ASC_DBG1(1, "asc_isr_callback: scp 0x%lx\n", (ulong) scp);
6835
6836 if (scp == NULL) {
6837 ASC_PRINT("asc_isr_callback: scp is NULL\n");
6838 return;
6839 }
6840 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6841
6842 /*
6843 * If the request's host pointer is not valid, display a
6844 * message and return.
6845 */
6846 shp = scp->device->host;
6847 for (i = 0; i < asc_board_count; i++) {
6848 if (asc_host[i] == shp) {
6849 break;
6850 }
6851 }
6852 if (i == asc_board_count) {
6853 ASC_PRINT2(
6854 "asc_isr_callback: scp 0x%lx has bad host pointer, host 0x%lx\n",
6855 (ulong) scp, (ulong) shp);
6856 return;
6857 }
6858
6859 ASC_STATS(shp, callback);
6860 ASC_DBG1(1, "asc_isr_callback: shp 0x%lx\n", (ulong) shp);
6861
6862 /*
6863 * If the request isn't found on the active queue, it may
6864 * have been removed to handle a reset request.
6865 * Display a message and return.
6866 */
6867 boardp = ASC_BOARDP(shp);
6868 ASC_ASSERT(asc_dvc_varp == &boardp->dvc_var.asc_dvc_var);
6869 if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
6870 ASC_PRINT2(
6871 "asc_isr_callback: board %d: scp 0x%lx not on active queue\n",
6872 boardp->id, (ulong) scp);
6873 return;
6874 }
6875
6876 /*
6877 * 'qdonep' contains the command's ending status.
6878 */
6879 switch (qdonep->d3.done_stat) {
6880 case QD_NO_ERROR:
6881 ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n");
6882 scp->result = 0;
6883
6884 /*
6885 * If an INQUIRY command completed successfully, then call
6886 * the AscInquiryHandling() function to set-up the device.
6887 */
6888 if (scp->cmnd[0] == INQUIRY && scp->device->lun == 0 &&
6889 (scp->request_bufflen - qdonep->remain_bytes) >= 8)
6890 {
6891 AscInquiryHandling(asc_dvc_varp, scp->device->id & 0x7,
6892 (ASC_SCSI_INQUIRY *) scp->request_buffer);
6893 }
6894
6895 /*
6896 * Check for an underrun condition.
6897 *
6898 * If there was no error and an underrun condition, then
6899 * then return the number of underrun bytes.
6900 */
6901 if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
6902 qdonep->remain_bytes <= scp->request_bufflen) {
6903 ASC_DBG1(1, "asc_isr_callback: underrun condition %u bytes\n",
6904 (unsigned) qdonep->remain_bytes);
6905 scp->resid = qdonep->remain_bytes;
6906 }
6907 break;
6908
6909 case QD_WITH_ERROR:
6910 ASC_DBG(2, "asc_isr_callback: QD_WITH_ERROR\n");
6911 switch (qdonep->d3.host_stat) {
6912 case QHSTA_NO_ERROR:
6913 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
6914 ASC_DBG(2, "asc_isr_callback: SAM_STAT_CHECK_CONDITION\n");
6915 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6916 sizeof(scp->sense_buffer));
6917 /*
6918 * Note: The 'status_byte()' macro used by target drivers
6919 * defined in scsi.h shifts the status byte returned by
6920 * host drivers right by 1 bit. This is why target drivers
6921 * also use right shifted status byte definitions. For
6922 * instance target drivers use CHECK_CONDITION, defined to
6923 * 0x1, instead of the SCSI defined check condition value
6924 * of 0x2. Host drivers are supposed to return the status
6925 * byte as it is defined by SCSI.
6926 */
6927 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6928 STATUS_BYTE(qdonep->d3.scsi_stat);
6929 } else {
6930 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
6931 }
6932 break;
6933
6934 default:
6935 /* QHSTA error occurred */
6936 ASC_DBG1(1, "asc_isr_callback: host_stat 0x%x\n",
6937 qdonep->d3.host_stat);
6938 scp->result = HOST_BYTE(DID_BAD_TARGET);
6939 break;
6940 }
6941 break;
6942
6943 case QD_ABORTED_BY_HOST:
6944 ASC_DBG(1, "asc_isr_callback: QD_ABORTED_BY_HOST\n");
6945 scp->result = HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.scsi_msg) |
6946 STATUS_BYTE(qdonep->d3.scsi_stat);
6947 break;
6948
6949 default:
6950 ASC_DBG1(1, "asc_isr_callback: done_stat 0x%x\n", qdonep->d3.done_stat);
6951 scp->result = HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.scsi_msg) |
6952 STATUS_BYTE(qdonep->d3.scsi_stat);
6953 break;
6954 }
6955
6956 /*
6957 * If the 'init_tidmask' bit isn't already set for the target and the
6958 * current request finished normally, then set the bit for the target
6959 * to indicate that a device is present.
6960 */
6961 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6962 qdonep->d3.done_stat == QD_NO_ERROR &&
6963 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
6964 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6965 }
6966
6967 /*
6968 * Because interrupts may be enabled by the 'struct scsi_cmnd' done
6969 * function, add the command to the end of the board's done queue.
6970 * The done function for the command will be called from
6971 * advansys_interrupt().
6972 */
6973 asc_enqueue(&boardp->done, scp, ASC_BACK);
6974
6975 return;
6976}
6977
6978/*
6979 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6980 *
6981 * Callback function for the Wide SCSI Adv Library.
6982 */
6983STATIC void
6984adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6985{
6986 asc_board_t *boardp;
6987 adv_req_t *reqp;
6988 adv_sgblk_t *sgblkp;
6989 struct scsi_cmnd *scp;
6990 struct Scsi_Host *shp;
6991 int i;
6992 ADV_DCNT resid_cnt;
6993
6994
6995 ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
6996 (ulong) adv_dvc_varp, (ulong) scsiqp);
6997 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6998
6999 /*
7000 * Get the adv_req_t structure for the command that has been
7001 * completed. The adv_req_t structure actually contains the
7002 * completed ADV_SCSI_REQ_Q structure.
7003 */
7004 reqp = (adv_req_t *) ADV_U32_TO_VADDR(scsiqp->srb_ptr);
7005 ASC_DBG1(1, "adv_isr_callback: reqp 0x%lx\n", (ulong) reqp);
7006 if (reqp == NULL) {
7007 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
7008 return;
7009 }
7010
7011 /*
7012 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
7013 * command that has been completed.
7014 *
7015 * Note: The adv_req_t request structure and adv_sgblk_t structure,
7016 * if any, are dropped, because a board structure pointer can not be
7017 * determined.
7018 */
7019 scp = reqp->cmndp;
7020 ASC_DBG1(1, "adv_isr_callback: scp 0x%lx\n", (ulong) scp);
7021 if (scp == NULL) {
7022 ASC_PRINT("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
7023 return;
7024 }
7025 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7026
7027 /*
7028 * If the request's host pointer is not valid, display a message
7029 * and return.
7030 */
7031 shp = scp->device->host;
7032 for (i = 0; i < asc_board_count; i++) {
7033 if (asc_host[i] == shp) {
7034 break;
7035 }
7036 }
7037 /*
7038 * Note: If the host structure is not found, the adv_req_t request
7039 * structure and adv_sgblk_t structure, if any, is dropped.
7040 */
7041 if (i == asc_board_count) {
7042 ASC_PRINT2(
7043 "adv_isr_callback: scp 0x%lx has bad host pointer, host 0x%lx\n",
7044 (ulong) scp, (ulong) shp);
7045 return;
7046 }
7047
7048 ASC_STATS(shp, callback);
7049 ASC_DBG1(1, "adv_isr_callback: shp 0x%lx\n", (ulong) shp);
7050
7051 /*
7052 * If the request isn't found on the active queue, it may have been
7053 * removed to handle a reset request. Display a message and return.
7054 *
7055 * Note: Because the structure may still be in use don't attempt
7056 * to free the adv_req_t and adv_sgblk_t, if any, structures.
7057 */
7058 boardp = ASC_BOARDP(shp);
7059 ASC_ASSERT(adv_dvc_varp == &boardp->dvc_var.adv_dvc_var);
7060 if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
7061 ASC_PRINT2(
7062 "adv_isr_callback: board %d: scp 0x%lx not on active queue\n",
7063 boardp->id, (ulong) scp);
7064 return;
7065 }
7066
7067 /*
7068 * 'done_status' contains the command's ending status.
7069 */
7070 switch (scsiqp->done_status) {
7071 case QD_NO_ERROR:
7072 ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n");
7073 scp->result = 0;
7074
7075 /*
7076 * Check for an underrun condition.
7077 *
7078 * If there was no error and an underrun condition, then
7079 * then return the number of underrun bytes.
7080 */
7081 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
7082 if (scp->request_bufflen != 0 && resid_cnt != 0 &&
7083 resid_cnt <= scp->request_bufflen) {
7084 ASC_DBG1(1, "adv_isr_callback: underrun condition %lu bytes\n",
7085 (ulong) resid_cnt);
7086 scp->resid = resid_cnt;
7087 }
7088 break;
7089
7090 case QD_WITH_ERROR:
7091 ASC_DBG(2, "adv_isr_callback: QD_WITH_ERROR\n");
7092 switch (scsiqp->host_status) {
7093 case QHSTA_NO_ERROR:
7094 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
7095 ASC_DBG(2, "adv_isr_callback: SAM_STAT_CHECK_CONDITION\n");
7096 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7097 sizeof(scp->sense_buffer));
7098 /*
7099 * Note: The 'status_byte()' macro used by target drivers
7100 * defined in scsi.h shifts the status byte returned by
7101 * host drivers right by 1 bit. This is why target drivers
7102 * also use right shifted status byte definitions. For
7103 * instance target drivers use CHECK_CONDITION, defined to
7104 * 0x1, instead of the SCSI defined check condition value
7105 * of 0x2. Host drivers are supposed to return the status
7106 * byte as it is defined by SCSI.
7107 */
7108 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7109 STATUS_BYTE(scsiqp->scsi_status);
7110 } else {
7111 scp->result = STATUS_BYTE(scsiqp->scsi_status);
7112 }
7113 break;
7114
7115 default:
7116 /* Some other QHSTA error occurred. */
7117 ASC_DBG1(1, "adv_isr_callback: host_status 0x%x\n",
7118 scsiqp->host_status);
7119 scp->result = HOST_BYTE(DID_BAD_TARGET);
7120 break;
7121 }
7122 break;
7123
7124 case QD_ABORTED_BY_HOST:
7125 ASC_DBG(1, "adv_isr_callback: QD_ABORTED_BY_HOST\n");
7126 scp->result = HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
7127 break;
7128
7129 default:
7130 ASC_DBG1(1, "adv_isr_callback: done_status 0x%x\n", scsiqp->done_status);
7131 scp->result = HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
7132 break;
7133 }
7134
7135 /*
7136 * If the 'init_tidmask' bit isn't already set for the target and the
7137 * current request finished normally, then set the bit for the target
7138 * to indicate that a device is present.
7139 */
7140 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7141 scsiqp->done_status == QD_NO_ERROR &&
7142 scsiqp->host_status == QHSTA_NO_ERROR) {
7143 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7144 }
7145
7146 /*
7147 * Because interrupts may be enabled by the 'struct scsi_cmnd' done
7148 * function, add the command to the end of the board's done queue.
7149 * The done function for the command will be called from
7150 * advansys_interrupt().
7151 */
7152 asc_enqueue(&boardp->done, scp, ASC_BACK);
7153
7154 /*
7155 * Free all 'adv_sgblk_t' structures allocated for the request.
7156 */
7157 while ((sgblkp = reqp->sgblkp) != NULL)
7158 {
7159 /* Remove 'sgblkp' from the request list. */
7160 reqp->sgblkp = sgblkp->next_sgblkp;
7161
7162 /* Add 'sgblkp' to the board free list. */
7163 sgblkp->next_sgblkp = boardp->adv_sgblkp;
7164 boardp->adv_sgblkp = sgblkp;
7165 }
7166
7167 /*
7168 * Free the adv_req_t structure used with the command by adding
7169 * it back to the board free list.
7170 */
7171 reqp->next_reqp = boardp->adv_reqp;
7172 boardp->adv_reqp = reqp;
7173
7174 ASC_DBG(1, "adv_isr_callback: done\n");
7175
7176 return;
7177}
7178
7179/*
7180 * adv_async_callback() - Adv Library asynchronous event callback function.
7181 */
7182STATIC void
7183adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
7184{
7185 switch (code)
7186 {
7187 case ADV_ASYNC_SCSI_BUS_RESET_DET:
7188 /*
7189 * The firmware detected a SCSI Bus reset.
7190 */
7191 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_SCSI_BUS_RESET_DET\n");
7192 break;
7193
7194 case ADV_ASYNC_RDMA_FAILURE:
7195 /*
7196 * Handle RDMA failure by resetting the SCSI Bus and
7197 * possibly the chip if it is unresponsive. Log the error
7198 * with a unique code.
7199 */
7200 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_RDMA_FAILURE\n");
7201 AdvResetChipAndSB(adv_dvc_varp);
7202 break;
7203
7204 case ADV_HOST_SCSI_BUS_RESET:
7205 /*
7206 * Host generated SCSI bus reset occurred.
7207 */
7208 ASC_DBG(0, "adv_async_callback: ADV_HOST_SCSI_BUS_RESET\n");
7209 break;
7210
7211 default:
7212 ASC_DBG1(0, "DvcAsyncCallBack: unknown code 0x%x\n", code);
7213 break;
7214 }
7215}
7216
7217/*
7218 * Add a 'REQP' to the end of specified queue. Set 'tidmask'
7219 * to indicate a command is queued for the device.
7220 *
7221 * 'flag' may be either ASC_FRONT or ASC_BACK.
7222 *
7223 * 'REQPNEXT(reqp)' returns reqp's next pointer.
7224 */
7225STATIC void
7226asc_enqueue(asc_queue_t *ascq, REQP reqp, int flag)
7227{
7228 int tid;
7229
7230 ASC_DBG3(3, "asc_enqueue: ascq 0x%lx, reqp 0x%lx, flag %d\n",
7231 (ulong) ascq, (ulong) reqp, flag);
7232 ASC_ASSERT(reqp != NULL);
7233 ASC_ASSERT(flag == ASC_FRONT || flag == ASC_BACK);
7234 tid = REQPTID(reqp);
7235 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7236 if (flag == ASC_FRONT) {
7237 reqp->host_scribble = (unsigned char *)ascq->q_first[tid];
7238 ascq->q_first[tid] = reqp;
7239 /* If the queue was empty, set the last pointer. */
7240 if (ascq->q_last[tid] == NULL) {
7241 ascq->q_last[tid] = reqp;
7242 }
7243 } else { /* ASC_BACK */
7244 if (ascq->q_last[tid] != NULL) {
7245 ascq->q_last[tid]->host_scribble = (unsigned char *)reqp;
7246 }
7247 ascq->q_last[tid] = reqp;
7248 reqp->host_scribble = NULL;
7249 /* If the queue was empty, set the first pointer. */
7250 if (ascq->q_first[tid] == NULL) {
7251 ascq->q_first[tid] = reqp;
7252 }
7253 }
7254 /* The queue has at least one entry, set its bit. */
7255 ascq->q_tidmask |= ADV_TID_TO_TIDMASK(tid);
7256#ifdef ADVANSYS_STATS
7257 /* Maintain request queue statistics. */
7258 ascq->q_tot_cnt[tid]++;
7259 ascq->q_cur_cnt[tid]++;
7260 if (ascq->q_cur_cnt[tid] > ascq->q_max_cnt[tid]) {
7261 ascq->q_max_cnt[tid] = ascq->q_cur_cnt[tid];
7262 ASC_DBG2(2, "asc_enqueue: new q_max_cnt[%d] %d\n",
7263 tid, ascq->q_max_cnt[tid]);
7264 }
7265 REQPTIME(reqp) = REQTIMESTAMP();
7266#endif /* ADVANSYS_STATS */
7267 ASC_DBG1(3, "asc_enqueue: reqp 0x%lx\n", (ulong) reqp);
7268 return;
7269}
7270
7271/*
7272 * Return first queued 'REQP' on the specified queue for
7273 * the specified target device. Clear the 'tidmask' bit for
7274 * the device if no more commands are left queued for it.
7275 *
7276 * 'REQPNEXT(reqp)' returns reqp's next pointer.
7277 */
7278STATIC REQP
7279asc_dequeue(asc_queue_t *ascq, int tid)
7280{
7281 REQP reqp;
7282
7283 ASC_DBG2(3, "asc_dequeue: ascq 0x%lx, tid %d\n", (ulong) ascq, tid);
7284 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7285 if ((reqp = ascq->q_first[tid]) != NULL) {
7286 ASC_ASSERT(ascq->q_tidmask & ADV_TID_TO_TIDMASK(tid));
7287 ascq->q_first[tid] = REQPNEXT(reqp);
7288 /* If the queue is empty, clear its bit and the last pointer. */
7289 if (ascq->q_first[tid] == NULL) {
7290 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7291 ASC_ASSERT(ascq->q_last[tid] == reqp);
7292 ascq->q_last[tid] = NULL;
7293 }
7294#ifdef ADVANSYS_STATS
7295 /* Maintain request queue statistics. */
7296 ascq->q_cur_cnt[tid]--;
7297 ASC_ASSERT(ascq->q_cur_cnt[tid] >= 0);
7298 REQTIMESTAT("asc_dequeue", ascq, reqp, tid);
7299#endif /* ADVANSYS_STATS */
7300 }
7301 ASC_DBG1(3, "asc_dequeue: reqp 0x%lx\n", (ulong) reqp);
7302 return reqp;
7303}
7304
7305/*
7306 * Return a pointer to a singly linked list of all the requests queued
7307 * for 'tid' on the 'asc_queue_t' pointed to by 'ascq'.
7308 *
7309 * If 'lastpp' is not NULL, '*lastpp' will be set to point to the
7310 * the last request returned in the singly linked list.
7311 *
7312 * 'tid' should either be a valid target id or if it is ASC_TID_ALL,
7313 * then all queued requests are concatenated into one list and
7314 * returned.
7315 *
7316 * Note: If 'lastpp' is used to append a new list to the end of
7317 * an old list, only change the old list last pointer if '*lastpp'
7318 * (or the function return value) is not NULL, i.e. use a temporary
7319 * variable for 'lastpp' and check its value after the function return
7320 * before assigning it to the list last pointer.
7321 *
7322 * Unfortunately collecting queuing time statistics adds overhead to
7323 * the function that isn't inherent to the function's algorithm.
7324 */
7325STATIC REQP
7326asc_dequeue_list(asc_queue_t *ascq, REQP *lastpp, int tid)
7327{
7328 REQP firstp, lastp;
7329 int i;
7330
7331 ASC_DBG2(3, "asc_dequeue_list: ascq 0x%lx, tid %d\n", (ulong) ascq, tid);
7332 ASC_ASSERT((tid == ASC_TID_ALL) || (tid >= 0 && tid <= ADV_MAX_TID));
7333
7334 /*
7335 * If 'tid' is not ASC_TID_ALL, return requests only for
7336 * the specified 'tid'. If 'tid' is ASC_TID_ALL, return all
7337 * requests for all tids.
7338 */
7339 if (tid != ASC_TID_ALL) {
7340 /* Return all requests for the specified 'tid'. */
7341 if ((ascq->q_tidmask & ADV_TID_TO_TIDMASK(tid)) == 0) {
7342 /* List is empty; Set first and last return pointers to NULL. */
7343 firstp = lastp = NULL;
7344 } else {
7345 firstp = ascq->q_first[tid];
7346 lastp = ascq->q_last[tid];
7347 ascq->q_first[tid] = ascq->q_last[tid] = NULL;
7348 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7349#ifdef ADVANSYS_STATS
7350 {
7351 REQP reqp;
7352 ascq->q_cur_cnt[tid] = 0;
7353 for (reqp = firstp; reqp; reqp = REQPNEXT(reqp)) {
7354 REQTIMESTAT("asc_dequeue_list", ascq, reqp, tid);
7355 }
7356 }
7357#endif /* ADVANSYS_STATS */
7358 }
7359 } else {
7360 /* Return all requests for all tids. */
7361 firstp = lastp = NULL;
7362 for (i = 0; i <= ADV_MAX_TID; i++) {
7363 if (ascq->q_tidmask & ADV_TID_TO_TIDMASK(i)) {
7364 if (firstp == NULL) {
7365 firstp = ascq->q_first[i];
7366 lastp = ascq->q_last[i];
7367 } else {
7368 ASC_ASSERT(lastp != NULL);
7369 lastp->host_scribble = (unsigned char *)ascq->q_first[i];
7370 lastp = ascq->q_last[i];
7371 }
7372 ascq->q_first[i] = ascq->q_last[i] = NULL;
7373 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7374#ifdef ADVANSYS_STATS
7375 ascq->q_cur_cnt[i] = 0;
7376#endif /* ADVANSYS_STATS */
7377 }
7378 }
7379#ifdef ADVANSYS_STATS
7380 {
7381 REQP reqp;
7382 for (reqp = firstp; reqp; reqp = REQPNEXT(reqp)) {
7383 REQTIMESTAT("asc_dequeue_list", ascq, reqp, reqp->device->id);
7384 }
7385 }
7386#endif /* ADVANSYS_STATS */
7387 }
7388 if (lastpp) {
7389 *lastpp = lastp;
7390 }
7391 ASC_DBG1(3, "asc_dequeue_list: firstp 0x%lx\n", (ulong) firstp);
7392 return firstp;
7393}
7394
7395/*
7396 * Remove the specified 'REQP' from the specified queue for
7397 * the specified target device. Clear the 'tidmask' bit for the
7398 * device if no more commands are left queued for it.
7399 *
7400 * 'REQPNEXT(reqp)' returns reqp's the next pointer.
7401 *
7402 * Return ASC_TRUE if the command was found and removed,
7403 * otherwise return ASC_FALSE.
7404 */
7405STATIC int
7406asc_rmqueue(asc_queue_t *ascq, REQP reqp)
7407{
7408 REQP currp, prevp;
7409 int tid;
7410 int ret = ASC_FALSE;
7411
7412 ASC_DBG2(3, "asc_rmqueue: ascq 0x%lx, reqp 0x%lx\n",
7413 (ulong) ascq, (ulong) reqp);
7414 ASC_ASSERT(reqp != NULL);
7415
7416 tid = REQPTID(reqp);
7417 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7418
7419 /*
7420 * Handle the common case of 'reqp' being the first
7421 * entry on the queue.
7422 */
7423 if (reqp == ascq->q_first[tid]) {
7424 ret = ASC_TRUE;
7425 ascq->q_first[tid] = REQPNEXT(reqp);
7426 /* If the queue is now empty, clear its bit and the last pointer. */
7427 if (ascq->q_first[tid] == NULL) {
7428 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7429 ASC_ASSERT(ascq->q_last[tid] == reqp);
7430 ascq->q_last[tid] = NULL;
7431 }
7432 } else if (ascq->q_first[tid] != NULL) {
7433 ASC_ASSERT(ascq->q_last[tid] != NULL);
7434 /*
7435 * Because the case of 'reqp' being the first entry has been
7436 * handled above and it is known the queue is not empty, if
7437 * 'reqp' is found on the queue it is guaranteed the queue will
7438 * not become empty and that 'q_first[tid]' will not be changed.
7439 *
7440 * Set 'prevp' to the first entry, 'currp' to the second entry,
7441 * and search for 'reqp'.
7442 */
7443 for (prevp = ascq->q_first[tid], currp = REQPNEXT(prevp);
7444 currp; prevp = currp, currp = REQPNEXT(currp)) {
7445 if (currp == reqp) {
7446 ret = ASC_TRUE;
7447 prevp->host_scribble = (unsigned char *)REQPNEXT(currp);
7448 reqp->host_scribble = NULL;
7449 if (ascq->q_last[tid] == reqp) {
7450 ascq->q_last[tid] = prevp;
7451 }
7452 break;
7453 }
7454 }
7455 }
7456#ifdef ADVANSYS_STATS
7457 /* Maintain request queue statistics. */
7458 if (ret == ASC_TRUE) {
7459 ascq->q_cur_cnt[tid]--;
7460 REQTIMESTAT("asc_rmqueue", ascq, reqp, tid);
7461 }
7462 ASC_ASSERT(ascq->q_cur_cnt[tid] >= 0);
7463#endif /* ADVANSYS_STATS */
7464 ASC_DBG2(3, "asc_rmqueue: reqp 0x%lx, ret %d\n", (ulong) reqp, ret);
7465 return ret;
7466}
7467
7468/*
7469 * Execute as many queued requests as possible for the specified queue.
7470 *
7471 * Calls asc_execute_scsi_cmnd() to execute a REQP/struct scsi_cmnd.
7472 */
7473STATIC void
7474asc_execute_queue(asc_queue_t *ascq)
7475{
7476 ADV_SCSI_BIT_ID_TYPE scan_tidmask;
7477 REQP reqp;
7478 int i;
7479
7480 ASC_DBG1(1, "asc_execute_queue: ascq 0x%lx\n", (ulong) ascq);
7481 /*
7482 * Execute queued commands for devices attached to
7483 * the current board in round-robin fashion.
7484 */
7485 scan_tidmask = ascq->q_tidmask;
7486 do {
7487 for (i = 0; i <= ADV_MAX_TID; i++) {
7488 if (scan_tidmask & ADV_TID_TO_TIDMASK(i)) {
7489 if ((reqp = asc_dequeue(ascq, i)) == NULL) {
7490 scan_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7491 } else if (asc_execute_scsi_cmnd((struct scsi_cmnd *) reqp)
7492 == ASC_BUSY) {
7493 scan_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7494 /*
7495 * The request returned ASC_BUSY. Enqueue at the front of
7496 * target's waiting list to maintain correct ordering.
7497 */
7498 asc_enqueue(ascq, reqp, ASC_FRONT);
7499 }
7500 }
7501 }
7502 } while (scan_tidmask);
7503 return;
7504}
7505
7506#ifdef CONFIG_PROC_FS
7507/*
7508 * asc_prt_board_devices()
7509 *
7510 * Print driver information for devices attached to the board.
7511 *
7512 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7513 * cf. asc_prt_line().
7514 *
7515 * Return the number of characters copied into 'cp'. No more than
7516 * 'cplen' characters will be copied to 'cp'.
7517 */
7518STATIC int
7519asc_prt_board_devices(struct Scsi_Host *shp, char *cp, int cplen)
7520{
7521 asc_board_t *boardp;
7522 int leftlen;
7523 int totlen;
7524 int len;
7525 int chip_scsi_id;
7526 int i;
7527
7528 boardp = ASC_BOARDP(shp);
7529 leftlen = cplen;
7530 totlen = len = 0;
7531
7532 len = asc_prt_line(cp, leftlen,
7533"\nDevice Information for AdvanSys SCSI Host %d:\n", shp->host_no);
7534 ASC_PRT_NEXT();
7535
7536 if (ASC_NARROW_BOARD(boardp)) {
7537 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
7538 } else {
7539 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
7540 }
7541
7542 len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
7543 ASC_PRT_NEXT();
7544 for (i = 0; i <= ADV_MAX_TID; i++) {
7545 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
7546 len = asc_prt_line(cp, leftlen, " %X,", i);
7547 ASC_PRT_NEXT();
7548 }
7549 }
7550 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
7551 ASC_PRT_NEXT();
7552
7553 return totlen;
7554}
7555
7556/*
7557 * Display Wide Board BIOS Information.
7558 */
7559STATIC int
7560asc_prt_adv_bios(struct Scsi_Host *shp, char *cp, int cplen)
7561{
7562 asc_board_t *boardp;
7563 int leftlen;
7564 int totlen;
7565 int len;
7566 ushort major, minor, letter;
7567
7568 boardp = ASC_BOARDP(shp);
7569 leftlen = cplen;
7570 totlen = len = 0;
7571
7572 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
7573 ASC_PRT_NEXT();
7574
7575 /*
7576 * If the BIOS saved a valid signature, then fill in
7577 * the BIOS code segment base address.
7578 */
7579 if (boardp->bios_signature != 0x55AA) {
7580 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
7581 ASC_PRT_NEXT();
7582 len = asc_prt_line(cp, leftlen,
7583"BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
7584 ASC_PRT_NEXT();
7585 len = asc_prt_line(cp, leftlen,
7586"can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
7587 ASC_PRT_NEXT();
7588 } else {
7589 major = (boardp->bios_version >> 12) & 0xF;
7590 minor = (boardp->bios_version >> 8) & 0xF;
7591 letter = (boardp->bios_version & 0xFF);
7592
7593 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
7594 major, minor, letter >= 26 ? '?' : letter + 'A');
7595 ASC_PRT_NEXT();
7596
7597 /*
7598 * Current available ROM BIOS release is 3.1I for UW
7599 * and 3.2I for U2W. This code doesn't differentiate
7600 * UW and U2W boards.
7601 */
7602 if (major < 3 || (major <= 3 && minor < 1) ||
7603 (major <= 3 && minor <= 1 && letter < ('I'- 'A'))) {
7604 len = asc_prt_line(cp, leftlen,
7605"Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
7606 ASC_PRT_NEXT();
7607 len = asc_prt_line(cp, leftlen,
7608"ftp://ftp.connectcom.net/pub\n");
7609 ASC_PRT_NEXT();
7610 }
7611 }
7612
7613 return totlen;
7614}
7615
7616/*
7617 * Add serial number to information bar if signature AAh
7618 * is found in at bit 15-9 (7 bits) of word 1.
7619 *
7620 * Serial Number consists fo 12 alpha-numeric digits.
7621 *
7622 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
7623 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
7624 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
7625 * 5 - Product revision (A-J) Word0: " "
7626 *
7627 * Signature Word1: 15-9 (7 bits)
7628 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
7629 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
7630 *
7631 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
7632 *
7633 * Note 1: Only production cards will have a serial number.
7634 *
7635 * Note 2: Signature is most significant 7 bits (0xFE).
7636 *
7637 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
7638 */
7639STATIC int
7640asc_get_eeprom_string(ushort *serialnum, uchar *cp)
7641{
7642 ushort w, num;
7643
7644 if ((serialnum[1] & 0xFE00) != ((ushort) 0xAA << 8)) {
7645 return ASC_FALSE;
7646 } else {
7647 /*
7648 * First word - 6 digits.
7649 */
7650 w = serialnum[0];
7651
7652 /* Product type - 1st digit. */
7653 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
7654 /* Product type is P=Prototype */
7655 *cp += 0x8;
7656 }
7657 cp++;
7658
7659 /* Manufacturing location - 2nd digit. */
7660 *cp++ = 'A' + ((w & 0x1C00) >> 10);
7661
7662 /* Product ID - 3rd, 4th digits. */
7663 num = w & 0x3FF;
7664 *cp++ = '0' + (num / 100);
7665 num %= 100;
7666 *cp++ = '0' + (num / 10);
7667
7668 /* Product revision - 5th digit. */
7669 *cp++ = 'A' + (num % 10);
7670
7671 /*
7672 * Second word
7673 */
7674 w = serialnum[1];
7675
7676 /*
7677 * Year - 6th digit.
7678 *
7679 * If bit 15 of third word is set, then the
7680 * last digit of the year is greater than 7.
7681 */
7682 if (serialnum[2] & 0x8000) {
7683 *cp++ = '8' + ((w & 0x1C0) >> 6);
7684 } else {
7685 *cp++ = '0' + ((w & 0x1C0) >> 6);
7686 }
7687
7688 /* Week of year - 7th, 8th digits. */
7689 num = w & 0x003F;
7690 *cp++ = '0' + num / 10;
7691 num %= 10;
7692 *cp++ = '0' + num;
7693
7694 /*
7695 * Third word
7696 */
7697 w = serialnum[2] & 0x7FFF;
7698
7699 /* Serial number - 9th digit. */
7700 *cp++ = 'A' + (w / 1000);
7701
7702 /* 10th, 11th, 12th digits. */
7703 num = w % 1000;
7704 *cp++ = '0' + num / 100;
7705 num %= 100;
7706 *cp++ = '0' + num / 10;
7707 num %= 10;
7708 *cp++ = '0' + num;
7709
7710 *cp = '\0'; /* Null Terminate the string. */
7711 return ASC_TRUE;
7712 }
7713}
7714
7715/*
7716 * asc_prt_asc_board_eeprom()
7717 *
7718 * Print board EEPROM configuration.
7719 *
7720 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7721 * cf. asc_prt_line().
7722 *
7723 * Return the number of characters copied into 'cp'. No more than
7724 * 'cplen' characters will be copied to 'cp'.
7725 */
7726STATIC int
7727asc_prt_asc_board_eeprom(struct Scsi_Host *shp, char *cp, int cplen)
7728{
7729 asc_board_t *boardp;
7730 ASC_DVC_VAR *asc_dvc_varp;
7731 int leftlen;
7732 int totlen;
7733 int len;
7734 ASCEEP_CONFIG *ep;
7735 int i;
7736#ifdef CONFIG_ISA
7737 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
7738#endif /* CONFIG_ISA */
7739 uchar serialstr[13];
7740
7741 boardp = ASC_BOARDP(shp);
7742 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
7743 ep = &boardp->eep_config.asc_eep;
7744
7745 leftlen = cplen;
7746 totlen = len = 0;
7747
7748 len = asc_prt_line(cp, leftlen,
7749"\nEEPROM Settings for AdvanSys SCSI Host %d:\n", shp->host_no);
7750 ASC_PRT_NEXT();
7751
7752 if (asc_get_eeprom_string((ushort *) &ep->adapter_info[0], serialstr) ==
7753 ASC_TRUE) {
7754 len = asc_prt_line(cp, leftlen, " Serial Number: %s\n", serialstr);
7755 ASC_PRT_NEXT();
7756 } else {
7757 if (ep->adapter_info[5] == 0xBB) {
7758 len = asc_prt_line(cp, leftlen,
7759 " Default Settings Used for EEPROM-less Adapter.\n");
7760 ASC_PRT_NEXT();
7761 } else {
7762 len = asc_prt_line(cp, leftlen,
7763 " Serial Number Signature Not Present.\n");
7764 ASC_PRT_NEXT();
7765 }
7766 }
7767
7768 len = asc_prt_line(cp, leftlen,
7769" Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7770 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng, ep->max_tag_qng);
7771 ASC_PRT_NEXT();
7772
7773 len = asc_prt_line(cp, leftlen,
7774" cntl 0x%x, no_scam 0x%x\n",
7775 ep->cntl, ep->no_scam);
7776 ASC_PRT_NEXT();
7777
7778 len = asc_prt_line(cp, leftlen,
7779" Target ID: ");
7780 ASC_PRT_NEXT();
7781 for (i = 0; i <= ASC_MAX_TID; i++) {
7782 len = asc_prt_line(cp, leftlen, " %d", i);
7783 ASC_PRT_NEXT();
7784 }
7785 len = asc_prt_line(cp, leftlen, "\n");
7786 ASC_PRT_NEXT();
7787
7788 len = asc_prt_line(cp, leftlen,
7789" Disconnects: ");
7790 ASC_PRT_NEXT();
7791 for (i = 0; i <= ASC_MAX_TID; i++) {
7792 len = asc_prt_line(cp, leftlen, " %c",
7793 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7794 ASC_PRT_NEXT();
7795 }
7796 len = asc_prt_line(cp, leftlen, "\n");
7797 ASC_PRT_NEXT();
7798
7799 len = asc_prt_line(cp, leftlen,
7800" Command Queuing: ");
7801 ASC_PRT_NEXT();
7802 for (i = 0; i <= ASC_MAX_TID; i++) {
7803 len = asc_prt_line(cp, leftlen, " %c",
7804 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7805 ASC_PRT_NEXT();
7806 }
7807 len = asc_prt_line(cp, leftlen, "\n");
7808 ASC_PRT_NEXT();
7809
7810 len = asc_prt_line(cp, leftlen,
7811" Start Motor: ");
7812 ASC_PRT_NEXT();
7813 for (i = 0; i <= ASC_MAX_TID; i++) {
7814 len = asc_prt_line(cp, leftlen, " %c",
7815 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7816 ASC_PRT_NEXT();
7817 }
7818 len = asc_prt_line(cp, leftlen, "\n");
7819 ASC_PRT_NEXT();
7820
7821 len = asc_prt_line(cp, leftlen,
7822" Synchronous Transfer:");
7823 ASC_PRT_NEXT();
7824 for (i = 0; i <= ASC_MAX_TID; i++) {
7825 len = asc_prt_line(cp, leftlen, " %c",
7826 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7827 ASC_PRT_NEXT();
7828 }
7829 len = asc_prt_line(cp, leftlen, "\n");
7830 ASC_PRT_NEXT();
7831
7832#ifdef CONFIG_ISA
7833 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
7834 len = asc_prt_line(cp, leftlen,
7835" Host ISA DMA speed: %d MB/S\n",
7836 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
7837 ASC_PRT_NEXT();
7838 }
7839#endif /* CONFIG_ISA */
7840
7841 return totlen;
7842}
7843
7844/*
7845 * asc_prt_adv_board_eeprom()
7846 *
7847 * Print board EEPROM configuration.
7848 *
7849 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7850 * cf. asc_prt_line().
7851 *
7852 * Return the number of characters copied into 'cp'. No more than
7853 * 'cplen' characters will be copied to 'cp'.
7854 */
7855STATIC int
7856asc_prt_adv_board_eeprom(struct Scsi_Host *shp, char *cp, int cplen)
7857{
7858 asc_board_t *boardp;
7859 ADV_DVC_VAR *adv_dvc_varp;
7860 int leftlen;
7861 int totlen;
7862 int len;
7863 int i;
7864 char *termstr;
7865 uchar serialstr[13];
7866 ADVEEP_3550_CONFIG *ep_3550 = NULL;
7867 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
7868 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
7869 ushort word;
7870 ushort *wordp;
7871 ushort sdtr_speed = 0;
7872
7873 boardp = ASC_BOARDP(shp);
7874 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
7875 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7876 {
7877 ep_3550 = &boardp->eep_config.adv_3550_eep;
7878 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7879 {
7880 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
7881 } else
7882 {
7883 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
7884 }
7885
7886 leftlen = cplen;
7887 totlen = len = 0;
7888
7889 len = asc_prt_line(cp, leftlen,
7890"\nEEPROM Settings for AdvanSys SCSI Host %d:\n", shp->host_no);
7891 ASC_PRT_NEXT();
7892
7893 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7894 {
7895 wordp = &ep_3550->serial_number_word1;
7896 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7897 {
7898 wordp = &ep_38C0800->serial_number_word1;
7899 } else
7900 {
7901 wordp = &ep_38C1600->serial_number_word1;
7902 }
7903
7904 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
7905 len = asc_prt_line(cp, leftlen, " Serial Number: %s\n", serialstr);
7906 ASC_PRT_NEXT();
7907 } else {
7908 len = asc_prt_line(cp, leftlen,
7909 " Serial Number Signature Not Present.\n");
7910 ASC_PRT_NEXT();
7911 }
7912
7913 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7914 {
7915 len = asc_prt_line(cp, leftlen,
7916" Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7917 ep_3550->adapter_scsi_id, ep_3550->max_host_qng,
7918 ep_3550->max_dvc_qng);
7919 ASC_PRT_NEXT();
7920 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7921 {
7922 len = asc_prt_line(cp, leftlen,
7923" Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7924 ep_38C0800->adapter_scsi_id, ep_38C0800->max_host_qng,
7925 ep_38C0800->max_dvc_qng);
7926 ASC_PRT_NEXT();
7927 } else
7928 {
7929 len = asc_prt_line(cp, leftlen,
7930" Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7931 ep_38C1600->adapter_scsi_id, ep_38C1600->max_host_qng,
7932 ep_38C1600->max_dvc_qng);
7933 ASC_PRT_NEXT();
7934 }
7935 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7936 {
7937 word = ep_3550->termination;
7938 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7939 {
7940 word = ep_38C0800->termination_lvd;
7941 } else
7942 {
7943 word = ep_38C1600->termination_lvd;
7944 }
7945 switch (word) {
7946 case 1:
7947 termstr = "Low Off/High Off";
7948 break;
7949 case 2:
7950 termstr = "Low Off/High On";
7951 break;
7952 case 3:
7953 termstr = "Low On/High On";
7954 break;
7955 default:
7956 case 0:
7957 termstr = "Automatic";
7958 break;
7959 }
7960
7961 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7962 {
7963 len = asc_prt_line(cp, leftlen,
7964" termination: %u (%s), bios_ctrl: 0x%x\n",
7965 ep_3550->termination, termstr, ep_3550->bios_ctrl);
7966 ASC_PRT_NEXT();
7967 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7968 {
7969 len = asc_prt_line(cp, leftlen,
7970" termination: %u (%s), bios_ctrl: 0x%x\n",
7971 ep_38C0800->termination_lvd, termstr, ep_38C0800->bios_ctrl);
7972 ASC_PRT_NEXT();
7973 } else
7974 {
7975 len = asc_prt_line(cp, leftlen,
7976" termination: %u (%s), bios_ctrl: 0x%x\n",
7977 ep_38C1600->termination_lvd, termstr, ep_38C1600->bios_ctrl);
7978 ASC_PRT_NEXT();
7979 }
7980
7981 len = asc_prt_line(cp, leftlen,
7982" Target ID: ");
7983 ASC_PRT_NEXT();
7984 for (i = 0; i <= ADV_MAX_TID; i++) {
7985 len = asc_prt_line(cp, leftlen, " %X", i);
7986 ASC_PRT_NEXT();
7987 }
7988 len = asc_prt_line(cp, leftlen, "\n");
7989 ASC_PRT_NEXT();
7990
7991 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7992 {
7993 word = ep_3550->disc_enable;
7994 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7995 {
7996 word = ep_38C0800->disc_enable;
7997 } else
7998 {
7999 word = ep_38C1600->disc_enable;
8000 }
8001 len = asc_prt_line(cp, leftlen,
8002" Disconnects: ");
8003 ASC_PRT_NEXT();
8004 for (i = 0; i <= ADV_MAX_TID; i++) {
8005 len = asc_prt_line(cp, leftlen, " %c",
8006 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8007 ASC_PRT_NEXT();
8008 }
8009 len = asc_prt_line(cp, leftlen, "\n");
8010 ASC_PRT_NEXT();
8011
8012 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8013 {
8014 word = ep_3550->tagqng_able;
8015 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8016 {
8017 word = ep_38C0800->tagqng_able;
8018 } else
8019 {
8020 word = ep_38C1600->tagqng_able;
8021 }
8022 len = asc_prt_line(cp, leftlen,
8023" Command Queuing: ");
8024 ASC_PRT_NEXT();
8025 for (i = 0; i <= ADV_MAX_TID; i++) {
8026 len = asc_prt_line(cp, leftlen, " %c",
8027 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8028 ASC_PRT_NEXT();
8029 }
8030 len = asc_prt_line(cp, leftlen, "\n");
8031 ASC_PRT_NEXT();
8032
8033 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8034 {
8035 word = ep_3550->start_motor;
8036 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8037 {
8038 word = ep_38C0800->start_motor;
8039 } else
8040 {
8041 word = ep_38C1600->start_motor;
8042 }
8043 len = asc_prt_line(cp, leftlen,
8044" Start Motor: ");
8045 ASC_PRT_NEXT();
8046 for (i = 0; i <= ADV_MAX_TID; i++) {
8047 len = asc_prt_line(cp, leftlen, " %c",
8048 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8049 ASC_PRT_NEXT();
8050 }
8051 len = asc_prt_line(cp, leftlen, "\n");
8052 ASC_PRT_NEXT();
8053
8054 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8055 {
8056 len = asc_prt_line(cp, leftlen,
8057" Synchronous Transfer:");
8058 ASC_PRT_NEXT();
8059 for (i = 0; i <= ADV_MAX_TID; i++) {
8060 len = asc_prt_line(cp, leftlen, " %c",
8061 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8062 ASC_PRT_NEXT();
8063 }
8064 len = asc_prt_line(cp, leftlen, "\n");
8065 ASC_PRT_NEXT();
8066 }
8067
8068 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8069 {
8070 len = asc_prt_line(cp, leftlen,
8071" Ultra Transfer: ");
8072 ASC_PRT_NEXT();
8073 for (i = 0; i <= ADV_MAX_TID; i++) {
8074 len = asc_prt_line(cp, leftlen, " %c",
8075 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8076 ASC_PRT_NEXT();
8077 }
8078 len = asc_prt_line(cp, leftlen, "\n");
8079 ASC_PRT_NEXT();
8080 }
8081
8082 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8083 {
8084 word = ep_3550->wdtr_able;
8085 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8086 {
8087 word = ep_38C0800->wdtr_able;
8088 } else
8089 {
8090 word = ep_38C1600->wdtr_able;
8091 }
8092 len = asc_prt_line(cp, leftlen,
8093" Wide Transfer: ");
8094 ASC_PRT_NEXT();
8095 for (i = 0; i <= ADV_MAX_TID; i++) {
8096 len = asc_prt_line(cp, leftlen, " %c",
8097 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8098 ASC_PRT_NEXT();
8099 }
8100 len = asc_prt_line(cp, leftlen, "\n");
8101 ASC_PRT_NEXT();
8102
8103 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
8104 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600)
8105 {
8106 len = asc_prt_line(cp, leftlen,
8107" Synchronous Transfer Speed (Mhz):\n ");
8108 ASC_PRT_NEXT();
8109 for (i = 0; i <= ADV_MAX_TID; i++) {
8110 char *speed_str;
8111
8112 if (i == 0)
8113 {
8114 sdtr_speed = adv_dvc_varp->sdtr_speed1;
8115 } else if (i == 4)
8116 {
8117 sdtr_speed = adv_dvc_varp->sdtr_speed2;
8118 } else if (i == 8)
8119 {
8120 sdtr_speed = adv_dvc_varp->sdtr_speed3;
8121 } else if (i == 12)
8122 {
8123 sdtr_speed = adv_dvc_varp->sdtr_speed4;
8124 }
8125 switch (sdtr_speed & ADV_MAX_TID)
8126 {
8127 case 0: speed_str = "Off"; break;
8128 case 1: speed_str = " 5"; break;
8129 case 2: speed_str = " 10"; break;
8130 case 3: speed_str = " 20"; break;
8131 case 4: speed_str = " 40"; break;
8132 case 5: speed_str = " 80"; break;
8133 default: speed_str = "Unk"; break;
8134 }
8135 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
8136 ASC_PRT_NEXT();
8137 if (i == 7)
8138 {
8139 len = asc_prt_line(cp, leftlen, "\n ");
8140 ASC_PRT_NEXT();
8141 }
8142 sdtr_speed >>= 4;
8143 }
8144 len = asc_prt_line(cp, leftlen, "\n");
8145 ASC_PRT_NEXT();
8146 }
8147
8148 return totlen;
8149}
8150
8151/*
8152 * asc_prt_driver_conf()
8153 *
8154 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8155 * cf. asc_prt_line().
8156 *
8157 * Return the number of characters copied into 'cp'. No more than
8158 * 'cplen' characters will be copied to 'cp'.
8159 */
8160STATIC int
8161asc_prt_driver_conf(struct Scsi_Host *shp, char *cp, int cplen)
8162{
8163 asc_board_t *boardp;
8164 int leftlen;
8165 int totlen;
8166 int len;
8167 int chip_scsi_id;
8168
8169 boardp = ASC_BOARDP(shp);
8170
8171 leftlen = cplen;
8172 totlen = len = 0;
8173
8174 len = asc_prt_line(cp, leftlen,
8175"\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
8176 shp->host_no);
8177 ASC_PRT_NEXT();
8178
8179 len = asc_prt_line(cp, leftlen,
8180" host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
8181 shp->host_busy, shp->last_reset, shp->max_id, shp->max_lun,
8182 shp->max_channel);
8183 ASC_PRT_NEXT();
8184
8185 len = asc_prt_line(cp, leftlen,
8186" unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
8187 shp->unique_id, shp->can_queue, shp->this_id, shp->sg_tablesize,
8188 shp->cmd_per_lun);
8189 ASC_PRT_NEXT();
8190
8191 len = asc_prt_line(cp, leftlen,
8192" unchecked_isa_dma %d, use_clustering %d\n",
8193 shp->unchecked_isa_dma, shp->use_clustering);
8194 ASC_PRT_NEXT();
8195
8196 len = asc_prt_line(cp, leftlen,
8197" flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
8198 boardp->flags, boardp->last_reset, jiffies, boardp->asc_n_io_port);
8199 ASC_PRT_NEXT();
8200
8201 /* 'shp->n_io_port' may be truncated because it is only one byte. */
8202 len = asc_prt_line(cp, leftlen,
8203" io_port 0x%x, n_io_port 0x%x\n",
8204 shp->io_port, shp->n_io_port);
8205 ASC_PRT_NEXT();
8206
8207 if (ASC_NARROW_BOARD(boardp)) {
8208 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
8209 } else {
8210 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
8211 }
8212
8213 return totlen;
8214}
8215
8216/*
8217 * asc_prt_asc_board_info()
8218 *
8219 * Print dynamic board configuration information.
8220 *
8221 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8222 * cf. asc_prt_line().
8223 *
8224 * Return the number of characters copied into 'cp'. No more than
8225 * 'cplen' characters will be copied to 'cp'.
8226 */
8227STATIC int
8228asc_prt_asc_board_info(struct Scsi_Host *shp, char *cp, int cplen)
8229{
8230 asc_board_t *boardp;
8231 int chip_scsi_id;
8232 int leftlen;
8233 int totlen;
8234 int len;
8235 ASC_DVC_VAR *v;
8236 ASC_DVC_CFG *c;
8237 int i;
8238 int renegotiate = 0;
8239
8240 boardp = ASC_BOARDP(shp);
8241 v = &boardp->dvc_var.asc_dvc_var;
8242 c = &boardp->dvc_cfg.asc_dvc_cfg;
8243 chip_scsi_id = c->chip_scsi_id;
8244
8245 leftlen = cplen;
8246 totlen = len = 0;
8247
8248 len = asc_prt_line(cp, leftlen,
8249"\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
8250 shp->host_no);
8251 ASC_PRT_NEXT();
8252
8253 len = asc_prt_line(cp, leftlen,
8254" chip_version %u, lib_version 0x%x, lib_serial_no %u, mcode_date 0x%x\n",
8255 c->chip_version, c->lib_version, c->lib_serial_no, c->mcode_date);
8256 ASC_PRT_NEXT();
8257
8258 len = asc_prt_line(cp, leftlen,
8259" mcode_version 0x%x, err_code %u\n",
8260 c->mcode_version, v->err_code);
8261 ASC_PRT_NEXT();
8262
8263 /* Current number of commands waiting for the host. */
8264 len = asc_prt_line(cp, leftlen,
8265" Total Command Pending: %d\n", v->cur_total_qng);
8266 ASC_PRT_NEXT();
8267
8268 len = asc_prt_line(cp, leftlen,
8269" Command Queuing:");
8270 ASC_PRT_NEXT();
8271 for (i = 0; i <= ASC_MAX_TID; i++) {
8272 if ((chip_scsi_id == i) ||
8273 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8274 continue;
8275 }
8276 len = asc_prt_line(cp, leftlen, " %X:%c",
8277 i, (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8278 ASC_PRT_NEXT();
8279 }
8280 len = asc_prt_line(cp, leftlen, "\n");
8281 ASC_PRT_NEXT();
8282
8283 /* Current number of commands waiting for a device. */
8284 len = asc_prt_line(cp, leftlen,
8285" Command Queue Pending:");
8286 ASC_PRT_NEXT();
8287 for (i = 0; i <= ASC_MAX_TID; i++) {
8288 if ((chip_scsi_id == i) ||
8289 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8290 continue;
8291 }
8292 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
8293 ASC_PRT_NEXT();
8294 }
8295 len = asc_prt_line(cp, leftlen, "\n");
8296 ASC_PRT_NEXT();
8297
8298 /* Current limit on number of commands that can be sent to a device. */
8299 len = asc_prt_line(cp, leftlen,
8300" Command Queue Limit:");
8301 ASC_PRT_NEXT();
8302 for (i = 0; i <= ASC_MAX_TID; i++) {
8303 if ((chip_scsi_id == i) ||
8304 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8305 continue;
8306 }
8307 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
8308 ASC_PRT_NEXT();
8309 }
8310 len = asc_prt_line(cp, leftlen, "\n");
8311 ASC_PRT_NEXT();
8312
8313 /* Indicate whether the device has returned queue full status. */
8314 len = asc_prt_line(cp, leftlen,
8315" Command Queue Full:");
8316 ASC_PRT_NEXT();
8317 for (i = 0; i <= ASC_MAX_TID; i++) {
8318 if ((chip_scsi_id == i) ||
8319 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8320 continue;
8321 }
8322 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
8323 len = asc_prt_line(cp, leftlen, " %X:Y-%d",
8324 i, boardp->queue_full_cnt[i]);
8325 } else {
8326 len = asc_prt_line(cp, leftlen, " %X:N", i);
8327 }
8328 ASC_PRT_NEXT();
8329 }
8330 len = asc_prt_line(cp, leftlen, "\n");
8331 ASC_PRT_NEXT();
8332
8333 len = asc_prt_line(cp, leftlen,
8334" Synchronous Transfer:");
8335 ASC_PRT_NEXT();
8336 for (i = 0; i <= ASC_MAX_TID; i++) {
8337 if ((chip_scsi_id == i) ||
8338 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8339 continue;
8340 }
8341 len = asc_prt_line(cp, leftlen, " %X:%c",
8342 i, (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8343 ASC_PRT_NEXT();
8344 }
8345 len = asc_prt_line(cp, leftlen, "\n");
8346 ASC_PRT_NEXT();
8347
8348 for (i = 0; i <= ASC_MAX_TID; i++) {
8349 uchar syn_period_ix;
8350
8351 if ((chip_scsi_id == i) ||
8352 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
8353 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
8354 continue;
8355 }
8356
8357 len = asc_prt_line(cp, leftlen, " %X:", i);
8358 ASC_PRT_NEXT();
8359
8360 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0)
8361 {
8362 len = asc_prt_line(cp, leftlen, " Asynchronous");
8363 ASC_PRT_NEXT();
8364 } else
8365 {
8366 syn_period_ix =
8367 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index - 1);
8368
8369 len = asc_prt_line(cp, leftlen,
8370 " Transfer Period Factor: %d (%d.%d Mhz),",
8371 v->sdtr_period_tbl[syn_period_ix],
8372 250 / v->sdtr_period_tbl[syn_period_ix],
8373 ASC_TENTHS(250, v->sdtr_period_tbl[syn_period_ix]));
8374 ASC_PRT_NEXT();
8375
8376 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
8377 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
8378 ASC_PRT_NEXT();
8379 }
8380
8381 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8382 len = asc_prt_line(cp, leftlen, "*\n");
8383 renegotiate = 1;
8384 } else
8385 {
8386 len = asc_prt_line(cp, leftlen, "\n");
8387 }
8388 ASC_PRT_NEXT();
8389 }
8390
8391 if (renegotiate)
8392 {
8393 len = asc_prt_line(cp, leftlen,
8394 " * = Re-negotiation pending before next command.\n");
8395 ASC_PRT_NEXT();
8396 }
8397
8398 return totlen;
8399}
8400
8401/*
8402 * asc_prt_adv_board_info()
8403 *
8404 * Print dynamic board configuration information.
8405 *
8406 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8407 * cf. asc_prt_line().
8408 *
8409 * Return the number of characters copied into 'cp'. No more than
8410 * 'cplen' characters will be copied to 'cp'.
8411 */
8412STATIC int
8413asc_prt_adv_board_info(struct Scsi_Host *shp, char *cp, int cplen)
8414{
8415 asc_board_t *boardp;
8416 int leftlen;
8417 int totlen;
8418 int len;
8419 int i;
8420 ADV_DVC_VAR *v;
8421 ADV_DVC_CFG *c;
8422 AdvPortAddr iop_base;
8423 ushort chip_scsi_id;
8424 ushort lramword;
8425 uchar lrambyte;
8426 ushort tagqng_able;
8427 ushort sdtr_able, wdtr_able;
8428 ushort wdtr_done, sdtr_done;
8429 ushort period = 0;
8430 int renegotiate = 0;
8431
8432 boardp = ASC_BOARDP(shp);
8433 v = &boardp->dvc_var.adv_dvc_var;
8434 c = &boardp->dvc_cfg.adv_dvc_cfg;
8435 iop_base = v->iop_base;
8436 chip_scsi_id = v->chip_scsi_id;
8437
8438 leftlen = cplen;
8439 totlen = len = 0;
8440
8441 len = asc_prt_line(cp, leftlen,
8442"\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
8443 shp->host_no);
8444 ASC_PRT_NEXT();
8445
8446 len = asc_prt_line(cp, leftlen,
8447" iop_base 0x%lx, cable_detect: %X, err_code %u\n",
8448 v->iop_base,
8449 AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1) & CABLE_DETECT,
8450 v->err_code);
8451 ASC_PRT_NEXT();
8452
8453 len = asc_prt_line(cp, leftlen,
8454" chip_version %u, lib_version 0x%x, mcode_date 0x%x, mcode_version 0x%x\n",
8455 c->chip_version, c->lib_version, c->mcode_date, c->mcode_version);
8456 ASC_PRT_NEXT();
8457
8458 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8459 len = asc_prt_line(cp, leftlen,
8460" Queuing Enabled:");
8461 ASC_PRT_NEXT();
8462 for (i = 0; i <= ADV_MAX_TID; i++) {
8463 if ((chip_scsi_id == i) ||
8464 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8465 continue;
8466 }
8467
8468 len = asc_prt_line(cp, leftlen, " %X:%c",
8469 i, (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8470 ASC_PRT_NEXT();
8471 }
8472 len = asc_prt_line(cp, leftlen, "\n");
8473 ASC_PRT_NEXT();
8474
8475 len = asc_prt_line(cp, leftlen,
8476" Queue Limit:");
8477 ASC_PRT_NEXT();
8478 for (i = 0; i <= ADV_MAX_TID; i++) {
8479 if ((chip_scsi_id == i) ||
8480 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8481 continue;
8482 }
8483
8484 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i, lrambyte);
8485
8486 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
8487 ASC_PRT_NEXT();
8488 }
8489 len = asc_prt_line(cp, leftlen, "\n");
8490 ASC_PRT_NEXT();
8491
8492 len = asc_prt_line(cp, leftlen,
8493" Command Pending:");
8494 ASC_PRT_NEXT();
8495 for (i = 0; i <= ADV_MAX_TID; i++) {
8496 if ((chip_scsi_id == i) ||
8497 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8498 continue;
8499 }
8500
8501 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i, lrambyte);
8502
8503 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
8504 ASC_PRT_NEXT();
8505 }
8506 len = asc_prt_line(cp, leftlen, "\n");
8507 ASC_PRT_NEXT();
8508
8509 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8510 len = asc_prt_line(cp, leftlen,
8511" Wide Enabled:");
8512 ASC_PRT_NEXT();
8513 for (i = 0; i <= ADV_MAX_TID; i++) {
8514 if ((chip_scsi_id == i) ||
8515 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8516 continue;
8517 }
8518
8519 len = asc_prt_line(cp, leftlen, " %X:%c",
8520 i, (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8521 ASC_PRT_NEXT();
8522 }
8523 len = asc_prt_line(cp, leftlen, "\n");
8524 ASC_PRT_NEXT();
8525
8526 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
8527 len = asc_prt_line(cp, leftlen,
8528" Transfer Bit Width:");
8529 ASC_PRT_NEXT();
8530 for (i = 0; i <= ADV_MAX_TID; i++) {
8531 if ((chip_scsi_id == i) ||
8532 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8533 continue;
8534 }
8535
8536 AdvReadWordLram(iop_base, ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
8537 lramword);
8538
8539 len = asc_prt_line(cp, leftlen, " %X:%d",
8540 i, (lramword & 0x8000) ? 16 : 8);
8541 ASC_PRT_NEXT();
8542
8543 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
8544 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8545 len = asc_prt_line(cp, leftlen, "*");
8546 ASC_PRT_NEXT();
8547 renegotiate = 1;
8548 }
8549 }
8550 len = asc_prt_line(cp, leftlen, "\n");
8551 ASC_PRT_NEXT();
8552
8553 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8554 len = asc_prt_line(cp, leftlen,
8555" Synchronous Enabled:");
8556 ASC_PRT_NEXT();
8557 for (i = 0; i <= ADV_MAX_TID; i++) {
8558 if ((chip_scsi_id == i) ||
8559 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8560 continue;
8561 }
8562
8563 len = asc_prt_line(cp, leftlen, " %X:%c",
8564 i, (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8565 ASC_PRT_NEXT();
8566 }
8567 len = asc_prt_line(cp, leftlen, "\n");
8568 ASC_PRT_NEXT();
8569
8570 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
8571 for (i = 0; i <= ADV_MAX_TID; i++) {
8572
8573 AdvReadWordLram(iop_base, ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
8574 lramword);
8575 lramword &= ~0x8000;
8576
8577 if ((chip_scsi_id == i) ||
8578 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
8579 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
8580 continue;
8581 }
8582
8583 len = asc_prt_line(cp, leftlen, " %X:", i);
8584 ASC_PRT_NEXT();
8585
8586 if ((lramword & 0x1F) == 0) /* Check for REQ/ACK Offset 0. */
8587 {
8588 len = asc_prt_line(cp, leftlen, " Asynchronous");
8589 ASC_PRT_NEXT();
8590 } else
8591 {
8592 len = asc_prt_line(cp, leftlen, " Transfer Period Factor: ");
8593 ASC_PRT_NEXT();
8594
8595 if ((lramword & 0x1F00) == 0x1100) /* 80 Mhz */
8596 {
8597 len = asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
8598 ASC_PRT_NEXT();
8599 } else if ((lramword & 0x1F00) == 0x1000) /* 40 Mhz */
8600 {
8601 len = asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
8602 ASC_PRT_NEXT();
8603 } else /* 20 Mhz or below. */
8604 {
8605 period = (((lramword >> 8) * 25) + 50)/4;
8606
8607 if (period == 0) /* Should never happen. */
8608 {
8609 len = asc_prt_line(cp, leftlen, "%d (? Mhz), ");
8610 ASC_PRT_NEXT();
8611 } else
8612 {
8613 len = asc_prt_line(cp, leftlen,
8614 "%d (%d.%d Mhz),",
8615 period, 250/period, ASC_TENTHS(250, period));
8616 ASC_PRT_NEXT();
8617 }
8618 }
8619
8620 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
8621 lramword & 0x1F);
8622 ASC_PRT_NEXT();
8623 }
8624
8625 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8626 len = asc_prt_line(cp, leftlen, "*\n");
8627 renegotiate = 1;
8628 } else
8629 {
8630 len = asc_prt_line(cp, leftlen, "\n");
8631 }
8632 ASC_PRT_NEXT();
8633 }
8634
8635 if (renegotiate)
8636 {
8637 len = asc_prt_line(cp, leftlen,
8638 " * = Re-negotiation pending before next command.\n");
8639 ASC_PRT_NEXT();
8640 }
8641
8642 return totlen;
8643}
8644
8645/*
8646 * asc_proc_copy()
8647 *
8648 * Copy proc information to a read buffer taking into account the current
8649 * read offset in the file and the remaining space in the read buffer.
8650 */
8651STATIC int
8652asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
8653 char *cp, int cplen)
8654{
8655 int cnt = 0;
8656
8657 ASC_DBG3(2, "asc_proc_copy: offset %d, advoffset %d, cplen %d\n",
8658 (unsigned) offset, (unsigned) advoffset, cplen);
8659 if (offset <= advoffset) {
8660 /* Read offset below current offset, copy everything. */
8661 cnt = min(cplen, leftlen);
8662 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
8663 (ulong) curbuf, (ulong) cp, cnt);
8664 memcpy(curbuf, cp, cnt);
8665 } else if (offset < advoffset + cplen) {
8666 /* Read offset within current range, partial copy. */
8667 cnt = (advoffset + cplen) - offset;
8668 cp = (cp + cplen) - cnt;
8669 cnt = min(cnt, leftlen);
8670 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
8671 (ulong) curbuf, (ulong) cp, cnt);
8672 memcpy(curbuf, cp, cnt);
8673 }
8674 return cnt;
8675}
8676
8677/*
8678 * asc_prt_line()
8679 *
8680 * If 'cp' is NULL print to the console, otherwise print to a buffer.
8681 *
8682 * Return 0 if printing to the console, otherwise return the number of
8683 * bytes written to the buffer.
8684 *
8685 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
8686 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
8687 */
8688STATIC int
8689asc_prt_line(char *buf, int buflen, char *fmt, ...)
8690{
8691 va_list args;
8692 int ret;
8693 char s[ASC_PRTLINE_SIZE];
8694
8695 va_start(args, fmt);
8696 ret = vsprintf(s, fmt, args);
8697 ASC_ASSERT(ret < ASC_PRTLINE_SIZE);
8698 if (buf == NULL) {
8699 (void) printk(s);
8700 ret = 0;
8701 } else {
8702 ret = min(buflen, ret);
8703 memcpy(buf, s, ret);
8704 }
8705 va_end(args);
8706 return ret;
8707}
8708#endif /* CONFIG_PROC_FS */
8709
8710
8711/*
8712 * --- Functions Required by the Asc Library
8713 */
8714
8715/*
8716 * Delay for 'n' milliseconds. Don't use the 'jiffies'
8717 * global variable which is incremented once every 5 ms
8718 * from a timer interrupt, because this function may be
8719 * called when interrupts are disabled.
8720 */
8721STATIC void
8722DvcSleepMilliSecond(ADV_DCNT n)
8723{
8724 ASC_DBG1(4, "DvcSleepMilliSecond: %lu\n", (ulong) n);
8725 mdelay(n);
8726}
8727
8728/*
8729 * Currently and inline noop but leave as a placeholder.
8730 * Leave DvcEnterCritical() as a noop placeholder.
8731 */
8732STATIC inline ulong
8733DvcEnterCritical(void)
8734{
8735 return 0;
8736}
8737
8738/*
8739 * Critical sections are all protected by the board spinlock.
8740 * Leave DvcLeaveCritical() as a noop placeholder.
8741 */
8742STATIC inline void
8743DvcLeaveCritical(ulong flags)
8744{
8745 return;
8746}
8747
8748/*
8749 * void
8750 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8751 *
8752 * Calling/Exit State:
8753 * none
8754 *
8755 * Description:
8756 * Output an ASC_SCSI_Q structure to the chip
8757 */
8758STATIC void
8759DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8760{
8761 int i;
8762
8763 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8764 AscSetChipLramAddr(iop_base, s_addr);
8765 for (i = 0; i < 2 * words; i += 2) {
8766 if (i == 4 || i == 20) {
8767 continue;
8768 }
8769 outpw(iop_base + IOP_RAM_DATA,
8770 ((ushort) outbuf[i + 1] << 8) | outbuf[i]);
8771 }
8772}
8773
8774/*
8775 * void
8776 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
8777 *
8778 * Calling/Exit State:
8779 * none
8780 *
8781 * Description:
8782 * Input an ASC_QDONE_INFO structure from the chip
8783 */
8784STATIC void
8785DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
8786{
8787 int i;
8788 ushort word;
8789
8790 AscSetChipLramAddr(iop_base, s_addr);
8791 for (i = 0; i < 2 * words; i += 2) {
8792 if (i == 10) {
8793 continue;
8794 }
8795 word = inpw(iop_base + IOP_RAM_DATA);
8796 inbuf[i] = word & 0xff;
8797 inbuf[i + 1] = (word >> 8) & 0xff;
8798 }
8799 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
8800}
8801
8802/*
8803 * Read a PCI configuration byte.
8804 */
8805STATIC uchar __init
8806DvcReadPCIConfigByte(
8807 ASC_DVC_VAR *asc_dvc,
8808 ushort offset)
8809{
8810#ifdef CONFIG_PCI
8811 uchar byte_data;
8812 pci_read_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, &byte_data);
8813 return byte_data;
8814#else /* !defined(CONFIG_PCI) */
8815 return 0;
8816#endif /* !defined(CONFIG_PCI) */
8817}
8818
8819/*
8820 * Write a PCI configuration byte.
8821 */
8822STATIC void __init
8823DvcWritePCIConfigByte(
8824 ASC_DVC_VAR *asc_dvc,
8825 ushort offset,
8826 uchar byte_data)
8827{
8828#ifdef CONFIG_PCI
8829 pci_write_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, byte_data);
8830#endif /* CONFIG_PCI */
8831}
8832
8833/*
8834 * Return the BIOS address of the adapter at the specified
8835 * I/O port and with the specified bus type.
8836 */
8837STATIC ushort __init
8838AscGetChipBiosAddress(
8839 PortAddr iop_base,
8840 ushort bus_type)
8841{
8842 ushort cfg_lsw;
8843 ushort bios_addr;
8844
8845 /*
8846 * The PCI BIOS is re-located by the motherboard BIOS. Because
8847 * of this the driver can not determine where a PCI BIOS is
8848 * loaded and executes.
8849 */
8850 if (bus_type & ASC_IS_PCI)
8851 {
8852 return(0);
8853 }
8854
8855#ifdef CONFIG_ISA
8856 if((bus_type & ASC_IS_EISA) != 0)
8857 {
8858 cfg_lsw = AscGetEisaChipCfg(iop_base);
8859 cfg_lsw &= 0x000F;
8860 bios_addr = (ushort)(ASC_BIOS_MIN_ADDR +
8861 (cfg_lsw * ASC_BIOS_BANK_SIZE));
8862 return(bios_addr);
8863 }/* if */
8864#endif /* CONFIG_ISA */
8865
8866 cfg_lsw = AscGetChipCfgLsw(iop_base);
8867
8868 /*
8869 * ISA PnP uses the top bit as the 32K BIOS flag
8870 */
8871 if (bus_type == ASC_IS_ISAPNP)
8872 {
8873 cfg_lsw &= 0x7FFF;
8874 }/* if */
8875
8876 bios_addr = (ushort)(((cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE) +
8877 ASC_BIOS_MIN_ADDR);
8878 return(bios_addr);
8879}
8880
8881
8882/*
8883 * --- Functions Required by the Adv Library
8884 */
8885
8886/*
8887 * DvcGetPhyAddr()
8888 *
8889 * Return the physical address of 'vaddr' and set '*lenp' to the
8890 * number of physically contiguous bytes that follow 'vaddr'.
8891 * 'flag' indicates the type of structure whose physical address
8892 * is being translated.
8893 *
8894 * Note: Because Linux currently doesn't page the kernel and all
8895 * kernel buffers are physically contiguous, leave '*lenp' unchanged.
8896 */
8897ADV_PADDR
8898DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
8899 uchar *vaddr, ADV_SDCNT *lenp, int flag)
8900{
8901 ADV_PADDR paddr;
8902
8903 paddr = virt_to_bus(vaddr);
8904
8905 ASC_DBG4(4,
8906 "DvcGetPhyAddr: vaddr 0x%lx, lenp 0x%lx *lenp %lu, paddr 0x%lx\n",
8907 (ulong) vaddr, (ulong) lenp, (ulong) *((ulong *) lenp), (ulong) paddr);
8908
8909 return paddr;
8910}
8911
8912/*
8913 * Read a PCI configuration byte.
8914 */
8915STATIC uchar __init
8916DvcAdvReadPCIConfigByte(
8917 ADV_DVC_VAR *asc_dvc,
8918 ushort offset)
8919{
8920#ifdef CONFIG_PCI
8921 uchar byte_data;
8922 pci_read_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, &byte_data);
8923 return byte_data;
8924#else /* CONFIG_PCI */
8925 return 0;
8926#endif /* CONFIG_PCI */
8927}
8928
8929/*
8930 * Write a PCI configuration byte.
8931 */
8932STATIC void __init
8933DvcAdvWritePCIConfigByte(
8934 ADV_DVC_VAR *asc_dvc,
8935 ushort offset,
8936 uchar byte_data)
8937{
8938#ifdef CONFIG_PCI
8939 pci_write_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, byte_data);
8940#else /* CONFIG_PCI */
8941 return;
8942#endif /* CONFIG_PCI */
8943}
8944
8945/*
8946 * --- Tracing and Debugging Functions
8947 */
8948
8949#ifdef ADVANSYS_STATS
8950#ifdef CONFIG_PROC_FS
8951/*
8952 * asc_prt_board_stats()
8953 *
8954 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8955 * cf. asc_prt_line().
8956 *
8957 * Return the number of characters copied into 'cp'. No more than
8958 * 'cplen' characters will be copied to 'cp'.
8959 */
8960STATIC int
8961asc_prt_board_stats(struct Scsi_Host *shp, char *cp, int cplen)
8962{
8963 int leftlen;
8964 int totlen;
8965 int len;
8966 struct asc_stats *s;
8967 asc_board_t *boardp;
8968
8969 leftlen = cplen;
8970 totlen = len = 0;
8971
8972 boardp = ASC_BOARDP(shp);
8973 s = &boardp->asc_stats;
8974
8975 len = asc_prt_line(cp, leftlen,
8976"\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n", shp->host_no);
8977 ASC_PRT_NEXT();
8978
8979 len = asc_prt_line(cp, leftlen,
8980" queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
8981 s->queuecommand, s->reset, s->biosparam, s->interrupt);
8982 ASC_PRT_NEXT();
8983
8984 len = asc_prt_line(cp, leftlen,
8985" callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
8986 s->callback, s->done, s->build_error, s->adv_build_noreq,
8987 s->adv_build_nosg);
8988 ASC_PRT_NEXT();
8989
8990 len = asc_prt_line(cp, leftlen,
8991" exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
8992 s->exe_noerror, s->exe_busy, s->exe_error, s->exe_unknown);
8993 ASC_PRT_NEXT();
8994
8995 /*
8996 * Display data transfer statistics.
8997 */
8998 if (s->cont_cnt > 0) {
8999 len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
9000 ASC_PRT_NEXT();
9001
9002 len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
9003 s->cont_xfer/2,
9004 ASC_TENTHS(s->cont_xfer, 2));
9005 ASC_PRT_NEXT();
9006
9007 /* Contiguous transfer average size */
9008 len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
9009 (s->cont_xfer/2)/s->cont_cnt,
9010 ASC_TENTHS((s->cont_xfer/2), s->cont_cnt));
9011 ASC_PRT_NEXT();
9012 }
9013
9014 if (s->sg_cnt > 0) {
9015
9016 len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
9017 s->sg_cnt, s->sg_elem);
9018 ASC_PRT_NEXT();
9019
9020 len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
9021 s->sg_xfer/2,
9022 ASC_TENTHS(s->sg_xfer, 2));
9023 ASC_PRT_NEXT();
9024
9025 /* Scatter gather transfer statistics */
9026 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
9027 s->sg_elem/s->sg_cnt,
9028 ASC_TENTHS(s->sg_elem, s->sg_cnt));
9029 ASC_PRT_NEXT();
9030
9031 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
9032 (s->sg_xfer/2)/s->sg_elem,
9033 ASC_TENTHS((s->sg_xfer/2), s->sg_elem));
9034 ASC_PRT_NEXT();
9035
9036 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
9037 (s->sg_xfer/2)/s->sg_cnt,
9038 ASC_TENTHS((s->sg_xfer/2), s->sg_cnt));
9039 ASC_PRT_NEXT();
9040 }
9041
9042 /*
9043 * Display request queuing statistics.
9044 */
9045 len = asc_prt_line(cp, leftlen,
9046" Active and Waiting Request Queues (Time Unit: %d HZ):\n", HZ);
9047 ASC_PRT_NEXT();
9048
9049
9050 return totlen;
9051}
9052
9053/*
9054 * asc_prt_target_stats()
9055 *
9056 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
9057 * cf. asc_prt_line().
9058 *
9059 * This is separated from asc_prt_board_stats because a full set
9060 * of targets will overflow ASC_PRTBUF_SIZE.
9061 *
9062 * Return the number of characters copied into 'cp'. No more than
9063 * 'cplen' characters will be copied to 'cp'.
9064 */
9065STATIC int
9066asc_prt_target_stats(struct Scsi_Host *shp, int tgt_id, char *cp, int cplen)
9067{
9068 int leftlen;
9069 int totlen;
9070 int len;
9071 struct asc_stats *s;
9072 ushort chip_scsi_id;
9073 asc_board_t *boardp;
9074 asc_queue_t *active;
9075 asc_queue_t *waiting;
9076
9077 leftlen = cplen;
9078 totlen = len = 0;
9079
9080 boardp = ASC_BOARDP(shp);
9081 s = &boardp->asc_stats;
9082
9083 active = &ASC_BOARDP(shp)->active;
9084 waiting = &ASC_BOARDP(shp)->waiting;
9085
9086 if (ASC_NARROW_BOARD(boardp)) {
9087 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
9088 } else {
9089 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
9090 }
9091
9092 if ((chip_scsi_id == tgt_id) ||
9093 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(tgt_id)) == 0)) {
9094 return 0;
9095 }
9096
9097 do {
9098 if (active->q_tot_cnt[tgt_id] > 0 || waiting->q_tot_cnt[tgt_id] > 0) {
9099 len = asc_prt_line(cp, leftlen, " target %d\n", tgt_id);
9100 ASC_PRT_NEXT();
9101
9102 len = asc_prt_line(cp, leftlen,
9103" active: cnt [cur %d, max %d, tot %u], time [min %d, max %d, avg %lu.%01lu]\n",
9104 active->q_cur_cnt[tgt_id], active->q_max_cnt[tgt_id],
9105 active->q_tot_cnt[tgt_id],
9106 active->q_min_tim[tgt_id], active->q_max_tim[tgt_id],
9107 (active->q_tot_cnt[tgt_id] == 0) ? 0 :
9108 (active->q_tot_tim[tgt_id]/active->q_tot_cnt[tgt_id]),
9109 (active->q_tot_cnt[tgt_id] == 0) ? 0 :
9110 ASC_TENTHS(active->q_tot_tim[tgt_id],
9111 active->q_tot_cnt[tgt_id]));
9112 ASC_PRT_NEXT();
9113
9114 len = asc_prt_line(cp, leftlen,
9115" waiting: cnt [cur %d, max %d, tot %u], time [min %u, max %u, avg %lu.%01lu]\n",
9116 waiting->q_cur_cnt[tgt_id], waiting->q_max_cnt[tgt_id],
9117 waiting->q_tot_cnt[tgt_id],
9118 waiting->q_min_tim[tgt_id], waiting->q_max_tim[tgt_id],
9119 (waiting->q_tot_cnt[tgt_id] == 0) ? 0 :
9120 (waiting->q_tot_tim[tgt_id]/waiting->q_tot_cnt[tgt_id]),
9121 (waiting->q_tot_cnt[tgt_id] == 0) ? 0 :
9122 ASC_TENTHS(waiting->q_tot_tim[tgt_id],
9123 waiting->q_tot_cnt[tgt_id]));
9124 ASC_PRT_NEXT();
9125 }
9126 } while (0);
9127
9128 return totlen;
9129}
9130#endif /* CONFIG_PROC_FS */
9131#endif /* ADVANSYS_STATS */
9132
9133#ifdef ADVANSYS_DEBUG
9134/*
9135 * asc_prt_scsi_host()
9136 */
9137STATIC void
9138asc_prt_scsi_host(struct Scsi_Host *s)
9139{
9140 asc_board_t *boardp;
9141
9142 boardp = ASC_BOARDP(s);
9143
9144 printk("Scsi_Host at addr 0x%lx\n", (ulong) s);
9145 printk(
9146" host_busy %u, host_no %d, last_reset %d,\n",
9147 s->host_busy, s->host_no,
9148 (unsigned) s->last_reset);
9149
9150 printk(
9151" base 0x%lx, io_port 0x%lx, n_io_port %u, irq 0x%x,\n",
9152 (ulong) s->base, (ulong) s->io_port, s->n_io_port, s->irq);
9153
9154 printk(
9155" dma_channel %d, this_id %d, can_queue %d,\n",
9156 s->dma_channel, s->this_id, s->can_queue);
9157
9158 printk(
9159" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
9160 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
9161
9162 if (ASC_NARROW_BOARD(boardp)) {
9163 asc_prt_asc_dvc_var(&ASC_BOARDP(s)->dvc_var.asc_dvc_var);
9164 asc_prt_asc_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.asc_dvc_cfg);
9165 } else {
9166 asc_prt_adv_dvc_var(&ASC_BOARDP(s)->dvc_var.adv_dvc_var);
9167 asc_prt_adv_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.adv_dvc_cfg);
9168 }
9169}
9170
9171/*
9172 * asc_prt_scsi_cmnd()
9173 */
9174STATIC void
9175asc_prt_scsi_cmnd(struct scsi_cmnd *s)
9176{
9177 printk("struct scsi_cmnd at addr 0x%lx\n", (ulong) s);
9178
9179 printk(
9180" host 0x%lx, device 0x%lx, target %u, lun %u, channel %u,\n",
9181 (ulong) s->device->host, (ulong) s->device, s->device->id, s->device->lun,
9182 s->device->channel);
9183
9184 asc_prt_hex(" CDB", s->cmnd, s->cmd_len);
9185
9186 printk (
9187"sc_data_direction %u, resid %d\n",
9188 s->sc_data_direction, s->resid);
9189
9190 printk(
f5ad5614
CH		 9191" use_sg %u, sglist_len %u\n",
9192 s->use_sg, s->sglist_len);
1da177e4
LT		 9193
9194 printk(
c6295cdf
TH		 9195" serial_number 0x%x, retries %d, allowed %d\n",
9196 (unsigned) s->serial_number, s->retries, s->allowed);
1da177e4
LT		 9197
9198 printk(
b21a4138
JB		 9199" timeout_per_command %d\n",
9200 s->timeout_per_command);
1da177e4 9201
1da177e4
LT		 9202 printk(
9203" scsi_done 0x%lx, done 0x%lx, host_scribble 0x%lx, result 0x%x\n",
9204 (ulong) s->scsi_done, (ulong) s->done,
9205 (ulong) s->host_scribble, s->result);
9206
9207 printk(
9208" tag %u, pid %u\n",
9209 (unsigned) s->tag, (unsigned) s->pid);
9210}
9211
9212/*
9213 * asc_prt_asc_dvc_var()
9214 */
9215STATIC void
9216asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
9217{
9218 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong) h);
9219
9220 printk(
9221" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl %d,\n",
9222 h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
9223
9224 printk(
9225" bus_type %d, isr_callback 0x%lx, exe_callback 0x%lx, init_sdtr 0x%x,\n",
9226 h->bus_type, (ulong) h->isr_callback, (ulong) h->exe_callback,
9227 (unsigned) h->init_sdtr);
9228
9229 printk(
9230" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, chip_no 0x%x,\n",
9231 (unsigned) h->sdtr_done, (unsigned) h->use_tagged_qng,
9232 (unsigned) h->unit_not_ready, (unsigned) h->chip_no);
9233
9234 printk(
9235" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait %u,\n",
9236 (unsigned) h->queue_full_or_busy, (unsigned) h->start_motor,
9237 (unsigned) h->scsi_reset_wait);
9238
9239 printk(
9240" is_in_int %u, max_total_qng %u, cur_total_qng %u, in_critical_cnt %u,\n",
9241 (unsigned) h->is_in_int, (unsigned) h->max_total_qng,
9242 (unsigned) h->cur_total_qng, (unsigned) h->in_critical_cnt);
9243
9244 printk(
9245" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, pci_fix_asyn_xfer 0x%x,\n",
9246 (unsigned) h->last_q_shortage, (unsigned) h->init_state,
9247 (unsigned) h->no_scam, (unsigned) h->pci_fix_asyn_xfer);
9248
9249 printk(
9250" cfg 0x%lx, irq_no 0x%x\n",
9251 (ulong) h->cfg, (unsigned) h->irq_no);
9252}
9253
9254/*
9255 * asc_prt_asc_dvc_cfg()
9256 */
9257STATIC void
9258asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
9259{
9260 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong) h);
9261
9262 printk(
9263" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
9264 h->can_tagged_qng, h->cmd_qng_enabled);
9265 printk(
9266" disc_enable 0x%x, sdtr_enable 0x%x,\n",
9267 h->disc_enable, h->sdtr_enable);
9268
9269 printk(
9270" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, chip_version %d,\n",
9271 h->chip_scsi_id, h->isa_dma_speed, h->isa_dma_channel,
9272 h->chip_version);
9273
9274 printk(
9275" pci_device_id %d, lib_serial_no %u, lib_version %u, mcode_date 0x%x,\n",
9276 to_pci_dev(h->dev)->device, h->lib_serial_no, h->lib_version,
9277 h->mcode_date);
9278
9279 printk(
9280" mcode_version %d, overrun_buf 0x%lx\n",
9281 h->mcode_version, (ulong) h->overrun_buf);
9282}
9283
9284/*
9285 * asc_prt_asc_scsi_q()
9286 */
9287STATIC void
9288asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
9289{
9290 ASC_SG_HEAD *sgp;
9291 int i;
9292
9293 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong) q);
9294
9295 printk(
9296" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
9297 q->q2.target_ix, q->q1.target_lun,
9298 (ulong) q->q2.srb_ptr, q->q2.tag_code);
9299
9300 printk(
9301" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
9302 (ulong) le32_to_cpu(q->q1.data_addr),
9303 (ulong) le32_to_cpu(q->q1.data_cnt),
9304 (ulong) le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
9305
9306 printk(
9307" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
9308 (ulong) q->cdbptr, q->q2.cdb_len,
9309 (ulong) q->sg_head, q->q1.sg_queue_cnt);
9310
9311 if (q->sg_head) {
9312 sgp = q->sg_head;
9313 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong) sgp);
9314 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt, sgp->queue_cnt);
9315 for (i = 0; i < sgp->entry_cnt; i++) {
9316 printk(" [%u]: addr 0x%lx, bytes %lu\n",
9317 i, (ulong) le32_to_cpu(sgp->sg_list[i].addr),
9318 (ulong) le32_to_cpu(sgp->sg_list[i].bytes));
9319 }
9320
9321 }
9322}
9323
9324/*
9325 * asc_prt_asc_qdone_info()
9326 */
9327STATIC void
9328asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
9329{
9330 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong) q);
9331 printk(
9332" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
9333 (ulong) q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
9334 q->d2.tag_code);
9335 printk(
9336" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
9337 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
9338}
9339
9340/*
9341 * asc_prt_adv_dvc_var()
9342 *
9343 * Display an ADV_DVC_VAR structure.
9344 */
9345STATIC void
9346asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
9347{
9348 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong) h);
9349
9350 printk(
9351" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
9352 (ulong) h->iop_base, h->err_code, (unsigned) h->ultra_able);
9353
9354 printk(
9355" isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n",
9356 (ulong) h->isr_callback, (unsigned) h->sdtr_able,
9357 (unsigned) h->wdtr_able);
9358
9359 printk(
9360" start_motor 0x%x, scsi_reset_wait 0x%x, irq_no 0x%x,\n",
9361 (unsigned) h->start_motor,
9362 (unsigned) h->scsi_reset_wait, (unsigned) h->irq_no);
9363
9364 printk(
9365" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
9366 (unsigned) h->max_host_qng, (unsigned) h->max_dvc_qng,
9367 (ulong) h->carr_freelist);
9368
9369 printk(
9370" icq_sp 0x%lx, irq_sp 0x%lx\n",
9371 (ulong) h->icq_sp, (ulong) h->irq_sp);
9372
9373 printk(
9374" no_scam 0x%x, tagqng_able 0x%x\n",
9375 (unsigned) h->no_scam, (unsigned) h->tagqng_able);
9376
9377 printk(
9378" chip_scsi_id 0x%x, cfg 0x%lx\n",
9379 (unsigned) h->chip_scsi_id, (ulong) h->cfg);
9380}
9381
9382/*
9383 * asc_prt_adv_dvc_cfg()
9384 *
9385 * Display an ADV_DVC_CFG structure.
9386 */
9387STATIC void
9388asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
9389{
9390 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong) h);
9391
9392 printk(
9393" disc_enable 0x%x, termination 0x%x\n",
9394 h->disc_enable, h->termination);
9395
9396 printk(
9397" chip_version 0x%x, mcode_date 0x%x\n",
9398 h->chip_version, h->mcode_date);
9399
9400 printk(
9401" mcode_version 0x%x, pci_device_id 0x%x, lib_version %u\n",
9402 h->mcode_version, to_pci_dev(h->dev)->device, h->lib_version);
9403
9404 printk(
9405" control_flag 0x%x, pci_slot_info 0x%x\n",
9406 h->control_flag, h->pci_slot_info);
9407}
9408
9409/*
9410 * asc_prt_adv_scsi_req_q()
9411 *
9412 * Display an ADV_SCSI_REQ_Q structure.
9413 */
9414STATIC void
9415asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
9416{
9417 int sg_blk_cnt;
9418 struct asc_sg_block *sg_ptr;
9419
9420 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong) q);
9421
9422 printk(
9423" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
9424 q->target_id, q->target_lun, (ulong) q->srb_ptr, q->a_flag);
9425
9426 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
9427 q->cntl, (ulong) le32_to_cpu(q->data_addr), (ulong) q->vdata_addr);
9428
9429 printk(
9430" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
9431 (ulong) le32_to_cpu(q->data_cnt),
9432 (ulong) le32_to_cpu(q->sense_addr), q->sense_len);
9433
9434 printk(
9435" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
9436 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
9437
9438 printk(
9439" sg_working_ix 0x%x, target_cmd %u\n",
9440 q->sg_working_ix, q->target_cmd);
9441
9442 printk(
9443" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
9444 (ulong) le32_to_cpu(q->scsiq_rptr),
9445 (ulong) le32_to_cpu(q->sg_real_addr), (ulong) q->sg_list_ptr);
9446
9447 /* Display the request's ADV_SG_BLOCK structures. */
9448 if (q->sg_list_ptr != NULL)
9449 {
9450 sg_blk_cnt = 0;
9451 while (1) {
9452 /*
9453 * 'sg_ptr' is a physical address. Convert it to a virtual
9454 * address by indexing 'sg_blk_cnt' into the virtual address
9455 * array 'sg_list_ptr'.
9456 *
9457 * XXX - Assumes all SG physical blocks are virtually contiguous.
9458 */
9459 sg_ptr = &(((ADV_SG_BLOCK *) (q->sg_list_ptr))[sg_blk_cnt]);
9460 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
9461 if (sg_ptr->sg_ptr == 0)
9462 {
9463 break;
9464 }
9465 sg_blk_cnt++;
9466 }
9467 }
9468}
9469
9470/*
9471 * asc_prt_adv_sgblock()
9472 *
9473 * Display an ADV_SG_BLOCK structure.
9474 */
9475STATIC void
9476asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
9477{
9478 int i;
9479
9480 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
9481 (ulong) b, sgblockno);
9482 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
9483 b->sg_cnt, (ulong) le32_to_cpu(b->sg_ptr));
9484 ASC_ASSERT(b->sg_cnt <= NO_OF_SG_PER_BLOCK);
9485 if (b->sg_ptr != 0)
9486 {
9487 ASC_ASSERT(b->sg_cnt == NO_OF_SG_PER_BLOCK);
9488 }
9489 for (i = 0; i < b->sg_cnt; i++) {
9490 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
9491 i, (ulong) b->sg_list[i].sg_addr, (ulong) b->sg_list[i].sg_count);
9492 }
9493}
9494
9495/*
9496 * asc_prt_hex()
9497 *
9498 * Print hexadecimal output in 4 byte groupings 32 bytes
9499 * or 8 double-words per line.
9500 */
9501STATIC void
9502asc_prt_hex(char *f, uchar *s, int l)
9503{
9504 int i;
9505 int j;
9506 int k;
9507 int m;
9508
9509 printk("%s: (%d bytes)\n", f, l);
9510
9511 for (i = 0; i < l; i += 32) {
9512
9513 /* Display a maximum of 8 double-words per line. */
9514 if ((k = (l - i) / 4) >= 8) {
9515 k = 8;
9516 m = 0;
9517 } else {
9518 m = (l - i) % 4;
9519 }
9520
9521 for (j = 0; j < k; j++) {
9522 printk(" %2.2X%2.2X%2.2X%2.2X",
9523 (unsigned) s[i+(j*4)], (unsigned) s[i+(j*4)+1],
9524 (unsigned) s[i+(j*4)+2], (unsigned) s[i+(j*4)+3]);
9525 }
9526
9527 switch (m) {
9528 case 0:
9529 default:
9530 break;
9531 case 1:
9532 printk(" %2.2X",
9533 (unsigned) s[i+(j*4)]);
9534 break;
9535 case 2:
9536 printk(" %2.2X%2.2X",
9537 (unsigned) s[i+(j*4)],
9538 (unsigned) s[i+(j*4)+1]);
9539 break;
9540 case 3:
9541 printk(" %2.2X%2.2X%2.2X",
9542 (unsigned) s[i+(j*4)+1],
9543 (unsigned) s[i+(j*4)+2],
9544 (unsigned) s[i+(j*4)+3]);
9545 break;
9546 }
9547
9548 printk("\n");
9549 }
9550}
9551#endif /* ADVANSYS_DEBUG */
9552
9553/*
9554 * --- Asc Library Functions
9555 */
9556
9557STATIC ushort __init
9558AscGetEisaChipCfg(
9559 PortAddr iop_base)
9560{
9561 PortAddr eisa_cfg_iop;
9562
9563 eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9564 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
9565 return (inpw(eisa_cfg_iop));
9566}
9567
9568STATIC uchar __init
9569AscSetChipScsiID(
9570 PortAddr iop_base,
9571 uchar new_host_id
9572)
9573{
9574 ushort cfg_lsw;
9575
9576 if (AscGetChipScsiID(iop_base) == new_host_id) {
9577 return (new_host_id);
9578 }
9579 cfg_lsw = AscGetChipCfgLsw(iop_base);
9580 cfg_lsw &= 0xF8FF;
9581 cfg_lsw |= (ushort) ((new_host_id & ASC_MAX_TID) << 8);
9582 AscSetChipCfgLsw(iop_base, cfg_lsw);
9583 return (AscGetChipScsiID(iop_base));
9584}
9585
9586STATIC uchar __init
9587AscGetChipScsiCtrl(
9588 PortAddr iop_base)
9589{
9590 uchar sc;
9591
9592 AscSetBank(iop_base, 1);
9593 sc = inp(iop_base + IOP_REG_SC);
9594 AscSetBank(iop_base, 0);
9595 return (sc);
9596}
9597
9598STATIC uchar __init
9599AscGetChipVersion(
9600 PortAddr iop_base,
9601 ushort bus_type
9602)
9603{
9604 if ((bus_type & ASC_IS_EISA) != 0) {
9605 PortAddr eisa_iop;
9606 uchar revision;
9607 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9608 (PortAddr) ASC_EISA_REV_IOP_MASK;
9609 revision = inp(eisa_iop);
9610 return ((uchar) ((ASC_CHIP_MIN_VER_EISA - 1) + revision));
9611 }
9612 return (AscGetChipVerNo(iop_base));
9613}
9614
9615STATIC ushort __init
9616AscGetChipBusType(
9617 PortAddr iop_base)
9618{
9619 ushort chip_ver;
9620
9621 chip_ver = AscGetChipVerNo(iop_base);
9622 if (
9623 (chip_ver >= ASC_CHIP_MIN_VER_VL)
9624 && (chip_ver <= ASC_CHIP_MAX_VER_VL)
9625) {
9626 if (
9627 ((iop_base & 0x0C30) == 0x0C30)
9628 || ((iop_base & 0x0C50) == 0x0C50)
9629) {
9630 return (ASC_IS_EISA);
9631 }
9632 return (ASC_IS_VL);
9633 }
9634 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) &&
9635 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) {
9636 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) {
9637 return (ASC_IS_ISAPNP);
9638 }
9639 return (ASC_IS_ISA);
9640 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) &&
9641 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) {
9642 return (ASC_IS_PCI);
9643 }
9644 return (0);
9645}
9646
9647STATIC ASC_DCNT
9648AscLoadMicroCode(
9649 PortAddr iop_base,
9650 ushort s_addr,
9651 uchar *mcode_buf,
9652 ushort mcode_size
9653)
9654{
9655 ASC_DCNT chksum;
9656 ushort mcode_word_size;
9657 ushort mcode_chksum;
9658
9659 /* Write the microcode buffer starting at LRAM address 0. */
9660 mcode_word_size = (ushort) (mcode_size >> 1);
9661 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
9662 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
9663
9664 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
9665 ASC_DBG1(1, "AscLoadMicroCode: chksum 0x%lx\n", (ulong) chksum);
9666 mcode_chksum = (ushort) AscMemSumLramWord(iop_base,
9667 (ushort) ASC_CODE_SEC_BEG,
9668 (ushort) ((mcode_size - s_addr - (ushort) ASC_CODE_SEC_BEG) / 2));
9669 ASC_DBG1(1, "AscLoadMicroCode: mcode_chksum 0x%lx\n",
9670 (ulong) mcode_chksum);
9671 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
9672 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
9673 return (chksum);
9674}
9675
9676STATIC int
9677AscFindSignature(
9678 PortAddr iop_base
9679)
9680{
9681 ushort sig_word;
9682
9683 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureByte(0x%x) 0x%x\n",
9684 iop_base, AscGetChipSignatureByte(iop_base));
9685 if (AscGetChipSignatureByte(iop_base) == (uchar) ASC_1000_ID1B) {
9686 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureWord(0x%x) 0x%x\n",
9687 iop_base, AscGetChipSignatureWord(iop_base));
9688 sig_word = AscGetChipSignatureWord(iop_base);
9689 if ((sig_word == (ushort) ASC_1000_ID0W) ||
9690 (sig_word == (ushort) ASC_1000_ID0W_FIX)) {
9691 return (1);
9692 }
9693 }
9694 return (0);
9695}
9696
9697STATIC PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __initdata =
9698{
9699 0x100, ASC_IOADR_1, 0x120, ASC_IOADR_2, 0x140, ASC_IOADR_3, ASC_IOADR_4,
9700 ASC_IOADR_5, ASC_IOADR_6, ASC_IOADR_7, ASC_IOADR_8
9701};
9702
9703#ifdef CONFIG_ISA
9704STATIC uchar _isa_pnp_inited __initdata = 0;
9705
9706STATIC PortAddr __init
9707AscSearchIOPortAddr(
9708 PortAddr iop_beg,
9709 ushort bus_type)
9710{
9711 if (bus_type & ASC_IS_VL) {
9712 while ((iop_beg = AscSearchIOPortAddr11(iop_beg)) != 0) {
9713 if (AscGetChipVersion(iop_beg, bus_type) <= ASC_CHIP_MAX_VER_VL) {
9714 return (iop_beg);
9715 }
9716 }
9717 return (0);
9718 }
9719 if (bus_type & ASC_IS_ISA) {
9720 if (_isa_pnp_inited == 0) {
9721 AscSetISAPNPWaitForKey();
9722 _isa_pnp_inited++;
9723 }
9724 while ((iop_beg = AscSearchIOPortAddr11(iop_beg)) != 0) {
9725 if ((AscGetChipVersion(iop_beg, bus_type) & ASC_CHIP_VER_ISA_BIT) != 0) {
9726 return (iop_beg);
9727 }
9728 }
9729 return (0);
9730 }
9731 if (bus_type & ASC_IS_EISA) {
9732 if ((iop_beg = AscSearchIOPortAddrEISA(iop_beg)) != 0) {
9733 return (iop_beg);
9734 }
9735 return (0);
9736 }
9737 return (0);
9738}
9739
9740STATIC PortAddr __init
9741AscSearchIOPortAddr11(
9742 PortAddr s_addr
9743)
9744{
9745 int i;
9746 PortAddr iop_base;
9747
9748 for (i = 0; i < ASC_IOADR_TABLE_MAX_IX; i++) {
9749 if (_asc_def_iop_base[i] > s_addr) {
9750 break;
9751 }
9752 }
9753 for (; i < ASC_IOADR_TABLE_MAX_IX; i++) {
9754 iop_base = _asc_def_iop_base[i];
9755 if (check_region(iop_base, ASC_IOADR_GAP) != 0) {
9756 ASC_DBG1(1,
9757 "AscSearchIOPortAddr11: check_region() failed I/O port 0x%x\n",
9758 iop_base);
9759 continue;
9760 }
9761 ASC_DBG1(1, "AscSearchIOPortAddr11: probing I/O port 0x%x\n", iop_base);
9762 if (AscFindSignature(iop_base)) {
9763 return (iop_base);
9764 }
9765 }
9766 return (0);
9767}
9768
9769STATIC void __init
9770AscSetISAPNPWaitForKey(void)
9771{
9772 outp(ASC_ISA_PNP_PORT_ADDR, 0x02);
9773 outp(ASC_ISA_PNP_PORT_WRITE, 0x02);
9774 return;
9775}
9776#endif /* CONFIG_ISA */
9777
9778STATIC void __init
9779AscToggleIRQAct(
9780 PortAddr iop_base
9781)
9782{
9783 AscSetChipStatus(iop_base, CIW_IRQ_ACT);
9784 AscSetChipStatus(iop_base, 0);
9785 return;
9786}
9787
9788STATIC uchar __init
9789AscGetChipIRQ(
9790 PortAddr iop_base,
9791 ushort bus_type)
9792{
9793 ushort cfg_lsw;
9794 uchar chip_irq;
9795
9796 if ((bus_type & ASC_IS_EISA) != 0) {
9797 cfg_lsw = AscGetEisaChipCfg(iop_base);
9798 chip_irq = (uchar) (((cfg_lsw >> 8) & 0x07) + 10);
9799 if ((chip_irq == 13) || (chip_irq > 15)) {
9800 return (0);
9801 }
9802 return (chip_irq);
9803 }
9804 if ((bus_type & ASC_IS_VL) != 0) {
9805 cfg_lsw = AscGetChipCfgLsw(iop_base);
9806 chip_irq = (uchar) (((cfg_lsw >> 2) & 0x07));
9807 if ((chip_irq == 0) ||
9808 (chip_irq == 4) ||
9809 (chip_irq == 7)) {
9810 return (0);
9811 }
9812 return ((uchar) (chip_irq + (ASC_MIN_IRQ_NO - 1)));
9813 }
9814 cfg_lsw = AscGetChipCfgLsw(iop_base);
9815 chip_irq = (uchar) (((cfg_lsw >> 2) & 0x03));
9816 if (chip_irq == 3)
9817 chip_irq += (uchar) 2;
9818 return ((uchar) (chip_irq + ASC_MIN_IRQ_NO));
9819}
9820
9821STATIC uchar __init
9822AscSetChipIRQ(
9823 PortAddr iop_base,
9824 uchar irq_no,
9825 ushort bus_type)
9826{
9827 ushort cfg_lsw;
9828
9829 if ((bus_type & ASC_IS_VL) != 0) {
9830 if (irq_no != 0) {
9831 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) {
9832 irq_no = 0;
9833 } else {
9834 irq_no -= (uchar) ((ASC_MIN_IRQ_NO - 1));
9835 }
9836 }
9837 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFE3);
9838 cfg_lsw |= (ushort) 0x0010;
9839 AscSetChipCfgLsw(iop_base, cfg_lsw);
9840 AscToggleIRQAct(iop_base);
9841 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFE0);
9842 cfg_lsw |= (ushort) ((irq_no & 0x07) << 2);
9843 AscSetChipCfgLsw(iop_base, cfg_lsw);
9844 AscToggleIRQAct(iop_base);
9845 return (AscGetChipIRQ(iop_base, bus_type));
9846 }
9847 if ((bus_type & (ASC_IS_ISA)) != 0) {
9848 if (irq_no == 15)
9849 irq_no -= (uchar) 2;
9850 irq_no -= (uchar) ASC_MIN_IRQ_NO;
9851 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFF3);
9852 cfg_lsw |= (ushort) ((irq_no & 0x03) << 2);
9853 AscSetChipCfgLsw(iop_base, cfg_lsw);
9854 return (AscGetChipIRQ(iop_base, bus_type));
9855 }
9856 return (0);
9857}
9858
9859#ifdef CONFIG_ISA
9860STATIC void __init
9861AscEnableIsaDma(
9862 uchar dma_channel)
9863{
9864 if (dma_channel < 4) {
9865 outp(0x000B, (ushort) (0xC0 | dma_channel));
9866 outp(0x000A, dma_channel);
9867 } else if (dma_channel < 8) {
9868 outp(0x00D6, (ushort) (0xC0 | (dma_channel - 4)));
9869 outp(0x00D4, (ushort) (dma_channel - 4));
9870 }
9871 return;
9872}
9873#endif /* CONFIG_ISA */
9874
9875STATIC int
9876AscIsrChipHalted(
9877 ASC_DVC_VAR *asc_dvc
9878)
9879{
9880 EXT_MSG ext_msg;
9881 EXT_MSG out_msg;
9882 ushort halt_q_addr;
9883 int sdtr_accept;
9884 ushort int_halt_code;
9885 ASC_SCSI_BIT_ID_TYPE scsi_busy;
9886 ASC_SCSI_BIT_ID_TYPE target_id;
9887 PortAddr iop_base;
9888 uchar tag_code;
9889 uchar q_status;
9890 uchar halt_qp;
9891 uchar sdtr_data;
9892 uchar target_ix;
9893 uchar q_cntl, tid_no;
9894 uchar cur_dvc_qng;
9895 uchar asyn_sdtr;
9896 uchar scsi_status;
9897 asc_board_t *boardp;
9898
9899 ASC_ASSERT(asc_dvc->drv_ptr != NULL);
9900 boardp = asc_dvc->drv_ptr;
9901
9902 iop_base = asc_dvc->iop_base;
9903 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
9904
9905 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
9906 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
9907 target_ix = AscReadLramByte(iop_base,
9908 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TARGET_IX));
9909 q_cntl = AscReadLramByte(iop_base,
9910 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL));
9911 tid_no = ASC_TIX_TO_TID(target_ix);
9912 target_id = (uchar) ASC_TID_TO_TARGET_ID(tid_no);
9913 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9914 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
9915 } else {
9916 asyn_sdtr = 0;
9917 }
9918 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
9919 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9920 AscSetChipSDTR(iop_base, 0, tid_no);
9921 boardp->sdtr_data[tid_no] = 0;
9922 }
9923 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9924 return (0);
9925 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
9926 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9927 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9928 boardp->sdtr_data[tid_no] = asyn_sdtr;
9929 }
9930 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9931 return (0);
9932 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
9933
9934 AscMemWordCopyPtrFromLram(iop_base,
9935 ASCV_MSGIN_BEG,
9936 (uchar *) &ext_msg,
9937 sizeof(EXT_MSG) >> 1);
9938
9939 if (ext_msg.msg_type == MS_EXTEND &&
9940 ext_msg.msg_req == MS_SDTR_CODE &&
9941 ext_msg.msg_len == MS_SDTR_LEN) {
9942 sdtr_accept = TRUE;
9943 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
9944
9945 sdtr_accept = FALSE;
9946 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
9947 }
9948 if ((ext_msg.xfer_period <
9949 asc_dvc->sdtr_period_tbl[asc_dvc->host_init_sdtr_index]) ||
9950 (ext_msg.xfer_period >
9951 asc_dvc->sdtr_period_tbl[asc_dvc->max_sdtr_index])) {
9952 sdtr_accept = FALSE;
9953 ext_msg.xfer_period =
9954 asc_dvc->sdtr_period_tbl[asc_dvc->host_init_sdtr_index];
9955 }
9956 if (sdtr_accept) {
9957 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
9958 ext_msg.req_ack_offset);
9959 if ((sdtr_data == 0xFF)) {
9960
9961 q_cntl |= QC_MSG_OUT;
9962 asc_dvc->init_sdtr &= ~target_id;
9963 asc_dvc->sdtr_done &= ~target_id;
9964 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9965 boardp->sdtr_data[tid_no] = asyn_sdtr;
9966 }
9967 }
9968 if (ext_msg.req_ack_offset == 0) {
9969
9970 q_cntl &= ~QC_MSG_OUT;
9971 asc_dvc->init_sdtr &= ~target_id;
9972 asc_dvc->sdtr_done &= ~target_id;
9973 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9974 } else {
9975 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
9976
9977 q_cntl &= ~QC_MSG_OUT;
9978 asc_dvc->sdtr_done |= target_id;
9979 asc_dvc->init_sdtr |= target_id;
9980 asc_dvc->pci_fix_asyn_xfer &= ~target_id;
9981 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
9982 ext_msg.req_ack_offset);
9983 AscSetChipSDTR(iop_base, sdtr_data, tid_no);
9984 boardp->sdtr_data[tid_no] = sdtr_data;
9985 } else {
9986
9987 q_cntl |= QC_MSG_OUT;
9988 AscMsgOutSDTR(asc_dvc,
9989 ext_msg.xfer_period,
9990 ext_msg.req_ack_offset);
9991 asc_dvc->pci_fix_asyn_xfer &= ~target_id;
9992 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
9993 ext_msg.req_ack_offset);
9994 AscSetChipSDTR(iop_base, sdtr_data, tid_no);
9995 boardp->sdtr_data[tid_no] = sdtr_data;
9996 asc_dvc->sdtr_done |= target_id;
9997 asc_dvc->init_sdtr |= target_id;
9998 }
9999 }
10000
10001 AscWriteLramByte(iop_base,
10002 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10003 q_cntl);
10004 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10005 return (0);
10006 } else if (ext_msg.msg_type == MS_EXTEND &&
10007 ext_msg.msg_req == MS_WDTR_CODE &&
10008 ext_msg.msg_len == MS_WDTR_LEN) {
10009
10010 ext_msg.wdtr_width = 0;
10011 AscMemWordCopyPtrToLram(iop_base,
10012 ASCV_MSGOUT_BEG,
10013 (uchar *) &ext_msg,
10014 sizeof(EXT_MSG) >> 1);
10015 q_cntl |= QC_MSG_OUT;
10016 AscWriteLramByte(iop_base,
10017 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10018 q_cntl);
10019 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10020 return (0);
10021 } else {
10022
10023 ext_msg.msg_type = MESSAGE_REJECT;
10024 AscMemWordCopyPtrToLram(iop_base,
10025 ASCV_MSGOUT_BEG,
10026 (uchar *) &ext_msg,
10027 sizeof(EXT_MSG) >> 1);
10028 q_cntl |= QC_MSG_OUT;
10029 AscWriteLramByte(iop_base,
10030 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10031 q_cntl);
10032 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10033 return (0);
10034 }
10035 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
10036
10037 q_cntl |= QC_REQ_SENSE;
10038
10039 if ((asc_dvc->init_sdtr & target_id) != 0) {
10040
10041 asc_dvc->sdtr_done &= ~target_id;
10042
10043 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10044 q_cntl |= QC_MSG_OUT;
10045 AscMsgOutSDTR(asc_dvc,
10046 asc_dvc->sdtr_period_tbl[(sdtr_data >> 4) &
10047 (uchar) (asc_dvc->max_sdtr_index - 1)],
10048 (uchar) (sdtr_data & (uchar) ASC_SYN_MAX_OFFSET));
10049 }
10050
10051 AscWriteLramByte(iop_base,
10052 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10053 q_cntl);
10054
10055 tag_code = AscReadLramByte(iop_base,
10056 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TAG_CODE));
10057 tag_code &= 0xDC;
10058 if (
10059 (asc_dvc->pci_fix_asyn_xfer & target_id)
10060 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
10061) {
10062
10063 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
10064 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
10065
10066 }
10067 AscWriteLramByte(iop_base,
10068 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TAG_CODE),
10069 tag_code);
10070
10071 q_status = AscReadLramByte(iop_base,
10072 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_STATUS));
10073 q_status |= (QS_READY | QS_BUSY);
10074 AscWriteLramByte(iop_base,
10075 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10076 q_status);
10077
10078 scsi_busy = AscReadLramByte(iop_base,
10079 (ushort) ASCV_SCSIBUSY_B);
10080 scsi_busy &= ~target_id;
10081 AscWriteLramByte(iop_base, (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10082
10083 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10084 return (0);
10085 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
10086
10087 AscMemWordCopyPtrFromLram(iop_base,
10088 ASCV_MSGOUT_BEG,
10089 (uchar *) &out_msg,
10090 sizeof(EXT_MSG) >> 1);
10091
10092 if ((out_msg.msg_type == MS_EXTEND) &&
10093 (out_msg.msg_len == MS_SDTR_LEN) &&
10094 (out_msg.msg_req == MS_SDTR_CODE)) {
10095
10096 asc_dvc->init_sdtr &= ~target_id;
10097 asc_dvc->sdtr_done &= ~target_id;
10098 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
10099 boardp->sdtr_data[tid_no] = asyn_sdtr;
10100 }
10101 q_cntl &= ~QC_MSG_OUT;
10102 AscWriteLramByte(iop_base,
10103 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10104 q_cntl);
10105 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10106 return (0);
10107 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
10108
10109 scsi_status = AscReadLramByte(iop_base,
10110 (ushort) ((ushort) halt_q_addr + (ushort) ASC_SCSIQ_SCSI_STATUS));
10111 cur_dvc_qng = AscReadLramByte(iop_base,
10112 (ushort) ((ushort) ASC_QADR_BEG + (ushort) target_ix));
10113 if ((cur_dvc_qng > 0) &&
10114 (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
10115
10116 scsi_busy = AscReadLramByte(iop_base,
10117 (ushort) ASCV_SCSIBUSY_B);
10118 scsi_busy |= target_id;
10119 AscWriteLramByte(iop_base,
10120 (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10121 asc_dvc->queue_full_or_busy |= target_id;
10122
10123 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
10124 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
10125 cur_dvc_qng -= 1;
10126 asc_dvc->max_dvc_qng[tid_no] = cur_dvc_qng;
10127
10128 AscWriteLramByte(iop_base,
10129 (ushort) ((ushort) ASCV_MAX_DVC_QNG_BEG +
10130 (ushort) tid_no),
10131 cur_dvc_qng);
10132
10133 /*
10134 * Set the device queue depth to the number of
10135 * active requests when the QUEUE FULL condition
10136 * was encountered.
10137 */
10138 boardp->queue_full |= target_id;
10139 boardp->queue_full_cnt[tid_no] = cur_dvc_qng;
10140 }
10141 }
10142 }
10143 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10144 return (0);
10145 }
10146#if CC_VERY_LONG_SG_LIST
10147 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC)
10148 {
10149 uchar q_no;
10150 ushort q_addr;
10151 uchar sg_wk_q_no;
10152 uchar first_sg_wk_q_no;
10153 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
10154 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
10155 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
10156 ushort sg_list_dwords;
10157 ushort sg_entry_cnt;
10158 uchar next_qp;
10159 int i;
10160
10161 q_no = AscReadLramByte(iop_base, (ushort) ASCV_REQ_SG_LIST_QP);
10162 if (q_no == ASC_QLINK_END)
10163 {
10164 return(0);
10165 }
10166
10167 q_addr = ASC_QNO_TO_QADDR(q_no);
10168
10169 /*
10170 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
10171 * structure pointer using a macro provided by the driver.
10172 * The ASC_SCSI_REQ pointer provides a pointer to the
10173 * host ASC_SG_HEAD structure.
10174 */
10175 /* Read request's SRB pointer. */
10176 scsiq = (ASC_SCSI_Q *)
10177 ASC_SRB2SCSIQ(
10178 ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
10179 (ushort) (q_addr + ASC_SCSIQ_D_SRBPTR))));
10180
10181 /*
10182 * Get request's first and working SG queue.
10183 */
10184 sg_wk_q_no = AscReadLramByte(iop_base,
10185 (ushort) (q_addr + ASC_SCSIQ_B_SG_WK_QP));
10186
10187 first_sg_wk_q_no = AscReadLramByte(iop_base,
10188 (ushort) (q_addr + ASC_SCSIQ_B_FIRST_SG_WK_QP));
10189
10190 /*
10191 * Reset request's working SG queue back to the
10192 * first SG queue.
10193 */
10194 AscWriteLramByte(iop_base,
10195 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_SG_WK_QP),
10196 first_sg_wk_q_no);
10197
10198 sg_head = scsiq->sg_head;
10199
10200 /*
10201 * Set sg_entry_cnt to the number of SG elements
10202 * that will be completed on this interrupt.
10203 *
10204 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
10205 * SG elements. The data_cnt and data_addr fields which
10206 * add 1 to the SG element capacity are not used when
10207 * restarting SG handling after a halt.
10208 */
10209 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1))
10210 {
10211 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
10212
10213 /*
10214 * Keep track of remaining number of SG elements that will
10215 * need to be handled on the next interrupt.
10216 */
10217 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
10218 } else
10219 {
10220 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
10221 scsiq->remain_sg_entry_cnt = 0;
10222 }
10223
10224 /*
10225 * Copy SG elements into the list of allocated SG queues.
10226 *
10227 * Last index completed is saved in scsiq->next_sg_index.
10228 */
10229 next_qp = first_sg_wk_q_no;
10230 q_addr = ASC_QNO_TO_QADDR(next_qp);
10231 scsi_sg_q.sg_head_qp = q_no;
10232 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10233 for( i = 0; i < sg_head->queue_cnt; i++)
10234 {
10235 scsi_sg_q.seq_no = i + 1;
10236 if (sg_entry_cnt > ASC_SG_LIST_PER_Q)
10237 {
10238 sg_list_dwords = (uchar) (ASC_SG_LIST_PER_Q * 2);
10239 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10240 /*
10241 * After very first SG queue RISC FW uses next
10242 * SG queue first element then checks sg_list_cnt
10243 * against zero and then decrements, so set
10244 * sg_list_cnt 1 less than number of SG elements
10245 * in each SG queue.
10246 */
10247 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
10248 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
10249 } else {
10250 /*
10251 * This is the last SG queue in the list of
10252 * allocated SG queues. If there are more
10253 * SG elements than will fit in the allocated
10254 * queues, then set the QCSG_SG_XFER_MORE flag.
10255 */
10256 if (scsiq->remain_sg_entry_cnt != 0)
10257 {
10258 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10259 } else
10260 {
10261 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10262 }
10263 /* equals sg_entry_cnt * 2 */
10264 sg_list_dwords = sg_entry_cnt << 1;
10265 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
10266 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
10267 sg_entry_cnt = 0;
10268 }
10269
10270 scsi_sg_q.q_no = next_qp;
10271 AscMemWordCopyPtrToLram(iop_base,
10272 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10273 (uchar *) &scsi_sg_q,
10274 sizeof(ASC_SG_LIST_Q) >> 1);
10275
10276 AscMemDWordCopyPtrToLram(iop_base,
10277 q_addr + ASC_SGQ_LIST_BEG,
10278 (uchar *) &sg_head->sg_list[scsiq->next_sg_index],
10279 sg_list_dwords);
10280
10281 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
10282
10283 /*
10284 * If the just completed SG queue contained the
10285 * last SG element, then no more SG queues need
10286 * to be written.
10287 */
10288 if (scsi_sg_q.cntl & QCSG_SG_XFER_END)
10289 {
10290 break;
10291 }
10292
10293 next_qp = AscReadLramByte( iop_base,
10294 ( ushort )( q_addr+ASC_SCSIQ_B_FWD ) );
10295 q_addr = ASC_QNO_TO_QADDR( next_qp );
10296 }
10297
10298 /*
10299 * Clear the halt condition so the RISC will be restarted
10300 * after the return.
10301 */
10302 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10303 return(0);
10304 }
10305#endif /* CC_VERY_LONG_SG_LIST */
10306 return (0);
10307}
10308
10309STATIC uchar
10310_AscCopyLramScsiDoneQ(
10311 PortAddr iop_base,
10312 ushort q_addr,
10313 ASC_QDONE_INFO * scsiq,
10314 ASC_DCNT max_dma_count
10315)
10316{
10317 ushort _val;
10318 uchar sg_queue_cnt;
10319
10320 DvcGetQinfo(iop_base,
10321 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
10322 (uchar *) scsiq,
10323 (sizeof (ASC_SCSIQ_2) + sizeof (ASC_SCSIQ_3)) / 2);
10324
10325 _val = AscReadLramWord(iop_base,
10326 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS));
10327 scsiq->q_status = (uchar) _val;
10328 scsiq->q_no = (uchar) (_val >> 8);
10329 _val = AscReadLramWord(iop_base,
10330 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_CNTL));
10331 scsiq->cntl = (uchar) _val;
10332 sg_queue_cnt = (uchar) (_val >> 8);
10333 _val = AscReadLramWord(iop_base,
10334 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_SENSE_LEN));
10335 scsiq->sense_len = (uchar) _val;
10336 scsiq->extra_bytes = (uchar) (_val >> 8);
10337
10338 /*
10339 * Read high word of remain bytes from alternate location.
10340 */
10341 scsiq->remain_bytes = (((ADV_DCNT) AscReadLramWord( iop_base,
10342 (ushort) (q_addr+ (ushort) ASC_SCSIQ_W_ALT_DC1))) << 16);
10343 /*
10344 * Read low word of remain bytes from original location.
10345 */
10346 scsiq->remain_bytes += AscReadLramWord(iop_base,
10347 (ushort) (q_addr+ (ushort) ASC_SCSIQ_DW_REMAIN_XFER_CNT));
10348
10349 scsiq->remain_bytes &= max_dma_count;
10350 return (sg_queue_cnt);
10351}
10352
10353STATIC int
10354AscIsrQDone(
10355 ASC_DVC_VAR *asc_dvc
10356)
10357{
10358 uchar next_qp;
10359 uchar n_q_used;
10360 uchar sg_list_qp;
10361 uchar sg_queue_cnt;
10362 uchar q_cnt;
10363 uchar done_q_tail;
10364 uchar tid_no;
10365 ASC_SCSI_BIT_ID_TYPE scsi_busy;
10366 ASC_SCSI_BIT_ID_TYPE target_id;
10367 PortAddr iop_base;
10368 ushort q_addr;
10369 ushort sg_q_addr;
10370 uchar cur_target_qng;
10371 ASC_QDONE_INFO scsiq_buf;
10372 ASC_QDONE_INFO *scsiq;
10373 int false_overrun;
10374 ASC_ISR_CALLBACK asc_isr_callback;
10375
10376 iop_base = asc_dvc->iop_base;
10377 asc_isr_callback = asc_dvc->isr_callback;
10378 n_q_used = 1;
10379 scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
10380 done_q_tail = (uchar) AscGetVarDoneQTail(iop_base);
10381 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
10382 next_qp = AscReadLramByte(iop_base,
10383 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_FWD));
10384 if (next_qp != ASC_QLINK_END) {
10385 AscPutVarDoneQTail(iop_base, next_qp);
10386 q_addr = ASC_QNO_TO_QADDR(next_qp);
10387 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
10388 asc_dvc->max_dma_count);
10389 AscWriteLramByte(iop_base,
10390 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10391 (uchar) (scsiq->q_status & (uchar) ~ (QS_READY | QS_ABORTED)));
10392 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
10393 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
10394 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
10395 sg_q_addr = q_addr;
10396 sg_list_qp = next_qp;
10397 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
10398 sg_list_qp = AscReadLramByte(iop_base,
10399 (ushort) (sg_q_addr + (ushort) ASC_SCSIQ_B_FWD));
10400 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
10401 if (sg_list_qp == ASC_QLINK_END) {
10402 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_SG_Q_LINKS);
10403 scsiq->d3.done_stat = QD_WITH_ERROR;
10404 scsiq->d3.host_stat = QHSTA_D_QDONE_SG_LIST_CORRUPTED;
10405 goto FATAL_ERR_QDONE;
10406 }
10407 AscWriteLramByte(iop_base,
10408 (ushort) (sg_q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10409 QS_FREE);
10410 }
10411 n_q_used = sg_queue_cnt + 1;
10412 AscPutVarDoneQTail(iop_base, sg_list_qp);
10413 }
10414 if (asc_dvc->queue_full_or_busy & target_id) {
10415 cur_target_qng = AscReadLramByte(iop_base,
10416 (ushort) ((ushort) ASC_QADR_BEG + (ushort) scsiq->d2.target_ix));
10417 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
10418 scsi_busy = AscReadLramByte(iop_base,
10419 (ushort) ASCV_SCSIBUSY_B);
10420 scsi_busy &= ~target_id;
10421 AscWriteLramByte(iop_base,
10422 (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10423 asc_dvc->queue_full_or_busy &= ~target_id;
10424 }
10425 }
10426 if (asc_dvc->cur_total_qng >= n_q_used) {
10427 asc_dvc->cur_total_qng -= n_q_used;
10428 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
10429 asc_dvc->cur_dvc_qng[tid_no]--;
10430 }
10431 } else {
10432 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
10433 scsiq->d3.done_stat = QD_WITH_ERROR;
10434 goto FATAL_ERR_QDONE;
10435 }
10436 if ((scsiq->d2.srb_ptr == 0UL) ||
10437 ((scsiq->q_status & QS_ABORTED) != 0)) {
10438 return (0x11);
10439 } else if (scsiq->q_status == QS_DONE) {
10440 false_overrun = FALSE;
10441 if (scsiq->extra_bytes != 0) {
10442 scsiq->remain_bytes += (ADV_DCNT) scsiq->extra_bytes;
10443 }
10444 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
10445 if (scsiq->d3.host_stat == QHSTA_M_DATA_OVER_RUN) {
10446 if ((scsiq->cntl & (QC_DATA_IN | QC_DATA_OUT)) == 0) {
10447 scsiq->d3.done_stat = QD_NO_ERROR;
10448 scsiq->d3.host_stat = QHSTA_NO_ERROR;
10449 } else if (false_overrun) {
10450 scsiq->d3.done_stat = QD_NO_ERROR;
10451 scsiq->d3.host_stat = QHSTA_NO_ERROR;
10452 }
10453 } else if (scsiq->d3.host_stat ==
10454 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
10455 AscStopChip(iop_base);
10456 AscSetChipControl(iop_base,
10457 (uchar) (CC_SCSI_RESET | CC_HALT));
10458 DvcDelayNanoSecond(asc_dvc, 60000);
10459 AscSetChipControl(iop_base, CC_HALT);
10460 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
10461 AscSetChipStatus(iop_base, 0);
10462 AscSetChipControl(iop_base, 0);
10463 }
10464 }
10465 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
10466 (*asc_isr_callback) (asc_dvc, scsiq);
10467 } else {
10468 if ((AscReadLramByte(iop_base,
10469 (ushort) (q_addr + (ushort) ASC_SCSIQ_CDB_BEG)) ==
10470 START_STOP)) {
10471 asc_dvc->unit_not_ready &= ~target_id;
10472 if (scsiq->d3.done_stat != QD_NO_ERROR) {
10473 asc_dvc->start_motor &= ~target_id;
10474 }
10475 }
10476 }
10477 return (1);
10478 } else {
10479 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
10480 FATAL_ERR_QDONE:
10481 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
10482 (*asc_isr_callback) (asc_dvc, scsiq);
10483 }
10484 return (0x80);
10485 }
10486 }
10487 return (0);
10488}
10489
10490STATIC int
10491AscISR(
10492 ASC_DVC_VAR *asc_dvc
10493)
10494{
10495 ASC_CS_TYPE chipstat;
10496 PortAddr iop_base;
10497 ushort saved_ram_addr;
10498 uchar ctrl_reg;
10499 uchar saved_ctrl_reg;
10500 int int_pending;
10501 int status;
10502 uchar host_flag;
10503
10504 iop_base = asc_dvc->iop_base;
10505 int_pending = FALSE;
10506
10507 if (AscIsIntPending(iop_base) == 0)
10508 {
10509 return int_pending;
10510 }
10511
10512 if (((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0)
10513 || (asc_dvc->isr_callback == 0)
10514) {
10515 return (ERR);
10516 }
10517 if (asc_dvc->in_critical_cnt != 0) {
10518 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
10519 return (ERR);
10520 }
10521 if (asc_dvc->is_in_int) {
10522 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
10523 return (ERR);
10524 }
10525 asc_dvc->is_in_int = TRUE;
10526 ctrl_reg = AscGetChipControl(iop_base);
10527 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
10528 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
10529 chipstat = AscGetChipStatus(iop_base);
10530 if (chipstat & CSW_SCSI_RESET_LATCH) {
10531 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
10532 int i = 10;
10533 int_pending = TRUE;
10534 asc_dvc->sdtr_done = 0;
10535 saved_ctrl_reg &= (uchar) (~CC_HALT);
10536 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) &&
10537 (i-- > 0))
10538 {
10539 DvcSleepMilliSecond(100);
10540 }
10541 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
10542 AscSetChipControl(iop_base, CC_HALT);
10543 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
10544 AscSetChipStatus(iop_base, 0);
10545 chipstat = AscGetChipStatus(iop_base);
10546 }
10547 }
10548 saved_ram_addr = AscGetChipLramAddr(iop_base);
10549 host_flag = AscReadLramByte(iop_base,
10550 ASCV_HOST_FLAG_B) & (uchar) (~ASC_HOST_FLAG_IN_ISR);
10551 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
10552 (uchar) (host_flag | (uchar) ASC_HOST_FLAG_IN_ISR));
10553 if ((chipstat & CSW_INT_PENDING)
10554 || (int_pending)
10555) {
10556 AscAckInterrupt(iop_base);
10557 int_pending = TRUE;
10558 if ((chipstat & CSW_HALTED) &&
10559 (ctrl_reg & CC_SINGLE_STEP)) {
10560 if (AscIsrChipHalted(asc_dvc) == ERR) {
10561 goto ISR_REPORT_QDONE_FATAL_ERROR;
10562 } else {
10563 saved_ctrl_reg &= (uchar) (~CC_HALT);
10564 }
10565 } else {
10566 ISR_REPORT_QDONE_FATAL_ERROR:
10567 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
10568 while (((status = AscIsrQDone(asc_dvc)) & 0x01) != 0) {
10569 }
10570 } else {
10571 do {
10572 if ((status = AscIsrQDone(asc_dvc)) == 1) {
10573 break;
10574 }
10575 } while (status == 0x11);
10576 }
10577 if ((status & 0x80) != 0)
10578 int_pending = ERR;
10579 }
10580 }
10581 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
10582 AscSetChipLramAddr(iop_base, saved_ram_addr);
10583 AscSetChipControl(iop_base, saved_ctrl_reg);
10584 asc_dvc->is_in_int = FALSE;
10585 return (int_pending);
10586}
10587
10588/* Microcode buffer is kept after initialization for error recovery. */
10589STATIC uchar _asc_mcode_buf[] =
10590{
10591 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10592 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10593 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10594 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10595 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00,
10596 0x00, 0x00, 0x00, 0x00, 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10597 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00,
10598 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00,
10599 0x80, 0x73, 0x48, 0x04, 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
10600 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2, 0xC2, 0x00, 0x92, 0x80,
10601 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98, 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80,
10602 0x4F, 0x00, 0xF5, 0x00, 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
10603 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8, 0xCD, 0x04, 0x4D, 0x00,
10604 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1,
10605 0x80, 0x73, 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
10606 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00, 0x84, 0x97, 0x07, 0xA6,
10607 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00,
10608 0x69, 0x60, 0xCE, 0x00, 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
10609 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6, 0x34, 0x01, 0x00, 0x33,
10610 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01, 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04,
10611 0x04, 0x85, 0x05, 0xD8, 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
10612 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01, 0x00, 0x33, 0x0A, 0x00,
10613 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01, 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04,
10614 0x36, 0x2D, 0x00, 0x33, 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
10615 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3, 0x3C, 0x01, 0x00, 0x05,
10616 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6, 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01,
10617 0xBE, 0x81, 0xFD, 0x23, 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
10618 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00, 0xC2, 0x88, 0x06, 0x23,
10619 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01, 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0,
10620 0xDA, 0x01, 0xE6, 0x84, 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
10621 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC, 0x4F, 0x00, 0x84, 0x97,
10622 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01, 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80,
10623 0xF0, 0x97, 0x00, 0x46, 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
10624 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88, 0x04, 0x98, 0xF0, 0x80,
10625 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02, 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6,
10626 0x4C, 0x04, 0x46, 0x82, 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
10627 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02, 0x07, 0xA6, 0x5A, 0x02,
10628 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02, 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96,
10629 0x48, 0x82, 0x04, 0x23, 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
10630 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01, 0x6F, 0x00, 0xA5, 0x01,
10631 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01, 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02,
10632 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
10633 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E, 0x80, 0x63, 0x00, 0x43,
10634 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01, 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01,
10635 0x10, 0x31, 0x12, 0x35, 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
10636 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8, 0x00, 0x33, 0x1F, 0x00,
10637 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39, 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6,
10638 0x14, 0x03, 0x00, 0xA6, 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
10639 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0xEE, 0x82,
10640 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42, 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8,
10641 0x31, 0x05, 0x07, 0x01, 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
10642 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6, 0x3C, 0x04, 0x06, 0xA6,
10643 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33, 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83,
10644 0x60, 0x96, 0x32, 0x83, 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
10645 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05, 0xFF, 0xA2, 0x7A, 0x03,
10646 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83, 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03,
10647 0xEC, 0x00, 0x6E, 0x00, 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
10648 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6, 0xA4, 0x03, 0x00, 0xA6,
10649 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42, 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03,
10650 0xD4, 0x83, 0x7C, 0x95, 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
10651 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95, 0xC0, 0x83, 0x00, 0x33,
10652 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32, 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23,
10653 0xA1, 0x01, 0x10, 0x84, 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
10654 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04, 0x06, 0xA6, 0x0A, 0x04,
10655 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84,
10656 0x07, 0xF0, 0x06, 0xA4, 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
10657 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6, 0x38, 0x04, 0x00, 0x33,
10658 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84, 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC,
10659 0x00, 0x33, 0x00, 0x84, 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
10660 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x80, 0x63, 0xA3, 0x01,
10661 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2, 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00,
10662 0x00, 0x33, 0x1D, 0x00, 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
10663 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04, 0x08, 0x23, 0x22, 0xA3,
10664 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04, 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23,
10665 0xF8, 0x88, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
10666 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20, 0x81, 0x62, 0xE8, 0x81,
10667 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE, 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81,
10668 0xC0, 0x20, 0x81, 0x62, 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
10669 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3, 0xF4, 0x04, 0x00, 0x33,
10670 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC, 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01,
10671 0x04, 0x98, 0x26, 0x95, 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
10672 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85, 0x46, 0x97, 0xCD, 0x04,
10673 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01, 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85,
10674 0x02, 0x23, 0xA0, 0x01, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
10675 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01, 0x49, 0x00, 0x81, 0x01,
10676 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01, 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01,
10677 0xC9, 0x00, 0x00, 0x05, 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
10678 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63, 0x07, 0xA4, 0xF8, 0x05,
10679 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85, 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0,
10680 0xB8, 0x05, 0x80, 0x63, 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
10681 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00, 0x62, 0x97, 0x04, 0x85,
10682 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85, 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0,
10683 0xC4, 0x05, 0xF4, 0x85, 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
10684 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05, 0x80, 0x67, 0x80, 0x63,
10685 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23, 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23,
10686 0x80, 0x00, 0x06, 0x87, 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
10687 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23, 0x07, 0x41, 0x83, 0x03,
10688 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33, 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6,
10689 0x20, 0x23, 0x63, 0x60, 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
10690 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00, 0x52, 0x00, 0x06, 0x61,
10691 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA, 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01,
10692 0x04, 0xCC, 0x00, 0x33, 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
10693 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23, 0xDF, 0x00, 0x06, 0xA6,
10694 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20,
10695 0x81, 0x62, 0x00, 0x63, 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
10696 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B, 0x40, 0x0E, 0x80, 0x63,
10697 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43,
10698 0x00, 0xA0, 0xA2, 0x06, 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
10699 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x07, 0xA6, 0xD6, 0x06,
10700 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6,
10701 0xE8, 0x06, 0x00, 0x33, 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
10702 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20, 0x81, 0x62, 0x04, 0x01,
10703 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33,
10704 0x2C, 0x00, 0xC2, 0x88, 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
10705 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88, 0x00, 0x00, 0x80, 0x67,
10706 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61,
10707 0x84, 0x01, 0xE6, 0x84, 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
10708 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04, 0x80, 0x05, 0x81, 0x05,
10709 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01,
10710 0x70, 0x04, 0x71, 0x00, 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
10711 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01, 0xF1, 0x00, 0x70, 0x00,
10712 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01, 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00,
10713 0x81, 0x01, 0x70, 0x04, 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
10714 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1, 0xC4, 0x07, 0x00, 0x33,
10715 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05, 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01,
10716 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
10717 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01, 0x05, 0x05, 0x00, 0x63,
10718 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02,
10719 0x77, 0x04, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
10720 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63, 0xF3, 0x04,
10721 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43, 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08,
10722 0x74, 0x04, 0x02, 0x01, 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
10723 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04, 0x5A, 0x88, 0x02, 0x01,
10724 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95, 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08,
10725 0x00, 0x05, 0x4E, 0x88, 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
10726 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x38, 0x2B,
10727 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09, 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09,
10728 0x00, 0x63, 0x00, 0x32, 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
10729 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32, 0x40, 0x36, 0x40, 0x3A,
10730 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40, 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3,
10731 0x00, 0x63, 0x80, 0x73, 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
10732 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01, 0xA1, 0x23, 0xA1, 0x01,
10733 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77, 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2,
10734 0xF1, 0xC7, 0x41, 0x23, 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
10735};
10736
10737STATIC ushort _asc_mcode_size = sizeof(_asc_mcode_buf);
10738STATIC ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
10739
10740#define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
10741STATIC uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] =
10742{
10743 INQUIRY,
10744 REQUEST_SENSE,
10745 READ_CAPACITY,
10746 READ_TOC,
10747 MODE_SELECT,
10748 MODE_SENSE,
10749 MODE_SELECT_10,
10750 MODE_SENSE_10,
10751 0xFF,
10752 0xFF,
10753 0xFF,
10754 0xFF,
10755 0xFF,
10756 0xFF,
10757 0xFF,
10758 0xFF
10759};
10760
10761STATIC int
10762AscExeScsiQueue(
10763 ASC_DVC_VAR *asc_dvc,
10764 ASC_SCSI_Q *scsiq
10765)
10766{
10767 PortAddr iop_base;
10768 ulong last_int_level;
10769 int sta;
10770 int n_q_required;
10771 int disable_syn_offset_one_fix;
10772 int i;
10773 ASC_PADDR addr;
10774 ASC_EXE_CALLBACK asc_exe_callback;
10775 ushort sg_entry_cnt = 0;
10776 ushort sg_entry_cnt_minus_one = 0;
10777 uchar target_ix;
10778 uchar tid_no;
10779 uchar sdtr_data;
10780 uchar extra_bytes;
10781 uchar scsi_cmd;
10782 uchar disable_cmd;
10783 ASC_SG_HEAD *sg_head;
10784 ASC_DCNT data_cnt;
10785
10786 iop_base = asc_dvc->iop_base;
10787 sg_head = scsiq->sg_head;
10788 asc_exe_callback = asc_dvc->exe_callback;
10789 if (asc_dvc->err_code != 0)
10790 return (ERR);
10791 if (scsiq == (ASC_SCSI_Q *) 0L) {
10792 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_SCSIQ_NULL_PTR);
10793 return (ERR);
10794 }
10795 scsiq->q1.q_no = 0;
10796 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
10797 scsiq->q1.extra_bytes = 0;
10798 }
10799 sta = 0;
10800 target_ix = scsiq->q2.target_ix;
10801 tid_no = ASC_TIX_TO_TID(target_ix);
10802 n_q_required = 1;
10803 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
10804 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
10805 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
10806 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10807 AscMsgOutSDTR(asc_dvc,
10808 asc_dvc->sdtr_period_tbl[(sdtr_data >> 4) &
10809 (uchar) (asc_dvc->max_sdtr_index - 1)],
10810 (uchar) (sdtr_data & (uchar) ASC_SYN_MAX_OFFSET));
10811 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
10812 }
10813 }
10814 last_int_level = DvcEnterCritical();
10815 if (asc_dvc->in_critical_cnt != 0) {
10816 DvcLeaveCritical(last_int_level);
10817 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
10818 return (ERR);
10819 }
10820 asc_dvc->in_critical_cnt++;
10821 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10822 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
10823 asc_dvc->in_critical_cnt--;
10824 DvcLeaveCritical(last_int_level);
10825 return (ERR);
10826 }
10827#if !CC_VERY_LONG_SG_LIST
10828 if (sg_entry_cnt > ASC_MAX_SG_LIST)
10829 {
10830 asc_dvc->in_critical_cnt--;
10831 DvcLeaveCritical(last_int_level);
10832 return(ERR);
10833 }
10834#endif /* !CC_VERY_LONG_SG_LIST */
10835 if (sg_entry_cnt == 1) {
10836 scsiq->q1.data_addr = (ADV_PADDR) sg_head->sg_list[0].addr;
10837 scsiq->q1.data_cnt = (ADV_DCNT) sg_head->sg_list[0].bytes;
10838 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
10839 }
10840 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
10841 }
10842 scsi_cmd = scsiq->cdbptr[0];
10843 disable_syn_offset_one_fix = FALSE;
10844 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
10845 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
10846 if (scsiq->q1.cntl & QC_SG_HEAD) {
10847 data_cnt = 0;
10848 for (i = 0; i < sg_entry_cnt; i++) {
10849 data_cnt += (ADV_DCNT) le32_to_cpu(sg_head->sg_list[i].bytes);
10850 }
10851 } else {
10852 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10853 }
10854 if (data_cnt != 0UL) {
10855 if (data_cnt < 512UL) {
10856 disable_syn_offset_one_fix = TRUE;
10857 } else {
10858 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST; i++) {
10859 disable_cmd = _syn_offset_one_disable_cmd[i];
10860 if (disable_cmd == 0xFF) {
10861 break;
10862 }
10863 if (scsi_cmd == disable_cmd) {
10864 disable_syn_offset_one_fix = TRUE;
10865 break;
10866 }
10867 }
10868 }
10869 }
10870 }
10871 if (disable_syn_offset_one_fix) {
10872 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10873 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
10874 ASC_TAG_FLAG_DISABLE_DISCONNECT);
10875 } else {
10876 scsiq->q2.tag_code &= 0x27;
10877 }
10878 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10879 if (asc_dvc->bug_fix_cntl) {
10880 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10881 if ((scsi_cmd == READ_6) ||
10882 (scsi_cmd == READ_10)) {
10883 addr =
10884 (ADV_PADDR) le32_to_cpu(
10885 sg_head->sg_list[sg_entry_cnt_minus_one].addr) +
10886 (ADV_DCNT) le32_to_cpu(
10887 sg_head->sg_list[sg_entry_cnt_minus_one].bytes);
10888 extra_bytes = (uchar) ((ushort) addr & 0x0003);
10889 if ((extra_bytes != 0) &&
10890 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES)
10891 == 0)) {
10892 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
10893 scsiq->q1.extra_bytes = extra_bytes;
10894 data_cnt = le32_to_cpu(
10895 sg_head->sg_list[sg_entry_cnt_minus_one].bytes);
10896 data_cnt -= (ASC_DCNT) extra_bytes;
10897 sg_head->sg_list[sg_entry_cnt_minus_one].bytes =
10898 cpu_to_le32(data_cnt);
10899 }
10900 }
10901 }
10902 }
10903 sg_head->entry_to_copy = sg_head->entry_cnt;
10904#if CC_VERY_LONG_SG_LIST
10905 /*
10906 * Set the sg_entry_cnt to the maximum possible. The rest of
10907 * the SG elements will be copied when the RISC completes the
10908 * SG elements that fit and halts.
10909 */
10910 if (sg_entry_cnt > ASC_MAX_SG_LIST)
10911 {
10912 sg_entry_cnt = ASC_MAX_SG_LIST;
10913 }
10914#endif /* CC_VERY_LONG_SG_LIST */
10915 n_q_required = AscSgListToQueue(sg_entry_cnt);
10916 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
10917 (uint) n_q_required) || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10918 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10919 n_q_required)) == 1) {
10920 asc_dvc->in_critical_cnt--;
10921 if (asc_exe_callback != 0) {
10922 (*asc_exe_callback) (asc_dvc, scsiq);
10923 }
10924 DvcLeaveCritical(last_int_level);
10925 return (sta);
10926 }
10927 }
10928 } else {
10929 if (asc_dvc->bug_fix_cntl) {
10930 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10931 if ((scsi_cmd == READ_6) ||
10932 (scsi_cmd == READ_10)) {
10933 addr = le32_to_cpu(scsiq->q1.data_addr) +
10934 le32_to_cpu(scsiq->q1.data_cnt);
10935 extra_bytes = (uchar) ((ushort) addr & 0x0003);
10936 if ((extra_bytes != 0) &&
10937 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES)
10938 == 0)) {
10939 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10940 if (((ushort) data_cnt & 0x01FF) == 0) {
10941 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
10942 data_cnt -= (ASC_DCNT) extra_bytes;
10943 scsiq->q1.data_cnt = cpu_to_le32(data_cnt);
10944 scsiq->q1.extra_bytes = extra_bytes;
10945 }
10946 }
10947 }
10948 }
10949 }
10950 n_q_required = 1;
10951 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
10952 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10953 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10954 n_q_required)) == 1) {
10955 asc_dvc->in_critical_cnt--;
10956 if (asc_exe_callback != 0) {
10957 (*asc_exe_callback) (asc_dvc, scsiq);
10958 }
10959 DvcLeaveCritical(last_int_level);
10960 return (sta);
10961 }
10962 }
10963 }
10964 asc_dvc->in_critical_cnt--;
10965 DvcLeaveCritical(last_int_level);
10966 return (sta);
10967}
10968
10969STATIC int
10970AscSendScsiQueue(
10971 ASC_DVC_VAR *asc_dvc,
10972 ASC_SCSI_Q *scsiq,
10973 uchar n_q_required
10974)
10975{
10976 PortAddr iop_base;
10977 uchar free_q_head;
10978 uchar next_qp;
10979 uchar tid_no;
10980 uchar target_ix;
10981 int sta;
10982
10983 iop_base = asc_dvc->iop_base;
10984 target_ix = scsiq->q2.target_ix;
10985 tid_no = ASC_TIX_TO_TID(target_ix);
10986 sta = 0;
10987 free_q_head = (uchar) AscGetVarFreeQHead(iop_base);
10988 if (n_q_required > 1) {
10989 if ((next_qp = AscAllocMultipleFreeQueue(iop_base,
10990 free_q_head, (uchar) (n_q_required)))
10991 != (uchar) ASC_QLINK_END) {
10992 asc_dvc->last_q_shortage = 0;
10993 scsiq->sg_head->queue_cnt = n_q_required - 1;
10994 scsiq->q1.q_no = free_q_head;
10995 if ((sta = AscPutReadySgListQueue(asc_dvc, scsiq,
10996 free_q_head)) == 1) {
10997 AscPutVarFreeQHead(iop_base, next_qp);
10998 asc_dvc->cur_total_qng += (uchar) (n_q_required);
10999 asc_dvc->cur_dvc_qng[tid_no]++;
11000 }
11001 return (sta);
11002 }
11003 } else if (n_q_required == 1) {
11004 if ((next_qp = AscAllocFreeQueue(iop_base,
11005 free_q_head)) != ASC_QLINK_END) {
11006 scsiq->q1.q_no = free_q_head;
11007 if ((sta = AscPutReadyQueue(asc_dvc, scsiq,
11008 free_q_head)) == 1) {
11009 AscPutVarFreeQHead(iop_base, next_qp);
11010 asc_dvc->cur_total_qng++;
11011 asc_dvc->cur_dvc_qng[tid_no]++;
11012 }
11013 return (sta);
11014 }
11015 }
11016 return (sta);
11017}
11018
11019STATIC int
11020AscSgListToQueue(
11021 int sg_list
11022)
11023{
11024 int n_sg_list_qs;
11025
11026 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
11027 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
11028 n_sg_list_qs++;
11029 return (n_sg_list_qs + 1);
11030}
11031
11032
11033STATIC uint
11034AscGetNumOfFreeQueue(
11035 ASC_DVC_VAR *asc_dvc,
11036 uchar target_ix,
11037 uchar n_qs
11038)
11039{
11040 uint cur_used_qs;
11041 uint cur_free_qs;
11042 ASC_SCSI_BIT_ID_TYPE target_id;
11043 uchar tid_no;
11044
11045 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
11046 tid_no = ASC_TIX_TO_TID(target_ix);
11047 if ((asc_dvc->unit_not_ready & target_id) ||
11048 (asc_dvc->queue_full_or_busy & target_id)) {
11049 return (0);
11050 }
11051 if (n_qs == 1) {
11052 cur_used_qs = (uint) asc_dvc->cur_total_qng +
11053 (uint) asc_dvc->last_q_shortage +
11054 (uint) ASC_MIN_FREE_Q;
11055 } else {
11056 cur_used_qs = (uint) asc_dvc->cur_total_qng +
11057 (uint) ASC_MIN_FREE_Q;
11058 }
11059 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
11060 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
11061 if (asc_dvc->cur_dvc_qng[tid_no] >=
11062 asc_dvc->max_dvc_qng[tid_no]) {
11063 return (0);
11064 }
11065 return (cur_free_qs);
11066 }
11067 if (n_qs > 1) {
11068 if ((n_qs > asc_dvc->last_q_shortage) && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
11069 asc_dvc->last_q_shortage = n_qs;
11070 }
11071 }
11072 return (0);
11073}
11074
11075STATIC int
11076AscPutReadyQueue(
11077 ASC_DVC_VAR *asc_dvc,
11078 ASC_SCSI_Q *scsiq,
11079 uchar q_no
11080)
11081{
11082 ushort q_addr;
11083 uchar tid_no;
11084 uchar sdtr_data;
11085 uchar syn_period_ix;
11086 uchar syn_offset;
11087 PortAddr iop_base;
11088
11089 iop_base = asc_dvc->iop_base;
11090 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
11091 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
11092 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
11093 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
11094 syn_period_ix = (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
11095 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
11096 AscMsgOutSDTR(asc_dvc,
11097 asc_dvc->sdtr_period_tbl[syn_period_ix],
11098 syn_offset);
11099 scsiq->q1.cntl |= QC_MSG_OUT;
11100 }
11101 q_addr = ASC_QNO_TO_QADDR(q_no);
11102 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
11103 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG ;
11104 }
11105 scsiq->q1.status = QS_FREE;
11106 AscMemWordCopyPtrToLram(iop_base,
11107 q_addr + ASC_SCSIQ_CDB_BEG,
11108 (uchar *) scsiq->cdbptr,
11109 scsiq->q2.cdb_len >> 1);
11110
11111 DvcPutScsiQ(iop_base,
11112 q_addr + ASC_SCSIQ_CPY_BEG,
11113 (uchar *) &scsiq->q1.cntl,
11114 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
11115 AscWriteLramWord(iop_base,
11116 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS),
11117 (ushort) (((ushort) scsiq->q1.q_no << 8) | (ushort) QS_READY));
11118 return (1);
11119}
11120
11121STATIC int
11122AscPutReadySgListQueue(
11123 ASC_DVC_VAR *asc_dvc,
11124 ASC_SCSI_Q *scsiq,
11125 uchar q_no
11126)
11127{
11128 int sta;
11129 int i;
11130 ASC_SG_HEAD *sg_head;
11131 ASC_SG_LIST_Q scsi_sg_q;
11132 ASC_DCNT saved_data_addr;
11133 ASC_DCNT saved_data_cnt;
11134 PortAddr iop_base;
11135 ushort sg_list_dwords;
11136 ushort sg_index;
11137 ushort sg_entry_cnt;
11138 ushort q_addr;
11139 uchar next_qp;
11140
11141 iop_base = asc_dvc->iop_base;
11142 sg_head = scsiq->sg_head;
11143 saved_data_addr = scsiq->q1.data_addr;
11144 saved_data_cnt = scsiq->q1.data_cnt;
11145 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
11146 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
11147#if CC_VERY_LONG_SG_LIST
11148 /*
11149 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
11150 * then not all SG elements will fit in the allocated queues.
11151 * The rest of the SG elements will be copied when the RISC
11152 * completes the SG elements that fit and halts.
11153 */
11154 if (sg_head->entry_cnt > ASC_MAX_SG_LIST)
11155 {
11156 /*
11157 * Set sg_entry_cnt to be the number of SG elements that
11158 * will fit in the allocated SG queues. It is minus 1, because
11159 * the first SG element is handled above. ASC_MAX_SG_LIST is
11160 * already inflated by 1 to account for this. For example it
11161 * may be 50 which is 1 + 7 queues * 7 SG elements.
11162 */
11163 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
11164
11165 /*
11166 * Keep track of remaining number of SG elements that will
11167 * need to be handled from a_isr.c.
11168 */
11169 scsiq->remain_sg_entry_cnt = sg_head->entry_cnt - ASC_MAX_SG_LIST;
11170 } else
11171 {
11172#endif /* CC_VERY_LONG_SG_LIST */
11173 /*
11174 * Set sg_entry_cnt to be the number of SG elements that
11175 * will fit in the allocated SG queues. It is minus 1, because
11176 * the first SG element is handled above.
11177 */
11178 sg_entry_cnt = sg_head->entry_cnt - 1;
11179#if CC_VERY_LONG_SG_LIST
11180 }
11181#endif /* CC_VERY_LONG_SG_LIST */
11182 if (sg_entry_cnt != 0) {
11183 scsiq->q1.cntl |= QC_SG_HEAD;
11184 q_addr = ASC_QNO_TO_QADDR(q_no);
11185 sg_index = 1;
11186 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
11187 scsi_sg_q.sg_head_qp = q_no;
11188 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
11189 for (i = 0; i < sg_head->queue_cnt; i++) {
11190 scsi_sg_q.seq_no = i + 1;
11191 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
11192 sg_list_dwords = (uchar) (ASC_SG_LIST_PER_Q * 2);
11193 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
11194 if (i == 0) {
11195 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q;
11196 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q;
11197 } else {
11198 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
11199 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
11200 }
11201 } else {
11202#if CC_VERY_LONG_SG_LIST
11203 /*
11204 * This is the last SG queue in the list of
11205 * allocated SG queues. If there are more
11206 * SG elements than will fit in the allocated
11207 * queues, then set the QCSG_SG_XFER_MORE flag.
11208 */
11209 if (sg_head->entry_cnt > ASC_MAX_SG_LIST)
11210 {
11211 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
11212 } else
11213 {
11214#endif /* CC_VERY_LONG_SG_LIST */
11215 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
11216#if CC_VERY_LONG_SG_LIST
11217 }
11218#endif /* CC_VERY_LONG_SG_LIST */
11219 sg_list_dwords = sg_entry_cnt << 1;
11220 if (i == 0) {
11221 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
11222 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt;
11223 } else {
11224 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
11225 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
11226 }
11227 sg_entry_cnt = 0;
11228 }
11229 next_qp = AscReadLramByte(iop_base,
11230 (ushort) (q_addr + ASC_SCSIQ_B_FWD));
11231 scsi_sg_q.q_no = next_qp;
11232 q_addr = ASC_QNO_TO_QADDR(next_qp);
11233 AscMemWordCopyPtrToLram(iop_base,
11234 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
11235 (uchar *) &scsi_sg_q,
11236 sizeof(ASC_SG_LIST_Q) >> 1);
11237 AscMemDWordCopyPtrToLram(iop_base,
11238 q_addr + ASC_SGQ_LIST_BEG,
11239 (uchar *) &sg_head->sg_list[sg_index],
11240 sg_list_dwords);
11241 sg_index += ASC_SG_LIST_PER_Q;
11242 scsiq->next_sg_index = sg_index;
11243 }
11244 } else {
11245 scsiq->q1.cntl &= ~QC_SG_HEAD;
11246 }
11247 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
11248 scsiq->q1.data_addr = saved_data_addr;
11249 scsiq->q1.data_cnt = saved_data_cnt;
11250 return (sta);
11251}
11252
11253STATIC int
11254AscSetRunChipSynRegAtID(
11255 PortAddr iop_base,
11256 uchar tid_no,
11257 uchar sdtr_data
11258)
11259{
11260 int sta = FALSE;
11261
11262 if (AscHostReqRiscHalt(iop_base)) {
11263 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
11264 AscStartChip(iop_base);
11265 return (sta);
11266 }
11267 return (sta);
11268}
11269
11270STATIC int
11271AscSetChipSynRegAtID(
11272 PortAddr iop_base,
11273 uchar id,
11274 uchar sdtr_data
11275)
11276{
11277 ASC_SCSI_BIT_ID_TYPE org_id;
11278 int i;
11279 int sta = TRUE;
11280
11281 AscSetBank(iop_base, 1);
11282 org_id = AscReadChipDvcID(iop_base);
11283 for (i = 0; i <= ASC_MAX_TID; i++) {
11284 if (org_id == (0x01 << i))
11285 break;
11286 }
11287 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
11288 AscWriteChipDvcID(iop_base, id);
11289 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
11290 AscSetBank(iop_base, 0);
11291 AscSetChipSyn(iop_base, sdtr_data);
11292 if (AscGetChipSyn(iop_base) != sdtr_data) {
11293 sta = FALSE;
11294 }
11295 } else {
11296 sta = FALSE;
11297 }
11298 AscSetBank(iop_base, 1);
11299 AscWriteChipDvcID(iop_base, org_id);
11300 AscSetBank(iop_base, 0);
11301 return (sta);
11302}
11303
11304STATIC ushort
11305AscInitLram(
11306 ASC_DVC_VAR *asc_dvc
11307)
11308{
11309 uchar i;
11310 ushort s_addr;
11311 PortAddr iop_base;
11312 ushort warn_code;
11313
11314 iop_base = asc_dvc->iop_base;
11315 warn_code = 0;
11316 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
11317 (ushort) (((int) (asc_dvc->max_total_qng + 2 + 1) * 64) >> 1)
11318);
11319 i = ASC_MIN_ACTIVE_QNO;
11320 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
11321 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11322 (uchar) (i + 1));
11323 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11324 (uchar) (asc_dvc->max_total_qng));
11325 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11326 (uchar) i);
11327 i++;
11328 s_addr += ASC_QBLK_SIZE;
11329 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
11330 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11331 (uchar) (i + 1));
11332 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11333 (uchar) (i - 1));
11334 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11335 (uchar) i);
11336 }
11337 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11338 (uchar) ASC_QLINK_END);
11339 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11340 (uchar) (asc_dvc->max_total_qng - 1));
11341 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11342 (uchar) asc_dvc->max_total_qng);
11343 i++;
11344 s_addr += ASC_QBLK_SIZE;
11345 for (; i <= (uchar) (asc_dvc->max_total_qng + 3);
11346 i++, s_addr += ASC_QBLK_SIZE) {
11347 AscWriteLramByte(iop_base,
11348 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_FWD), i);
11349 AscWriteLramByte(iop_base,
11350 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_BWD), i);
11351 AscWriteLramByte(iop_base,
11352 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_QNO), i);
11353 }
11354 return (warn_code);
11355}
11356
11357STATIC ushort
11358AscInitQLinkVar(
11359 ASC_DVC_VAR *asc_dvc
11360)
11361{
11362 PortAddr iop_base;
11363 int i;
11364 ushort lram_addr;
11365
11366 iop_base = asc_dvc->iop_base;
11367 AscPutRiscVarFreeQHead(iop_base, 1);
11368 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
11369 AscPutVarFreeQHead(iop_base, 1);
11370 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
11371 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
11372 (uchar) ((int) asc_dvc->max_total_qng + 1));
11373 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
11374 (uchar) ((int) asc_dvc->max_total_qng + 2));
11375 AscWriteLramByte(iop_base, (ushort) ASCV_TOTAL_READY_Q_B,
11376 asc_dvc->max_total_qng);
11377 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
11378 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
11379 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
11380 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
11381 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
11382 AscPutQDoneInProgress(iop_base, 0);
11383 lram_addr = ASC_QADR_BEG;
11384 for (i = 0; i < 32; i++, lram_addr += 2) {
11385 AscWriteLramWord(iop_base, lram_addr, 0);
11386 }
11387 return (0);
11388}
11389
11390STATIC int
11391AscSetLibErrorCode(
11392 ASC_DVC_VAR *asc_dvc,
11393 ushort err_code
11394)
11395{
11396 if (asc_dvc->err_code == 0) {
11397 asc_dvc->err_code = err_code;
11398 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
11399 err_code);
11400 }
11401 return (err_code);
11402}
11403
11404
11405STATIC uchar
11406AscMsgOutSDTR(
11407 ASC_DVC_VAR *asc_dvc,
11408 uchar sdtr_period,
11409 uchar sdtr_offset
11410)
11411{
11412 EXT_MSG sdtr_buf;
11413 uchar sdtr_period_index;
11414 PortAddr iop_base;
11415
11416 iop_base = asc_dvc->iop_base;
11417 sdtr_buf.msg_type = MS_EXTEND;
11418 sdtr_buf.msg_len = MS_SDTR_LEN;
11419 sdtr_buf.msg_req = MS_SDTR_CODE;
11420 sdtr_buf.xfer_period = sdtr_period;
11421 sdtr_offset &= ASC_SYN_MAX_OFFSET;
11422 sdtr_buf.req_ack_offset = sdtr_offset;
11423 if ((sdtr_period_index =
11424 AscGetSynPeriodIndex(asc_dvc, sdtr_period)) <=
11425 asc_dvc->max_sdtr_index) {
11426 AscMemWordCopyPtrToLram(iop_base,
11427 ASCV_MSGOUT_BEG,
11428 (uchar *) &sdtr_buf,
11429 sizeof (EXT_MSG) >> 1);
11430 return ((sdtr_period_index << 4) | sdtr_offset);
11431 } else {
11432
11433 sdtr_buf.req_ack_offset = 0;
11434 AscMemWordCopyPtrToLram(iop_base,
11435 ASCV_MSGOUT_BEG,
11436 (uchar *) &sdtr_buf,
11437 sizeof (EXT_MSG) >> 1);
11438 return (0);
11439 }
11440}
11441
11442STATIC uchar
11443AscCalSDTRData(
11444 ASC_DVC_VAR *asc_dvc,
11445 uchar sdtr_period,
11446 uchar syn_offset
11447)
11448{
11449 uchar byte;
11450 uchar sdtr_period_ix;
11451
11452 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
11453 if (
11454 (sdtr_period_ix > asc_dvc->max_sdtr_index)
11455) {
11456 return (0xFF);
11457 }
11458 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
11459 return (byte);
11460}
11461
11462STATIC void
11463AscSetChipSDTR(
11464 PortAddr iop_base,
11465 uchar sdtr_data,
11466 uchar tid_no
11467)
11468{
11469 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
11470 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
11471 return;
11472}
11473
11474STATIC uchar
11475AscGetSynPeriodIndex(
11476 ASC_DVC_VAR *asc_dvc,
11477 uchar syn_time
11478)
11479{
11480 uchar *period_table;
11481 int max_index;
11482 int min_index;
11483 int i;
11484
11485 period_table = asc_dvc->sdtr_period_tbl;
11486 max_index = (int) asc_dvc->max_sdtr_index;
11487 min_index = (int)asc_dvc->host_init_sdtr_index;
11488 if ((syn_time <= period_table[max_index])) {
11489 for (i = min_index; i < (max_index - 1); i++) {
11490 if (syn_time <= period_table[i]) {
11491 return ((uchar) i);
11492 }
11493 }
11494 return ((uchar) max_index);
11495 } else {
11496 return ((uchar) (max_index + 1));
11497 }
11498}
11499
11500STATIC uchar
11501AscAllocFreeQueue(
11502 PortAddr iop_base,
11503 uchar free_q_head
11504)
11505{
11506 ushort q_addr;
11507 uchar next_qp;
11508 uchar q_status;
11509
11510 q_addr = ASC_QNO_TO_QADDR(free_q_head);
11511 q_status = (uchar) AscReadLramByte(iop_base,
11512 (ushort) (q_addr + ASC_SCSIQ_B_STATUS));
11513 next_qp = AscReadLramByte(iop_base,
11514 (ushort) (q_addr + ASC_SCSIQ_B_FWD));
11515 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END)) {
11516 return (next_qp);
11517 }
11518 return (ASC_QLINK_END);
11519}
11520
11521STATIC uchar
11522AscAllocMultipleFreeQueue(
11523 PortAddr iop_base,
11524 uchar free_q_head,
11525 uchar n_free_q
11526)
11527{
11528 uchar i;
11529
11530 for (i = 0; i < n_free_q; i++) {
11531 if ((free_q_head = AscAllocFreeQueue(iop_base, free_q_head))
11532 == ASC_QLINK_END) {
11533 return (ASC_QLINK_END);
11534 }
11535 }
11536 return (free_q_head);
11537}
11538
11539STATIC int
11540AscHostReqRiscHalt(
11541 PortAddr iop_base
11542)
11543{
11544 int count = 0;
11545 int sta = 0;
11546 uchar saved_stop_code;
11547
11548 if (AscIsChipHalted(iop_base))
11549 return (1);
11550 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
11551 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11552 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP
11553);
11554 do {
11555 if (AscIsChipHalted(iop_base)) {
11556 sta = 1;
11557 break;
11558 }
11559 DvcSleepMilliSecond(100);
11560 } while (count++ < 20);
11561 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
11562 return (sta);
11563}
11564
11565STATIC int
11566AscStopQueueExe(
11567 PortAddr iop_base
11568)
11569{
11570 int count = 0;
11571
11572 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
11573 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11574 ASC_STOP_REQ_RISC_STOP);
11575 do {
11576 if (
11577 AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
11578 ASC_STOP_ACK_RISC_STOP) {
11579 return (1);
11580 }
11581 DvcSleepMilliSecond(100);
11582 } while (count++ < 20);
11583 }
11584 return (0);
11585}
11586
11587STATIC void
11588DvcDelayMicroSecond(ADV_DVC_VAR *asc_dvc, ushort micro_sec)
11589{
11590 udelay(micro_sec);
11591}
11592
11593STATIC void
11594DvcDelayNanoSecond(ASC_DVC_VAR *asc_dvc, ASC_DCNT nano_sec)
11595{
11596 udelay((nano_sec + 999)/1000);
11597}
11598
11599#ifdef CONFIG_ISA
11600STATIC ASC_DCNT __init
11601AscGetEisaProductID(
11602 PortAddr iop_base)
11603{
11604 PortAddr eisa_iop;
11605 ushort product_id_high, product_id_low;
11606 ASC_DCNT product_id;
11607
11608 eisa_iop = ASC_GET_EISA_SLOT(iop_base) | ASC_EISA_PID_IOP_MASK;
11609 product_id_low = inpw(eisa_iop);
11610 product_id_high = inpw(eisa_iop + 2);
11611 product_id = ((ASC_DCNT) product_id_high << 16) |
11612 (ASC_DCNT) product_id_low;
11613 return (product_id);
11614}
11615
11616STATIC PortAddr __init
11617AscSearchIOPortAddrEISA(
11618 PortAddr iop_base)
11619{
11620 ASC_DCNT eisa_product_id;
11621
11622 if (iop_base == 0) {
11623 iop_base = ASC_EISA_MIN_IOP_ADDR;
11624 } else {
11625 if (iop_base == ASC_EISA_MAX_IOP_ADDR)
11626 return (0);
11627 if ((iop_base & 0x0050) == 0x0050) {
11628 iop_base += ASC_EISA_BIG_IOP_GAP;
11629 } else {
11630 iop_base += ASC_EISA_SMALL_IOP_GAP;
11631 }
11632 }
11633 while (iop_base <= ASC_EISA_MAX_IOP_ADDR) {
11634 eisa_product_id = AscGetEisaProductID(iop_base);
11635 if ((eisa_product_id == ASC_EISA_ID_740) ||
11636 (eisa_product_id == ASC_EISA_ID_750)) {
11637 if (AscFindSignature(iop_base)) {
11638 inpw(iop_base + 4);
11639 return (iop_base);
11640 }
11641 }
11642 if (iop_base == ASC_EISA_MAX_IOP_ADDR)
11643 return (0);
11644 if ((iop_base & 0x0050) == 0x0050) {
11645 iop_base += ASC_EISA_BIG_IOP_GAP;
11646 } else {
11647 iop_base += ASC_EISA_SMALL_IOP_GAP;
11648 }
11649 }
11650 return (0);
11651}
11652#endif /* CONFIG_ISA */
11653
11654STATIC int
11655AscStartChip(
11656 PortAddr iop_base
11657)
11658{
11659 AscSetChipControl(iop_base, 0);
11660 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
11661 return (0);
11662 }
11663 return (1);
11664}
11665
11666STATIC int
11667AscStopChip(
11668 PortAddr iop_base
11669)
11670{
11671 uchar cc_val;
11672
11673 cc_val = AscGetChipControl(iop_base) & (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
11674 AscSetChipControl(iop_base, (uchar) (cc_val | CC_HALT));
11675 AscSetChipIH(iop_base, INS_HALT);
11676 AscSetChipIH(iop_base, INS_RFLAG_WTM);
11677 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
11678 return (0);
11679 }
11680 return (1);
11681}
11682
11683STATIC int
11684AscIsChipHalted(
11685 PortAddr iop_base
11686)
11687{
11688 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
11689 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
11690 return (1);
11691 }
11692 }
11693 return (0);
11694}
11695
11696STATIC void
11697AscSetChipIH(
11698 PortAddr iop_base,
11699 ushort ins_code
11700)
11701{
11702 AscSetBank(iop_base, 1);
11703 AscWriteChipIH(iop_base, ins_code);
11704 AscSetBank(iop_base, 0);
11705 return;
11706}
11707
11708STATIC void
11709AscAckInterrupt(
11710 PortAddr iop_base
11711)
11712{
11713 uchar host_flag;
11714 uchar risc_flag;
11715 ushort loop;
11716
11717 loop = 0;
11718 do {
11719 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
11720 if (loop++ > 0x7FFF) {
11721 break;
11722 }
11723 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
11724 host_flag = AscReadLramByte(iop_base, ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
11725 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
11726 (uchar) (host_flag | ASC_HOST_FLAG_ACK_INT));
11727 AscSetChipStatus(iop_base, CIW_INT_ACK);
11728 loop = 0;
11729 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
11730 AscSetChipStatus(iop_base, CIW_INT_ACK);
11731 if (loop++ > 3) {
11732 break;
11733 }
11734 }
11735 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
11736 return;
11737}
11738
11739STATIC void
11740AscDisableInterrupt(
11741 PortAddr iop_base
11742)
11743{
11744 ushort cfg;
11745
11746 cfg = AscGetChipCfgLsw(iop_base);
11747 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
11748 return;
11749}
11750
11751STATIC void
11752AscEnableInterrupt(
11753 PortAddr iop_base
11754)
11755{
11756 ushort cfg;
11757
11758 cfg = AscGetChipCfgLsw(iop_base);
11759 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
11760 return;
11761}
11762
11763
11764
11765STATIC void
11766AscSetBank(
11767 PortAddr iop_base,
11768 uchar bank
11769)
11770{
11771 uchar val;
11772
11773 val = AscGetChipControl(iop_base) &
11774 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET | CC_CHIP_RESET));
11775 if (bank == 1) {
11776 val |= CC_BANK_ONE;
11777 } else if (bank == 2) {
11778 val |= CC_DIAG | CC_BANK_ONE;
11779 } else {
11780 val &= ~CC_BANK_ONE;
11781 }
11782 AscSetChipControl(iop_base, val);
11783 return;
11784}
11785
11786STATIC int
11787AscResetChipAndScsiBus(
11788 ASC_DVC_VAR *asc_dvc
11789)
11790{
11791 PortAddr iop_base;
11792 int i = 10;
11793
11794 iop_base = asc_dvc->iop_base;
11795 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) && (i-- > 0))
11796 {
11797 DvcSleepMilliSecond(100);
11798 }
11799 AscStopChip(iop_base);
11800 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
11801 DvcDelayNanoSecond(asc_dvc, 60000);
11802 AscSetChipIH(iop_base, INS_RFLAG_WTM);
11803 AscSetChipIH(iop_base, INS_HALT);
11804 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
11805 AscSetChipControl(iop_base, CC_HALT);
11806 DvcSleepMilliSecond(200);
11807 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
11808 AscSetChipStatus(iop_base, 0);
11809 return (AscIsChipHalted(iop_base));
11810}
11811
11812STATIC ASC_DCNT __init
11813AscGetMaxDmaCount(
11814 ushort bus_type)
11815{
11816 if (bus_type & ASC_IS_ISA)
11817 return (ASC_MAX_ISA_DMA_COUNT);
11818 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
11819 return (ASC_MAX_VL_DMA_COUNT);
11820 return (ASC_MAX_PCI_DMA_COUNT);
11821}
11822
11823#ifdef CONFIG_ISA
11824STATIC ushort __init
11825AscGetIsaDmaChannel(
11826 PortAddr iop_base)
11827{
11828 ushort channel;
11829
11830 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
11831 if (channel == 0x03)
11832 return (0);
11833 else if (channel == 0x00)
11834 return (7);
11835 return (channel + 4);
11836}
11837
11838STATIC ushort __init
11839AscSetIsaDmaChannel(
11840 PortAddr iop_base,
11841 ushort dma_channel)
11842{
11843 ushort cfg_lsw;
11844 uchar value;
11845
11846 if ((dma_channel >= 5) && (dma_channel <= 7)) {
11847 if (dma_channel == 7)
11848 value = 0x00;
11849 else
11850 value = dma_channel - 4;
11851 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
11852 cfg_lsw |= value;
11853 AscSetChipCfgLsw(iop_base, cfg_lsw);
11854 return (AscGetIsaDmaChannel(iop_base));
11855 }
11856 return (0);
11857}
11858
11859STATIC uchar __init
11860AscSetIsaDmaSpeed(
11861 PortAddr iop_base,
11862 uchar speed_value)
11863{
11864 speed_value &= 0x07;
11865 AscSetBank(iop_base, 1);
11866 AscWriteChipDmaSpeed(iop_base, speed_value);
11867 AscSetBank(iop_base, 0);
11868 return (AscGetIsaDmaSpeed(iop_base));
11869}
11870
11871STATIC uchar __init
11872AscGetIsaDmaSpeed(
11873 PortAddr iop_base
11874)
11875{
11876 uchar speed_value;
11877
11878 AscSetBank(iop_base, 1);
11879 speed_value = AscReadChipDmaSpeed(iop_base);
11880 speed_value &= 0x07;
11881 AscSetBank(iop_base, 0);
11882 return (speed_value);
11883}
11884#endif /* CONFIG_ISA */
11885
11886STATIC ushort __init
11887AscReadPCIConfigWord(
11888 ASC_DVC_VAR *asc_dvc,
11889 ushort pci_config_offset)
11890{
11891 uchar lsb, msb;
11892
11893 lsb = DvcReadPCIConfigByte(asc_dvc, pci_config_offset);
11894 msb = DvcReadPCIConfigByte(asc_dvc, pci_config_offset + 1);
11895 return ((ushort) ((msb << 8) | lsb));
11896}
11897
11898STATIC ushort __init
11899AscInitGetConfig(
11900 ASC_DVC_VAR *asc_dvc
11901)
11902{
11903 ushort warn_code;
11904 PortAddr iop_base;
11905 ushort PCIDeviceID;
11906 ushort PCIVendorID;
11907 uchar PCIRevisionID;
11908 uchar prevCmdRegBits;
11909
11910 warn_code = 0;
11911 iop_base = asc_dvc->iop_base;
11912 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
11913 if (asc_dvc->err_code != 0) {
11914 return (UW_ERR);
11915 }
11916 if (asc_dvc->bus_type == ASC_IS_PCI) {
11917 PCIVendorID = AscReadPCIConfigWord(asc_dvc,
11918 AscPCIConfigVendorIDRegister);
11919
11920 PCIDeviceID = AscReadPCIConfigWord(asc_dvc,
11921 AscPCIConfigDeviceIDRegister);
11922
11923 PCIRevisionID = DvcReadPCIConfigByte(asc_dvc,
11924 AscPCIConfigRevisionIDRegister);
11925
11926 if (PCIVendorID != ASC_PCI_VENDORID) {
11927 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11928 }
11929 prevCmdRegBits = DvcReadPCIConfigByte(asc_dvc,
11930 AscPCIConfigCommandRegister);
11931
11932 if ((prevCmdRegBits & AscPCICmdRegBits_IOMemBusMaster) !=
11933 AscPCICmdRegBits_IOMemBusMaster) {
11934 DvcWritePCIConfigByte(asc_dvc,
11935 AscPCIConfigCommandRegister,
11936 (prevCmdRegBits |
11937 AscPCICmdRegBits_IOMemBusMaster));
11938
11939 if ((DvcReadPCIConfigByte(asc_dvc,
11940 AscPCIConfigCommandRegister)
11941 & AscPCICmdRegBits_IOMemBusMaster)
11942 != AscPCICmdRegBits_IOMemBusMaster) {
11943 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11944 }
11945 }
11946 if ((PCIDeviceID == ASC_PCI_DEVICEID_1200A) ||
11947 (PCIDeviceID == ASC_PCI_DEVICEID_1200B)) {
11948 DvcWritePCIConfigByte(asc_dvc,
11949 AscPCIConfigLatencyTimer, 0x00);
11950 if (DvcReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer)
11951 != 0x00) {
11952 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11953 }
11954 } else if (PCIDeviceID == ASC_PCI_DEVICEID_ULTRA) {
11955 if (DvcReadPCIConfigByte(asc_dvc,
11956 AscPCIConfigLatencyTimer) < 0x20) {
11957 DvcWritePCIConfigByte(asc_dvc,
11958 AscPCIConfigLatencyTimer, 0x20);
11959
11960 if (DvcReadPCIConfigByte(asc_dvc,
11961 AscPCIConfigLatencyTimer) < 0x20) {
11962 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11963 }
11964 }
11965 }
11966 }
11967
11968 if (AscFindSignature(iop_base)) {
11969 warn_code |= AscInitAscDvcVar(asc_dvc);
11970 warn_code |= AscInitFromEEP(asc_dvc);
11971 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
11972 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT) {
11973 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
11974 }
11975 } else {
11976 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11977 }
11978 return(warn_code);
11979}
11980
11981STATIC ushort __init
11982AscInitSetConfig(
11983 ASC_DVC_VAR *asc_dvc
11984)
11985{
11986 ushort warn_code = 0;
11987
11988 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
11989 if (asc_dvc->err_code != 0)
11990 return (UW_ERR);
11991 if (AscFindSignature(asc_dvc->iop_base)) {
11992 warn_code |= AscInitFromAscDvcVar(asc_dvc);
11993 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
11994 } else {
11995 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11996 }
11997 return (warn_code);
11998}
11999
12000STATIC ushort __init
12001AscInitFromAscDvcVar(
12002 ASC_DVC_VAR *asc_dvc
12003)
12004{
12005 PortAddr iop_base;
12006 ushort cfg_msw;
12007 ushort warn_code;
12008 ushort pci_device_id = 0;
12009
12010 iop_base = asc_dvc->iop_base;
12011#ifdef CONFIG_PCI
12012 if (asc_dvc->cfg->dev)
12013 pci_device_id = to_pci_dev(asc_dvc->cfg->dev)->device;
12014#endif
12015 warn_code = 0;
12016 cfg_msw = AscGetChipCfgMsw(iop_base);
12017 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12018 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
12019 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12020 AscSetChipCfgMsw(iop_base, cfg_msw);
12021 }
12022 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
12023 asc_dvc->cfg->cmd_qng_enabled) {
12024 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
12025 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12026 }
12027 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12028 warn_code |= ASC_WARN_AUTO_CONFIG;
12029 }
12030 if ((asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) {
12031 if (AscSetChipIRQ(iop_base, asc_dvc->irq_no, asc_dvc->bus_type)
12032 != asc_dvc->irq_no) {
12033 asc_dvc->err_code |= ASC_IERR_SET_IRQ_NO;
12034 }
12035 }
12036 if (asc_dvc->bus_type & ASC_IS_PCI) {
12037 cfg_msw &= 0xFFC0;
12038 AscSetChipCfgMsw(iop_base, cfg_msw);
12039 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
12040 } else {
12041 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) ||
12042 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) {
12043 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
12044 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12045 }
12046 }
12047 } else if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
12048 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
12049 == ASC_CHIP_VER_ASYN_BUG) {
12050 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12051 }
12052 }
12053 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
12054 asc_dvc->cfg->chip_scsi_id) {
12055 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
12056 }
12057#ifdef CONFIG_ISA
12058 if (asc_dvc->bus_type & ASC_IS_ISA) {
12059 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
12060 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
12061 }
12062#endif /* CONFIG_ISA */
12063 return (warn_code);
12064}
12065
12066STATIC ushort
12067AscInitAsc1000Driver(
12068 ASC_DVC_VAR *asc_dvc
12069)
12070{
12071 ushort warn_code;
12072 PortAddr iop_base;
12073
12074 iop_base = asc_dvc->iop_base;
12075 warn_code = 0;
12076 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
12077 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
12078 AscResetChipAndScsiBus(asc_dvc);
12079 DvcSleepMilliSecond((ASC_DCNT)
12080 ((ushort) asc_dvc->scsi_reset_wait * 1000));
12081 }
12082 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
12083 if (asc_dvc->err_code != 0)
12084 return (UW_ERR);
12085 if (!AscFindSignature(asc_dvc->iop_base)) {
12086 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12087 return (warn_code);
12088 }
12089 AscDisableInterrupt(iop_base);
12090 warn_code |= AscInitLram(asc_dvc);
12091 if (asc_dvc->err_code != 0)
12092 return (UW_ERR);
12093 ASC_DBG1(1, "AscInitAsc1000Driver: _asc_mcode_chksum 0x%lx\n",
12094 (ulong) _asc_mcode_chksum);
12095 if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
12096 _asc_mcode_size) != _asc_mcode_chksum) {
12097 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
12098 return (warn_code);
12099 }
12100 warn_code |= AscInitMicroCodeVar(asc_dvc);
12101 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
12102 AscEnableInterrupt(iop_base);
12103 return (warn_code);
12104}
12105
12106STATIC ushort __init
12107AscInitAscDvcVar(
12108 ASC_DVC_VAR *asc_dvc)
12109{
12110 int i;
12111 PortAddr iop_base;
12112 ushort warn_code;
12113 uchar chip_version;
12114
12115 iop_base = asc_dvc->iop_base;
12116 warn_code = 0;
12117 asc_dvc->err_code = 0;
12118 if ((asc_dvc->bus_type &
12119 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
12120 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
12121 }
12122 AscSetChipControl(iop_base, CC_HALT);
12123 AscSetChipStatus(iop_base, 0);
12124 asc_dvc->bug_fix_cntl = 0;
12125 asc_dvc->pci_fix_asyn_xfer = 0;
12126 asc_dvc->pci_fix_asyn_xfer_always = 0;
12127 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
12128 asc_dvc->sdtr_done = 0;
12129 asc_dvc->cur_total_qng = 0;
12130 asc_dvc->is_in_int = 0;
12131 asc_dvc->in_critical_cnt = 0;
12132 asc_dvc->last_q_shortage = 0;
12133 asc_dvc->use_tagged_qng = 0;
12134 asc_dvc->no_scam = 0;
12135 asc_dvc->unit_not_ready = 0;
12136 asc_dvc->queue_full_or_busy = 0;
12137 asc_dvc->redo_scam = 0;
12138 asc_dvc->res2 = 0;
12139 asc_dvc->host_init_sdtr_index = 0;
12140 asc_dvc->cfg->can_tagged_qng = 0;
12141 asc_dvc->cfg->cmd_qng_enabled = 0;
12142 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
12143 asc_dvc->init_sdtr = 0;
12144 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
12145 asc_dvc->scsi_reset_wait = 3;
12146 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
12147 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
12148 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
12149 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
12150 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
12151 asc_dvc->cfg->lib_serial_no = ASC_LIB_SERIAL_NUMBER;
12152 asc_dvc->cfg->lib_version = (ASC_LIB_VERSION_MAJOR << 8) |
12153 ASC_LIB_VERSION_MINOR;
12154 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
12155 asc_dvc->cfg->chip_version = chip_version;
12156 asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
12157 asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
12158 asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
12159 asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
12160 asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
12161 asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
12162 asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
12163 asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
12164 asc_dvc->max_sdtr_index = 7;
12165 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
12166 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
12167 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
12168 asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
12169 asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
12170 asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
12171 asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
12172 asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
12173 asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
12174 asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
12175 asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
12176 asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
12177 asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
12178 asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
12179 asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
12180 asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
12181 asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
12182 asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
12183 asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
12184 asc_dvc->max_sdtr_index = 15;
12185 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150)
12186 {
12187 AscSetExtraControl(iop_base,
12188 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
12189 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
12190 AscSetExtraControl(iop_base,
12191 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER));
12192 }
12193 }
12194 if (asc_dvc->bus_type == ASC_IS_PCI) {
12195 AscSetExtraControl(iop_base, (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
12196 }
12197
12198 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
12199 if (AscGetChipBusType(iop_base) == ASC_IS_ISAPNP) {
12200 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
12201 asc_dvc->bus_type = ASC_IS_ISAPNP;
12202 }
12203#ifdef CONFIG_ISA
12204 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
12205 asc_dvc->cfg->isa_dma_channel = (uchar) AscGetIsaDmaChannel(iop_base);
12206 }
12207#endif /* CONFIG_ISA */
12208 for (i = 0; i <= ASC_MAX_TID; i++) {
12209 asc_dvc->cur_dvc_qng[i] = 0;
12210 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
12211 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *) 0L;
12212 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *) 0L;
12213 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
12214 }
12215 return (warn_code);
12216}
12217
12218STATIC ushort __init
12219AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
12220{
12221 ASCEEP_CONFIG eep_config_buf;
12222 ASCEEP_CONFIG *eep_config;
12223 PortAddr iop_base;
12224 ushort chksum;
12225 ushort warn_code;
12226 ushort cfg_msw, cfg_lsw;
12227 int i;
12228 int write_eep = 0;
12229
12230 iop_base = asc_dvc->iop_base;
12231 warn_code = 0;
12232 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
12233 AscStopQueueExe(iop_base);
12234 if ((AscStopChip(iop_base) == FALSE) ||
12235 (AscGetChipScsiCtrl(iop_base) != 0)) {
12236 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
12237 AscResetChipAndScsiBus(asc_dvc);
12238 DvcSleepMilliSecond((ASC_DCNT)
12239 ((ushort) asc_dvc->scsi_reset_wait * 1000));
12240 }
12241 if (AscIsChipHalted(iop_base) == FALSE) {
12242 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
12243 return (warn_code);
12244 }
12245 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
12246 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
12247 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
12248 return (warn_code);
12249 }
12250 eep_config = (ASCEEP_CONFIG *) &eep_config_buf;
12251 cfg_msw = AscGetChipCfgMsw(iop_base);
12252 cfg_lsw = AscGetChipCfgLsw(iop_base);
12253 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12254 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
12255 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12256 AscSetChipCfgMsw(iop_base, cfg_msw);
12257 }
12258 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
12259 ASC_DBG1(1, "AscInitFromEEP: chksum 0x%x\n", chksum);
12260 if (chksum == 0) {
12261 chksum = 0xaa55;
12262 }
12263 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12264 warn_code |= ASC_WARN_AUTO_CONFIG;
12265 if (asc_dvc->cfg->chip_version == 3) {
12266 if (eep_config->cfg_lsw != cfg_lsw) {
12267 warn_code |= ASC_WARN_EEPROM_RECOVER;
12268 eep_config->cfg_lsw = AscGetChipCfgLsw(iop_base);
12269 }
12270 if (eep_config->cfg_msw != cfg_msw) {
12271 warn_code |= ASC_WARN_EEPROM_RECOVER;
12272 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12273 }
12274 }
12275 }
12276 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12277 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
12278 ASC_DBG1(1, "AscInitFromEEP: eep_config->chksum 0x%x\n",
12279 eep_config->chksum);
12280 if (chksum != eep_config->chksum) {
12281 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
12282 ASC_CHIP_VER_PCI_ULTRA_3050 )
12283 {
12284 ASC_DBG(1,
12285"AscInitFromEEP: chksum error ignored; EEPROM-less board\n");
12286 eep_config->init_sdtr = 0xFF;
12287 eep_config->disc_enable = 0xFF;
12288 eep_config->start_motor = 0xFF;
12289 eep_config->use_cmd_qng = 0;
12290 eep_config->max_total_qng = 0xF0;
12291 eep_config->max_tag_qng = 0x20;
12292 eep_config->cntl = 0xBFFF;
12293 ASC_EEP_SET_CHIP_ID(eep_config, 7);
12294 eep_config->no_scam = 0;
12295 eep_config->adapter_info[0] = 0;
12296 eep_config->adapter_info[1] = 0;
12297 eep_config->adapter_info[2] = 0;
12298 eep_config->adapter_info[3] = 0;
12299 eep_config->adapter_info[4] = 0;
12300 /* Indicate EEPROM-less board. */
12301 eep_config->adapter_info[5] = 0xBB;
12302 } else {
12303 ASC_PRINT(
12304"AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
12305 write_eep = 1;
12306 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12307 }
12308 }
12309 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
12310 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
12311 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
12312 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
12313 asc_dvc->start_motor = eep_config->start_motor;
12314 asc_dvc->dvc_cntl = eep_config->cntl;
12315 asc_dvc->no_scam = eep_config->no_scam;
12316 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
12317 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
12318 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
12319 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
12320 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
12321 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
12322 if (!AscTestExternalLram(asc_dvc)) {
12323 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) {
12324 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
12325 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
12326 } else {
12327 eep_config->cfg_msw |= 0x0800;
12328 cfg_msw |= 0x0800;
12329 AscSetChipCfgMsw(iop_base, cfg_msw);
12330 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
12331 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
12332 }
12333 } else {
12334 }
12335 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
12336 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
12337 }
12338 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
12339 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
12340 }
12341 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
12342 eep_config->max_tag_qng = eep_config->max_total_qng;
12343 }
12344 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
12345 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
12346 }
12347 asc_dvc->max_total_qng = eep_config->max_total_qng;
12348 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
12349 eep_config->use_cmd_qng) {
12350 eep_config->disc_enable = eep_config->use_cmd_qng;
12351 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12352 }
12353 if (asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) {
12354 asc_dvc->irq_no = AscGetChipIRQ(iop_base, asc_dvc->bus_type);
12355 }
12356 ASC_EEP_SET_CHIP_ID(eep_config, ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
12357 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
12358 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
12359 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
12360 asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
12361 }
12362
12363 for (i = 0; i <= ASC_MAX_TID; i++) {
12364 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
12365 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
12366 asc_dvc->cfg->sdtr_period_offset[i] =
12367 (uchar) (ASC_DEF_SDTR_OFFSET |
12368 (asc_dvc->host_init_sdtr_index << 4));
12369 }
12370 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12371 if (write_eep) {
12372 if ((i = AscSetEEPConfig(iop_base, eep_config, asc_dvc->bus_type)) !=
12373 0) {
12374 ASC_PRINT1(
12375"AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n", i);
12376 } else {
12377 ASC_PRINT("AscInitFromEEP: Succesfully re-wrote EEPROM.");
12378 }
12379 }
12380 return (warn_code);
12381}
12382
12383STATIC ushort
12384AscInitMicroCodeVar(
12385 ASC_DVC_VAR *asc_dvc
12386)
12387{
12388 int i;
12389 ushort warn_code;
12390 PortAddr iop_base;
12391 ASC_PADDR phy_addr;
12392 ASC_DCNT phy_size;
12393
12394 iop_base = asc_dvc->iop_base;
12395 warn_code = 0;
12396 for (i = 0; i <= ASC_MAX_TID; i++) {
12397 AscPutMCodeInitSDTRAtID(iop_base, i,
12398 asc_dvc->cfg->sdtr_period_offset[i]
12399);
12400 }
12401
12402 AscInitQLinkVar(asc_dvc);
12403 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
12404 asc_dvc->cfg->disc_enable);
12405 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
12406 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
12407
12408 /* Align overrun buffer on an 8 byte boundary. */
12409 phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
12410 phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
12411 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
12412 (uchar *) &phy_addr, 1);
12413 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
12414 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
12415 (uchar *) &phy_size, 1);
12416
12417 asc_dvc->cfg->mcode_date =
12418 AscReadLramWord(iop_base, (ushort) ASCV_MC_DATE_W);
12419 asc_dvc->cfg->mcode_version =
12420 AscReadLramWord(iop_base, (ushort) ASCV_MC_VER_W);
12421
12422 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
12423 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
12424 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
12425 return (warn_code);
12426 }
12427 if (AscStartChip(iop_base) != 1) {
12428 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
12429 return (warn_code);
12430 }
12431
12432 return (warn_code);
12433}
12434
12435STATIC int __init
12436AscTestExternalLram(
12437 ASC_DVC_VAR *asc_dvc)
12438{
12439 PortAddr iop_base;
12440 ushort q_addr;
12441 ushort saved_word;
12442 int sta;
12443
12444 iop_base = asc_dvc->iop_base;
12445 sta = 0;
12446 q_addr = ASC_QNO_TO_QADDR(241);
12447 saved_word = AscReadLramWord(iop_base, q_addr);
12448 AscSetChipLramAddr(iop_base, q_addr);
12449 AscSetChipLramData(iop_base, 0x55AA);
12450 DvcSleepMilliSecond(10);
12451 AscSetChipLramAddr(iop_base, q_addr);
12452 if (AscGetChipLramData(iop_base) == 0x55AA) {
12453 sta = 1;
12454 AscWriteLramWord(iop_base, q_addr, saved_word);
12455 }
12456 return (sta);
12457}
12458
12459STATIC int __init
12460AscWriteEEPCmdReg(
12461 PortAddr iop_base,
12462 uchar cmd_reg
12463)
12464{
12465 uchar read_back;
12466 int retry;
12467
12468 retry = 0;
12469 while (TRUE) {
12470 AscSetChipEEPCmd(iop_base, cmd_reg);
12471 DvcSleepMilliSecond(1);
12472 read_back = AscGetChipEEPCmd(iop_base);
12473 if (read_back == cmd_reg) {
12474 return (1);
12475 }
12476 if (retry++ > ASC_EEP_MAX_RETRY) {
12477 return (0);
12478 }
12479 }
12480}
12481
12482STATIC int __init
12483AscWriteEEPDataReg(
12484 PortAddr iop_base,
12485 ushort data_reg
12486)
12487{
12488 ushort read_back;
12489 int retry;
12490
12491 retry = 0;
12492 while (TRUE) {
12493 AscSetChipEEPData(iop_base, data_reg);
12494 DvcSleepMilliSecond(1);
12495 read_back = AscGetChipEEPData(iop_base);
12496 if (read_back == data_reg) {
12497 return (1);
12498 }
12499 if (retry++ > ASC_EEP_MAX_RETRY) {
12500 return (0);
12501 }
12502 }
12503}
12504
12505STATIC void __init
12506AscWaitEEPRead(void)
12507{
12508 DvcSleepMilliSecond(1);
12509 return;
12510}
12511
12512STATIC void __init
12513AscWaitEEPWrite(void)
12514{
12515 DvcSleepMilliSecond(20);
12516 return;
12517}
12518
12519STATIC ushort __init
12520AscReadEEPWord(
12521 PortAddr iop_base,
12522 uchar addr)
12523{
12524 ushort read_wval;
12525 uchar cmd_reg;
12526
12527 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
12528 AscWaitEEPRead();
12529 cmd_reg = addr | ASC_EEP_CMD_READ;
12530 AscWriteEEPCmdReg(iop_base, cmd_reg);
12531 AscWaitEEPRead();
12532 read_wval = AscGetChipEEPData(iop_base);
12533 AscWaitEEPRead();
12534 return (read_wval);
12535}
12536
12537STATIC ushort __init
12538AscWriteEEPWord(
12539 PortAddr iop_base,
12540 uchar addr,
12541 ushort word_val)
12542{
12543 ushort read_wval;
12544
12545 read_wval = AscReadEEPWord(iop_base, addr);
12546 if (read_wval != word_val) {
12547 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
12548 AscWaitEEPRead();
12549 AscWriteEEPDataReg(iop_base, word_val);
12550 AscWaitEEPRead();
12551 AscWriteEEPCmdReg(iop_base,
12552 (uchar) ((uchar) ASC_EEP_CMD_WRITE | addr));
12553 AscWaitEEPWrite();
12554 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
12555 AscWaitEEPRead();
12556 return (AscReadEEPWord(iop_base, addr));
12557 }
12558 return (read_wval);
12559}
12560
12561STATIC ushort __init
12562AscGetEEPConfig(
12563 PortAddr iop_base,
12564 ASCEEP_CONFIG * cfg_buf, ushort bus_type)
12565{
12566 ushort wval;
12567 ushort sum;
12568 ushort *wbuf;
12569 int cfg_beg;
12570 int cfg_end;
12571 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
12572 int s_addr;
12573
12574 wbuf = (ushort *) cfg_buf;
12575 sum = 0;
12576 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
12577 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12578 *wbuf = AscReadEEPWord(iop_base, (uchar) s_addr);
12579 sum += *wbuf;
12580 }
12581 if (bus_type & ASC_IS_VL) {
12582 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12583 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12584 } else {
12585 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12586 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12587 }
12588 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12589 wval = AscReadEEPWord( iop_base, ( uchar )s_addr ) ;
12590 if (s_addr <= uchar_end_in_config) {
12591 /*
12592 * Swap all char fields - must unswap bytes already swapped
12593 * by AscReadEEPWord().
12594 */
12595 *wbuf = le16_to_cpu(wval);
12596 } else {
12597 /* Don't swap word field at the end - cntl field. */
12598 *wbuf = wval;
12599 }
12600 sum += wval; /* Checksum treats all EEPROM data as words. */
12601 }
12602 /*
12603 * Read the checksum word which will be compared against 'sum'
12604 * by the caller. Word field already swapped.
12605 */
12606 *wbuf = AscReadEEPWord(iop_base, (uchar) s_addr);
12607 return (sum);
12608}
12609
12610STATIC int __init
12611AscSetEEPConfigOnce(
12612 PortAddr iop_base,
12613 ASCEEP_CONFIG * cfg_buf, ushort bus_type)
12614{
12615 int n_error;
12616 ushort *wbuf;
12617 ushort word;
12618 ushort sum;
12619 int s_addr;
12620 int cfg_beg;
12621 int cfg_end;
12622 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
12623
12624
12625 wbuf = (ushort *) cfg_buf;
12626 n_error = 0;
12627 sum = 0;
12628 /* Write two config words; AscWriteEEPWord() will swap bytes. */
12629 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12630 sum += *wbuf;
12631 if (*wbuf != AscWriteEEPWord(iop_base, (uchar) s_addr, *wbuf)) {
12632 n_error++;
12633 }
12634 }
12635 if (bus_type & ASC_IS_VL) {
12636 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12637 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12638 } else {
12639 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12640 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12641 }
12642 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12643 if (s_addr <= uchar_end_in_config) {
12644 /*
12645 * This is a char field. Swap char fields before they are
12646 * swapped again by AscWriteEEPWord().
12647 */
12648 word = cpu_to_le16(*wbuf);
12649 if (word != AscWriteEEPWord( iop_base, (uchar) s_addr, word)) {
12650 n_error++;
12651 }
12652 } else {
12653 /* Don't swap word field at the end - cntl field. */
12654 if (*wbuf != AscWriteEEPWord(iop_base, (uchar) s_addr, *wbuf)) {
12655 n_error++;
12656 }
12657 }
12658 sum += *wbuf; /* Checksum calculated from word values. */
12659 }
12660 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
12661 *wbuf = sum;
12662 if (sum != AscWriteEEPWord(iop_base, (uchar) s_addr, sum)) {
12663 n_error++;
12664 }
12665
12666 /* Read EEPROM back again. */
12667 wbuf = (ushort *) cfg_buf;
12668 /*
12669 * Read two config words; Byte-swapping done by AscReadEEPWord().
12670 */
12671 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12672 if (*wbuf != AscReadEEPWord(iop_base, (uchar) s_addr)) {
12673 n_error++;
12674 }
12675 }
12676 if (bus_type & ASC_IS_VL) {
12677 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12678 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12679 } else {
12680 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12681 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12682 }
12683 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12684 if (s_addr <= uchar_end_in_config) {
12685 /*
12686 * Swap all char fields. Must unswap bytes already swapped
12687 * by AscReadEEPWord().
12688 */
12689 word = le16_to_cpu(AscReadEEPWord(iop_base, (uchar) s_addr));
12690 } else {
12691 /* Don't swap word field at the end - cntl field. */
12692 word = AscReadEEPWord(iop_base, (uchar) s_addr);
12693 }
12694 if (*wbuf != word) {
12695 n_error++;
12696 }
12697 }
12698 /* Read checksum; Byte swapping not needed. */
12699 if (AscReadEEPWord(iop_base, (uchar) s_addr) != sum) {
12700 n_error++;
12701 }
12702 return (n_error);
12703}
12704
12705STATIC int __init
12706AscSetEEPConfig(
12707 PortAddr iop_base,
12708 ASCEEP_CONFIG * cfg_buf, ushort bus_type
12709)
12710{
12711 int retry;
12712 int n_error;
12713
12714 retry = 0;
12715 while (TRUE) {
12716 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
12717 bus_type)) == 0) {
12718 break;
12719 }
12720 if (++retry > ASC_EEP_MAX_RETRY) {
12721 break;
12722 }
12723 }
12724 return (n_error);
12725}
12726
12727STATIC void
12728AscAsyncFix(
12729 ASC_DVC_VAR *asc_dvc,
12730 uchar tid_no,
12731 ASC_SCSI_INQUIRY *inq)
12732{
12733 uchar dvc_type;
12734 ASC_SCSI_BIT_ID_TYPE tid_bits;
12735
12736 dvc_type = ASC_INQ_DVC_TYPE(inq);
12737 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no);
12738
12739 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN)
12740 {
12741 if (!(asc_dvc->init_sdtr & tid_bits))
12742 {
12743 if ((dvc_type == TYPE_ROM) &&
12744 (AscCompareString((uchar *) inq->vendor_id,
12745 (uchar *) "HP ", 3) == 0))
12746 {
12747 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
12748 }
12749 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
12750 if ((dvc_type == TYPE_PROCESSOR) ||
12751 (dvc_type == TYPE_SCANNER) ||
12752 (dvc_type == TYPE_ROM) ||
12753 (dvc_type == TYPE_TAPE))
12754 {
12755 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
12756 }
12757
12758 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
12759 {
12760 AscSetRunChipSynRegAtID(asc_dvc->iop_base, tid_no,
12761 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
12762 }
12763 }
12764 }
12765 return;
12766}
12767
12768STATIC int
12769AscTagQueuingSafe(ASC_SCSI_INQUIRY *inq)
12770{
12771 if ((inq->add_len >= 32) &&
12772 (AscCompareString((uchar *) inq->vendor_id,
12773 (uchar *) "QUANTUM XP34301", 15) == 0) &&
12774 (AscCompareString((uchar *) inq->product_rev_level,
12775 (uchar *) "1071", 4) == 0))
12776 {
12777 return 0;
12778 }
12779 return 1;
12780}
12781
12782STATIC void
12783AscInquiryHandling(ASC_DVC_VAR *asc_dvc,
12784 uchar tid_no, ASC_SCSI_INQUIRY *inq)
12785{
12786 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no);
12787 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng;
12788
12789 orig_init_sdtr = asc_dvc->init_sdtr;
12790 orig_use_tagged_qng = asc_dvc->use_tagged_qng;
12791
12792 asc_dvc->init_sdtr &= ~tid_bit;
12793 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
12794 asc_dvc->use_tagged_qng &= ~tid_bit;
12795
12796 if (ASC_INQ_RESPONSE_FMT(inq) >= 2 || ASC_INQ_ANSI_VER(inq) >= 2) {
12797 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && ASC_INQ_SYNC(inq)) {
12798 asc_dvc->init_sdtr |= tid_bit;
12799 }
12800 if ((asc_dvc->cfg->cmd_qng_enabled & tid_bit) &&
12801 ASC_INQ_CMD_QUEUE(inq)) {
12802 if (AscTagQueuingSafe(inq)) {
12803 asc_dvc->use_tagged_qng |= tid_bit;
12804 asc_dvc->cfg->can_tagged_qng |= tid_bit;
12805 }
12806 }
12807 }
12808 if (orig_use_tagged_qng != asc_dvc->use_tagged_qng) {
12809 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
12810 asc_dvc->cfg->disc_enable);
12811 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
12812 asc_dvc->use_tagged_qng);
12813 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
12814 asc_dvc->cfg->can_tagged_qng);
12815
12816 asc_dvc->max_dvc_qng[tid_no] =
12817 asc_dvc->cfg->max_tag_qng[tid_no];
12818 AscWriteLramByte(asc_dvc->iop_base,
12819 (ushort) (ASCV_MAX_DVC_QNG_BEG + tid_no),
12820 asc_dvc->max_dvc_qng[tid_no]);
12821 }
12822 if (orig_init_sdtr != asc_dvc->init_sdtr) {
12823 AscAsyncFix(asc_dvc, tid_no, inq);
12824 }
12825 return;
12826}
12827
12828STATIC int
12829AscCompareString(
12830 uchar *str1,
12831 uchar *str2,
12832 int len
12833)
12834{
12835 int i;
12836 int diff;
12837
12838 for (i = 0; i < len; i++) {
12839 diff = (int) (str1[i] - str2[i]);
12840 if (diff != 0)
12841 return (diff);
12842 }
12843 return (0);
12844}
12845
12846STATIC uchar
12847AscReadLramByte(
12848 PortAddr iop_base,
12849 ushort addr
12850)
12851{
12852 uchar byte_data;
12853 ushort word_data;
12854
12855 if (isodd_word(addr)) {
12856 AscSetChipLramAddr(iop_base, addr - 1);
12857 word_data = AscGetChipLramData(iop_base);
12858 byte_data = (uchar) ((word_data >> 8) & 0xFF);
12859 } else {
12860 AscSetChipLramAddr(iop_base, addr);
12861 word_data = AscGetChipLramData(iop_base);
12862 byte_data = (uchar) (word_data & 0xFF);
12863 }
12864 return (byte_data);
12865}
12866STATIC ushort
12867AscReadLramWord(
12868 PortAddr iop_base,
12869 ushort addr
12870)
12871{
12872 ushort word_data;
12873
12874 AscSetChipLramAddr(iop_base, addr);
12875 word_data = AscGetChipLramData(iop_base);
12876 return (word_data);
12877}
12878
12879#if CC_VERY_LONG_SG_LIST
12880STATIC ASC_DCNT
12881AscReadLramDWord(
12882 PortAddr iop_base,
12883 ushort addr
12884)
12885{
12886 ushort val_low, val_high;
12887 ASC_DCNT dword_data;
12888
12889 AscSetChipLramAddr(iop_base, addr);
12890 val_low = AscGetChipLramData(iop_base);
12891 val_high = AscGetChipLramData(iop_base);
12892 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
12893 return (dword_data);
12894}
12895#endif /* CC_VERY_LONG_SG_LIST */
12896
12897STATIC void
12898AscWriteLramWord(
12899 PortAddr iop_base,
12900 ushort addr,
12901 ushort word_val
12902)
12903{
12904 AscSetChipLramAddr(iop_base, addr);
12905 AscSetChipLramData(iop_base, word_val);
12906 return;
12907}
12908
12909STATIC void
12910AscWriteLramByte(
12911 PortAddr iop_base,
12912 ushort addr,
12913 uchar byte_val
12914)
12915{
12916 ushort word_data;
12917
12918 if (isodd_word(addr)) {
12919 addr--;
12920 word_data = AscReadLramWord(iop_base, addr);
12921 word_data &= 0x00FF;
12922 word_data |= (((ushort) byte_val << 8) & 0xFF00);
12923 } else {
12924 word_data = AscReadLramWord(iop_base, addr);
12925 word_data &= 0xFF00;
12926 word_data |= ((ushort) byte_val & 0x00FF);
12927 }
12928 AscWriteLramWord(iop_base, addr, word_data);
12929 return;
12930}
12931
12932/*
12933 * Copy 2 bytes to LRAM.
12934 *
12935 * The source data is assumed to be in little-endian order in memory
12936 * and is maintained in little-endian order when written to LRAM.
12937 */
12938STATIC void
12939AscMemWordCopyPtrToLram(
12940 PortAddr iop_base,
12941 ushort s_addr,
12942 uchar *s_buffer,
12943 int words
12944)
12945{
12946 int i;
12947
12948 AscSetChipLramAddr(iop_base, s_addr);
12949 for (i = 0; i < 2 * words; i += 2) {
12950 /*
12951 * On a little-endian system the second argument below
12952 * produces a little-endian ushort which is written to
12953 * LRAM in little-endian order. On a big-endian system
12954 * the second argument produces a big-endian ushort which
12955 * is "transparently" byte-swapped by outpw() and written
12956 * in little-endian order to LRAM.
12957 */
12958 outpw(iop_base + IOP_RAM_DATA,
12959 ((ushort) s_buffer[i + 1] << 8) | s_buffer[i]);
12960 }
12961 return;
12962}
12963
12964/*
12965 * Copy 4 bytes to LRAM.
12966 *
12967 * The source data is assumed to be in little-endian order in memory
12968 * and is maintained in little-endian order when writen to LRAM.
12969 */
12970STATIC void
12971AscMemDWordCopyPtrToLram(
12972 PortAddr iop_base,
12973 ushort s_addr,
12974 uchar *s_buffer,
12975 int dwords
12976)
12977{
12978 int i;
12979
12980 AscSetChipLramAddr(iop_base, s_addr);
12981 for (i = 0; i < 4 * dwords; i += 4) {
12982 outpw(iop_base + IOP_RAM_DATA,
12983 ((ushort) s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
12984 outpw(iop_base + IOP_RAM_DATA,
12985 ((ushort) s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
12986 }
12987 return;
12988}
12989
12990/*
12991 * Copy 2 bytes from LRAM.
12992 *
12993 * The source data is assumed to be in little-endian order in LRAM
12994 * and is maintained in little-endian order when written to memory.
12995 */
12996STATIC void
12997AscMemWordCopyPtrFromLram(
12998 PortAddr iop_base,
12999 ushort s_addr,
13000 uchar *d_buffer,
13001 int words
13002)
13003{
13004 int i;
13005 ushort word;
13006
13007 AscSetChipLramAddr(iop_base, s_addr);
13008 for (i = 0; i < 2 * words; i += 2) {
13009 word = inpw(iop_base + IOP_RAM_DATA);
13010 d_buffer[i] = word & 0xff;
13011 d_buffer[i + 1] = (word >> 8) & 0xff;
13012 }
13013 return;
13014}
13015
13016STATIC ASC_DCNT
13017AscMemSumLramWord(
13018 PortAddr iop_base,
13019 ushort s_addr,
13020 int words
13021)
13022{
13023 ASC_DCNT sum;
13024 int i;
13025
13026 sum = 0L;
13027 for (i = 0; i < words; i++, s_addr += 2) {
13028 sum += AscReadLramWord(iop_base, s_addr);
13029 }
13030 return (sum);
13031}
13032
13033STATIC void
13034AscMemWordSetLram(
13035 PortAddr iop_base,
13036 ushort s_addr,
13037 ushort set_wval,
13038 int words
13039)
13040{
13041 int i;
13042
13043 AscSetChipLramAddr(iop_base, s_addr);
13044 for (i = 0; i < words; i++) {
13045 AscSetChipLramData(iop_base, set_wval);
13046 }
13047 return;
13048}
13049
13050
13051/*
13052 * --- Adv Library Functions
13053 */
13054
13055/* a_mcode.h */
13056
13057/* Microcode buffer is kept after initialization for error recovery. */
13058STATIC unsigned char _adv_asc3550_buf[] = {
13059 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc, 0x01, 0x00, 0x48, 0xe4,
13060 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7,
13061 0xff, 0x00, 0x82, 0xe7, 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
13062 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00, 0x00, 0xec, 0x85, 0xf0,
13063 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54, 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00,
13064 0x98, 0x57, 0xd0, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
13065 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea,
13066 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00,
13067 0xc0, 0x00, 0x01, 0x01, 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
13068 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00, 0x3e, 0x00, 0x80, 0x00,
13069 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01,
13070 0x78, 0x01, 0x62, 0x0a, 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
13071 0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
13072 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00, 0x00, 0x01, 0xb0, 0x08, 0x30, 0x13, 0x64, 0x15,
13073 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44, 0x02, 0x48, 0x00, 0x4c, 0x04, 0xea, 0x5d, 0xf0,
13074 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01,
13075 0x4e, 0x01, 0x4e, 0x0b, 0x1e, 0x0e, 0x0c, 0x10, 0x0a, 0x12, 0x04, 0x13, 0x40, 0x13, 0x30, 0x1c,
13076 0x00, 0x4e, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xa7, 0xf0,
13077 0xb8, 0xf0, 0x0e, 0xf7, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00, 0xa4, 0x00, 0xb5, 0x00,
13078 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xde, 0x03, 0x56, 0x0a, 0x14, 0x0e, 0x02, 0x10,
13079 0x04, 0x10, 0x0a, 0x10, 0x36, 0x10, 0x0a, 0x13, 0x12, 0x13, 0x52, 0x13, 0x10, 0x15, 0x14, 0x15,
13080 0xac, 0x16, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45,
13081 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x83, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6,
13082 0x0b, 0xf0, 0x0c, 0xf0, 0x5c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8, 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa,
13083 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x1c, 0x00, 0x9e, 0x00, 0xa8, 0x00,
13084 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7a, 0x01, 0xc0, 0x01,
13085 0xc2, 0x01, 0x7c, 0x02, 0x5a, 0x03, 0xea, 0x04, 0xe8, 0x07, 0x68, 0x08, 0x69, 0x08, 0xba, 0x08,
13086 0xe9, 0x09, 0x06, 0x0b, 0x3a, 0x0e, 0x00, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10, 0x06, 0x12,
13087 0x0c, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x82, 0x13, 0x42, 0x14, 0xd6, 0x14, 0x8a, 0x15, 0xc6, 0x17,
13088 0xd2, 0x17, 0x6b, 0x18, 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, 0x0e, 0x47, 0x48, 0x47,
13089 0x41, 0x48, 0x89, 0x48, 0x80, 0x4c, 0x00, 0x54, 0x44, 0x55, 0xe5, 0x55, 0x14, 0x56, 0x77, 0x57,
13090 0xbf, 0x57, 0x40, 0x5c, 0x06, 0x80, 0x08, 0x90, 0x03, 0xa1, 0xfe, 0x9c, 0xf0, 0x29, 0x02, 0xfe,
13091 0xb8, 0x0c, 0xff, 0x10, 0x00, 0x00, 0xd0, 0xfe, 0xcc, 0x18, 0x00, 0xcf, 0xfe, 0x80, 0x01, 0xff,
13092 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00, 0x00, 0xfe, 0x57, 0x24,
13093 0x00, 0xfe, 0x48, 0x00, 0x4f, 0xff, 0x04, 0x00, 0x00, 0x10, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08,
13094 0x01, 0x01, 0xff, 0x08, 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x0f,
13095 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00, 0xfe, 0x04, 0xf7, 0xcf,
13096 0x2a, 0x67, 0x0b, 0x01, 0xfe, 0xce, 0x0e, 0xfe, 0x04, 0xf7, 0xcf, 0x67, 0x0b, 0x3c, 0x2a, 0xfe,
13097 0x3d, 0xf0, 0xfe, 0x02, 0x02, 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x91, 0xf0, 0xfe, 0xf0, 0x01, 0xfe,
13098 0x90, 0xf0, 0xfe, 0xf0, 0x01, 0xfe, 0x8f, 0xf0, 0x9c, 0x05, 0x51, 0x3b, 0x02, 0xfe, 0xd4, 0x0c,
13099 0x01, 0xfe, 0x44, 0x0d, 0xfe, 0xdd, 0x12, 0xfe, 0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x05, 0xfe, 0xa6,
13100 0x00, 0xfe, 0xd3, 0x12, 0x47, 0x18, 0xfe, 0xa6, 0x00, 0xb5, 0xfe, 0x48, 0xf0, 0xfe, 0x86, 0x02,
13101 0xfe, 0x49, 0xf0, 0xfe, 0xa0, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xbe, 0x02, 0xfe, 0x46, 0xf0, 0xfe,
13102 0x50, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x56, 0x02, 0xfe, 0x43, 0xf0, 0xfe, 0x44, 0x02, 0xfe, 0x44,
13103 0xf0, 0xfe, 0x48, 0x02, 0xfe, 0x45, 0xf0, 0xfe, 0x4c, 0x02, 0x17, 0x0b, 0xa0, 0x17, 0x06, 0x18,
13104 0x96, 0x02, 0x29, 0xfe, 0x00, 0x1c, 0xde, 0xfe, 0x02, 0x1c, 0xdd, 0xfe, 0x1e, 0x1c, 0xfe, 0xe9,
13105 0x10, 0x01, 0xfe, 0x20, 0x17, 0xfe, 0xe7, 0x10, 0xfe, 0x06, 0xfc, 0xc7, 0x0a, 0x6b, 0x01, 0x9e,
13106 0x02, 0x29, 0x14, 0x4d, 0x37, 0x97, 0x01, 0xfe, 0x64, 0x0f, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xbd,
13107 0x10, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe, 0x58, 0x1c, 0x17, 0x06,
13108 0x18, 0x96, 0x2a, 0x25, 0x29, 0xfe, 0x3d, 0xf0, 0xfe, 0x02, 0x02, 0x21, 0xfe, 0x94, 0x02, 0xfe,
13109 0x5a, 0x1c, 0xea, 0xfe, 0x14, 0x1c, 0x14, 0xfe, 0x30, 0x00, 0x37, 0x97, 0x01, 0xfe, 0x54, 0x0f,
13110 0x17, 0x06, 0x18, 0x96, 0x02, 0xd0, 0x1e, 0x20, 0x07, 0x10, 0x34, 0xfe, 0x69, 0x10, 0x17, 0x06,
13111 0x18, 0x96, 0xfe, 0x04, 0xec, 0x20, 0x46, 0x3d, 0x12, 0x20, 0xfe, 0x05, 0xf6, 0xc7, 0x01, 0xfe,
13112 0x52, 0x16, 0x09, 0x4a, 0x4c, 0x35, 0x11, 0x2d, 0x3c, 0x8a, 0x01, 0xe6, 0x02, 0x29, 0x0a, 0x40,
13113 0x01, 0x0e, 0x07, 0x00, 0x5d, 0x01, 0x6f, 0xfe, 0x18, 0x10, 0xfe, 0x41, 0x58, 0x0a, 0x99, 0x01,
13114 0x0e, 0xfe, 0xc8, 0x54, 0x64, 0xfe, 0x0c, 0x03, 0x01, 0xe6, 0x02, 0x29, 0x2a, 0x46, 0xfe, 0x02,
13115 0xe8, 0x27, 0xf8, 0xfe, 0x9e, 0x43, 0xf7, 0xfe, 0x27, 0xf0, 0xfe, 0xdc, 0x01, 0xfe, 0x07, 0x4b,
13116 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x40, 0x1c, 0x25, 0xd2, 0xfe, 0x26, 0xf0, 0xfe, 0x56, 0x03, 0xfe,
13117 0xa0, 0xf0, 0xfe, 0x44, 0x03, 0xfe, 0x11, 0xf0, 0x9c, 0xfe, 0xef, 0x10, 0xfe, 0x9f, 0xf0, 0xfe,
13118 0x64, 0x03, 0xeb, 0x0f, 0xfe, 0x11, 0x00, 0x02, 0x5a, 0x2a, 0xfe, 0x48, 0x1c, 0xeb, 0x09, 0x04,
13119 0x1d, 0xfe, 0x18, 0x13, 0x23, 0x1e, 0x98, 0xac, 0x12, 0x98, 0x0a, 0x40, 0x01, 0x0e, 0xac, 0x75,
13120 0x01, 0xfe, 0xbc, 0x15, 0x11, 0xca, 0x25, 0xd2, 0xfe, 0x01, 0xf0, 0xd2, 0xfe, 0x82, 0xf0, 0xfe,
13121 0x92, 0x03, 0xec, 0x11, 0xfe, 0xe4, 0x00, 0x65, 0xfe, 0xa4, 0x03, 0x25, 0x32, 0x1f, 0xfe, 0xb4,
13122 0x03, 0x01, 0x43, 0xfe, 0x06, 0xf0, 0xfe, 0xc4, 0x03, 0x8d, 0x81, 0xfe, 0x0a, 0xf0, 0xfe, 0x7a,
13123 0x06, 0x02, 0x22, 0x05, 0x6b, 0x28, 0x16, 0xfe, 0xf6, 0x04, 0x14, 0x2c, 0x01, 0x33, 0x8f, 0xfe,
13124 0x66, 0x02, 0x02, 0xd1, 0xeb, 0x2a, 0x67, 0x1a, 0xfe, 0x67, 0x1b, 0xf8, 0xf7, 0xfe, 0x48, 0x1c,
13125 0x70, 0x01, 0x6e, 0x87, 0x0a, 0x40, 0x01, 0x0e, 0x07, 0x00, 0x16, 0xd3, 0x0a, 0xca, 0x01, 0x0e,
13126 0x74, 0x60, 0x59, 0x76, 0x27, 0x05, 0x6b, 0x28, 0xfe, 0x10, 0x12, 0x14, 0x2c, 0x01, 0x33, 0x8f,
13127 0xfe, 0x66, 0x02, 0x02, 0xd1, 0xbc, 0x7d, 0xbd, 0x7f, 0x25, 0x22, 0x65, 0xfe, 0x3c, 0x04, 0x1f,
13128 0xfe, 0x38, 0x04, 0x68, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e, 0x12, 0x2b, 0xff, 0x02,
13129 0x00, 0x10, 0x01, 0x08, 0x1f, 0xfe, 0xe0, 0x04, 0x2b, 0x01, 0x08, 0x1f, 0x22, 0x30, 0x2e, 0xd5,
13130 0xfe, 0x4c, 0x44, 0xfe, 0x4c, 0x12, 0x60, 0xfe, 0x44, 0x48, 0x13, 0x2c, 0xfe, 0x4c, 0x54, 0x64,
13131 0xd3, 0x46, 0x76, 0x27, 0xfa, 0xef, 0xfe, 0x62, 0x13, 0x09, 0x04, 0x1d, 0xfe, 0x2a, 0x13, 0x2f,
13132 0x07, 0x7e, 0xa5, 0xfe, 0x20, 0x10, 0x13, 0x2c, 0xfe, 0x4c, 0x54, 0x64, 0xd3, 0xfa, 0xef, 0x86,
13133 0x09, 0x04, 0x1d, 0xfe, 0x08, 0x13, 0x2f, 0x07, 0x7e, 0x6e, 0x09, 0x04, 0x1d, 0xfe, 0x1c, 0x12,
13134 0x14, 0x92, 0x09, 0x04, 0x06, 0x3b, 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe, 0x70, 0x0c, 0x02, 0x22,
13135 0x2b, 0x11, 0xfe, 0xe6, 0x00, 0xfe, 0x1c, 0x90, 0xf9, 0x03, 0x14, 0x92, 0x01, 0x33, 0x02, 0x29,
13136 0xfe, 0x42, 0x5b, 0x67, 0x1a, 0xfe, 0x46, 0x59, 0xf8, 0xf7, 0xfe, 0x87, 0x80, 0xfe, 0x31, 0xe4,
13137 0x4f, 0x09, 0x04, 0x0b, 0xfe, 0x78, 0x13, 0xfe, 0x20, 0x80, 0x07, 0x1a, 0xfe, 0x70, 0x12, 0x49,
13138 0x04, 0x06, 0xfe, 0x60, 0x13, 0x05, 0xfe, 0xa2, 0x00, 0x28, 0x16, 0xfe, 0x80, 0x05, 0xfe, 0x31,
13139 0xe4, 0x6a, 0x49, 0x04, 0x0b, 0xfe, 0x4a, 0x13, 0x05, 0xfe, 0xa0, 0x00, 0x28, 0xfe, 0x42, 0x12,
13140 0x5e, 0x01, 0x08, 0x25, 0x32, 0xf1, 0x01, 0x08, 0x26, 0xfe, 0x98, 0x05, 0x11, 0xfe, 0xe3, 0x00,
13141 0x23, 0x49, 0xfe, 0x4a, 0xf0, 0xfe, 0x6a, 0x05, 0xfe, 0x49, 0xf0, 0xfe, 0x64, 0x05, 0x83, 0x24,
13142 0xfe, 0x21, 0x00, 0xa1, 0x24, 0xfe, 0x22, 0x00, 0xa0, 0x24, 0x4c, 0xfe, 0x09, 0x48, 0x01, 0x08,
13143 0x26, 0xfe, 0x98, 0x05, 0xfe, 0xe2, 0x08, 0x49, 0x04, 0xc5, 0x3b, 0x01, 0x86, 0x24, 0x06, 0x12,
13144 0xcc, 0x37, 0xfe, 0x27, 0x01, 0x09, 0x04, 0x1d, 0xfe, 0x22, 0x12, 0x47, 0x01, 0xa7, 0x14, 0x92,
13145 0x09, 0x04, 0x06, 0x3b, 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe, 0x70, 0x0c, 0x02, 0x22, 0x05, 0xfe,
13146 0x9c, 0x00, 0x28, 0xfe, 0x3e, 0x12, 0x05, 0x50, 0x28, 0xfe, 0x36, 0x13, 0x47, 0x01, 0xa7, 0x26,
13147 0xfe, 0x08, 0x06, 0x0a, 0x06, 0x49, 0x04, 0x19, 0xfe, 0x02, 0x12, 0x5f, 0x01, 0xfe, 0xaa, 0x14,
13148 0x1f, 0xfe, 0xfe, 0x05, 0x11, 0x9a, 0x01, 0x43, 0x11, 0xfe, 0xe5, 0x00, 0x05, 0x50, 0xb4, 0x0c,
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13266 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xfe, 0x80, 0x5c, 0x01, 0x6f, 0xfe, 0x0e, 0x10, 0x07, 0x7e, 0x45,
13267 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x6c, 0x0f, 0x03, 0xfe, 0x44, 0x58, 0x74, 0xfe, 0x01, 0xec, 0x97,
13268 0xfe, 0x9e, 0x40, 0xfe, 0x9d, 0xe7, 0x00, 0xfe, 0x9c, 0xe7, 0x1b, 0x76, 0x27, 0x01, 0xda, 0xfe,
13269 0xdd, 0x10, 0x2a, 0xbc, 0x7d, 0xbd, 0x7f, 0x30, 0x2e, 0xd5, 0x07, 0x1b, 0xfe, 0x48, 0x12, 0x07,
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13271 0xfe, 0x23, 0x00, 0x16, 0xfe, 0x4a, 0x11, 0x07, 0x06, 0x16, 0xfe, 0xa8, 0x11, 0x07, 0x19, 0xfe,
13272 0x12, 0x12, 0x07, 0x00, 0x16, 0x22, 0x14, 0xc2, 0x01, 0x33, 0x9f, 0x2b, 0x01, 0x08, 0x8c, 0x43,
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13274 0x2f, 0x07, 0x9b, 0xfe, 0xd9, 0x13, 0x79, 0x39, 0x68, 0x3a, 0x77, 0xfe, 0xfc, 0x10, 0x09, 0x04,
13275 0x6a, 0xfe, 0x72, 0x12, 0xc0, 0x38, 0xc1, 0x4e, 0xf4, 0xf5, 0x8e, 0xfe, 0xc6, 0x10, 0x1e, 0x58,
13276 0xfe, 0x26, 0x13, 0x05, 0x7b, 0x31, 0x7c, 0x77, 0xfe, 0x82, 0x0c, 0x0c, 0x54, 0x18, 0x55, 0x23,
13277 0x0c, 0x7b, 0x0c, 0x7c, 0x01, 0xa8, 0x24, 0x69, 0x73, 0x12, 0x58, 0x01, 0xa5, 0xc0, 0x38, 0xc1,
13278 0x4e, 0xfe, 0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe, 0x04, 0xfa, 0x38, 0xfe, 0x05, 0xfa, 0x4e, 0xfe,
13279 0x91, 0x10, 0x05, 0x56, 0x31, 0x57, 0xfe, 0x40, 0x56, 0xfe, 0xe1, 0x56, 0x0c, 0x56, 0x18, 0x57,
13280 0x83, 0xc0, 0x38, 0xc1, 0x4e, 0xf4, 0xf5, 0x05, 0x52, 0x31, 0x53, 0xfe, 0x00, 0x56, 0xfe, 0xa1,
13281 0x56, 0x0c, 0x52, 0x18, 0x53, 0x09, 0x04, 0x6a, 0xfe, 0x1e, 0x12, 0x1e, 0x58, 0xfe, 0x1f, 0x40,
13282 0x05, 0x54, 0x31, 0x55, 0xfe, 0x2c, 0x50, 0xfe, 0xae, 0x50, 0x05, 0x56, 0x31, 0x57, 0xfe, 0x44,
13283 0x50, 0xfe, 0xc6, 0x50, 0x05, 0x52, 0x31, 0x53, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0x05, 0x39,
13284 0x31, 0x3a, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x02, 0x5c, 0x24, 0x06, 0x12, 0xcd, 0x02, 0x5b,
13285 0x2b, 0x01, 0x08, 0x1f, 0x44, 0x30, 0x2e, 0xd5, 0x07, 0x06, 0x21, 0x44, 0x2f, 0x07, 0x9b, 0x21,
13286 0x5b, 0x01, 0x6e, 0x1c, 0x3d, 0x16, 0x44, 0x09, 0x04, 0x0b, 0xe2, 0x79, 0x39, 0x68, 0x3a, 0xfe,
13287 0x0a, 0x55, 0x34, 0xfe, 0x8b, 0x55, 0xbe, 0x39, 0xbf, 0x3a, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51,
13288 0x02, 0x5b, 0xfe, 0x19, 0x81, 0xaf, 0xfe, 0x19, 0x41, 0x02, 0x5b, 0x2b, 0x01, 0x08, 0x25, 0x32,
13289 0x1f, 0xa2, 0x30, 0x2e, 0xd8, 0x4b, 0x1a, 0xfe, 0xa6, 0x12, 0x4b, 0x0b, 0x3b, 0x02, 0x44, 0x01,
13290 0x08, 0x25, 0x32, 0x1f, 0xa2, 0x30, 0x2e, 0xd6, 0x07, 0x1a, 0x21, 0x44, 0x01, 0x08, 0x1f, 0xa2,
13291 0x30, 0x2e, 0xfe, 0xe8, 0x09, 0xfe, 0xc2, 0x49, 0x60, 0x05, 0xfe, 0x9c, 0x00, 0x28, 0x84, 0x49,
13292 0x04, 0x19, 0x34, 0x9f, 0xfe, 0xbb, 0x45, 0x4b, 0x00, 0x45, 0x3e, 0x06, 0x78, 0x3d, 0xfe, 0xda,
13293 0x14, 0x01, 0x6e, 0x87, 0xfe, 0x4b, 0x45, 0xe2, 0x2f, 0x07, 0x9a, 0xe1, 0x05, 0xc6, 0x28, 0x84,
13294 0x05, 0x3f, 0x28, 0x34, 0x5e, 0x02, 0x5b, 0xfe, 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17,
13295 0x05, 0x50, 0xb4, 0x0c, 0x50, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xaa, 0x14, 0x02,
13296 0x5c, 0x01, 0x08, 0x25, 0x32, 0x1f, 0x44, 0x30, 0x2e, 0xd6, 0x07, 0x06, 0x21, 0x44, 0x01, 0xfe,
13297 0x8e, 0x13, 0xfe, 0x42, 0x58, 0xfe, 0x82, 0x14, 0xfe, 0xa4, 0x14, 0x87, 0xfe, 0x4a, 0xf4, 0x0b,
13298 0x16, 0x44, 0xfe, 0x4a, 0xf4, 0x06, 0xfe, 0x0c, 0x12, 0x2f, 0x07, 0x9a, 0x85, 0x02, 0x5b, 0x05,
13299 0x3f, 0xb4, 0x0c, 0x3f, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xd8, 0x14, 0x02, 0x5c,
13300 0x13, 0x06, 0x65, 0xfe, 0xca, 0x12, 0x26, 0xfe, 0xe0, 0x12, 0x72, 0xf1, 0x01, 0x08, 0x23, 0x72,
13301 0x03, 0x8f, 0xfe, 0xdc, 0x12, 0x25, 0xfe, 0xdc, 0x12, 0x1f, 0xfe, 0xca, 0x12, 0x5e, 0x2b, 0x01,
13302 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0xfe, 0xff, 0x7f,
13303 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c,
13304 0x3d, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
13305 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0xfe, 0x0b, 0x58, 0x03, 0x0a, 0x50, 0x01,
13306 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c, 0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4,
13307 0x19, 0x48, 0xfe, 0x00, 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27,
13308 0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08, 0xfe, 0x82, 0x4a, 0xfe,
13309 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01, 0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60,
13310 0x89, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14,
13311 0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe, 0xcc, 0x12, 0x49, 0x04,
13312 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2, 0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13,
13313 0x06, 0x17, 0xc3, 0x78, 0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83,
13314 0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c, 0x13, 0x06, 0xfe, 0x56,
13315 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00, 0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93,
13316 0x13, 0x06, 0xfe, 0x28, 0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4,
13317 0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90, 0x01, 0xba, 0xfe, 0x4e,
13318 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4, 0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe,
13319 0x04, 0xf4, 0x6c, 0xfe, 0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c,
13320 0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba, 0xfe, 0x9c, 0x14, 0xb7,
13321 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7,
13322 0x19, 0x83, 0x60, 0x23, 0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
13323 0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x0b, 0x01,
13324 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03,
13325 0x15, 0x06, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
13326 0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89, 0x4a, 0x01, 0x08, 0x03,
13327 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44, 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00,
13328 0x3b, 0x72, 0x9f, 0x5e, 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
13329 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd, 0x01, 0x43, 0x1e, 0xcd,
13330 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10,
13331 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
13332 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3, 0x88, 0x03, 0x0a, 0x42,
13333 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2,
13334 0xfe, 0x49, 0xe4, 0x10, 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
13335 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, 0x1c, 0xfe,
13336 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01, 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe,
13337 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
13338 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58, 0x05, 0xfe, 0x66, 0x01,
13339 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66,
13340 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
13341 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17, 0x10, 0x71, 0xfe, 0x83,
13342 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe,
13343 0x94, 0x14, 0xfe, 0x10, 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
13344 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71, 0xfe, 0x30, 0xbc, 0xfe,
13345 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a,
13346 0x16, 0xfe, 0x5c, 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
13347 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc, 0xfe, 0x1d, 0xf7, 0x4f,
13348 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58,
13349 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
13350 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14, 0x06, 0x37, 0x95, 0xa9,
13351 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17, 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d,
13352 0x13, 0x0d, 0x03, 0x71, 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
13353 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x3c, 0x8a, 0x0a,
13354 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0, 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc,
13355 0xb0, 0xfe, 0xf3, 0x13, 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
13356 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xf6, 0xfe, 0xd6, 0xf0,
13357 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c, 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76,
13358 0x27, 0x01, 0xda, 0x17, 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
13359 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68, 0xc8, 0xfe, 0x48, 0x55,
13360 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73, 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0,
13361 0x0a, 0x40, 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
13362 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01, 0x0e, 0x73, 0x75, 0x03,
13363 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18, 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b,
13364 0xfe, 0x4e, 0xe4, 0xc2, 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
13365 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05, 0xfe, 0x94, 0x00, 0xfe,
13366 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e,
13367 0x45, 0xfe, 0x0c, 0x12, 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
13368 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1b, 0xfe, 0x5a,
13369 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26, 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07,
13370 0x0b, 0x5d, 0x24, 0x93, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
13371 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9, 0x03, 0x25, 0xfe, 0xca,
13372 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6, 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
13373};
13374
13375STATIC unsigned short _adv_asc3550_size =
13376 sizeof(_adv_asc3550_buf); /* 0x13AD */
13377STATIC ADV_DCNT _adv_asc3550_chksum =
13378 0x04D52DDDUL; /* Expanded little-endian checksum. */
13379
13380/* Microcode buffer is kept after initialization for error recovery. */
13381STATIC unsigned char _adv_asc38C0800_buf[] = {
13382 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4, 0x01, 0x00, 0x48, 0xe4,
13383 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19, 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6,
13384 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
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13613 0x07, 0x00, 0x17, 0x24, 0x15, 0xc9, 0x01, 0x36, 0xa9, 0x2d, 0x01, 0x0b, 0x94, 0x4b, 0x04, 0x2d,
13614 0xdd, 0x09, 0xd1, 0x01, 0xfe, 0x26, 0x0f, 0x12, 0x82, 0x02, 0x2b, 0x2d, 0x32, 0x07, 0xa6, 0xfe,
13615 0xd9, 0x13, 0x3a, 0x3d, 0x3b, 0x3e, 0x56, 0xfe, 0xf0, 0x11, 0x08, 0x05, 0x5a, 0xfe, 0x72, 0x12,
13616 0x9b, 0x2e, 0x9c, 0x3c, 0x90, 0xc0, 0x96, 0xfe, 0xba, 0x11, 0x22, 0x62, 0xfe, 0x26, 0x13, 0x03,
13617 0x7f, 0x29, 0x80, 0x56, 0xfe, 0x76, 0x0d, 0x0c, 0x60, 0x14, 0x61, 0x21, 0x0c, 0x7f, 0x0c, 0x80,
13618 0x01, 0xb3, 0x25, 0x6e, 0x77, 0x13, 0x62, 0x01, 0xef, 0x9b, 0x2e, 0x9c, 0x3c, 0xfe, 0x04, 0x55,
13619 0xfe, 0xa5, 0x55, 0xfe, 0x04, 0xfa, 0x2e, 0xfe, 0x05, 0xfa, 0x3c, 0xfe, 0x91, 0x10, 0x03, 0x3f,
13620 0x29, 0x40, 0xfe, 0x40, 0x56, 0xfe, 0xe1, 0x56, 0x0c, 0x3f, 0x14, 0x40, 0x88, 0x9b, 0x2e, 0x9c,
13621 0x3c, 0x90, 0xc0, 0x03, 0x5e, 0x29, 0x5f, 0xfe, 0x00, 0x56, 0xfe, 0xa1, 0x56, 0x0c, 0x5e, 0x14,
13622 0x5f, 0x08, 0x05, 0x5a, 0xfe, 0x1e, 0x12, 0x22, 0x62, 0xfe, 0x1f, 0x40, 0x03, 0x60, 0x29, 0x61,
13623 0xfe, 0x2c, 0x50, 0xfe, 0xae, 0x50, 0x03, 0x3f, 0x29, 0x40, 0xfe, 0x44, 0x50, 0xfe, 0xc6, 0x50,
13624 0x03, 0x5e, 0x29, 0x5f, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0x03, 0x3d, 0x29, 0x3e, 0xfe, 0x40,
13625 0x50, 0xfe, 0xc2, 0x50, 0x02, 0x89, 0x25, 0x06, 0x13, 0xd4, 0x02, 0x72, 0x2d, 0x01, 0x0b, 0x1d,
13626 0x4c, 0x33, 0x31, 0xde, 0x07, 0x06, 0x23, 0x4c, 0x32, 0x07, 0xa6, 0x23, 0x72, 0x01, 0xaf, 0x1e,
13627 0x43, 0x17, 0x4c, 0x08, 0x05, 0x0a, 0xee, 0x3a, 0x3d, 0x3b, 0x3e, 0xfe, 0x0a, 0x55, 0x35, 0xfe,
13628 0x8b, 0x55, 0x57, 0x3d, 0x7d, 0x3e, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0x02, 0x72, 0xfe, 0x19,
13629 0x81, 0xba, 0xfe, 0x19, 0x41, 0x02, 0x72, 0x2d, 0x01, 0x0b, 0x1c, 0x34, 0x1d, 0xe8, 0x33, 0x31,
13630 0xe1, 0x55, 0x19, 0xfe, 0xa6, 0x12, 0x55, 0x0a, 0x4d, 0x02, 0x4c, 0x01, 0x0b, 0x1c, 0x34, 0x1d,
13631 0xe8, 0x33, 0x31, 0xdf, 0x07, 0x19, 0x23, 0x4c, 0x01, 0x0b, 0x1d, 0xe8, 0x33, 0x31, 0xfe, 0xe8,
13632 0x09, 0xfe, 0xc2, 0x49, 0x51, 0x03, 0xfe, 0x9c, 0x00, 0x28, 0x8a, 0x53, 0x05, 0x1f, 0x35, 0xa9,
13633 0xfe, 0xbb, 0x45, 0x55, 0x00, 0x4e, 0x44, 0x06, 0x7c, 0x43, 0xfe, 0xda, 0x14, 0x01, 0xaf, 0x8c,
13634 0xfe, 0x4b, 0x45, 0xee, 0x32, 0x07, 0xa5, 0xed, 0x03, 0xcd, 0x28, 0x8a, 0x03, 0x45, 0x28, 0x35,
13635 0x67, 0x02, 0x72, 0xfe, 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17, 0x03, 0x5c, 0xc1, 0x0c,
13636 0x5c, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01, 0xfe, 0x9e, 0x15, 0x02, 0x89, 0x01, 0x0b, 0x1c,
13637 0x34, 0x1d, 0x4c, 0x33, 0x31, 0xdf, 0x07, 0x06, 0x23, 0x4c, 0x01, 0xf1, 0xfe, 0x42, 0x58, 0xf1,
13638 0xfe, 0xa4, 0x14, 0x8c, 0xfe, 0x4a, 0xf4, 0x0a, 0x17, 0x4c, 0xfe, 0x4a, 0xf4, 0x06, 0xea, 0x32,
13639 0x07, 0xa5, 0x8b, 0x02, 0x72, 0x03, 0x45, 0xc1, 0x0c, 0x45, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89,
13640 0x01, 0xfe, 0xcc, 0x15, 0x02, 0x89, 0x0f, 0x06, 0x27, 0xfe, 0xbe, 0x13, 0x26, 0xfe, 0xd4, 0x13,
13641 0x76, 0xfe, 0x89, 0x48, 0x01, 0x0b, 0x21, 0x76, 0x04, 0x7b, 0xfe, 0xd0, 0x13, 0x1c, 0xfe, 0xd0,
13642 0x13, 0x1d, 0xfe, 0xbe, 0x13, 0x67, 0x2d, 0x01, 0x0b, 0xfe, 0xd5, 0x10, 0x0f, 0x71, 0xff, 0x02,
13643 0x00, 0x57, 0x52, 0x93, 0x1e, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x04, 0x0f,
13644 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x04,
13645 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52,
13646 0x93, 0xfe, 0x0b, 0x58, 0x04, 0x09, 0x5c, 0x01, 0x87, 0x09, 0x45, 0x01, 0x87, 0x04, 0xfe, 0x03,
13647 0xa1, 0x1e, 0x11, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x1f, 0x52, 0xfe, 0x00, 0x7d, 0xfe,
13648 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x6a, 0x2a, 0x0c, 0x5e, 0x14, 0x5f, 0x57, 0x3f,
13649 0x7d, 0x40, 0x04, 0xdd, 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x8d, 0x04, 0x01,
13650 0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15, 0x33,
13651 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15, 0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59,
13652 0x03, 0xcd, 0x28, 0xfe, 0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee,
13653 0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c, 0x30, 0xfe, 0x78, 0x10,
13654 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83, 0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00,
13655 0x96, 0xf2, 0x18, 0x6d, 0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00,
13656 0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28, 0x10, 0x69, 0x06, 0xfe,
13657 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2, 0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06,
13658 0x88, 0x98, 0xfe, 0x90, 0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe,
13659 0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4, 0x9e, 0xfe, 0xf3, 0x10,
13660 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e, 0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
13661 0x6e, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
13662 0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d, 0xf4, 0x00, 0xe9, 0x91,
13663 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58, 0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01,
13664 0x0b, 0x26, 0xf3, 0x16, 0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76,
13665 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x19, 0x01, 0x0b,
13666 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1, 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76,
13667 0xfe, 0x89, 0x4a, 0x01, 0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
13668 0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01,
13669 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27, 0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00,
13670 0xfe, 0x20, 0x13, 0x1d, 0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
13671 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e, 0x07, 0x11, 0xae, 0x09,
13672 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80,
13673 0xe7, 0x11, 0x07, 0x11, 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
13674 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xfe, 0x80, 0x4c,
13675 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87,
13676 0x04, 0x18, 0x11, 0x75, 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
13677 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4, 0x17, 0xad, 0x9a, 0x1b,
13678 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04, 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10,
13679 0x18, 0x11, 0x75, 0x03, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
13680 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c,
13681 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17,
13682 0xfe, 0xb6, 0x14, 0x35, 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
13683 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x2e, 0x97, 0xfe, 0x5a,
13684 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c, 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
13685 0x04, 0xb9, 0x23, 0xfe, 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
13686 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0xcb, 0x97, 0xfe, 0x92,
13687 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23, 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02,
13688 0xf6, 0x11, 0x75, 0xfe, 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
13689 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0x9a, 0x5b, 0x41, 0xfe,
13690 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd,
13691 0x00, 0x6a, 0x2a, 0x04, 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
13692 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04, 0xfe, 0x7e, 0x18, 0x1e,
13693 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2, 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10,
13694 0x7c, 0x6f, 0x4f, 0x32, 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
13695 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, 0xf0, 0xfe, 0x00, 0xcc,
13696 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11, 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c,
13697 0x01, 0x73, 0xfe, 0x16, 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
13698 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c, 0xe7, 0x0a, 0x10, 0xfe,
13699 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18, 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37,
13700 0x12, 0x2f, 0x01, 0x73, 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
13701 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77, 0x13, 0xa3, 0x04, 0x09,
13702 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46, 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8,
13703 0x18, 0x77, 0x78, 0x04, 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
13704 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe, 0x1c, 0x19, 0x03, 0xfe,
13705 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19,
13706 0x03, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
13707 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe, 0x08, 0x10, 0x03, 0xfe,
13708 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e, 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7,
13709 0x1e, 0x6e, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
13710 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19, 0x04, 0x07, 0x7e, 0xfe,
13711 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a,
13712 0xf0, 0xfe, 0x92, 0x19, 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
13713 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59, 0xa9, 0xb8, 0x04, 0x15,
13714 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe, 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c,
13715 0xf7, 0xfe, 0x14, 0xf0, 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
13716 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
13717};
13718
13719STATIC unsigned short _adv_asc38C0800_size =
13720 sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
13721STATIC ADV_DCNT _adv_asc38C0800_chksum =
13722 0x050D3FD8UL; /* Expanded little-endian checksum. */
13723
13724/* Microcode buffer is kept after initialization for error recovery. */
13725STATIC unsigned char _adv_asc38C1600_buf[] = {
13726 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0, 0x18, 0xe4, 0x01, 0x00,
13727 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13, 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f,
13728 0x00, 0xfa, 0xff, 0xff, 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
13729 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00, 0x98, 0x57, 0x01, 0xe6,
13730 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4, 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0,
13731 0x10, 0x00, 0xc2, 0x0e, 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
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14072 0x50, 0x1b, 0xfe, 0xd4, 0x14, 0x31, 0x02, 0xc9, 0x2b, 0xfe, 0x26, 0x1b, 0xfe, 0xba, 0x10, 0x1c,
14073 0x1a, 0x87, 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x54, 0xb1,
14074 0xfe, 0x72, 0x1b, 0xfe, 0xb2, 0x14, 0xfc, 0xb3, 0x54, 0x7c, 0x12, 0xfe, 0xaf, 0x19, 0xfe, 0x98,
14075 0xe7, 0x00, 0x02, 0xc9, 0x2b, 0xfe, 0x66, 0x1b, 0xfe, 0x8a, 0x10, 0x1c, 0x1a, 0x87, 0x8b, 0x0f,
14076 0xfe, 0x30, 0x90, 0x04, 0xfe, 0xb0, 0x93, 0x3a, 0x0b, 0xfe, 0x18, 0x58, 0xfe, 0x32, 0x90, 0x04,
14077 0xfe, 0xb2, 0x93, 0x3a, 0x0b, 0xfe, 0x19, 0x58, 0x0e, 0xa8, 0xb3, 0x4a, 0x7c, 0x12, 0xfe, 0x0f,
14078 0x79, 0xfe, 0x1c, 0xf7, 0x4a, 0xb1, 0xfe, 0xc6, 0x1b, 0xfe, 0x5e, 0x14, 0x31, 0x02, 0xc9, 0x2b,
14079 0xfe, 0x96, 0x1b, 0x5c, 0xfe, 0x02, 0xf6, 0x1a, 0x87, 0xfe, 0x18, 0xfe, 0x6a, 0xfe, 0x19, 0xfe,
14080 0x6b, 0x01, 0xfe, 0x1e, 0x1f, 0xfe, 0x1d, 0xf7, 0x65, 0xb1, 0xfe, 0xee, 0x1b, 0xfe, 0x36, 0x14,
14081 0xfe, 0x1c, 0x13, 0xb3, 0x65, 0x3e, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x1a,
14082 0xfe, 0x81, 0xe7, 0x1a, 0x15, 0xfe, 0xdd, 0x00, 0x7a, 0x30, 0x02, 0x7a, 0x30, 0xfe, 0x12, 0x45,
14083 0x2b, 0xfe, 0xdc, 0x1b, 0x1f, 0x07, 0x47, 0xb5, 0xc3, 0x05, 0x35, 0xfe, 0x39, 0xf0, 0x75, 0x26,
14084 0x02, 0xfe, 0x7e, 0x18, 0x23, 0x1d, 0x36, 0x13, 0x11, 0x02, 0x87, 0x03, 0xe3, 0x23, 0x07, 0xfe,
14085 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x90, 0x34, 0x60, 0xfe, 0x02, 0x80, 0x09, 0x56, 0xfe, 0x3c, 0x13,
14086 0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x51, 0xfe, 0x06, 0x83, 0x0a, 0x5a, 0x01, 0x18, 0xcb, 0xfe,
14087 0x3e, 0x12, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, 0xfe, 0xb2, 0x16, 0xfe, 0x00, 0xcc, 0xcb,
14088 0xfe, 0xf3, 0x13, 0x3f, 0x89, 0x09, 0x1a, 0xa5, 0x0a, 0x9d, 0x01, 0x18, 0xfe, 0x80, 0x4c, 0x01,
14089 0x85, 0xfe, 0x16, 0x10, 0x09, 0x9b, 0x4e, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14, 0x56,
14090 0xfe, 0xd6, 0xf0, 0xfe, 0x52, 0x1c, 0x1c, 0x0d, 0x02, 0xfe, 0x9c, 0xe7, 0x0d, 0x19, 0xfe, 0x15,
14091 0x00, 0x40, 0x8d, 0x30, 0x01, 0xf4, 0x1c, 0x07, 0x02, 0x51, 0xfe, 0x06, 0x83, 0xfe, 0x18, 0x80,
14092 0x61, 0x28, 0x44, 0x15, 0x56, 0x01, 0x85, 0x1c, 0x07, 0x02, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90,
14093 0x91, 0xde, 0x7e, 0xdf, 0xfe, 0x48, 0x55, 0x31, 0xfe, 0xc9, 0x55, 0x02, 0x21, 0xb9, 0x88, 0x20,
14094 0xb9, 0x02, 0x0a, 0xba, 0x01, 0x18, 0xfe, 0x41, 0x48, 0x0a, 0x57, 0x01, 0x18, 0xfe, 0x49, 0x44,
14095 0x1b, 0xfe, 0x1e, 0x1d, 0x88, 0x89, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x09, 0x1a, 0xa4, 0x0a, 0x67,
14096 0x01, 0xa3, 0x0a, 0x57, 0x01, 0x18, 0x88, 0x89, 0x02, 0xfe, 0x4e, 0xe4, 0x1d, 0x7b, 0xfe, 0x52,
14097 0x1d, 0x03, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xdd, 0x7b,
14098 0xfe, 0x64, 0x1d, 0x03, 0xfe, 0x92, 0x00, 0xd1, 0x12, 0xfe, 0x1a, 0x10, 0xfe, 0x4e, 0xe4, 0xfe,
14099 0x0b, 0x00, 0x7b, 0xfe, 0x76, 0x1d, 0x03, 0xfe, 0x94, 0x00, 0xd1, 0x24, 0xfe, 0x08, 0x10, 0x03,
14100 0xfe, 0x96, 0x00, 0xd1, 0x63, 0xfe, 0x4e, 0x45, 0x83, 0xca, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1,
14101 0x10, 0x23, 0x49, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe,
14102 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa, 0x1d, 0x13, 0x1d, 0x02, 0x09, 0x92, 0xfe, 0x5a,
14103 0xf0, 0xfe, 0xba, 0x1d, 0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8,
14104 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe, 0x1a, 0x10, 0x09, 0x0d,
14105 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e, 0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42,
14106 0xfe, 0x04, 0xfe, 0x99, 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
14107 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e, 0xfe, 0x82, 0xf0, 0xfe,
14108 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18,
14109 0x80, 0x04, 0xfe, 0x98, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
14110 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86, 0x83, 0x33, 0x0b, 0x0e,
14111 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04,
14112 0x80, 0x04, 0xfe, 0x84, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
14113 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04, 0xfe, 0x99, 0x83, 0xfe,
14114 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47,
14115 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
14116 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x08, 0x90, 0x04,
14117 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79,
14118 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
14119 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x3c, 0x90, 0x04,
14120 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b, 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83,
14121 0x33, 0x0b, 0x77, 0x0e, 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
14122};
14123
14124STATIC unsigned short _adv_asc38C1600_size =
14125 sizeof(_adv_asc38C1600_buf); /* 0x1673 */
14126STATIC ADV_DCNT _adv_asc38C1600_chksum =
14127 0x0604EF77UL; /* Expanded little-endian checksum. */
14128
14129/* a_init.c */
14130/*
14131 * EEPROM Configuration.
14132 *
14133 * All drivers should use this structure to set the default EEPROM
14134 * configuration. The BIOS now uses this structure when it is built.
14135 * Additional structure information can be found in a_condor.h where
14136 * the structure is defined.
14137 *
14138 * The *_Field_IsChar structs are needed to correct for endianness.
14139 * These values are read from the board 16 bits at a time directly
14140 * into the structs. Because some fields are char, the values will be
14141 * in the wrong order. The *_Field_IsChar tells when to flip the
14142 * bytes. Data read and written to PCI memory is automatically swapped
14143 * on big-endian platforms so char fields read as words are actually being
14144 * unswapped on big-endian platforms.
14145 */
14146STATIC ADVEEP_3550_CONFIG
14147Default_3550_EEPROM_Config __initdata = {
14148 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
14149 0x0000, /* cfg_msw */
14150 0xFFFF, /* disc_enable */
14151 0xFFFF, /* wdtr_able */
14152 0xFFFF, /* sdtr_able */
14153 0xFFFF, /* start_motor */
14154 0xFFFF, /* tagqng_able */
14155 0xFFFF, /* bios_scan */
14156 0, /* scam_tolerant */
14157 7, /* adapter_scsi_id */
14158 0, /* bios_boot_delay */
14159 3, /* scsi_reset_delay */
14160 0, /* bios_id_lun */
14161 0, /* termination */
14162 0, /* reserved1 */
14163 0xFFE7, /* bios_ctrl */
14164 0xFFFF, /* ultra_able */
14165 0, /* reserved2 */
14166 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
14167 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14168 0, /* dvc_cntl */
14169 0, /* bug_fix */
14170 0, /* serial_number_word1 */
14171 0, /* serial_number_word2 */
14172 0, /* serial_number_word3 */
14173 0, /* check_sum */
14174 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* oem_name[16] */
14175 0, /* dvc_err_code */
14176 0, /* adv_err_code */
14177 0, /* adv_err_addr */
14178 0, /* saved_dvc_err_code */
14179 0, /* saved_adv_err_code */
14180 0, /* saved_adv_err_addr */
14181 0 /* num_of_err */
14182};
14183
14184STATIC ADVEEP_3550_CONFIG
14185ADVEEP_3550_Config_Field_IsChar __initdata = {
14186 0, /* cfg_lsw */
14187 0, /* cfg_msw */
14188 0, /* -disc_enable */
14189 0, /* wdtr_able */
14190 0, /* sdtr_able */
14191 0, /* start_motor */
14192 0, /* tagqng_able */
14193 0, /* bios_scan */
14194 0, /* scam_tolerant */
14195 1, /* adapter_scsi_id */
14196 1, /* bios_boot_delay */
14197 1, /* scsi_reset_delay */
14198 1, /* bios_id_lun */
14199 1, /* termination */
14200 1, /* reserved1 */
14201 0, /* bios_ctrl */
14202 0, /* ultra_able */
14203 0, /* reserved2 */
14204 1, /* max_host_qng */
14205 1, /* max_dvc_qng */
14206 0, /* dvc_cntl */
14207 0, /* bug_fix */
14208 0, /* serial_number_word1 */
14209 0, /* serial_number_word2 */
14210 0, /* serial_number_word3 */
14211 0, /* check_sum */
14212 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* oem_name[16] */
14213 0, /* dvc_err_code */
14214 0, /* adv_err_code */
14215 0, /* adv_err_addr */
14216 0, /* saved_dvc_err_code */
14217 0, /* saved_adv_err_code */
14218 0, /* saved_adv_err_addr */
14219 0 /* num_of_err */
14220};
14221
14222STATIC ADVEEP_38C0800_CONFIG
14223Default_38C0800_EEPROM_Config __initdata = {
14224 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
14225 0x0000, /* 01 cfg_msw */
14226 0xFFFF, /* 02 disc_enable */
14227 0xFFFF, /* 03 wdtr_able */
14228 0x4444, /* 04 sdtr_speed1 */
14229 0xFFFF, /* 05 start_motor */
14230 0xFFFF, /* 06 tagqng_able */
14231 0xFFFF, /* 07 bios_scan */
14232 0, /* 08 scam_tolerant */
14233 7, /* 09 adapter_scsi_id */
14234 0, /* bios_boot_delay */
14235 3, /* 10 scsi_reset_delay */
14236 0, /* bios_id_lun */
14237 0, /* 11 termination_se */
14238 0, /* termination_lvd */
14239 0xFFE7, /* 12 bios_ctrl */
14240 0x4444, /* 13 sdtr_speed2 */
14241 0x4444, /* 14 sdtr_speed3 */
14242 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
14243 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14244 0, /* 16 dvc_cntl */
14245 0x4444, /* 17 sdtr_speed4 */
14246 0, /* 18 serial_number_word1 */
14247 0, /* 19 serial_number_word2 */
14248 0, /* 20 serial_number_word3 */
14249 0, /* 21 check_sum */
14250 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */
14251 0, /* 30 dvc_err_code */
14252 0, /* 31 adv_err_code */
14253 0, /* 32 adv_err_addr */
14254 0, /* 33 saved_dvc_err_code */
14255 0, /* 34 saved_adv_err_code */
14256 0, /* 35 saved_adv_err_addr */
14257 0, /* 36 reserved */
14258 0, /* 37 reserved */
14259 0, /* 38 reserved */
14260 0, /* 39 reserved */
14261 0, /* 40 reserved */
14262 0, /* 41 reserved */
14263 0, /* 42 reserved */
14264 0, /* 43 reserved */
14265 0, /* 44 reserved */
14266 0, /* 45 reserved */
14267 0, /* 46 reserved */
14268 0, /* 47 reserved */
14269 0, /* 48 reserved */
14270 0, /* 49 reserved */
14271 0, /* 50 reserved */
14272 0, /* 51 reserved */
14273 0, /* 52 reserved */
14274 0, /* 53 reserved */
14275 0, /* 54 reserved */
14276 0, /* 55 reserved */
14277 0, /* 56 cisptr_lsw */
14278 0, /* 57 cisprt_msw */
14279 ADV_PCI_VENDOR_ID, /* 58 subsysvid */
14280 ADV_PCI_DEVID_38C0800_REV1, /* 59 subsysid */
14281 0, /* 60 reserved */
14282 0, /* 61 reserved */
14283 0, /* 62 reserved */
14284 0 /* 63 reserved */
14285};
14286
14287STATIC ADVEEP_38C0800_CONFIG
14288ADVEEP_38C0800_Config_Field_IsChar __initdata = {
14289 0, /* 00 cfg_lsw */
14290 0, /* 01 cfg_msw */
14291 0, /* 02 disc_enable */
14292 0, /* 03 wdtr_able */
14293 0, /* 04 sdtr_speed1 */
14294 0, /* 05 start_motor */
14295 0, /* 06 tagqng_able */
14296 0, /* 07 bios_scan */
14297 0, /* 08 scam_tolerant */
14298 1, /* 09 adapter_scsi_id */
14299 1, /* bios_boot_delay */
14300 1, /* 10 scsi_reset_delay */
14301 1, /* bios_id_lun */
14302 1, /* 11 termination_se */
14303 1, /* termination_lvd */
14304 0, /* 12 bios_ctrl */
14305 0, /* 13 sdtr_speed2 */
14306 0, /* 14 sdtr_speed3 */
14307 1, /* 15 max_host_qng */
14308 1, /* max_dvc_qng */
14309 0, /* 16 dvc_cntl */
14310 0, /* 17 sdtr_speed4 */
14311 0, /* 18 serial_number_word1 */
14312 0, /* 19 serial_number_word2 */
14313 0, /* 20 serial_number_word3 */
14314 0, /* 21 check_sum */
14315 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* 22-29 oem_name[16] */
14316 0, /* 30 dvc_err_code */
14317 0, /* 31 adv_err_code */
14318 0, /* 32 adv_err_addr */
14319 0, /* 33 saved_dvc_err_code */
14320 0, /* 34 saved_adv_err_code */
14321 0, /* 35 saved_adv_err_addr */
14322 0, /* 36 reserved */
14323 0, /* 37 reserved */
14324 0, /* 38 reserved */
14325 0, /* 39 reserved */
14326 0, /* 40 reserved */
14327 0, /* 41 reserved */
14328 0, /* 42 reserved */
14329 0, /* 43 reserved */
14330 0, /* 44 reserved */
14331 0, /* 45 reserved */
14332 0, /* 46 reserved */
14333 0, /* 47 reserved */
14334 0, /* 48 reserved */
14335 0, /* 49 reserved */
14336 0, /* 50 reserved */
14337 0, /* 51 reserved */
14338 0, /* 52 reserved */
14339 0, /* 53 reserved */
14340 0, /* 54 reserved */
14341 0, /* 55 reserved */
14342 0, /* 56 cisptr_lsw */
14343 0, /* 57 cisprt_msw */
14344 0, /* 58 subsysvid */
14345 0, /* 59 subsysid */
14346 0, /* 60 reserved */
14347 0, /* 61 reserved */
14348 0, /* 62 reserved */
14349 0 /* 63 reserved */
14350};
14351
14352STATIC ADVEEP_38C1600_CONFIG
14353Default_38C1600_EEPROM_Config __initdata = {
14354 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
14355 0x0000, /* 01 cfg_msw */
14356 0xFFFF, /* 02 disc_enable */
14357 0xFFFF, /* 03 wdtr_able */
14358 0x5555, /* 04 sdtr_speed1 */
14359 0xFFFF, /* 05 start_motor */
14360 0xFFFF, /* 06 tagqng_able */
14361 0xFFFF, /* 07 bios_scan */
14362 0, /* 08 scam_tolerant */
14363 7, /* 09 adapter_scsi_id */
14364 0, /* bios_boot_delay */
14365 3, /* 10 scsi_reset_delay */
14366 0, /* bios_id_lun */
14367 0, /* 11 termination_se */
14368 0, /* termination_lvd */
14369 0xFFE7, /* 12 bios_ctrl */
14370 0x5555, /* 13 sdtr_speed2 */
14371 0x5555, /* 14 sdtr_speed3 */
14372 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
14373 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14374 0, /* 16 dvc_cntl */
14375 0x5555, /* 17 sdtr_speed4 */
14376 0, /* 18 serial_number_word1 */
14377 0, /* 19 serial_number_word2 */
14378 0, /* 20 serial_number_word3 */
14379 0, /* 21 check_sum */
14380 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */
14381 0, /* 30 dvc_err_code */
14382 0, /* 31 adv_err_code */
14383 0, /* 32 adv_err_addr */
14384 0, /* 33 saved_dvc_err_code */
14385 0, /* 34 saved_adv_err_code */
14386 0, /* 35 saved_adv_err_addr */
14387 0, /* 36 reserved */
14388 0, /* 37 reserved */
14389 0, /* 38 reserved */
14390 0, /* 39 reserved */
14391 0, /* 40 reserved */
14392 0, /* 41 reserved */
14393 0, /* 42 reserved */
14394 0, /* 43 reserved */
14395 0, /* 44 reserved */
14396 0, /* 45 reserved */
14397 0, /* 46 reserved */
14398 0, /* 47 reserved */
14399 0, /* 48 reserved */
14400 0, /* 49 reserved */
14401 0, /* 50 reserved */
14402 0, /* 51 reserved */
14403 0, /* 52 reserved */
14404 0, /* 53 reserved */
14405 0, /* 54 reserved */
14406 0, /* 55 reserved */
14407 0, /* 56 cisptr_lsw */
14408 0, /* 57 cisprt_msw */
14409 ADV_PCI_VENDOR_ID, /* 58 subsysvid */
14410 ADV_PCI_DEVID_38C1600_REV1, /* 59 subsysid */
14411 0, /* 60 reserved */
14412 0, /* 61 reserved */
14413 0, /* 62 reserved */
14414 0 /* 63 reserved */
14415};
14416
14417STATIC ADVEEP_38C1600_CONFIG
14418ADVEEP_38C1600_Config_Field_IsChar __initdata = {
14419 0, /* 00 cfg_lsw */
14420 0, /* 01 cfg_msw */
14421 0, /* 02 disc_enable */
14422 0, /* 03 wdtr_able */
14423 0, /* 04 sdtr_speed1 */
14424 0, /* 05 start_motor */
14425 0, /* 06 tagqng_able */
14426 0, /* 07 bios_scan */
14427 0, /* 08 scam_tolerant */
14428 1, /* 09 adapter_scsi_id */
14429 1, /* bios_boot_delay */
14430 1, /* 10 scsi_reset_delay */
14431 1, /* bios_id_lun */
14432 1, /* 11 termination_se */
14433 1, /* termination_lvd */
14434 0, /* 12 bios_ctrl */
14435 0, /* 13 sdtr_speed2 */
14436 0, /* 14 sdtr_speed3 */
14437 1, /* 15 max_host_qng */
14438 1, /* max_dvc_qng */
14439 0, /* 16 dvc_cntl */
14440 0, /* 17 sdtr_speed4 */
14441 0, /* 18 serial_number_word1 */
14442 0, /* 19 serial_number_word2 */
14443 0, /* 20 serial_number_word3 */
14444 0, /* 21 check_sum */
14445 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* 22-29 oem_name[16] */
14446 0, /* 30 dvc_err_code */
14447 0, /* 31 adv_err_code */
14448 0, /* 32 adv_err_addr */
14449 0, /* 33 saved_dvc_err_code */
14450 0, /* 34 saved_adv_err_code */
14451 0, /* 35 saved_adv_err_addr */
14452 0, /* 36 reserved */
14453 0, /* 37 reserved */
14454 0, /* 38 reserved */
14455 0, /* 39 reserved */
14456 0, /* 40 reserved */
14457 0, /* 41 reserved */
14458 0, /* 42 reserved */
14459 0, /* 43 reserved */
14460 0, /* 44 reserved */
14461 0, /* 45 reserved */
14462 0, /* 46 reserved */
14463 0, /* 47 reserved */
14464 0, /* 48 reserved */
14465 0, /* 49 reserved */
14466 0, /* 50 reserved */
14467 0, /* 51 reserved */
14468 0, /* 52 reserved */
14469 0, /* 53 reserved */
14470 0, /* 54 reserved */
14471 0, /* 55 reserved */
14472 0, /* 56 cisptr_lsw */
14473 0, /* 57 cisprt_msw */
14474 0, /* 58 subsysvid */
14475 0, /* 59 subsysid */
14476 0, /* 60 reserved */
14477 0, /* 61 reserved */
14478 0, /* 62 reserved */
14479 0 /* 63 reserved */
14480};
14481
14482/*
14483 * Initialize the ADV_DVC_VAR structure.
14484 *
14485 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
14486 *
14487 * For a non-fatal error return a warning code. If there are no warnings
14488 * then 0 is returned.
14489 */
14490STATIC int __init
14491AdvInitGetConfig(ADV_DVC_VAR *asc_dvc)
14492{
14493 ushort warn_code;
14494 AdvPortAddr iop_base;
14495 uchar pci_cmd_reg;
14496 int status;
14497
14498 warn_code = 0;
14499 asc_dvc->err_code = 0;
14500 iop_base = asc_dvc->iop_base;
14501
14502 /*
14503 * PCI Command Register
14504 *
14505 * Note: AscPCICmdRegBits_BusMastering definition (0x0007) includes
14506 * I/O Space Control, Memory Space Control and Bus Master Control bits.
14507 */
14508
14509 if (((pci_cmd_reg = DvcAdvReadPCIConfigByte(asc_dvc,
14510 AscPCIConfigCommandRegister))
14511 & AscPCICmdRegBits_BusMastering)
14512 != AscPCICmdRegBits_BusMastering)
14513 {
14514 pci_cmd_reg |= AscPCICmdRegBits_BusMastering;
14515
14516 DvcAdvWritePCIConfigByte(asc_dvc,
14517 AscPCIConfigCommandRegister, pci_cmd_reg);
14518
14519 if (((DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigCommandRegister))
14520 & AscPCICmdRegBits_BusMastering)
14521 != AscPCICmdRegBits_BusMastering)
14522 {
14523 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
14524 }
14525 }
14526
14527 /*
14528 * PCI Latency Timer
14529 *
14530 * If the "latency timer" register is 0x20 or above, then we don't need
14531 * to change it. Otherwise, set it to 0x20 (i.e. set it to 0x20 if it
14532 * comes up less than 0x20).
14533 */
14534 if (DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer) < 0x20) {
14535 DvcAdvWritePCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer, 0x20);
14536 if (DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer) < 0x20)
14537 {
14538 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
14539 }
14540 }
14541
14542 /*
14543 * Save the state of the PCI Configuration Command Register
14544 * "Parity Error Response Control" Bit. If the bit is clear (0),
14545 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
14546 * DMA parity errors.
14547 */
14548 asc_dvc->cfg->control_flag = 0;
14549 if (((DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigCommandRegister)
14550 & AscPCICmdRegBits_ParErrRespCtrl)) == 0)
14551 {
14552 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
14553 }
14554
14555 asc_dvc->cfg->lib_version = (ADV_LIB_VERSION_MAJOR << 8) |
14556 ADV_LIB_VERSION_MINOR;
14557 asc_dvc->cfg->chip_version =
14558 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
14559
14560 ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: 0x%x 0x%x\n",
14561 (ushort) AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
14562 (ushort) ADV_CHIP_ID_BYTE);
14563
14564 ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: 0x%x 0x%x\n",
14565 (ushort) AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
14566 (ushort) ADV_CHIP_ID_WORD);
14567
14568 /*
14569 * Reset the chip to start and allow register writes.
14570 */
14571 if (AdvFindSignature(iop_base) == 0)
14572 {
14573 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
14574 return ADV_ERROR;
14575 }
14576 else {
14577 /*
14578 * The caller must set 'chip_type' to a valid setting.
14579 */
14580 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
14581 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
14582 asc_dvc->chip_type != ADV_CHIP_ASC38C1600)
14583 {
14584 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
14585 return ADV_ERROR;
14586 }
14587
14588 /*
14589 * Reset Chip.
14590 */
14591 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
14592 ADV_CTRL_REG_CMD_RESET);
14593 DvcSleepMilliSecond(100);
14594 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
14595 ADV_CTRL_REG_CMD_WR_IO_REG);
14596
14597 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
14598 {
14599 if ((status = AdvInitFrom38C1600EEP(asc_dvc)) == ADV_ERROR)
14600 {
14601 return ADV_ERROR;
14602 }
14603 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
14604 {
14605 if ((status = AdvInitFrom38C0800EEP(asc_dvc)) == ADV_ERROR)
14606 {
14607 return ADV_ERROR;
14608 }
14609 } else
14610 {
14611 if ((status = AdvInitFrom3550EEP(asc_dvc)) == ADV_ERROR)
14612 {
14613 return ADV_ERROR;
14614 }
14615 }
14616 warn_code |= status;
14617 }
14618
14619 return warn_code;
14620}
14621
14622/*
14623 * Initialize the ASC-3550.
14624 *
14625 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
14626 *
14627 * For a non-fatal error return a warning code. If there are no warnings
14628 * then 0 is returned.
14629 *
14630 * Needed after initialization for error recovery.
14631 */
14632STATIC int
14633AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
14634{
14635 AdvPortAddr iop_base;
14636 ushort warn_code;
14637 ADV_DCNT sum;
14638 int begin_addr;
14639 int end_addr;
14640 ushort code_sum;
14641 int word;
14642 int j;
14643 int adv_asc3550_expanded_size;
14644 ADV_CARR_T *carrp;
14645 ADV_DCNT contig_len;
14646 ADV_SDCNT buf_size;
14647 ADV_PADDR carr_paddr;
14648 int i;
14649 ushort scsi_cfg1;
14650 uchar tid;
14651 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
14652 ushort wdtr_able = 0, sdtr_able, tagqng_able;
14653 uchar max_cmd[ADV_MAX_TID + 1];
14654
14655 /* If there is already an error, don't continue. */
14656 if (asc_dvc->err_code != 0)
14657 {
14658 return ADV_ERROR;
14659 }
14660
14661 /*
14662 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
14663 */
14664 if (asc_dvc->chip_type != ADV_CHIP_ASC3550)
14665 {
14666 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
14667 return ADV_ERROR;
14668 }
14669
14670 warn_code = 0;
14671 iop_base = asc_dvc->iop_base;
14672
14673 /*
14674 * Save the RISC memory BIOS region before writing the microcode.
14675 * The BIOS may already be loaded and using its RISC LRAM region
14676 * so its region must be saved and restored.
14677 *
14678 * Note: This code makes the assumption, which is currently true,
14679 * that a chip reset does not clear RISC LRAM.
14680 */
14681 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
14682 {
14683 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
14684 }
14685
14686 /*
14687 * Save current per TID negotiated values.
14688 */
14689 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
14690 {
14691 ushort bios_version, major, minor;
14692
14693 bios_version = bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM)/2];
14694 major = (bios_version >> 12) & 0xF;
14695 minor = (bios_version >> 8) & 0xF;
14696 if (major < 3 || (major == 3 && minor == 1))
14697 {
14698 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
14699 AdvReadWordLram(iop_base, 0x120, wdtr_able);
14700 } else
14701 {
14702 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
14703 }
14704 }
14705 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
14706 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
14707 for (tid = 0; tid <= ADV_MAX_TID; tid++)
14708 {
14709 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
14710 max_cmd[tid]);
14711 }
14712
14713 /*
14714 * Load the Microcode
14715 *
14716 * Write the microcode image to RISC memory starting at address 0.
14717 */
14718 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
14719 /* Assume the following compressed format of the microcode buffer:
14720 *
14721 * 254 word (508 byte) table indexed by byte code followed
14722 * by the following byte codes:
14723 *
14724 * 1-Byte Code:
14725 * 00: Emit word 0 in table.
14726 * 01: Emit word 1 in table.
14727 * .
14728 * FD: Emit word 253 in table.
14729 *
14730 * Multi-Byte Code:
14731 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
14732 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
14733 */
14734 word = 0;
14735 for (i = 253 * 2; i < _adv_asc3550_size; i++)
14736 {
14737 if (_adv_asc3550_buf[i] == 0xff)
14738 {
14739 for (j = 0; j < _adv_asc3550_buf[i + 1]; j++)
14740 {
14741 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14742 _adv_asc3550_buf[i + 3] << 8) |
14743 _adv_asc3550_buf[i + 2]));
14744 word++;
14745 }
14746 i += 3;
14747 } else if (_adv_asc3550_buf[i] == 0xfe)
14748 {
14749 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14750 _adv_asc3550_buf[i + 2] << 8) |
14751 _adv_asc3550_buf[i + 1]));
14752 i += 2;
14753 word++;
14754 } else
14755 {
14756 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14757 _adv_asc3550_buf[(_adv_asc3550_buf[i] * 2) + 1] << 8) |
14758 _adv_asc3550_buf[_adv_asc3550_buf[i] * 2]));
14759 word++;
14760 }
14761 }
14762
14763 /*
14764 * Set 'word' for later use to clear the rest of memory and save
14765 * the expanded mcode size.
14766 */
14767 word *= 2;
14768 adv_asc3550_expanded_size = word;
14769
14770 /*
14771 * Clear the rest of ASC-3550 Internal RAM (8KB).
14772 */
14773 for (; word < ADV_3550_MEMSIZE; word += 2)
14774 {
14775 AdvWriteWordAutoIncLram(iop_base, 0);
14776 }
14777
14778 /*
14779 * Verify the microcode checksum.
14780 */
14781 sum = 0;
14782 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
14783
14784 for (word = 0; word < adv_asc3550_expanded_size; word += 2)
14785 {
14786 sum += AdvReadWordAutoIncLram(iop_base);
14787 }
14788
14789 if (sum != _adv_asc3550_chksum)
14790 {
14791 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
14792 return ADV_ERROR;
14793 }
14794
14795 /*
14796 * Restore the RISC memory BIOS region.
14797 */
14798 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
14799 {
14800 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
14801 }
14802
14803 /*
14804 * Calculate and write the microcode code checksum to the microcode
14805 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
14806 */
14807 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
14808 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
14809 code_sum = 0;
14810 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
14811 for (word = begin_addr; word < end_addr; word += 2)
14812 {
14813 code_sum += AdvReadWordAutoIncLram(iop_base);
14814 }
14815 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
14816
14817 /*
14818 * Read and save microcode version and date.
14819 */
14820 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
14821 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
14822
14823 /*
14824 * Set the chip type to indicate the ASC3550.
14825 */
14826 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
14827
14828 /*
14829 * If the PCI Configuration Command Register "Parity Error Response
14830 * Control" Bit was clear (0), then set the microcode variable
14831 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
14832 * to ignore DMA parity errors.
14833 */
14834 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
14835 {
14836 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
14837 word |= CONTROL_FLAG_IGNORE_PERR;
14838 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
14839 }
14840
14841 /*
14842 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
14843 * threshold of 128 bytes. This register is only accessible to the host.
14844 */
14845 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
14846 START_CTL_EMFU | READ_CMD_MRM);
14847
14848 /*
14849 * Microcode operating variables for WDTR, SDTR, and command tag
14850 * queuing will be set in AdvInquiryHandling() based on what a
14851 * device reports it is capable of in Inquiry byte 7.
14852 *
14853 * If SCSI Bus Resets have been disabled, then directly set
14854 * SDTR and WDTR from the EEPROM configuration. This will allow
14855 * the BIOS and warm boot to work without a SCSI bus hang on
14856 * the Inquiry caused by host and target mismatched DTR values.
14857 * Without the SCSI Bus Reset, before an Inquiry a device can't
14858 * be assumed to be in Asynchronous, Narrow mode.
14859 */
14860 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
14861 {
14862 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
14863 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
14864 }
14865
14866 /*
14867 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
14868 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
14869 * bitmask. These values determine the maximum SDTR speed negotiated
14870 * with a device.
14871 *
14872 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
14873 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
14874 * without determining here whether the device supports SDTR.
14875 *
14876 * 4-bit speed SDTR speed name
14877 * =========== ===============
14878 * 0000b (0x0) SDTR disabled
14879 * 0001b (0x1) 5 Mhz
14880 * 0010b (0x2) 10 Mhz
14881 * 0011b (0x3) 20 Mhz (Ultra)
14882 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
14883 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
14884 * 0110b (0x6) Undefined
14885 * .
14886 * 1111b (0xF) Undefined
14887 */
14888 word = 0;
14889 for (tid = 0; tid <= ADV_MAX_TID; tid++)
14890 {
14891 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able)
14892 {
14893 /* Set Ultra speed for TID 'tid'. */
14894 word |= (0x3 << (4 * (tid % 4)));
14895 } else
14896 {
14897 /* Set Fast speed for TID 'tid'. */
14898 word |= (0x2 << (4 * (tid % 4)));
14899 }
14900 if (tid == 3) /* Check if done with sdtr_speed1. */
14901 {
14902 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
14903 word = 0;
14904 } else if (tid == 7) /* Check if done with sdtr_speed2. */
14905 {
14906 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
14907 word = 0;
14908 } else if (tid == 11) /* Check if done with sdtr_speed3. */
14909 {
14910 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
14911 word = 0;
14912 } else if (tid == 15) /* Check if done with sdtr_speed4. */
14913 {
14914 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
14915 /* End of loop. */
14916 }
14917 }
14918
14919 /*
14920 * Set microcode operating variable for the disconnect per TID bitmask.
14921 */
14922 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
14923
14924 /*
14925 * Set SCSI_CFG0 Microcode Default Value.
14926 *
14927 * The microcode will set the SCSI_CFG0 register using this value
14928 * after it is started below.
14929 */
14930 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
14931 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
14932 asc_dvc->chip_scsi_id);
14933
14934 /*
14935 * Determine SCSI_CFG1 Microcode Default Value.
14936 *
14937 * The microcode will set the SCSI_CFG1 register using this value
14938 * after it is started below.
14939 */
14940
14941 /* Read current SCSI_CFG1 Register value. */
14942 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
14943
14944 /*
14945 * If all three connectors are in use, return an error.
14946 */
14947 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
14948 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0)
14949 {
14950 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
14951 return ADV_ERROR;
14952 }
14953
14954 /*
14955 * If the internal narrow cable is reversed all of the SCSI_CTRL
14956 * register signals will be set. Check for and return an error if
14957 * this condition is found.
14958 */
14959 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
14960 {
14961 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
14962 return ADV_ERROR;
14963 }
14964
14965 /*
14966 * If this is a differential board and a single-ended device
14967 * is attached to one of the connectors, return an error.
14968 */
14969 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0)
14970 {
14971 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
14972 return ADV_ERROR;
14973 }
14974
14975 /*
14976 * If automatic termination control is enabled, then set the
14977 * termination value based on a table listed in a_condor.h.
14978 *
14979 * If manual termination was specified with an EEPROM setting
14980 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
14981 * is ready to be 'ored' into SCSI_CFG1.
14982 */
14983 if (asc_dvc->cfg->termination == 0)
14984 {
14985 /*
14986 * The software always controls termination by setting TERM_CTL_SEL.
14987 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
14988 */
14989 asc_dvc->cfg->termination |= TERM_CTL_SEL;
14990
14991 switch(scsi_cfg1 & CABLE_DETECT)
14992 {
14993 /* TERM_CTL_H: on, TERM_CTL_L: on */
14994 case 0x3: case 0x7: case 0xB: case 0xD: case 0xE: case 0xF:
14995 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
14996 break;
14997
14998 /* TERM_CTL_H: on, TERM_CTL_L: off */
14999 case 0x1: case 0x5: case 0x9: case 0xA: case 0xC:
15000 asc_dvc->cfg->termination |= TERM_CTL_H;
15001 break;
15002
15003 /* TERM_CTL_H: off, TERM_CTL_L: off */
15004 case 0x2: case 0x6:
15005 break;
15006 }
15007 }
15008
15009 /*
15010 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
15011 */
15012 scsi_cfg1 &= ~TERM_CTL;
15013
15014 /*
15015 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
15016 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
15017 * referenced, because the hardware internally inverts
15018 * the Termination High and Low bits if TERM_POL is set.
15019 */
15020 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
15021
15022 /*
15023 * Set SCSI_CFG1 Microcode Default Value
15024 *
15025 * Set filter value and possibly modified termination control
15026 * bits in the Microcode SCSI_CFG1 Register Value.
15027 *
15028 * The microcode will set the SCSI_CFG1 register using this value
15029 * after it is started below.
15030 */
15031 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
15032 FLTR_DISABLE | scsi_cfg1);
15033
15034 /*
15035 * Set MEM_CFG Microcode Default Value
15036 *
15037 * The microcode will set the MEM_CFG register using this value
15038 * after it is started below.
15039 *
15040 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
15041 * are defined.
15042 *
15043 * ASC-3550 has 8KB internal memory.
15044 */
15045 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
15046 BIOS_EN | RAM_SZ_8KB);
15047
15048 /*
15049 * Set SEL_MASK Microcode Default Value
15050 *
15051 * The microcode will set the SEL_MASK register using this value
15052 * after it is started below.
15053 */
15054 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
15055 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
15056
15057 /*
15058 * Build carrier freelist.
15059 *
15060 * Driver must have already allocated memory and set 'carrier_buf'.
15061 */
15062 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
15063
15064 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
15065 asc_dvc->carr_freelist = NULL;
15066 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
15067 {
15068 buf_size = ADV_CARRIER_BUFSIZE;
15069 } else
15070 {
15071 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
15072 }
15073
15074 do {
15075 /*
15076 * Get physical address of the carrier 'carrp'.
15077 */
15078 contig_len = sizeof(ADV_CARR_T);
15079 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
15080 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
15081
15082 buf_size -= sizeof(ADV_CARR_T);
15083
15084 /*
15085 * If the current carrier is not physically contiguous, then
15086 * maybe there was a page crossing. Try the next carrier aligned
15087 * start address.
15088 */
15089 if (contig_len < sizeof(ADV_CARR_T))
15090 {
15091 carrp++;
15092 continue;
15093 }
15094
15095 carrp->carr_pa = carr_paddr;
15096 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
15097
15098 /*
15099 * Insert the carrier at the beginning of the freelist.
15100 */
15101 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
15102 asc_dvc->carr_freelist = carrp;
15103
15104 carrp++;
15105 }
15106 while (buf_size > 0);
15107
15108 /*
15109 * Set-up the Host->RISC Initiator Command Queue (ICQ).
15110 */
15111
15112 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
15113 {
15114 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15115 return ADV_ERROR;
15116 }
15117 asc_dvc->carr_freelist = (ADV_CARR_T *)
15118 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
15119
15120 /*
15121 * The first command issued will be placed in the stopper carrier.
15122 */
15123 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15124
15125 /*
15126 * Set RISC ICQ physical address start value.
15127 */
15128 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
15129
15130 /*
15131 * Set-up the RISC->Host Initiator Response Queue (IRQ).
15132 */
15133 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
15134 {
15135 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15136 return ADV_ERROR;
15137 }
15138 asc_dvc->carr_freelist = (ADV_CARR_T *)
15139 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
15140
15141 /*
15142 * The first command completed by the RISC will be placed in
15143 * the stopper.
15144 *
15145 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
15146 * completed the RISC will set the ASC_RQ_STOPPER bit.
15147 */
15148 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15149
15150 /*
15151 * Set RISC IRQ physical address start value.
15152 */
15153 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
15154 asc_dvc->carr_pending_cnt = 0;
15155
15156 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
15157 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
15158
15159 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
15160 AdvWriteWordRegister(iop_base, IOPW_PC, word);
15161
15162 /* finally, finally, gentlemen, start your engine */
15163 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
15164
15165 /*
15166 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
15167 * Resets should be performed. The RISC has to be running
15168 * to issue a SCSI Bus Reset.
15169 */
15170 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
15171 {
15172 /*
15173 * If the BIOS Signature is present in memory, restore the
15174 * BIOS Handshake Configuration Table and do not perform
15175 * a SCSI Bus Reset.
15176 */
15177 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
15178 {
15179 /*
15180 * Restore per TID negotiated values.
15181 */
15182 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15183 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15184 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15185 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15186 {
15187 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15188 max_cmd[tid]);
15189 }
15190 } else
15191 {
15192 if (AdvResetSB(asc_dvc) != ADV_TRUE)
15193 {
15194 warn_code = ASC_WARN_BUSRESET_ERROR;
15195 }
15196 }
15197 }
15198
15199 return warn_code;
15200}
15201
15202/*
15203 * Initialize the ASC-38C0800.
15204 *
15205 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
15206 *
15207 * For a non-fatal error return a warning code. If there are no warnings
15208 * then 0 is returned.
15209 *
15210 * Needed after initialization for error recovery.
15211 */
15212STATIC int
15213AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
15214{
15215 AdvPortAddr iop_base;
15216 ushort warn_code;
15217 ADV_DCNT sum;
15218 int begin_addr;
15219 int end_addr;
15220 ushort code_sum;
15221 int word;
15222 int j;
15223 int adv_asc38C0800_expanded_size;
15224 ADV_CARR_T *carrp;
15225 ADV_DCNT contig_len;
15226 ADV_SDCNT buf_size;
15227 ADV_PADDR carr_paddr;
15228 int i;
15229 ushort scsi_cfg1;
15230 uchar byte;
15231 uchar tid;
15232 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
15233 ushort wdtr_able, sdtr_able, tagqng_able;
15234 uchar max_cmd[ADV_MAX_TID + 1];
15235
15236 /* If there is already an error, don't continue. */
15237 if (asc_dvc->err_code != 0)
15238 {
15239 return ADV_ERROR;
15240 }
15241
15242 /*
15243 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
15244 */
15245 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800)
15246 {
15247 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
15248 return ADV_ERROR;
15249 }
15250
15251 warn_code = 0;
15252 iop_base = asc_dvc->iop_base;
15253
15254 /*
15255 * Save the RISC memory BIOS region before writing the microcode.
15256 * The BIOS may already be loaded and using its RISC LRAM region
15257 * so its region must be saved and restored.
15258 *
15259 * Note: This code makes the assumption, which is currently true,
15260 * that a chip reset does not clear RISC LRAM.
15261 */
15262 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15263 {
15264 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15265 }
15266
15267 /*
15268 * Save current per TID negotiated values.
15269 */
15270 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15271 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15272 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15273 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15274 {
15275 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15276 max_cmd[tid]);
15277 }
15278
15279 /*
15280 * RAM BIST (RAM Built-In Self Test)
15281 *
15282 * Address : I/O base + offset 0x38h register (byte).
15283 * Function: Bit 7-6(RW) : RAM mode
15284 * Normal Mode : 0x00
15285 * Pre-test Mode : 0x40
15286 * RAM Test Mode : 0x80
15287 * Bit 5 : unused
15288 * Bit 4(RO) : Done bit
15289 * Bit 3-0(RO) : Status
15290 * Host Error : 0x08
15291 * Int_RAM Error : 0x04
15292 * RISC Error : 0x02
15293 * SCSI Error : 0x01
15294 * No Error : 0x00
15295 *
15296 * Note: RAM BIST code should be put right here, before loading the
15297 * microcode and after saving the RISC memory BIOS region.
15298 */
15299
15300 /*
15301 * LRAM Pre-test
15302 *
15303 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
15304 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
15305 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
15306 * to NORMAL_MODE, return an error too.
15307 */
15308 for (i = 0; i < 2; i++)
15309 {
15310 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
15311 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15312 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15313 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != PRE_TEST_VALUE)
15314 {
15315 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15316 return ADV_ERROR;
15317 }
15318
15319 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15320 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15321 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
15322 != NORMAL_VALUE)
15323 {
15324 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15325 return ADV_ERROR;
15326 }
15327 }
15328
15329 /*
15330 * LRAM Test - It takes about 1.5 ms to run through the test.
15331 *
15332 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
15333 * If Done bit not set or Status not 0, save register byte, set the
15334 * err_code, and return an error.
15335 */
15336 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
15337 DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
15338
15339 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15340 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0)
15341 {
15342 /* Get here if Done bit not set or Status not 0. */
15343 asc_dvc->bist_err_code = byte; /* for BIOS display message */
15344 asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
15345 return ADV_ERROR;
15346 }
15347
15348 /* We need to reset back to normal mode after LRAM test passes. */
15349 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15350
15351 /*
15352 * Load the Microcode
15353 *
15354 * Write the microcode image to RISC memory starting at address 0.
15355 *
15356 */
15357 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15358
15359 /* Assume the following compressed format of the microcode buffer:
15360 *
15361 * 254 word (508 byte) table indexed by byte code followed
15362 * by the following byte codes:
15363 *
15364 * 1-Byte Code:
15365 * 00: Emit word 0 in table.
15366 * 01: Emit word 1 in table.
15367 * .
15368 * FD: Emit word 253 in table.
15369 *
15370 * Multi-Byte Code:
15371 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
15372 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
15373 */
15374 word = 0;
15375 for (i = 253 * 2; i < _adv_asc38C0800_size; i++)
15376 {
15377 if (_adv_asc38C0800_buf[i] == 0xff)
15378 {
15379 for (j = 0; j < _adv_asc38C0800_buf[i + 1]; j++)
15380 {
15381 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15382 _adv_asc38C0800_buf[i + 3] << 8) |
15383 _adv_asc38C0800_buf[i + 2]));
15384 word++;
15385 }
15386 i += 3;
15387 } else if (_adv_asc38C0800_buf[i] == 0xfe)
15388 {
15389 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15390 _adv_asc38C0800_buf[i + 2] << 8) |
15391 _adv_asc38C0800_buf[i + 1]));
15392 i += 2;
15393 word++;
15394 } else
15395 {
15396 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15397 _adv_asc38C0800_buf[(_adv_asc38C0800_buf[i] * 2) + 1] << 8) |
15398 _adv_asc38C0800_buf[_adv_asc38C0800_buf[i] * 2]));
15399 word++;
15400 }
15401 }
15402
15403 /*
15404 * Set 'word' for later use to clear the rest of memory and save
15405 * the expanded mcode size.
15406 */
15407 word *= 2;
15408 adv_asc38C0800_expanded_size = word;
15409
15410 /*
15411 * Clear the rest of ASC-38C0800 Internal RAM (16KB).
15412 */
15413 for (; word < ADV_38C0800_MEMSIZE; word += 2)
15414 {
15415 AdvWriteWordAutoIncLram(iop_base, 0);
15416 }
15417
15418 /*
15419 * Verify the microcode checksum.
15420 */
15421 sum = 0;
15422 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15423
15424 for (word = 0; word < adv_asc38C0800_expanded_size; word += 2)
15425 {
15426 sum += AdvReadWordAutoIncLram(iop_base);
15427 }
15428 ASC_DBG2(1, "AdvInitAsc38C0800Driver: word %d, i %d\n", word, i);
15429
15430 ASC_DBG2(1,
15431 "AdvInitAsc38C0800Driver: sum 0x%lx, _adv_asc38C0800_chksum 0x%lx\n",
15432 (ulong) sum, (ulong) _adv_asc38C0800_chksum);
15433
15434 if (sum != _adv_asc38C0800_chksum)
15435 {
15436 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
15437 return ADV_ERROR;
15438 }
15439
15440 /*
15441 * Restore the RISC memory BIOS region.
15442 */
15443 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15444 {
15445 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15446 }
15447
15448 /*
15449 * Calculate and write the microcode code checksum to the microcode
15450 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
15451 */
15452 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
15453 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
15454 code_sum = 0;
15455 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
15456 for (word = begin_addr; word < end_addr; word += 2)
15457 {
15458 code_sum += AdvReadWordAutoIncLram(iop_base);
15459 }
15460 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
15461
15462 /*
15463 * Read microcode version and date.
15464 */
15465 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
15466 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
15467
15468 /*
15469 * Set the chip type to indicate the ASC38C0800.
15470 */
15471 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
15472
15473 /*
15474 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
15475 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
15476 * cable detection and then we are able to read C_DET[3:0].
15477 *
15478 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
15479 * Microcode Default Value' section below.
15480 */
15481 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15482 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, scsi_cfg1 | DIS_TERM_DRV);
15483
15484 /*
15485 * If the PCI Configuration Command Register "Parity Error Response
15486 * Control" Bit was clear (0), then set the microcode variable
15487 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
15488 * to ignore DMA parity errors.
15489 */
15490 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
15491 {
15492 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15493 word |= CONTROL_FLAG_IGNORE_PERR;
15494 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15495 }
15496
15497 /*
15498 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
15499 * bits for the default FIFO threshold.
15500 *
15501 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
15502 *
15503 * For DMA Errata #4 set the BC_THRESH_ENB bit.
15504 */
15505 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
15506 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
15507
15508 /*
15509 * Microcode operating variables for WDTR, SDTR, and command tag
15510 * queuing will be set in AdvInquiryHandling() based on what a
15511 * device reports it is capable of in Inquiry byte 7.
15512 *
15513 * If SCSI Bus Resets have been disabled, then directly set
15514 * SDTR and WDTR from the EEPROM configuration. This will allow
15515 * the BIOS and warm boot to work without a SCSI bus hang on
15516 * the Inquiry caused by host and target mismatched DTR values.
15517 * Without the SCSI Bus Reset, before an Inquiry a device can't
15518 * be assumed to be in Asynchronous, Narrow mode.
15519 */
15520 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
15521 {
15522 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
15523 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
15524 }
15525
15526 /*
15527 * Set microcode operating variables for DISC and SDTR_SPEED1,
15528 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
15529 * configuration values.
15530 *
15531 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
15532 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
15533 * without determining here whether the device supports SDTR.
15534 */
15535 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
15536 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
15537 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
15538 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
15539 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
15540
15541 /*
15542 * Set SCSI_CFG0 Microcode Default Value.
15543 *
15544 * The microcode will set the SCSI_CFG0 register using this value
15545 * after it is started below.
15546 */
15547 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
15548 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
15549 asc_dvc->chip_scsi_id);
15550
15551 /*
15552 * Determine SCSI_CFG1 Microcode Default Value.
15553 *
15554 * The microcode will set the SCSI_CFG1 register using this value
15555 * after it is started below.
15556 */
15557
15558 /* Read current SCSI_CFG1 Register value. */
15559 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15560
15561 /*
15562 * If the internal narrow cable is reversed all of the SCSI_CTRL
15563 * register signals will be set. Check for and return an error if
15564 * this condition is found.
15565 */
15566 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
15567 {
15568 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
15569 return ADV_ERROR;
15570 }
15571
15572 /*
15573 * All kind of combinations of devices attached to one of four connectors
15574 * are acceptable except HVD device attached. For example, LVD device can
15575 * be attached to SE connector while SE device attached to LVD connector.
15576 * If LVD device attached to SE connector, it only runs up to Ultra speed.
15577 *
15578 * If an HVD device is attached to one of LVD connectors, return an error.
15579 * However, there is no way to detect HVD device attached to SE connectors.
15580 */
15581 if (scsi_cfg1 & HVD)
15582 {
15583 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
15584 return ADV_ERROR;
15585 }
15586
15587 /*
15588 * If either SE or LVD automatic termination control is enabled, then
15589 * set the termination value based on a table listed in a_condor.h.
15590 *
15591 * If manual termination was specified with an EEPROM setting then
15592 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready to
15593 * be 'ored' into SCSI_CFG1.
15594 */
15595 if ((asc_dvc->cfg->termination & TERM_SE) == 0)
15596 {
15597 /* SE automatic termination control is enabled. */
15598 switch(scsi_cfg1 & C_DET_SE)
15599 {
15600 /* TERM_SE_HI: on, TERM_SE_LO: on */
15601 case 0x1: case 0x2: case 0x3:
15602 asc_dvc->cfg->termination |= TERM_SE;
15603 break;
15604
15605 /* TERM_SE_HI: on, TERM_SE_LO: off */
15606 case 0x0:
15607 asc_dvc->cfg->termination |= TERM_SE_HI;
15608 break;
15609 }
15610 }
15611
15612 if ((asc_dvc->cfg->termination & TERM_LVD) == 0)
15613 {
15614 /* LVD automatic termination control is enabled. */
15615 switch(scsi_cfg1 & C_DET_LVD)
15616 {
15617 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
15618 case 0x4: case 0x8: case 0xC:
15619 asc_dvc->cfg->termination |= TERM_LVD;
15620 break;
15621
15622 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
15623 case 0x0:
15624 break;
15625 }
15626 }
15627
15628 /*
15629 * Clear any set TERM_SE and TERM_LVD bits.
15630 */
15631 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
15632
15633 /*
15634 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
15635 */
15636 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
15637
15638 /*
15639 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE bits
15640 * and set possibly modified termination control bits in the Microcode
15641 * SCSI_CFG1 Register Value.
15642 */
15643 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
15644
15645 /*
15646 * Set SCSI_CFG1 Microcode Default Value
15647 *
15648 * Set possibly modified termination control and reset DIS_TERM_DRV
15649 * bits in the Microcode SCSI_CFG1 Register Value.
15650 *
15651 * The microcode will set the SCSI_CFG1 register using this value
15652 * after it is started below.
15653 */
15654 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
15655
15656 /*
15657 * Set MEM_CFG Microcode Default Value
15658 *
15659 * The microcode will set the MEM_CFG register using this value
15660 * after it is started below.
15661 *
15662 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
15663 * are defined.
15664 *
15665 * ASC-38C0800 has 16KB internal memory.
15666 */
15667 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
15668 BIOS_EN | RAM_SZ_16KB);
15669
15670 /*
15671 * Set SEL_MASK Microcode Default Value
15672 *
15673 * The microcode will set the SEL_MASK register using this value
15674 * after it is started below.
15675 */
15676 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
15677 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
15678
15679 /*
15680 * Build the carrier freelist.
15681 *
15682 * Driver must have already allocated memory and set 'carrier_buf'.
15683 */
15684 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
15685
15686 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
15687 asc_dvc->carr_freelist = NULL;
15688 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
15689 {
15690 buf_size = ADV_CARRIER_BUFSIZE;
15691 } else
15692 {
15693 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
15694 }
15695
15696 do {
15697 /*
15698 * Get physical address for the carrier 'carrp'.
15699 */
15700 contig_len = sizeof(ADV_CARR_T);
15701 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
15702 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
15703
15704 buf_size -= sizeof(ADV_CARR_T);
15705
15706 /*
15707 * If the current carrier is not physically contiguous, then
15708 * maybe there was a page crossing. Try the next carrier aligned
15709 * start address.
15710 */
15711 if (contig_len < sizeof(ADV_CARR_T))
15712 {
15713 carrp++;
15714 continue;
15715 }
15716
15717 carrp->carr_pa = carr_paddr;
15718 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
15719
15720 /*
15721 * Insert the carrier at the beginning of the freelist.
15722 */
15723 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
15724 asc_dvc->carr_freelist = carrp;
15725
15726 carrp++;
15727 }
15728 while (buf_size > 0);
15729
15730 /*
15731 * Set-up the Host->RISC Initiator Command Queue (ICQ).
15732 */
15733
15734 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
15735 {
15736 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15737 return ADV_ERROR;
15738 }
15739 asc_dvc->carr_freelist = (ADV_CARR_T *)
15740 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
15741
15742 /*
15743 * The first command issued will be placed in the stopper carrier.
15744 */
15745 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15746
15747 /*
15748 * Set RISC ICQ physical address start value.
15749 * carr_pa is LE, must be native before write
15750 */
15751 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
15752
15753 /*
15754 * Set-up the RISC->Host Initiator Response Queue (IRQ).
15755 */
15756 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
15757 {
15758 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15759 return ADV_ERROR;
15760 }
15761 asc_dvc->carr_freelist = (ADV_CARR_T *)
15762 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
15763
15764 /*
15765 * The first command completed by the RISC will be placed in
15766 * the stopper.
15767 *
15768 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
15769 * completed the RISC will set the ASC_RQ_STOPPER bit.
15770 */
15771 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15772
15773 /*
15774 * Set RISC IRQ physical address start value.
15775 *
15776 * carr_pa is LE, must be native before write *
15777 */
15778 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
15779 asc_dvc->carr_pending_cnt = 0;
15780
15781 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
15782 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
15783
15784 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
15785 AdvWriteWordRegister(iop_base, IOPW_PC, word);
15786
15787 /* finally, finally, gentlemen, start your engine */
15788 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
15789
15790 /*
15791 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
15792 * Resets should be performed. The RISC has to be running
15793 * to issue a SCSI Bus Reset.
15794 */
15795 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
15796 {
15797 /*
15798 * If the BIOS Signature is present in memory, restore the
15799 * BIOS Handshake Configuration Table and do not perform
15800 * a SCSI Bus Reset.
15801 */
15802 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
15803 {
15804 /*
15805 * Restore per TID negotiated values.
15806 */
15807 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15808 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15809 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15810 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15811 {
15812 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15813 max_cmd[tid]);
15814 }
15815 } else
15816 {
15817 if (AdvResetSB(asc_dvc) != ADV_TRUE)
15818 {
15819 warn_code = ASC_WARN_BUSRESET_ERROR;
15820 }
15821 }
15822 }
15823
15824 return warn_code;
15825}
15826
15827/*
15828 * Initialize the ASC-38C1600.
15829 *
15830 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
15831 *
15832 * For a non-fatal error return a warning code. If there are no warnings
15833 * then 0 is returned.
15834 *
15835 * Needed after initialization for error recovery.
15836 */
15837STATIC int
15838AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
15839{
15840 AdvPortAddr iop_base;
15841 ushort warn_code;
15842 ADV_DCNT sum;
15843 int begin_addr;
15844 int end_addr;
15845 ushort code_sum;
15846 long word;
15847 int j;
15848 int adv_asc38C1600_expanded_size;
15849 ADV_CARR_T *carrp;
15850 ADV_DCNT contig_len;
15851 ADV_SDCNT buf_size;
15852 ADV_PADDR carr_paddr;
15853 int i;
15854 ushort scsi_cfg1;
15855 uchar byte;
15856 uchar tid;
15857 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
15858 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
15859 uchar max_cmd[ASC_MAX_TID + 1];
15860
15861 /* If there is already an error, don't continue. */
15862 if (asc_dvc->err_code != 0)
15863 {
15864 return ADV_ERROR;
15865 }
15866
15867 /*
15868 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
15869 */
15870 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600)
15871 {
15872 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
15873 return ADV_ERROR;
15874 }
15875
15876 warn_code = 0;
15877 iop_base = asc_dvc->iop_base;
15878
15879 /*
15880 * Save the RISC memory BIOS region before writing the microcode.
15881 * The BIOS may already be loaded and using its RISC LRAM region
15882 * so its region must be saved and restored.
15883 *
15884 * Note: This code makes the assumption, which is currently true,
15885 * that a chip reset does not clear RISC LRAM.
15886 */
15887 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15888 {
15889 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15890 }
15891
15892 /*
15893 * Save current per TID negotiated values.
15894 */
15895 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15896 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15897 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
15898 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15899 for (tid = 0; tid <= ASC_MAX_TID; tid++)
15900 {
15901 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15902 max_cmd[tid]);
15903 }
15904
15905 /*
15906 * RAM BIST (Built-In Self Test)
15907 *
15908 * Address : I/O base + offset 0x38h register (byte).
15909 * Function: Bit 7-6(RW) : RAM mode
15910 * Normal Mode : 0x00
15911 * Pre-test Mode : 0x40
15912 * RAM Test Mode : 0x80
15913 * Bit 5 : unused
15914 * Bit 4(RO) : Done bit
15915 * Bit 3-0(RO) : Status
15916 * Host Error : 0x08
15917 * Int_RAM Error : 0x04
15918 * RISC Error : 0x02
15919 * SCSI Error : 0x01
15920 * No Error : 0x00
15921 *
15922 * Note: RAM BIST code should be put right here, before loading the
15923 * microcode and after saving the RISC memory BIOS region.
15924 */
15925
15926 /*
15927 * LRAM Pre-test
15928 *
15929 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
15930 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
15931 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
15932 * to NORMAL_MODE, return an error too.
15933 */
15934 for (i = 0; i < 2; i++)
15935 {
15936 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
15937 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15938 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15939 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != PRE_TEST_VALUE)
15940 {
15941 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15942 return ADV_ERROR;
15943 }
15944
15945 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15946 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15947 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
15948 != NORMAL_VALUE)
15949 {
15950 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15951 return ADV_ERROR;
15952 }
15953 }
15954
15955 /*
15956 * LRAM Test - It takes about 1.5 ms to run through the test.
15957 *
15958 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
15959 * If Done bit not set or Status not 0, save register byte, set the
15960 * err_code, and return an error.
15961 */
15962 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
15963 DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
15964
15965 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15966 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0)
15967 {
15968 /* Get here if Done bit not set or Status not 0. */
15969 asc_dvc->bist_err_code = byte; /* for BIOS display message */
15970 asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
15971 return ADV_ERROR;
15972 }
15973
15974 /* We need to reset back to normal mode after LRAM test passes. */
15975 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15976
15977 /*
15978 * Load the Microcode
15979 *
15980 * Write the microcode image to RISC memory starting at address 0.
15981 *
15982 */
15983 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15984
15985 /*
15986 * Assume the following compressed format of the microcode buffer:
15987 *
15988 * 254 word (508 byte) table indexed by byte code followed
15989 * by the following byte codes:
15990 *
15991 * 1-Byte Code:
15992 * 00: Emit word 0 in table.
15993 * 01: Emit word 1 in table.
15994 * .
15995 * FD: Emit word 253 in table.
15996 *
15997 * Multi-Byte Code:
15998 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
15999 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
16000 */
16001 word = 0;
16002 for (i = 253 * 2; i < _adv_asc38C1600_size; i++)
16003 {
16004 if (_adv_asc38C1600_buf[i] == 0xff)
16005 {
16006 for (j = 0; j < _adv_asc38C1600_buf[i + 1]; j++)
16007 {
16008 AdvWriteWordAutoIncLram(iop_base, (((ushort)
16009 _adv_asc38C1600_buf[i + 3] << 8) |
16010 _adv_asc38C1600_buf[i + 2]));
16011 word++;
16012 }
16013 i += 3;
16014 } else if (_adv_asc38C1600_buf[i] == 0xfe)
16015 {
16016 AdvWriteWordAutoIncLram(iop_base, (((ushort)
16017 _adv_asc38C1600_buf[i + 2] << 8) |
16018 _adv_asc38C1600_buf[i + 1]));
16019 i += 2;
16020 word++;
16021 } else
16022 {
16023 AdvWriteWordAutoIncLram(iop_base, (((ushort)
16024 _adv_asc38C1600_buf[(_adv_asc38C1600_buf[i] * 2) + 1] << 8) |
16025 _adv_asc38C1600_buf[_adv_asc38C1600_buf[i] * 2]));
16026 word++;
16027 }
16028 }
16029
16030 /*
16031 * Set 'word' for later use to clear the rest of memory and save
16032 * the expanded mcode size.
16033 */
16034 word *= 2;
16035 adv_asc38C1600_expanded_size = word;
16036
16037 /*
16038 * Clear the rest of ASC-38C1600 Internal RAM (32KB).
16039 */
16040 for (; word < ADV_38C1600_MEMSIZE; word += 2)
16041 {
16042 AdvWriteWordAutoIncLram(iop_base, 0);
16043 }
16044
16045 /*
16046 * Verify the microcode checksum.
16047 */
16048 sum = 0;
16049 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
16050
16051 for (word = 0; word < adv_asc38C1600_expanded_size; word += 2)
16052 {
16053 sum += AdvReadWordAutoIncLram(iop_base);
16054 }
16055
16056 if (sum != _adv_asc38C1600_chksum)
16057 {
16058 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
16059 return ADV_ERROR;
16060 }
16061
16062 /*
16063 * Restore the RISC memory BIOS region.
16064 */
16065 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
16066 {
16067 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
16068 }
16069
16070 /*
16071 * Calculate and write the microcode code checksum to the microcode
16072 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
16073 */
16074 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
16075 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
16076 code_sum = 0;
16077 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
16078 for (word = begin_addr; word < end_addr; word += 2)
16079 {
16080 code_sum += AdvReadWordAutoIncLram(iop_base);
16081 }
16082 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
16083
16084 /*
16085 * Read microcode version and date.
16086 */
16087 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
16088 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
16089
16090 /*
16091 * Set the chip type to indicate the ASC38C1600.
16092 */
16093 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
16094
16095 /*
16096 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
16097 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
16098 * cable detection and then we are able to read C_DET[3:0].
16099 *
16100 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
16101 * Microcode Default Value' section below.
16102 */
16103 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
16104 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, scsi_cfg1 | DIS_TERM_DRV);
16105
16106 /*
16107 * If the PCI Configuration Command Register "Parity Error Response
16108 * Control" Bit was clear (0), then set the microcode variable
16109 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
16110 * to ignore DMA parity errors.
16111 */
16112 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
16113 {
16114 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16115 word |= CONTROL_FLAG_IGNORE_PERR;
16116 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16117 }
16118
16119 /*
16120 * If the BIOS control flag AIPP (Asynchronous Information
16121 * Phase Protection) disable bit is not set, then set the firmware
16122 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
16123 * AIPP checking and encoding.
16124 */
16125 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0)
16126 {
16127 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16128 word |= CONTROL_FLAG_ENABLE_AIPP;
16129 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16130 }
16131
16132 /*
16133 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
16134 * and START_CTL_TH [3:2].
16135 */
16136 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
16137 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
16138
16139 /*
16140 * Microcode operating variables for WDTR, SDTR, and command tag
16141 * queuing will be set in AdvInquiryHandling() based on what a
16142 * device reports it is capable of in Inquiry byte 7.
16143 *
16144 * If SCSI Bus Resets have been disabled, then directly set
16145 * SDTR and WDTR from the EEPROM configuration. This will allow
16146 * the BIOS and warm boot to work without a SCSI bus hang on
16147 * the Inquiry caused by host and target mismatched DTR values.
16148 * Without the SCSI Bus Reset, before an Inquiry a device can't
16149 * be assumed to be in Asynchronous, Narrow mode.
16150 */
16151 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
16152 {
16153 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
16154 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
16155 }
16156
16157 /*
16158 * Set microcode operating variables for DISC and SDTR_SPEED1,
16159 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
16160 * configuration values.
16161 *
16162 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
16163 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
16164 * without determining here whether the device supports SDTR.
16165 */
16166 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
16167 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
16168 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
16169 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
16170 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
16171
16172 /*
16173 * Set SCSI_CFG0 Microcode Default Value.
16174 *
16175 * The microcode will set the SCSI_CFG0 register using this value
16176 * after it is started below.
16177 */
16178 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
16179 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
16180 asc_dvc->chip_scsi_id);
16181
16182 /*
16183 * Calculate SCSI_CFG1 Microcode Default Value.
16184 *
16185 * The microcode will set the SCSI_CFG1 register using this value
16186 * after it is started below.
16187 *
16188 * Each ASC-38C1600 function has only two cable detect bits.
16189 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
16190 */
16191 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
16192
16193 /*
16194 * If the cable is reversed all of the SCSI_CTRL register signals
16195 * will be set. Check for and return an error if this condition is
16196 * found.
16197 */
16198 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
16199 {
16200 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
16201 return ADV_ERROR;
16202 }
16203
16204 /*
16205 * Each ASC-38C1600 function has two connectors. Only an HVD device
16206 * can not be connected to either connector. An LVD device or SE device
16207 * may be connected to either connecor. If an SE device is connected,
16208 * then at most Ultra speed (20 Mhz) can be used on both connectors.
16209 *
16210 * If an HVD device is attached, return an error.
16211 */
16212 if (scsi_cfg1 & HVD)
16213 {
16214 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
16215 return ADV_ERROR;
16216 }
16217
16218 /*
16219 * Each function in the ASC-38C1600 uses only the SE cable detect and
16220 * termination because there are two connectors for each function. Each
16221 * function may use either LVD or SE mode. Corresponding the SE automatic
16222 * termination control EEPROM bits are used for each function. Each
16223 * function has its own EEPROM. If SE automatic control is enabled for
16224 * the function, then set the termination value based on a table listed
16225 * in a_condor.h.
16226 *
16227 * If manual termination is specified in the EEPROM for the function,
16228 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
16229 * ready to be 'ored' into SCSI_CFG1.
16230 */
16231 if ((asc_dvc->cfg->termination & TERM_SE) == 0)
16232 {
16233 /* SE automatic termination control is enabled. */
16234 switch(scsi_cfg1 & C_DET_SE)
16235 {
16236 /* TERM_SE_HI: on, TERM_SE_LO: on */
16237 case 0x1: case 0x2: case 0x3:
16238 asc_dvc->cfg->termination |= TERM_SE;
16239 break;
16240
16241 case 0x0:
16242 if (ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) == 0)
16243 {
16244 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
16245 }
16246 else
16247 {
16248 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
16249 asc_dvc->cfg->termination |= TERM_SE_HI;
16250 }
16251 break;
16252 }
16253 }
16254
16255 /*
16256 * Clear any set TERM_SE bits.
16257 */
16258 scsi_cfg1 &= ~TERM_SE;
16259
16260 /*
16261 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
16262 */
16263 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
16264
16265 /*
16266 * Clear Big Endian and Terminator Polarity bits and set possibly
16267 * modified termination control bits in the Microcode SCSI_CFG1
16268 * Register Value.
16269 *
16270 * Big Endian bit is not used even on big endian machines.
16271 */
16272 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
16273
16274 /*
16275 * Set SCSI_CFG1 Microcode Default Value
16276 *
16277 * Set possibly modified termination control bits in the Microcode
16278 * SCSI_CFG1 Register Value.
16279 *
16280 * The microcode will set the SCSI_CFG1 register using this value
16281 * after it is started below.
16282 */
16283 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
16284
16285 /*
16286 * Set MEM_CFG Microcode Default Value
16287 *
16288 * The microcode will set the MEM_CFG register using this value
16289 * after it is started below.
16290 *
16291 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
16292 * are defined.
16293 *
16294 * ASC-38C1600 has 32KB internal memory.
16295 *
16296 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
16297 * out a special 16K Adv Library and Microcode version. After the issue
16298 * resolved, we should turn back to the 32K support. Both a_condor.h and
16299 * mcode.sas files also need to be updated.
16300 *
16301 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
16302 * BIOS_EN | RAM_SZ_32KB);
16303 */
16304 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, BIOS_EN | RAM_SZ_16KB);
16305
16306 /*
16307 * Set SEL_MASK Microcode Default Value
16308 *
16309 * The microcode will set the SEL_MASK register using this value
16310 * after it is started below.
16311 */
16312 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
16313 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
16314
16315 /*
16316 * Build the carrier freelist.
16317 *
16318 * Driver must have already allocated memory and set 'carrier_buf'.
16319 */
16320
16321 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
16322
16323 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
16324 asc_dvc->carr_freelist = NULL;
16325 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
16326 {
16327 buf_size = ADV_CARRIER_BUFSIZE;
16328 } else
16329 {
16330 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
16331 }
16332
16333 do {
16334 /*
16335 * Get physical address for the carrier 'carrp'.
16336 */
16337 contig_len = sizeof(ADV_CARR_T);
16338 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
16339 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
16340
16341 buf_size -= sizeof(ADV_CARR_T);
16342
16343 /*
16344 * If the current carrier is not physically contiguous, then
16345 * maybe there was a page crossing. Try the next carrier aligned
16346 * start address.
16347 */
16348 if (contig_len < sizeof(ADV_CARR_T))
16349 {
16350 carrp++;
16351 continue;
16352 }
16353
16354 carrp->carr_pa = carr_paddr;
16355 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
16356
16357 /*
16358 * Insert the carrier at the beginning of the freelist.
16359 */
16360 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
16361 asc_dvc->carr_freelist = carrp;
16362
16363 carrp++;
16364 }
16365 while (buf_size > 0);
16366
16367 /*
16368 * Set-up the Host->RISC Initiator Command Queue (ICQ).
16369 */
16370 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
16371 {
16372 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
16373 return ADV_ERROR;
16374 }
16375 asc_dvc->carr_freelist = (ADV_CARR_T *)
16376 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
16377
16378 /*
16379 * The first command issued will be placed in the stopper carrier.
16380 */
16381 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
16382
16383 /*
16384 * Set RISC ICQ physical address start value. Initialize the
16385 * COMMA register to the same value otherwise the RISC will
16386 * prematurely detect a command is available.
16387 */
16388 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
16389 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
16390 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
16391
16392 /*
16393 * Set-up the RISC->Host Initiator Response Queue (IRQ).
16394 */
16395 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
16396 {
16397 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
16398 return ADV_ERROR;
16399 }
16400 asc_dvc->carr_freelist = (ADV_CARR_T *)
16401 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
16402
16403 /*
16404 * The first command completed by the RISC will be placed in
16405 * the stopper.
16406 *
16407 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
16408 * completed the RISC will set the ASC_RQ_STOPPER bit.
16409 */
16410 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
16411
16412 /*
16413 * Set RISC IRQ physical address start value.
16414 */
16415 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
16416 asc_dvc->carr_pending_cnt = 0;
16417
16418 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
16419 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
16420 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
16421 AdvWriteWordRegister(iop_base, IOPW_PC, word);
16422
16423 /* finally, finally, gentlemen, start your engine */
16424 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
16425
16426 /*
16427 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
16428 * Resets should be performed. The RISC has to be running
16429 * to issue a SCSI Bus Reset.
16430 */
16431 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
16432 {
16433 /*
16434 * If the BIOS Signature is present in memory, restore the
16435 * per TID microcode operating variables.
16436 */
16437 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
16438 {
16439 /*
16440 * Restore per TID negotiated values.
16441 */
16442 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
16443 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
16444 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
16445 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
16446 for (tid = 0; tid <= ASC_MAX_TID; tid++)
16447 {
16448 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
16449 max_cmd[tid]);
16450 }
16451 } else
16452 {
16453 if (AdvResetSB(asc_dvc) != ADV_TRUE)
16454 {
16455 warn_code = ASC_WARN_BUSRESET_ERROR;
16456 }
16457 }
16458 }
16459
16460 return warn_code;
16461}
16462
16463/*
16464 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
16465 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
16466 * all of this is done.
16467 *
16468 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
16469 *
16470 * For a non-fatal error return a warning code. If there are no warnings
16471 * then 0 is returned.
16472 *
16473 * Note: Chip is stopped on entry.
16474 */
16475STATIC int __init
16476AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
16477{
16478 AdvPortAddr iop_base;
16479 ushort warn_code;
16480 ADVEEP_3550_CONFIG eep_config;
16481 int i;
16482
16483 iop_base = asc_dvc->iop_base;
16484
16485 warn_code = 0;
16486
16487 /*
16488 * Read the board's EEPROM configuration.
16489 *
16490 * Set default values if a bad checksum is found.
16491 */
16492 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16493 {
16494 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16495
16496 /*
16497 * Set EEPROM default values.
16498 */
16499 for (i = 0; i < sizeof(ADVEEP_3550_CONFIG); i++)
16500 {
16501 *((uchar *) &eep_config + i) =
16502 *((uchar *) &Default_3550_EEPROM_Config + i);
16503 }
16504
16505 /*
16506 * Assume the 6 byte board serial number that was read
16507 * from EEPROM is correct even if the EEPROM checksum
16508 * failed.
16509 */
16510 eep_config.serial_number_word3 =
16511 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16512
16513 eep_config.serial_number_word2 =
16514 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16515
16516 eep_config.serial_number_word1 =
16517 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16518
16519 AdvSet3550EEPConfig(iop_base, &eep_config);
16520 }
16521 /*
16522 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
16523 * EEPROM configuration that was read.
16524 *
16525 * This is the mapping of EEPROM fields to Adv Library fields.
16526 */
16527 asc_dvc->wdtr_able = eep_config.wdtr_able;
16528 asc_dvc->sdtr_able = eep_config.sdtr_able;
16529 asc_dvc->ultra_able = eep_config.ultra_able;
16530 asc_dvc->tagqng_able = eep_config.tagqng_able;
16531 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16532 asc_dvc->max_host_qng = eep_config.max_host_qng;
16533 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16534 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
16535 asc_dvc->start_motor = eep_config.start_motor;
16536 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16537 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16538 asc_dvc->no_scam = eep_config.scam_tolerant;
16539 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
16540 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
16541 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
16542
16543 /*
16544 * Set the host maximum queuing (max. 253, min. 16) and the per device
16545 * maximum queuing (max. 63, min. 4).
16546 */
16547 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
16548 {
16549 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16550 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
16551 {
16552 /* If the value is zero, assume it is uninitialized. */
16553 if (eep_config.max_host_qng == 0)
16554 {
16555 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16556 } else
16557 {
16558 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
16559 }
16560 }
16561
16562 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
16563 {
16564 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16565 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
16566 {
16567 /* If the value is zero, assume it is uninitialized. */
16568 if (eep_config.max_dvc_qng == 0)
16569 {
16570 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16571 } else
16572 {
16573 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
16574 }
16575 }
16576
16577 /*
16578 * If 'max_dvc_qng' is greater than 'max_host_qng', then
16579 * set 'max_dvc_qng' to 'max_host_qng'.
16580 */
16581 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
16582 {
16583 eep_config.max_dvc_qng = eep_config.max_host_qng;
16584 }
16585
16586 /*
16587 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
16588 * values based on possibly adjusted EEPROM values.
16589 */
16590 asc_dvc->max_host_qng = eep_config.max_host_qng;
16591 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16592
16593
16594 /*
16595 * If the EEPROM 'termination' field is set to automatic (0), then set
16596 * the ADV_DVC_CFG 'termination' field to automatic also.
16597 *
16598 * If the termination is specified with a non-zero 'termination'
16599 * value check that a legal value is set and set the ADV_DVC_CFG
16600 * 'termination' field appropriately.
16601 */
16602 if (eep_config.termination == 0)
16603 {
16604 asc_dvc->cfg->termination = 0; /* auto termination */
16605 } else
16606 {
16607 /* Enable manual control with low off / high off. */
16608 if (eep_config.termination == 1)
16609 {
16610 asc_dvc->cfg->termination = TERM_CTL_SEL;
16611
16612 /* Enable manual control with low off / high on. */
16613 } else if (eep_config.termination == 2)
16614 {
16615 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
16616
16617 /* Enable manual control with low on / high on. */
16618 } else if (eep_config.termination == 3)
16619 {
16620 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
16621 } else
16622 {
16623 /*
16624 * The EEPROM 'termination' field contains a bad value. Use
16625 * automatic termination instead.
16626 */
16627 asc_dvc->cfg->termination = 0;
16628 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16629 }
16630 }
16631
16632 return warn_code;
16633}
16634
16635/*
16636 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
16637 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
16638 * all of this is done.
16639 *
16640 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
16641 *
16642 * For a non-fatal error return a warning code. If there are no warnings
16643 * then 0 is returned.
16644 *
16645 * Note: Chip is stopped on entry.
16646 */
16647STATIC int __init
16648AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
16649{
16650 AdvPortAddr iop_base;
16651 ushort warn_code;
16652 ADVEEP_38C0800_CONFIG eep_config;
16653 int i;
16654 uchar tid, termination;
16655 ushort sdtr_speed = 0;
16656
16657 iop_base = asc_dvc->iop_base;
16658
16659 warn_code = 0;
16660
16661 /*
16662 * Read the board's EEPROM configuration.
16663 *
16664 * Set default values if a bad checksum is found.
16665 */
16666 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16667 {
16668 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16669
16670 /*
16671 * Set EEPROM default values.
16672 */
16673 for (i = 0; i < sizeof(ADVEEP_38C0800_CONFIG); i++)
16674 {
16675 *((uchar *) &eep_config + i) =
16676 *((uchar *) &Default_38C0800_EEPROM_Config + i);
16677 }
16678
16679 /*
16680 * Assume the 6 byte board serial number that was read
16681 * from EEPROM is correct even if the EEPROM checksum
16682 * failed.
16683 */
16684 eep_config.serial_number_word3 =
16685 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16686
16687 eep_config.serial_number_word2 =
16688 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16689
16690 eep_config.serial_number_word1 =
16691 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16692
16693 AdvSet38C0800EEPConfig(iop_base, &eep_config);
16694 }
16695 /*
16696 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
16697 * EEPROM configuration that was read.
16698 *
16699 * This is the mapping of EEPROM fields to Adv Library fields.
16700 */
16701 asc_dvc->wdtr_able = eep_config.wdtr_able;
16702 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
16703 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
16704 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
16705 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
16706 asc_dvc->tagqng_able = eep_config.tagqng_able;
16707 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16708 asc_dvc->max_host_qng = eep_config.max_host_qng;
16709 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16710 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
16711 asc_dvc->start_motor = eep_config.start_motor;
16712 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16713 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16714 asc_dvc->no_scam = eep_config.scam_tolerant;
16715 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
16716 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
16717 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
16718
16719 /*
16720 * For every Target ID if any of its 'sdtr_speed[1234]' bits
16721 * are set, then set an 'sdtr_able' bit for it.
16722 */
16723 asc_dvc->sdtr_able = 0;
16724 for (tid = 0; tid <= ADV_MAX_TID; tid++)
16725 {
16726 if (tid == 0)
16727 {
16728 sdtr_speed = asc_dvc->sdtr_speed1;
16729 } else if (tid == 4)
16730 {
16731 sdtr_speed = asc_dvc->sdtr_speed2;
16732 } else if (tid == 8)
16733 {
16734 sdtr_speed = asc_dvc->sdtr_speed3;
16735 } else if (tid == 12)
16736 {
16737 sdtr_speed = asc_dvc->sdtr_speed4;
16738 }
16739 if (sdtr_speed & ADV_MAX_TID)
16740 {
16741 asc_dvc->sdtr_able |= (1 << tid);
16742 }
16743 sdtr_speed >>= 4;
16744 }
16745
16746 /*
16747 * Set the host maximum queuing (max. 253, min. 16) and the per device
16748 * maximum queuing (max. 63, min. 4).
16749 */
16750 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
16751 {
16752 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16753 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
16754 {
16755 /* If the value is zero, assume it is uninitialized. */
16756 if (eep_config.max_host_qng == 0)
16757 {
16758 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16759 } else
16760 {
16761 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
16762 }
16763 }
16764
16765 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
16766 {
16767 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16768 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
16769 {
16770 /* If the value is zero, assume it is uninitialized. */
16771 if (eep_config.max_dvc_qng == 0)
16772 {
16773 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16774 } else
16775 {
16776 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
16777 }
16778 }
16779
16780 /*
16781 * If 'max_dvc_qng' is greater than 'max_host_qng', then
16782 * set 'max_dvc_qng' to 'max_host_qng'.
16783 */
16784 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
16785 {
16786 eep_config.max_dvc_qng = eep_config.max_host_qng;
16787 }
16788
16789 /*
16790 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
16791 * values based on possibly adjusted EEPROM values.
16792 */
16793 asc_dvc->max_host_qng = eep_config.max_host_qng;
16794 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16795
16796 /*
16797 * If the EEPROM 'termination' field is set to automatic (0), then set
16798 * the ADV_DVC_CFG 'termination' field to automatic also.
16799 *
16800 * If the termination is specified with a non-zero 'termination'
16801 * value check that a legal value is set and set the ADV_DVC_CFG
16802 * 'termination' field appropriately.
16803 */
16804 if (eep_config.termination_se == 0)
16805 {
16806 termination = 0; /* auto termination for SE */
16807 } else
16808 {
16809 /* Enable manual control with low off / high off. */
16810 if (eep_config.termination_se == 1)
16811 {
16812 termination = 0;
16813
16814 /* Enable manual control with low off / high on. */
16815 } else if (eep_config.termination_se == 2)
16816 {
16817 termination = TERM_SE_HI;
16818
16819 /* Enable manual control with low on / high on. */
16820 } else if (eep_config.termination_se == 3)
16821 {
16822 termination = TERM_SE;
16823 } else
16824 {
16825 /*
16826 * The EEPROM 'termination_se' field contains a bad value.
16827 * Use automatic termination instead.
16828 */
16829 termination = 0;
16830 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16831 }
16832 }
16833
16834 if (eep_config.termination_lvd == 0)
16835 {
16836 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
16837 } else
16838 {
16839 /* Enable manual control with low off / high off. */
16840 if (eep_config.termination_lvd == 1)
16841 {
16842 asc_dvc->cfg->termination = termination;
16843
16844 /* Enable manual control with low off / high on. */
16845 } else if (eep_config.termination_lvd == 2)
16846 {
16847 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
16848
16849 /* Enable manual control with low on / high on. */
16850 } else if (eep_config.termination_lvd == 3)
16851 {
16852 asc_dvc->cfg->termination =
16853 termination | TERM_LVD;
16854 } else
16855 {
16856 /*
16857 * The EEPROM 'termination_lvd' field contains a bad value.
16858 * Use automatic termination instead.
16859 */
16860 asc_dvc->cfg->termination = termination;
16861 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16862 }
16863 }
16864
16865 return warn_code;
16866}
16867
16868/*
16869 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
16870 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
16871 * all of this is done.
16872 *
16873 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
16874 *
16875 * For a non-fatal error return a warning code. If there are no warnings
16876 * then 0 is returned.
16877 *
16878 * Note: Chip is stopped on entry.
16879 */
16880STATIC int __init
16881AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
16882{
16883 AdvPortAddr iop_base;
16884 ushort warn_code;
16885 ADVEEP_38C1600_CONFIG eep_config;
16886 int i;
16887 uchar tid, termination;
16888 ushort sdtr_speed = 0;
16889
16890 iop_base = asc_dvc->iop_base;
16891
16892 warn_code = 0;
16893
16894 /*
16895 * Read the board's EEPROM configuration.
16896 *
16897 * Set default values if a bad checksum is found.
16898 */
16899 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16900 {
16901 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16902
16903 /*
16904 * Set EEPROM default values.
16905 */
16906 for (i = 0; i < sizeof(ADVEEP_38C1600_CONFIG); i++)
16907 {
16908 if (i == 1 && ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) != 0)
16909 {
16910 /*
16911 * Set Function 1 EEPROM Word 0 MSB
16912 *
16913 * Clear the BIOS_ENABLE (bit 14) and INTAB (bit 11)
16914 * EEPROM bits.
16915 *
16916 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 and
16917 * old Mac system booting problem. The Expansion ROM must
16918 * be disabled in Function 1 for these systems.
16919 *
16920 */
16921 *((uchar *) &eep_config + i) =
16922 ((*((uchar *) &Default_38C1600_EEPROM_Config + i)) &
16923 (~(((ADV_EEPROM_BIOS_ENABLE | ADV_EEPROM_INTAB) >> 8) &
16924 0xFF)));
16925
16926 /*
16927 * Set the INTAB (bit 11) if the GPIO 0 input indicates
16928 * the Function 1 interrupt line is wired to INTA.
16929 *
16930 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
16931 * 1 - Function 1 interrupt line wired to INT A.
16932 * 0 - Function 1 interrupt line wired to INT B.
16933 *
16934 * Note: Adapter boards always have Function 0 wired to INTA.
16935 * Put all 5 GPIO bits in input mode and then read
16936 * their input values.
16937 */
16938 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
16939 if (AdvReadByteRegister(iop_base, IOPB_GPIO_DATA) & 0x01)
16940 {
16941 /* Function 1 interrupt wired to INTA; Set EEPROM bit. */
16942 *((uchar *) &eep_config + i) |=
16943 ((ADV_EEPROM_INTAB >> 8) & 0xFF);
16944 }
16945 }
16946 else
16947 {
16948 *((uchar *) &eep_config + i) =
16949 *((uchar *) &Default_38C1600_EEPROM_Config + i);
16950 }
16951 }
16952
16953 /*
16954 * Assume the 6 byte board serial number that was read
16955 * from EEPROM is correct even if the EEPROM checksum
16956 * failed.
16957 */
16958 eep_config.serial_number_word3 =
16959 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16960
16961 eep_config.serial_number_word2 =
16962 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16963
16964 eep_config.serial_number_word1 =
16965 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16966
16967 AdvSet38C1600EEPConfig(iop_base, &eep_config);
16968 }
16969
16970 /*
16971 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
16972 * EEPROM configuration that was read.
16973 *
16974 * This is the mapping of EEPROM fields to Adv Library fields.
16975 */
16976 asc_dvc->wdtr_able = eep_config.wdtr_able;
16977 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
16978 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
16979 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
16980 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
16981 asc_dvc->ppr_able = 0;
16982 asc_dvc->tagqng_able = eep_config.tagqng_able;
16983 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16984 asc_dvc->max_host_qng = eep_config.max_host_qng;
16985 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16986 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
16987 asc_dvc->start_motor = eep_config.start_motor;
16988 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16989 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16990 asc_dvc->no_scam = eep_config.scam_tolerant;
16991
16992 /*
16993 * For every Target ID if any of its 'sdtr_speed[1234]' bits
16994 * are set, then set an 'sdtr_able' bit for it.
16995 */
16996 asc_dvc->sdtr_able = 0;
16997 for (tid = 0; tid <= ASC_MAX_TID; tid++)
16998 {
16999 if (tid == 0)
17000 {
17001 sdtr_speed = asc_dvc->sdtr_speed1;
17002 } else if (tid == 4)
17003 {
17004 sdtr_speed = asc_dvc->sdtr_speed2;
17005 } else if (tid == 8)
17006 {
17007 sdtr_speed = asc_dvc->sdtr_speed3;
17008 } else if (tid == 12)
17009 {
17010 sdtr_speed = asc_dvc->sdtr_speed4;
17011 }
17012 if (sdtr_speed & ASC_MAX_TID)
17013 {
17014 asc_dvc->sdtr_able |= (1 << tid);
17015 }
17016 sdtr_speed >>= 4;
17017 }
17018
17019 /*
17020 * Set the host maximum queuing (max. 253, min. 16) and the per device
17021 * maximum queuing (max. 63, min. 4).
17022 */
17023 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
17024 {
17025 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
17026 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
17027 {
17028 /* If the value is zero, assume it is uninitialized. */
17029 if (eep_config.max_host_qng == 0)
17030 {
17031 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
17032 } else
17033 {
17034 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
17035 }
17036 }
17037
17038 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
17039 {
17040 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
17041 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
17042 {
17043 /* If the value is zero, assume it is uninitialized. */
17044 if (eep_config.max_dvc_qng == 0)
17045 {
17046 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
17047 } else
17048 {
17049 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
17050 }
17051 }
17052
17053 /*
17054 * If 'max_dvc_qng' is greater than 'max_host_qng', then
17055 * set 'max_dvc_qng' to 'max_host_qng'.
17056 */
17057 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
17058 {
17059 eep_config.max_dvc_qng = eep_config.max_host_qng;
17060 }
17061
17062 /*
17063 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
17064 * values based on possibly adjusted EEPROM values.
17065 */
17066 asc_dvc->max_host_qng = eep_config.max_host_qng;
17067 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
17068
17069 /*
17070 * If the EEPROM 'termination' field is set to automatic (0), then set
17071 * the ASC_DVC_CFG 'termination' field to automatic also.
17072 *
17073 * If the termination is specified with a non-zero 'termination'
17074 * value check that a legal value is set and set the ASC_DVC_CFG
17075 * 'termination' field appropriately.
17076 */
17077 if (eep_config.termination_se == 0)
17078 {
17079 termination = 0; /* auto termination for SE */
17080 } else
17081 {
17082 /* Enable manual control with low off / high off. */
17083 if (eep_config.termination_se == 1)
17084 {
17085 termination = 0;
17086
17087 /* Enable manual control with low off / high on. */
17088 } else if (eep_config.termination_se == 2)
17089 {
17090 termination = TERM_SE_HI;
17091
17092 /* Enable manual control with low on / high on. */
17093 } else if (eep_config.termination_se == 3)
17094 {
17095 termination = TERM_SE;
17096 } else
17097 {
17098 /*
17099 * The EEPROM 'termination_se' field contains a bad value.
17100 * Use automatic termination instead.
17101 */
17102 termination = 0;
17103 warn_code |= ASC_WARN_EEPROM_TERMINATION;
17104 }
17105 }
17106
17107 if (eep_config.termination_lvd == 0)
17108 {
17109 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
17110 } else
17111 {
17112 /* Enable manual control with low off / high off. */
17113 if (eep_config.termination_lvd == 1)
17114 {
17115 asc_dvc->cfg->termination = termination;
17116
17117 /* Enable manual control with low off / high on. */
17118 } else if (eep_config.termination_lvd == 2)
17119 {
17120 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
17121
17122 /* Enable manual control with low on / high on. */
17123 } else if (eep_config.termination_lvd == 3)
17124 {
17125 asc_dvc->cfg->termination =
17126 termination | TERM_LVD;
17127 } else
17128 {
17129 /*
17130 * The EEPROM 'termination_lvd' field contains a bad value.
17131 * Use automatic termination instead.
17132 */
17133 asc_dvc->cfg->termination = termination;
17134 warn_code |= ASC_WARN_EEPROM_TERMINATION;
17135 }
17136 }
17137
17138 return warn_code;
17139}
17140
17141/*
17142 * Read EEPROM configuration into the specified buffer.
17143 *
17144 * Return a checksum based on the EEPROM configuration read.
17145 */
17146STATIC ushort __init
17147AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
17148{
17149 ushort wval, chksum;
17150 ushort *wbuf;
17151 int eep_addr;
17152 ushort *charfields;
17153
17154 charfields = (ushort *) &ADVEEP_3550_Config_Field_IsChar;
17155 wbuf = (ushort *) cfg_buf;
17156 chksum = 0;
17157
17158 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17159 eep_addr < ADV_EEP_DVC_CFG_END;
17160 eep_addr++, wbuf++)
17161 {
17162 wval = AdvReadEEPWord(iop_base, eep_addr);
17163 chksum += wval; /* Checksum is calculated from word values. */
17164 if (*charfields++) {
17165 *wbuf = le16_to_cpu(wval);
17166 } else {
17167 *wbuf = wval;
17168 }
17169 }
17170 /* Read checksum word. */
17171 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17172 wbuf++; charfields++;
17173
17174 /* Read rest of EEPROM not covered by the checksum. */
17175 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17176 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17177 eep_addr++, wbuf++)
17178 {
17179 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17180 if (*charfields++) {
17181 *wbuf = le16_to_cpu(*wbuf);
17182 }
17183 }
17184 return chksum;
17185}
17186
17187/*
17188 * Read EEPROM configuration into the specified buffer.
17189 *
17190 * Return a checksum based on the EEPROM configuration read.
17191 */
17192STATIC ushort __init
17193AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
17194 ADVEEP_38C0800_CONFIG *cfg_buf)
17195{
17196 ushort wval, chksum;
17197 ushort *wbuf;
17198 int eep_addr;
17199 ushort *charfields;
17200
17201 charfields = (ushort *) &ADVEEP_38C0800_Config_Field_IsChar;
17202 wbuf = (ushort *) cfg_buf;
17203 chksum = 0;
17204
17205 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17206 eep_addr < ADV_EEP_DVC_CFG_END;
17207 eep_addr++, wbuf++)
17208 {
17209 wval = AdvReadEEPWord(iop_base, eep_addr);
17210 chksum += wval; /* Checksum is calculated from word values. */
17211 if (*charfields++) {
17212 *wbuf = le16_to_cpu(wval);
17213 } else {
17214 *wbuf = wval;
17215 }
17216 }
17217 /* Read checksum word. */
17218 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17219 wbuf++; charfields++;
17220
17221 /* Read rest of EEPROM not covered by the checksum. */
17222 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17223 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17224 eep_addr++, wbuf++)
17225 {
17226 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17227 if (*charfields++) {
17228 *wbuf = le16_to_cpu(*wbuf);
17229 }
17230 }
17231 return chksum;
17232}
17233
17234/*
17235 * Read EEPROM configuration into the specified buffer.
17236 *
17237 * Return a checksum based on the EEPROM configuration read.
17238 */
17239STATIC ushort __init
17240AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
17241 ADVEEP_38C1600_CONFIG *cfg_buf)
17242{
17243 ushort wval, chksum;
17244 ushort *wbuf;
17245 int eep_addr;
17246 ushort *charfields;
17247
17248 charfields = (ushort*) &ADVEEP_38C1600_Config_Field_IsChar;
17249 wbuf = (ushort *) cfg_buf;
17250 chksum = 0;
17251
17252 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17253 eep_addr < ADV_EEP_DVC_CFG_END;
17254 eep_addr++, wbuf++)
17255 {
17256 wval = AdvReadEEPWord(iop_base, eep_addr);
17257 chksum += wval; /* Checksum is calculated from word values. */
17258 if (*charfields++) {
17259 *wbuf = le16_to_cpu(wval);
17260 } else {
17261 *wbuf = wval;
17262 }
17263 }
17264 /* Read checksum word. */
17265 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17266 wbuf++; charfields++;
17267
17268 /* Read rest of EEPROM not covered by the checksum. */
17269 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17270 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17271 eep_addr++, wbuf++)
17272 {
17273 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17274 if (*charfields++) {
17275 *wbuf = le16_to_cpu(*wbuf);
17276 }
17277 }
17278 return chksum;
17279}
17280
17281/*
17282 * Read the EEPROM from specified location
17283 */
17284STATIC ushort __init
17285AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
17286{
17287 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
17288 ASC_EEP_CMD_READ | eep_word_addr);
17289 AdvWaitEEPCmd(iop_base);
17290 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
17291}
17292
17293/*
17294 * Wait for EEPROM command to complete
17295 */
17296STATIC void __init
17297AdvWaitEEPCmd(AdvPortAddr iop_base)
17298{
17299 int eep_delay_ms;
17300
17301 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++)
17302 {
17303 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE)
17304 {
17305 break;
17306 }
17307 DvcSleepMilliSecond(1);
17308 }
17309 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == 0)
17310 {
17311 ASC_ASSERT(0);
17312 }
17313 return;
17314}
17315
17316/*
17317 * Write the EEPROM from 'cfg_buf'.
17318 */
17319void
17320AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
17321{
17322 ushort *wbuf;
17323 ushort addr, chksum;
17324 ushort *charfields;
17325
17326 wbuf = (ushort *) cfg_buf;
17327 charfields = (ushort *) &ADVEEP_3550_Config_Field_IsChar;
17328 chksum = 0;
17329
17330 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17331 AdvWaitEEPCmd(iop_base);
17332
17333 /*
17334 * Write EEPROM from word 0 to word 20.
17335 */
17336 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17337 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17338 {
17339 ushort word;
17340
17341 if (*charfields++) {
17342 word = cpu_to_le16(*wbuf);
17343 } else {
17344 word = *wbuf;
17345 }
17346 chksum += *wbuf; /* Checksum is calculated from word values. */
17347 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17348 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17349 AdvWaitEEPCmd(iop_base);
17350 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17351 }
17352
17353 /*
17354 * Write EEPROM checksum at word 21.
17355 */
17356 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17357 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17358 AdvWaitEEPCmd(iop_base);
17359 wbuf++; charfields++;
17360
17361 /*
17362 * Write EEPROM OEM name at words 22 to 29.
17363 */
17364 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17365 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17366 {
17367 ushort word;
17368
17369 if (*charfields++) {
17370 word = cpu_to_le16(*wbuf);
17371 } else {
17372 word = *wbuf;
17373 }
17374 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17375 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17376 AdvWaitEEPCmd(iop_base);
17377 }
17378 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17379 AdvWaitEEPCmd(iop_base);
17380 return;
17381}
17382
17383/*
17384 * Write the EEPROM from 'cfg_buf'.
17385 */
17386void
17387AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
17388 ADVEEP_38C0800_CONFIG *cfg_buf)
17389{
17390 ushort *wbuf;
17391 ushort *charfields;
17392 ushort addr, chksum;
17393
17394 wbuf = (ushort *) cfg_buf;
17395 charfields = (ushort *) &ADVEEP_38C0800_Config_Field_IsChar;
17396 chksum = 0;
17397
17398 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17399 AdvWaitEEPCmd(iop_base);
17400
17401 /*
17402 * Write EEPROM from word 0 to word 20.
17403 */
17404 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17405 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17406 {
17407 ushort word;
17408
17409 if (*charfields++) {
17410 word = cpu_to_le16(*wbuf);
17411 } else {
17412 word = *wbuf;
17413 }
17414 chksum += *wbuf; /* Checksum is calculated from word values. */
17415 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17416 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17417 AdvWaitEEPCmd(iop_base);
17418 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17419 }
17420
17421 /*
17422 * Write EEPROM checksum at word 21.
17423 */
17424 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17425 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17426 AdvWaitEEPCmd(iop_base);
17427 wbuf++; charfields++;
17428
17429 /*
17430 * Write EEPROM OEM name at words 22 to 29.
17431 */
17432 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17433 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17434 {
17435 ushort word;
17436
17437 if (*charfields++) {
17438 word = cpu_to_le16(*wbuf);
17439 } else {
17440 word = *wbuf;
17441 }
17442 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17443 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17444 AdvWaitEEPCmd(iop_base);
17445 }
17446 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17447 AdvWaitEEPCmd(iop_base);
17448 return;
17449}
17450
17451/*
17452 * Write the EEPROM from 'cfg_buf'.
17453 */
17454void
17455AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
17456 ADVEEP_38C1600_CONFIG *cfg_buf)
17457{
17458 ushort *wbuf;
17459 ushort *charfields;
17460 ushort addr, chksum;
17461
17462 wbuf = (ushort *) cfg_buf;
17463 charfields = (ushort *) &ADVEEP_38C1600_Config_Field_IsChar;
17464 chksum = 0;
17465
17466 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17467 AdvWaitEEPCmd(iop_base);
17468
17469 /*
17470 * Write EEPROM from word 0 to word 20.
17471 */
17472 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17473 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17474 {
17475 ushort word;
17476
17477 if (*charfields++) {
17478 word = cpu_to_le16(*wbuf);
17479 } else {
17480 word = *wbuf;
17481 }
17482 chksum += *wbuf; /* Checksum is calculated from word values. */
17483 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17484 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17485 AdvWaitEEPCmd(iop_base);
17486 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17487 }
17488
17489 /*
17490 * Write EEPROM checksum at word 21.
17491 */
17492 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17493 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17494 AdvWaitEEPCmd(iop_base);
17495 wbuf++; charfields++;
17496
17497 /*
17498 * Write EEPROM OEM name at words 22 to 29.
17499 */
17500 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17501 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17502 {
17503 ushort word;
17504
17505 if (*charfields++) {
17506 word = cpu_to_le16(*wbuf);
17507 } else {
17508 word = *wbuf;
17509 }
17510 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17511 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17512 AdvWaitEEPCmd(iop_base);
17513 }
17514 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17515 AdvWaitEEPCmd(iop_base);
17516 return;
17517}
17518
17519/* a_advlib.c */
17520/*
17521 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
17522 *
17523 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
17524 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
17525 * RISC to notify it a new command is ready to be executed.
17526 *
17527 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
17528 * set to SCSI_MAX_RETRY.
17529 *
17530 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
17531 * for DMA addresses or math operations are byte swapped to little-endian
17532 * order.
17533 *
17534 * Return:
17535 * ADV_SUCCESS(1) - The request was successfully queued.
17536 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
17537 * request completes.
17538 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
17539 * host IC error.
17540 */
17541STATIC int
17542AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc,
17543 ADV_SCSI_REQ_Q *scsiq)
17544{
17545 ulong last_int_level;
17546 AdvPortAddr iop_base;
17547 ADV_DCNT req_size;
17548 ADV_PADDR req_paddr;
17549 ADV_CARR_T *new_carrp;
17550
17551 ASC_ASSERT(scsiq != NULL); /* 'scsiq' should never be NULL. */
17552
17553 /*
17554 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
17555 */
17556 if (scsiq->target_id > ADV_MAX_TID)
17557 {
17558 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
17559 scsiq->done_status = QD_WITH_ERROR;
17560 return ADV_ERROR;
17561 }
17562
17563 iop_base = asc_dvc->iop_base;
17564
17565 last_int_level = DvcEnterCritical();
17566
17567 /*
17568 * Allocate a carrier ensuring at least one carrier always
17569 * remains on the freelist and initialize fields.
17570 */
17571 if ((new_carrp = asc_dvc->carr_freelist) == NULL)
17572 {
17573 DvcLeaveCritical(last_int_level);
17574 return ADV_BUSY;
17575 }
17576 asc_dvc->carr_freelist = (ADV_CARR_T *)
17577 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
17578 asc_dvc->carr_pending_cnt++;
17579
17580 /*
17581 * Set the carrier to be a stopper by setting 'next_vpa'
17582 * to the stopper value. The current stopper will be changed
17583 * below to point to the new stopper.
17584 */
17585 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
17586
17587 /*
17588 * Clear the ADV_SCSI_REQ_Q done flag.
17589 */
17590 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
17591
17592 req_size = sizeof(ADV_SCSI_REQ_Q);
17593 req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *) scsiq,
17594 (ADV_SDCNT *) &req_size, ADV_IS_SCSIQ_FLAG);
17595
17596 ASC_ASSERT(ADV_32BALIGN(req_paddr) == req_paddr);
17597 ASC_ASSERT(req_size >= sizeof(ADV_SCSI_REQ_Q));
17598
17599 /* Wait for assertion before making little-endian */
17600 req_paddr = cpu_to_le32(req_paddr);
17601
17602 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
17603 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
17604 scsiq->scsiq_rptr = req_paddr;
17605
17606 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
17607 /*
17608 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
17609 * order during initialization.
17610 */
17611 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
17612
17613 /*
17614 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
17615 * the microcode. The newly allocated stopper will become the new
17616 * stopper.
17617 */
17618 asc_dvc->icq_sp->areq_vpa = req_paddr;
17619
17620 /*
17621 * Set the 'next_vpa' pointer for the old stopper to be the
17622 * physical address of the new stopper. The RISC can only
17623 * follow physical addresses.
17624 */
17625 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
17626
17627 /*
17628 * Set the host adapter stopper pointer to point to the new carrier.
17629 */
17630 asc_dvc->icq_sp = new_carrp;
17631
17632 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
17633 asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17634 {
17635 /*
17636 * Tickle the RISC to tell it to read its Command Queue Head pointer.
17637 */
17638 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
17639 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
17640 {
17641 /*
17642 * Clear the tickle value. In the ASC-3550 the RISC flag
17643 * command 'clr_tickle_a' does not work unless the host
17644 * value is cleared.
17645 */
17646 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
17647 }
17648 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17649 {
17650 /*
17651 * Notify the RISC a carrier is ready by writing the physical
17652 * address of the new carrier stopper to the COMMA register.
17653 */
17654 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
17655 le32_to_cpu(new_carrp->carr_pa));
17656 }
17657
17658 DvcLeaveCritical(last_int_level);
17659
17660 return ADV_SUCCESS;
17661}
17662
17663/*
17664 * Reset SCSI Bus and purge all outstanding requests.
17665 *
17666 * Return Value:
17667 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
17668 * ADV_FALSE(0) - Microcode command failed.
17669 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
17670 * may be hung which requires driver recovery.
17671 */
17672STATIC int
17673AdvResetSB(ADV_DVC_VAR *asc_dvc)
17674{
17675 int status;
17676
17677 /*
17678 * Send the SCSI Bus Reset idle start idle command which asserts
17679 * the SCSI Bus Reset signal.
17680 */
17681 status = AdvSendIdleCmd(asc_dvc, (ushort) IDLE_CMD_SCSI_RESET_START, 0L);
17682 if (status != ADV_TRUE)
17683 {
17684 return status;
17685 }
17686
17687 /*
17688 * Delay for the specified SCSI Bus Reset hold time.
17689 *
17690 * The hold time delay is done on the host because the RISC has no
17691 * microsecond accurate timer.
17692 */
17693 DvcDelayMicroSecond(asc_dvc, (ushort) ASC_SCSI_RESET_HOLD_TIME_US);
17694
17695 /*
17696 * Send the SCSI Bus Reset end idle command which de-asserts
17697 * the SCSI Bus Reset signal and purges any pending requests.
17698 */
17699 status = AdvSendIdleCmd(asc_dvc, (ushort) IDLE_CMD_SCSI_RESET_END, 0L);
17700 if (status != ADV_TRUE)
17701 {
17702 return status;
17703 }
17704
17705 DvcSleepMilliSecond((ADV_DCNT) asc_dvc->scsi_reset_wait * 1000);
17706
17707 return status;
17708}
17709
17710/*
17711 * Reset chip and SCSI Bus.
17712 *
17713 * Return Value:
17714 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
17715 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
17716 */
17717STATIC int
17718AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
17719{
17720 int status;
17721 ushort wdtr_able, sdtr_able, tagqng_able;
17722 ushort ppr_able = 0;
17723 uchar tid, max_cmd[ADV_MAX_TID + 1];
17724 AdvPortAddr iop_base;
17725 ushort bios_sig;
17726
17727 iop_base = asc_dvc->iop_base;
17728
17729 /*
17730 * Save current per TID negotiated values.
17731 */
17732 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
17733 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
17734 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17735 {
17736 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
17737 }
17738 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
17739 for (tid = 0; tid <= ADV_MAX_TID; tid++)
17740 {
17741 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
17742 max_cmd[tid]);
17743 }
17744
17745 /*
17746 * Force the AdvInitAsc3550/38C0800Driver() function to
17747 * perform a SCSI Bus Reset by clearing the BIOS signature word.
17748 * The initialization functions assumes a SCSI Bus Reset is not
17749 * needed if the BIOS signature word is present.
17750 */
17751 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
17752 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
17753
17754 /*
17755 * Stop chip and reset it.
17756 */
17757 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
17758 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
17759 DvcSleepMilliSecond(100);
17760 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_WR_IO_REG);
17761
17762 /*
17763 * Reset Adv Library error code, if any, and try
17764 * re-initializing the chip.
17765 */
17766 asc_dvc->err_code = 0;
17767 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17768 {
17769 status = AdvInitAsc38C1600Driver(asc_dvc);
17770 }
17771 else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17772 {
17773 status = AdvInitAsc38C0800Driver(asc_dvc);
17774 } else
17775 {
17776 status = AdvInitAsc3550Driver(asc_dvc);
17777 }
17778
17779 /* Translate initialization return value to status value. */
17780 if (status == 0)
17781 {
17782 status = ADV_TRUE;
17783 } else
17784 {
17785 status = ADV_FALSE;
17786 }
17787
17788 /*
17789 * Restore the BIOS signature word.
17790 */
17791 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
17792
17793 /*
17794 * Restore per TID negotiated values.
17795 */
17796 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
17797 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
17798 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17799 {
17800 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
17801 }
17802 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
17803 for (tid = 0; tid <= ADV_MAX_TID; tid++)
17804 {
17805 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
17806 max_cmd[tid]);
17807 }
17808
17809 return status;
17810}
17811
17812/*
17813 * Adv Library Interrupt Service Routine
17814 *
17815 * This function is called by a driver's interrupt service routine.
17816 * The function disables and re-enables interrupts.
17817 *
17818 * When a microcode idle command is completed, the ADV_DVC_VAR
17819 * 'idle_cmd_done' field is set to ADV_TRUE.
17820 *
17821 * Note: AdvISR() can be called when interrupts are disabled or even
17822 * when there is no hardware interrupt condition present. It will
17823 * always check for completed idle commands and microcode requests.
17824 * This is an important feature that shouldn't be changed because it
17825 * allows commands to be completed from polling mode loops.
17826 *
17827 * Return:
17828 * ADV_TRUE(1) - interrupt was pending
17829 * ADV_FALSE(0) - no interrupt was pending
17830 */
17831STATIC int
17832AdvISR(ADV_DVC_VAR *asc_dvc)
17833{
17834 AdvPortAddr iop_base;
17835 uchar int_stat;
17836 ushort target_bit;
17837 ADV_CARR_T *free_carrp;
17838 ADV_VADDR irq_next_vpa;
17839 int flags;
17840 ADV_SCSI_REQ_Q *scsiq;
17841
17842 flags = DvcEnterCritical();
17843
17844 iop_base = asc_dvc->iop_base;
17845
17846 /* Reading the register clears the interrupt. */
17847 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
17848
17849 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
17850 ADV_INTR_STATUS_INTRC)) == 0)
17851 {
17852 DvcLeaveCritical(flags);
17853 return ADV_FALSE;
17854 }
17855
17856 /*
17857 * Notify the driver of an asynchronous microcode condition by
17858 * calling the ADV_DVC_VAR.async_callback function. The function
17859 * is passed the microcode ASC_MC_INTRB_CODE byte value.
17860 */
17861 if (int_stat & ADV_INTR_STATUS_INTRB)
17862 {
17863 uchar intrb_code;
17864
17865 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
17866
17867 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
17868 asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17869 {
17870 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
17871 asc_dvc->carr_pending_cnt != 0)
17872 {
17873 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
17874 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
17875 {
17876 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
17877 }
17878 }
17879 }
17880
17881 if (asc_dvc->async_callback != 0)
17882 {
17883 (*asc_dvc->async_callback)(asc_dvc, intrb_code);
17884 }
17885 }
17886
17887 /*
17888 * Check if the IRQ stopper carrier contains a completed request.
17889 */
17890 while (((irq_next_vpa =
17891 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0)
17892 {
17893 /*
17894 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
17895 * The RISC will have set 'areq_vpa' to a virtual address.
17896 *
17897 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
17898 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
17899 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
17900 * in AdvExeScsiQueue().
17901 */
17902 scsiq = (ADV_SCSI_REQ_Q *)
17903 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
17904
17905 /*
17906 * Request finished with good status and the queue was not
17907 * DMAed to host memory by the firmware. Set all status fields
17908 * to indicate good status.
17909 */
17910 if ((irq_next_vpa & ASC_RQ_GOOD) != 0)
17911 {
17912 scsiq->done_status = QD_NO_ERROR;
17913 scsiq->host_status = scsiq->scsi_status = 0;
17914 scsiq->data_cnt = 0L;
17915 }
17916
17917 /*
17918 * Advance the stopper pointer to the next carrier
17919 * ignoring the lower four bits. Free the previous
17920 * stopper carrier.
17921 */
17922 free_carrp = asc_dvc->irq_sp;
17923 asc_dvc->irq_sp = (ADV_CARR_T *)
17924 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
17925
17926 free_carrp->next_vpa =
17927 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
17928 asc_dvc->carr_freelist = free_carrp;
17929 asc_dvc->carr_pending_cnt--;
17930
17931 ASC_ASSERT(scsiq != NULL);
17932 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
17933
17934 /*
17935 * Clear request microcode control flag.
17936 */
17937 scsiq->cntl = 0;
17938
17939 /*
17940 * If the command that completed was a SCSI INQUIRY and
17941 * LUN 0 was sent the command, then process the INQUIRY
17942 * command information for the device.
17943 *
17944 * Note: If data returned were either VPD or CmdDt data,
17945 * don't process the INQUIRY command information for
17946 * the device, otherwise may erroneously set *_able bits.
17947 */
17948 if (scsiq->done_status == QD_NO_ERROR &&
17949 scsiq->cdb[0] == INQUIRY &&
17950 scsiq->target_lun == 0 &&
17951 (scsiq->cdb[1] & ADV_INQ_RTN_VPD_AND_CMDDT)
17952 == ADV_INQ_RTN_STD_INQUIRY_DATA)
17953 {
17954 AdvInquiryHandling(asc_dvc, scsiq);
17955 }
17956
17957 /*
17958 * Notify the driver of the completed request by passing
17959 * the ADV_SCSI_REQ_Q pointer to its callback function.
17960 */
17961 scsiq->a_flag |= ADV_SCSIQ_DONE;
17962 (*asc_dvc->isr_callback)(asc_dvc, scsiq);
17963 /*
17964 * Note: After the driver callback function is called, 'scsiq'
17965 * can no longer be referenced.
17966 *
17967 * Fall through and continue processing other completed
17968 * requests...
17969 */
17970
17971 /*
17972 * Disable interrupts again in case the driver inadvertently
17973 * enabled interrupts in its callback function.
17974 *
17975 * The DvcEnterCritical() return value is ignored, because
17976 * the 'flags' saved when AdvISR() was first entered will be
17977 * used to restore the interrupt flag on exit.
17978 */
17979 (void) DvcEnterCritical();
17980 }
17981 DvcLeaveCritical(flags);
17982 return ADV_TRUE;
17983}
17984
17985/*
17986 * Send an idle command to the chip and wait for completion.
17987 *
17988 * Command completion is polled for once per microsecond.
17989 *
17990 * The function can be called from anywhere including an interrupt handler.
17991 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
17992 * functions to prevent reentrancy.
17993 *
17994 * Return Values:
17995 * ADV_TRUE - command completed successfully
17996 * ADV_FALSE - command failed
17997 * ADV_ERROR - command timed out
17998 */
17999STATIC int
18000AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
18001 ushort idle_cmd,
18002 ADV_DCNT idle_cmd_parameter)
18003{
18004 ulong last_int_level;
18005 int result;
18006 ADV_DCNT i, j;
18007 AdvPortAddr iop_base;
18008
18009 last_int_level = DvcEnterCritical();
18010
18011 iop_base = asc_dvc->iop_base;
18012
18013 /*
18014 * Clear the idle command status which is set by the microcode
18015 * to a non-zero value to indicate when the command is completed.
18016 * The non-zero result is one of the IDLE_CMD_STATUS_* values
18017 * defined in a_advlib.h.
18018 */
18019 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort) 0);
18020
18021 /*
18022 * Write the idle command value after the idle command parameter
18023 * has been written to avoid a race condition. If the order is not
18024 * followed, the microcode may process the idle command before the
18025 * parameters have been written to LRAM.
18026 */
18027 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
18028 cpu_to_le32(idle_cmd_parameter));
18029 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
18030
18031 /*
18032 * Tickle the RISC to tell it to process the idle command.
18033 */
18034 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
18035 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
18036 {
18037 /*
18038 * Clear the tickle value. In the ASC-3550 the RISC flag
18039 * command 'clr_tickle_b' does not work unless the host
18040 * value is cleared.
18041 */
18042 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
18043 }
18044
18045 /* Wait for up to 100 millisecond for the idle command to timeout. */
18046 for (i = 0; i < SCSI_WAIT_100_MSEC; i++)
18047 {
18048 /* Poll once each microsecond for command completion. */
18049 for (j = 0; j < SCSI_US_PER_MSEC; j++)
18050 {
18051 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, result);
18052 if (result != 0)
18053 {
18054 DvcLeaveCritical(last_int_level);
18055 return result;
18056 }
18057 DvcDelayMicroSecond(asc_dvc, (ushort) 1);
18058 }
18059 }
18060
18061 ASC_ASSERT(0); /* The idle command should never timeout. */
18062 DvcLeaveCritical(last_int_level);
18063 return ADV_ERROR;
18064}
18065
18066/*
18067 * Inquiry Information Byte 7 Handling
18068 *
18069 * Handle SCSI Inquiry Command information for a device by setting
18070 * microcode operating variables that affect WDTR, SDTR, and Tag
18071 * Queuing.
18072 */
18073STATIC void
18074AdvInquiryHandling(
18075 ADV_DVC_VAR *asc_dvc,
18076 ADV_SCSI_REQ_Q *scsiq)
18077{
18078 AdvPortAddr iop_base;
18079 uchar tid;
18080 ADV_SCSI_INQUIRY *inq;
18081 ushort tidmask;
18082 ushort cfg_word;
18083
18084 /*
18085 * AdvInquiryHandling() requires up to INQUIRY information Byte 7
18086 * to be available.
18087 *
18088 * If less than 8 bytes of INQUIRY information were requested or less
18089 * than 8 bytes were transferred, then return. cdb[4] is the request
18090 * length and the ADV_SCSI_REQ_Q 'data_cnt' field is set by the
18091 * microcode to the transfer residual count.
18092 */
18093
18094 if (scsiq->cdb[4] < 8 ||
18095 (scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) < 8)
18096 {
18097 return;
18098 }
18099
18100 iop_base = asc_dvc->iop_base;
18101 tid = scsiq->target_id;
18102
18103 inq = (ADV_SCSI_INQUIRY *) scsiq->vdata_addr;
18104
18105 /*
18106 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices.
18107 */
18108 if (ADV_INQ_RESPONSE_FMT(inq) < 2 && ADV_INQ_ANSI_VER(inq) < 2)
18109 {
18110 return;
18111 } else
18112 {
18113 /*
18114 * INQUIRY Byte 7 Handling
18115 *
18116 * Use a device's INQUIRY byte 7 to determine whether it
18117 * supports WDTR, SDTR, and Tag Queuing. If the feature
18118 * is enabled in the EEPROM and the device supports the
18119 * feature, then enable it in the microcode.
18120 */
18121
18122 tidmask = ADV_TID_TO_TIDMASK(tid);
18123
18124 /*
18125 * Wide Transfers
18126 *
18127 * If the EEPROM enabled WDTR for the device and the device
18128 * supports wide bus (16 bit) transfers, then turn on the
18129 * device's 'wdtr_able' bit and write the new value to the
18130 * microcode.
18131 */
18132 if ((asc_dvc->wdtr_able & tidmask) && ADV_INQ_WIDE16(inq))
18133 {
18134 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
18135 if ((cfg_word & tidmask) == 0)
18136 {
18137 cfg_word |= tidmask;
18138 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
18139
18140 /*
18141 * Clear the microcode "SDTR negotiation" and "WDTR
18142 * negotiation" done indicators for the target to cause
18143 * it to negotiate with the new setting set above.
18144 * WDTR when accepted causes the target to enter
18145 * asynchronous mode, so SDTR must be negotiated.
18146 */
18147 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18148 cfg_word &= ~tidmask;
18149 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18150 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
18151 cfg_word &= ~tidmask;
18152 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
18153 }
18154 }
18155
18156 /*
18157 * Synchronous Transfers
18158 *
18159 * If the EEPROM enabled SDTR for the device and the device
18160 * supports synchronous transfers, then turn on the device's
18161 * 'sdtr_able' bit. Write the new value to the microcode.
18162 */
18163 if ((asc_dvc->sdtr_able & tidmask) && ADV_INQ_SYNC(inq))
18164 {
18165 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
18166 if ((cfg_word & tidmask) == 0)
18167 {
18168 cfg_word |= tidmask;
18169 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
18170
18171 /*
18172 * Clear the microcode "SDTR negotiation" done indicator
18173 * for the target to cause it to negotiate with the new
18174 * setting set above.
18175 */
18176 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18177 cfg_word &= ~tidmask;
18178 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18179 }
18180 }
18181 /*
18182 * If the Inquiry data included enough space for the SPI-3
18183 * Clocking field, then check if DT mode is supported.
18184 */
18185 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600 &&
18186 (scsiq->cdb[4] >= 57 ||
18187 (scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) >= 57))
18188 {
18189 /*
18190 * PPR (Parallel Protocol Request) Capable
18191 *
18192 * If the device supports DT mode, then it must be PPR capable.
18193 * The PPR message will be used in place of the SDTR and WDTR
18194 * messages to negotiate synchronous speed and offset, transfer
18195 * width, and protocol options.
18196 */
18197 if (ADV_INQ_CLOCKING(inq) & ADV_INQ_CLOCKING_DT_ONLY)
18198 {
18199 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, asc_dvc->ppr_able);
18200 asc_dvc->ppr_able |= tidmask;
18201 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, asc_dvc->ppr_able);
18202 }
18203 }
18204
18205 /*
18206 * If the EEPROM enabled Tag Queuing for the device and the
18207 * device supports Tag Queueing, then turn on the device's
18208 * 'tagqng_enable' bit in the microcode and set the microcode
18209 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng'
18210 * value.
18211 *
18212 * Tag Queuing is disabled for the BIOS which runs in polled
18213 * mode and would see no benefit from Tag Queuing. Also by
18214 * disabling Tag Queuing in the BIOS devices with Tag Queuing
18215 * bugs will at least work with the BIOS.
18216 */
18217 if ((asc_dvc->tagqng_able & tidmask) && ADV_INQ_CMD_QUEUE(inq))
18218 {
18219 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
18220 cfg_word |= tidmask;
18221 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
18222
18223 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
18224 asc_dvc->max_dvc_qng);
18225 }
18226 }
18227}
18228MODULE_LICENSE("Dual BSD/GPL");
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