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1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
87507cfd 43#include <linux/dma-mapping.h>
a9524a76 44#include <linux/device.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4
LT		 47#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
af64371a 51#define DRV_VERSION "1.3"
1da177e4
LT		 52
53
54enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
12fad3f9 59 AHCI_MAX_CMDS = 32,
dd410ff1 60 AHCI_CMD_SZ = 32,
12fad3f9 61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 62 AHCI_RX_FIS_SZ = 256,
a0ea7328 63 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
4b10e559 72 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
78cd52d0 77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 78
79 board_ahci = 0,
bf2af2a2 80 board_ahci_vt8251 = 1,
1da177e4
LT		 81
82 /* global controller registers */
83 HOST_CAP = 0x00, /* host capabilities */
84 HOST_CTL = 0x04, /* global host control */
85 HOST_IRQ_STAT = 0x08, /* interrupt status */
86 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
87 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
88
89 /* HOST_CTL bits */
90 HOST_RESET = (1 << 0), /* reset controller; self-clear */
91 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
92 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
93
94 /* HOST_CAP bits */
22b49985 95 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
979db803 96 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 97 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 98
99 /* registers for each SATA port */
100 PORT_LST_ADDR = 0x00, /* command list DMA addr */
101 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
102 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
103 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
104 PORT_IRQ_STAT = 0x10, /* interrupt status */
105 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
106 PORT_CMD = 0x18, /* port command */
107 PORT_TFDATA = 0x20, /* taskfile data */
108 PORT_SIG = 0x24, /* device TF signature */
109 PORT_CMD_ISSUE = 0x38, /* command issue */
110 PORT_SCR = 0x28, /* SATA phy register block */
111 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
112 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
113 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
114 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
115
116 /* PORT_IRQ_{STAT,MASK} bits */
117 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
118 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
119 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
120 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
121 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
122 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
123 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
124 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
125
126 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
127 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
128 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
129 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
130 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
131 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
132 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
133 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
134 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
135
78cd52d0
TH		 136 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
137 PORT_IRQ_IF_ERR |
138 PORT_IRQ_CONNECT |
4296971d 139 PORT_IRQ_PHYRDY |
78cd52d0
TH		 140 PORT_IRQ_UNK_FIS,
141 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
142 PORT_IRQ_TF_ERR |
143 PORT_IRQ_HBUS_DATA_ERR,
144 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
145 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
146 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 147
148 /* PORT_CMD bits */
02eaa666 149 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 150 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
151 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
152 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 153 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 154 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
155 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
156 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
157
158 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
159 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
160 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4
JG		 161
162 /* hpriv->flags bits */
163 AHCI_FLAG_MSI = (1 << 0),
bf2af2a2
BJ		 164
165 /* ap->flags bits */
166 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
1da177e4
LT		 167};
168
169struct ahci_cmd_hdr {
170 u32 opts;
171 u32 status;
172 u32 tbl_addr;
173 u32 tbl_addr_hi;
174 u32 reserved[4];
175};
176
177struct ahci_sg {
178 u32 addr;
179 u32 addr_hi;
180 u32 reserved;
181 u32 flags_size;
182};
183
184struct ahci_host_priv {
185 unsigned long flags;
186 u32 cap; /* cache of HOST_CAP register */
187 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
188};
189
190struct ahci_port_priv {
191 struct ahci_cmd_hdr *cmd_slot;
192 dma_addr_t cmd_slot_dma;
193 void *cmd_tbl;
194 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 195 void *rx_fis;
196 dma_addr_t rx_fis_dma;
197};
198
199static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
200static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
201static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 202static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4 203static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
1da177e4 204static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 205static int ahci_port_start(struct ata_port *ap);
206static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 207static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
208static void ahci_qc_prep(struct ata_queued_cmd *qc);
209static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 210static void ahci_freeze(struct ata_port *ap);
211static void ahci_thaw(struct ata_port *ap);
212static void ahci_error_handler(struct ata_port *ap);
213static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
907f4678 214static void ahci_remove_one (struct pci_dev *pdev);
1da177e4 215
193515d5 216static struct scsi_host_template ahci_sht = {
1da177e4
LT		 217 .module = THIS_MODULE,
218 .name = DRV_NAME,
219 .ioctl = ata_scsi_ioctl,
220 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 221 .change_queue_depth = ata_scsi_change_queue_depth,
222 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 223 .this_id = ATA_SHT_THIS_ID,
224 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 225 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
226 .emulated = ATA_SHT_EMULATED,
227 .use_clustering = AHCI_USE_CLUSTERING,
228 .proc_name = DRV_NAME,
229 .dma_boundary = AHCI_DMA_BOUNDARY,
230 .slave_configure = ata_scsi_slave_config,
ccf68c34 231 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 232 .bios_param = ata_std_bios_param,
1da177e4
LT		 233};
234
057ace5e 235static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 236 .port_disable = ata_port_disable,
237
238 .check_status = ahci_check_status,
239 .check_altstatus = ahci_check_status,
1da177e4
LT		 240 .dev_select = ata_noop_dev_select,
241
242 .tf_read = ahci_tf_read,
243
1da177e4
LT		 244 .qc_prep = ahci_qc_prep,
245 .qc_issue = ahci_qc_issue,
246
1da177e4
LT		 247 .irq_handler = ahci_interrupt,
248 .irq_clear = ahci_irq_clear,
249
250 .scr_read = ahci_scr_read,
251 .scr_write = ahci_scr_write,
252
78cd52d0
TH		 253 .freeze = ahci_freeze,
254 .thaw = ahci_thaw,
255
256 .error_handler = ahci_error_handler,
257 .post_internal_cmd = ahci_post_internal_cmd,
258
1da177e4
LT		 259 .port_start = ahci_port_start,
260 .port_stop = ahci_port_stop,
1da177e4
LT		 261};
262
98ac62de 263static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 264 /* board_ahci */
265 {
266 .sht = &ahci_sht,
267 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
4296971d
TH		 268 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
269 ATA_FLAG_SKIP_D2H_BSY,
7da79312 270 .pio_mask = 0x1f, /* pio0-4 */
1da177e4
LT		 271 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
272 .port_ops = &ahci_ops,
273 },
bf2af2a2
BJ		 274 /* board_ahci_vt8251 */
275 {
276 .sht = &ahci_sht,
277 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
278 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
4296971d 279 ATA_FLAG_SKIP_D2H_BSY |
bf2af2a2
BJ		 280 AHCI_FLAG_RESET_NEEDS_CLO,
281 .pio_mask = 0x1f, /* pio0-4 */
282 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
283 .port_ops = &ahci_ops,
284 },
1da177e4
LT		 285};
286
3b7d697d 287static const struct pci_device_id ahci_pci_tbl[] = {
1da177e4
LT		 288 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
289 board_ahci }, /* ICH6 */
290 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
291 board_ahci }, /* ICH6M */
292 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
293 board_ahci }, /* ICH7 */
294 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
295 board_ahci }, /* ICH7M */
296 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
297 board_ahci }, /* ICH7R */
298 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
299 board_ahci }, /* ULi M5288 */
680d3235
JG		 300 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
301 board_ahci }, /* ESB2 */
302 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
303 board_ahci }, /* ESB2 */
304 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
305 board_ahci }, /* ESB2 */
3db368f7
JG		 306 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
307 board_ahci }, /* ICH7-M DH */
f285757c
JG		 308 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
309 board_ahci }, /* ICH8 */
310 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
311 board_ahci }, /* ICH8 */
312 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
313 board_ahci }, /* ICH8 */
314 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
315 board_ahci }, /* ICH8M */
316 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
317 board_ahci }, /* ICH8M */
bd12097c
JG		 318 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
319 board_ahci }, /* JMicron JMB360 */
9220a2d0
JG		 320 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
321 board_ahci }, /* JMicron JMB363 */
8b316a39
JG		 322 { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
323 board_ahci }, /* ATI SB600 non-raid */
324 { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
325 board_ahci }, /* ATI SB600 raid */
bf2af2a2
BJ		 326 { PCI_VENDOR_ID_VIA, 0x3349, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
327 board_ahci_vt8251 }, /* VIA VT8251 */
1da177e4
LT		 328 { } /* terminate list */
329};
330
331
332static struct pci_driver ahci_pci_driver = {
333 .name = DRV_NAME,
334 .id_table = ahci_pci_tbl,
335 .probe = ahci_init_one,
907f4678 336 .remove = ahci_remove_one,
1da177e4
LT		 337};
338
339
340static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
341{
342 return base + 0x100 + (port * 0x80);
343}
344
ea6ba10b 345static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
1da177e4 346{
ea6ba10b 347 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
1da177e4
LT		 348}
349
1da177e4
LT		 350static int ahci_port_start(struct ata_port *ap)
351{
352 struct device *dev = ap->host_set->dev;
353 struct ahci_host_priv *hpriv = ap->host_set->private_data;
354 struct ahci_port_priv *pp;
ea6ba10b
JG		 355 void __iomem *mmio = ap->host_set->mmio_base;
356 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
357 void *mem;
1da177e4 358 dma_addr_t mem_dma;
6037d6bb 359 int rc;
1da177e4 360
1da177e4 361 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
0a139e79
TH		 362 if (!pp)
363 return -ENOMEM;
1da177e4
LT		 364 memset(pp, 0, sizeof(*pp));
365
6037d6bb
JG		 366 rc = ata_pad_alloc(ap, dev);
367 if (rc) {
cedc9a47 368 kfree(pp);
6037d6bb 369 return rc;
cedc9a47
JG		 370 }
371
1da177e4
LT		 372 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
373 if (!mem) {
6037d6bb 374 ata_pad_free(ap, dev);
0a139e79
TH		 375 kfree(pp);
376 return -ENOMEM;
1da177e4
LT		 377 }
378 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
379
380 /*
381 * First item in chunk of DMA memory: 32-slot command table,
382 * 32 bytes each in size
383 */
384 pp->cmd_slot = mem;
385 pp->cmd_slot_dma = mem_dma;
386
387 mem += AHCI_CMD_SLOT_SZ;
388 mem_dma += AHCI_CMD_SLOT_SZ;
389
390 /*
391 * Second item: Received-FIS area
392 */
393 pp->rx_fis = mem;
394 pp->rx_fis_dma = mem_dma;
395
396 mem += AHCI_RX_FIS_SZ;
397 mem_dma += AHCI_RX_FIS_SZ;
398
399 /*
400 * Third item: data area for storing a single command
401 * and its scatter-gather table
402 */
403 pp->cmd_tbl = mem;
404 pp->cmd_tbl_dma = mem_dma;
405
1da177e4
LT		 406 ap->private_data = pp;
407
408 if (hpriv->cap & HOST_CAP_64)
409 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
410 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
411 readl(port_mmio + PORT_LST_ADDR); /* flush */
412
413 if (hpriv->cap & HOST_CAP_64)
414 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
415 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
416 readl(port_mmio + PORT_FIS_ADDR); /* flush */
417
418 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
419 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
420 PORT_CMD_START, port_mmio + PORT_CMD);
421 readl(port_mmio + PORT_CMD); /* flush */
422
423 return 0;
1da177e4
LT		 424}
425
426
427static void ahci_port_stop(struct ata_port *ap)
428{
429 struct device *dev = ap->host_set->dev;
430 struct ahci_port_priv *pp = ap->private_data;
ea6ba10b
JG		 431 void __iomem *mmio = ap->host_set->mmio_base;
432 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4
LT		 433 u32 tmp;
434
435 tmp = readl(port_mmio + PORT_CMD);
436 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
437 writel(tmp, port_mmio + PORT_CMD);
438 readl(port_mmio + PORT_CMD); /* flush */
439
440 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
441 * this is slightly incorrect.
442 */
443 msleep(500);
444
445 ap->private_data = NULL;
446 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
447 pp->cmd_slot, pp->cmd_slot_dma);
6037d6bb 448 ata_pad_free(ap, dev);
1da177e4 449 kfree(pp);
1da177e4
LT		 450}
451
452static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
453{
454 unsigned int sc_reg;
455
456 switch (sc_reg_in) {
457 case SCR_STATUS: sc_reg = 0; break;
458 case SCR_CONTROL: sc_reg = 1; break;
459 case SCR_ERROR: sc_reg = 2; break;
460 case SCR_ACTIVE: sc_reg = 3; break;
461 default:
462 return 0xffffffffU;
463 }
464
1e4f2a96 465 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 466}
467
468
469static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
470 u32 val)
471{
472 unsigned int sc_reg;
473
474 switch (sc_reg_in) {
475 case SCR_STATUS: sc_reg = 0; break;
476 case SCR_CONTROL: sc_reg = 1; break;
477 case SCR_ERROR: sc_reg = 2; break;
478 case SCR_ACTIVE: sc_reg = 3; break;
479 default:
480 return;
481 }
482
1e4f2a96 483 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 484}
485
7c76d1e8
TH		 486static int ahci_stop_engine(struct ata_port *ap)
487{
488 void __iomem *mmio = ap->host_set->mmio_base;
489 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
490 int work;
491 u32 tmp;
492
493 tmp = readl(port_mmio + PORT_CMD);
494 tmp &= ~PORT_CMD_START;
495 writel(tmp, port_mmio + PORT_CMD);
496
497 /* wait for engine to stop. TODO: this could be
498 * as long as 500 msec
499 */
500 work = 1000;
501 while (work-- > 0) {
502 tmp = readl(port_mmio + PORT_CMD);
503 if ((tmp & PORT_CMD_LIST_ON) == 0)
504 return 0;
505 udelay(10);
506 }
507
508 return -EIO;
509}
510
511static void ahci_start_engine(struct ata_port *ap)
512{
513 void __iomem *mmio = ap->host_set->mmio_base;
514 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
515 u32 tmp;
516
517 tmp = readl(port_mmio + PORT_CMD);
518 tmp |= PORT_CMD_START;
519 writel(tmp, port_mmio + PORT_CMD);
520 readl(port_mmio + PORT_CMD); /* flush */
521}
522
422b7595 523static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4
LT		 524{
525 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
526 struct ata_taskfile tf;
422b7595
TH		 527 u32 tmp;
528
529 tmp = readl(port_mmio + PORT_SIG);
530 tf.lbah = (tmp >> 24) & 0xff;
531 tf.lbam = (tmp >> 16) & 0xff;
532 tf.lbal = (tmp >> 8) & 0xff;
533 tf.nsect = (tmp) & 0xff;
534
535 return ata_dev_classify(&tf);
536}
537
12fad3f9
TH		 538static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
539 u32 opts)
cc9278ed 540{
12fad3f9
TH		 541 dma_addr_t cmd_tbl_dma;
542
543 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
544
545 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
546 pp->cmd_slot[tag].status = 0;
547 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
548 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 549}
550
bf2af2a2 551static int ahci_clo(struct ata_port *ap)
4658f79b 552{
bf2af2a2 553 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
4658f79b 554 struct ahci_host_priv *hpriv = ap->host_set->private_data;
bf2af2a2
BJ		 555 u32 tmp;
556
557 if (!(hpriv->cap & HOST_CAP_CLO))
558 return -EOPNOTSUPP;
559
560 tmp = readl(port_mmio + PORT_CMD);
561 tmp |= PORT_CMD_CLO;
562 writel(tmp, port_mmio + PORT_CMD);
563
564 tmp = ata_wait_register(port_mmio + PORT_CMD,
565 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
566 if (tmp & PORT_CMD_CLO)
567 return -EIO;
568
569 return 0;
570}
571
4296971d
TH		 572static int ahci_prereset(struct ata_port *ap)
573{
574 if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
575 (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
576 /* ATA_BUSY hasn't cleared, so send a CLO */
577 ahci_clo(ap);
578 }
579
580 return ata_std_prereset(ap);
581}
582
bf2af2a2
BJ		 583static int ahci_softreset(struct ata_port *ap, unsigned int *class)
584{
4658f79b
TH		 585 struct ahci_port_priv *pp = ap->private_data;
586 void __iomem *mmio = ap->host_set->mmio_base;
587 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
588 const u32 cmd_fis_len = 5; /* five dwords */
589 const char *reason = NULL;
590 struct ata_taskfile tf;
75fe1806 591 u32 tmp;
4658f79b
TH		 592 u8 *fis;
593 int rc;
594
595 DPRINTK("ENTER\n");
596
81952c54 597 if (ata_port_offline(ap)) {
c2a65852
TH		 598 DPRINTK("PHY reports no device\n");
599 *class = ATA_DEV_NONE;
600 return 0;
601 }
602
4658f79b
TH		 603 /* prepare for SRST (AHCI-1.1 10.4.1) */
604 rc = ahci_stop_engine(ap);
605 if (rc) {
606 reason = "failed to stop engine";
607 goto fail_restart;
608 }
609
610 /* check BUSY/DRQ, perform Command List Override if necessary */
611 ahci_tf_read(ap, &tf);
612 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
bf2af2a2 613 rc = ahci_clo(ap);
4658f79b 614
bf2af2a2
BJ		 615 if (rc == -EOPNOTSUPP) {
616 reason = "port busy but CLO unavailable";
617 goto fail_restart;
618 } else if (rc) {
619 reason = "port busy but CLO failed";
4658f79b
TH		 620 goto fail_restart;
621 }
622 }
623
624 /* restart engine */
625 ahci_start_engine(ap);
626
3373efd8 627 ata_tf_init(ap->device, &tf);
4658f79b
TH		 628 fis = pp->cmd_tbl;
629
630 /* issue the first D2H Register FIS */
12fad3f9
TH		 631 ahci_fill_cmd_slot(pp, 0,
632 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
4658f79b
TH		 633
634 tf.ctl |= ATA_SRST;
635 ata_tf_to_fis(&tf, fis, 0);
636 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
637
638 writel(1, port_mmio + PORT_CMD_ISSUE);
4658f79b 639
75fe1806
TH		 640 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
641 if (tmp & 0x1) {
4658f79b
TH		 642 rc = -EIO;
643 reason = "1st FIS failed";
644 goto fail;
645 }
646
647 /* spec says at least 5us, but be generous and sleep for 1ms */
648 msleep(1);
649
650 /* issue the second D2H Register FIS */
12fad3f9 651 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
4658f79b
TH		 652
653 tf.ctl &= ~ATA_SRST;
654 ata_tf_to_fis(&tf, fis, 0);
655 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
656
657 writel(1, port_mmio + PORT_CMD_ISSUE);
658 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
659
660 /* spec mandates ">= 2ms" before checking status.
661 * We wait 150ms, because that was the magic delay used for
662 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
663 * between when the ATA command register is written, and then
664 * status is checked. Because waiting for "a while" before
665 * checking status is fine, post SRST, we perform this magic
666 * delay here as well.
667 */
668 msleep(150);
669
670 *class = ATA_DEV_NONE;
81952c54 671 if (ata_port_online(ap)) {
4658f79b
TH		 672 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
673 rc = -EIO;
674 reason = "device not ready";
675 goto fail;
676 }
677 *class = ahci_dev_classify(ap);
678 }
679
680 DPRINTK("EXIT, class=%u\n", *class);
681 return 0;
682
683 fail_restart:
684 ahci_start_engine(ap);
685 fail:
f15a1daf 686 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 687 return rc;
688}
689
2bf2cb26 690static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
422b7595 691{
4296971d
TH		 692 struct ahci_port_priv *pp = ap->private_data;
693 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
694 struct ata_taskfile tf;
4bd00f6a
TH		 695 int rc;
696
697 DPRINTK("ENTER\n");
1da177e4 698
e0bfd149 699 ahci_stop_engine(ap);
4296971d
TH		 700
701 /* clear D2H reception area to properly wait for D2H FIS */
702 ata_tf_init(ap->device, &tf);
703 tf.command = 0xff;
704 ata_tf_to_fis(&tf, d2h_fis, 0);
705
2bf2cb26 706 rc = sata_std_hardreset(ap, class);
4296971d 707
e0bfd149 708 ahci_start_engine(ap);
1da177e4 709
81952c54 710 if (rc == 0 && ata_port_online(ap))
4bd00f6a
TH		 711 *class = ahci_dev_classify(ap);
712 if (*class == ATA_DEV_UNKNOWN)
713 *class = ATA_DEV_NONE;
1da177e4 714
4bd00f6a
TH		 715 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
716 return rc;
717}
718
719static void ahci_postreset(struct ata_port *ap, unsigned int *class)
720{
721 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
722 u32 new_tmp, tmp;
723
724 ata_std_postreset(ap, class);
02eaa666
JG		 725
726 /* Make sure port's ATAPI bit is set appropriately */
727 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 728 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 729 new_tmp |= PORT_CMD_ATAPI;
730 else
731 new_tmp &= ~PORT_CMD_ATAPI;
732 if (new_tmp != tmp) {
733 writel(new_tmp, port_mmio + PORT_CMD);
734 readl(port_mmio + PORT_CMD); /* flush */
735 }
1da177e4
LT		 736}
737
738static u8 ahci_check_status(struct ata_port *ap)
739{
1e4f2a96 740 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4
LT		 741
742 return readl(mmio + PORT_TFDATA) & 0xFF;
743}
744
1da177e4
LT		 745static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
746{
747 struct ahci_port_priv *pp = ap->private_data;
748 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
749
750 ata_tf_from_fis(d2h_fis, tf);
751}
752
12fad3f9 753static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 754{
cedc9a47
JG		 755 struct scatterlist *sg;
756 struct ahci_sg *ahci_sg;
828d09de 757 unsigned int n_sg = 0;
1da177e4
LT		 758
759 VPRINTK("ENTER\n");
760
761 /*
762 * Next, the S/G list.
763 */
12fad3f9 764 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
cedc9a47
JG		 765 ata_for_each_sg(sg, qc) {
766 dma_addr_t addr = sg_dma_address(sg);
767 u32 sg_len = sg_dma_len(sg);
768
769 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
770 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
771 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 772
cedc9a47 773 ahci_sg++;
828d09de 774 n_sg++;
1da177e4 775 }
828d09de
JG		 776
777 return n_sg;
1da177e4
LT		 778}
779
780static void ahci_qc_prep(struct ata_queued_cmd *qc)
781{
a0ea7328
JG		 782 struct ata_port *ap = qc->ap;
783 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 784 int is_atapi = is_atapi_taskfile(&qc->tf);
12fad3f9 785 void *cmd_tbl;
1da177e4
LT		 786 u32 opts;
787 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 788 unsigned int n_elem;
1da177e4 789
1da177e4
LT		 790 /*
791 * Fill in command table information. First, the header,
792 * a SATA Register - Host to Device command FIS.
793 */
12fad3f9
TH		 794 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
795
796 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
cc9278ed 797 if (is_atapi) {
12fad3f9
TH		 798 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
799 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 800 }
1da177e4 801
cc9278ed
TH		 802 n_elem = 0;
803 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 804 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 805
cc9278ed
TH		 806 /*
807 * Fill in command slot information.
808 */
809 opts = cmd_fis_len | n_elem << 16;
810 if (qc->tf.flags & ATA_TFLAG_WRITE)
811 opts |= AHCI_CMD_WRITE;
812 if (is_atapi)
4b10e559 813 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 814
12fad3f9 815 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 816}
817
78cd52d0 818static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 819{
78cd52d0
TH		 820 struct ahci_port_priv *pp = ap->private_data;
821 struct ata_eh_info *ehi = &ap->eh_info;
822 unsigned int err_mask = 0, action = 0;
823 struct ata_queued_cmd *qc;
824 u32 serror;
1da177e4 825
78cd52d0 826 ata_ehi_clear_desc(ehi);
1da177e4 827
78cd52d0
TH		 828 /* AHCI needs SError cleared; otherwise, it might lock up */
829 serror = ahci_scr_read(ap, SCR_ERROR);
830 ahci_scr_write(ap, SCR_ERROR, serror);
1da177e4 831
78cd52d0
TH		 832 /* analyze @irq_stat */
833 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
834
835 if (irq_stat & PORT_IRQ_TF_ERR)
836 err_mask |= AC_ERR_DEV;
837
838 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
839 err_mask |= AC_ERR_HOST_BUS;
840 action |= ATA_EH_SOFTRESET;
1da177e4
LT		 841 }
842
78cd52d0
TH		 843 if (irq_stat & PORT_IRQ_IF_ERR) {
844 err_mask |= AC_ERR_ATA_BUS;
845 action |= ATA_EH_SOFTRESET;
846 ata_ehi_push_desc(ehi, ", interface fatal error");
847 }
1da177e4 848
78cd52d0 849 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
4296971d 850 ata_ehi_hotplugged(ehi);
78cd52d0
TH		 851 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
852 "connection status changed" : "PHY RDY changed");
853 }
854
855 if (irq_stat & PORT_IRQ_UNK_FIS) {
856 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1da177e4 857
78cd52d0
TH		 858 err_mask |= AC_ERR_HSM;
859 action |= ATA_EH_SOFTRESET;
860 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
861 unk[0], unk[1], unk[2], unk[3]);
862 }
1da177e4 863
78cd52d0
TH		 864 /* okay, let's hand over to EH */
865 ehi->serror |= serror;
866 ehi->action |= action;
b8f6153e 867
1da177e4 868 qc = ata_qc_from_tag(ap, ap->active_tag);
78cd52d0
TH		 869 if (qc)
870 qc->err_mask |= err_mask;
871 else
872 ehi->err_mask |= err_mask;
a72ec4ce 873
78cd52d0
TH		 874 if (irq_stat & PORT_IRQ_FREEZE)
875 ata_port_freeze(ap);
876 else
877 ata_port_abort(ap);
1da177e4
LT		 878}
879
78cd52d0 880static void ahci_host_intr(struct ata_port *ap)
1da177e4 881{
ea6ba10b
JG		 882 void __iomem *mmio = ap->host_set->mmio_base;
883 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
12fad3f9
TH		 884 struct ata_eh_info *ehi = &ap->eh_info;
885 u32 status, qc_active;
886 int rc;
1da177e4
LT		 887
888 status = readl(port_mmio + PORT_IRQ_STAT);
889 writel(status, port_mmio + PORT_IRQ_STAT);
890
78cd52d0
TH		 891 if (unlikely(status & PORT_IRQ_ERROR)) {
892 ahci_error_intr(ap, status);
893 return;
1da177e4
LT		 894 }
895
12fad3f9
TH		 896 if (ap->sactive)
897 qc_active = readl(port_mmio + PORT_SCR_ACT);
898 else
899 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
900
901 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
902 if (rc > 0)
903 return;
904 if (rc < 0) {
905 ehi->err_mask |= AC_ERR_HSM;
906 ehi->action |= ATA_EH_SOFTRESET;
907 ata_port_freeze(ap);
908 return;
1da177e4
LT		 909 }
910
2a3917a8
TH		 911 /* hmmm... a spurious interupt */
912
12fad3f9
TH		 913 /* some devices send D2H reg with I bit set during NCQ command phase */
914 if (ap->sactive && status & PORT_IRQ_D2H_REG_FIS)
915 return;
916
2a3917a8
TH		 917 /* ignore interim PIO setup fis interrupts */
918 if (ata_tag_valid(ap->active_tag)) {
919 struct ata_queued_cmd *qc =
920 ata_qc_from_tag(ap, ap->active_tag);
921
922 if (qc && qc->tf.protocol == ATA_PROT_PIO &&
923 (status & PORT_IRQ_PIOS_FIS))
924 return;
925 }
926
78cd52d0
TH		 927 if (ata_ratelimit())
928 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
12fad3f9
TH		 929 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
930 status, ap->active_tag, ap->sactive);
1da177e4
LT		 931}
932
933static void ahci_irq_clear(struct ata_port *ap)
934{
935 /* TODO */
936}
937
12fad3f9 938static irqreturn_t ahci_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1da177e4
LT		 939{
940 struct ata_host_set *host_set = dev_instance;
941 struct ahci_host_priv *hpriv;
942 unsigned int i, handled = 0;
ea6ba10b 943 void __iomem *mmio;
1da177e4
LT		 944 u32 irq_stat, irq_ack = 0;
945
946 VPRINTK("ENTER\n");
947
948 hpriv = host_set->private_data;
949 mmio = host_set->mmio_base;
950
951 /* sigh. 0xffffffff is a valid return from h/w */
952 irq_stat = readl(mmio + HOST_IRQ_STAT);
953 irq_stat &= hpriv->port_map;
954 if (!irq_stat)
955 return IRQ_NONE;
956
957 spin_lock(&host_set->lock);
958
959 for (i = 0; i < host_set->n_ports; i++) {
960 struct ata_port *ap;
1da177e4 961
67846b30
JG		 962 if (!(irq_stat & (1 << i)))
963 continue;
964
1da177e4 965 ap = host_set->ports[i];
67846b30 966 if (ap) {
78cd52d0 967 ahci_host_intr(ap);
67846b30
JG		 968 VPRINTK("port %u\n", i);
969 } else {
970 VPRINTK("port %u (no irq)\n", i);
6971ed1f
TH		 971 if (ata_ratelimit())
972 dev_printk(KERN_WARNING, host_set->dev,
a9524a76 973 "interrupt on disabled port %u\n", i);
1da177e4 974 }
67846b30
JG		 975
976 irq_ack |= (1 << i);
1da177e4
LT		 977 }
978
979 if (irq_ack) {
980 writel(irq_ack, mmio + HOST_IRQ_STAT);
981 handled = 1;
982 }
983
78cd52d0 984 spin_unlock(&host_set->lock);
1da177e4
LT		 985
986 VPRINTK("EXIT\n");
987
988 return IRQ_RETVAL(handled);
989}
990
9a3d9eb0 991static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 992{
993 struct ata_port *ap = qc->ap;
ea6ba10b 994 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4 995
12fad3f9
TH		 996 if (qc->tf.protocol == ATA_PROT_NCQ)
997 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
998 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 999 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1000
1001 return 0;
1002}
1003
78cd52d0
TH		 1004static void ahci_freeze(struct ata_port *ap)
1005{
1006 void __iomem *mmio = ap->host_set->mmio_base;
1007 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1008
1009 /* turn IRQ off */
1010 writel(0, port_mmio + PORT_IRQ_MASK);
1011}
1012
1013static void ahci_thaw(struct ata_port *ap)
1014{
1015 void __iomem *mmio = ap->host_set->mmio_base;
1016 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1017 u32 tmp;
1018
1019 /* clear IRQ */
1020 tmp = readl(port_mmio + PORT_IRQ_STAT);
1021 writel(tmp, port_mmio + PORT_IRQ_STAT);
1022 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1023
1024 /* turn IRQ back on */
1025 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1026}
1027
1028static void ahci_error_handler(struct ata_port *ap)
1029{
1030 if (!(ap->flags & ATA_FLAG_FROZEN)) {
1031 /* restart engine */
1032 ahci_stop_engine(ap);
1033 ahci_start_engine(ap);
1034 }
1035
1036 /* perform recovery */
4296971d 1037 ata_do_eh(ap, ahci_prereset, ahci_softreset, ahci_hardreset,
f5914a46 1038 ahci_postreset);
78cd52d0
TH		 1039}
1040
1041static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1042{
1043 struct ata_port *ap = qc->ap;
1044
1045 if (qc->flags & ATA_QCFLAG_FAILED)
1046 qc->err_mask |= AC_ERR_OTHER;
1047
1048 if (qc->err_mask) {
1049 /* make DMA engine forget about the failed command */
1050 ahci_stop_engine(ap);
1051 ahci_start_engine(ap);
1052 }
1053}
1054
1da177e4
LT		 1055static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1056 unsigned int port_idx)
1057{
1058 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1059 base = ahci_port_base_ul(base, port_idx);
1060 VPRINTK("base now==0x%lx\n", base);
1061
1062 port->cmd_addr = base;
1063 port->scr_addr = base + PORT_SCR;
1064
1065 VPRINTK("EXIT\n");
1066}
1067
1068static int ahci_host_init(struct ata_probe_ent *probe_ent)
1069{
1070 struct ahci_host_priv *hpriv = probe_ent->private_data;
1071 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1072 void __iomem *mmio = probe_ent->mmio_base;
1073 u32 tmp, cap_save;
1da177e4
LT		 1074 unsigned int i, j, using_dac;
1075 int rc;
1076 void __iomem *port_mmio;
1077
1078 cap_save = readl(mmio + HOST_CAP);
1079 cap_save &= ( (1<<28) | (1<<17) );
1080 cap_save |= (1 << 27);
1081
1082 /* global controller reset */
1083 tmp = readl(mmio + HOST_CTL);
1084 if ((tmp & HOST_RESET) == 0) {
1085 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1086 readl(mmio + HOST_CTL); /* flush */
1087 }
1088
1089 /* reset must complete within 1 second, or
1090 * the hardware should be considered fried.
1091 */
1092 ssleep(1);
1093
1094 tmp = readl(mmio + HOST_CTL);
1095 if (tmp & HOST_RESET) {
a9524a76
JG		 1096 dev_printk(KERN_ERR, &pdev->dev,
1097 "controller reset failed (0x%x)\n", tmp);
1da177e4
LT		 1098 return -EIO;
1099 }
1100
1101 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1102 (void) readl(mmio + HOST_CTL); /* flush */
1103 writel(cap_save, mmio + HOST_CAP);
1104 writel(0xf, mmio + HOST_PORTS_IMPL);
1105 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1106
bd12097c
JG		 1107 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1108 u16 tmp16;
1109
1110 pci_read_config_word(pdev, 0x92, &tmp16);
1111 tmp16 |= 0xf;
1112 pci_write_config_word(pdev, 0x92, tmp16);
1113 }
1da177e4
LT		 1114
1115 hpriv->cap = readl(mmio + HOST_CAP);
1116 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1117 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1118
1119 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1120 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1121
1122 using_dac = hpriv->cap & HOST_CAP_64;
1123 if (using_dac &&
1124 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1125 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1126 if (rc) {
1127 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1128 if (rc) {
a9524a76
JG		 1129 dev_printk(KERN_ERR, &pdev->dev,
1130 "64-bit DMA enable failed\n");
1da177e4
LT		 1131 return rc;
1132 }
1133 }
1da177e4
LT		 1134 } else {
1135 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1136 if (rc) {
a9524a76
JG		 1137 dev_printk(KERN_ERR, &pdev->dev,
1138 "32-bit DMA enable failed\n");
1da177e4
LT		 1139 return rc;
1140 }
1141 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1142 if (rc) {
a9524a76
JG		 1143 dev_printk(KERN_ERR, &pdev->dev,
1144 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1145 return rc;
1146 }
1147 }
1148
1149 for (i = 0; i < probe_ent->n_ports; i++) {
1150#if 0 /* BIOSen initialize this incorrectly */
1151 if (!(hpriv->port_map & (1 << i)))
1152 continue;
1153#endif
1154
1155 port_mmio = ahci_port_base(mmio, i);
1156 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1157
1158 ahci_setup_port(&probe_ent->port[i],
1159 (unsigned long) mmio, i);
1160
1161 /* make sure port is not active */
1162 tmp = readl(port_mmio + PORT_CMD);
1163 VPRINTK("PORT_CMD 0x%x\n", tmp);
1164 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1165 PORT_CMD_FIS_RX | PORT_CMD_START)) {
1166 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1167 PORT_CMD_FIS_RX | PORT_CMD_START);
1168 writel(tmp, port_mmio + PORT_CMD);
1169 readl(port_mmio + PORT_CMD); /* flush */
1170
1171 /* spec says 500 msecs for each bit, so
1172 * this is slightly incorrect.
1173 */
1174 msleep(500);
1175 }
1176
1177 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1178
1179 j = 0;
1180 while (j < 100) {
1181 msleep(10);
1182 tmp = readl(port_mmio + PORT_SCR_STAT);
1183 if ((tmp & 0xf) == 0x3)
1184 break;
1185 j++;
1186 }
1187
1188 tmp = readl(port_mmio + PORT_SCR_ERR);
1189 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1190 writel(tmp, port_mmio + PORT_SCR_ERR);
1191
1192 /* ack any pending irq events for this port */
1193 tmp = readl(port_mmio + PORT_IRQ_STAT);
1194 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1195 if (tmp)
1196 writel(tmp, port_mmio + PORT_IRQ_STAT);
1197
1198 writel(1 << i, mmio + HOST_IRQ_STAT);
1da177e4
LT		 1199 }
1200
1201 tmp = readl(mmio + HOST_CTL);
1202 VPRINTK("HOST_CTL 0x%x\n", tmp);
1203 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1204 tmp = readl(mmio + HOST_CTL);
1205 VPRINTK("HOST_CTL 0x%x\n", tmp);
1206
1207 pci_set_master(pdev);
1208
1209 return 0;
1210}
1211
1da177e4
LT		 1212static void ahci_print_info(struct ata_probe_ent *probe_ent)
1213{
1214 struct ahci_host_priv *hpriv = probe_ent->private_data;
1215 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
ea6ba10b 1216 void __iomem *mmio = probe_ent->mmio_base;
1da177e4
LT		 1217 u32 vers, cap, impl, speed;
1218 const char *speed_s;
1219 u16 cc;
1220 const char *scc_s;
1221
1222 vers = readl(mmio + HOST_VERSION);
1223 cap = hpriv->cap;
1224 impl = hpriv->port_map;
1225
1226 speed = (cap >> 20) & 0xf;
1227 if (speed == 1)
1228 speed_s = "1.5";
1229 else if (speed == 2)
1230 speed_s = "3";
1231 else
1232 speed_s = "?";
1233
1234 pci_read_config_word(pdev, 0x0a, &cc);
1235 if (cc == 0x0101)
1236 scc_s = "IDE";
1237 else if (cc == 0x0106)
1238 scc_s = "SATA";
1239 else if (cc == 0x0104)
1240 scc_s = "RAID";
1241 else
1242 scc_s = "unknown";
1243
a9524a76
JG		 1244 dev_printk(KERN_INFO, &pdev->dev,
1245 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1246 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1247 ,
1da177e4
LT		 1248
1249 (vers >> 24) & 0xff,
1250 (vers >> 16) & 0xff,
1251 (vers >> 8) & 0xff,
1252 vers & 0xff,
1253
1254 ((cap >> 8) & 0x1f) + 1,
1255 (cap & 0x1f) + 1,
1256 speed_s,
1257 impl,
1258 scc_s);
1259
a9524a76
JG		 1260 dev_printk(KERN_INFO, &pdev->dev,
1261 "flags: "
1da177e4
LT		 1262 "%s%s%s%s%s%s"
1263 "%s%s%s%s%s%s%s\n"
1264 ,
1da177e4
LT		 1265
1266 cap & (1 << 31) ? "64bit " : "",
1267 cap & (1 << 30) ? "ncq " : "",
1268 cap & (1 << 28) ? "ilck " : "",
1269 cap & (1 << 27) ? "stag " : "",
1270 cap & (1 << 26) ? "pm " : "",
1271 cap & (1 << 25) ? "led " : "",
1272
1273 cap & (1 << 24) ? "clo " : "",
1274 cap & (1 << 19) ? "nz " : "",
1275 cap & (1 << 18) ? "only " : "",
1276 cap & (1 << 17) ? "pmp " : "",
1277 cap & (1 << 15) ? "pio " : "",
1278 cap & (1 << 14) ? "slum " : "",
1279 cap & (1 << 13) ? "part " : ""
1280 );
1281}
1282
1283static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1284{
1285 static int printed_version;
1286 struct ata_probe_ent *probe_ent = NULL;
1287 struct ahci_host_priv *hpriv;
1288 unsigned long base;
ea6ba10b 1289 void __iomem *mmio_base;
1da177e4 1290 unsigned int board_idx = (unsigned int) ent->driver_data;
907f4678 1291 int have_msi, pci_dev_busy = 0;
1da177e4
LT		 1292 int rc;
1293
1294 VPRINTK("ENTER\n");
1295
12fad3f9
TH		 1296 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1297
1da177e4 1298 if (!printed_version++)
a9524a76 1299 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4
LT		 1300
1301 rc = pci_enable_device(pdev);
1302 if (rc)
1303 return rc;
1304
1305 rc = pci_request_regions(pdev, DRV_NAME);
1306 if (rc) {
1307 pci_dev_busy = 1;
1308 goto err_out;
1309 }
1310
907f4678
JG		 1311 if (pci_enable_msi(pdev) == 0)
1312 have_msi = 1;
1313 else {
1314 pci_intx(pdev, 1);
1315 have_msi = 0;
1316 }
1da177e4
LT		 1317
1318 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1319 if (probe_ent == NULL) {
1320 rc = -ENOMEM;
907f4678 1321 goto err_out_msi;
1da177e4
LT		 1322 }
1323
1324 memset(probe_ent, 0, sizeof(*probe_ent));
1325 probe_ent->dev = pci_dev_to_dev(pdev);
1326 INIT_LIST_HEAD(&probe_ent->node);
1327
374b1873 1328 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1da177e4
LT		 1329 if (mmio_base == NULL) {
1330 rc = -ENOMEM;
1331 goto err_out_free_ent;
1332 }
1333 base = (unsigned long) mmio_base;
1334
1335 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1336 if (!hpriv) {
1337 rc = -ENOMEM;
1338 goto err_out_iounmap;
1339 }
1340 memset(hpriv, 0, sizeof(*hpriv));
1341
1342 probe_ent->sht = ahci_port_info[board_idx].sht;
1343 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1344 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1345 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1346 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1347
1348 probe_ent->irq = pdev->irq;
1349 probe_ent->irq_flags = SA_SHIRQ;
1350 probe_ent->mmio_base = mmio_base;
1351 probe_ent->private_data = hpriv;
1352
4b0060f4
JG		 1353 if (have_msi)
1354 hpriv->flags |= AHCI_FLAG_MSI;
907f4678 1355
bd12097c
JG		 1356 /* JMicron-specific fixup: make sure we're in AHCI mode */
1357 if (pdev->vendor == 0x197b)
1358 pci_write_config_byte(pdev, 0x41, 0xa1);
1359
1da177e4
LT		 1360 /* initialize adapter */
1361 rc = ahci_host_init(probe_ent);
1362 if (rc)
1363 goto err_out_hpriv;
1364
12fad3f9
TH		 1365 if (hpriv->cap & HOST_CAP_NCQ)
1366 probe_ent->host_flags |= ATA_FLAG_NCQ;
1367
1da177e4
LT		 1368 ahci_print_info(probe_ent);
1369
1370 /* FIXME: check ata_device_add return value */
1371 ata_device_add(probe_ent);
1372 kfree(probe_ent);
1373
1374 return 0;
1375
1376err_out_hpriv:
1377 kfree(hpriv);
1378err_out_iounmap:
374b1873 1379 pci_iounmap(pdev, mmio_base);
1da177e4
LT		 1380err_out_free_ent:
1381 kfree(probe_ent);
907f4678
JG		 1382err_out_msi:
1383 if (have_msi)
1384 pci_disable_msi(pdev);
1385 else
1386 pci_intx(pdev, 0);
1da177e4
LT		 1387 pci_release_regions(pdev);
1388err_out:
1389 if (!pci_dev_busy)
1390 pci_disable_device(pdev);
1391 return rc;
1392}
1393
907f4678
JG		 1394static void ahci_remove_one (struct pci_dev *pdev)
1395{
1396 struct device *dev = pci_dev_to_dev(pdev);
1397 struct ata_host_set *host_set = dev_get_drvdata(dev);
1398 struct ahci_host_priv *hpriv = host_set->private_data;
907f4678
JG		 1399 unsigned int i;
1400 int have_msi;
1401
720ba126
TH		 1402 for (i = 0; i < host_set->n_ports; i++)
1403 ata_port_detach(host_set->ports[i]);
907f4678 1404
4b0060f4 1405 have_msi = hpriv->flags & AHCI_FLAG_MSI;
907f4678 1406 free_irq(host_set->irq, host_set);
907f4678
JG		 1407
1408 for (i = 0; i < host_set->n_ports; i++) {
720ba126 1409 struct ata_port *ap = host_set->ports[i];
907f4678
JG		 1410
1411 ata_scsi_release(ap->host);
1412 scsi_host_put(ap->host);
1413 }
1414
e005f01d 1415 kfree(hpriv);
374b1873 1416 pci_iounmap(pdev, host_set->mmio_base);
ead5de99
JG		 1417 kfree(host_set);
1418
907f4678
JG		 1419 if (have_msi)
1420 pci_disable_msi(pdev);
1421 else
1422 pci_intx(pdev, 0);
1423 pci_release_regions(pdev);
907f4678
JG		 1424 pci_disable_device(pdev);
1425 dev_set_drvdata(dev, NULL);
1426}
1da177e4
LT		 1427
1428static int __init ahci_init(void)
1429{
1430 return pci_module_init(&ahci_pci_driver);
1431}
1432
1da177e4
LT		 1433static void __exit ahci_exit(void)
1434{
1435 pci_unregister_driver(&ahci_pci_driver);
1436}
1437
1438
1439MODULE_AUTHOR("Jeff Garzik");
1440MODULE_DESCRIPTION("AHCI SATA low-level driver");
1441MODULE_LICENSE("GPL");
1442MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1443MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1444
1445module_init(ahci_init);
1446module_exit(ahci_exit);
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