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scsi: aic7xxx: Adjust indentation in ahc_find_syncrate
[mirror_ubuntu-hirsute-kernel.git] / drivers / scsi / aic7xxx / aic7xxx_core.c
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1da177e4
LT		 1/*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
79778a27 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
1da177e4
LT		 41 */
42
1da177e4
LT		 43#include "aic7xxx_osm.h"
44#include "aic7xxx_inline.h"
45#include "aicasm/aicasm_insformat.h"
1da177e4 46
1da177e4 47/***************************** Lookup Tables **********************************/
d1d7b19d 48static const char *const ahc_chip_names[] = {
1da177e4
LT		 49 "NONE",
50 "aic7770",
51 "aic7850",
52 "aic7855",
53 "aic7859",
54 "aic7860",
55 "aic7870",
56 "aic7880",
57 "aic7895",
58 "aic7895C",
59 "aic7890/91",
60 "aic7896/97",
61 "aic7892",
62 "aic7899"
63};
1da177e4
LT		 64
65/*
66 * Hardware error codes.
67 */
68struct ahc_hard_error_entry {
69 uint8_t errno;
d1d7b19d 70 const char *errmesg;
1da177e4
LT		 71};
72
d1d7b19d 73static const struct ahc_hard_error_entry ahc_hard_errors[] = {
1da177e4 74 { ILLHADDR, "Illegal Host Access" },
5f367f02 75 { ILLSADDR, "Illegal Sequencer Address referenced" },
1da177e4
LT		 76 { ILLOPCODE, "Illegal Opcode in sequencer program" },
77 { SQPARERR, "Sequencer Parity Error" },
78 { DPARERR, "Data-path Parity Error" },
79 { MPARERR, "Scratch or SCB Memory Parity Error" },
80 { PCIERRSTAT, "PCI Error detected" },
81 { CIOPARERR, "CIOBUS Parity Error" },
82};
6391a113 83static const u_int num_errors = ARRAY_SIZE(ahc_hard_errors);
1da177e4 84
d1d7b19d 85static const struct ahc_phase_table_entry ahc_phase_table[] =
1da177e4
LT		 86{
87 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
88 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
89 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
90 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
91 { P_COMMAND, MSG_NOOP, "in Command phase" },
92 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
93 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
94 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
95 { P_BUSFREE, MSG_NOOP, "while idle" },
96 { 0, MSG_NOOP, "in unknown phase" }
97};
98
99/*
100 * In most cases we only wish to itterate over real phases, so
101 * exclude the last element from the count.
102 */
6391a113 103static const u_int num_phases = ARRAY_SIZE(ahc_phase_table) - 1;
1da177e4
LT		 104
105/*
106 * Valid SCSIRATE values. (p. 3-17)
107 * Provides a mapping of tranfer periods in ns to the proper value to
108 * stick in the scsixfer reg.
109 */
d1d7b19d 110static const struct ahc_syncrate ahc_syncrates[] =
1da177e4
LT		 111{
112 /* ultra2 fast/ultra period rate */
113 { 0x42, 0x000, 9, "80.0" },
114 { 0x03, 0x000, 10, "40.0" },
115 { 0x04, 0x000, 11, "33.0" },
116 { 0x05, 0x100, 12, "20.0" },
117 { 0x06, 0x110, 15, "16.0" },
118 { 0x07, 0x120, 18, "13.4" },
119 { 0x08, 0x000, 25, "10.0" },
120 { 0x19, 0x010, 31, "8.0" },
121 { 0x1a, 0x020, 37, "6.67" },
122 { 0x1b, 0x030, 43, "5.7" },
123 { 0x1c, 0x040, 50, "5.0" },
124 { 0x00, 0x050, 56, "4.4" },
125 { 0x00, 0x060, 62, "4.0" },
126 { 0x00, 0x070, 68, "3.6" },
127 { 0x00, 0x000, 0, NULL }
128};
129
130/* Our Sequencer Program */
131#include "aic7xxx_seq.h"
132
133/**************************** Function Declarations ***************************/
134static void ahc_force_renegotiation(struct ahc_softc *ahc,
135 struct ahc_devinfo *devinfo);
136static struct ahc_tmode_tstate*
137 ahc_alloc_tstate(struct ahc_softc *ahc,
138 u_int scsi_id, char channel);
139#ifdef AHC_TARGET_MODE
140static void ahc_free_tstate(struct ahc_softc *ahc,
141 u_int scsi_id, char channel, int force);
142#endif
d1d7b19d 143static const struct ahc_syncrate*
1da177e4
LT		 144 ahc_devlimited_syncrate(struct ahc_softc *ahc,
145 struct ahc_initiator_tinfo *,
146 u_int *period,
147 u_int *ppr_options,
148 role_t role);
149static void ahc_update_pending_scbs(struct ahc_softc *ahc);
150static void ahc_fetch_devinfo(struct ahc_softc *ahc,
151 struct ahc_devinfo *devinfo);
152static void ahc_scb_devinfo(struct ahc_softc *ahc,
153 struct ahc_devinfo *devinfo,
154 struct scb *scb);
155static void ahc_assert_atn(struct ahc_softc *ahc);
156static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
157 struct ahc_devinfo *devinfo,
158 struct scb *scb);
159static void ahc_build_transfer_msg(struct ahc_softc *ahc,
160 struct ahc_devinfo *devinfo);
161static void ahc_construct_sdtr(struct ahc_softc *ahc,
162 struct ahc_devinfo *devinfo,
163 u_int period, u_int offset);
164static void ahc_construct_wdtr(struct ahc_softc *ahc,
165 struct ahc_devinfo *devinfo,
166 u_int bus_width);
167static void ahc_construct_ppr(struct ahc_softc *ahc,
168 struct ahc_devinfo *devinfo,
169 u_int period, u_int offset,
170 u_int bus_width, u_int ppr_options);
171static void ahc_clear_msg_state(struct ahc_softc *ahc);
172static void ahc_handle_proto_violation(struct ahc_softc *ahc);
173static void ahc_handle_message_phase(struct ahc_softc *ahc);
174typedef enum {
175 AHCMSG_1B,
176 AHCMSG_2B,
177 AHCMSG_EXT
178} ahc_msgtype;
179static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
180 u_int msgval, int full);
181static int ahc_parse_msg(struct ahc_softc *ahc,
182 struct ahc_devinfo *devinfo);
183static int ahc_handle_msg_reject(struct ahc_softc *ahc,
184 struct ahc_devinfo *devinfo);
185static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
186 struct ahc_devinfo *devinfo);
187static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
188static void ahc_handle_devreset(struct ahc_softc *ahc,
189 struct ahc_devinfo *devinfo,
190 cam_status status, char *message,
191 int verbose_level);
192#ifdef AHC_TARGET_MODE
193static void ahc_setup_target_msgin(struct ahc_softc *ahc,
194 struct ahc_devinfo *devinfo,
195 struct scb *scb);
196#endif
197
198static bus_dmamap_callback_t ahc_dmamap_cb;
d1d7b19d
DV		 199static void ahc_build_free_scb_list(struct ahc_softc *ahc);
200static int ahc_init_scbdata(struct ahc_softc *ahc);
201static void ahc_fini_scbdata(struct ahc_softc *ahc);
1da177e4
LT		 202static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
203 struct scb *prev_scb,
204 struct scb *scb);
205static int ahc_qinfifo_count(struct ahc_softc *ahc);
206static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
207 u_int prev, u_int scbptr);
208static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
209static u_int ahc_rem_wscb(struct ahc_softc *ahc,
210 u_int scbpos, u_int prev);
211static void ahc_reset_current_bus(struct ahc_softc *ahc);
212#ifdef AHC_DUMP_SEQ
213static void ahc_dumpseq(struct ahc_softc *ahc);
214#endif
215static int ahc_loadseq(struct ahc_softc *ahc);
216static int ahc_check_patch(struct ahc_softc *ahc,
980b306a 217 const struct patch **start_patch,
1da177e4
LT		 218 u_int start_instr, u_int *skip_addr);
219static void ahc_download_instr(struct ahc_softc *ahc,
220 u_int instrptr, uint8_t *dconsts);
221#ifdef AHC_TARGET_MODE
222static void ahc_queue_lstate_event(struct ahc_softc *ahc,
223 struct ahc_tmode_lstate *lstate,
224 u_int initiator_id,
225 u_int event_type,
226 u_int event_arg);
227static void ahc_update_scsiid(struct ahc_softc *ahc,
228 u_int targid_mask);
229static int ahc_handle_target_cmd(struct ahc_softc *ahc,
230 struct target_cmd *cmd);
231#endif
be0d6768 232
d1d7b19d
DV		 233static u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl);
234static void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl);
235static void ahc_busy_tcl(struct ahc_softc *ahc,
236 u_int tcl, u_int busyid);
237
238/************************** SCB and SCB queue management **********************/
239static void ahc_run_untagged_queues(struct ahc_softc *ahc);
240static void ahc_run_untagged_queue(struct ahc_softc *ahc,
241 struct scb_tailq *queue);
242
243/****************************** Initialization ********************************/
244static void ahc_alloc_scbs(struct ahc_softc *ahc);
245static void ahc_shutdown(void *arg);
246
247/*************************** Interrupt Services *******************************/
248static void ahc_clear_intstat(struct ahc_softc *ahc);
249static void ahc_run_qoutfifo(struct ahc_softc *ahc);
250#ifdef AHC_TARGET_MODE
251static void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused);
252#endif
253static void ahc_handle_brkadrint(struct ahc_softc *ahc);
254static void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat);
255static void ahc_handle_scsiint(struct ahc_softc *ahc,
256 u_int intstat);
257static void ahc_clear_critical_section(struct ahc_softc *ahc);
258
259/***************************** Error Recovery *********************************/
260static void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb);
261static int ahc_abort_scbs(struct ahc_softc *ahc, int target,
262 char channel, int lun, u_int tag,
263 role_t role, uint32_t status);
264static void ahc_calc_residual(struct ahc_softc *ahc,
265 struct scb *scb);
266
267/*********************** Untagged Transaction Routines ************************/
268static inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc);
269static inline void ahc_release_untagged_queues(struct ahc_softc *ahc);
270
271/*
272 * Block our completion routine from starting the next untagged
273 * transaction for this target or target lun.
274 */
275static inline void
276ahc_freeze_untagged_queues(struct ahc_softc *ahc)
277{
278 if ((ahc->flags & AHC_SCB_BTT) == 0)
279 ahc->untagged_queue_lock++;
280}
281
282/*
283 * Allow the next untagged transaction for this target or target lun
284 * to be executed. We use a counting semaphore to allow the lock
285 * to be acquired recursively. Once the count drops to zero, the
286 * transaction queues will be run.
287 */
288static inline void
289ahc_release_untagged_queues(struct ahc_softc *ahc)
290{
291 if ((ahc->flags & AHC_SCB_BTT) == 0) {
292 ahc->untagged_queue_lock--;
293 if (ahc->untagged_queue_lock == 0)
294 ahc_run_untagged_queues(ahc);
295 }
296}
297
be0d6768
DV		 298/************************* Sequencer Execution Control ************************/
299/*
300 * Work around any chip bugs related to halting sequencer execution.
301 * On Ultra2 controllers, we must clear the CIOBUS stretch signal by
302 * reading a register that will set this signal and deassert it.
303 * Without this workaround, if the chip is paused, by an interrupt or
304 * manual pause while accessing scb ram, accesses to certain registers
305 * will hang the system (infinite pci retries).
306 */
d1d7b19d 307static void
be0d6768
DV		 308ahc_pause_bug_fix(struct ahc_softc *ahc)
309{
310 if ((ahc->features & AHC_ULTRA2) != 0)
311 (void)ahc_inb(ahc, CCSCBCTL);
312}
313
314/*
315 * Determine whether the sequencer has halted code execution.
316 * Returns non-zero status if the sequencer is stopped.
317 */
318int
319ahc_is_paused(struct ahc_softc *ahc)
320{
321 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
322}
323
324/*
325 * Request that the sequencer stop and wait, indefinitely, for it
326 * to stop. The sequencer will only acknowledge that it is paused
327 * once it has reached an instruction boundary and PAUSEDIS is
328 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
329 * for critical sections.
330 */
331void
332ahc_pause(struct ahc_softc *ahc)
333{
334 ahc_outb(ahc, HCNTRL, ahc->pause);
335
336 /*
337 * Since the sequencer can disable pausing in a critical section, we
338 * must loop until it actually stops.
339 */
340 while (ahc_is_paused(ahc) == 0)
341 ;
342
343 ahc_pause_bug_fix(ahc);
344}
345
346/*
347 * Allow the sequencer to continue program execution.
348 * We check here to ensure that no additional interrupt
349 * sources that would cause the sequencer to halt have been
350 * asserted. If, for example, a SCSI bus reset is detected
351 * while we are fielding a different, pausing, interrupt type,
352 * we don't want to release the sequencer before going back
353 * into our interrupt handler and dealing with this new
354 * condition.
355 */
356void
357ahc_unpause(struct ahc_softc *ahc)
358{
359 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
360 ahc_outb(ahc, HCNTRL, ahc->unpause);
361}
362
363/************************** Memory mapping routines ***************************/
d1d7b19d 364static struct ahc_dma_seg *
be0d6768
DV		 365ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)
366{
367 int sg_index;
368
369 sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg);
370 /* sg_list_phys points to entry 1, not 0 */
371 sg_index++;
372
373 return (&scb->sg_list[sg_index]);
374}
375
d1d7b19d 376static uint32_t
be0d6768
DV		 377ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg)
378{
379 int sg_index;
380
381 /* sg_list_phys points to entry 1, not 0 */
382 sg_index = sg - &scb->sg_list[1];
383
384 return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list)));
385}
386
d1d7b19d 387static uint32_t
be0d6768
DV		 388ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
389{
390 return (ahc->scb_data->hscb_busaddr
391 + (sizeof(struct hardware_scb) * index));
392}
393
d1d7b19d 394static void
be0d6768
DV		 395ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op)
396{
397 ahc_dmamap_sync(ahc, ahc->scb_data->hscb_dmat,
398 ahc->scb_data->hscb_dmamap,
399 /*offset*/(scb->hscb - ahc->hscbs) * sizeof(*scb->hscb),
400 /*len*/sizeof(*scb->hscb), op);
401}
402
403void
404ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op)
405{
406 if (scb->sg_count == 0)
407 return;
408
409 ahc_dmamap_sync(ahc, ahc->scb_data->sg_dmat, scb->sg_map->sg_dmamap,
410 /*offset*/(scb->sg_list - scb->sg_map->sg_vaddr)
411 * sizeof(struct ahc_dma_seg),
412 /*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op);
413}
414
d1d7b19d
DV		 415#ifdef AHC_TARGET_MODE
416static uint32_t
be0d6768
DV		 417ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index)
418{
419 return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo);
420}
d1d7b19d 421#endif
be0d6768 422
25985edc 423/*********************** Miscellaneous Support Functions ***********************/
be0d6768
DV		 424/*
425 * Determine whether the sequencer reported a residual
426 * for this SCB/transaction.
427 */
d1d7b19d 428static void
be0d6768
DV		 429ahc_update_residual(struct ahc_softc *ahc, struct scb *scb)
430{
431 uint32_t sgptr;
432
433 sgptr = ahc_le32toh(scb->hscb->sgptr);
434 if ((sgptr & SG_RESID_VALID) != 0)
435 ahc_calc_residual(ahc, scb);
436}
437
438/*
439 * Return pointers to the transfer negotiation information
440 * for the specified our_id/remote_id pair.
441 */
442struct ahc_initiator_tinfo *
443ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
444 u_int remote_id, struct ahc_tmode_tstate **tstate)
445{
446 /*
447 * Transfer data structures are stored from the perspective
448 * of the target role. Since the parameters for a connection
449 * in the initiator role to a given target are the same as
450 * when the roles are reversed, we pretend we are the target.
451 */
452 if (channel == 'B')
453 our_id += 8;
454 *tstate = ahc->enabled_targets[our_id];
455 return (&(*tstate)->transinfo[remote_id]);
456}
457
458uint16_t
459ahc_inw(struct ahc_softc *ahc, u_int port)
460{
461 uint16_t r = ahc_inb(ahc, port+1) << 8;
462 return r | ahc_inb(ahc, port);
463}
464
465void
466ahc_outw(struct ahc_softc *ahc, u_int port, u_int value)
467{
468 ahc_outb(ahc, port, value & 0xFF);
469 ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
470}
471
472uint32_t
473ahc_inl(struct ahc_softc *ahc, u_int port)
474{
475 return ((ahc_inb(ahc, port))
476 | (ahc_inb(ahc, port+1) << 8)
477 | (ahc_inb(ahc, port+2) << 16)
478 | (ahc_inb(ahc, port+3) << 24));
479}
480
481void
482ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value)
483{
484 ahc_outb(ahc, port, (value) & 0xFF);
485 ahc_outb(ahc, port+1, ((value) >> 8) & 0xFF);
486 ahc_outb(ahc, port+2, ((value) >> 16) & 0xFF);
487 ahc_outb(ahc, port+3, ((value) >> 24) & 0xFF);
488}
489
490uint64_t
491ahc_inq(struct ahc_softc *ahc, u_int port)
492{
493 return ((ahc_inb(ahc, port))
494 | (ahc_inb(ahc, port+1) << 8)
495 | (ahc_inb(ahc, port+2) << 16)
496 | (ahc_inb(ahc, port+3) << 24)
497 | (((uint64_t)ahc_inb(ahc, port+4)) << 32)
498 | (((uint64_t)ahc_inb(ahc, port+5)) << 40)
499 | (((uint64_t)ahc_inb(ahc, port+6)) << 48)
500 | (((uint64_t)ahc_inb(ahc, port+7)) << 56));
501}
502
503void
504ahc_outq(struct ahc_softc *ahc, u_int port, uint64_t value)
505{
506 ahc_outb(ahc, port, value & 0xFF);
507 ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
508 ahc_outb(ahc, port+2, (value >> 16) & 0xFF);
509 ahc_outb(ahc, port+3, (value >> 24) & 0xFF);
510 ahc_outb(ahc, port+4, (value >> 32) & 0xFF);
511 ahc_outb(ahc, port+5, (value >> 40) & 0xFF);
512 ahc_outb(ahc, port+6, (value >> 48) & 0xFF);
513 ahc_outb(ahc, port+7, (value >> 56) & 0xFF);
514}
515
516/*
517 * Get a free scb. If there are none, see if we can allocate a new SCB.
518 */
519struct scb *
520ahc_get_scb(struct ahc_softc *ahc)
521{
522 struct scb *scb;
523
524 if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL) {
525 ahc_alloc_scbs(ahc);
526 scb = SLIST_FIRST(&ahc->scb_data->free_scbs);
527 if (scb == NULL)
528 return (NULL);
529 }
530 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle);
531 return (scb);
532}
533
534/*
535 * Return an SCB resource to the free list.
536 */
537void
538ahc_free_scb(struct ahc_softc *ahc, struct scb *scb)
539{
540 struct hardware_scb *hscb;
541
542 hscb = scb->hscb;
543 /* Clean up for the next user */
544 ahc->scb_data->scbindex[hscb->tag] = NULL;
545 scb->flags = SCB_FREE;
546 hscb->control = 0;
547
548 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle);
549
550 /* Notify the OSM that a resource is now available. */
551 ahc_platform_scb_free(ahc, scb);
552}
553
554struct scb *
555ahc_lookup_scb(struct ahc_softc *ahc, u_int tag)
556{
557 struct scb* scb;
558
559 scb = ahc->scb_data->scbindex[tag];
560 if (scb != NULL)
561 ahc_sync_scb(ahc, scb,
562 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
563 return (scb);
564}
565
d1d7b19d 566static void
be0d6768
DV		 567ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb)
568{
569 struct hardware_scb *q_hscb;
570 u_int saved_tag;
571
572 /*
573 * Our queuing method is a bit tricky. The card
574 * knows in advance which HSCB to download, and we
575 * can't disappoint it. To achieve this, the next
576 * SCB to download is saved off in ahc->next_queued_scb.
577 * When we are called to queue "an arbitrary scb",
578 * we copy the contents of the incoming HSCB to the one
579 * the sequencer knows about, swap HSCB pointers and
580 * finally assign the SCB to the tag indexed location
581 * in the scb_array. This makes sure that we can still
582 * locate the correct SCB by SCB_TAG.
583 */
584 q_hscb = ahc->next_queued_scb->hscb;
585 saved_tag = q_hscb->tag;
586 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
587 if ((scb->flags & SCB_CDB32_PTR) != 0) {
588 q_hscb->shared_data.cdb_ptr =
589 ahc_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag)
590 + offsetof(struct hardware_scb, cdb32));
591 }
592 q_hscb->tag = saved_tag;
593 q_hscb->next = scb->hscb->tag;
594
595 /* Now swap HSCB pointers. */
596 ahc->next_queued_scb->hscb = scb->hscb;
597 scb->hscb = q_hscb;
598
599 /* Now define the mapping from tag to SCB in the scbindex */
600 ahc->scb_data->scbindex[scb->hscb->tag] = scb;
601}
602
603/*
604 * Tell the sequencer about a new transaction to execute.
605 */
606void
607ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb)
608{
609 ahc_swap_with_next_hscb(ahc, scb);
610
611 if (scb->hscb->tag == SCB_LIST_NULL
612 || scb->hscb->next == SCB_LIST_NULL)
613 panic("Attempt to queue invalid SCB tag %x:%x\n",
614 scb->hscb->tag, scb->hscb->next);
615
616 /*
617 * Setup data "oddness".
618 */
619 scb->hscb->lun &= LID;
620 if (ahc_get_transfer_length(scb) & 0x1)
621 scb->hscb->lun |= SCB_XFERLEN_ODD;
622
623 /*
624 * Keep a history of SCBs we've downloaded in the qinfifo.
625 */
626 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
627
628 /*
629 * Make sure our data is consistent from the
630 * perspective of the adapter.
631 */
632 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
633
634 /* Tell the adapter about the newly queued SCB */
635 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
636 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
637 } else {
638 if ((ahc->features & AHC_AUTOPAUSE) == 0)
639 ahc_pause(ahc);
640 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
641 if ((ahc->features & AHC_AUTOPAUSE) == 0)
642 ahc_unpause(ahc);
643 }
644}
645
646struct scsi_sense_data *
647ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb)
648{
649 int offset;
650
651 offset = scb - ahc->scb_data->scbarray;
652 return (&ahc->scb_data->sense[offset]);
653}
654
d1d7b19d 655static uint32_t
be0d6768
DV		 656ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb)
657{
658 int offset;
659
660 offset = scb - ahc->scb_data->scbarray;
661 return (ahc->scb_data->sense_busaddr
662 + (offset * sizeof(struct scsi_sense_data)));
663}
664
665/************************** Interrupt Processing ******************************/
d1d7b19d 666static void
be0d6768
DV		 667ahc_sync_qoutfifo(struct ahc_softc *ahc, int op)
668{
669 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
670 /*offset*/0, /*len*/256, op);
671}
672
d1d7b19d 673static void
be0d6768
DV		 674ahc_sync_tqinfifo(struct ahc_softc *ahc, int op)
675{
676#ifdef AHC_TARGET_MODE
677 if ((ahc->flags & AHC_TARGETROLE) != 0) {
678 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
679 ahc->shared_data_dmamap,
680 ahc_targetcmd_offset(ahc, 0),
681 sizeof(struct target_cmd) * AHC_TMODE_CMDS,
682 op);
683 }
684#endif
685}
686
687/*
688 * See if the firmware has posted any completed commands
689 * into our in-core command complete fifos.
690 */
691#define AHC_RUN_QOUTFIFO 0x1
692#define AHC_RUN_TQINFIFO 0x2
d1d7b19d 693static u_int
be0d6768
DV		 694ahc_check_cmdcmpltqueues(struct ahc_softc *ahc)
695{
696 u_int retval;
697
698 retval = 0;
699 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
700 /*offset*/ahc->qoutfifonext, /*len*/1,
701 BUS_DMASYNC_POSTREAD);
702 if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL)
703 retval |= AHC_RUN_QOUTFIFO;
704#ifdef AHC_TARGET_MODE
705 if ((ahc->flags & AHC_TARGETROLE) != 0
706 && (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) {
707 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
708 ahc->shared_data_dmamap,
709 ahc_targetcmd_offset(ahc, ahc->tqinfifofnext),
710 /*len*/sizeof(struct target_cmd),
711 BUS_DMASYNC_POSTREAD);
712 if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0)
713 retval |= AHC_RUN_TQINFIFO;
714 }
715#endif
716 return (retval);
717}
718
719/*
720 * Catch an interrupt from the adapter
721 */
722int
723ahc_intr(struct ahc_softc *ahc)
724{
725 u_int intstat;
726
727 if ((ahc->pause & INTEN) == 0) {
728 /*
729 * Our interrupt is not enabled on the chip
730 * and may be disabled for re-entrancy reasons,
731 * so just return. This is likely just a shared
732 * interrupt.
733 */
734 return (0);
735 }
736 /*
737 * Instead of directly reading the interrupt status register,
738 * infer the cause of the interrupt by checking our in-core
739 * completion queues. This avoids a costly PCI bus read in
740 * most cases.
741 */
742 if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0
743 && (ahc_check_cmdcmpltqueues(ahc) != 0))
744 intstat = CMDCMPLT;
745 else {
746 intstat = ahc_inb(ahc, INTSTAT);
747 }
748
749 if ((intstat & INT_PEND) == 0) {
750#if AHC_PCI_CONFIG > 0
751 if (ahc->unsolicited_ints > 500) {
752 ahc->unsolicited_ints = 0;
753 if ((ahc->chip & AHC_PCI) != 0
754 && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
755 ahc->bus_intr(ahc);
756 }
757#endif
758 ahc->unsolicited_ints++;
759 return (0);
760 }
761 ahc->unsolicited_ints = 0;
762
763 if (intstat & CMDCMPLT) {
764 ahc_outb(ahc, CLRINT, CLRCMDINT);
765
766 /*
767 * Ensure that the chip sees that we've cleared
768 * this interrupt before we walk the output fifo.
769 * Otherwise, we may, due to posted bus writes,
770 * clear the interrupt after we finish the scan,
771 * and after the sequencer has added new entries
772 * and asserted the interrupt again.
773 */
774 ahc_flush_device_writes(ahc);
775 ahc_run_qoutfifo(ahc);
776#ifdef AHC_TARGET_MODE
777 if ((ahc->flags & AHC_TARGETROLE) != 0)
778 ahc_run_tqinfifo(ahc, /*paused*/FALSE);
779#endif
780 }
781
782 /*
783 * Handle statuses that may invalidate our cached
784 * copy of INTSTAT separately.
785 */
786 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) {
787 /* Hot eject. Do nothing */
788 } else if (intstat & BRKADRINT) {
789 ahc_handle_brkadrint(ahc);
790 } else if ((intstat & (SEQINT|SCSIINT)) != 0) {
791
792 ahc_pause_bug_fix(ahc);
793
794 if ((intstat & SEQINT) != 0)
795 ahc_handle_seqint(ahc, intstat);
796
797 if ((intstat & SCSIINT) != 0)
798 ahc_handle_scsiint(ahc, intstat);
799 }
800 return (1);
801}
802
1da177e4
LT		 803/************************* Sequencer Execution Control ************************/
804/*
805 * Restart the sequencer program from address zero
806 */
d1d7b19d 807static void
1da177e4
LT		 808ahc_restart(struct ahc_softc *ahc)
809{
7583221f 810 uint8_t sblkctl;
1da177e4
LT		 811
812 ahc_pause(ahc);
813
814 /* No more pending messages. */
815 ahc_clear_msg_state(ahc);
816
817 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
818 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
819 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
820 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
821 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
822 ahc_outb(ahc, SAVED_LUN, 0xFF);
823
824 /*
825 * Ensure that the sequencer's idea of TQINPOS
826 * matches our own. The sequencer increments TQINPOS
827 * only after it sees a DMA complete and a reset could
828 * occur before the increment leaving the kernel to believe
829 * the command arrived but the sequencer to not.
830 */
831 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
832
833 /* Always allow reselection */
834 ahc_outb(ahc, SCSISEQ,
835 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
836 if ((ahc->features & AHC_CMD_CHAN) != 0) {
837 /* Ensure that no DMA operations are in progress */
838 ahc_outb(ahc, CCSCBCNT, 0);
839 ahc_outb(ahc, CCSGCTL, 0);
840 ahc_outb(ahc, CCSCBCTL, 0);
841 }
842 /*
843 * If we were in the process of DMA'ing SCB data into
844 * an SCB, replace that SCB on the free list. This prevents
845 * an SCB leak.
846 */
847 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
848 ahc_add_curscb_to_free_list(ahc);
849 ahc_outb(ahc, SEQ_FLAGS2,
850 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
851 }
79778a27
JB		 852
853 /*
854 * Clear any pending sequencer interrupt. It is no
855 * longer relevant since we're resetting the Program
856 * Counter.
857 */
858 ahc_outb(ahc, CLRINT, CLRSEQINT);
859
1da177e4
LT		 860 ahc_outb(ahc, MWI_RESIDUAL, 0);
861 ahc_outb(ahc, SEQCTL, ahc->seqctl);
862 ahc_outb(ahc, SEQADDR0, 0);
863 ahc_outb(ahc, SEQADDR1, 0);
79778a27 864
7583221f 865 /*
866 * Take the LED out of diagnostic mode on PM resume, too
867 */
868 sblkctl = ahc_inb(ahc, SBLKCTL);
869 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
870
1da177e4
LT		 871 ahc_unpause(ahc);
872}
873
874/************************* Input/Output Queues ********************************/
d1d7b19d 875static void
1da177e4
LT		 876ahc_run_qoutfifo(struct ahc_softc *ahc)
877{
878 struct scb *scb;
879 u_int scb_index;
880
881 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
882 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
883
884 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
885 if ((ahc->qoutfifonext & 0x03) == 0x03) {
886 u_int modnext;
887
888 /*
889 * Clear 32bits of QOUTFIFO at a time
890 * so that we don't clobber an incoming
891 * byte DMA to the array on architectures
892 * that only support 32bit load and store
893 * operations.
894 */
895 modnext = ahc->qoutfifonext & ~0x3;
896 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
897 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
898 ahc->shared_data_dmamap,
899 /*offset*/modnext, /*len*/4,
900 BUS_DMASYNC_PREREAD);
901 }
902 ahc->qoutfifonext++;
903
904 scb = ahc_lookup_scb(ahc, scb_index);
905 if (scb == NULL) {
48813cf9 906 printk("%s: WARNING no command for scb %d "
1da177e4
LT		 907 "(cmdcmplt)\nQOUTPOS = %d\n",
908 ahc_name(ahc), scb_index,
909 (ahc->qoutfifonext - 1) & 0xFF);
910 continue;
911 }
912
913 /*
914 * Save off the residual
915 * if there is one.
916 */
917 ahc_update_residual(ahc, scb);
918 ahc_done(ahc, scb);
919 }
920}
921
d1d7b19d 922static void
1da177e4
LT		 923ahc_run_untagged_queues(struct ahc_softc *ahc)
924{
925 int i;
926
927 for (i = 0; i < 16; i++)
928 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
929}
930
d1d7b19d 931static void
1da177e4
LT		 932ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
933{
934 struct scb *scb;
935
936 if (ahc->untagged_queue_lock != 0)
937 return;
938
939 if ((scb = TAILQ_FIRST(queue)) != NULL
940 && (scb->flags & SCB_ACTIVE) == 0) {
941 scb->flags |= SCB_ACTIVE;
942 ahc_queue_scb(ahc, scb);
943 }
944}
945
946/************************* Interrupt Handling *********************************/
d1d7b19d 947static void
1da177e4
LT		 948ahc_handle_brkadrint(struct ahc_softc *ahc)
949{
950 /*
951 * We upset the sequencer :-(
952 * Lookup the error message
953 */
954 int i;
955 int error;
956
957 error = ahc_inb(ahc, ERROR);
958 for (i = 0; error != 1 && i < num_errors; i++)
959 error >>= 1;
48813cf9 960 printk("%s: brkadrint, %s at seqaddr = 0x%x\n",
1da177e4
LT		 961 ahc_name(ahc), ahc_hard_errors[i].errmesg,
962 ahc_inb(ahc, SEQADDR0) |
963 (ahc_inb(ahc, SEQADDR1) << 8));
964
965 ahc_dump_card_state(ahc);
966
967 /* Tell everyone that this HBA is no longer available */
968 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
969 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
970 CAM_NO_HBA);
971
972 /* Disable all interrupt sources by resetting the controller */
973 ahc_shutdown(ahc);
974}
975
d1d7b19d 976static void
1da177e4
LT		 977ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
978{
979 struct scb *scb;
980 struct ahc_devinfo devinfo;
981
982 ahc_fetch_devinfo(ahc, &devinfo);
983
984 /*
985 * Clear the upper byte that holds SEQINT status
986 * codes and clear the SEQINT bit. We will unpause
987 * the sequencer, if appropriate, after servicing
988 * the request.
989 */
990 ahc_outb(ahc, CLRINT, CLRSEQINT);
991 switch (intstat & SEQINT_MASK) {
992 case BAD_STATUS:
993 {
994 u_int scb_index;
995 struct hardware_scb *hscb;
996
997 /*
998 * Set the default return value to 0 (don't
999 * send sense). The sense code will change
1000 * this if needed.
1001 */
1002 ahc_outb(ahc, RETURN_1, 0);
1003
1004 /*
1005 * The sequencer will notify us when a command
1006 * has an error that would be of interest to
1007 * the kernel. This allows us to leave the sequencer
1008 * running in the common case of command completes
1009 * without error. The sequencer will already have
1010 * dma'd the SCB back up to us, so we can reference
1011 * the in kernel copy directly.
1012 */
1013 scb_index = ahc_inb(ahc, SCB_TAG);
1014 scb = ahc_lookup_scb(ahc, scb_index);
1015 if (scb == NULL) {
1016 ahc_print_devinfo(ahc, &devinfo);
48813cf9 1017 printk("ahc_intr - referenced scb "
1da177e4
LT		 1018 "not valid during seqint 0x%x scb(%d)\n",
1019 intstat, scb_index);
1020 ahc_dump_card_state(ahc);
1021 panic("for safety");
1022 goto unpause;
1023 }
1024
1025 hscb = scb->hscb;
1026
1027 /* Don't want to clobber the original sense code */
1028 if ((scb->flags & SCB_SENSE) != 0) {
1029 /*
1030 * Clear the SCB_SENSE Flag and have
1031 * the sequencer do a normal command
1032 * complete.
1033 */
1034 scb->flags &= ~SCB_SENSE;
1035 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
1036 break;
1037 }
1038 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
1039 /* Freeze the queue until the client sees the error. */
1040 ahc_freeze_devq(ahc, scb);
1041 ahc_freeze_scb(scb);
1042 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
1043 switch (hscb->shared_data.status.scsi_status) {
1044 case SCSI_STATUS_OK:
3f4f27e1 1045 printk("%s: Interrupted for status of 0???\n",
1da177e4
LT		 1046 ahc_name(ahc));
1047 break;
1048 case SCSI_STATUS_CMD_TERMINATED:
1049 case SCSI_STATUS_CHECK_COND:
1050 {
1051 struct ahc_dma_seg *sg;
1052 struct scsi_sense *sc;
1053 struct ahc_initiator_tinfo *targ_info;
1054 struct ahc_tmode_tstate *tstate;
1055 struct ahc_transinfo *tinfo;
1056#ifdef AHC_DEBUG
1057 if (ahc_debug & AHC_SHOW_SENSE) {
1058 ahc_print_path(ahc, scb);
48813cf9 1059 printk("SCB %d: requests Check Status\n",
1da177e4
LT		 1060 scb->hscb->tag);
1061 }
1062#endif
1063
1064 if (ahc_perform_autosense(scb) == 0)
1065 break;
1066
1067 targ_info = ahc_fetch_transinfo(ahc,
1068 devinfo.channel,
1069 devinfo.our_scsiid,
1070 devinfo.target,
1071 &tstate);
1072 tinfo = &targ_info->curr;
1073 sg = scb->sg_list;
1074 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
1075 /*
1076 * Save off the residual if there is one.
1077 */
1078 ahc_update_residual(ahc, scb);
1079#ifdef AHC_DEBUG
1080 if (ahc_debug & AHC_SHOW_SENSE) {
1081 ahc_print_path(ahc, scb);
48813cf9 1082 printk("Sending Sense\n");
1da177e4
LT		 1083 }
1084#endif
1085 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
1086 sg->len = ahc_get_sense_bufsize(ahc, scb);
1087 sg->len |= AHC_DMA_LAST_SEG;
1088
1089 /* Fixup byte order */
1090 sg->addr = ahc_htole32(sg->addr);
1091 sg->len = ahc_htole32(sg->len);
1092
1093 sc->opcode = REQUEST_SENSE;
1094 sc->byte2 = 0;
1095 if (tinfo->protocol_version <= SCSI_REV_2
1096 && SCB_GET_LUN(scb) < 8)
1097 sc->byte2 = SCB_GET_LUN(scb) << 5;
1098 sc->unused[0] = 0;
1099 sc->unused[1] = 0;
1100 sc->length = sg->len;
1101 sc->control = 0;
1102
1103 /*
1104 * We can't allow the target to disconnect.
1105 * This will be an untagged transaction and
1106 * having the target disconnect will make this
1107 * transaction indestinguishable from outstanding
1108 * tagged transactions.
1109 */
1110 hscb->control = 0;
1111
1112 /*
1113 * This request sense could be because the
1114 * the device lost power or in some other
1115 * way has lost our transfer negotiations.
1116 * Renegotiate if appropriate. Unit attention
1117 * errors will be reported before any data
1118 * phases occur.
1119 */
1120 if (ahc_get_residual(scb)
1121 == ahc_get_transfer_length(scb)) {
1122 ahc_update_neg_request(ahc, &devinfo,
1123 tstate, targ_info,
1124 AHC_NEG_IF_NON_ASYNC);
1125 }
1126 if (tstate->auto_negotiate & devinfo.target_mask) {
1127 hscb->control |= MK_MESSAGE;
1128 scb->flags &= ~SCB_NEGOTIATE;
1129 scb->flags |= SCB_AUTO_NEGOTIATE;
1130 }
1131 hscb->cdb_len = sizeof(*sc);
1132 hscb->dataptr = sg->addr;
1133 hscb->datacnt = sg->len;
1134 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
1135 hscb->sgptr = ahc_htole32(hscb->sgptr);
1136 scb->sg_count = 1;
1137 scb->flags |= SCB_SENSE;
1138 ahc_qinfifo_requeue_tail(ahc, scb);
1139 ahc_outb(ahc, RETURN_1, SEND_SENSE);
1140 /*
1141 * Ensure we have enough time to actually
1142 * retrieve the sense.
1143 */
1144 ahc_scb_timer_reset(scb, 5 * 1000000);
1145 break;
1146 }
1147 default:
1148 break;
1149 }
1150 break;
1151 }
1152 case NO_MATCH:
1153 {
1154 /* Ensure we don't leave the selection hardware on */
1155 ahc_outb(ahc, SCSISEQ,
1156 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1157
48813cf9 1158 printk("%s:%c:%d: no active SCB for reconnecting "
1da177e4
LT		 1159 "target - issuing BUS DEVICE RESET\n",
1160 ahc_name(ahc), devinfo.channel, devinfo.target);
48813cf9 1161 printk("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1da177e4
LT		 1162 "ARG_1 == 0x%x ACCUM = 0x%x\n",
1163 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
1164 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
48813cf9 1165 printk("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1da177e4
LT		 1166 "SINDEX == 0x%x\n",
1167 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
1168 ahc_index_busy_tcl(ahc,
1169 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
1170 ahc_inb(ahc, SAVED_LUN))),
1171 ahc_inb(ahc, SINDEX));
48813cf9 1172 printk("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1da177e4
LT		 1173 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
1174 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
1175 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
1176 ahc_inb(ahc, SCB_CONTROL));
48813cf9 1177 printk("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
1da177e4 1178 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
48813cf9
PE		 1179 printk("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
1180 printk("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
1da177e4
LT		 1181 ahc_dump_card_state(ahc);
1182 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
1183 ahc->msgout_len = 1;
1184 ahc->msgout_index = 0;
1185 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1186 ahc_outb(ahc, MSG_OUT, HOST_MSG);
1187 ahc_assert_atn(ahc);
1188 break;
1189 }
1190 case SEND_REJECT:
1191 {
1192 u_int rejbyte = ahc_inb(ahc, ACCUM);
48813cf9 1193 printk("%s:%c:%d: Warning - unknown message received from "
1da177e4
LT		 1194 "target (0x%x). Rejecting\n",
1195 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
1196 break;
1197 }
1198 case PROTO_VIOLATION:
1199 {
1200 ahc_handle_proto_violation(ahc);
1201 break;
1202 }
1203 case IGN_WIDE_RES:
1204 ahc_handle_ign_wide_residue(ahc, &devinfo);
1205 break;
1206 case PDATA_REINIT:
1207 ahc_reinitialize_dataptrs(ahc);
1208 break;
1209 case BAD_PHASE:
1210 {
1211 u_int lastphase;
1212
1213 lastphase = ahc_inb(ahc, LASTPHASE);
48813cf9 1214 printk("%s:%c:%d: unknown scsi bus phase %x, "
1da177e4
LT		 1215 "lastphase = 0x%x. Attempting to continue\n",
1216 ahc_name(ahc), devinfo.channel, devinfo.target,
1217 lastphase, ahc_inb(ahc, SCSISIGI));
1218 break;
1219 }
1220 case MISSED_BUSFREE:
1221 {
1222 u_int lastphase;
1223
1224 lastphase = ahc_inb(ahc, LASTPHASE);
48813cf9 1225 printk("%s:%c:%d: Missed busfree. "
1da177e4
LT		 1226 "Lastphase = 0x%x, Curphase = 0x%x\n",
1227 ahc_name(ahc), devinfo.channel, devinfo.target,
1228 lastphase, ahc_inb(ahc, SCSISIGI));
1229 ahc_restart(ahc);
1230 return;
1231 }
1232 case HOST_MSG_LOOP:
1233 {
1234 /*
1235 * The sequencer has encountered a message phase
1236 * that requires host assistance for completion.
1237 * While handling the message phase(s), we will be
1238 * notified by the sequencer after each byte is
25985edc 1239 * transferred so we can track bus phase changes.
1da177e4
LT		 1240 *
1241 * If this is the first time we've seen a HOST_MSG_LOOP
1242 * interrupt, initialize the state of the host message
1243 * loop.
1244 */
1245 if (ahc->msg_type == MSG_TYPE_NONE) {
1246 struct scb *scb;
1247 u_int scb_index;
1248 u_int bus_phase;
1249
1250 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1251 if (bus_phase != P_MESGIN
1252 && bus_phase != P_MESGOUT) {
48813cf9 1253 printk("ahc_intr: HOST_MSG_LOOP bad "
1da177e4
LT		 1254 "phase 0x%x\n",
1255 bus_phase);
1256 /*
1257 * Probably transitioned to bus free before
1258 * we got here. Just punt the message.
1259 */
1260 ahc_clear_intstat(ahc);
1261 ahc_restart(ahc);
1262 return;
1263 }
1264
1265 scb_index = ahc_inb(ahc, SCB_TAG);
1266 scb = ahc_lookup_scb(ahc, scb_index);
1267 if (devinfo.role == ROLE_INITIATOR) {
5e2f22d3
JB		 1268 if (bus_phase == P_MESGOUT) {
1269 if (scb == NULL)
1270 panic("HOST_MSG_LOOP with "
1271 "invalid SCB %x\n",
1272 scb_index);
1da177e4 1273
1da177e4
LT		 1274 ahc_setup_initiator_msgout(ahc,
1275 &devinfo,
1276 scb);
5e2f22d3 1277 } else {
1da177e4
LT		 1278 ahc->msg_type =
1279 MSG_TYPE_INITIATOR_MSGIN;
1280 ahc->msgin_index = 0;
1281 }
1282 }
1283#ifdef AHC_TARGET_MODE
1284 else {
1285 if (bus_phase == P_MESGOUT) {
1286 ahc->msg_type =
1287 MSG_TYPE_TARGET_MSGOUT;
1288 ahc->msgin_index = 0;
1289 }
1290 else
1291 ahc_setup_target_msgin(ahc,
1292 &devinfo,
1293 scb);
1294 }
1295#endif
1296 }
1297
1298 ahc_handle_message_phase(ahc);
1299 break;
1300 }
1301 case PERR_DETECTED:
1302 {
1303 /*
1304 * If we've cleared the parity error interrupt
1305 * but the sequencer still believes that SCSIPERR
1306 * is true, it must be that the parity error is
1307 * for the currently presented byte on the bus,
1308 * and we are not in a phase (data-in) where we will
1309 * eventually ack this byte. Ack the byte and
1310 * throw it away in the hope that the target will
1311 * take us to message out to deliver the appropriate
1312 * error message.
1313 */
1314 if ((intstat & SCSIINT) == 0
1315 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
1316
1317 if ((ahc->features & AHC_DT) == 0) {
1318 u_int curphase;
1319
1320 /*
1321 * The hardware will only let you ack bytes
1322 * if the expected phase in SCSISIGO matches
1323 * the current phase. Make sure this is
1324 * currently the case.
1325 */
1326 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1327 ahc_outb(ahc, LASTPHASE, curphase);
1328 ahc_outb(ahc, SCSISIGO, curphase);
1329 }
1330 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
1331 int wait;
1332
1333 /*
1334 * In a data phase. Faster to bitbucket
1335 * the data than to individually ack each
1336 * byte. This is also the only strategy
1337 * that will work with AUTOACK enabled.
1338 */
1339 ahc_outb(ahc, SXFRCTL1,
1340 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
1341 wait = 5000;
1342 while (--wait != 0) {
1343 if ((ahc_inb(ahc, SCSISIGI)
1344 & (CDI|MSGI)) != 0)
1345 break;
1346 ahc_delay(100);
1347 }
1348 ahc_outb(ahc, SXFRCTL1,
1349 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
1350 if (wait == 0) {
1351 struct scb *scb;
1352 u_int scb_index;
1353
1354 ahc_print_devinfo(ahc, &devinfo);
48813cf9 1355 printk("Unable to clear parity error. "
1da177e4
LT		 1356 "Resetting bus.\n");
1357 scb_index = ahc_inb(ahc, SCB_TAG);
1358 scb = ahc_lookup_scb(ahc, scb_index);
1359 if (scb != NULL)
1360 ahc_set_transaction_status(scb,
1361 CAM_UNCOR_PARITY);
1362 ahc_reset_channel(ahc, devinfo.channel,
1363 /*init reset*/TRUE);
1364 }
1365 } else {
1366 ahc_inb(ahc, SCSIDATL);
1367 }
1368 }
1369 break;
1370 }
1371 case DATA_OVERRUN:
1372 {
1373 /*
1374 * When the sequencer detects an overrun, it
1375 * places the controller in "BITBUCKET" mode
1376 * and allows the target to complete its transfer.
1377 * Unfortunately, none of the counters get updated
1378 * when the controller is in this mode, so we have
1379 * no way of knowing how large the overrun was.
1380 */
1381 u_int scbindex = ahc_inb(ahc, SCB_TAG);
1382 u_int lastphase = ahc_inb(ahc, LASTPHASE);
1383 u_int i;
1384
1385 scb = ahc_lookup_scb(ahc, scbindex);
1386 for (i = 0; i < num_phases; i++) {
1387 if (lastphase == ahc_phase_table[i].phase)
1388 break;
1389 }
1390 ahc_print_path(ahc, scb);
48813cf9 1391 printk("data overrun detected %s."
1da177e4
LT		 1392 " Tag == 0x%x.\n",
1393 ahc_phase_table[i].phasemsg,
1394 scb->hscb->tag);
1395 ahc_print_path(ahc, scb);
48813cf9 1396 printk("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
1da177e4
LT		 1397 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
1398 ahc_get_transfer_length(scb), scb->sg_count);
1399 if (scb->sg_count > 0) {
1400 for (i = 0; i < scb->sg_count; i++) {
1401
48813cf9 1402 printk("sg[%d] - Addr 0x%x%x : Length %d\n",
1da177e4
LT		 1403 i,
1404 (ahc_le32toh(scb->sg_list[i].len) >> 24
1405 & SG_HIGH_ADDR_BITS),
1406 ahc_le32toh(scb->sg_list[i].addr),
1407 ahc_le32toh(scb->sg_list[i].len)
1408 & AHC_SG_LEN_MASK);
1409 }
1410 }
1411 /*
1412 * Set this and it will take effect when the
1413 * target does a command complete.
1414 */
1415 ahc_freeze_devq(ahc, scb);
1416 if ((scb->flags & SCB_SENSE) == 0) {
1417 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
1418 } else {
1419 scb->flags &= ~SCB_SENSE;
1420 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
1421 }
1422 ahc_freeze_scb(scb);
1423
1424 if ((ahc->features & AHC_ULTRA2) != 0) {
1425 /*
1426 * Clear the channel in case we return
1427 * to data phase later.
1428 */
1429 ahc_outb(ahc, SXFRCTL0,
1430 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
1431 ahc_outb(ahc, SXFRCTL0,
1432 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
1433 }
1434 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1435 u_int dscommand1;
1436
1437 /* Ensure HHADDR is 0 for future DMA operations. */
1438 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
1439 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
1440 ahc_outb(ahc, HADDR, 0);
1441 ahc_outb(ahc, DSCOMMAND1, dscommand1);
1442 }
1443 break;
1444 }
1445 case MKMSG_FAILED:
1446 {
1447 u_int scbindex;
1448
48813cf9 1449 printk("%s:%c:%d:%d: Attempt to issue message failed\n",
1da177e4
LT		 1450 ahc_name(ahc), devinfo.channel, devinfo.target,
1451 devinfo.lun);
1452 scbindex = ahc_inb(ahc, SCB_TAG);
1453 scb = ahc_lookup_scb(ahc, scbindex);
1454 if (scb != NULL
1455 && (scb->flags & SCB_RECOVERY_SCB) != 0)
1456 /*
1457 * Ensure that we didn't put a second instance of this
1458 * SCB into the QINFIFO.
1459 */
1460 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
1461 SCB_GET_CHANNEL(ahc, scb),
1462 SCB_GET_LUN(scb), scb->hscb->tag,
1463 ROLE_INITIATOR, /*status*/0,
1464 SEARCH_REMOVE);
1465 break;
1466 }
1467 case NO_FREE_SCB:
1468 {
48813cf9 1469 printk("%s: No free or disconnected SCBs\n", ahc_name(ahc));
1da177e4
LT		 1470 ahc_dump_card_state(ahc);
1471 panic("for safety");
1472 break;
1473 }
1474 case SCB_MISMATCH:
1475 {
1476 u_int scbptr;
1477
1478 scbptr = ahc_inb(ahc, SCBPTR);
48813cf9 1479 printk("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
1da177e4
LT		 1480 scbptr, ahc_inb(ahc, ARG_1),
1481 ahc->scb_data->hscbs[scbptr].tag);
1482 ahc_dump_card_state(ahc);
25985edc 1483 panic("for safety");
1da177e4
LT		 1484 break;
1485 }
1486 case OUT_OF_RANGE:
1487 {
48813cf9
PE		 1488 printk("%s: BTT calculation out of range\n", ahc_name(ahc));
1489 printk("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1da177e4
LT		 1490 "ARG_1 == 0x%x ACCUM = 0x%x\n",
1491 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
1492 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
48813cf9 1493 printk("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1da177e4
LT		 1494 "SINDEX == 0x%x\n, A == 0x%x\n",
1495 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
1496 ahc_index_busy_tcl(ahc,
1497 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
1498 ahc_inb(ahc, SAVED_LUN))),
1499 ahc_inb(ahc, SINDEX),
1500 ahc_inb(ahc, ACCUM));
48813cf9 1501 printk("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1da177e4
LT		 1502 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
1503 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
1504 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
1505 ahc_inb(ahc, SCB_CONTROL));
48813cf9 1506 printk("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
1da177e4
LT		 1507 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
1508 ahc_dump_card_state(ahc);
1509 panic("for safety");
1510 break;
1511 }
1512 default:
48813cf9 1513 printk("ahc_intr: seqint, "
1da177e4
LT		 1514 "intstat == 0x%x, scsisigi = 0x%x\n",
1515 intstat, ahc_inb(ahc, SCSISIGI));
1516 break;
1517 }
1518unpause:
1519 /*
1520 * The sequencer is paused immediately on
1521 * a SEQINT, so we should restart it when
1522 * we're done.
1523 */
1524 ahc_unpause(ahc);
1525}
1526
d1d7b19d 1527static void
1da177e4
LT		 1528ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
1529{
1530 u_int scb_index;
1531 u_int status0;
1532 u_int status;
1533 struct scb *scb;
1534 char cur_channel;
1535 char intr_channel;
1536
1537 if ((ahc->features & AHC_TWIN) != 0
1538 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
1539 cur_channel = 'B';
1540 else
1541 cur_channel = 'A';
1542 intr_channel = cur_channel;
1543
1544 if ((ahc->features & AHC_ULTRA2) != 0)
1545 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
1546 else
1547 status0 = 0;
1548 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1549 if (status == 0 && status0 == 0) {
1550 if ((ahc->features & AHC_TWIN) != 0) {
1551 /* Try the other channel */
1552 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1553 status = ahc_inb(ahc, SSTAT1)
1554 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1555 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
1556 }
1557 if (status == 0) {
48813cf9 1558 printk("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1da177e4
LT		 1559 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1560 ahc_unpause(ahc);
1561 return;
1562 }
1563 }
1564
1565 /* Make sure the sequencer is in a safe location. */
1566 ahc_clear_critical_section(ahc);
1567
1568 scb_index = ahc_inb(ahc, SCB_TAG);
1569 scb = ahc_lookup_scb(ahc, scb_index);
1570 if (scb != NULL
1571 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1572 scb = NULL;
1573
1574 if ((ahc->features & AHC_ULTRA2) != 0
1575 && (status0 & IOERR) != 0) {
1576 int now_lvd;
1577
1578 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
48813cf9 1579 printk("%s: Transceiver State Has Changed to %s mode\n",
1da177e4
LT		 1580 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1581 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1582 /*
1583 * When transitioning to SE mode, the reset line
1584 * glitches, triggering an arbitration bug in some
1585 * Ultra2 controllers. This bug is cleared when we
1586 * assert the reset line. Since a reset glitch has
1587 * already occurred with this transition and a
1588 * transceiver state change is handled just like
1589 * a bus reset anyway, asserting the reset line
1590 * ourselves is safe.
1591 */
1592 ahc_reset_channel(ahc, intr_channel,
1593 /*Initiate Reset*/now_lvd == 0);
1594 } else if ((status & SCSIRSTI) != 0) {
48813cf9 1595 printk("%s: Someone reset channel %c\n",
1da177e4
LT		 1596 ahc_name(ahc), intr_channel);
1597 if (intr_channel != cur_channel)
1598 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1599 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1600 } else if ((status & SCSIPERR) != 0) {
1601 /*
1602 * Determine the bus phase and queue an appropriate message.
1603 * SCSIPERR is latched true as soon as a parity error
1604 * occurs. If the sequencer acked the transfer that
1605 * caused the parity error and the currently presented
1606 * transfer on the bus has correct parity, SCSIPERR will
1607 * be cleared by CLRSCSIPERR. Use this to determine if
1608 * we should look at the last phase the sequencer recorded,
1609 * or the current phase presented on the bus.
1610 */
1611 struct ahc_devinfo devinfo;
1612 u_int mesg_out;
1613 u_int curphase;
1614 u_int errorphase;
1615 u_int lastphase;
1616 u_int scsirate;
1617 u_int i;
1618 u_int sstat2;
1619 int silent;
1620
1621 lastphase = ahc_inb(ahc, LASTPHASE);
1622 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1623 sstat2 = ahc_inb(ahc, SSTAT2);
1624 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1625 /*
1626 * For all phases save DATA, the sequencer won't
1627 * automatically ack a byte that has a parity error
1628 * in it. So the only way that the current phase
1629 * could be 'data-in' is if the parity error is for
1630 * an already acked byte in the data phase. During
1631 * synchronous data-in transfers, we may actually
1632 * ack bytes before latching the current phase in
1633 * LASTPHASE, leading to the discrepancy between
1634 * curphase and lastphase.
1635 */
1636 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1637 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1638 errorphase = curphase;
1639 else
1640 errorphase = lastphase;
1641
1642 for (i = 0; i < num_phases; i++) {
1643 if (errorphase == ahc_phase_table[i].phase)
1644 break;
1645 }
1646 mesg_out = ahc_phase_table[i].mesg_out;
1647 silent = FALSE;
1648 if (scb != NULL) {
1649 if (SCB_IS_SILENT(scb))
1650 silent = TRUE;
1651 else
1652 ahc_print_path(ahc, scb);
1653 scb->flags |= SCB_TRANSMISSION_ERROR;
1654 } else
48813cf9 1655 printk("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1da177e4
LT		 1656 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1657 scsirate = ahc_inb(ahc, SCSIRATE);
1658 if (silent == FALSE) {
48813cf9 1659 printk("parity error detected %s. "
1da177e4
LT		 1660 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1661 ahc_phase_table[i].phasemsg,
1662 ahc_inw(ahc, SEQADDR0),
1663 scsirate);
1664 if ((ahc->features & AHC_DT) != 0) {
1665 if ((sstat2 & CRCVALERR) != 0)
48813cf9 1666 printk("\tCRC Value Mismatch\n");
1da177e4 1667 if ((sstat2 & CRCENDERR) != 0)
48813cf9 1668 printk("\tNo terminal CRC packet "
a7634b6f 1669 "received\n");
1da177e4 1670 if ((sstat2 & CRCREQERR) != 0)
48813cf9 1671 printk("\tIllegal CRC packet "
1da177e4
LT		 1672 "request\n");
1673 if ((sstat2 & DUAL_EDGE_ERR) != 0)
48813cf9 1674 printk("\tUnexpected %sDT Data Phase\n",
1da177e4
LT		 1675 (scsirate & SINGLE_EDGE)
1676 ? "" : "non-");
1677 }
1678 }
1679
1680 if ((ahc->features & AHC_DT) != 0
1681 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1682 /*
1683 * This error applies regardless of
1684 * data direction, so ignore the value
1685 * in the phase table.
1686 */
1687 mesg_out = MSG_INITIATOR_DET_ERR;
1688 }
1689
1690 /*
1691 * We've set the hardware to assert ATN if we
1692 * get a parity error on "in" phases, so all we
1693 * need to do is stuff the message buffer with
1694 * the appropriate message. "In" phases have set
1695 * mesg_out to something other than MSG_NOP.
1696 */
1697 if (mesg_out != MSG_NOOP) {
1698 if (ahc->msg_type != MSG_TYPE_NONE)
1699 ahc->send_msg_perror = TRUE;
1700 else
1701 ahc_outb(ahc, MSG_OUT, mesg_out);
1702 }
1703 /*
1704 * Force a renegotiation with this target just in
1705 * case we are out of sync for some external reason
1706 * unknown (or unreported) by the target.
1707 */
1708 ahc_fetch_devinfo(ahc, &devinfo);
1709 ahc_force_renegotiation(ahc, &devinfo);
1710
1711 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1712 ahc_unpause(ahc);
1713 } else if ((status & SELTO) != 0) {
1714 u_int scbptr;
1715
1716 /* Stop the selection */
1717 ahc_outb(ahc, SCSISEQ, 0);
1718
1719 /* No more pending messages */
1720 ahc_clear_msg_state(ahc);
1721
1722 /* Clear interrupt state */
1723 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1724 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1725
1726 /*
1727 * Although the driver does not care about the
1728 * 'Selection in Progress' status bit, the busy
25985edc 1729 * LED does. SELINGO is only cleared by a successful
1da177e4
LT		 1730 * selection, so we must manually clear it to insure
1731 * the LED turns off just incase no future successful
1732 * selections occur (e.g. no devices on the bus).
1733 */
1734 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1735
1736 scbptr = ahc_inb(ahc, WAITING_SCBH);
1737 ahc_outb(ahc, SCBPTR, scbptr);
1738 scb_index = ahc_inb(ahc, SCB_TAG);
1739
1740 scb = ahc_lookup_scb(ahc, scb_index);
1741 if (scb == NULL) {
48813cf9 1742 printk("%s: ahc_intr - referenced scb not "
1da177e4
LT		 1743 "valid during SELTO scb(%d, %d)\n",
1744 ahc_name(ahc), scbptr, scb_index);
1745 ahc_dump_card_state(ahc);
1746 } else {
1747 struct ahc_devinfo devinfo;
1748#ifdef AHC_DEBUG
1749 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1750 ahc_print_path(ahc, scb);
48813cf9 1751 printk("Saw Selection Timeout for SCB 0x%x\n",
1da177e4
LT		 1752 scb_index);
1753 }
1754#endif
1da177e4 1755 ahc_scb_devinfo(ahc, &devinfo, scb);
1da177e4
LT		 1756 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1757 ahc_freeze_devq(ahc, scb);
79778a27
JB		 1758
1759 /*
1760 * Cancel any pending transactions on the device
1761 * now that it seems to be missing. This will
1762 * also revert us to async/narrow transfers until
1763 * we can renegotiate with the device.
1764 */
1765 ahc_handle_devreset(ahc, &devinfo,
1766 CAM_SEL_TIMEOUT,
1767 "Selection Timeout",
1768 /*verbose_level*/1);
1da177e4
LT		 1769 }
1770 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1771 ahc_restart(ahc);
1772 } else if ((status & BUSFREE) != 0
1773 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1774 struct ahc_devinfo devinfo;
1775 u_int lastphase;
1776 u_int saved_scsiid;
1777 u_int saved_lun;
1778 u_int target;
1779 u_int initiator_role_id;
1780 char channel;
1781 int printerror;
1782
1783 /*
1784 * Clear our selection hardware as soon as possible.
1785 * We may have an entry in the waiting Q for this target,
1786 * that is affected by this busfree and we don't want to
1787 * go about selecting the target while we handle the event.
1788 */
1789 ahc_outb(ahc, SCSISEQ,
1790 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1791
1792 /*
1793 * Disable busfree interrupts and clear the busfree
1794 * interrupt status. We do this here so that several
1795 * bus transactions occur prior to clearing the SCSIINT
1796 * latch. It can take a bit for the clearing to take effect.
1797 */
1798 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1799 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1800
1801 /*
1802 * Look at what phase we were last in.
1803 * If its message out, chances are pretty good
1804 * that the busfree was in response to one of
1805 * our abort requests.
1806 */
1807 lastphase = ahc_inb(ahc, LASTPHASE);
1808 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1809 saved_lun = ahc_inb(ahc, SAVED_LUN);
1810 target = SCSIID_TARGET(ahc, saved_scsiid);
1811 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1812 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1813 ahc_compile_devinfo(&devinfo, initiator_role_id,
1814 target, saved_lun, channel, ROLE_INITIATOR);
1815 printerror = 1;
1816
1817 if (lastphase == P_MESGOUT) {
1818 u_int tag;
1819
1820 tag = SCB_LIST_NULL;
1821 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1822 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1823 if (ahc->msgout_buf[ahc->msgout_index - 1]
1824 == MSG_ABORT_TAG)
1825 tag = scb->hscb->tag;
1826 ahc_print_path(ahc, scb);
48813cf9 1827 printk("SCB %d - Abort%s Completed.\n",
1da177e4
LT		 1828 scb->hscb->tag, tag == SCB_LIST_NULL ?
1829 "" : " Tag");
1830 ahc_abort_scbs(ahc, target, channel,
1831 saved_lun, tag,
1832 ROLE_INITIATOR,
1833 CAM_REQ_ABORTED);
1834 printerror = 0;
1835 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1836 MSG_BUS_DEV_RESET, TRUE)) {
1837#ifdef __FreeBSD__
1838 /*
1839 * Don't mark the user's request for this BDR
1840 * as completing with CAM_BDR_SENT. CAM3
1841 * specifies CAM_REQ_CMP.
1842 */
1843 if (scb != NULL
1844 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1845 && ahc_match_scb(ahc, scb, target, channel,
1846 CAM_LUN_WILDCARD,
1847 SCB_LIST_NULL,
1848 ROLE_INITIATOR)) {
1849 ahc_set_transaction_status(scb, CAM_REQ_CMP);
1850 }
1851#endif
1852 ahc_compile_devinfo(&devinfo,
1853 initiator_role_id,
1854 target,
1855 CAM_LUN_WILDCARD,
1856 channel,
1857 ROLE_INITIATOR);
1858 ahc_handle_devreset(ahc, &devinfo,
1859 CAM_BDR_SENT,
1860 "Bus Device Reset",
1861 /*verbose_level*/0);
1862 printerror = 0;
1863 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1864 MSG_EXT_PPR, FALSE)) {
1865 struct ahc_initiator_tinfo *tinfo;
1866 struct ahc_tmode_tstate *tstate;
1867
1868 /*
1869 * PPR Rejected. Try non-ppr negotiation
1870 * and retry command.
1871 */
1872 tinfo = ahc_fetch_transinfo(ahc,
1873 devinfo.channel,
1874 devinfo.our_scsiid,
1875 devinfo.target,
1876 &tstate);
1877 tinfo->curr.transport_version = 2;
1878 tinfo->goal.transport_version = 2;
1879 tinfo->goal.ppr_options = 0;
1880 ahc_qinfifo_requeue_tail(ahc, scb);
1881 printerror = 0;
1882 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1883 MSG_EXT_WDTR, FALSE)) {
1884 /*
1885 * Negotiation Rejected. Go-narrow and
1886 * retry command.
1887 */
1888 ahc_set_width(ahc, &devinfo,
1889 MSG_EXT_WDTR_BUS_8_BIT,
1890 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1891 /*paused*/TRUE);
1892 ahc_qinfifo_requeue_tail(ahc, scb);
1893 printerror = 0;
1894 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1895 MSG_EXT_SDTR, FALSE)) {
1896 /*
1897 * Negotiation Rejected. Go-async and
1898 * retry command.
1899 */
1900 ahc_set_syncrate(ahc, &devinfo,
1901 /*syncrate*/NULL,
1902 /*period*/0, /*offset*/0,
1903 /*ppr_options*/0,
1904 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1905 /*paused*/TRUE);
1906 ahc_qinfifo_requeue_tail(ahc, scb);
1907 printerror = 0;
1908 }
1909 }
1910 if (printerror != 0) {
1911 u_int i;
1912
1913 if (scb != NULL) {
1914 u_int tag;
1915
1916 if ((scb->hscb->control & TAG_ENB) != 0)
1917 tag = scb->hscb->tag;
1918 else
1919 tag = SCB_LIST_NULL;
1920 ahc_print_path(ahc, scb);
1921 ahc_abort_scbs(ahc, target, channel,
1922 SCB_GET_LUN(scb), tag,
1923 ROLE_INITIATOR,
1924 CAM_UNEXP_BUSFREE);
1925 } else {
1926 /*
1927 * We had not fully identified this connection,
1928 * so we cannot abort anything.
1929 */
48813cf9 1930 printk("%s: ", ahc_name(ahc));
1da177e4
LT		 1931 }
1932 for (i = 0; i < num_phases; i++) {
1933 if (lastphase == ahc_phase_table[i].phase)
1934 break;
1935 }
1936 if (lastphase != P_BUSFREE) {
1937 /*
1938 * Renegotiate with this device at the
25985edc 1939 * next opportunity just in case this busfree
1da177e4
LT		 1940 * is due to a negotiation mismatch with the
1941 * device.
1942 */
1943 ahc_force_renegotiation(ahc, &devinfo);
1944 }
48813cf9 1945 printk("Unexpected busfree %s\n"
1da177e4
LT		 1946 "SEQADDR == 0x%x\n",
1947 ahc_phase_table[i].phasemsg,
1948 ahc_inb(ahc, SEQADDR0)
1949 | (ahc_inb(ahc, SEQADDR1) << 8));
1950 }
1951 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1952 ahc_restart(ahc);
1953 } else {
48813cf9 1954 printk("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1da177e4
LT		 1955 ahc_name(ahc), status);
1956 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1957 }
1958}
1959
1960/*
1961 * Force renegotiation to occur the next time we initiate
1962 * a command to the current device.
1963 */
1964static void
1965ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1966{
1967 struct ahc_initiator_tinfo *targ_info;
1968 struct ahc_tmode_tstate *tstate;
1969
1970 targ_info = ahc_fetch_transinfo(ahc,
1971 devinfo->channel,
1972 devinfo->our_scsiid,
1973 devinfo->target,
1974 &tstate);
1975 ahc_update_neg_request(ahc, devinfo, tstate,
1976 targ_info, AHC_NEG_IF_NON_ASYNC);
1977}
1978
1979#define AHC_MAX_STEPS 2000
d1d7b19d 1980static void
1da177e4
LT		 1981ahc_clear_critical_section(struct ahc_softc *ahc)
1982{
1983 int stepping;
1984 int steps;
1985 u_int simode0;
1986 u_int simode1;
1987
1988 if (ahc->num_critical_sections == 0)
1989 return;
1990
1991 stepping = FALSE;
1992 steps = 0;
1993 simode0 = 0;
1994 simode1 = 0;
1995 for (;;) {
1996 struct cs *cs;
1997 u_int seqaddr;
1998 u_int i;
1999
2000 seqaddr = ahc_inb(ahc, SEQADDR0)
2001 | (ahc_inb(ahc, SEQADDR1) << 8);
2002
2003 /*
2004 * Seqaddr represents the next instruction to execute,
2005 * so we are really executing the instruction just
2006 * before it.
2007 */
2008 if (seqaddr != 0)
2009 seqaddr -= 1;
2010 cs = ahc->critical_sections;
2011 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
2012
2013 if (cs->begin < seqaddr && cs->end >= seqaddr)
2014 break;
2015 }
2016
2017 if (i == ahc->num_critical_sections)
2018 break;
2019
2020 if (steps > AHC_MAX_STEPS) {
48813cf9 2021 printk("%s: Infinite loop in critical section\n",
1da177e4
LT		 2022 ahc_name(ahc));
2023 ahc_dump_card_state(ahc);
2024 panic("critical section loop");
2025 }
2026
2027 steps++;
2028 if (stepping == FALSE) {
2029
2030 /*
2031 * Disable all interrupt sources so that the
2032 * sequencer will not be stuck by a pausing
2033 * interrupt condition while we attempt to
2034 * leave a critical section.
2035 */
2036 simode0 = ahc_inb(ahc, SIMODE0);
2037 ahc_outb(ahc, SIMODE0, 0);
2038 simode1 = ahc_inb(ahc, SIMODE1);
2039 if ((ahc->features & AHC_DT) != 0)
2040 /*
2041 * On DT class controllers, we
2042 * use the enhanced busfree logic.
2043 * Unfortunately we cannot re-enable
2044 * busfree detection within the
2045 * current connection, so we must
2046 * leave it on while single stepping.
2047 */
2048 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
2049 else
2050 ahc_outb(ahc, SIMODE1, 0);
2051 ahc_outb(ahc, CLRINT, CLRSCSIINT);
2052 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
2053 stepping = TRUE;
2054 }
2055 if ((ahc->features & AHC_DT) != 0) {
2056 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
2057 ahc_outb(ahc, CLRINT, CLRSCSIINT);
2058 }
2059 ahc_outb(ahc, HCNTRL, ahc->unpause);
2060 while (!ahc_is_paused(ahc))
2061 ahc_delay(200);
2062 }
2063 if (stepping) {
2064 ahc_outb(ahc, SIMODE0, simode0);
2065 ahc_outb(ahc, SIMODE1, simode1);
2066 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2067 }
2068}
2069
2070/*
2071 * Clear any pending interrupt status.
2072 */
d1d7b19d 2073static void
1da177e4
LT		 2074ahc_clear_intstat(struct ahc_softc *ahc)
2075{
2076 /* Clear any interrupt conditions this may have caused */
2077 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
2078 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
2079 CLRREQINIT);
2080 ahc_flush_device_writes(ahc);
2081 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
2082 ahc_flush_device_writes(ahc);
2083 ahc_outb(ahc, CLRINT, CLRSCSIINT);
2084 ahc_flush_device_writes(ahc);
2085}
2086
2087/**************************** Debugging Routines ******************************/
2088#ifdef AHC_DEBUG
2089uint32_t ahc_debug = AHC_DEBUG_OPTS;
2090#endif
2091
d1d7b19d
DV		 2092#if 0 /* unused */
2093static void
1da177e4
LT		 2094ahc_print_scb(struct scb *scb)
2095{
2096 int i;
2097
2098 struct hardware_scb *hscb = scb->hscb;
2099
48813cf9 2100 printk("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1da177e4
LT		 2101 (void *)scb,
2102 hscb->control,
2103 hscb->scsiid,
2104 hscb->lun,
2105 hscb->cdb_len);
48813cf9 2106 printk("Shared Data: ");
1da177e4 2107 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
48813cf9
PE		 2108 printk("%#02x", hscb->shared_data.cdb[i]);
2109 printk(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1da177e4
LT		 2110 ahc_le32toh(hscb->dataptr),
2111 ahc_le32toh(hscb->datacnt),
2112 ahc_le32toh(hscb->sgptr),
2113 hscb->tag);
2114 if (scb->sg_count > 0) {
2115 for (i = 0; i < scb->sg_count; i++) {
48813cf9 2116 printk("sg[%d] - Addr 0x%x%x : Length %d\n",
1da177e4
LT		 2117 i,
2118 (ahc_le32toh(scb->sg_list[i].len) >> 24
2119 & SG_HIGH_ADDR_BITS),
2120 ahc_le32toh(scb->sg_list[i].addr),
2121 ahc_le32toh(scb->sg_list[i].len));
2122 }
2123 }
2124}
d1d7b19d 2125#endif
1da177e4
LT		 2126
2127/************************* Transfer Negotiation *******************************/
2128/*
2129 * Allocate per target mode instance (ID we respond to as a target)
2130 * transfer negotiation data structures.
2131 */
2132static struct ahc_tmode_tstate *
2133ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
2134{
2135 struct ahc_tmode_tstate *master_tstate;
2136 struct ahc_tmode_tstate *tstate;
2137 int i;
2138
2139 master_tstate = ahc->enabled_targets[ahc->our_id];
2140 if (channel == 'B') {
2141 scsi_id += 8;
2142 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
2143 }
2144 if (ahc->enabled_targets[scsi_id] != NULL
2145 && ahc->enabled_targets[scsi_id] != master_tstate)
2146 panic("%s: ahc_alloc_tstate - Target already allocated",
2147 ahc_name(ahc));
48813cf9 2148 tstate = kmalloc(sizeof(*tstate), GFP_ATOMIC);
1da177e4
LT		 2149 if (tstate == NULL)
2150 return (NULL);
2151
2152 /*
2153 * If we have allocated a master tstate, copy user settings from
2154 * the master tstate (taken from SRAM or the EEPROM) for this
2155 * channel, but reset our current and goal settings to async/narrow
2156 * until an initiator talks to us.
2157 */
2158 if (master_tstate != NULL) {
2159 memcpy(tstate, master_tstate, sizeof(*tstate));
2160 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
2161 tstate->ultraenb = 0;
2162 for (i = 0; i < AHC_NUM_TARGETS; i++) {
2163 memset(&tstate->transinfo[i].curr, 0,
2164 sizeof(tstate->transinfo[i].curr));
2165 memset(&tstate->transinfo[i].goal, 0,
2166 sizeof(tstate->transinfo[i].goal));
2167 }
2168 } else
2169 memset(tstate, 0, sizeof(*tstate));
2170 ahc->enabled_targets[scsi_id] = tstate;
2171 return (tstate);
2172}
2173
2174#ifdef AHC_TARGET_MODE
2175/*
2176 * Free per target mode instance (ID we respond to as a target)
2177 * transfer negotiation data structures.
2178 */
2179static void
2180ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
2181{
2182 struct ahc_tmode_tstate *tstate;
2183
2184 /*
2185 * Don't clean up our "master" tstate.
2186 * It has our default user settings.
2187 */
2188 if (((channel == 'B' && scsi_id == ahc->our_id_b)
2189 || (channel == 'A' && scsi_id == ahc->our_id))
2190 && force == FALSE)
2191 return;
2192
2193 if (channel == 'B')
2194 scsi_id += 8;
2195 tstate = ahc->enabled_targets[scsi_id];
2196 if (tstate != NULL)
48813cf9 2197 kfree(tstate);
1da177e4
LT		 2198 ahc->enabled_targets[scsi_id] = NULL;
2199}
2200#endif
2201
2202/*
2203 * Called when we have an active connection to a target on the bus,
2204 * this function finds the nearest syncrate to the input period limited
2205 * by the capabilities of the bus connectivity of and sync settings for
2206 * the target.
2207 */
4efea4f6 2208static const struct ahc_syncrate *
1da177e4
LT		 2209ahc_devlimited_syncrate(struct ahc_softc *ahc,
2210 struct ahc_initiator_tinfo *tinfo,
2211 u_int *period, u_int *ppr_options, role_t role)
2212{
2213 struct ahc_transinfo *transinfo;
2214 u_int maxsync;
2215
2216 if ((ahc->features & AHC_ULTRA2) != 0) {
2217 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
2218 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
2219 maxsync = AHC_SYNCRATE_DT;
2220 } else {
2221 maxsync = AHC_SYNCRATE_ULTRA;
2222 /* Can't do DT on an SE bus */
2223 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2224 }
2225 } else if ((ahc->features & AHC_ULTRA) != 0) {
2226 maxsync = AHC_SYNCRATE_ULTRA;
2227 } else {
2228 maxsync = AHC_SYNCRATE_FAST;
2229 }
2230 /*
2231 * Never allow a value higher than our current goal
2232 * period otherwise we may allow a target initiated
2233 * negotiation to go above the limit as set by the
2234 * user. In the case of an initiator initiated
2235 * sync negotiation, we limit based on the user
2236 * setting. This allows the system to still accept
2237 * incoming negotiations even if target initiated
2238 * negotiation is not performed.
2239 */
2240 if (role == ROLE_TARGET)
2241 transinfo = &tinfo->user;
2242 else
2243 transinfo = &tinfo->goal;
2244 *ppr_options &= transinfo->ppr_options;
2245 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
6d07cb71 2246 maxsync = max(maxsync, (u_int)AHC_SYNCRATE_ULTRA2);
1da177e4
LT		 2247 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2248 }
2249 if (transinfo->period == 0) {
2250 *period = 0;
2251 *ppr_options = 0;
2252 return (NULL);
2253 }
6d07cb71 2254 *period = max(*period, (u_int)transinfo->period);
1da177e4
LT		 2255 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
2256}
2257
2258/*
2259 * Look up the valid period to SCSIRATE conversion in our table.
2260 * Return the period and offset that should be sent to the target
2261 * if this was the beginning of an SDTR.
2262 */
d1d7b19d 2263const struct ahc_syncrate *
1da177e4
LT		 2264ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
2265 u_int *ppr_options, u_int maxsync)
2266{
d1d7b19d 2267 const struct ahc_syncrate *syncrate;
1da177e4
LT		 2268
2269 if ((ahc->features & AHC_DT) == 0)
2270 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2271
2272 /* Skip all DT only entries if DT is not available */
2273 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2274 && maxsync < AHC_SYNCRATE_ULTRA2)
2275 maxsync = AHC_SYNCRATE_ULTRA2;
142009a3
JB		 2276
2277 /* Now set the maxsync based on the card capabilities
2278 * DT is already done above */
2279 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
2280 && maxsync < AHC_SYNCRATE_ULTRA)
2281 maxsync = AHC_SYNCRATE_ULTRA;
2282 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
2283 && maxsync < AHC_SYNCRATE_FAST)
2284 maxsync = AHC_SYNCRATE_FAST;
2285
1da177e4
LT		 2286 for (syncrate = &ahc_syncrates[maxsync];
2287 syncrate->rate != NULL;
2288 syncrate++) {
2289
2290 /*
2291 * The Ultra2 table doesn't go as low
2292 * as for the Fast/Ultra cards.
2293 */
2294 if ((ahc->features & AHC_ULTRA2) != 0
2295 && (syncrate->sxfr_u2 == 0))
2296 break;
2297
2298 if (*period <= syncrate->period) {
2299 /*
2300 * When responding to a target that requests
2301 * sync, the requested rate may fall between
2302 * two rates that we can output, but still be
2303 * a rate that we can receive. Because of this,
2304 * we want to respond to the target with
2305 * the same rate that it sent to us even
2306 * if the period we use to send data to it
2307 * is lower. Only lower the response period
2308 * if we must.
2309 */
2310 if (syncrate == &ahc_syncrates[maxsync])
2311 *period = syncrate->period;
2312
2313 /*
2314 * At some speeds, we only support
2315 * ST transfers.
2316 */
4dbc96ad 2317 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1da177e4
LT		 2318 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2319 break;
2320 }
2321 }
2322
2323 if ((*period == 0)
2324 || (syncrate->rate == NULL)
2325 || ((ahc->features & AHC_ULTRA2) != 0
2326 && (syncrate->sxfr_u2 == 0))) {
2327 /* Use asynchronous transfers. */
2328 *period = 0;
2329 syncrate = NULL;
2330 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2331 }
2332 return (syncrate);
2333}
2334
2335/*
2336 * Convert from an entry in our syncrate table to the SCSI equivalent
2337 * sync "period" factor.
2338 */
2339u_int
2340ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
2341{
d1d7b19d 2342 const struct ahc_syncrate *syncrate;
1da177e4
LT		 2343
2344 if ((ahc->features & AHC_ULTRA2) != 0)
2345 scsirate &= SXFR_ULTRA2;
2346 else
2347 scsirate &= SXFR;
2348
142009a3
JB		 2349 /* now set maxsync based on card capabilities */
2350 if ((ahc->features & AHC_DT) == 0 && maxsync < AHC_SYNCRATE_ULTRA2)
2351 maxsync = AHC_SYNCRATE_ULTRA2;
2352 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
2353 && maxsync < AHC_SYNCRATE_ULTRA)
2354 maxsync = AHC_SYNCRATE_ULTRA;
2355 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
2356 && maxsync < AHC_SYNCRATE_FAST)
2357 maxsync = AHC_SYNCRATE_FAST;
2358
2359
1da177e4
LT		 2360 syncrate = &ahc_syncrates[maxsync];
2361 while (syncrate->rate != NULL) {
2362
2363 if ((ahc->features & AHC_ULTRA2) != 0) {
2364 if (syncrate->sxfr_u2 == 0)
2365 break;
2366 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
2367 return (syncrate->period);
2368 } else if (scsirate == (syncrate->sxfr & SXFR)) {
2369 return (syncrate->period);
2370 }
2371 syncrate++;
2372 }
2373 return (0); /* async */
2374}
2375
2376/*
2377 * Truncate the given synchronous offset to a value the
2378 * current adapter type and syncrate are capable of.
2379 */
d1d7b19d 2380static void
1da177e4
LT		 2381ahc_validate_offset(struct ahc_softc *ahc,
2382 struct ahc_initiator_tinfo *tinfo,
d1d7b19d 2383 const struct ahc_syncrate *syncrate,
1da177e4
LT		 2384 u_int *offset, int wide, role_t role)
2385{
2386 u_int maxoffset;
2387
2388 /* Limit offset to what we can do */
2389 if (syncrate == NULL) {
2390 maxoffset = 0;
2391 } else if ((ahc->features & AHC_ULTRA2) != 0) {
2392 maxoffset = MAX_OFFSET_ULTRA2;
2393 } else {
2394 if (wide)
2395 maxoffset = MAX_OFFSET_16BIT;
2396 else
2397 maxoffset = MAX_OFFSET_8BIT;
2398 }
6d07cb71 2399 *offset = min(*offset, maxoffset);
1da177e4
LT		 2400 if (tinfo != NULL) {
2401 if (role == ROLE_TARGET)
6d07cb71 2402 *offset = min(*offset, (u_int)tinfo->user.offset);
1da177e4 2403 else
6d07cb71 2404 *offset = min(*offset, (u_int)tinfo->goal.offset);
1da177e4
LT		 2405 }
2406}
2407
2408/*
2409 * Truncate the given transfer width parameter to a value the
2410 * current adapter type is capable of.
2411 */
d1d7b19d 2412static void
1da177e4
LT		 2413ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
2414 u_int *bus_width, role_t role)
2415{
2416 switch (*bus_width) {
2417 default:
2418 if (ahc->features & AHC_WIDE) {
2419 /* Respond Wide */
2420 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
2421 break;
2422 }
2423 /* FALLTHROUGH */
2424 case MSG_EXT_WDTR_BUS_8_BIT:
2425 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
2426 break;
2427 }
2428 if (tinfo != NULL) {
2429 if (role == ROLE_TARGET)
6d07cb71 2430 *bus_width = min((u_int)tinfo->user.width, *bus_width);
1da177e4 2431 else
6d07cb71 2432 *bus_width = min((u_int)tinfo->goal.width, *bus_width);
1da177e4
LT		 2433 }
2434}
2435
2436/*
2437 * Update the bitmask of targets for which the controller should
25985edc 2438 * negotiate with at the next convenient opportunity. This currently
1da177e4
LT		 2439 * means the next time we send the initial identify messages for
2440 * a new transaction.
2441 */
2442int
2443ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2444 struct ahc_tmode_tstate *tstate,
2445 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
2446{
2447 u_int auto_negotiate_orig;
2448
2449 auto_negotiate_orig = tstate->auto_negotiate;
2450 if (neg_type == AHC_NEG_ALWAYS) {
2451 /*
2452 * Force our "current" settings to be
2453 * unknown so that unless a bus reset
2454 * occurs the need to renegotiate is
2455 * recorded persistently.
2456 */
2457 if ((ahc->features & AHC_WIDE) != 0)
2458 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
2459 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
2460 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
2461 }
2462 if (tinfo->curr.period != tinfo->goal.period
2463 || tinfo->curr.width != tinfo->goal.width
2464 || tinfo->curr.offset != tinfo->goal.offset
2465 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
2466 || (neg_type == AHC_NEG_IF_NON_ASYNC
2467 && (tinfo->goal.offset != 0
2468 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
2469 || tinfo->goal.ppr_options != 0)))
2470 tstate->auto_negotiate |= devinfo->target_mask;
2471 else
2472 tstate->auto_negotiate &= ~devinfo->target_mask;
2473
2474 return (auto_negotiate_orig != tstate->auto_negotiate);
2475}
2476
2477/*
2478 * Update the user/goal/curr tables of synchronous negotiation
2479 * parameters as well as, in the case of a current or active update,
2480 * any data structures on the host controller. In the case of an
2481 * active update, the specified target is currently talking to us on
2482 * the bus, so the transfer parameter update must take effect
2483 * immediately.
2484 */
2485void
2486ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
d1d7b19d 2487 const struct ahc_syncrate *syncrate, u_int period,
1da177e4
LT		 2488 u_int offset, u_int ppr_options, u_int type, int paused)
2489{
2490 struct ahc_initiator_tinfo *tinfo;
2491 struct ahc_tmode_tstate *tstate;
2492 u_int old_period;
2493 u_int old_offset;
2494 u_int old_ppr;
2495 int active;
2496 int update_needed;
2497
2498 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2499 update_needed = 0;
2500
2501 if (syncrate == NULL) {
2502 period = 0;
2503 offset = 0;
2504 }
2505
2506 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2507 devinfo->target, &tstate);
2508
2509 if ((type & AHC_TRANS_USER) != 0) {
2510 tinfo->user.period = period;
2511 tinfo->user.offset = offset;
2512 tinfo->user.ppr_options = ppr_options;
2513 }
2514
2515 if ((type & AHC_TRANS_GOAL) != 0) {
2516 tinfo->goal.period = period;
2517 tinfo->goal.offset = offset;
2518 tinfo->goal.ppr_options = ppr_options;
2519 }
2520
2521 old_period = tinfo->curr.period;
2522 old_offset = tinfo->curr.offset;
2523 old_ppr = tinfo->curr.ppr_options;
2524
2525 if ((type & AHC_TRANS_CUR) != 0
2526 && (old_period != period
2527 || old_offset != offset
2528 || old_ppr != ppr_options)) {
2529 u_int scsirate;
2530
2531 update_needed++;
2532 scsirate = tinfo->scsirate;
2533 if ((ahc->features & AHC_ULTRA2) != 0) {
2534
2535 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
2536 if (syncrate != NULL) {
2537 scsirate |= syncrate->sxfr_u2;
2538 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
2539 scsirate |= ENABLE_CRC;
2540 else
2541 scsirate |= SINGLE_EDGE;
2542 }
2543 } else {
2544
2545 scsirate &= ~(SXFR|SOFS);
2546 /*
2547 * Ensure Ultra mode is set properly for
2548 * this target.
2549 */
2550 tstate->ultraenb &= ~devinfo->target_mask;
2551 if (syncrate != NULL) {
2552 if (syncrate->sxfr & ULTRA_SXFR) {
2553 tstate->ultraenb |=
2554 devinfo->target_mask;
2555 }
2556 scsirate |= syncrate->sxfr & SXFR;
2557 scsirate |= offset & SOFS;
2558 }
2559 if (active) {
2560 u_int sxfrctl0;
2561
2562 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
2563 sxfrctl0 &= ~FAST20;
2564 if (tstate->ultraenb & devinfo->target_mask)
2565 sxfrctl0 |= FAST20;
2566 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
2567 }
2568 }
2569 if (active) {
2570 ahc_outb(ahc, SCSIRATE, scsirate);
2571 if ((ahc->features & AHC_ULTRA2) != 0)
2572 ahc_outb(ahc, SCSIOFFSET, offset);
2573 }
2574
2575 tinfo->scsirate = scsirate;
2576 tinfo->curr.period = period;
2577 tinfo->curr.offset = offset;
2578 tinfo->curr.ppr_options = ppr_options;
2579
2580 ahc_send_async(ahc, devinfo->channel, devinfo->target,
9080063f 2581 CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
1da177e4
LT		 2582 if (bootverbose) {
2583 if (offset != 0) {
48813cf9 2584 printk("%s: target %d synchronous at %sMHz%s, "
1da177e4
LT		 2585 "offset = 0x%x\n", ahc_name(ahc),
2586 devinfo->target, syncrate->rate,
2587 (ppr_options & MSG_EXT_PPR_DT_REQ)
2588 ? " DT" : "", offset);
2589 } else {
48813cf9 2590 printk("%s: target %d using "
1da177e4
LT		 2591 "asynchronous transfers\n",
2592 ahc_name(ahc), devinfo->target);
2593 }
2594 }
2595 }
2596
2597 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2598 tinfo, AHC_NEG_TO_GOAL);
2599
2600 if (update_needed)
2601 ahc_update_pending_scbs(ahc);
2602}
2603
2604/*
2605 * Update the user/goal/curr tables of wide negotiation
2606 * parameters as well as, in the case of a current or active update,
2607 * any data structures on the host controller. In the case of an
2608 * active update, the specified target is currently talking to us on
2609 * the bus, so the transfer parameter update must take effect
2610 * immediately.
2611 */
2612void
2613ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2614 u_int width, u_int type, int paused)
2615{
2616 struct ahc_initiator_tinfo *tinfo;
2617 struct ahc_tmode_tstate *tstate;
2618 u_int oldwidth;
2619 int active;
2620 int update_needed;
2621
2622 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2623 update_needed = 0;
2624 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2625 devinfo->target, &tstate);
2626
2627 if ((type & AHC_TRANS_USER) != 0)
2628 tinfo->user.width = width;
2629
2630 if ((type & AHC_TRANS_GOAL) != 0)
2631 tinfo->goal.width = width;
2632
2633 oldwidth = tinfo->curr.width;
2634 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2635 u_int scsirate;
2636
2637 update_needed++;
2638 scsirate = tinfo->scsirate;
2639 scsirate &= ~WIDEXFER;
2640 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2641 scsirate |= WIDEXFER;
2642
2643 tinfo->scsirate = scsirate;
2644
2645 if (active)
2646 ahc_outb(ahc, SCSIRATE, scsirate);
2647
2648 tinfo->curr.width = width;
2649
2650 ahc_send_async(ahc, devinfo->channel, devinfo->target,
9080063f 2651 CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
1da177e4 2652 if (bootverbose) {
48813cf9 2653 printk("%s: target %d using %dbit transfers\n",
1da177e4
LT		 2654 ahc_name(ahc), devinfo->target,
2655 8 * (0x01 << width));
2656 }
2657 }
2658
2659 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2660 tinfo, AHC_NEG_TO_GOAL);
2661 if (update_needed)
2662 ahc_update_pending_scbs(ahc);
2663}
2664
2665/*
2666 * Update the current state of tagged queuing for a given target.
2667 */
e3e0ca51 2668static void
9080063f
HR		 2669ahc_set_tags(struct ahc_softc *ahc, struct scsi_cmnd *cmd,
2670 struct ahc_devinfo *devinfo, ahc_queue_alg alg)
1da177e4 2671{
9080063f
HR		 2672 struct scsi_device *sdev = cmd->device;
2673
2674 ahc_platform_set_tags(ahc, sdev, devinfo, alg);
1da177e4 2675 ahc_send_async(ahc, devinfo->channel, devinfo->target,
9080063f 2676 devinfo->lun, AC_TRANSFER_NEG);
1da177e4
LT		 2677}
2678
2679/*
2680 * When the transfer settings for a connection change, update any
2681 * in-transit SCBs to contain the new data so the hardware will
2682 * be set correctly during future (re)selections.
2683 */
2684static void
2685ahc_update_pending_scbs(struct ahc_softc *ahc)
2686{
2687 struct scb *pending_scb;
2688 int pending_scb_count;
2689 int i;
2690 int paused;
2691 u_int saved_scbptr;
2692
2693 /*
2694 * Traverse the pending SCB list and ensure that all of the
2695 * SCBs there have the proper settings.
2696 */
2697 pending_scb_count = 0;
2698 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2699 struct ahc_devinfo devinfo;
2700 struct hardware_scb *pending_hscb;
2701 struct ahc_initiator_tinfo *tinfo;
2702 struct ahc_tmode_tstate *tstate;
2703
2704 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2705 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2706 devinfo.our_scsiid,
2707 devinfo.target, &tstate);
2708 pending_hscb = pending_scb->hscb;
2709 pending_hscb->control &= ~ULTRAENB;
2710 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2711 pending_hscb->control |= ULTRAENB;
2712 pending_hscb->scsirate = tinfo->scsirate;
2713 pending_hscb->scsioffset = tinfo->curr.offset;
2714 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2715 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2716 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2717 pending_hscb->control &= ~MK_MESSAGE;
2718 }
2719 ahc_sync_scb(ahc, pending_scb,
2720 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2721 pending_scb_count++;
2722 }
2723
2724 if (pending_scb_count == 0)
2725 return;
2726
2727 if (ahc_is_paused(ahc)) {
2728 paused = 1;
2729 } else {
2730 paused = 0;
2731 ahc_pause(ahc);
2732 }
2733
2734 saved_scbptr = ahc_inb(ahc, SCBPTR);
2735 /* Ensure that the hscbs down on the card match the new information */
2736 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2737 struct hardware_scb *pending_hscb;
2738 u_int control;
2739 u_int scb_tag;
2740
2741 ahc_outb(ahc, SCBPTR, i);
2742 scb_tag = ahc_inb(ahc, SCB_TAG);
2743 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2744 if (pending_scb == NULL)
2745 continue;
2746
2747 pending_hscb = pending_scb->hscb;
2748 control = ahc_inb(ahc, SCB_CONTROL);
2749 control &= ~(ULTRAENB|MK_MESSAGE);
2750 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2751 ahc_outb(ahc, SCB_CONTROL, control);
2752 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2753 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2754 }
2755 ahc_outb(ahc, SCBPTR, saved_scbptr);
2756
2757 if (paused == 0)
2758 ahc_unpause(ahc);
2759}
2760
2761/**************************** Pathing Information *****************************/
2762static void
2763ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2764{
2765 u_int saved_scsiid;
2766 role_t role;
2767 int our_id;
2768
2769 if (ahc_inb(ahc, SSTAT0) & TARGET)
2770 role = ROLE_TARGET;
2771 else
2772 role = ROLE_INITIATOR;
2773
2774 if (role == ROLE_TARGET
2775 && (ahc->features & AHC_MULTI_TID) != 0
2776 && (ahc_inb(ahc, SEQ_FLAGS)
2777 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2778 /* We were selected, so pull our id from TARGIDIN */
2779 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2780 } else if ((ahc->features & AHC_ULTRA2) != 0)
2781 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2782 else
2783 our_id = ahc_inb(ahc, SCSIID) & OID;
2784
2785 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2786 ahc_compile_devinfo(devinfo,
2787 our_id,
2788 SCSIID_TARGET(ahc, saved_scsiid),
2789 ahc_inb(ahc, SAVED_LUN),
2790 SCSIID_CHANNEL(ahc, saved_scsiid),
2791 role);
2792}
2793
d1d7b19d 2794static const struct ahc_phase_table_entry*
1da177e4
LT		 2795ahc_lookup_phase_entry(int phase)
2796{
d1d7b19d
DV		 2797 const struct ahc_phase_table_entry *entry;
2798 const struct ahc_phase_table_entry *last_entry;
1da177e4
LT		 2799
2800 /*
2801 * num_phases doesn't include the default entry which
2802 * will be returned if the phase doesn't match.
2803 */
2804 last_entry = &ahc_phase_table[num_phases];
2805 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2806 if (phase == entry->phase)
2807 break;
2808 }
2809 return (entry);
2810}
2811
2812void
2813ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2814 u_int lun, char channel, role_t role)
2815{
2816 devinfo->our_scsiid = our_id;
2817 devinfo->target = target;
2818 devinfo->lun = lun;
2819 devinfo->target_offset = target;
2820 devinfo->channel = channel;
2821 devinfo->role = role;
2822 if (channel == 'B')
2823 devinfo->target_offset += 8;
2824 devinfo->target_mask = (0x01 << devinfo->target_offset);
2825}
2826
2827void
2828ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2829{
48813cf9 2830 printk("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
1da177e4
LT		 2831 devinfo->target, devinfo->lun);
2832}
2833
2834static void
2835ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2836 struct scb *scb)
2837{
2838 role_t role;
2839 int our_id;
2840
2841 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2842 role = ROLE_INITIATOR;
2843 if ((scb->flags & SCB_TARGET_SCB) != 0)
2844 role = ROLE_TARGET;
2845 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2846 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2847}
2848
2849
2850/************************ Message Phase Processing ****************************/
2851static void
2852ahc_assert_atn(struct ahc_softc *ahc)
2853{
2854 u_int scsisigo;
2855
2856 scsisigo = ATNO;
2857 if ((ahc->features & AHC_DT) == 0)
2858 scsisigo |= ahc_inb(ahc, SCSISIGI);
2859 ahc_outb(ahc, SCSISIGO, scsisigo);
2860}
2861
2862/*
2863 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2864 * or enters the initial message out phase, we are interrupted. Fill our
2865 * outgoing message buffer with the appropriate message and beging handing
2866 * the message phase(s) manually.
2867 */
2868static void
2869ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2870 struct scb *scb)
2871{
2872 /*
2873 * To facilitate adding multiple messages together,
2874 * each routine should increment the index and len
2875 * variables instead of setting them explicitly.
2876 */
2877 ahc->msgout_index = 0;
2878 ahc->msgout_len = 0;
2879
2880 if ((scb->flags & SCB_DEVICE_RESET) == 0
2881 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2882 u_int identify_msg;
2883
2884 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2885 if ((scb->hscb->control & DISCENB) != 0)
2886 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2887 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2888 ahc->msgout_len++;
2889
2890 if ((scb->hscb->control & TAG_ENB) != 0) {
2891 ahc->msgout_buf[ahc->msgout_index++] =
2892 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2893 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2894 ahc->msgout_len += 2;
2895 }
2896 }
2897
2898 if (scb->flags & SCB_DEVICE_RESET) {
2899 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2900 ahc->msgout_len++;
2901 ahc_print_path(ahc, scb);
48813cf9 2902 printk("Bus Device Reset Message Sent\n");
1da177e4
LT		 2903 /*
2904 * Clear our selection hardware in advance of
2905 * the busfree. We may have an entry in the waiting
2906 * Q for this target, and we don't want to go about
2907 * selecting while we handle the busfree and blow it
2908 * away.
2909 */
2910 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2911 } else if ((scb->flags & SCB_ABORT) != 0) {
2912 if ((scb->hscb->control & TAG_ENB) != 0)
2913 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2914 else
2915 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2916 ahc->msgout_len++;
2917 ahc_print_path(ahc, scb);
48813cf9 2918 printk("Abort%s Message Sent\n",
1da177e4
LT		 2919 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2920 /*
2921 * Clear our selection hardware in advance of
2922 * the busfree. We may have an entry in the waiting
2923 * Q for this target, and we don't want to go about
2924 * selecting while we handle the busfree and blow it
2925 * away.
2926 */
2927 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2928 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2929 ahc_build_transfer_msg(ahc, devinfo);
2930 } else {
48813cf9 2931 printk("ahc_intr: AWAITING_MSG for an SCB that "
1da177e4 2932 "does not have a waiting message\n");
48813cf9 2933 printk("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
1da177e4
LT		 2934 devinfo->target_mask);
2935 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2936 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2937 ahc_inb(ahc, MSG_OUT), scb->flags);
2938 }
2939
2940 /*
2941 * Clear the MK_MESSAGE flag from the SCB so we aren't
2942 * asked to send this message again.
2943 */
2944 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2945 scb->hscb->control &= ~MK_MESSAGE;
2946 ahc->msgout_index = 0;
2947 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2948}
2949
2950/*
2951 * Build an appropriate transfer negotiation message for the
2952 * currently active target.
2953 */
2954static void
2955ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2956{
2957 /*
2958 * We need to initiate transfer negotiations.
2959 * If our current and goal settings are identical,
2960 * we want to renegotiate due to a check condition.
2961 */
2962 struct ahc_initiator_tinfo *tinfo;
2963 struct ahc_tmode_tstate *tstate;
d1d7b19d 2964 const struct ahc_syncrate *rate;
1da177e4
LT		 2965 int dowide;
2966 int dosync;
2967 int doppr;
2968 u_int period;
2969 u_int ppr_options;
2970 u_int offset;
2971
2972 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2973 devinfo->target, &tstate);
2974 /*
2975 * Filter our period based on the current connection.
2976 * If we can't perform DT transfers on this segment (not in LVD
2977 * mode for instance), then our decision to issue a PPR message
2978 * may change.
2979 */
2980 period = tinfo->goal.period;
2981 offset = tinfo->goal.offset;
2982 ppr_options = tinfo->goal.ppr_options;
2983 /* Target initiated PPR is not allowed in the SCSI spec */
2984 if (devinfo->role == ROLE_TARGET)
2985 ppr_options = 0;
2986 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2987 &ppr_options, devinfo->role);
2988 dowide = tinfo->curr.width != tinfo->goal.width;
2989 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2990 /*
2991 * Only use PPR if we have options that need it, even if the device
2992 * claims to support it. There might be an expander in the way
2993 * that doesn't.
2994 */
2995 doppr = ppr_options != 0;
2996
2997 if (!dowide && !dosync && !doppr) {
2998 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2999 dosync = tinfo->goal.offset != 0;
3000 }
3001
3002 if (!dowide && !dosync && !doppr) {
3003 /*
3004 * Force async with a WDTR message if we have a wide bus,
3005 * or just issue an SDTR with a 0 offset.
3006 */
3007 if ((ahc->features & AHC_WIDE) != 0)
3008 dowide = 1;
3009 else
3010 dosync = 1;
3011
3012 if (bootverbose) {
3013 ahc_print_devinfo(ahc, devinfo);
48813cf9 3014 printk("Ensuring async\n");
1da177e4
LT		 3015 }
3016 }
3017
3018 /* Target initiated PPR is not allowed in the SCSI spec */
3019 if (devinfo->role == ROLE_TARGET)
3020 doppr = 0;
3021
3022 /*
3023 * Both the PPR message and SDTR message require the
3024 * goal syncrate to be limited to what the target device
3025 * is capable of handling (based on whether an LVD->SE
3026 * expander is on the bus), so combine these two cases.
3027 * Regardless, guarantee that if we are using WDTR and SDTR
3028 * messages that WDTR comes first.
3029 */
3030 if (doppr || (dosync && !dowide)) {
3031
3032 offset = tinfo->goal.offset;
3033 ahc_validate_offset(ahc, tinfo, rate, &offset,
3034 doppr ? tinfo->goal.width
3035 : tinfo->curr.width,
3036 devinfo->role);
3037 if (doppr) {
3038 ahc_construct_ppr(ahc, devinfo, period, offset,
3039 tinfo->goal.width, ppr_options);
3040 } else {
3041 ahc_construct_sdtr(ahc, devinfo, period, offset);
3042 }
3043 } else {
3044 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
3045 }
3046}
3047
3048/*
3049 * Build a synchronous negotiation message in our message
3050 * buffer based on the input parameters.
3051 */
3052static void
3053ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3054 u_int period, u_int offset)
3055{
3056 if (offset == 0)
3057 period = AHC_ASYNC_XFER_PERIOD;
6ea3c0b2
MW		 3058 ahc->msgout_index += spi_populate_sync_msg(
3059 ahc->msgout_buf + ahc->msgout_index, period, offset);
1da177e4
LT		 3060 ahc->msgout_len += 5;
3061 if (bootverbose) {
48813cf9 3062 printk("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
1da177e4
LT		 3063 ahc_name(ahc), devinfo->channel, devinfo->target,
3064 devinfo->lun, period, offset);
3065 }
3066}
3067
3068/*
3069 * Build a wide negotiation message in our message
3070 * buffer based on the input parameters.
3071 */
3072static void
3073ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3074 u_int bus_width)
3075{
6ea3c0b2
MW		 3076 ahc->msgout_index += spi_populate_width_msg(
3077 ahc->msgout_buf + ahc->msgout_index, bus_width);
1da177e4
LT		 3078 ahc->msgout_len += 4;
3079 if (bootverbose) {
48813cf9 3080 printk("(%s:%c:%d:%d): Sending WDTR %x\n",
1da177e4
LT		 3081 ahc_name(ahc), devinfo->channel, devinfo->target,
3082 devinfo->lun, bus_width);
3083 }
3084}
3085
3086/*
3087 * Build a parallel protocol request message in our message
3088 * buffer based on the input parameters.
3089 */
3090static void
3091ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3092 u_int period, u_int offset, u_int bus_width,
3093 u_int ppr_options)
3094{
3095 if (offset == 0)
3096 period = AHC_ASYNC_XFER_PERIOD;
6ea3c0b2
MW		 3097 ahc->msgout_index += spi_populate_ppr_msg(
3098 ahc->msgout_buf + ahc->msgout_index, period, offset,
3099 bus_width, ppr_options);
1da177e4
LT		 3100 ahc->msgout_len += 8;
3101 if (bootverbose) {
48813cf9 3102 printk("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
1da177e4
LT		 3103 "offset %x, ppr_options %x\n", ahc_name(ahc),
3104 devinfo->channel, devinfo->target, devinfo->lun,
3105 bus_width, period, offset, ppr_options);
3106 }
3107}
3108
3109/*
3110 * Clear any active message state.
3111 */
3112static void
3113ahc_clear_msg_state(struct ahc_softc *ahc)
3114{
3115 ahc->msgout_len = 0;
3116 ahc->msgin_index = 0;
3117 ahc->msg_type = MSG_TYPE_NONE;
3118 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
3119 /*
3120 * The target didn't care to respond to our
3121 * message request, so clear ATN.
3122 */
3123 ahc_outb(ahc, CLRSINT1, CLRATNO);
3124 }
3125 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
3126 ahc_outb(ahc, SEQ_FLAGS2,
3127 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
3128}
3129
3130static void
3131ahc_handle_proto_violation(struct ahc_softc *ahc)
3132{
3133 struct ahc_devinfo devinfo;
3134 struct scb *scb;
3135 u_int scbid;
3136 u_int seq_flags;
3137 u_int curphase;
3138 u_int lastphase;
3139 int found;
3140
3141 ahc_fetch_devinfo(ahc, &devinfo);
3142 scbid = ahc_inb(ahc, SCB_TAG);
3143 scb = ahc_lookup_scb(ahc, scbid);
3144 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
3145 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
3146 lastphase = ahc_inb(ahc, LASTPHASE);
3147 if ((seq_flags & NOT_IDENTIFIED) != 0) {
3148
3149 /*
3150 * The reconnecting target either did not send an
3151 * identify message, or did, but we didn't find an SCB
3152 * to match.
3153 */
3154 ahc_print_devinfo(ahc, &devinfo);
48813cf9 3155 printk("Target did not send an IDENTIFY message. "
1da177e4
LT		 3156 "LASTPHASE = 0x%x.\n", lastphase);
3157 scb = NULL;
3158 } else if (scb == NULL) {
3159 /*
3160 * We don't seem to have an SCB active for this
3161 * transaction. Print an error and reset the bus.
3162 */
3163 ahc_print_devinfo(ahc, &devinfo);
48813cf9 3164 printk("No SCB found during protocol violation\n");
1da177e4
LT		 3165 goto proto_violation_reset;
3166 } else {
3167 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
3168 if ((seq_flags & NO_CDB_SENT) != 0) {
3169 ahc_print_path(ahc, scb);
48813cf9 3170 printk("No or incomplete CDB sent to device.\n");
1da177e4
LT		 3171 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
3172 /*
3173 * The target never bothered to provide status to
3174 * us prior to completing the command. Since we don't
3175 * know the disposition of this command, we must attempt
3176 * to abort it. Assert ATN and prepare to send an abort
3177 * message.
3178 */
3179 ahc_print_path(ahc, scb);
48813cf9 3180 printk("Completed command without status.\n");
1da177e4
LT		 3181 } else {
3182 ahc_print_path(ahc, scb);
48813cf9 3183 printk("Unknown protocol violation.\n");
1da177e4
LT		 3184 ahc_dump_card_state(ahc);
3185 }
3186 }
3187 if ((lastphase & ~P_DATAIN_DT) == 0
3188 || lastphase == P_COMMAND) {
3189proto_violation_reset:
3190 /*
3191 * Target either went directly to data/command
3192 * phase or didn't respond to our ATN.
3193 * The only safe thing to do is to blow
3194 * it away with a bus reset.
3195 */
3196 found = ahc_reset_channel(ahc, 'A', TRUE);
48813cf9 3197 printk("%s: Issued Channel %c Bus Reset. "
1da177e4
LT		 3198 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
3199 } else {
3200 /*
3201 * Leave the selection hardware off in case
3202 * this abort attempt will affect yet to
3203 * be sent commands.
3204 */
3205 ahc_outb(ahc, SCSISEQ,
3206 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
3207 ahc_assert_atn(ahc);
3208 ahc_outb(ahc, MSG_OUT, HOST_MSG);
3209 if (scb == NULL) {
3210 ahc_print_devinfo(ahc, &devinfo);
3211 ahc->msgout_buf[0] = MSG_ABORT_TASK;
3212 ahc->msgout_len = 1;
3213 ahc->msgout_index = 0;
3214 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3215 } else {
3216 ahc_print_path(ahc, scb);
3217 scb->flags |= SCB_ABORT;
3218 }
48813cf9 3219 printk("Protocol violation %s. Attempting to abort.\n",
1da177e4
LT		 3220 ahc_lookup_phase_entry(curphase)->phasemsg);
3221 }
3222}
3223
3224/*
3225 * Manual message loop handler.
3226 */
3227static void
3228ahc_handle_message_phase(struct ahc_softc *ahc)
be0d6768 3229{
1da177e4
LT		 3230 struct ahc_devinfo devinfo;
3231 u_int bus_phase;
3232 int end_session;
3233
3234 ahc_fetch_devinfo(ahc, &devinfo);
3235 end_session = FALSE;
3236 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
3237
3238reswitch:
3239 switch (ahc->msg_type) {
3240 case MSG_TYPE_INITIATOR_MSGOUT:
3241 {
3242 int lastbyte;
3243 int phasemis;
3244 int msgdone;
3245
3246 if (ahc->msgout_len == 0)
3247 panic("HOST_MSG_LOOP interrupt with no active message");
3248
3249#ifdef AHC_DEBUG
3250 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3251 ahc_print_devinfo(ahc, &devinfo);
48813cf9 3252 printk("INITIATOR_MSG_OUT");
1da177e4
LT		 3253 }
3254#endif
3255 phasemis = bus_phase != P_MESGOUT;
3256 if (phasemis) {
3257#ifdef AHC_DEBUG
3258 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
48813cf9 3259 printk(" PHASEMIS %s\n",
1da177e4
LT		 3260 ahc_lookup_phase_entry(bus_phase)
3261 ->phasemsg);
3262 }
3263#endif
3264 if (bus_phase == P_MESGIN) {
3265 /*
3266 * Change gears and see if
3267 * this messages is of interest to
3268 * us or should be passed back to
3269 * the sequencer.
3270 */
3271 ahc_outb(ahc, CLRSINT1, CLRATNO);
3272 ahc->send_msg_perror = FALSE;
3273 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
3274 ahc->msgin_index = 0;
3275 goto reswitch;
3276 }
3277 end_session = TRUE;
3278 break;
3279 }
3280
3281 if (ahc->send_msg_perror) {
3282 ahc_outb(ahc, CLRSINT1, CLRATNO);
3283 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
3284#ifdef AHC_DEBUG
3285 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
48813cf9 3286 printk(" byte 0x%x\n", ahc->send_msg_perror);
1da177e4
LT		 3287#endif
3288 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
3289 break;
3290 }
3291
3292 msgdone = ahc->msgout_index == ahc->msgout_len;
3293 if (msgdone) {
3294 /*
3295 * The target has requested a retry.
3296 * Re-assert ATN, reset our message index to
3297 * 0, and try again.
3298 */
3299 ahc->msgout_index = 0;
3300 ahc_assert_atn(ahc);
3301 }
3302
3303 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
3304 if (lastbyte) {
3305 /* Last byte is signified by dropping ATN */
3306 ahc_outb(ahc, CLRSINT1, CLRATNO);
3307 }
3308
3309 /*
3310 * Clear our interrupt status and present
3311 * the next byte on the bus.
3312 */
3313 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
3314#ifdef AHC_DEBUG
3315 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
48813cf9 3316 printk(" byte 0x%x\n",
1da177e4
LT		 3317 ahc->msgout_buf[ahc->msgout_index]);
3318#endif
3319 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
3320 break;
3321 }
3322 case MSG_TYPE_INITIATOR_MSGIN:
3323 {
3324 int phasemis;
3325 int message_done;
3326
3327#ifdef AHC_DEBUG
3328 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3329 ahc_print_devinfo(ahc, &devinfo);
48813cf9 3330 printk("INITIATOR_MSG_IN");
1da177e4
LT		 3331 }
3332#endif
3333 phasemis = bus_phase != P_MESGIN;
3334 if (phasemis) {
3335#ifdef AHC_DEBUG
3336 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
48813cf9 3337 printk(" PHASEMIS %s\n",
1da177e4
LT		 3338 ahc_lookup_phase_entry(bus_phase)
3339 ->phasemsg);
3340 }
3341#endif
3342 ahc->msgin_index = 0;
3343 if (bus_phase == P_MESGOUT
3344 && (ahc->send_msg_perror == TRUE
3345 || (ahc->msgout_len != 0
3346 && ahc->msgout_index == 0))) {
3347 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3348 goto reswitch;
3349 }
3350 end_session = TRUE;
3351 break;
3352 }
3353
3354 /* Pull the byte in without acking it */
3355 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
3356#ifdef AHC_DEBUG
3357 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
48813cf9 3358 printk(" byte 0x%x\n",
1da177e4
LT		 3359 ahc->msgin_buf[ahc->msgin_index]);
3360#endif
3361
3362 message_done = ahc_parse_msg(ahc, &devinfo);
3363
3364 if (message_done) {
3365 /*
3366 * Clear our incoming message buffer in case there
3367 * is another message following this one.
3368 */
3369 ahc->msgin_index = 0;
3370
3371 /*
3372 * If this message illicited a response,
3373 * assert ATN so the target takes us to the
3374 * message out phase.
3375 */
3376 if (ahc->msgout_len != 0) {
3377#ifdef AHC_DEBUG
3378 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3379 ahc_print_devinfo(ahc, &devinfo);
48813cf9 3380 printk("Asserting ATN for response\n");
1da177e4
LT		 3381 }
3382#endif
3383 ahc_assert_atn(ahc);
3384 }
3385 } else
3386 ahc->msgin_index++;
3387
3388 if (message_done == MSGLOOP_TERMINATED) {
3389 end_session = TRUE;
3390 } else {
3391 /* Ack the byte */
3392 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
3393 ahc_inb(ahc, SCSIDATL);
3394 }
3395 break;
3396 }
3397 case MSG_TYPE_TARGET_MSGIN:
3398 {
3399 int msgdone;
3400 int msgout_request;
3401
3402 if (ahc->msgout_len == 0)
3403 panic("Target MSGIN with no active message");
3404
3405 /*
3406 * If we interrupted a mesgout session, the initiator
3407 * will not know this until our first REQ. So, we
3408 * only honor mesgout requests after we've sent our
3409 * first byte.
3410 */
3411 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
3412 && ahc->msgout_index > 0)
3413 msgout_request = TRUE;
3414 else
3415 msgout_request = FALSE;
3416
3417 if (msgout_request) {
3418
3419 /*
3420 * Change gears and see if
3421 * this messages is of interest to
3422 * us or should be passed back to
3423 * the sequencer.
3424 */
3425 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
3426 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
3427 ahc->msgin_index = 0;
3428 /* Dummy read to REQ for first byte */
3429 ahc_inb(ahc, SCSIDATL);
3430 ahc_outb(ahc, SXFRCTL0,
3431 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3432 break;
3433 }
3434
3435 msgdone = ahc->msgout_index == ahc->msgout_len;
3436 if (msgdone) {
3437 ahc_outb(ahc, SXFRCTL0,
3438 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
3439 end_session = TRUE;
3440 break;
3441 }
3442
3443 /*
3444 * Present the next byte on the bus.
3445 */
3446 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3447 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
3448 break;
3449 }
3450 case MSG_TYPE_TARGET_MSGOUT:
3451 {
3452 int lastbyte;
3453 int msgdone;
3454
3455 /*
3456 * The initiator signals that this is
3457 * the last byte by dropping ATN.
3458 */
3459 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
3460
3461 /*
3462 * Read the latched byte, but turn off SPIOEN first
3463 * so that we don't inadvertently cause a REQ for the
3464 * next byte.
3465 */
3466 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
3467 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
3468 msgdone = ahc_parse_msg(ahc, &devinfo);
3469 if (msgdone == MSGLOOP_TERMINATED) {
3470 /*
3471 * The message is *really* done in that it caused
3472 * us to go to bus free. The sequencer has already
3473 * been reset at this point, so pull the ejection
3474 * handle.
3475 */
3476 return;
3477 }
3478
3479 ahc->msgin_index++;
3480
3481 /*
3482 * XXX Read spec about initiator dropping ATN too soon
3483 * and use msgdone to detect it.
3484 */
3485 if (msgdone == MSGLOOP_MSGCOMPLETE) {
3486 ahc->msgin_index = 0;
3487
3488 /*
3489 * If this message illicited a response, transition
3490 * to the Message in phase and send it.
3491 */
3492 if (ahc->msgout_len != 0) {
3493 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
3494 ahc_outb(ahc, SXFRCTL0,
3495 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3496 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3497 ahc->msgin_index = 0;
3498 break;
3499 }
3500 }
3501
3502 if (lastbyte)
3503 end_session = TRUE;
3504 else {
3505 /* Ask for the next byte. */
3506 ahc_outb(ahc, SXFRCTL0,
3507 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3508 }
3509
3510 break;
3511 }
3512 default:
3513 panic("Unknown REQINIT message type");
3514 }
3515
3516 if (end_session) {
3517 ahc_clear_msg_state(ahc);
3518 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
3519 } else
3520 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
3521}
3522
3523/*
3524 * See if we sent a particular extended message to the target.
3525 * If "full" is true, return true only if the target saw the full
3526 * message. If "full" is false, return true if the target saw at
3527 * least the first byte of the message.
3528 */
3529static int
3530ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
3531{
3532 int found;
3533 u_int index;
3534
3535 found = FALSE;
3536 index = 0;
3537
3538 while (index < ahc->msgout_len) {
3539 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
3540 u_int end_index;
3541
3542 end_index = index + 1 + ahc->msgout_buf[index + 1];
3543 if (ahc->msgout_buf[index+2] == msgval
3544 && type == AHCMSG_EXT) {
3545
3546 if (full) {
3547 if (ahc->msgout_index > end_index)
3548 found = TRUE;
3549 } else if (ahc->msgout_index > index)
3550 found = TRUE;
3551 }
3552 index = end_index;
3553 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
3554 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3555
3556 /* Skip tag type and tag id or residue param*/
3557 index += 2;
3558 } else {
3559 /* Single byte message */
3560 if (type == AHCMSG_1B
3561 && ahc->msgout_buf[index] == msgval
3562 && ahc->msgout_index > index)
3563 found = TRUE;
3564 index++;
3565 }
3566
3567 if (found)
3568 break;
3569 }
3570 return (found);
3571}
3572
3573/*
3574 * Wait for a complete incoming message, parse it, and respond accordingly.
3575 */
3576static int
3577ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3578{
3579 struct ahc_initiator_tinfo *tinfo;
3580 struct ahc_tmode_tstate *tstate;
3581 int reject;
3582 int done;
3583 int response;
3584 u_int targ_scsirate;
3585
3586 done = MSGLOOP_IN_PROG;
3587 response = FALSE;
3588 reject = FALSE;
3589 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3590 devinfo->target, &tstate);
3591 targ_scsirate = tinfo->scsirate;
3592
3593 /*
3594 * Parse as much of the message as is available,
3595 * rejecting it if we don't support it. When
3596 * the entire message is available and has been
3597 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3598 * that we have parsed an entire message.
3599 *
3600 * In the case of extended messages, we accept the length
3601 * byte outright and perform more checking once we know the
3602 * extended message type.
3603 */
3604 switch (ahc->msgin_buf[0]) {
3605 case MSG_DISCONNECT:
3606 case MSG_SAVEDATAPOINTER:
3607 case MSG_CMDCOMPLETE:
3608 case MSG_RESTOREPOINTERS:
3609 case MSG_IGN_WIDE_RESIDUE:
3610 /*
3611 * End our message loop as these are messages
3612 * the sequencer handles on its own.
3613 */
3614 done = MSGLOOP_TERMINATED;
3615 break;
3616 case MSG_MESSAGE_REJECT:
3617 response = ahc_handle_msg_reject(ahc, devinfo);
3618 /* FALLTHROUGH */
3619 case MSG_NOOP:
3620 done = MSGLOOP_MSGCOMPLETE;
3621 break;
3622 case MSG_EXTENDED:
3623 {
3624 /* Wait for enough of the message to begin validation */
3625 if (ahc->msgin_index < 2)
3626 break;
3627 switch (ahc->msgin_buf[2]) {
3628 case MSG_EXT_SDTR:
3629 {
d1d7b19d 3630 const struct ahc_syncrate *syncrate;
1da177e4
LT		 3631 u_int period;
3632 u_int ppr_options;
3633 u_int offset;
3634 u_int saved_offset;
3635
3636 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3637 reject = TRUE;
3638 break;
3639 }
3640
3641 /*
3642 * Wait until we have both args before validating
3643 * and acting on this message.
3644 *
3645 * Add one to MSG_EXT_SDTR_LEN to account for
3646 * the extended message preamble.
3647 */
3648 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3649 break;
3650
3651 period = ahc->msgin_buf[3];
3652 ppr_options = 0;
3653 saved_offset = offset = ahc->msgin_buf[4];
3654 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3655 &ppr_options,
3656 devinfo->role);
3657 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3658 targ_scsirate & WIDEXFER,
3659 devinfo->role);
3660 if (bootverbose) {
48813cf9 3661 printk("(%s:%c:%d:%d): Received "
1da177e4
LT		 3662 "SDTR period %x, offset %x\n\t"
3663 "Filtered to period %x, offset %x\n",
3664 ahc_name(ahc), devinfo->channel,
3665 devinfo->target, devinfo->lun,
3666 ahc->msgin_buf[3], saved_offset,
3667 period, offset);
3668 }
3669 ahc_set_syncrate(ahc, devinfo,
3670 syncrate, period,
3671 offset, ppr_options,
3672 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3673 /*paused*/TRUE);
3674
3675 /*
3676 * See if we initiated Sync Negotiation
3677 * and didn't have to fall down to async
3678 * transfers.
3679 */
3680 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3681 /* We started it */
3682 if (saved_offset != offset) {
3683 /* Went too low - force async */
3684 reject = TRUE;
3685 }
3686 } else {
3687 /*
3688 * Send our own SDTR in reply
3689 */
3690 if (bootverbose
3691 && devinfo->role == ROLE_INITIATOR) {
48813cf9 3692 printk("(%s:%c:%d:%d): Target "
1da177e4
LT		 3693 "Initiated SDTR\n",
3694 ahc_name(ahc), devinfo->channel,
3695 devinfo->target, devinfo->lun);
3696 }
3697 ahc->msgout_index = 0;
3698 ahc->msgout_len = 0;
3699 ahc_construct_sdtr(ahc, devinfo,
3700 period, offset);
3701 ahc->msgout_index = 0;
3702 response = TRUE;
3703 }
3704 done = MSGLOOP_MSGCOMPLETE;
3705 break;
3706 }
3707 case MSG_EXT_WDTR:
3708 {
3709 u_int bus_width;
3710 u_int saved_width;
3711 u_int sending_reply;
3712
3713 sending_reply = FALSE;
3714 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3715 reject = TRUE;
3716 break;
3717 }
3718
3719 /*
3720 * Wait until we have our arg before validating
3721 * and acting on this message.
3722 *
3723 * Add one to MSG_EXT_WDTR_LEN to account for
3724 * the extended message preamble.
3725 */
3726 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3727 break;
3728
3729 bus_width = ahc->msgin_buf[3];
3730 saved_width = bus_width;
3731 ahc_validate_width(ahc, tinfo, &bus_width,
3732 devinfo->role);
3733 if (bootverbose) {
48813cf9 3734 printk("(%s:%c:%d:%d): Received WDTR "
1da177e4
LT		 3735 "%x filtered to %x\n",
3736 ahc_name(ahc), devinfo->channel,
3737 devinfo->target, devinfo->lun,
3738 saved_width, bus_width);
3739 }
3740
3741 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3742 /*
3743 * Don't send a WDTR back to the
3744 * target, since we asked first.
3745 * If the width went higher than our
3746 * request, reject it.
3747 */
3748 if (saved_width > bus_width) {
3749 reject = TRUE;
48813cf9 3750 printk("(%s:%c:%d:%d): requested %dBit "
1da177e4
LT		 3751 "transfers. Rejecting...\n",
3752 ahc_name(ahc), devinfo->channel,
3753 devinfo->target, devinfo->lun,
3754 8 * (0x01 << bus_width));
3755 bus_width = 0;
3756 }
3757 } else {
3758 /*
3759 * Send our own WDTR in reply
3760 */
3761 if (bootverbose
3762 && devinfo->role == ROLE_INITIATOR) {
48813cf9 3763 printk("(%s:%c:%d:%d): Target "
1da177e4
LT		 3764 "Initiated WDTR\n",
3765 ahc_name(ahc), devinfo->channel,
3766 devinfo->target, devinfo->lun);
3767 }
3768 ahc->msgout_index = 0;
3769 ahc->msgout_len = 0;
3770 ahc_construct_wdtr(ahc, devinfo, bus_width);
3771 ahc->msgout_index = 0;
3772 response = TRUE;
3773 sending_reply = TRUE;
3774 }
3775 /*
3776 * After a wide message, we are async, but
3777 * some devices don't seem to honor this portion
3778 * of the spec. Force a renegotiation of the
3779 * sync component of our transfer agreement even
3780 * if our goal is async. By updating our width
3781 * after forcing the negotiation, we avoid
3782 * renegotiating for width.
3783 */
3784 ahc_update_neg_request(ahc, devinfo, tstate,
3785 tinfo, AHC_NEG_ALWAYS);
3786 ahc_set_width(ahc, devinfo, bus_width,
3787 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3788 /*paused*/TRUE);
3789 if (sending_reply == FALSE && reject == FALSE) {
3790
3791 /*
3792 * We will always have an SDTR to send.
3793 */
3794 ahc->msgout_index = 0;
3795 ahc->msgout_len = 0;
3796 ahc_build_transfer_msg(ahc, devinfo);
3797 ahc->msgout_index = 0;
3798 response = TRUE;
3799 }
3800 done = MSGLOOP_MSGCOMPLETE;
3801 break;
3802 }
3803 case MSG_EXT_PPR:
3804 {
d1d7b19d 3805 const struct ahc_syncrate *syncrate;
1da177e4
LT		 3806 u_int period;
3807 u_int offset;
3808 u_int bus_width;
3809 u_int ppr_options;
3810 u_int saved_width;
3811 u_int saved_offset;
3812 u_int saved_ppr_options;
3813
3814 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3815 reject = TRUE;
3816 break;
3817 }
3818
3819 /*
3820 * Wait until we have all args before validating
3821 * and acting on this message.
3822 *
3823 * Add one to MSG_EXT_PPR_LEN to account for
3824 * the extended message preamble.
3825 */
3826 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3827 break;
3828
3829 period = ahc->msgin_buf[3];
3830 offset = ahc->msgin_buf[5];
3831 bus_width = ahc->msgin_buf[6];
3832 saved_width = bus_width;
3833 ppr_options = ahc->msgin_buf[7];
3834 /*
3835 * According to the spec, a DT only
3836 * period factor with no DT option
3837 * set implies async.
3838 */
3839 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3840 && period == 9)
3841 offset = 0;
3842 saved_ppr_options = ppr_options;
3843 saved_offset = offset;
3844
3845 /*
3846 * Mask out any options we don't support
3847 * on any controller. Transfer options are
3848 * only available if we are negotiating wide.
3849 */
3850 ppr_options &= MSG_EXT_PPR_DT_REQ;
3851 if (bus_width == 0)
3852 ppr_options = 0;
3853
3854 ahc_validate_width(ahc, tinfo, &bus_width,
3855 devinfo->role);
3856 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3857 &ppr_options,
3858 devinfo->role);
3859 ahc_validate_offset(ahc, tinfo, syncrate,
3860 &offset, bus_width,
3861 devinfo->role);
3862
3863 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3864 /*
3865 * If we are unable to do any of the
3866 * requested options (we went too low),
3867 * then we'll have to reject the message.
3868 */
3869 if (saved_width > bus_width
3870 || saved_offset != offset
3871 || saved_ppr_options != ppr_options) {
3872 reject = TRUE;
3873 period = 0;
3874 offset = 0;
3875 bus_width = 0;
3876 ppr_options = 0;
3877 syncrate = NULL;
3878 }
3879 } else {
3880 if (devinfo->role != ROLE_TARGET)
48813cf9 3881 printk("(%s:%c:%d:%d): Target "
1da177e4
LT		 3882 "Initiated PPR\n",
3883 ahc_name(ahc), devinfo->channel,
3884 devinfo->target, devinfo->lun);
3885 else
48813cf9 3886 printk("(%s:%c:%d:%d): Initiator "
1da177e4
LT		 3887 "Initiated PPR\n",
3888 ahc_name(ahc), devinfo->channel,
3889 devinfo->target, devinfo->lun);
3890 ahc->msgout_index = 0;
3891 ahc->msgout_len = 0;
3892 ahc_construct_ppr(ahc, devinfo, period, offset,
3893 bus_width, ppr_options);
3894 ahc->msgout_index = 0;
3895 response = TRUE;
3896 }
3897 if (bootverbose) {
48813cf9 3898 printk("(%s:%c:%d:%d): Received PPR width %x, "
1da177e4
LT		 3899 "period %x, offset %x,options %x\n"
3900 "\tFiltered to width %x, period %x, "
3901 "offset %x, options %x\n",
3902 ahc_name(ahc), devinfo->channel,
3903 devinfo->target, devinfo->lun,
3904 saved_width, ahc->msgin_buf[3],
3905 saved_offset, saved_ppr_options,
3906 bus_width, period, offset, ppr_options);
3907 }
3908 ahc_set_width(ahc, devinfo, bus_width,
3909 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3910 /*paused*/TRUE);
3911 ahc_set_syncrate(ahc, devinfo,
3912 syncrate, period,
3913 offset, ppr_options,
3914 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3915 /*paused*/TRUE);
3916 done = MSGLOOP_MSGCOMPLETE;
3917 break;
3918 }
3919 default:
3920 /* Unknown extended message. Reject it. */
3921 reject = TRUE;
3922 break;
3923 }
3924 break;
3925 }
3926#ifdef AHC_TARGET_MODE
3927 case MSG_BUS_DEV_RESET:
3928 ahc_handle_devreset(ahc, devinfo,
3929 CAM_BDR_SENT,
3930 "Bus Device Reset Received",
3931 /*verbose_level*/0);
3932 ahc_restart(ahc);
3933 done = MSGLOOP_TERMINATED;
3934 break;
3935 case MSG_ABORT_TAG:
3936 case MSG_ABORT:
3937 case MSG_CLEAR_QUEUE:
3938 {
3939 int tag;
3940
3941 /* Target mode messages */
3942 if (devinfo->role != ROLE_TARGET) {
3943 reject = TRUE;
3944 break;
3945 }
3946 tag = SCB_LIST_NULL;
3947 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3948 tag = ahc_inb(ahc, INITIATOR_TAG);
3949 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3950 devinfo->lun, tag, ROLE_TARGET,
3951 CAM_REQ_ABORTED);
3952
3953 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3954 if (tstate != NULL) {
3955 struct ahc_tmode_lstate* lstate;
3956
3957 lstate = tstate->enabled_luns[devinfo->lun];
3958 if (lstate != NULL) {
3959 ahc_queue_lstate_event(ahc, lstate,
3960 devinfo->our_scsiid,
3961 ahc->msgin_buf[0],
3962 /*arg*/tag);
3963 ahc_send_lstate_events(ahc, lstate);
3964 }
3965 }
3966 ahc_restart(ahc);
3967 done = MSGLOOP_TERMINATED;
3968 break;
3969 }
3970#endif
3971 case MSG_TERM_IO_PROC:
3972 default:
3973 reject = TRUE;
3974 break;
3975 }
3976
3977 if (reject) {
3978 /*
3979 * Setup to reject the message.
3980 */
3981 ahc->msgout_index = 0;
3982 ahc->msgout_len = 1;
3983 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3984 done = MSGLOOP_MSGCOMPLETE;
3985 response = TRUE;
3986 }
3987
3988 if (done != MSGLOOP_IN_PROG && !response)
3989 /* Clear the outgoing message buffer */
3990 ahc->msgout_len = 0;
3991
3992 return (done);
3993}
3994
3995/*
3996 * Process a message reject message.
3997 */
3998static int
3999ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
4000{
4001 /*
4002 * What we care about here is if we had an
4003 * outstanding SDTR or WDTR message for this
4004 * target. If we did, this is a signal that
4005 * the target is refusing negotiation.
4006 */
4007 struct scb *scb;
4008 struct ahc_initiator_tinfo *tinfo;
4009 struct ahc_tmode_tstate *tstate;
4010 u_int scb_index;
4011 u_int last_msg;
4012 int response = 0;
4013
4014 scb_index = ahc_inb(ahc, SCB_TAG);
4015 scb = ahc_lookup_scb(ahc, scb_index);
4016 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
4017 devinfo->our_scsiid,
4018 devinfo->target, &tstate);
4019 /* Might be necessary */
4020 last_msg = ahc_inb(ahc, LAST_MSG);
4021
4022 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
4023 /*
4024 * Target does not support the PPR message.
4025 * Attempt to negotiate SPI-2 style.
4026 */
4027 if (bootverbose) {
48813cf9 4028 printk("(%s:%c:%d:%d): PPR Rejected. "
1da177e4
LT		 4029 "Trying WDTR/SDTR\n",
4030 ahc_name(ahc), devinfo->channel,
4031 devinfo->target, devinfo->lun);
4032 }
4033 tinfo->goal.ppr_options = 0;
4034 tinfo->curr.transport_version = 2;
4035 tinfo->goal.transport_version = 2;
4036 ahc->msgout_index = 0;
4037 ahc->msgout_len = 0;
4038 ahc_build_transfer_msg(ahc, devinfo);
4039 ahc->msgout_index = 0;
4040 response = 1;
4041 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
4042
4043 /* note 8bit xfers */
48813cf9 4044 printk("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
1da177e4
LT		 4045 "8bit transfers\n", ahc_name(ahc),
4046 devinfo->channel, devinfo->target, devinfo->lun);
4047 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4048 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
4049 /*paused*/TRUE);
4050 /*
4051 * No need to clear the sync rate. If the target
4052 * did not accept the command, our syncrate is
4053 * unaffected. If the target started the negotiation,
4054 * but rejected our response, we already cleared the
4055 * sync rate before sending our WDTR.
4056 */
4057 if (tinfo->goal.offset != tinfo->curr.offset) {
4058
4059 /* Start the sync negotiation */
4060 ahc->msgout_index = 0;
4061 ahc->msgout_len = 0;
4062 ahc_build_transfer_msg(ahc, devinfo);
4063 ahc->msgout_index = 0;
4064 response = 1;
4065 }
4066 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
4067 /* note asynch xfers and clear flag */
4068 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
4069 /*offset*/0, /*ppr_options*/0,
4070 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
4071 /*paused*/TRUE);
48813cf9 4072 printk("(%s:%c:%d:%d): refuses synchronous negotiation. "
1da177e4
LT		 4073 "Using asynchronous transfers\n",
4074 ahc_name(ahc), devinfo->channel,
4075 devinfo->target, devinfo->lun);
4076 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
4077 int tag_type;
4078 int mask;
4079
4080 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
4081
4082 if (tag_type == MSG_SIMPLE_TASK) {
48813cf9 4083 printk("(%s:%c:%d:%d): refuses tagged commands. "
1da177e4
LT		 4084 "Performing non-tagged I/O\n", ahc_name(ahc),
4085 devinfo->channel, devinfo->target, devinfo->lun);
9080063f 4086 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_NONE);
1da177e4
LT		 4087 mask = ~0x23;
4088 } else {
48813cf9 4089 printk("(%s:%c:%d:%d): refuses %s tagged commands. "
1da177e4
LT		 4090 "Performing simple queue tagged I/O only\n",
4091 ahc_name(ahc), devinfo->channel, devinfo->target,
4092 devinfo->lun, tag_type == MSG_ORDERED_TASK
4093 ? "ordered" : "head of queue");
9080063f 4094 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_BASIC);
1da177e4
LT		 4095 mask = ~0x03;
4096 }
4097
4098 /*
4099 * Resend the identify for this CCB as the target
4100 * may believe that the selection is invalid otherwise.
4101 */
4102 ahc_outb(ahc, SCB_CONTROL,
4103 ahc_inb(ahc, SCB_CONTROL) & mask);
4104 scb->hscb->control &= mask;
4105 ahc_set_transaction_tag(scb, /*enabled*/FALSE,
4106 /*type*/MSG_SIMPLE_TASK);
4107 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
4108 ahc_assert_atn(ahc);
4109
4110 /*
4111 * This transaction is now at the head of
4112 * the untagged queue for this target.
4113 */
4114 if ((ahc->flags & AHC_SCB_BTT) == 0) {
4115 struct scb_tailq *untagged_q;
4116
4117 untagged_q =
4118 &(ahc->untagged_queues[devinfo->target_offset]);
4119 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
4120 scb->flags |= SCB_UNTAGGEDQ;
4121 }
4122 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
4123 scb->hscb->tag);
4124
4125 /*
4126 * Requeue all tagged commands for this target
25985edc 4127 * currently in our possession so they can be
1da177e4
LT		 4128 * converted to untagged commands.
4129 */
4130 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
4131 SCB_GET_CHANNEL(ahc, scb),
4132 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
4133 ROLE_INITIATOR, CAM_REQUEUE_REQ,
4134 SEARCH_COMPLETE);
4135 } else {
4136 /*
4137 * Otherwise, we ignore it.
4138 */
48813cf9 4139 printk("%s:%c:%d: Message reject for %x -- ignored\n",
1da177e4
LT		 4140 ahc_name(ahc), devinfo->channel, devinfo->target,
4141 last_msg);
4142 }
4143 return (response);
4144}
4145
4146/*
4147 * Process an ingnore wide residue message.
4148 */
4149static void
4150ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
4151{
4152 u_int scb_index;
4153 struct scb *scb;
4154
4155 scb_index = ahc_inb(ahc, SCB_TAG);
4156 scb = ahc_lookup_scb(ahc, scb_index);
4157 /*
4158 * XXX Actually check data direction in the sequencer?
4159 * Perhaps add datadir to some spare bits in the hscb?
4160 */
4161 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
4162 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
4163 /*
4164 * Ignore the message if we haven't
4165 * seen an appropriate data phase yet.
4166 */
4167 } else {
4168 /*
4169 * If the residual occurred on the last
4170 * transfer and the transfer request was
4171 * expected to end on an odd count, do
4172 * nothing. Otherwise, subtract a byte
4173 * and update the residual count accordingly.
4174 */
4175 uint32_t sgptr;
4176
4177 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
4178 if ((sgptr & SG_LIST_NULL) != 0
4179 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
4180 /*
4181 * If the residual occurred on the last
4182 * transfer and the transfer request was
4183 * expected to end on an odd count, do
4184 * nothing.
4185 */
4186 } else {
4187 struct ahc_dma_seg *sg;
4188 uint32_t data_cnt;
4189 uint32_t data_addr;
4190 uint32_t sglen;
4191
4192 /* Pull in all of the sgptr */
4193 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
4194 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
4195
4196 if ((sgptr & SG_LIST_NULL) != 0) {
4197 /*
4198 * The residual data count is not updated
4199 * for the command run to completion case.
4200 * Explicitly zero the count.
4201 */
4202 data_cnt &= ~AHC_SG_LEN_MASK;
4203 }
4204
4205 data_addr = ahc_inl(ahc, SHADDR);
4206
4207 data_cnt += 1;
4208 data_addr -= 1;
4209 sgptr &= SG_PTR_MASK;
4210
4211 sg = ahc_sg_bus_to_virt(scb, sgptr);
4212
4213 /*
4214 * The residual sg ptr points to the next S/G
4215 * to load so we must go back one.
4216 */
4217 sg--;
4218 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
4219 if (sg != scb->sg_list
4220 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
4221
4222 sg--;
4223 sglen = ahc_le32toh(sg->len);
4224 /*
4225 * Preserve High Address and SG_LIST bits
4226 * while setting the count to 1.
4227 */
4228 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
4229 data_addr = ahc_le32toh(sg->addr)
4230 + (sglen & AHC_SG_LEN_MASK) - 1;
4231
4232 /*
4233 * Increment sg so it points to the
4234 * "next" sg.
4235 */
4236 sg++;
4237 sgptr = ahc_sg_virt_to_bus(scb, sg);
4238 }
4239 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
4240 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
4241 /*
4242 * Toggle the "oddness" of the transfer length
4243 * to handle this mid-transfer ignore wide
4244 * residue. This ensures that the oddness is
4245 * correct for subsequent data transfers.
4246 */
4247 ahc_outb(ahc, SCB_LUN,
4248 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
4249 }
4250 }
4251}
4252
4253
4254/*
4255 * Reinitialize the data pointers for the active transfer
4256 * based on its current residual.
4257 */
4258static void
4259ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
4260{
4261 struct scb *scb;
4262 struct ahc_dma_seg *sg;
4263 u_int scb_index;
4264 uint32_t sgptr;
4265 uint32_t resid;
4266 uint32_t dataptr;
4267
4268 scb_index = ahc_inb(ahc, SCB_TAG);
4269 scb = ahc_lookup_scb(ahc, scb_index);
4270 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
4271 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
4272 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
4273 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
4274
4275 sgptr &= SG_PTR_MASK;
4276 sg = ahc_sg_bus_to_virt(scb, sgptr);
4277
4278 /* The residual sg_ptr always points to the next sg */
4279 sg--;
4280
4281 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
4282 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
4283 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
4284
4285 dataptr = ahc_le32toh(sg->addr)
4286 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
4287 - resid;
4288 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
4289 u_int dscommand1;
4290
4291 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
4292 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
4293 ahc_outb(ahc, HADDR,
4294 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
4295 ahc_outb(ahc, DSCOMMAND1, dscommand1);
4296 }
4297 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
4298 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
4299 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
4300 ahc_outb(ahc, HADDR, dataptr);
4301 ahc_outb(ahc, HCNT + 2, resid >> 16);
4302 ahc_outb(ahc, HCNT + 1, resid >> 8);
4303 ahc_outb(ahc, HCNT, resid);
4304 if ((ahc->features & AHC_ULTRA2) == 0) {
4305 ahc_outb(ahc, STCNT + 2, resid >> 16);
4306 ahc_outb(ahc, STCNT + 1, resid >> 8);
4307 ahc_outb(ahc, STCNT, resid);
4308 }
4309}
4310
4311/*
4312 * Handle the effects of issuing a bus device reset message.
4313 */
4314static void
4315ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
4316 cam_status status, char *message, int verbose_level)
4317{
4318#ifdef AHC_TARGET_MODE
4319 struct ahc_tmode_tstate* tstate;
4320 u_int lun;
4321#endif
4322 int found;
4323
4324 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
4325 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
4326 status);
4327
4328#ifdef AHC_TARGET_MODE
4329 /*
4330 * Send an immediate notify ccb to all target mord peripheral
4331 * drivers affected by this action.
4332 */
4333 tstate = ahc->enabled_targets[devinfo->our_scsiid];
4334 if (tstate != NULL) {
4335 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
4336 struct ahc_tmode_lstate* lstate;
4337
4338 lstate = tstate->enabled_luns[lun];
4339 if (lstate == NULL)
4340 continue;
4341
4342 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
4343 MSG_BUS_DEV_RESET, /*arg*/0);
4344 ahc_send_lstate_events(ahc, lstate);
4345 }
4346 }
4347#endif
4348
4349 /*
4350 * Go back to async/narrow transfers and renegotiate.
4351 */
4352 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4353 AHC_TRANS_CUR, /*paused*/TRUE);
4354 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
4355 /*period*/0, /*offset*/0, /*ppr_options*/0,
4356 AHC_TRANS_CUR, /*paused*/TRUE);
4357
79778a27
JB		 4358 if (status != CAM_SEL_TIMEOUT)
4359 ahc_send_async(ahc, devinfo->channel, devinfo->target,
9080063f 4360 CAM_LUN_WILDCARD, AC_SENT_BDR);
1da177e4
LT		 4361
4362 if (message != NULL
4363 && (verbose_level <= bootverbose))
48813cf9 4364 printk("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
1da177e4
LT		 4365 message, devinfo->channel, devinfo->target, found);
4366}
4367
4368#ifdef AHC_TARGET_MODE
4369static void
4370ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
4371 struct scb *scb)
4372{
4373
4374 /*
4375 * To facilitate adding multiple messages together,
4376 * each routine should increment the index and len
4377 * variables instead of setting them explicitly.
4378 */
4379 ahc->msgout_index = 0;
4380 ahc->msgout_len = 0;
4381
4382 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
4383 ahc_build_transfer_msg(ahc, devinfo);
4384 else
4385 panic("ahc_intr: AWAITING target message with no message");
4386
4387 ahc->msgout_index = 0;
4388 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
4389}
4390#endif
4391/**************************** Initialization **********************************/
4392/*
4393 * Allocate a controller structure for a new device
4394 * and perform initial initializion.
4395 */
4396struct ahc_softc *
4397ahc_alloc(void *platform_arg, char *name)
4398{
4399 struct ahc_softc *ahc;
4400 int i;
4401
4402#ifndef __FreeBSD__
48813cf9 4403 ahc = kmalloc(sizeof(*ahc), GFP_ATOMIC);
1da177e4 4404 if (!ahc) {
48813cf9
PE		 4405 printk("aic7xxx: cannot malloc softc!\n");
4406 kfree(name);
1da177e4
LT		 4407 return NULL;
4408 }
4409#else
4410 ahc = device_get_softc((device_t)platform_arg);
4411#endif
4412 memset(ahc, 0, sizeof(*ahc));
48813cf9 4413 ahc->seep_config = kmalloc(sizeof(*ahc->seep_config), GFP_ATOMIC);
1da177e4
LT		 4414 if (ahc->seep_config == NULL) {
4415#ifndef __FreeBSD__
48813cf9 4416 kfree(ahc);
1da177e4 4417#endif
48813cf9 4418 kfree(name);
1da177e4
LT		 4419 return (NULL);
4420 }
4421 LIST_INIT(&ahc->pending_scbs);
4422 /* We don't know our unit number until the OSM sets it */
4423 ahc->name = name;
4424 ahc->unit = -1;
4425 ahc->description = NULL;
4426 ahc->channel = 'A';
4427 ahc->channel_b = 'B';
4428 ahc->chip = AHC_NONE;
4429 ahc->features = AHC_FENONE;
4430 ahc->bugs = AHC_BUGNONE;
4431 ahc->flags = AHC_FNONE;
4432 /*
4433 * Default to all error reporting enabled with the
4434 * sequencer operating at its fastest speed.
4435 * The bus attach code may modify this.
4436 */
4437 ahc->seqctl = FASTMODE;
4438
4439 for (i = 0; i < AHC_NUM_TARGETS; i++)
4440 TAILQ_INIT(&ahc->untagged_queues[i]);
4441 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
4442 ahc_free(ahc);
4443 ahc = NULL;
4444 }
4445 return (ahc);
4446}
4447
4448int
4449ahc_softc_init(struct ahc_softc *ahc)
4450{
4451
4452 /* The IRQMS bit is only valid on VL and EISA chips */
4453 if ((ahc->chip & AHC_PCI) == 0)
4454 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
4455 else
4456 ahc->unpause = 0;
4457 ahc->pause = ahc->unpause | PAUSE;
4458 /* XXX The shared scb data stuff should be deprecated */
4459 if (ahc->scb_data == NULL) {
114fc1d9 4460 ahc->scb_data = kzalloc(sizeof(*ahc->scb_data), GFP_ATOMIC);
1da177e4
LT		 4461 if (ahc->scb_data == NULL)
4462 return (ENOMEM);
1da177e4
LT		 4463 }
4464
4465 return (0);
4466}
4467
1da177e4
LT		 4468void
4469ahc_set_unit(struct ahc_softc *ahc, int unit)
4470{
4471 ahc->unit = unit;
4472}
4473
4474void
4475ahc_set_name(struct ahc_softc *ahc, char *name)
4476{
4477 if (ahc->name != NULL)
48813cf9 4478 kfree(ahc->name);
1da177e4
LT		 4479 ahc->name = name;
4480}
4481
4482void
4483ahc_free(struct ahc_softc *ahc)
4484{
4485 int i;
4486
4487 switch (ahc->init_level) {
4488 default:
4489 case 5:
4490 ahc_shutdown(ahc);
4491 /* FALLTHROUGH */
4492 case 4:
4493 ahc_dmamap_unload(ahc, ahc->shared_data_dmat,
4494 ahc->shared_data_dmamap);
4495 /* FALLTHROUGH */
4496 case 3:
4497 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
4498 ahc->shared_data_dmamap);
4499 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat,
4500 ahc->shared_data_dmamap);
4501 /* FALLTHROUGH */
4502 case 2:
4503 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat);
4504 case 1:
1da177e4
LT		 4505 break;
4506 case 0:
4507 break;
4508 }
4509
1da177e4
LT		 4510 ahc_platform_free(ahc);
4511 ahc_fini_scbdata(ahc);
4512 for (i = 0; i < AHC_NUM_TARGETS; i++) {
4513 struct ahc_tmode_tstate *tstate;
4514
4515 tstate = ahc->enabled_targets[i];
4516 if (tstate != NULL) {
4517#ifdef AHC_TARGET_MODE
4518 int j;
4519
4520 for (j = 0; j < AHC_NUM_LUNS; j++) {
4521 struct ahc_tmode_lstate *lstate;
4522
4523 lstate = tstate->enabled_luns[j];
4524 if (lstate != NULL) {
4525 xpt_free_path(lstate->path);
48813cf9 4526 kfree(lstate);
1da177e4
LT		 4527 }
4528 }
4529#endif
48813cf9 4530 kfree(tstate);
1da177e4
LT		 4531 }
4532 }
4533#ifdef AHC_TARGET_MODE
4534 if (ahc->black_hole != NULL) {
4535 xpt_free_path(ahc->black_hole->path);
48813cf9 4536 kfree(ahc->black_hole);
1da177e4
LT		 4537 }
4538#endif
4539 if (ahc->name != NULL)
48813cf9 4540 kfree(ahc->name);
1da177e4 4541 if (ahc->seep_config != NULL)
48813cf9 4542 kfree(ahc->seep_config);
1da177e4 4543#ifndef __FreeBSD__
48813cf9 4544 kfree(ahc);
1da177e4
LT		 4545#endif
4546 return;
4547}
4548
d1d7b19d 4549static void
1da177e4
LT		 4550ahc_shutdown(void *arg)
4551{
4552 struct ahc_softc *ahc;
4553 int i;
4554
4555 ahc = (struct ahc_softc *)arg;
4556
4557 /* This will reset most registers to 0, but not all */
4558 ahc_reset(ahc, /*reinit*/FALSE);
4559 ahc_outb(ahc, SCSISEQ, 0);
4560 ahc_outb(ahc, SXFRCTL0, 0);
4561 ahc_outb(ahc, DSPCISTATUS, 0);
4562
4563 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4564 ahc_outb(ahc, i, 0);
4565}
4566
4567/*
4568 * Reset the controller and record some information about it
4569 * that is only available just after a reset. If "reinit" is
25985edc 4570 * non-zero, this reset occurred after initial configuration
1da177e4
LT		 4571 * and the caller requests that the chip be fully reinitialized
4572 * to a runable state. Chip interrupts are *not* enabled after
4573 * a reinitialization. The caller must enable interrupts via
4574 * ahc_intr_enable().
4575 */
4576int
4577ahc_reset(struct ahc_softc *ahc, int reinit)
4578{
4579 u_int sblkctl;
4580 u_int sxfrctl1_a, sxfrctl1_b;
4581 int error;
4582 int wait;
4583
4584 /*
4585 * Preserve the value of the SXFRCTL1 register for all channels.
4586 * It contains settings that affect termination and we don't want
4587 * to disturb the integrity of the bus.
4588 */
4589 ahc_pause(ahc);
1da177e4
LT		 4590 sxfrctl1_b = 0;
4591 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4592 u_int sblkctl;
4593
4594 /*
4595 * Save channel B's settings in case this chip
4596 * is setup for TWIN channel operation.
4597 */
4598 sblkctl = ahc_inb(ahc, SBLKCTL);
4599 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4600 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4601 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4602 }
4603 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4604
4605 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4606
4607 /*
4608 * Ensure that the reset has finished. We delay 1000us
4609 * prior to reading the register to make sure the chip
4610 * has sufficiently completed its reset to handle register
4611 * accesses.
4612 */
4613 wait = 1000;
4614 do {
4615 ahc_delay(1000);
4616 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4617
4618 if (wait == 0) {
48813cf9 4619 printk("%s: WARNING - Failed chip reset! "
1da177e4
LT		 4620 "Trying to initialize anyway.\n", ahc_name(ahc));
4621 }
4622 ahc_outb(ahc, HCNTRL, ahc->pause);
4623
4624 /* Determine channel configuration */
4625 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4626 /* No Twin Channel PCI cards */
4627 if ((ahc->chip & AHC_PCI) != 0)
4628 sblkctl &= ~SELBUSB;
4629 switch (sblkctl) {
4630 case 0:
4631 /* Single Narrow Channel */
4632 break;
4633 case 2:
4634 /* Wide Channel */
4635 ahc->features |= AHC_WIDE;
4636 break;
4637 case 8:
4638 /* Twin Channel */
4639 ahc->features |= AHC_TWIN;
4640 break;
4641 default:
48813cf9 4642 printk(" Unsupported adapter type. Ignoring\n");
1da177e4
LT		 4643 return(-1);
4644 }
4645
4646 /*
4647 * Reload sxfrctl1.
4648 *
4649 * We must always initialize STPWEN to 1 before we
4650 * restore the saved values. STPWEN is initialized
4651 * to a tri-state condition which can only be cleared
4652 * by turning it on.
4653 */
4654 if ((ahc->features & AHC_TWIN) != 0) {
4655 u_int sblkctl;
4656
4657 sblkctl = ahc_inb(ahc, SBLKCTL);
4658 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4659 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4660 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4661 }
4662 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4663
4664 error = 0;
4665 if (reinit != 0)
4666 /*
4667 * If a recovery action has forced a chip reset,
4668 * re-initialize the chip to our liking.
4669 */
4670 error = ahc->bus_chip_init(ahc);
4671#ifdef AHC_DUMP_SEQ
4672 else
4673 ahc_dumpseq(ahc);
4674#endif
4675
4676 return (error);
4677}
4678
4679/*
4680 * Determine the number of SCBs available on the controller
4681 */
4682int
4683ahc_probe_scbs(struct ahc_softc *ahc) {
4684 int i;
4685
4686 for (i = 0; i < AHC_SCB_MAX; i++) {
4687
4688 ahc_outb(ahc, SCBPTR, i);
4689 ahc_outb(ahc, SCB_BASE, i);
4690 if (ahc_inb(ahc, SCB_BASE) != i)
4691 break;
4692 ahc_outb(ahc, SCBPTR, 0);
4693 if (ahc_inb(ahc, SCB_BASE) != 0)
4694 break;
4695 }
4696 return (i);
4697}
4698
4699static void
4700ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4701{
4702 dma_addr_t *baddr;
4703
4704 baddr = (dma_addr_t *)arg;
4705 *baddr = segs->ds_addr;
4706}
4707
4708static void
4709ahc_build_free_scb_list(struct ahc_softc *ahc)
4710{
4711 int scbsize;
4712 int i;
4713
4714 scbsize = 32;
4715 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4716 scbsize = 64;
4717
4718 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4719 int j;
4720
4721 ahc_outb(ahc, SCBPTR, i);
4722
4723 /*
4724 * Touch all SCB bytes to avoid parity errors
4725 * should one of our debugging routines read
4726 * an otherwise uninitiatlized byte.
4727 */
4728 for (j = 0; j < scbsize; j++)
4729 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4730
4731 /* Clear the control byte. */
4732 ahc_outb(ahc, SCB_CONTROL, 0);
4733
4734 /* Set the next pointer */
4735 if ((ahc->flags & AHC_PAGESCBS) != 0)
4736 ahc_outb(ahc, SCB_NEXT, i+1);
4737 else
4738 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4739
4740 /* Make the tag number, SCSIID, and lun invalid */
4741 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4742 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4743 ahc_outb(ahc, SCB_LUN, 0xFF);
4744 }
4745
4746 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4747 /* SCB 0 heads the free list. */
4748 ahc_outb(ahc, FREE_SCBH, 0);
4749 } else {
4750 /* No free list. */
4751 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4752 }
4753
4754 /* Make sure that the last SCB terminates the free list */
4755 ahc_outb(ahc, SCBPTR, i-1);
4756 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4757}
4758
4759static int
4760ahc_init_scbdata(struct ahc_softc *ahc)
4761{
4762 struct scb_data *scb_data;
4763
4764 scb_data = ahc->scb_data;
4765 SLIST_INIT(&scb_data->free_scbs);
4766 SLIST_INIT(&scb_data->sg_maps);
4767
4768 /* Allocate SCB resources */
6396bb22
KC		 4769 scb_data->scbarray = kcalloc(AHC_SCB_MAX_ALLOC, sizeof(struct scb),
4770 GFP_ATOMIC);
1da177e4
LT		 4771 if (scb_data->scbarray == NULL)
4772 return (ENOMEM);
1da177e4
LT		 4773
4774 /* Determine the number of hardware SCBs and initialize them */
4775
4776 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4777 if (ahc->scb_data->maxhscbs == 0) {
48813cf9 4778 printk("%s: No SCB space found\n", ahc_name(ahc));
1da177e4
LT		 4779 return (ENXIO);
4780 }
4781
4782 /*
4783 * Create our DMA tags. These tags define the kinds of device
4784 * accessible memory allocations and memory mappings we will
4785 * need to perform during normal operation.
4786 *
4787 * Unless we need to further restrict the allocation, we rely
4788 * on the restrictions of the parent dmat, hence the common
4789 * use of MAXADDR and MAXSIZE.
4790 */
4791
4792 /* DMA tag for our hardware scb structures */
4793 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4794 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4795 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4796 /*highaddr*/BUS_SPACE_MAXADDR,
4797 /*filter*/NULL, /*filterarg*/NULL,
4798 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4799 /*nsegments*/1,
4800 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4801 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4802 goto error_exit;
4803 }
4804
4805 scb_data->init_level++;
4806
4807 /* Allocation for our hscbs */
4808 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
4809 (void **)&scb_data->hscbs,
4810 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
4811 goto error_exit;
4812 }
4813
4814 scb_data->init_level++;
4815
4816 /* And permanently map them */
4817 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4818 scb_data->hscbs,
4819 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4820 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4821
4822 scb_data->init_level++;
4823
4824 /* DMA tag for our sense buffers */
4825 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4826 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4827 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4828 /*highaddr*/BUS_SPACE_MAXADDR,
4829 /*filter*/NULL, /*filterarg*/NULL,
4830 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4831 /*nsegments*/1,
4832 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4833 /*flags*/0, &scb_data->sense_dmat) != 0) {
4834 goto error_exit;
4835 }
4836
4837 scb_data->init_level++;
4838
4839 /* Allocate them */
4840 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat,
4841 (void **)&scb_data->sense,
4842 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4843 goto error_exit;
4844 }
4845
4846 scb_data->init_level++;
4847
4848 /* And permanently map them */
4849 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4850 scb_data->sense,
4851 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4852 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4853
4854 scb_data->init_level++;
4855
4856 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4857 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4858 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4859 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4860 /*highaddr*/BUS_SPACE_MAXADDR,
4861 /*filter*/NULL, /*filterarg*/NULL,
4862 PAGE_SIZE, /*nsegments*/1,
4863 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4864 /*flags*/0, &scb_data->sg_dmat) != 0) {
4865 goto error_exit;
4866 }
4867
4868 scb_data->init_level++;
4869
4870 /* Perform initial CCB allocation */
4871 memset(scb_data->hscbs, 0,
4872 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4873 ahc_alloc_scbs(ahc);
4874
4875 if (scb_data->numscbs == 0) {
48813cf9 4876 printk("%s: ahc_init_scbdata - "
1da177e4
LT		 4877 "Unable to allocate initial scbs\n",
4878 ahc_name(ahc));
4879 goto error_exit;
4880 }
4881
4882 /*
4883 * Reserve the next queued SCB.
4884 */
4885 ahc->next_queued_scb = ahc_get_scb(ahc);
4886
4887 /*
25985edc 4888 * Note that we were successful
1da177e4
LT		 4889 */
4890 return (0);
4891
4892error_exit:
4893
4894 return (ENOMEM);
4895}
4896
4897static void
4898ahc_fini_scbdata(struct ahc_softc *ahc)
4899{
4900 struct scb_data *scb_data;
4901
4902 scb_data = ahc->scb_data;
4903 if (scb_data == NULL)
4904 return;
4905
4906 switch (scb_data->init_level) {
4907 default:
4908 case 7:
4909 {
4910 struct sg_map_node *sg_map;
4911
4912 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4913 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4914 ahc_dmamap_unload(ahc, scb_data->sg_dmat,
4915 sg_map->sg_dmamap);
4916 ahc_dmamem_free(ahc, scb_data->sg_dmat,
4917 sg_map->sg_vaddr,
4918 sg_map->sg_dmamap);
48813cf9 4919 kfree(sg_map);
1da177e4
LT		 4920 }
4921 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat);
4922 }
e2e80164 4923 /* fall through */
1da177e4
LT		 4924 case 6:
4925 ahc_dmamap_unload(ahc, scb_data->sense_dmat,
4926 scb_data->sense_dmamap);
e2e80164 4927 /* fall through */
1da177e4
LT		 4928 case 5:
4929 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4930 scb_data->sense_dmamap);
4931 ahc_dmamap_destroy(ahc, scb_data->sense_dmat,
4932 scb_data->sense_dmamap);
e2e80164 4933 /* fall through */
1da177e4
LT		 4934 case 4:
4935 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat);
e2e80164 4936 /* fall through */
1da177e4
LT		 4937 case 3:
4938 ahc_dmamap_unload(ahc, scb_data->hscb_dmat,
4939 scb_data->hscb_dmamap);
e2e80164 4940 /* fall through */
1da177e4
LT		 4941 case 2:
4942 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4943 scb_data->hscb_dmamap);
4944 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat,
4945 scb_data->hscb_dmamap);
e2e80164 4946 /* fall through */
1da177e4
LT		 4947 case 1:
4948 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4949 break;
4950 case 0:
4951 break;
4952 }
4953 if (scb_data->scbarray != NULL)
48813cf9 4954 kfree(scb_data->scbarray);
1da177e4
LT		 4955}
4956
d1d7b19d 4957static void
1da177e4
LT		 4958ahc_alloc_scbs(struct ahc_softc *ahc)
4959{
4960 struct scb_data *scb_data;
4961 struct scb *next_scb;
4962 struct sg_map_node *sg_map;
4963 dma_addr_t physaddr;
4964 struct ahc_dma_seg *segs;
4965 int newcount;
4966 int i;
4967
4968 scb_data = ahc->scb_data;
4969 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4970 /* Can't allocate any more */
4971 return;
4972
4973 next_scb = &scb_data->scbarray[scb_data->numscbs];
4974
48813cf9 4975 sg_map = kmalloc(sizeof(*sg_map), GFP_ATOMIC);
1da177e4
LT		 4976
4977 if (sg_map == NULL)
4978 return;
4979
4980 /* Allocate S/G space for the next batch of SCBS */
4981 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat,
4982 (void **)&sg_map->sg_vaddr,
4983 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
48813cf9 4984 kfree(sg_map);
1da177e4
LT		 4985 return;
4986 }
4987
4988 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4989
4990 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4991 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4992 &sg_map->sg_physaddr, /*flags*/0);
4993
4994 segs = sg_map->sg_vaddr;
4995 physaddr = sg_map->sg_physaddr;
4996
4997 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
6d07cb71 4998 newcount = min(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
1da177e4
LT		 4999 for (i = 0; i < newcount; i++) {
5000 struct scb_platform_data *pdata;
cca6cb8a 5001
48813cf9 5002 pdata = kmalloc(sizeof(*pdata), GFP_ATOMIC);
1da177e4
LT		 5003 if (pdata == NULL)
5004 break;
5005 next_scb->platform_data = pdata;
5006 next_scb->sg_map = sg_map;
5007 next_scb->sg_list = segs;
5008 /*
5009 * The sequencer always starts with the second entry.
5010 * The first entry is embedded in the scb.
5011 */
5012 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
5013 next_scb->ahc_softc = ahc;
5014 next_scb->flags = SCB_FREE;
1da177e4
LT		 5015 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
5016 next_scb->hscb->tag = ahc->scb_data->numscbs;
5017 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
5018 next_scb, links.sle);
5019 segs += AHC_NSEG;
5020 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
5021 next_scb++;
5022 ahc->scb_data->numscbs++;
5023 }
5024}
5025
5026void
5027ahc_controller_info(struct ahc_softc *ahc, char *buf)
5028{
5029 int len;
5030
5031 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
5032 buf += len;
5033 if ((ahc->features & AHC_TWIN) != 0)
5034 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
5035 "B SCSI Id=%d, primary %c, ",
5036 ahc->our_id, ahc->our_id_b,
5037 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
5038 else {
5039 const char *speed;
5040 const char *type;
5041
5042 speed = "";
5043 if ((ahc->features & AHC_ULTRA) != 0) {
5044 speed = "Ultra ";
5045 } else if ((ahc->features & AHC_DT) != 0) {
5046 speed = "Ultra160 ";
5047 } else if ((ahc->features & AHC_ULTRA2) != 0) {
5048 speed = "Ultra2 ";
5049 }
5050 if ((ahc->features & AHC_WIDE) != 0) {
5051 type = "Wide";
5052 } else {
5053 type = "Single";
5054 }
5055 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
5056 speed, type, ahc->channel, ahc->our_id);
5057 }
5058 buf += len;
5059
5060 if ((ahc->flags & AHC_PAGESCBS) != 0)
5061 sprintf(buf, "%d/%d SCBs",
5062 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
5063 else
5064 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
5065}
5066
5067int
5068ahc_chip_init(struct ahc_softc *ahc)
5069{
5070 int term;
5071 int error;
5072 u_int i;
5073 u_int scsi_conf;
5074 u_int scsiseq_template;
5075 uint32_t physaddr;
5076
5077 ahc_outb(ahc, SEQ_FLAGS, 0);
5078 ahc_outb(ahc, SEQ_FLAGS2, 0);
5079
5080 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
5081 if (ahc->features & AHC_TWIN) {
5082
5083 /*
5084 * Setup Channel B first.
5085 */
5086 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
5087 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
5088 ahc_outb(ahc, SCSIID, ahc->our_id_b);
5089 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
5090 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
5091 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
5092 if ((ahc->features & AHC_ULTRA2) != 0)
5093 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
5094 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
5095 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
5096
5097 /* Select Channel A */
5098 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
5099 }
5100 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
5101 if ((ahc->features & AHC_ULTRA2) != 0)
5102 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
5103 else
5104 ahc_outb(ahc, SCSIID, ahc->our_id);
5105 scsi_conf = ahc_inb(ahc, SCSICONF);
5106 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
5107 |term|ahc->seltime
5108 |ENSTIMER|ACTNEGEN);
5109 if ((ahc->features & AHC_ULTRA2) != 0)
5110 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
5111 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
5112 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
5113
5114 /* There are no untagged SCBs active yet. */
5115 for (i = 0; i < 16; i++) {
5116 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
5117 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5118 int lun;
5119
5120 /*
5121 * The SCB based BTT allows an entry per
5122 * target and lun pair.
5123 */
5124 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
5125 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
5126 }
5127 }
5128
5129 /* All of our queues are empty */
5130 for (i = 0; i < 256; i++)
5131 ahc->qoutfifo[i] = SCB_LIST_NULL;
5132 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
5133
5134 for (i = 0; i < 256; i++)
5135 ahc->qinfifo[i] = SCB_LIST_NULL;
5136
5137 if ((ahc->features & AHC_MULTI_TID) != 0) {
5138 ahc_outb(ahc, TARGID, 0);
5139 ahc_outb(ahc, TARGID + 1, 0);
5140 }
5141
5142 /*
5143 * Tell the sequencer where it can find our arrays in memory.
5144 */
5145 physaddr = ahc->scb_data->hscb_busaddr;
5146 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
5147 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
5148 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
5149 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
5150
5151 physaddr = ahc->shared_data_busaddr;
5152 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
5153 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
5154 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
5155 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
5156
5157 /*
5158 * Initialize the group code to command length table.
5159 * This overrides the values in TARG_SCSIRATE, so only
5160 * setup the table after we have processed that information.
5161 */
5162 ahc_outb(ahc, CMDSIZE_TABLE, 5);
5163 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
5164 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
5165 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
5166 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
5167 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
5168 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
5169 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
5170
5171 if ((ahc->features & AHC_HS_MAILBOX) != 0)
5172 ahc_outb(ahc, HS_MAILBOX, 0);
5173
5174 /* Tell the sequencer of our initial queue positions */
5175 if ((ahc->features & AHC_TARGETMODE) != 0) {
5176 ahc->tqinfifonext = 1;
5177 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
5178 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
5179 }
5180 ahc->qinfifonext = 0;
5181 ahc->qoutfifonext = 0;
5182 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5183 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
5184 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5185 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
5186 ahc_outb(ahc, SDSCB_QOFF, 0);
5187 } else {
5188 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5189 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
5190 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
5191 }
5192
5193 /* We don't have any waiting selections */
5194 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
5195
5196 /* Our disconnection list is empty too */
5197 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
5198
5199 /* Message out buffer starts empty */
5200 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
5201
5202 /*
5203 * Setup the allowed SCSI Sequences based on operational mode.
24ed7a97 5204 * If we are a target, we'll enable select in operations once
1da177e4
LT		 5205 * we've had a lun enabled.
5206 */
5207 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
5208 if ((ahc->flags & AHC_INITIATORROLE) != 0)
5209 scsiseq_template |= ENRSELI;
5210 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
5211
5212 /* Initialize our list of free SCBs. */
5213 ahc_build_free_scb_list(ahc);
5214
5215 /*
5216 * Tell the sequencer which SCB will be the next one it receives.
5217 */
5218 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5219
5220 /*
5221 * Load the Sequencer program and Enable the adapter
5222 * in "fast" mode.
5223 */
5224 if (bootverbose)
48813cf9 5225 printk("%s: Downloading Sequencer Program...",
1da177e4
LT		 5226 ahc_name(ahc));
5227
5228 error = ahc_loadseq(ahc);
5229 if (error != 0)
5230 return (error);
5231
5232 if ((ahc->features & AHC_ULTRA2) != 0) {
5233 int wait;
5234
5235 /*
5236 * Wait for up to 500ms for our transceivers
5237 * to settle. If the adapter does not have
5238 * a cable attached, the transceivers may
5239 * never settle, so don't complain if we
5240 * fail here.
5241 */
5242 for (wait = 5000;
5243 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
5244 wait--)
5245 ahc_delay(100);
5246 }
5247 ahc_restart(ahc);
5248 return (0);
5249}
5250
5251/*
5252 * Start the board, ready for normal operation
5253 */
5254int
5255ahc_init(struct ahc_softc *ahc)
5256{
5257 int max_targ;
5258 u_int i;
5259 u_int scsi_conf;
5260 u_int ultraenb;
5261 u_int discenable;
5262 u_int tagenable;
5263 size_t driver_data_size;
5264
5265#ifdef AHC_DEBUG
5266 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
5267 ahc->flags |= AHC_SEQUENCER_DEBUG;
5268#endif
5269
5270#ifdef AHC_PRINT_SRAM
48813cf9 5271 printk("Scratch Ram:");
1da177e4
LT		 5272 for (i = 0x20; i < 0x5f; i++) {
5273 if (((i % 8) == 0) && (i != 0)) {
48813cf9 5274 printk ("\n ");
1da177e4 5275 }
48813cf9 5276 printk (" 0x%x", ahc_inb(ahc, i));
1da177e4
LT		 5277 }
5278 if ((ahc->features & AHC_MORE_SRAM) != 0) {
5279 for (i = 0x70; i < 0x7f; i++) {
5280 if (((i % 8) == 0) && (i != 0)) {
48813cf9 5281 printk ("\n ");
1da177e4 5282 }
48813cf9 5283 printk (" 0x%x", ahc_inb(ahc, i));
1da177e4
LT		 5284 }
5285 }
48813cf9 5286 printk ("\n");
1da177e4
LT		 5287 /*
5288 * Reading uninitialized scratch ram may
5289 * generate parity errors.
5290 */
5291 ahc_outb(ahc, CLRINT, CLRPARERR);
5292 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
5293#endif
5294 max_targ = 15;
5295
5296 /*
5297 * Assume we have a board at this stage and it has been reset.
5298 */
5299 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
5300 ahc->our_id = ahc->our_id_b = 7;
5301
5302 /*
5303 * Default to allowing initiator operations.
5304 */
5305 ahc->flags |= AHC_INITIATORROLE;
5306
5307 /*
5308 * Only allow target mode features if this unit has them enabled.
5309 */
5310 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
5311 ahc->features &= ~AHC_TARGETMODE;
5312
1da177e4
LT		 5313 ahc->init_level++;
5314
5315 /*
5316 * DMA tag for our command fifos and other data in system memory
5317 * the card's sequencer must be able to access. For initiator
5318 * roles, we need to allocate space for the qinfifo and qoutfifo.
5319 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
5320 * When providing for the target mode role, we must additionally
5321 * provide space for the incoming target command fifo and an extra
5322 * byte to deal with a dma bug in some chip versions.
5323 */
5324 driver_data_size = 2 * 256 * sizeof(uint8_t);
5325 if ((ahc->features & AHC_TARGETMODE) != 0)
5326 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
5327 + /*DMA WideOdd Bug Buffer*/1;
5328 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
5329 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5330 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5331 /*highaddr*/BUS_SPACE_MAXADDR,
5332 /*filter*/NULL, /*filterarg*/NULL,
5333 driver_data_size,
5334 /*nsegments*/1,
5335 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5336 /*flags*/0, &ahc->shared_data_dmat) != 0) {
5337 return (ENOMEM);
5338 }
5339
5340 ahc->init_level++;
5341
5342 /* Allocation of driver data */
5343 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat,
5344 (void **)&ahc->qoutfifo,
5345 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
5346 return (ENOMEM);
5347 }
5348
5349 ahc->init_level++;
5350
5351 /* And permanently map it in */
5352 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
5353 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
5354 &ahc->shared_data_busaddr, /*flags*/0);
5355
5356 if ((ahc->features & AHC_TARGETMODE) != 0) {
5357 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
5358 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
5359 ahc->dma_bug_buf = ahc->shared_data_busaddr
5360 + driver_data_size - 1;
5361 /* All target command blocks start out invalid. */
5362 for (i = 0; i < AHC_TMODE_CMDS; i++)
5363 ahc->targetcmds[i].cmd_valid = 0;
5364 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
5365 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
5366 }
5367 ahc->qinfifo = &ahc->qoutfifo[256];
5368
5369 ahc->init_level++;
5370
5371 /* Allocate SCB data now that buffer_dmat is initialized */
5372 if (ahc->scb_data->maxhscbs == 0)
5373 if (ahc_init_scbdata(ahc) != 0)
5374 return (ENOMEM);
5375
5376 /*
5377 * Allocate a tstate to house information for our
5378 * initiator presence on the bus as well as the user
5379 * data for any target mode initiator.
5380 */
5381 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
48813cf9 5382 printk("%s: unable to allocate ahc_tmode_tstate. "
1da177e4
LT		 5383 "Failing attach\n", ahc_name(ahc));
5384 return (ENOMEM);
5385 }
5386
5387 if ((ahc->features & AHC_TWIN) != 0) {
5388 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
48813cf9 5389 printk("%s: unable to allocate ahc_tmode_tstate. "
1da177e4
LT		 5390 "Failing attach\n", ahc_name(ahc));
5391 return (ENOMEM);
5392 }
5393 }
5394
5395 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
5396 ahc->flags |= AHC_PAGESCBS;
5397 } else {
5398 ahc->flags &= ~AHC_PAGESCBS;
5399 }
5400
5401#ifdef AHC_DEBUG
5402 if (ahc_debug & AHC_SHOW_MISC) {
48813cf9 5403 printk("%s: hardware scb %u bytes; kernel scb %u bytes; "
1da177e4
LT		 5404 "ahc_dma %u bytes\n",
5405 ahc_name(ahc),
5406 (u_int)sizeof(struct hardware_scb),
5407 (u_int)sizeof(struct scb),
5408 (u_int)sizeof(struct ahc_dma_seg));
5409 }
5410#endif /* AHC_DEBUG */
5411
5412 /*
5413 * Look at the information that board initialization or
5414 * the board bios has left us.
5415 */
5416 if (ahc->features & AHC_TWIN) {
5417 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
5418 if ((scsi_conf & RESET_SCSI) != 0
5419 && (ahc->flags & AHC_INITIATORROLE) != 0)
5420 ahc->flags |= AHC_RESET_BUS_B;
5421 }
5422
5423 scsi_conf = ahc_inb(ahc, SCSICONF);
5424 if ((scsi_conf & RESET_SCSI) != 0
5425 && (ahc->flags & AHC_INITIATORROLE) != 0)
5426 ahc->flags |= AHC_RESET_BUS_A;
5427
5428 ultraenb = 0;
5429 tagenable = ALL_TARGETS_MASK;
5430
5431 /* Grab the disconnection disable table and invert it for our needs */
5432 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
48813cf9 5433 printk("%s: Host Adapter Bios disabled. Using default SCSI "
1da177e4
LT		 5434 "device parameters\n", ahc_name(ahc));
5435 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
5436 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
5437 discenable = ALL_TARGETS_MASK;
5438 if ((ahc->features & AHC_ULTRA) != 0)
5439 ultraenb = ALL_TARGETS_MASK;
5440 } else {
5441 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
5442 | ahc_inb(ahc, DISC_DSB));
5443 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
5444 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
5445 | ahc_inb(ahc, ULTRA_ENB);
5446 }
5447
5448 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
5449 max_targ = 7;
5450
5451 for (i = 0; i <= max_targ; i++) {
5452 struct ahc_initiator_tinfo *tinfo;
5453 struct ahc_tmode_tstate *tstate;
5454 u_int our_id;
5455 u_int target_id;
5456 char channel;
5457
5458 channel = 'A';
5459 our_id = ahc->our_id;
5460 target_id = i;
5461 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
5462 channel = 'B';
5463 our_id = ahc->our_id_b;
5464 target_id = i % 8;
5465 }
5466 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
5467 target_id, &tstate);
5468 /* Default to async narrow across the board */
5469 memset(tinfo, 0, sizeof(*tinfo));
5470 if (ahc->flags & AHC_USEDEFAULTS) {
5471 if ((ahc->features & AHC_WIDE) != 0)
5472 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5473
5474 /*
5475 * These will be truncated when we determine the
5476 * connection type we have with the target.
5477 */
5478 tinfo->user.period = ahc_syncrates->period;
5479 tinfo->user.offset = MAX_OFFSET;
5480 } else {
5481 u_int scsirate;
5482 uint16_t mask;
5483
5484 /* Take the settings leftover in scratch RAM. */
5485 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5486 mask = (0x01 << i);
5487 if ((ahc->features & AHC_ULTRA2) != 0) {
5488 u_int offset;
5489 u_int maxsync;
5490
5491 if ((scsirate & SOFS) == 0x0F) {
5492 /*
5493 * Haven't negotiated yet,
5494 * so the format is different.
5495 */
5496 scsirate = (scsirate & SXFR) >> 4
5497 | (ultraenb & mask)
5498 ? 0x08 : 0x0
5499 | (scsirate & WIDEXFER);
5500 offset = MAX_OFFSET_ULTRA2;
5501 } else
5502 offset = ahc_inb(ahc, TARG_OFFSET + i);
5503 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5504 /* Set to the lowest sync rate, 5MHz */
5505 scsirate |= 0x1c;
5506 maxsync = AHC_SYNCRATE_ULTRA2;
5507 if ((ahc->features & AHC_DT) != 0)
5508 maxsync = AHC_SYNCRATE_DT;
5509 tinfo->user.period =
5510 ahc_find_period(ahc, scsirate, maxsync);
5511 if (offset == 0)
5512 tinfo->user.period = 0;
5513 else
5514 tinfo->user.offset = MAX_OFFSET;
5515 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5516 && (ahc->features & AHC_DT) != 0)
5517 tinfo->user.ppr_options =
5518 MSG_EXT_PPR_DT_REQ;
5519 } else if ((scsirate & SOFS) != 0) {
5520 if ((scsirate & SXFR) == 0x40
5521 && (ultraenb & mask) != 0) {
5522 /* Treat 10MHz as a non-ultra speed */
5523 scsirate &= ~SXFR;
5524 ultraenb &= ~mask;
5525 }
5526 tinfo->user.period =
5527 ahc_find_period(ahc, scsirate,
5528 (ultraenb & mask)
5529 ? AHC_SYNCRATE_ULTRA
5530 : AHC_SYNCRATE_FAST);
5531 if (tinfo->user.period != 0)
5532 tinfo->user.offset = MAX_OFFSET;
5533 }
5534 if (tinfo->user.period == 0)
5535 tinfo->user.offset = 0;
5536 if ((scsirate & WIDEXFER) != 0
5537 && (ahc->features & AHC_WIDE) != 0)
5538 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5539 tinfo->user.protocol_version = 4;
5540 if ((ahc->features & AHC_DT) != 0)
5541 tinfo->user.transport_version = 3;
5542 else
5543 tinfo->user.transport_version = 2;
5544 tinfo->goal.protocol_version = 2;
5545 tinfo->goal.transport_version = 2;
5546 tinfo->curr.protocol_version = 2;
5547 tinfo->curr.transport_version = 2;
5548 }
5549 tstate->ultraenb = 0;
5550 }
5551 ahc->user_discenable = discenable;
5552 ahc->user_tagenable = tagenable;
5553
5554 return (ahc->bus_chip_init(ahc));
5555}
5556
5557void
5558ahc_intr_enable(struct ahc_softc *ahc, int enable)
5559{
5560 u_int hcntrl;
5561
5562 hcntrl = ahc_inb(ahc, HCNTRL);
5563 hcntrl &= ~INTEN;
5564 ahc->pause &= ~INTEN;
5565 ahc->unpause &= ~INTEN;
5566 if (enable) {
5567 hcntrl |= INTEN;
5568 ahc->pause |= INTEN;
5569 ahc->unpause |= INTEN;
5570 }
5571 ahc_outb(ahc, HCNTRL, hcntrl);
5572}
5573
5574/*
5575 * Ensure that the card is paused in a location
5576 * outside of all critical sections and that all
5577 * pending work is completed prior to returning.
5578 * This routine should only be called from outside
5579 * an interrupt context.
5580 */
5581void
5582ahc_pause_and_flushwork(struct ahc_softc *ahc)
5583{
5584 int intstat;
5585 int maxloops;
5586 int paused;
5587
5588 maxloops = 1000;
5589 ahc->flags |= AHC_ALL_INTERRUPTS;
5590 paused = FALSE;
5591 do {
79778a27 5592 if (paused) {
1da177e4 5593 ahc_unpause(ahc);
79778a27
JB		 5594 /*
5595 * Give the sequencer some time to service
5596 * any active selections.
5597 */
5598 ahc_delay(500);
5599 }
1da177e4
LT		 5600 ahc_intr(ahc);
5601 ahc_pause(ahc);
5602 paused = TRUE;
5603 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
1da177e4 5604 intstat = ahc_inb(ahc, INTSTAT);
79778a27
JB		 5605 if ((intstat & INT_PEND) == 0) {
5606 ahc_clear_critical_section(ahc);
5607 intstat = ahc_inb(ahc, INTSTAT);
5608 }
1da177e4
LT		 5609 } while (--maxloops
5610 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5611 && ((intstat & INT_PEND) != 0
5612 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5613 if (maxloops == 0) {
48813cf9 5614 printk("Infinite interrupt loop, INTSTAT = %x",
1da177e4
LT		 5615 ahc_inb(ahc, INTSTAT));
5616 }
5617 ahc_platform_flushwork(ahc);
5618 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5619}
5620
03e7925d 5621#ifdef CONFIG_PM
1da177e4
LT		 5622int
5623ahc_suspend(struct ahc_softc *ahc)
5624{
5625
5626 ahc_pause_and_flushwork(ahc);
5627
5628 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5629 ahc_unpause(ahc);
5630 return (EBUSY);
5631 }
5632
5633#ifdef AHC_TARGET_MODE
5634 /*
5635 * XXX What about ATIOs that have not yet been serviced?
5636 * Perhaps we should just refuse to be suspended if we
5637 * are acting in a target role.
5638 */
5639 if (ahc->pending_device != NULL) {
5640 ahc_unpause(ahc);
5641 return (EBUSY);
5642 }
5643#endif
5644 ahc_shutdown(ahc);
5645 return (0);
5646}
5647
5648int
5649ahc_resume(struct ahc_softc *ahc)
5650{
5651
5652 ahc_reset(ahc, /*reinit*/TRUE);
5653 ahc_intr_enable(ahc, TRUE);
5654 ahc_restart(ahc);
5655 return (0);
5656}
03e7925d 5657#endif
1da177e4
LT		 5658/************************** Busy Target Table *********************************/
5659/*
5660 * Return the untagged transaction id for a given target/channel lun.
5661 * Optionally, clear the entry.
5662 */
d1d7b19d 5663static u_int
1da177e4
LT		 5664ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5665{
5666 u_int scbid;
5667 u_int target_offset;
5668
5669 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5670 u_int saved_scbptr;
5671
5672 saved_scbptr = ahc_inb(ahc, SCBPTR);
5673 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5674 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5675 ahc_outb(ahc, SCBPTR, saved_scbptr);
5676 } else {
5677 target_offset = TCL_TARGET_OFFSET(tcl);
5678 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5679 }
5680
5681 return (scbid);
5682}
5683
d1d7b19d 5684static void
1da177e4
LT		 5685ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5686{
5687 u_int target_offset;
5688
5689 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5690 u_int saved_scbptr;
5691
5692 saved_scbptr = ahc_inb(ahc, SCBPTR);
5693 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5694 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5695 ahc_outb(ahc, SCBPTR, saved_scbptr);
5696 } else {
5697 target_offset = TCL_TARGET_OFFSET(tcl);
5698 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5699 }
5700}
5701
d1d7b19d 5702static void
1da177e4
LT		 5703ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5704{
5705 u_int target_offset;
5706
5707 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5708 u_int saved_scbptr;
5709
5710 saved_scbptr = ahc_inb(ahc, SCBPTR);
5711 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5712 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5713 ahc_outb(ahc, SCBPTR, saved_scbptr);
5714 } else {
5715 target_offset = TCL_TARGET_OFFSET(tcl);
5716 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5717 }
5718}
5719
5720/************************** SCB and SCB queue management **********************/
5721int
5722ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5723 char channel, int lun, u_int tag, role_t role)
5724{
5725 int targ = SCB_GET_TARGET(ahc, scb);
5726 char chan = SCB_GET_CHANNEL(ahc, scb);
5727 int slun = SCB_GET_LUN(scb);
5728 int match;
5729
5730 match = ((chan == channel) || (channel == ALL_CHANNELS));
5731 if (match != 0)
5732 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5733 if (match != 0)
5734 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5735 if (match != 0) {
5736#ifdef AHC_TARGET_MODE
5737 int group;
5738
5739 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5740 if (role == ROLE_INITIATOR) {
5741 match = (group != XPT_FC_GROUP_TMODE)
5742 && ((tag == scb->hscb->tag)
5743 || (tag == SCB_LIST_NULL));
5744 } else if (role == ROLE_TARGET) {
5745 match = (group == XPT_FC_GROUP_TMODE)
5746 && ((tag == scb->io_ctx->csio.tag_id)
5747 || (tag == SCB_LIST_NULL));
5748 }
5749#else /* !AHC_TARGET_MODE */
5750 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5751#endif /* AHC_TARGET_MODE */
5752 }
5753
5754 return match;
5755}
5756
d1d7b19d 5757static void
1da177e4
LT		 5758ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5759{
5760 int target;
5761 char channel;
5762 int lun;
5763
5764 target = SCB_GET_TARGET(ahc, scb);
5765 lun = SCB_GET_LUN(scb);
5766 channel = SCB_GET_CHANNEL(ahc, scb);
5767
5768 ahc_search_qinfifo(ahc, target, channel, lun,
5769 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5770 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5771
5772 ahc_platform_freeze_devq(ahc, scb);
5773}
5774
5775void
5776ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5777{
5778 struct scb *prev_scb;
5779
5780 prev_scb = NULL;
5781 if (ahc_qinfifo_count(ahc) != 0) {
5782 u_int prev_tag;
5783 uint8_t prev_pos;
5784
5785 prev_pos = ahc->qinfifonext - 1;
5786 prev_tag = ahc->qinfifo[prev_pos];
5787 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5788 }
5789 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5790 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5791 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5792 } else {
5793 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5794 }
5795}
5796
5797static void
5798ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5799 struct scb *scb)
5800{
5801 if (prev_scb == NULL) {
5802 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5803 } else {
5804 prev_scb->hscb->next = scb->hscb->tag;
5805 ahc_sync_scb(ahc, prev_scb,
5806 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5807 }
5808 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5809 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5810 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5811}
5812
5813static int
5814ahc_qinfifo_count(struct ahc_softc *ahc)
5815{
5816 uint8_t qinpos;
5817 uint8_t diff;
5818
5819 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5820 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5821 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5822 } else
5823 qinpos = ahc_inb(ahc, QINPOS);
5824 diff = ahc->qinfifonext - qinpos;
5825 return (diff);
5826}
5827
5828int
5829ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5830 int lun, u_int tag, role_t role, uint32_t status,
5831 ahc_search_action action)
5832{
5833 struct scb *scb;
5834 struct scb *prev_scb;
5835 uint8_t qinstart;
5836 uint8_t qinpos;
5837 uint8_t qintail;
5838 uint8_t next;
5839 uint8_t prev;
5840 uint8_t curscbptr;
5841 int found;
5842 int have_qregs;
5843
5844 qintail = ahc->qinfifonext;
5845 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5846 if (have_qregs) {
5847 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5848 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5849 } else
5850 qinstart = ahc_inb(ahc, QINPOS);
5851 qinpos = qinstart;
5852 found = 0;
5853 prev_scb = NULL;
5854
5855 if (action == SEARCH_COMPLETE) {
5856 /*
5857 * Don't attempt to run any queued untagged transactions
5858 * until we are done with the abort process.
5859 */
5860 ahc_freeze_untagged_queues(ahc);
5861 }
5862
5863 /*
5864 * Start with an empty queue. Entries that are not chosen
5865 * for removal will be re-added to the queue as we go.
5866 */
5867 ahc->qinfifonext = qinpos;
5868 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5869
5870 while (qinpos != qintail) {
5871 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5872 if (scb == NULL) {
48813cf9 5873 printk("qinpos = %d, SCB index = %d\n",
1da177e4
LT		 5874 qinpos, ahc->qinfifo[qinpos]);
5875 panic("Loop 1\n");
5876 }
5877
5878 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5879 /*
5880 * We found an scb that needs to be acted on.
5881 */
5882 found++;
5883 switch (action) {
5884 case SEARCH_COMPLETE:
5885 {
5886 cam_status ostat;
5887 cam_status cstat;
5888
5889 ostat = ahc_get_transaction_status(scb);
5890 if (ostat == CAM_REQ_INPROG)
5891 ahc_set_transaction_status(scb, status);
5892 cstat = ahc_get_transaction_status(scb);
5893 if (cstat != CAM_REQ_CMP)
5894 ahc_freeze_scb(scb);
5895 if ((scb->flags & SCB_ACTIVE) == 0)
48813cf9 5896 printk("Inactive SCB in qinfifo\n");
1da177e4
LT		 5897 ahc_done(ahc, scb);
5898
5899 /* FALLTHROUGH */
5900 }
5901 case SEARCH_REMOVE:
5902 break;
5903 case SEARCH_COUNT:
5904 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5905 prev_scb = scb;
5906 break;
5907 }
5908 } else {
5909 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5910 prev_scb = scb;
5911 }
5912 qinpos++;
5913 }
5914
5915 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5916 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5917 } else {
5918 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5919 }
5920
5921 if (action != SEARCH_COUNT
5922 && (found != 0)
5923 && (qinstart != ahc->qinfifonext)) {
5924 /*
5925 * The sequencer may be in the process of dmaing
5926 * down the SCB at the beginning of the queue.
5927 * This could be problematic if either the first,
5928 * or the second SCB is removed from the queue
5929 * (the first SCB includes a pointer to the "next"
5930 * SCB to dma). If we have removed any entries, swap
5931 * the first element in the queue with the next HSCB
5932 * so the sequencer will notice that NEXT_QUEUED_SCB
5933 * has changed during its dma attempt and will retry
5934 * the DMA.
5935 */
5936 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5937
5938 if (scb == NULL) {
48813cf9 5939 printk("found = %d, qinstart = %d, qinfifionext = %d\n",
1da177e4
LT		 5940 found, qinstart, ahc->qinfifonext);
5941 panic("First/Second Qinfifo fixup\n");
5942 }
5943 /*
5944 * ahc_swap_with_next_hscb forces our next pointer to
5945 * point to the reserved SCB for future commands. Save
5946 * and restore our original next pointer to maintain
5947 * queue integrity.
5948 */
5949 next = scb->hscb->next;
5950 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5951 ahc_swap_with_next_hscb(ahc, scb);
5952 scb->hscb->next = next;
5953 ahc->qinfifo[qinstart] = scb->hscb->tag;
5954
5955 /* Tell the card about the new head of the qinfifo. */
5956 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5957
5958 /* Fixup the tail "next" pointer. */
5959 qintail = ahc->qinfifonext - 1;
5960 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5961 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5962 }
5963
5964 /*
5965 * Search waiting for selection list.
5966 */
5967 curscbptr = ahc_inb(ahc, SCBPTR);
5968 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5969 prev = SCB_LIST_NULL;
5970
5971 while (next != SCB_LIST_NULL) {
5972 uint8_t scb_index;
5973
5974 ahc_outb(ahc, SCBPTR, next);
5975 scb_index = ahc_inb(ahc, SCB_TAG);
5976 if (scb_index >= ahc->scb_data->numscbs) {
48813cf9 5977 printk("Waiting List inconsistency. "
1da177e4
LT		 5978 "SCB index == %d, yet numscbs == %d.",
5979 scb_index, ahc->scb_data->numscbs);
5980 ahc_dump_card_state(ahc);
5981 panic("for safety");
5982 }
5983 scb = ahc_lookup_scb(ahc, scb_index);
5984 if (scb == NULL) {
48813cf9 5985 printk("scb_index = %d, next = %d\n",
1da177e4
LT		 5986 scb_index, next);
5987 panic("Waiting List traversal\n");
5988 }
5989 if (ahc_match_scb(ahc, scb, target, channel,
5990 lun, SCB_LIST_NULL, role)) {
5991 /*
5992 * We found an scb that needs to be acted on.
5993 */
5994 found++;
5995 switch (action) {
5996 case SEARCH_COMPLETE:
5997 {
5998 cam_status ostat;
5999 cam_status cstat;
6000
6001 ostat = ahc_get_transaction_status(scb);
6002 if (ostat == CAM_REQ_INPROG)
6003 ahc_set_transaction_status(scb,
6004 status);
6005 cstat = ahc_get_transaction_status(scb);
6006 if (cstat != CAM_REQ_CMP)
6007 ahc_freeze_scb(scb);
6008 if ((scb->flags & SCB_ACTIVE) == 0)
48813cf9 6009 printk("Inactive SCB in Waiting List\n");
1da177e4 6010 ahc_done(ahc, scb);
1da177e4 6011 }
e2e80164 6012 /* fall through */
1da177e4
LT		 6013 case SEARCH_REMOVE:
6014 next = ahc_rem_wscb(ahc, next, prev);
6015 break;
6016 case SEARCH_COUNT:
6017 prev = next;
6018 next = ahc_inb(ahc, SCB_NEXT);
6019 break;
6020 }
6021 } else {
6022
6023 prev = next;
6024 next = ahc_inb(ahc, SCB_NEXT);
6025 }
6026 }
6027 ahc_outb(ahc, SCBPTR, curscbptr);
6028
6029 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target,
6030 channel, lun, status, action);
6031
6032 if (action == SEARCH_COMPLETE)
6033 ahc_release_untagged_queues(ahc);
6034 return (found);
6035}
6036
6037int
6038ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx,
6039 int target, char channel, int lun, uint32_t status,
6040 ahc_search_action action)
6041{
6042 struct scb *scb;
6043 int maxtarget;
6044 int found;
6045 int i;
6046
6047 if (action == SEARCH_COMPLETE) {
6048 /*
6049 * Don't attempt to run any queued untagged transactions
6050 * until we are done with the abort process.
6051 */
6052 ahc_freeze_untagged_queues(ahc);
6053 }
6054
6055 found = 0;
6056 i = 0;
6057 if ((ahc->flags & AHC_SCB_BTT) == 0) {
6058
6059 maxtarget = 16;
6060 if (target != CAM_TARGET_WILDCARD) {
6061
6062 i = target;
6063 if (channel == 'B')
6064 i += 8;
6065 maxtarget = i + 1;
6066 }
6067 } else {
6068 maxtarget = 0;
6069 }
6070
6071 for (; i < maxtarget; i++) {
6072 struct scb_tailq *untagged_q;
6073 struct scb *next_scb;
6074
6075 untagged_q = &(ahc->untagged_queues[i]);
6076 next_scb = TAILQ_FIRST(untagged_q);
6077 while (next_scb != NULL) {
6078
6079 scb = next_scb;
6080 next_scb = TAILQ_NEXT(scb, links.tqe);
6081
6082 /*
6083 * The head of the list may be the currently
6084 * active untagged command for a device.
6085 * We're only searching for commands that
6086 * have not been started. A transaction
6087 * marked active but still in the qinfifo
6088 * is removed by the qinfifo scanning code
6089 * above.
6090 */
6091 if ((scb->flags & SCB_ACTIVE) != 0)
6092 continue;
6093
6094 if (ahc_match_scb(ahc, scb, target, channel, lun,
6095 SCB_LIST_NULL, ROLE_INITIATOR) == 0
6096 || (ctx != NULL && ctx != scb->io_ctx))
6097 continue;
6098
6099 /*
6100 * We found an scb that needs to be acted on.
6101 */
6102 found++;
6103 switch (action) {
6104 case SEARCH_COMPLETE:
6105 {
6106 cam_status ostat;
6107 cam_status cstat;
6108
6109 ostat = ahc_get_transaction_status(scb);
6110 if (ostat == CAM_REQ_INPROG)
6111 ahc_set_transaction_status(scb, status);
6112 cstat = ahc_get_transaction_status(scb);
6113 if (cstat != CAM_REQ_CMP)
6114 ahc_freeze_scb(scb);
6115 if ((scb->flags & SCB_ACTIVE) == 0)
48813cf9 6116 printk("Inactive SCB in untaggedQ\n");
1da177e4
LT		 6117 ahc_done(ahc, scb);
6118 break;
6119 }
6120 case SEARCH_REMOVE:
6121 scb->flags &= ~SCB_UNTAGGEDQ;
6122 TAILQ_REMOVE(untagged_q, scb, links.tqe);
6123 break;
6124 case SEARCH_COUNT:
6125 break;
6126 }
6127 }
6128 }
6129
6130 if (action == SEARCH_COMPLETE)
6131 ahc_release_untagged_queues(ahc);
6132 return (found);
6133}
6134
6135int
6136ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
6137 int lun, u_int tag, int stop_on_first, int remove,
6138 int save_state)
6139{
6140 struct scb *scbp;
6141 u_int next;
6142 u_int prev;
6143 u_int count;
6144 u_int active_scb;
6145
6146 count = 0;
6147 next = ahc_inb(ahc, DISCONNECTED_SCBH);
6148 prev = SCB_LIST_NULL;
6149
6150 if (save_state) {
6151 /* restore this when we're done */
6152 active_scb = ahc_inb(ahc, SCBPTR);
6153 } else
6154 /* Silence compiler */
6155 active_scb = SCB_LIST_NULL;
6156
6157 while (next != SCB_LIST_NULL) {
6158 u_int scb_index;
6159
6160 ahc_outb(ahc, SCBPTR, next);
6161 scb_index = ahc_inb(ahc, SCB_TAG);
6162 if (scb_index >= ahc->scb_data->numscbs) {
48813cf9 6163 printk("Disconnected List inconsistency. "
1da177e4
LT		 6164 "SCB index == %d, yet numscbs == %d.",
6165 scb_index, ahc->scb_data->numscbs);
6166 ahc_dump_card_state(ahc);
6167 panic("for safety");
6168 }
6169
6170 if (next == prev) {
6171 panic("Disconnected List Loop. "
6172 "cur SCBPTR == %x, prev SCBPTR == %x.",
6173 next, prev);
6174 }
6175 scbp = ahc_lookup_scb(ahc, scb_index);
6176 if (ahc_match_scb(ahc, scbp, target, channel, lun,
6177 tag, ROLE_INITIATOR)) {
6178 count++;
6179 if (remove) {
6180 next =
6181 ahc_rem_scb_from_disc_list(ahc, prev, next);
6182 } else {
6183 prev = next;
6184 next = ahc_inb(ahc, SCB_NEXT);
6185 }
6186 if (stop_on_first)
6187 break;
6188 } else {
6189 prev = next;
6190 next = ahc_inb(ahc, SCB_NEXT);
6191 }
6192 }
6193 if (save_state)
6194 ahc_outb(ahc, SCBPTR, active_scb);
6195 return (count);
6196}
6197
6198/*
6199 * Remove an SCB from the on chip list of disconnected transactions.
6200 * This is empty/unused if we are not performing SCB paging.
6201 */
6202static u_int
6203ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
6204{
6205 u_int next;
6206
6207 ahc_outb(ahc, SCBPTR, scbptr);
6208 next = ahc_inb(ahc, SCB_NEXT);
6209
6210 ahc_outb(ahc, SCB_CONTROL, 0);
6211
6212 ahc_add_curscb_to_free_list(ahc);
6213
6214 if (prev != SCB_LIST_NULL) {
6215 ahc_outb(ahc, SCBPTR, prev);
6216 ahc_outb(ahc, SCB_NEXT, next);
6217 } else
6218 ahc_outb(ahc, DISCONNECTED_SCBH, next);
6219
6220 return (next);
6221}
6222
6223/*
6224 * Add the SCB as selected by SCBPTR onto the on chip list of
6225 * free hardware SCBs. This list is empty/unused if we are not
6226 * performing SCB paging.
6227 */
6228static void
6229ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
6230{
6231 /*
6232 * Invalidate the tag so that our abort
6233 * routines don't think it's active.
6234 */
6235 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
6236
6237 if ((ahc->flags & AHC_PAGESCBS) != 0) {
6238 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
6239 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
6240 }
6241}
6242
6243/*
6244 * Manipulate the waiting for selection list and return the
6245 * scb that follows the one that we remove.
6246 */
6247static u_int
6248ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
be0d6768 6249{
1da177e4
LT		 6250 u_int curscb, next;
6251
6252 /*
6253 * Select the SCB we want to abort and
6254 * pull the next pointer out of it.
6255 */
6256 curscb = ahc_inb(ahc, SCBPTR);
6257 ahc_outb(ahc, SCBPTR, scbpos);
6258 next = ahc_inb(ahc, SCB_NEXT);
6259
6260 /* Clear the necessary fields */
6261 ahc_outb(ahc, SCB_CONTROL, 0);
6262
6263 ahc_add_curscb_to_free_list(ahc);
6264
6265 /* update the waiting list */
6266 if (prev == SCB_LIST_NULL) {
6267 /* First in the list */
6268 ahc_outb(ahc, WAITING_SCBH, next);
6269
6270 /*
6271 * Ensure we aren't attempting to perform
6272 * selection for this entry.
6273 */
6274 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
6275 } else {
6276 /*
6277 * Select the scb that pointed to us
6278 * and update its next pointer.
6279 */
6280 ahc_outb(ahc, SCBPTR, prev);
6281 ahc_outb(ahc, SCB_NEXT, next);
6282 }
6283
6284 /*
6285 * Point us back at the original scb position.
6286 */
6287 ahc_outb(ahc, SCBPTR, curscb);
6288 return next;
6289}
6290
6291/******************************** Error Handling ******************************/
6292/*
6293 * Abort all SCBs that match the given description (target/channel/lun/tag),
6294 * setting their status to the passed in status if the status has not already
6295 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
6296 * is paused before it is called.
6297 */
d1d7b19d 6298static int
1da177e4
LT		 6299ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
6300 int lun, u_int tag, role_t role, uint32_t status)
6301{
6302 struct scb *scbp;
6303 struct scb *scbp_next;
6304 u_int active_scb;
6305 int i, j;
6306 int maxtarget;
6307 int minlun;
6308 int maxlun;
6309
6310 int found;
6311
6312 /*
6313 * Don't attempt to run any queued untagged transactions
6314 * until we are done with the abort process.
6315 */
6316 ahc_freeze_untagged_queues(ahc);
6317
6318 /* restore this when we're done */
6319 active_scb = ahc_inb(ahc, SCBPTR);
6320
6321 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
6322 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
6323
6324 /*
6325 * Clean out the busy target table for any untagged commands.
6326 */
6327 i = 0;
6328 maxtarget = 16;
6329 if (target != CAM_TARGET_WILDCARD) {
6330 i = target;
6331 if (channel == 'B')
6332 i += 8;
6333 maxtarget = i + 1;
6334 }
6335
6336 if (lun == CAM_LUN_WILDCARD) {
6337
6338 /*
6339 * Unless we are using an SCB based
6340 * busy targets table, there is only
6341 * one table entry for all luns of
6342 * a target.
6343 */
6344 minlun = 0;
6345 maxlun = 1;
6346 if ((ahc->flags & AHC_SCB_BTT) != 0)
6347 maxlun = AHC_NUM_LUNS;
6348 } else {
6349 minlun = lun;
6350 maxlun = lun + 1;
6351 }
6352
6353 if (role != ROLE_TARGET) {
6354 for (;i < maxtarget; i++) {
6355 for (j = minlun;j < maxlun; j++) {
6356 u_int scbid;
6357 u_int tcl;
6358
6359 tcl = BUILD_TCL(i << 4, j);
6360 scbid = ahc_index_busy_tcl(ahc, tcl);
6361 scbp = ahc_lookup_scb(ahc, scbid);
6362 if (scbp == NULL
6363 || ahc_match_scb(ahc, scbp, target, channel,
6364 lun, tag, role) == 0)
6365 continue;
6366 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
6367 }
6368 }
6369
6370 /*
6371 * Go through the disconnected list and remove any entries we
6372 * have queued for completion, 0'ing their control byte too.
6373 * We save the active SCB and restore it ourselves, so there
6374 * is no reason for this search to restore it too.
6375 */
6376 ahc_search_disc_list(ahc, target, channel, lun, tag,
6377 /*stop_on_first*/FALSE, /*remove*/TRUE,
6378 /*save_state*/FALSE);
6379 }
6380
6381 /*
6382 * Go through the hardware SCB array looking for commands that
6383 * were active but not on any list. In some cases, these remnants
6384 * might not still have mappings in the scbindex array (e.g. unexpected
6385 * bus free with the same scb queued for an abort). Don't hold this
6386 * against them.
6387 */
6388 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6389 u_int scbid;
6390
6391 ahc_outb(ahc, SCBPTR, i);
6392 scbid = ahc_inb(ahc, SCB_TAG);
6393 scbp = ahc_lookup_scb(ahc, scbid);
6394 if ((scbp == NULL && scbid != SCB_LIST_NULL)
6395 || (scbp != NULL
6396 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
6397 ahc_add_curscb_to_free_list(ahc);
6398 }
6399
6400 /*
6401 * Go through the pending CCB list and look for
6402 * commands for this target that are still active.
6403 * These are other tagged commands that were
6404 * disconnected when the reset occurred.
6405 */
6406 scbp_next = LIST_FIRST(&ahc->pending_scbs);
6407 while (scbp_next != NULL) {
6408 scbp = scbp_next;
6409 scbp_next = LIST_NEXT(scbp, pending_links);
6410 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
6411 cam_status ostat;
6412
6413 ostat = ahc_get_transaction_status(scbp);
6414 if (ostat == CAM_REQ_INPROG)
6415 ahc_set_transaction_status(scbp, status);
6416 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
6417 ahc_freeze_scb(scbp);
6418 if ((scbp->flags & SCB_ACTIVE) == 0)
48813cf9 6419 printk("Inactive SCB on pending list\n");
1da177e4
LT		 6420 ahc_done(ahc, scbp);
6421 found++;
6422 }
6423 }
6424 ahc_outb(ahc, SCBPTR, active_scb);
6425 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
6426 ahc_release_untagged_queues(ahc);
6427 return found;
6428}
6429
6430static void
6431ahc_reset_current_bus(struct ahc_softc *ahc)
6432{
6433 uint8_t scsiseq;
6434
6435 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
6436 scsiseq = ahc_inb(ahc, SCSISEQ);
6437 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
6438 ahc_flush_device_writes(ahc);
6439 ahc_delay(AHC_BUSRESET_DELAY);
6440 /* Turn off the bus reset */
6441 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
6442
6443 ahc_clear_intstat(ahc);
6444
6445 /* Re-enable reset interrupts */
6446 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
6447}
6448
6449int
6450ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
6451{
6452 struct ahc_devinfo devinfo;
6453 u_int initiator, target, max_scsiid;
6454 u_int sblkctl;
6455 u_int scsiseq;
6456 u_int simode1;
6457 int found;
6458 int restart_needed;
6459 char cur_channel;
6460
6461 ahc->pending_device = NULL;
6462
6463 ahc_compile_devinfo(&devinfo,
6464 CAM_TARGET_WILDCARD,
6465 CAM_TARGET_WILDCARD,
6466 CAM_LUN_WILDCARD,
6467 channel, ROLE_UNKNOWN);
6468 ahc_pause(ahc);
6469
6470 /* Make sure the sequencer is in a safe location. */
6471 ahc_clear_critical_section(ahc);
6472
6473 /*
6474 * Run our command complete fifos to ensure that we perform
6475 * completion processing on any commands that 'completed'
6476 * before the reset occurred.
6477 */
6478 ahc_run_qoutfifo(ahc);
6479#ifdef AHC_TARGET_MODE
6480 /*
6481 * XXX - In Twin mode, the tqinfifo may have commands
6482 * for an unaffected channel in it. However, if
6483 * we have run out of ATIO resources to drain that
6484 * queue, we may not get them all out here. Further,
6485 * the blocked transactions for the reset channel
6486 * should just be killed off, irrespecitve of whether
6487 * we are blocked on ATIO resources. Write a routine
6488 * to compact the tqinfifo appropriately.
6489 */
6490 if ((ahc->flags & AHC_TARGETROLE) != 0) {
6491 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
6492 }
6493#endif
6494
6495 /*
6496 * Reset the bus if we are initiating this reset
6497 */
6498 sblkctl = ahc_inb(ahc, SBLKCTL);
6499 cur_channel = 'A';
6500 if ((ahc->features & AHC_TWIN) != 0
6501 && ((sblkctl & SELBUSB) != 0))
6502 cur_channel = 'B';
6503 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6504 if (cur_channel != channel) {
6505 /* Case 1: Command for another bus is active
6506 * Stealthily reset the other bus without
6507 * upsetting the current bus.
6508 */
6509 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
6510 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6511#ifdef AHC_TARGET_MODE
6512 /*
6513 * Bus resets clear ENSELI, so we cannot
6514 * defer re-enabling bus reset interrupts
6515 * if we are in target mode.
6516 */
6517 if ((ahc->flags & AHC_TARGETROLE) != 0)
6518 simode1 |= ENSCSIRST;
6519#endif
6520 ahc_outb(ahc, SIMODE1, simode1);
6521 if (initiate_reset)
6522 ahc_reset_current_bus(ahc);
6523 ahc_clear_intstat(ahc);
6524 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6525 ahc_outb(ahc, SBLKCTL, sblkctl);
6526 restart_needed = FALSE;
6527 } else {
6528 /* Case 2: A command from this bus is active or we're idle */
6529 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6530#ifdef AHC_TARGET_MODE
6531 /*
6532 * Bus resets clear ENSELI, so we cannot
6533 * defer re-enabling bus reset interrupts
6534 * if we are in target mode.
6535 */
6536 if ((ahc->flags & AHC_TARGETROLE) != 0)
6537 simode1 |= ENSCSIRST;
6538#endif
6539 ahc_outb(ahc, SIMODE1, simode1);
6540 if (initiate_reset)
6541 ahc_reset_current_bus(ahc);
6542 ahc_clear_intstat(ahc);
6543 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6544 restart_needed = TRUE;
6545 }
6546
6547 /*
6548 * Clean up all the state information for the
6549 * pending transactions on this bus.
6550 */
6551 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6552 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6553 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6554
6555 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6556
6557#ifdef AHC_TARGET_MODE
6558 /*
6559 * Send an immediate notify ccb to all target more peripheral
6560 * drivers affected by this action.
6561 */
6562 for (target = 0; target <= max_scsiid; target++) {
6563 struct ahc_tmode_tstate* tstate;
6564 u_int lun;
6565
6566 tstate = ahc->enabled_targets[target];
6567 if (tstate == NULL)
6568 continue;
6569 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6570 struct ahc_tmode_lstate* lstate;
6571
6572 lstate = tstate->enabled_luns[lun];
6573 if (lstate == NULL)
6574 continue;
6575
6576 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6577 EVENT_TYPE_BUS_RESET, /*arg*/0);
6578 ahc_send_lstate_events(ahc, lstate);
6579 }
6580 }
6581#endif
6582 /* Notify the XPT that a bus reset occurred */
6583 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
9080063f 6584 CAM_LUN_WILDCARD, AC_BUS_RESET);
1da177e4
LT		 6585
6586 /*
6587 * Revert to async/narrow transfers until we renegotiate.
6588 */
6589 for (target = 0; target <= max_scsiid; target++) {
6590
6591 if (ahc->enabled_targets[target] == NULL)
6592 continue;
6593 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6594 struct ahc_devinfo devinfo;
6595
6596 ahc_compile_devinfo(&devinfo, target, initiator,
6597 CAM_LUN_WILDCARD,
6598 channel, ROLE_UNKNOWN);
6599 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6600 AHC_TRANS_CUR, /*paused*/TRUE);
6601 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6602 /*period*/0, /*offset*/0,
6603 /*ppr_options*/0, AHC_TRANS_CUR,
6604 /*paused*/TRUE);
6605 }
6606 }
6607
6608 if (restart_needed)
6609 ahc_restart(ahc);
6610 else
6611 ahc_unpause(ahc);
6612 return found;
6613}
6614
6615
6616/***************************** Residual Processing ****************************/
6617/*
6618 * Calculate the residual for a just completed SCB.
6619 */
d1d7b19d 6620static void
1da177e4
LT		 6621ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6622{
6623 struct hardware_scb *hscb;
6624 struct status_pkt *spkt;
6625 uint32_t sgptr;
6626 uint32_t resid_sgptr;
6627 uint32_t resid;
6628
6629 /*
6630 * 5 cases.
6631 * 1) No residual.
6632 * SG_RESID_VALID clear in sgptr.
6633 * 2) Transferless command
6634 * 3) Never performed any transfers.
6635 * sgptr has SG_FULL_RESID set.
6636 * 4) No residual but target did not
6637 * save data pointers after the
6638 * last transfer, so sgptr was
6639 * never updated.
6640 * 5) We have a partial residual.
6641 * Use residual_sgptr to determine
6642 * where we are.
6643 */
6644
6645 hscb = scb->hscb;
6646 sgptr = ahc_le32toh(hscb->sgptr);
6647 if ((sgptr & SG_RESID_VALID) == 0)
6648 /* Case 1 */
6649 return;
6650 sgptr &= ~SG_RESID_VALID;
6651
6652 if ((sgptr & SG_LIST_NULL) != 0)
6653 /* Case 2 */
6654 return;
6655
6656 spkt = &hscb->shared_data.status;
6657 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr);
6658 if ((sgptr & SG_FULL_RESID) != 0) {
6659 /* Case 3 */
6660 resid = ahc_get_transfer_length(scb);
6661 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6662 /* Case 4 */
6663 return;
6664 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6665 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6666 } else {
6667 struct ahc_dma_seg *sg;
6668
6669 /*
6670 * Remainder of the SG where the transfer
6671 * stopped.
6672 */
6673 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6674 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6675
6676 /* The residual sg_ptr always points to the next sg */
6677 sg--;
6678
6679 /*
6680 * Add up the contents of all residual
6681 * SG segments that are after the SG where
6682 * the transfer stopped.
6683 */
6684 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6685 sg++;
6686 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
6687 }
6688 }
6689 if ((scb->flags & SCB_SENSE) == 0)
6690 ahc_set_residual(scb, resid);
6691 else
6692 ahc_set_sense_residual(scb, resid);
6693
6694#ifdef AHC_DEBUG
6695 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6696 ahc_print_path(ahc, scb);
48813cf9 6697 printk("Handled %sResidual of %d bytes\n",
1da177e4
LT		 6698 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6699 }
6700#endif
6701}
6702
6703/******************************* Target Mode **********************************/
6704#ifdef AHC_TARGET_MODE
6705/*
6706 * Add a target mode event to this lun's queue
6707 */
6708static void
6709ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6710 u_int initiator_id, u_int event_type, u_int event_arg)
6711{
6712 struct ahc_tmode_event *event;
6713 int pending;
6714
6715 xpt_freeze_devq(lstate->path, /*count*/1);
6716 if (lstate->event_w_idx >= lstate->event_r_idx)
6717 pending = lstate->event_w_idx - lstate->event_r_idx;
6718 else
6719 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6720 - (lstate->event_r_idx - lstate->event_w_idx);
6721
6722 if (event_type == EVENT_TYPE_BUS_RESET
6723 || event_type == MSG_BUS_DEV_RESET) {
6724 /*
6725 * Any earlier events are irrelevant, so reset our buffer.
6726 * This has the effect of allowing us to deal with reset
6727 * floods (an external device holding down the reset line)
6728 * without losing the event that is really interesting.
6729 */
6730 lstate->event_r_idx = 0;
6731 lstate->event_w_idx = 0;
6732 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6733 }
6734
6735 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6736 xpt_print_path(lstate->path);
48813cf9 6737 printk("immediate event %x:%x lost\n",
1da177e4
LT		 6738 lstate->event_buffer[lstate->event_r_idx].event_type,
6739 lstate->event_buffer[lstate->event_r_idx].event_arg);
6740 lstate->event_r_idx++;
6741 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6742 lstate->event_r_idx = 0;
6743 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6744 }
6745
6746 event = &lstate->event_buffer[lstate->event_w_idx];
6747 event->initiator_id = initiator_id;
6748 event->event_type = event_type;
6749 event->event_arg = event_arg;
6750 lstate->event_w_idx++;
6751 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6752 lstate->event_w_idx = 0;
6753}
6754
6755/*
6756 * Send any target mode events queued up waiting
6757 * for immediate notify resources.
6758 */
6759void
6760ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6761{
6762 struct ccb_hdr *ccbh;
6763 struct ccb_immed_notify *inot;
6764
6765 while (lstate->event_r_idx != lstate->event_w_idx
6766 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6767 struct ahc_tmode_event *event;
6768
6769 event = &lstate->event_buffer[lstate->event_r_idx];
6770 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6771 inot = (struct ccb_immed_notify *)ccbh;
6772 switch (event->event_type) {
6773 case EVENT_TYPE_BUS_RESET:
6774 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6775 break;
6776 default:
6777 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6778 inot->message_args[0] = event->event_type;
6779 inot->message_args[1] = event->event_arg;
6780 break;
6781 }
6782 inot->initiator_id = event->initiator_id;
6783 inot->sense_len = 0;
6784 xpt_done((union ccb *)inot);
6785 lstate->event_r_idx++;
6786 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6787 lstate->event_r_idx = 0;
6788 }
6789}
6790#endif
6791
6792/******************** Sequencer Program Patching/Download *********************/
6793
6794#ifdef AHC_DUMP_SEQ
6795void
6796ahc_dumpseq(struct ahc_softc* ahc)
6797{
6798 int i;
6799
6800 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6801 ahc_outb(ahc, SEQADDR0, 0);
6802 ahc_outb(ahc, SEQADDR1, 0);
6803 for (i = 0; i < ahc->instruction_ram_size; i++) {
6804 uint8_t ins_bytes[4];
6805
6806 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
48813cf9 6807 printk("0x%08x\n", ins_bytes[0] << 24
1da177e4
LT		 6808 | ins_bytes[1] << 16
6809 | ins_bytes[2] << 8
6810 | ins_bytes[3]);
6811 }
6812}
6813#endif
6814
6815static int
6816ahc_loadseq(struct ahc_softc *ahc)
6817{
88b13609
SK		 6818 struct cs cs_table[NUM_CRITICAL_SECTIONS];
6819 u_int begin_set[NUM_CRITICAL_SECTIONS];
6820 u_int end_set[NUM_CRITICAL_SECTIONS];
980b306a 6821 const struct patch *cur_patch;
1da177e4
LT		 6822 u_int cs_count;
6823 u_int cur_cs;
6824 u_int i;
6825 u_int skip_addr;
6826 u_int sg_prefetch_cnt;
6827 int downloaded;
6828 uint8_t download_consts[7];
6829
6830 /*
6831 * Start out with 0 critical sections
6832 * that apply to this firmware load.
6833 */
6834 cs_count = 0;
6835 cur_cs = 0;
6836 memset(begin_set, 0, sizeof(begin_set));
6837 memset(end_set, 0, sizeof(end_set));
6838
6839 /* Setup downloadable constant table */
6840 download_consts[QOUTFIFO_OFFSET] = 0;
6841 if (ahc->targetcmds != NULL)
6842 download_consts[QOUTFIFO_OFFSET] += 32;
6843 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6844 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6845 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6846 sg_prefetch_cnt = ahc->pci_cachesize;
6847 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6848 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6849 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6850 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6851 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6852
6853 cur_patch = patches;
6854 downloaded = 0;
6855 skip_addr = 0;
6856 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6857 ahc_outb(ahc, SEQADDR0, 0);
6858 ahc_outb(ahc, SEQADDR1, 0);
6859
6860 for (i = 0; i < sizeof(seqprog)/4; i++) {
6861 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6862 /*
6863 * Don't download this instruction as it
6864 * is in a patch that was removed.
6865 */
6866 continue;
6867 }
6868
6869 if (downloaded == ahc->instruction_ram_size) {
6870 /*
6871 * We're about to exceed the instruction
6872 * storage capacity for this chip. Fail
6873 * the load.
6874 */
48813cf9 6875 printk("\n%s: Program too large for instruction memory "
1da177e4
LT		 6876 "size of %d!\n", ahc_name(ahc),
6877 ahc->instruction_ram_size);
6878 return (ENOMEM);
6879 }
6880
6881 /*
6882 * Move through the CS table until we find a CS
6883 * that might apply to this instruction.
6884 */
88b13609 6885 for (; cur_cs < NUM_CRITICAL_SECTIONS; cur_cs++) {
1da177e4
LT		 6886 if (critical_sections[cur_cs].end <= i) {
6887 if (begin_set[cs_count] == TRUE
6888 && end_set[cs_count] == FALSE) {
6889 cs_table[cs_count].end = downloaded;
6890 end_set[cs_count] = TRUE;
6891 cs_count++;
6892 }
6893 continue;
6894 }
6895 if (critical_sections[cur_cs].begin <= i
6896 && begin_set[cs_count] == FALSE) {
6897 cs_table[cs_count].begin = downloaded;
6898 begin_set[cs_count] = TRUE;
6899 }
6900 break;
6901 }
6902 ahc_download_instr(ahc, i, download_consts);
6903 downloaded++;
6904 }
6905
6906 ahc->num_critical_sections = cs_count;
6907 if (cs_count != 0) {
6908
6909 cs_count *= sizeof(struct cs);
48813cf9 6910 ahc->critical_sections = kmalloc(cs_count, GFP_ATOMIC);
1da177e4
LT		 6911 if (ahc->critical_sections == NULL)
6912 panic("ahc_loadseq: Could not malloc");
6913 memcpy(ahc->critical_sections, cs_table, cs_count);
6914 }
6915 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6916
6917 if (bootverbose) {
48813cf9
PE		 6918 printk(" %d instructions downloaded\n", downloaded);
6919 printk("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
1da177e4
LT		 6920 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6921 }
6922 return (0);
6923}
6924
6925static int
980b306a 6926ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch,
1da177e4
LT		 6927 u_int start_instr, u_int *skip_addr)
6928{
980b306a
DV		 6929 const struct patch *cur_patch;
6930 const struct patch *last_patch;
1da177e4
LT		 6931 u_int num_patches;
6932
6391a113 6933 num_patches = ARRAY_SIZE(patches);
1da177e4
LT		 6934 last_patch = &patches[num_patches];
6935 cur_patch = *start_patch;
6936
6937 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6938
6939 if (cur_patch->patch_func(ahc) == 0) {
6940
6941 /* Start rejecting code */
6942 *skip_addr = start_instr + cur_patch->skip_instr;
6943 cur_patch += cur_patch->skip_patch;
6944 } else {
6945 /* Accepted this patch. Advance to the next
6946 * one and wait for our intruction pointer to
6947 * hit this point.
6948 */
6949 cur_patch++;
6950 }
6951 }
6952
6953 *start_patch = cur_patch;
6954 if (start_instr < *skip_addr)
6955 /* Still skipping */
6956 return (0);
6957
6958 return (1);
6959}
6960
6961static void
6962ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6963{
6964 union ins_formats instr;
6965 struct ins_format1 *fmt1_ins;
6966 struct ins_format3 *fmt3_ins;
6967 u_int opcode;
6968
6969 /*
6970 * The firmware is always compiled into a little endian format.
6971 */
6972 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6973
6974 fmt1_ins = &instr.format1;
6975 fmt3_ins = NULL;
6976
6977 /* Pull the opcode */
6978 opcode = instr.format1.opcode;
6979 switch (opcode) {
6980 case AIC_OP_JMP:
6981 case AIC_OP_JC:
6982 case AIC_OP_JNC:
6983 case AIC_OP_CALL:
6984 case AIC_OP_JNE:
6985 case AIC_OP_JNZ:
6986 case AIC_OP_JE:
6987 case AIC_OP_JZ:
6988 {
980b306a 6989 const struct patch *cur_patch;
1da177e4
LT		 6990 int address_offset;
6991 u_int address;
6992 u_int skip_addr;
6993 u_int i;
6994
6995 fmt3_ins = &instr.format3;
6996 address_offset = 0;
6997 address = fmt3_ins->address;
6998 cur_patch = patches;
6999 skip_addr = 0;
7000
7001 for (i = 0; i < address;) {
7002
7003 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
7004
7005 if (skip_addr > i) {
7006 int end_addr;
7007
6d07cb71 7008 end_addr = min(address, skip_addr);
1da177e4
LT		 7009 address_offset += end_addr - i;
7010 i = skip_addr;
7011 } else {
7012 i++;
7013 }
7014 }
7015 address -= address_offset;
7016 fmt3_ins->address = address;
1da177e4 7017 }
e2e80164 7018 /* fall through */
1da177e4
LT		 7019 case AIC_OP_OR:
7020 case AIC_OP_AND:
7021 case AIC_OP_XOR:
7022 case AIC_OP_ADD:
7023 case AIC_OP_ADC:
7024 case AIC_OP_BMOV:
7025 if (fmt1_ins->parity != 0) {
7026 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
7027 }
7028 fmt1_ins->parity = 0;
7029 if ((ahc->features & AHC_CMD_CHAN) == 0
7030 && opcode == AIC_OP_BMOV) {
7031 /*
7032 * Block move was added at the same time
7033 * as the command channel. Verify that
7034 * this is only a move of a single element
7035 * and convert the BMOV to a MOV
7036 * (AND with an immediate of FF).
7037 */
7038 if (fmt1_ins->immediate != 1)
7039 panic("%s: BMOV not supported\n",
7040 ahc_name(ahc));
7041 fmt1_ins->opcode = AIC_OP_AND;
7042 fmt1_ins->immediate = 0xff;
7043 }
e2e80164 7044 /* fall through */
1da177e4
LT		 7045 case AIC_OP_ROL:
7046 if ((ahc->features & AHC_ULTRA2) != 0) {
7047 int i, count;
7048
7049 /* Calculate odd parity for the instruction */
7050 for (i = 0, count = 0; i < 31; i++) {
7051 uint32_t mask;
7052
7053 mask = 0x01 << i;
7054 if ((instr.integer & mask) != 0)
7055 count++;
7056 }
7057 if ((count & 0x01) == 0)
7058 instr.format1.parity = 1;
7059 } else {
7060 /* Compress the instruction for older sequencers */
7061 if (fmt3_ins != NULL) {
7062 instr.integer =
7063 fmt3_ins->immediate
7064 | (fmt3_ins->source << 8)
7065 | (fmt3_ins->address << 16)
7066 | (fmt3_ins->opcode << 25);
7067 } else {
7068 instr.integer =
7069 fmt1_ins->immediate
7070 | (fmt1_ins->source << 8)
7071 | (fmt1_ins->destination << 16)
7072 | (fmt1_ins->ret << 24)
7073 | (fmt1_ins->opcode << 25);
7074 }
7075 }
7076 /* The sequencer is a little endian cpu */
7077 instr.integer = ahc_htole32(instr.integer);
7078 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
7079 break;
7080 default:
7081 panic("Unknown opcode encountered in seq program");
7082 break;
7083 }
7084}
7085
7086int
d1d7b19d 7087ahc_print_register(const ahc_reg_parse_entry_t *table, u_int num_entries,
1da177e4
LT		 7088 const char *name, u_int address, u_int value,
7089 u_int *cur_column, u_int wrap_point)
7090{
7091 int printed;
7092 u_int printed_mask;
7093
7094 if (cur_column != NULL && *cur_column >= wrap_point) {
48813cf9 7095 printk("\n");
1da177e4
LT		 7096 *cur_column = 0;
7097 }
48813cf9 7098 printed = printk("%s[0x%x]", name, value);
1da177e4 7099 if (table == NULL) {
48813cf9 7100 printed += printk(" ");
1da177e4
LT		 7101 *cur_column += printed;
7102 return (printed);
7103 }
7104 printed_mask = 0;
7105 while (printed_mask != 0xFF) {
7106 int entry;
7107
7108 for (entry = 0; entry < num_entries; entry++) {
7109 if (((value & table[entry].mask)
7110 != table[entry].value)
7111 || ((printed_mask & table[entry].mask)
7112 == table[entry].mask))
7113 continue;
7114
48813cf9 7115 printed += printk("%s%s",
1da177e4
LT		 7116 printed_mask == 0 ? ":(" : "|",
7117 table[entry].name);
7118 printed_mask |= table[entry].mask;
7119
7120 break;
7121 }
7122 if (entry >= num_entries)
7123 break;
7124 }
7125 if (printed_mask != 0)
48813cf9 7126 printed += printk(") ");
1da177e4 7127 else
48813cf9 7128 printed += printk(" ");
1da177e4
LT		 7129 if (cur_column != NULL)
7130 *cur_column += printed;
7131 return (printed);
7132}
7133
7134void
7135ahc_dump_card_state(struct ahc_softc *ahc)
7136{
7137 struct scb *scb;
7138 struct scb_tailq *untagged_q;
7139 u_int cur_col;
7140 int paused;
7141 int target;
7142 int maxtarget;
7143 int i;
7144 uint8_t last_phase;
7145 uint8_t qinpos;
7146 uint8_t qintail;
7147 uint8_t qoutpos;
7148 uint8_t scb_index;
7149 uint8_t saved_scbptr;
7150
7151 if (ahc_is_paused(ahc)) {
7152 paused = 1;
7153 } else {
7154 paused = 0;
7155 ahc_pause(ahc);
7156 }
7157
7158 saved_scbptr = ahc_inb(ahc, SCBPTR);
7159 last_phase = ahc_inb(ahc, LASTPHASE);
48813cf9 7160 printk(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
1da177e4
LT		 7161 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
7162 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
7163 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
7164 if (paused)
48813cf9
PE		 7165 printk("Card was paused\n");
7166 printk("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
1da177e4
LT		 7167 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
7168 ahc_inb(ahc, ARG_2));
48813cf9 7169 printk("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
1da177e4
LT		 7170 ahc_inb(ahc, SCBPTR));
7171 cur_col = 0;
7172 if ((ahc->features & AHC_DT) != 0)
7173 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
7174 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
7175 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
7176 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
7177 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
7178 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
7179 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
7180 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
7181 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
7182 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
7183 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
7184 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
7185 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
7186 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
7187 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
7188 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
7189 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
7190 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
7191 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
7192 if (cur_col != 0)
48813cf9
PE		 7193 printk("\n");
7194 printk("STACK:");
1da177e4 7195 for (i = 0; i < STACK_SIZE; i++)
48813cf9
PE		 7196 printk(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
7197 printk("\nSCB count = %d\n", ahc->scb_data->numscbs);
7198 printk("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
7199 printk("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
1da177e4 7200 /* QINFIFO */
48813cf9 7201 printk("QINFIFO entries: ");
1da177e4
LT		 7202 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
7203 qinpos = ahc_inb(ahc, SNSCB_QOFF);
7204 ahc_outb(ahc, SNSCB_QOFF, qinpos);
7205 } else
7206 qinpos = ahc_inb(ahc, QINPOS);
7207 qintail = ahc->qinfifonext;
7208 while (qinpos != qintail) {
48813cf9 7209 printk("%d ", ahc->qinfifo[qinpos]);
1da177e4
LT		 7210 qinpos++;
7211 }
48813cf9 7212 printk("\n");
1da177e4 7213
48813cf9 7214 printk("Waiting Queue entries: ");
1da177e4
LT		 7215 scb_index = ahc_inb(ahc, WAITING_SCBH);
7216 i = 0;
7217 while (scb_index != SCB_LIST_NULL && i++ < 256) {
7218 ahc_outb(ahc, SCBPTR, scb_index);
48813cf9 7219 printk("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
1da177e4
LT		 7220 scb_index = ahc_inb(ahc, SCB_NEXT);
7221 }
48813cf9 7222 printk("\n");
1da177e4 7223
48813cf9 7224 printk("Disconnected Queue entries: ");
1da177e4
LT		 7225 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
7226 i = 0;
7227 while (scb_index != SCB_LIST_NULL && i++ < 256) {
7228 ahc_outb(ahc, SCBPTR, scb_index);
48813cf9 7229 printk("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
1da177e4
LT		 7230 scb_index = ahc_inb(ahc, SCB_NEXT);
7231 }
48813cf9 7232 printk("\n");
1da177e4
LT		 7233
7234 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
48813cf9 7235 printk("QOUTFIFO entries: ");
1da177e4
LT		 7236 qoutpos = ahc->qoutfifonext;
7237 i = 0;
7238 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
48813cf9 7239 printk("%d ", ahc->qoutfifo[qoutpos]);
1da177e4
LT		 7240 qoutpos++;
7241 }
48813cf9 7242 printk("\n");
1da177e4 7243
48813cf9 7244 printk("Sequencer Free SCB List: ");
1da177e4
LT		 7245 scb_index = ahc_inb(ahc, FREE_SCBH);
7246 i = 0;
7247 while (scb_index != SCB_LIST_NULL && i++ < 256) {
7248 ahc_outb(ahc, SCBPTR, scb_index);
48813cf9 7249 printk("%d ", scb_index);
1da177e4
LT		 7250 scb_index = ahc_inb(ahc, SCB_NEXT);
7251 }
48813cf9 7252 printk("\n");
1da177e4 7253
48813cf9 7254 printk("Sequencer SCB Info: ");
1da177e4
LT		 7255 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
7256 ahc_outb(ahc, SCBPTR, i);
48813cf9 7257 cur_col = printk("\n%3d ", i);
1da177e4
LT		 7258
7259 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
7260 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
7261 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
7262 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
7263 }
48813cf9 7264 printk("\n");
1da177e4 7265
48813cf9 7266 printk("Pending list: ");
1da177e4
LT		 7267 i = 0;
7268 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7269 if (i++ > 256)
7270 break;
48813cf9 7271 cur_col = printk("\n%3d ", scb->hscb->tag);
1da177e4
LT		 7272 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
7273 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
7274 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
7275 if ((ahc->flags & AHC_PAGESCBS) == 0) {
7276 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
48813cf9 7277 printk("(");
1da177e4
LT		 7278 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
7279 &cur_col, 60);
7280 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
48813cf9 7281 printk(")");
1da177e4
LT		 7282 }
7283 }
48813cf9 7284 printk("\n");
1da177e4 7285
48813cf9 7286 printk("Kernel Free SCB list: ");
1da177e4
LT		 7287 i = 0;
7288 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
7289 if (i++ > 256)
7290 break;
48813cf9 7291 printk("%d ", scb->hscb->tag);
1da177e4 7292 }
48813cf9 7293 printk("\n");
1da177e4
LT		 7294
7295 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
7296 for (target = 0; target <= maxtarget; target++) {
7297 untagged_q = &ahc->untagged_queues[target];
7298 if (TAILQ_FIRST(untagged_q) == NULL)
7299 continue;
48813cf9 7300 printk("Untagged Q(%d): ", target);
1da177e4
LT		 7301 i = 0;
7302 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
7303 if (i++ > 256)
7304 break;
48813cf9 7305 printk("%d ", scb->hscb->tag);
1da177e4 7306 }
48813cf9 7307 printk("\n");
1da177e4
LT		 7308 }
7309
48813cf9 7310 printk("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
1da177e4
LT		 7311 ahc_outb(ahc, SCBPTR, saved_scbptr);
7312 if (paused == 0)
7313 ahc_unpause(ahc);
7314}
7315
7316/************************* Target Mode ****************************************/
7317#ifdef AHC_TARGET_MODE
7318cam_status
7319ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
7320 struct ahc_tmode_tstate **tstate,
7321 struct ahc_tmode_lstate **lstate,
7322 int notfound_failure)
7323{
7324
7325 if ((ahc->features & AHC_TARGETMODE) == 0)
7326 return (CAM_REQ_INVALID);
7327
7328 /*
7329 * Handle the 'black hole' device that sucks up
7330 * requests to unattached luns on enabled targets.
7331 */
7332 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
7333 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
7334 *tstate = NULL;
7335 *lstate = ahc->black_hole;
7336 } else {
7337 u_int max_id;
7338
2b89dad0
HR		 7339 max_id = (ahc->features & AHC_WIDE) ? 16 : 8;
7340 if (ccb->ccb_h.target_id >= max_id)
1da177e4
LT		 7341 return (CAM_TID_INVALID);
7342
7343 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
7344 return (CAM_LUN_INVALID);
7345
7346 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
7347 *lstate = NULL;
7348 if (*tstate != NULL)
7349 *lstate =
7350 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
7351 }
7352
7353 if (notfound_failure != 0 && *lstate == NULL)
7354 return (CAM_PATH_INVALID);
7355
7356 return (CAM_REQ_CMP);
7357}
7358
7359void
7360ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
7361{
7362 struct ahc_tmode_tstate *tstate;
7363 struct ahc_tmode_lstate *lstate;
7364 struct ccb_en_lun *cel;
7365 cam_status status;
7366 u_long s;
7367 u_int target;
7368 u_int lun;
7369 u_int target_mask;
7370 u_int our_id;
7371 int error;
7372 char channel;
7373
7374 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
7375 /*notfound_failure*/FALSE);
7376
7377 if (status != CAM_REQ_CMP) {
7378 ccb->ccb_h.status = status;
7379 return;
7380 }
7381
7382 if (cam_sim_bus(sim) == 0)
7383 our_id = ahc->our_id;
7384 else
7385 our_id = ahc->our_id_b;
7386
7387 if (ccb->ccb_h.target_id != our_id) {
7388 /*
7389 * our_id represents our initiator ID, or
7390 * the ID of the first target to have an
7391 * enabled lun in target mode. There are
7392 * two cases that may preclude enabling a
7393 * target id other than our_id.
7394 *
7395 * o our_id is for an active initiator role.
7396 * Since the hardware does not support
7397 * reselections to the initiator role at
7398 * anything other than our_id, and our_id
7399 * is used by the hardware to indicate the
7400 * ID to use for both select-out and
7401 * reselect-out operations, the only target
7402 * ID we can support in this mode is our_id.
7403 *
7404 * o The MULTARGID feature is not available and
7405 * a previous target mode ID has been enabled.
7406 */
7407 if ((ahc->features & AHC_MULTIROLE) != 0) {
7408
7409 if ((ahc->features & AHC_MULTI_TID) != 0
7410 && (ahc->flags & AHC_INITIATORROLE) != 0) {
7411 /*
7412 * Only allow additional targets if
7413 * the initiator role is disabled.
7414 * The hardware cannot handle a re-select-in
7415 * on the initiator id during a re-select-out
7416 * on a different target id.
7417 */
7418 status = CAM_TID_INVALID;
7419 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
7420 || ahc->enabled_luns > 0) {
7421 /*
7422 * Only allow our target id to change
7423 * if the initiator role is not configured
7424 * and there are no enabled luns which
7425 * are attached to the currently registered
7426 * scsi id.
7427 */
7428 status = CAM_TID_INVALID;
7429 }
7430 } else if ((ahc->features & AHC_MULTI_TID) == 0
7431 && ahc->enabled_luns > 0) {
7432
7433 status = CAM_TID_INVALID;
7434 }
7435 }
7436
7437 if (status != CAM_REQ_CMP) {
7438 ccb->ccb_h.status = status;
7439 return;
7440 }
7441
7442 /*
7443 * We now have an id that is valid.
7444 * If we aren't in target mode, switch modes.
7445 */
7446 if ((ahc->flags & AHC_TARGETROLE) == 0
7447 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7448 u_long s;
7449 ahc_flag saved_flags;
7450
48813cf9 7451 printk("Configuring Target Mode\n");
1da177e4
LT		 7452 ahc_lock(ahc, &s);
7453 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
7454 ccb->ccb_h.status = CAM_BUSY;
7455 ahc_unlock(ahc, &s);
7456 return;
7457 }
7458 saved_flags = ahc->flags;
7459 ahc->flags |= AHC_TARGETROLE;
7460 if ((ahc->features & AHC_MULTIROLE) == 0)
7461 ahc->flags &= ~AHC_INITIATORROLE;
7462 ahc_pause(ahc);
7463 error = ahc_loadseq(ahc);
7464 if (error != 0) {
7465 /*
7466 * Restore original configuration and notify
7467 * the caller that we cannot support target mode.
7468 * Since the adapter started out in this
7469 * configuration, the firmware load will succeed,
7470 * so there is no point in checking ahc_loadseq's
7471 * return value.
7472 */
7473 ahc->flags = saved_flags;
7474 (void)ahc_loadseq(ahc);
7475 ahc_restart(ahc);
7476 ahc_unlock(ahc, &s);
7477 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
7478 return;
7479 }
7480 ahc_restart(ahc);
7481 ahc_unlock(ahc, &s);
7482 }
7483 cel = &ccb->cel;
7484 target = ccb->ccb_h.target_id;
7485 lun = ccb->ccb_h.target_lun;
7486 channel = SIM_CHANNEL(ahc, sim);
7487 target_mask = 0x01 << target;
7488 if (channel == 'B')
7489 target_mask <<= 8;
7490
7491 if (cel->enable != 0) {
7492 u_int scsiseq;
7493
7494 /* Are we already enabled?? */
7495 if (lstate != NULL) {
7496 xpt_print_path(ccb->ccb_h.path);
48813cf9 7497 printk("Lun already enabled\n");
1da177e4
LT		 7498 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
7499 return;
7500 }
7501
7502 if (cel->grp6_len != 0
7503 || cel->grp7_len != 0) {
7504 /*
7505 * Don't (yet?) support vendor
7506 * specific commands.
7507 */
7508 ccb->ccb_h.status = CAM_REQ_INVALID;
48813cf9 7509 printk("Non-zero Group Codes\n");
1da177e4
LT		 7510 return;
7511 }
7512
7513 /*
7514 * Seems to be okay.
7515 * Setup our data structures.
7516 */
7517 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
7518 tstate = ahc_alloc_tstate(ahc, target, channel);
7519 if (tstate == NULL) {
7520 xpt_print_path(ccb->ccb_h.path);
48813cf9 7521 printk("Couldn't allocate tstate\n");
1da177e4
LT		 7522 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7523 return;
7524 }
7525 }
114fc1d9 7526 lstate = kzalloc(sizeof(*lstate), GFP_ATOMIC);
1da177e4
LT		 7527 if (lstate == NULL) {
7528 xpt_print_path(ccb->ccb_h.path);
48813cf9 7529 printk("Couldn't allocate lstate\n");
1da177e4
LT		 7530 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7531 return;
7532 }
1da177e4
LT		 7533 status = xpt_create_path(&lstate->path, /*periph*/NULL,
7534 xpt_path_path_id(ccb->ccb_h.path),
7535 xpt_path_target_id(ccb->ccb_h.path),
7536 xpt_path_lun_id(ccb->ccb_h.path));
7537 if (status != CAM_REQ_CMP) {
48813cf9 7538 kfree(lstate);
1da177e4 7539 xpt_print_path(ccb->ccb_h.path);
48813cf9 7540 printk("Couldn't allocate path\n");
1da177e4
LT		 7541 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7542 return;
7543 }
7544 SLIST_INIT(&lstate->accept_tios);
7545 SLIST_INIT(&lstate->immed_notifies);
7546 ahc_lock(ahc, &s);
7547 ahc_pause(ahc);
7548 if (target != CAM_TARGET_WILDCARD) {
7549 tstate->enabled_luns[lun] = lstate;
7550 ahc->enabled_luns++;
7551
7552 if ((ahc->features & AHC_MULTI_TID) != 0) {
7553 u_int targid_mask;
7554
7555 targid_mask = ahc_inb(ahc, TARGID)
7556 | (ahc_inb(ahc, TARGID + 1) << 8);
7557
7558 targid_mask |= target_mask;
7559 ahc_outb(ahc, TARGID, targid_mask);
7560 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7561
7562 ahc_update_scsiid(ahc, targid_mask);
7563 } else {
7564 u_int our_id;
7565 char channel;
7566
7567 channel = SIM_CHANNEL(ahc, sim);
7568 our_id = SIM_SCSI_ID(ahc, sim);
7569
7570 /*
7571 * This can only happen if selections
7572 * are not enabled
7573 */
7574 if (target != our_id) {
7575 u_int sblkctl;
7576 char cur_channel;
7577 int swap;
7578
7579 sblkctl = ahc_inb(ahc, SBLKCTL);
7580 cur_channel = (sblkctl & SELBUSB)
7581 ? 'B' : 'A';
7582 if ((ahc->features & AHC_TWIN) == 0)
7583 cur_channel = 'A';
7584 swap = cur_channel != channel;
7585 if (channel == 'A')
7586 ahc->our_id = target;
7587 else
7588 ahc->our_id_b = target;
7589
7590 if (swap)
7591 ahc_outb(ahc, SBLKCTL,
7592 sblkctl ^ SELBUSB);
7593
7594 ahc_outb(ahc, SCSIID, target);
7595
7596 if (swap)
7597 ahc_outb(ahc, SBLKCTL, sblkctl);
7598 }
7599 }
7600 } else
7601 ahc->black_hole = lstate;
7602 /* Allow select-in operations */
7603 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7604 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7605 scsiseq |= ENSELI;
7606 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7607 scsiseq = ahc_inb(ahc, SCSISEQ);
7608 scsiseq |= ENSELI;
7609 ahc_outb(ahc, SCSISEQ, scsiseq);
7610 }
7611 ahc_unpause(ahc);
7612 ahc_unlock(ahc, &s);
7613 ccb->ccb_h.status = CAM_REQ_CMP;
7614 xpt_print_path(ccb->ccb_h.path);
48813cf9 7615 printk("Lun now enabled for target mode\n");
1da177e4
LT		 7616 } else {
7617 struct scb *scb;
7618 int i, empty;
7619
7620 if (lstate == NULL) {
7621 ccb->ccb_h.status = CAM_LUN_INVALID;
7622 return;
7623 }
7624
7625 ahc_lock(ahc, &s);
7626
7627 ccb->ccb_h.status = CAM_REQ_CMP;
7628 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7629 struct ccb_hdr *ccbh;
7630
7631 ccbh = &scb->io_ctx->ccb_h;
7632 if (ccbh->func_code == XPT_CONT_TARGET_IO
7633 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
48813cf9 7634 printk("CTIO pending\n");
1da177e4
LT		 7635 ccb->ccb_h.status = CAM_REQ_INVALID;
7636 ahc_unlock(ahc, &s);
7637 return;
7638 }
7639 }
7640
7641 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
48813cf9 7642 printk("ATIOs pending\n");
1da177e4
LT		 7643 ccb->ccb_h.status = CAM_REQ_INVALID;
7644 }
7645
7646 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
48813cf9 7647 printk("INOTs pending\n");
1da177e4
LT		 7648 ccb->ccb_h.status = CAM_REQ_INVALID;
7649 }
7650
7651 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7652 ahc_unlock(ahc, &s);
7653 return;
7654 }
7655
7656 xpt_print_path(ccb->ccb_h.path);
48813cf9 7657 printk("Target mode disabled\n");
1da177e4 7658 xpt_free_path(lstate->path);
48813cf9 7659 kfree(lstate);
1da177e4
LT		 7660
7661 ahc_pause(ahc);
7662 /* Can we clean up the target too? */
7663 if (target != CAM_TARGET_WILDCARD) {
7664 tstate->enabled_luns[lun] = NULL;
7665 ahc->enabled_luns--;
7666 for (empty = 1, i = 0; i < 8; i++)
7667 if (tstate->enabled_luns[i] != NULL) {
7668 empty = 0;
7669 break;
7670 }
7671
7672 if (empty) {
7673 ahc_free_tstate(ahc, target, channel,
7674 /*force*/FALSE);
7675 if (ahc->features & AHC_MULTI_TID) {
7676 u_int targid_mask;
7677
7678 targid_mask = ahc_inb(ahc, TARGID)
7679 | (ahc_inb(ahc, TARGID + 1)
7680 << 8);
7681
7682 targid_mask &= ~target_mask;
7683 ahc_outb(ahc, TARGID, targid_mask);
7684 ahc_outb(ahc, TARGID+1,
7685 (targid_mask >> 8));
7686 ahc_update_scsiid(ahc, targid_mask);
7687 }
7688 }
7689 } else {
7690
7691 ahc->black_hole = NULL;
7692
7693 /*
7694 * We can't allow selections without
7695 * our black hole device.
7696 */
7697 empty = TRUE;
7698 }
7699 if (ahc->enabled_luns == 0) {
7700 /* Disallow select-in */
7701 u_int scsiseq;
7702
7703 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7704 scsiseq &= ~ENSELI;
7705 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7706 scsiseq = ahc_inb(ahc, SCSISEQ);
7707 scsiseq &= ~ENSELI;
7708 ahc_outb(ahc, SCSISEQ, scsiseq);
7709
7710 if ((ahc->features & AHC_MULTIROLE) == 0) {
48813cf9 7711 printk("Configuring Initiator Mode\n");
1da177e4
LT		 7712 ahc->flags &= ~AHC_TARGETROLE;
7713 ahc->flags |= AHC_INITIATORROLE;
7714 /*
7715 * Returning to a configuration that
7716 * fit previously will always succeed.
7717 */
7718 (void)ahc_loadseq(ahc);
7719 ahc_restart(ahc);
7720 /*
7721 * Unpaused. The extra unpause
7722 * that follows is harmless.
7723 */
7724 }
7725 }
7726 ahc_unpause(ahc);
7727 ahc_unlock(ahc, &s);
7728 }
7729}
7730
7731static void
7732ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7733{
7734 u_int scsiid_mask;
7735 u_int scsiid;
7736
7737 if ((ahc->features & AHC_MULTI_TID) == 0)
7738 panic("ahc_update_scsiid called on non-multitid unit\n");
7739
7740 /*
7741 * Since we will rely on the TARGID mask
7742 * for selection enables, ensure that OID
7743 * in SCSIID is not set to some other ID
7744 * that we don't want to allow selections on.
7745 */
7746 if ((ahc->features & AHC_ULTRA2) != 0)
7747 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7748 else
7749 scsiid = ahc_inb(ahc, SCSIID);
7750 scsiid_mask = 0x1 << (scsiid & OID);
7751 if ((targid_mask & scsiid_mask) == 0) {
7752 u_int our_id;
7753
7754 /* ffs counts from 1 */
7755 our_id = ffs(targid_mask);
7756 if (our_id == 0)
7757 our_id = ahc->our_id;
7758 else
7759 our_id--;
7760 scsiid &= TID;
7761 scsiid |= our_id;
7762 }
7763 if ((ahc->features & AHC_ULTRA2) != 0)
7764 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7765 else
7766 ahc_outb(ahc, SCSIID, scsiid);
7767}
7768
d1d7b19d 7769static void
1da177e4
LT		 7770ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7771{
7772 struct target_cmd *cmd;
7773
7774 /*
7775 * If the card supports auto-access pause,
7776 * we can access the card directly regardless
7777 * of whether it is paused or not.
7778 */
7779 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7780 paused = TRUE;
7781
7782 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7783 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7784
7785 /*
7786 * Only advance through the queue if we
7787 * have the resources to process the command.
7788 */
7789 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7790 break;
7791
7792 cmd->cmd_valid = 0;
7793 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
7794 ahc->shared_data_dmamap,
7795 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7796 sizeof(struct target_cmd),
7797 BUS_DMASYNC_PREREAD);
7798 ahc->tqinfifonext++;
7799
7800 /*
7801 * Lazily update our position in the target mode incoming
7802 * command queue as seen by the sequencer.
7803 */
7804 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7805 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7806 u_int hs_mailbox;
7807
7808 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7809 hs_mailbox &= ~HOST_TQINPOS;
7810 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7811 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7812 } else {
7813 if (!paused)
7814 ahc_pause(ahc);
7815 ahc_outb(ahc, KERNEL_TQINPOS,
7816 ahc->tqinfifonext & HOST_TQINPOS);
7817 if (!paused)
7818 ahc_unpause(ahc);
7819 }
7820 }
7821 }
7822}
7823
7824static int
7825ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7826{
7827 struct ahc_tmode_tstate *tstate;
7828 struct ahc_tmode_lstate *lstate;
7829 struct ccb_accept_tio *atio;
7830 uint8_t *byte;
7831 int initiator;
7832 int target;
7833 int lun;
7834
7835 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7836 target = SCSIID_OUR_ID(cmd->scsiid);
7837 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7838
7839 byte = cmd->bytes;
7840 tstate = ahc->enabled_targets[target];
7841 lstate = NULL;
7842 if (tstate != NULL)
7843 lstate = tstate->enabled_luns[lun];
7844
7845 /*
7846 * Commands for disabled luns go to the black hole driver.
7847 */
7848 if (lstate == NULL)
7849 lstate = ahc->black_hole;
7850
7851 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7852 if (atio == NULL) {
7853 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7854 /*
7855 * Wait for more ATIOs from the peripheral driver for this lun.
7856 */
7857 if (bootverbose)
48813cf9 7858 printk("%s: ATIOs exhausted\n", ahc_name(ahc));
1da177e4
LT		 7859 return (1);
7860 } else
7861 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7862#if 0
48813cf9 7863 printk("Incoming command from %d for %d:%d%s\n",
1da177e4
LT		 7864 initiator, target, lun,
7865 lstate == ahc->black_hole ? "(Black Holed)" : "");
7866#endif
7867 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7868
7869 if (lstate == ahc->black_hole) {
7870 /* Fill in the wildcards */
7871 atio->ccb_h.target_id = target;
7872 atio->ccb_h.target_lun = lun;
7873 }
7874
7875 /*
7876 * Package it up and send it off to
7877 * whomever has this lun enabled.
7878 */
7879 atio->sense_len = 0;
7880 atio->init_id = initiator;
7881 if (byte[0] != 0xFF) {
7882 /* Tag was included */
7883 atio->tag_action = *byte++;
7884 atio->tag_id = *byte++;
7885 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
7886 } else {
7887 atio->ccb_h.flags = 0;
7888 }
7889 byte++;
7890
7891 /* Okay. Now determine the cdb size based on the command code */
7892 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7893 case 0:
7894 atio->cdb_len = 6;
7895 break;
7896 case 1:
7897 case 2:
7898 atio->cdb_len = 10;
7899 break;
7900 case 4:
7901 atio->cdb_len = 16;
7902 break;
7903 case 5:
7904 atio->cdb_len = 12;
7905 break;
7906 case 3:
7907 default:
7908 /* Only copy the opcode. */
7909 atio->cdb_len = 1;
48813cf9 7910 printk("Reserved or VU command code type encountered\n");
1da177e4
LT		 7911 break;
7912 }
7913
7914 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7915
7916 atio->ccb_h.status |= CAM_CDB_RECVD;
7917
7918 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7919 /*
7920 * We weren't allowed to disconnect.
7921 * We're hanging on the bus until a
7922 * continue target I/O comes in response
7923 * to this accept tio.
7924 */
7925#if 0
48813cf9 7926 printk("Received Immediate Command %d:%d:%d - %p\n",
1da177e4
LT		 7927 initiator, target, lun, ahc->pending_device);
7928#endif
7929 ahc->pending_device = lstate;
7930 ahc_freeze_ccb((union ccb *)atio);
7931 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7932 }
7933 xpt_done((union ccb*)atio);
7934 return (0);
7935}
7936
7937#endif
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