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1da177e4 LT |
1 | /* |
2 | * Aic7xxx register and scratch ram definitions. | |
3 | * | |
4 | * Copyright (c) 1994-1998 Justin Gibbs. | |
5 | * All rights reserved. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions, and the following disclaimer, | |
12 | * without modification, immediately at the beginning of the file. | |
13 | * 2. The name of the author may not be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * Where this Software is combined with software released under the terms of | |
17 | * the GNU General Public License ("GPL") and the terms of the GPL would require the | |
18 | * combined work to also be released under the terms of the GPL, the terms | |
19 | * and conditions of this License will apply in addition to those of the | |
20 | * GPL with the exception of any terms or conditions of this License that | |
21 | * conflict with, or are expressly prohibited by, the GPL. | |
22 | * | |
23 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | |
24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
26 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR | |
27 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
28 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
29 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
30 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
31 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
32 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
33 | * SUCH DAMAGE. | |
34 | * | |
35 | * $Id: aic7xxx.reg,v 1.4 1997/06/27 19:38:39 gibbs Exp $ | |
36 | */ | |
37 | ||
38 | /* | |
39 | * This file is processed by the aic7xxx_asm utility for use in assembling | |
40 | * firmware for the aic7xxx family of SCSI host adapters as well as to generate | |
41 | * a C header file for use in the kernel portion of the Aic7xxx driver. | |
42 | * | |
43 | * All page numbers refer to the Adaptec AIC-7770 Data Book available from | |
44 | * Adaptec's Technical Documents Department 1-800-934-2766 | |
45 | */ | |
46 | ||
47 | /* | |
48 | * SCSI Sequence Control (p. 3-11). | |
49 | * Each bit, when set starts a specific SCSI sequence on the bus | |
50 | */ | |
51 | register SCSISEQ { | |
52 | address 0x000 | |
53 | access_mode RW | |
54 | bit TEMODE 0x80 | |
55 | bit ENSELO 0x40 | |
56 | bit ENSELI 0x20 | |
57 | bit ENRSELI 0x10 | |
58 | bit ENAUTOATNO 0x08 | |
59 | bit ENAUTOATNI 0x04 | |
60 | bit ENAUTOATNP 0x02 | |
61 | bit SCSIRSTO 0x01 | |
62 | } | |
63 | ||
64 | /* | |
65 | * SCSI Transfer Control 0 Register (pp. 3-13). | |
66 | * Controls the SCSI module data path. | |
67 | */ | |
68 | register SXFRCTL0 { | |
69 | address 0x001 | |
70 | access_mode RW | |
71 | bit DFON 0x80 | |
72 | bit DFPEXP 0x40 | |
73 | bit FAST20 0x20 | |
74 | bit CLRSTCNT 0x10 | |
75 | bit SPIOEN 0x08 | |
76 | bit SCAMEN 0x04 | |
77 | bit CLRCHN 0x02 | |
78 | } | |
79 | ||
80 | /* | |
81 | * SCSI Transfer Control 1 Register (pp. 3-14,15). | |
82 | * Controls the SCSI module data path. | |
83 | */ | |
84 | register SXFRCTL1 { | |
85 | address 0x002 | |
86 | access_mode RW | |
87 | bit BITBUCKET 0x80 | |
88 | bit SWRAPEN 0x40 | |
89 | bit ENSPCHK 0x20 | |
90 | mask STIMESEL 0x18 | |
91 | bit ENSTIMER 0x04 | |
92 | bit ACTNEGEN 0x02 | |
93 | bit STPWEN 0x01 /* Powered Termination */ | |
94 | } | |
95 | ||
96 | /* | |
97 | * SCSI Control Signal Read Register (p. 3-15). | |
98 | * Reads the actual state of the SCSI bus pins | |
99 | */ | |
100 | register SCSISIGI { | |
101 | address 0x003 | |
102 | access_mode RO | |
103 | bit CDI 0x80 | |
104 | bit IOI 0x40 | |
105 | bit MSGI 0x20 | |
106 | bit ATNI 0x10 | |
107 | bit SELI 0x08 | |
108 | bit BSYI 0x04 | |
109 | bit REQI 0x02 | |
110 | bit ACKI 0x01 | |
111 | /* | |
112 | * Possible phases in SCSISIGI | |
113 | */ | |
114 | mask PHASE_MASK CDI|IOI|MSGI | |
115 | mask P_DATAOUT 0x00 | |
116 | mask P_DATAIN IOI | |
117 | mask P_COMMAND CDI | |
118 | mask P_MESGOUT CDI|MSGI | |
119 | mask P_STATUS CDI|IOI | |
120 | mask P_MESGIN CDI|IOI|MSGI | |
121 | } | |
122 | ||
123 | /* | |
124 | * SCSI Control Signal Write Register (p. 3-16). | |
125 | * Writing to this register modifies the control signals on the bus. Only | |
126 | * those signals that are allowed in the current mode (Initiator/Target) are | |
127 | * asserted. | |
128 | */ | |
129 | register SCSISIGO { | |
130 | address 0x003 | |
131 | access_mode WO | |
132 | bit CDO 0x80 | |
133 | bit IOO 0x40 | |
134 | bit MSGO 0x20 | |
135 | bit ATNO 0x10 | |
136 | bit SELO 0x08 | |
137 | bit BSYO 0x04 | |
138 | bit REQO 0x02 | |
139 | bit ACKO 0x01 | |
140 | /* | |
141 | * Possible phases to write into SCSISIG0 | |
142 | */ | |
143 | mask PHASE_MASK CDI|IOI|MSGI | |
144 | mask P_DATAOUT 0x00 | |
145 | mask P_DATAIN IOI | |
146 | mask P_COMMAND CDI | |
147 | mask P_MESGOUT CDI|MSGI | |
148 | mask P_STATUS CDI|IOI | |
149 | mask P_MESGIN CDI|IOI|MSGI | |
150 | } | |
151 | ||
152 | /* | |
153 | * SCSI Rate Control (p. 3-17). | |
154 | * Contents of this register determine the Synchronous SCSI data transfer | |
155 | * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the | |
156 | * SOFS (3:0) bits disables synchronous data transfers. Any offset value | |
157 | * greater than 0 enables synchronous transfers. | |
158 | */ | |
159 | register SCSIRATE { | |
160 | address 0x004 | |
161 | access_mode RW | |
162 | bit WIDEXFER 0x80 /* Wide transfer control */ | |
163 | mask SXFR 0x70 /* Sync transfer rate */ | |
164 | mask SXFR_ULTRA2 0x7f /* Sync transfer rate */ | |
165 | mask SOFS 0x0f /* Sync offset */ | |
166 | } | |
167 | ||
168 | /* | |
169 | * SCSI ID (p. 3-18). | |
170 | * Contains the ID of the board and the current target on the | |
171 | * selected channel. | |
172 | */ | |
173 | register SCSIID { | |
174 | address 0x005 | |
175 | access_mode RW | |
176 | mask TID 0xf0 /* Target ID mask */ | |
177 | mask OID 0x0f /* Our ID mask */ | |
178 | /* | |
179 | * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) | |
180 | * The aic7890/91 allow an offset of up to 127 transfers in both wide | |
181 | * and narrow mode. | |
182 | */ | |
183 | alias SCSIOFFSET | |
184 | mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ | |
185 | } | |
186 | ||
187 | /* | |
188 | * SCSI Latched Data (p. 3-19). | |
189 | * Read/Write latches used to transfer data on the SCSI bus during | |
190 | * Automatic or Manual PIO mode. SCSIDATH can be used for the | |
191 | * upper byte of a 16bit wide asynchronouse data phase transfer. | |
192 | */ | |
193 | register SCSIDATL { | |
194 | address 0x006 | |
195 | access_mode RW | |
196 | } | |
197 | ||
198 | register SCSIDATH { | |
199 | address 0x007 | |
200 | access_mode RW | |
201 | } | |
202 | ||
203 | /* | |
204 | * SCSI Transfer Count (pp. 3-19,20) | |
205 | * These registers count down the number of bytes transferred | |
206 | * across the SCSI bus. The counter is decremented only once | |
207 | * the data has been safely transferred. SDONE in SSTAT0 is | |
208 | * set when STCNT goes to 0 | |
209 | */ | |
210 | register STCNT { | |
211 | address 0x008 | |
212 | size 3 | |
213 | access_mode RW | |
214 | } | |
215 | ||
216 | /* | |
217 | * Option Mode Register (Alternate Mode) (p. 5-198) | |
218 | * This register is used to set certain options on Ultra3 based chips. | |
219 | * The chip must be in alternate mode (bit ALT_MODE in SFUNCT must be set) | |
220 | */ | |
221 | register OPTIONMODE { | |
222 | address 0x008 | |
223 | access_mode RW | |
224 | bit AUTORATEEN 0x80 | |
225 | bit AUTOACKEN 0x40 | |
226 | bit ATNMGMNTEN 0x20 | |
227 | bit BUSFREEREV 0x10 | |
228 | bit EXPPHASEDIS 0x08 | |
229 | bit SCSIDATL_IMGEN 0x04 | |
230 | bit AUTO_MSGOUT_DE 0x02 | |
231 | bit DIS_MSGIN_DUALEDGE 0x01 | |
232 | } | |
233 | ||
234 | ||
235 | /* | |
236 | * Clear SCSI Interrupt 0 (p. 3-20) | |
237 | * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. | |
238 | */ | |
239 | register CLRSINT0 { | |
240 | address 0x00b | |
241 | access_mode WO | |
242 | bit CLRSELDO 0x40 | |
243 | bit CLRSELDI 0x20 | |
244 | bit CLRSELINGO 0x10 | |
245 | bit CLRSWRAP 0x08 | |
246 | bit CLRSPIORDY 0x02 | |
247 | } | |
248 | ||
249 | /* | |
250 | * SCSI Status 0 (p. 3-21) | |
251 | * Contains one set of SCSI Interrupt codes | |
252 | * These are most likely of interest to the sequencer | |
253 | */ | |
254 | register SSTAT0 { | |
255 | address 0x00b | |
256 | access_mode RO | |
257 | bit TARGET 0x80 /* Board acting as target */ | |
258 | bit SELDO 0x40 /* Selection Done */ | |
259 | bit SELDI 0x20 /* Board has been selected */ | |
260 | bit SELINGO 0x10 /* Selection In Progress */ | |
261 | bit SWRAP 0x08 /* 24bit counter wrap */ | |
262 | bit IOERR 0x08 /* LVD Tranceiver mode changed */ | |
263 | bit SDONE 0x04 /* STCNT = 0x000000 */ | |
264 | bit SPIORDY 0x02 /* SCSI PIO Ready */ | |
265 | bit DMADONE 0x01 /* DMA transfer completed */ | |
266 | } | |
267 | ||
268 | /* | |
269 | * Clear SCSI Interrupt 1 (p. 3-23) | |
270 | * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. | |
271 | */ | |
272 | register CLRSINT1 { | |
273 | address 0x00c | |
274 | access_mode WO | |
275 | bit CLRSELTIMEO 0x80 | |
276 | bit CLRATNO 0x40 | |
277 | bit CLRSCSIRSTI 0x20 | |
278 | bit CLRBUSFREE 0x08 | |
279 | bit CLRSCSIPERR 0x04 | |
280 | bit CLRPHASECHG 0x02 | |
281 | bit CLRREQINIT 0x01 | |
282 | } | |
283 | ||
284 | /* | |
285 | * SCSI Status 1 (p. 3-24) | |
286 | */ | |
287 | register SSTAT1 { | |
288 | address 0x00c | |
289 | access_mode RO | |
290 | bit SELTO 0x80 | |
291 | bit ATNTARG 0x40 | |
292 | bit SCSIRSTI 0x20 | |
293 | bit PHASEMIS 0x10 | |
294 | bit BUSFREE 0x08 | |
295 | bit SCSIPERR 0x04 | |
296 | bit PHASECHG 0x02 | |
297 | bit REQINIT 0x01 | |
298 | } | |
299 | ||
300 | /* | |
301 | * SCSI Status 2 (pp. 3-25,26) | |
302 | */ | |
303 | register SSTAT2 { | |
304 | address 0x00d | |
305 | access_mode RO | |
306 | bit OVERRUN 0x80 | |
307 | bit SHVALID 0x40 | |
308 | bit WIDE_RES 0x20 | |
309 | bit EXP_ACTIVE 0x10 /* SCSI Expander Active */ | |
310 | bit CRCVALERR 0x08 /* CRC Value Error */ | |
311 | bit CRCENDERR 0x04 /* CRC End Error */ | |
312 | bit CRCREQERR 0x02 /* CRC REQ Error */ | |
313 | bit DUAL_EDGE_ERROR 0x01 /* Invalid pins for Dual Edge phase */ | |
314 | mask SFCNT 0x1f | |
315 | } | |
316 | ||
317 | /* | |
318 | * SCSI Status 3 (p. 3-26) | |
319 | */ | |
320 | register SSTAT3 { | |
321 | address 0x00e | |
322 | access_mode RO | |
323 | mask SCSICNT 0xf0 | |
324 | mask OFFCNT 0x0f | |
325 | } | |
326 | ||
327 | /* | |
328 | * SCSI ID for the aic7890/91 chips | |
329 | */ | |
330 | register SCSIID_ULTRA2 { | |
331 | address 0x00f | |
332 | access_mode RW | |
333 | mask TID 0xf0 /* Target ID mask */ | |
334 | mask OID 0x0f /* Our ID mask */ | |
335 | } | |
336 | ||
337 | /* | |
338 | * SCSI Interrupt Mode 1 (p. 3-28) | |
339 | * Setting any bit will enable the corresponding function | |
340 | * in SIMODE0 to interrupt via the IRQ pin. | |
341 | */ | |
342 | register SIMODE0 { | |
343 | address 0x010 | |
344 | access_mode RW | |
345 | bit ENSELDO 0x40 | |
346 | bit ENSELDI 0x20 | |
347 | bit ENSELINGO 0x10 | |
348 | bit ENSWRAP 0x08 | |
349 | bit ENIOERR 0x08 /* LVD Tranceiver mode changes */ | |
350 | bit ENSDONE 0x04 | |
351 | bit ENSPIORDY 0x02 | |
352 | bit ENDMADONE 0x01 | |
353 | } | |
354 | ||
355 | /* | |
356 | * SCSI Interrupt Mode 1 (pp. 3-28,29) | |
357 | * Setting any bit will enable the corresponding function | |
358 | * in SIMODE1 to interrupt via the IRQ pin. | |
359 | */ | |
360 | register SIMODE1 { | |
361 | address 0x011 | |
362 | access_mode RW | |
363 | bit ENSELTIMO 0x80 | |
364 | bit ENATNTARG 0x40 | |
365 | bit ENSCSIRST 0x20 | |
366 | bit ENPHASEMIS 0x10 | |
367 | bit ENBUSFREE 0x08 | |
368 | bit ENSCSIPERR 0x04 | |
369 | bit ENPHASECHG 0x02 | |
370 | bit ENREQINIT 0x01 | |
371 | } | |
372 | ||
373 | /* | |
374 | * SCSI Data Bus (High) (p. 3-29) | |
375 | * This register reads data on the SCSI Data bus directly. | |
376 | */ | |
377 | register SCSIBUSL { | |
378 | address 0x012 | |
379 | access_mode RO | |
380 | } | |
381 | ||
382 | register SCSIBUSH { | |
383 | address 0x013 | |
384 | access_mode RO | |
385 | } | |
386 | ||
387 | /* | |
388 | * SCSI/Host Address (p. 3-30) | |
389 | * These registers hold the host address for the byte about to be | |
390 | * transferred on the SCSI bus. They are counted up in the same | |
391 | * manner as STCNT is counted down. SHADDR should always be used | |
392 | * to determine the address of the last byte transferred since HADDR | |
393 | * can be skewed by write ahead. | |
394 | */ | |
395 | register SHADDR { | |
396 | address 0x014 | |
397 | size 4 | |
398 | access_mode RO | |
399 | } | |
400 | ||
401 | /* | |
402 | * Selection Timeout Timer (p. 3-30) | |
403 | */ | |
404 | register SELTIMER { | |
405 | address 0x018 | |
406 | access_mode RW | |
407 | bit STAGE6 0x20 | |
408 | bit STAGE5 0x10 | |
409 | bit STAGE4 0x08 | |
410 | bit STAGE3 0x04 | |
411 | bit STAGE2 0x02 | |
412 | bit STAGE1 0x01 | |
413 | } | |
414 | ||
415 | /* | |
416 | * Selection/Reselection ID (p. 3-31) | |
417 | * Upper four bits are the device id. The ONEBIT is set when the re/selecting | |
418 | * device did not set its own ID. | |
419 | */ | |
420 | register SELID { | |
421 | address 0x019 | |
422 | access_mode RW | |
423 | mask SELID_MASK 0xf0 | |
424 | bit ONEBIT 0x08 | |
425 | } | |
426 | ||
427 | /* | |
428 | * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) | |
429 | * Indicates if external logic has been attached to the chip to | |
430 | * perform the tasks of accessing a serial eeprom, testing termination | |
431 | * strength, and performing cable detection. On the aic7860, most of | |
432 | * these features are handled on chip, but on the aic7855 an attached | |
433 | * aic3800 does the grunt work. | |
434 | */ | |
435 | register SPIOCAP { | |
436 | address 0x01b | |
437 | access_mode RW | |
438 | bit SOFT1 0x80 | |
439 | bit SOFT0 0x40 | |
440 | bit SOFTCMDEN 0x20 | |
441 | bit HAS_BRDCTL 0x10 /* External Board control */ | |
442 | bit SEEPROM 0x08 /* External serial eeprom logic */ | |
443 | bit EEPROM 0x04 /* Writable external BIOS ROM */ | |
444 | bit ROM 0x02 /* Logic for accessing external ROM */ | |
445 | bit SSPIOCPS 0x01 /* Termination and cable detection */ | |
446 | } | |
447 | ||
448 | /* | |
449 | * SCSI Block Control (p. 3-32) | |
450 | * Controls Bus type and channel selection. In a twin channel configuration | |
451 | * addresses 0x00-0x1e are gated to the appropriate channel based on this | |
452 | * register. SELWIDE allows for the coexistence of 8bit and 16bit devices | |
453 | * on a wide bus. | |
454 | */ | |
455 | register SBLKCTL { | |
456 | address 0x01f | |
457 | access_mode RW | |
458 | bit DIAGLEDEN 0x80 /* Aic78X0 only */ | |
459 | bit DIAGLEDON 0x40 /* Aic78X0 only */ | |
460 | bit AUTOFLUSHDIS 0x20 | |
461 | bit SELBUSB 0x08 | |
462 | bit ENAB40 0x08 /* LVD transceiver active */ | |
463 | bit ENAB20 0x04 /* SE/HVD transceiver active */ | |
464 | bit SELWIDE 0x02 | |
465 | bit XCVR 0x01 /* External transceiver active */ | |
466 | } | |
467 | ||
468 | /* | |
469 | * Sequencer Control (p. 3-33) | |
470 | * Error detection mode and speed configuration | |
471 | */ | |
472 | register SEQCTL { | |
473 | address 0x060 | |
474 | access_mode RW | |
475 | bit PERRORDIS 0x80 | |
476 | bit PAUSEDIS 0x40 | |
477 | bit FAILDIS 0x20 | |
478 | bit FASTMODE 0x10 | |
479 | bit BRKADRINTEN 0x08 | |
480 | bit STEP 0x04 | |
481 | bit SEQRESET 0x02 | |
482 | bit LOADRAM 0x01 | |
483 | } | |
484 | ||
485 | /* | |
486 | * Sequencer RAM Data (p. 3-34) | |
487 | * Single byte window into the Scratch Ram area starting at the address | |
488 | * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write | |
489 | * four bytes in succession. The SEQADDRs will increment after the most | |
490 | * significant byte is written | |
491 | */ | |
492 | register SEQRAM { | |
493 | address 0x061 | |
494 | access_mode RW | |
495 | } | |
496 | ||
497 | /* | |
498 | * Sequencer Address Registers (p. 3-35) | |
499 | * Only the first bit of SEQADDR1 holds addressing information | |
500 | */ | |
501 | register SEQADDR0 { | |
502 | address 0x062 | |
503 | access_mode RW | |
504 | } | |
505 | ||
506 | register SEQADDR1 { | |
507 | address 0x063 | |
508 | access_mode RW | |
509 | mask SEQADDR1_MASK 0x01 | |
510 | } | |
511 | ||
512 | /* | |
513 | * Accumulator | |
514 | * We cheat by passing arguments in the Accumulator up to the kernel driver | |
515 | */ | |
516 | register ACCUM { | |
517 | address 0x064 | |
518 | access_mode RW | |
519 | accumulator | |
520 | } | |
521 | ||
522 | register SINDEX { | |
523 | address 0x065 | |
524 | access_mode RW | |
525 | sindex | |
526 | } | |
527 | ||
528 | register DINDEX { | |
529 | address 0x066 | |
530 | access_mode RW | |
531 | } | |
532 | ||
533 | register ALLONES { | |
534 | address 0x069 | |
535 | access_mode RO | |
536 | allones | |
537 | } | |
538 | ||
539 | register ALLZEROS { | |
540 | address 0x06a | |
541 | access_mode RO | |
542 | allzeros | |
543 | } | |
544 | ||
545 | register NONE { | |
546 | address 0x06a | |
547 | access_mode WO | |
548 | none | |
549 | } | |
550 | ||
551 | register FLAGS { | |
552 | address 0x06b | |
553 | access_mode RO | |
554 | bit ZERO 0x02 | |
555 | bit CARRY 0x01 | |
556 | } | |
557 | ||
558 | register SINDIR { | |
559 | address 0x06c | |
560 | access_mode RO | |
561 | } | |
562 | ||
563 | register DINDIR { | |
564 | address 0x06d | |
565 | access_mode WO | |
566 | } | |
567 | ||
568 | register FUNCTION1 { | |
569 | address 0x06e | |
570 | access_mode RW | |
571 | } | |
572 | ||
573 | register STACK { | |
574 | address 0x06f | |
575 | access_mode RO | |
576 | } | |
577 | ||
578 | /* | |
579 | * Board Control (p. 3-43) | |
580 | */ | |
581 | register BCTL { | |
582 | address 0x084 | |
583 | access_mode RW | |
584 | bit ACE 0x08 | |
585 | bit ENABLE 0x01 | |
586 | } | |
587 | ||
588 | register DSCOMMAND0 { | |
589 | address 0x084 | |
590 | access_mode RW | |
591 | bit CACHETHEN 0x80 | |
592 | bit DPARCKEN 0x40 | |
593 | bit MPARCKEN 0x20 | |
594 | bit EXTREQLCK 0x10 | |
595 | bit INTSCBRAMSEL 0x08 | |
596 | bit RAMPS 0x04 | |
597 | bit USCBSIZE32 0x02 | |
598 | bit CIOPARCKEN 0x01 | |
599 | } | |
600 | ||
601 | /* | |
602 | * On the aic78X0 chips, Board Control is replaced by the DSCommand | |
603 | * register (p. 4-64) | |
604 | */ | |
605 | register DSCOMMAND { | |
606 | address 0x084 | |
607 | access_mode RW | |
608 | bit CACHETHEN 0x80 /* Cache Threshold enable */ | |
609 | bit DPARCKEN 0x40 /* Data Parity Check Enable */ | |
610 | bit MPARCKEN 0x20 /* Memory Parity Check Enable */ | |
611 | bit EXTREQLCK 0x10 /* External Request Lock */ | |
612 | } | |
613 | ||
614 | /* | |
615 | * Bus On/Off Time (p. 3-44) | |
616 | */ | |
617 | register BUSTIME { | |
618 | address 0x085 | |
619 | access_mode RW | |
620 | mask BOFF 0xf0 | |
621 | mask BON 0x0f | |
622 | } | |
623 | ||
624 | /* | |
625 | * Bus Speed (p. 3-45) | |
626 | */ | |
627 | register BUSSPD { | |
628 | address 0x086 | |
629 | access_mode RW | |
630 | mask DFTHRSH 0xc0 | |
631 | mask STBOFF 0x38 | |
632 | mask STBON 0x07 | |
633 | mask DFTHRSH_100 0xc0 | |
634 | } | |
635 | ||
636 | /* | |
637 | * Host Control (p. 3-47) R/W | |
638 | * Overall host control of the device. | |
639 | */ | |
640 | register HCNTRL { | |
641 | address 0x087 | |
642 | access_mode RW | |
643 | bit POWRDN 0x40 | |
644 | bit SWINT 0x10 | |
645 | bit IRQMS 0x08 | |
646 | bit PAUSE 0x04 | |
647 | bit INTEN 0x02 | |
648 | bit CHIPRST 0x01 | |
649 | bit CHIPRSTACK 0x01 | |
650 | } | |
651 | ||
652 | /* | |
653 | * Host Address (p. 3-48) | |
654 | * This register contains the address of the byte about | |
655 | * to be transferred across the host bus. | |
656 | */ | |
657 | register HADDR { | |
658 | address 0x088 | |
659 | size 4 | |
660 | access_mode RW | |
661 | } | |
662 | ||
663 | register HCNT { | |
664 | address 0x08c | |
665 | size 3 | |
666 | access_mode RW | |
667 | } | |
668 | ||
669 | /* | |
670 | * SCB Pointer (p. 3-49) | |
671 | * Gate one of the four SCBs into the SCBARRAY window. | |
672 | */ | |
673 | register SCBPTR { | |
674 | address 0x090 | |
675 | access_mode RW | |
676 | } | |
677 | ||
678 | /* | |
679 | * Interrupt Status (p. 3-50) | |
680 | * Status for system interrupts | |
681 | */ | |
682 | register INTSTAT { | |
683 | address 0x091 | |
684 | access_mode RW | |
685 | bit BRKADRINT 0x08 | |
686 | bit SCSIINT 0x04 | |
687 | bit CMDCMPLT 0x02 | |
688 | bit SEQINT 0x01 | |
689 | mask BAD_PHASE SEQINT /* unknown scsi bus phase */ | |
690 | mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ | |
691 | mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/ | |
692 | mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ | |
693 | mask EXTENDED_MSG 0x40|SEQINT /* Extended message received */ | |
694 | mask WIDE_RESIDUE 0x50|SEQINT /* need kernel to back up */ | |
695 | /* the SG array for us */ | |
696 | mask REJECT_MSG 0x60|SEQINT /* Reject message received */ | |
697 | mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ | |
698 | mask RESIDUAL 0x80|SEQINT /* Residual byte count != 0 */ | |
699 | mask AWAITING_MSG 0xa0|SEQINT /* | |
700 | * Kernel requested to specify | |
701 | * a message to this target | |
702 | * (command was null), so tell | |
703 | * it that it can fill the | |
704 | * message buffer. | |
705 | */ | |
706 | mask SEQ_SG_FIXUP 0xb0|SEQINT /* need help with fixing up | |
707 | * the sg array pointer after | |
708 | * a phasemis with no valid | |
709 | * sg elements in the shadow | |
710 | * pipeline. | |
711 | */ | |
712 | mask TRACEPOINT2 0xc0|SEQINT | |
713 | mask MSGIN_PHASEMIS 0xd0|SEQINT /* | |
714 | * Target changed phase on us | |
715 | * when we were expecting | |
716 | * another msgin byte. | |
717 | */ | |
718 | mask DATA_OVERRUN 0xe0|SEQINT /* | |
719 | * Target attempted to write | |
720 | * beyond the bounds of its | |
721 | * command. | |
722 | */ | |
723 | ||
724 | mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ | |
725 | mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) | |
726 | } | |
727 | ||
728 | /* | |
729 | * Hard Error (p. 3-53) | |
730 | * Reporting of catastrophic errors. You usually cannot recover from | |
731 | * these without a full board reset. | |
732 | */ | |
733 | register ERROR { | |
734 | address 0x092 | |
735 | access_mode RO | |
736 | bit CIOPARERR 0x80 /* Ultra2 only */ | |
737 | bit PCIERRSTAT 0x40 /* PCI only */ | |
738 | bit MPARERR 0x20 /* PCI only */ | |
739 | bit DPARERR 0x10 /* PCI only */ | |
740 | bit SQPARERR 0x08 | |
741 | bit ILLOPCODE 0x04 | |
742 | bit ILLSADDR 0x02 | |
743 | bit DSCTMOUT 0x02 /* Ultra3 only */ | |
744 | bit ILLHADDR 0x01 | |
745 | } | |
746 | ||
747 | /* | |
748 | * Clear Interrupt Status (p. 3-52) | |
749 | */ | |
750 | register CLRINT { | |
751 | address 0x092 | |
752 | access_mode WO | |
753 | bit CLRPARERR 0x10 /* PCI only */ | |
754 | bit CLRBRKADRINT 0x08 | |
755 | bit CLRSCSIINT 0x04 | |
756 | bit CLRCMDINT 0x02 | |
757 | bit CLRSEQINT 0x01 | |
758 | } | |
759 | ||
760 | register DFCNTRL { | |
761 | address 0x093 | |
762 | access_mode RW | |
763 | bit PRELOADEN 0x80 /* aic7890 only */ | |
764 | bit WIDEODD 0x40 | |
765 | bit SCSIEN 0x20 | |
766 | bit SDMAEN 0x10 | |
767 | bit SDMAENACK 0x10 | |
768 | bit HDMAEN 0x08 | |
769 | bit HDMAENACK 0x08 | |
770 | bit DIRECTION 0x04 | |
771 | bit FIFOFLUSH 0x02 | |
772 | bit FIFORESET 0x01 | |
773 | } | |
774 | ||
775 | register DFSTATUS { | |
776 | address 0x094 | |
777 | access_mode RO | |
778 | bit PRELOAD_AVAIL 0x80 | |
779 | bit DWORDEMP 0x20 | |
780 | bit MREQPEND 0x10 | |
781 | bit HDONE 0x08 | |
782 | bit DFTHRESH 0x04 | |
783 | bit FIFOFULL 0x02 | |
784 | bit FIFOEMP 0x01 | |
785 | } | |
786 | ||
787 | register DFDAT { | |
788 | address 0x099 | |
789 | access_mode RW | |
790 | } | |
791 | ||
792 | /* | |
793 | * SCB Auto Increment (p. 3-59) | |
794 | * Byte offset into the SCB Array and an optional bit to allow auto | |
795 | * incrementing of the address during download and upload operations | |
796 | */ | |
797 | register SCBCNT { | |
798 | address 0x09a | |
799 | access_mode RW | |
800 | bit SCBAUTO 0x80 | |
801 | mask SCBCNT_MASK 0x1f | |
802 | } | |
803 | ||
804 | /* | |
805 | * Queue In FIFO (p. 3-60) | |
806 | * Input queue for queued SCBs (commands that the seqencer has yet to start) | |
807 | */ | |
808 | register QINFIFO { | |
809 | address 0x09b | |
810 | access_mode RW | |
811 | } | |
812 | ||
813 | /* | |
814 | * Queue In Count (p. 3-60) | |
815 | * Number of queued SCBs | |
816 | */ | |
817 | register QINCNT { | |
818 | address 0x09c | |
819 | access_mode RO | |
820 | } | |
821 | ||
822 | /* | |
823 | * SCSIDATL IMAGE Register (p. 5-104) | |
824 | * Write to this register also go to SCSIDATL but this register will preserve | |
825 | * the data for later reading as long as the SCSIDATL_IMGEN bit in the | |
826 | * OPTIONMODE register is set. | |
827 | */ | |
828 | register SCSIDATL_IMG { | |
829 | address 0x09c | |
830 | access_mode RW | |
831 | } | |
832 | ||
833 | /* | |
834 | * Queue Out FIFO (p. 3-61) | |
835 | * Queue of SCBs that have completed and await the host | |
836 | */ | |
837 | register QOUTFIFO { | |
838 | address 0x09d | |
839 | access_mode WO | |
840 | } | |
841 | ||
842 | /* | |
843 | * CRC Control 1 Register (p. 5-105) | |
844 | * Control bits for the Ultra 160/m CRC facilities | |
845 | */ | |
846 | register CRCCONTROL1 { | |
847 | address 0x09d | |
848 | access_mode RW | |
849 | bit CRCONSEEN 0x80 /* CRC ON Single Edge ENable */ | |
850 | bit CRCVALCHKEN 0x40 /* CRC Value Check Enable */ | |
851 | bit CRCENDCHKEN 0x20 /* CRC End Check Enable */ | |
852 | bit CRCREQCHKEN 0x10 | |
853 | bit TARGCRCENDEN 0x08 /* Enable End CRC transfer when target */ | |
854 | bit TARGCRCCNTEN 0x04 /* Enable CRC transfer when target */ | |
855 | } | |
856 | ||
857 | /* | |
858 | * Queue Out Count (p. 3-61) | |
859 | * Number of queued SCBs in the Out FIFO | |
860 | */ | |
861 | register QOUTCNT { | |
862 | address 0x09e | |
863 | access_mode RO | |
864 | } | |
865 | ||
866 | /* | |
867 | * SCSI Phase Register (p. 5-106) | |
868 | * Current bus phase | |
869 | */ | |
870 | register SCSIPHASE { | |
871 | address 0x09e | |
872 | access_mode RO | |
873 | bit SP_STATUS 0x20 | |
874 | bit SP_COMMAND 0x10 | |
875 | bit SP_MSG_IN 0x08 | |
876 | bit SP_MSG_OUT 0x04 | |
877 | bit SP_DATA_IN 0x02 | |
878 | bit SP_DATA_OUT 0x01 | |
879 | } | |
880 | ||
881 | /* | |
882 | * Special Function | |
883 | */ | |
884 | register SFUNCT { | |
885 | address 0x09f | |
886 | access_mode RW | |
887 | bit ALT_MODE 0x80 | |
888 | } | |
889 | ||
890 | /* | |
891 | * SCB Definition (p. 5-4) | |
892 | */ | |
893 | scb { | |
894 | address 0x0a0 | |
895 | SCB_CONTROL { | |
896 | size 1 | |
897 | bit MK_MESSAGE 0x80 | |
898 | bit DISCENB 0x40 | |
899 | bit TAG_ENB 0x20 | |
900 | bit DISCONNECTED 0x04 | |
901 | mask SCB_TAG_TYPE 0x03 | |
902 | } | |
903 | SCB_TCL { | |
904 | size 1 | |
905 | bit SELBUSB 0x08 | |
906 | mask TID 0xf0 | |
907 | mask LID 0x07 | |
908 | } | |
909 | SCB_TARGET_STATUS { | |
910 | size 1 | |
911 | } | |
912 | SCB_SGCOUNT { | |
913 | size 1 | |
914 | } | |
915 | SCB_SGPTR { | |
916 | size 4 | |
917 | } | |
918 | SCB_RESID_SGCNT { | |
919 | size 1 | |
920 | } | |
921 | SCB_RESID_DCNT { | |
922 | size 3 | |
923 | } | |
924 | SCB_DATAPTR { | |
925 | size 4 | |
926 | } | |
927 | SCB_DATACNT { | |
928 | /* | |
929 | * Really only 3 bytes, but padded to make | |
930 | * the kernel's job easier. | |
931 | */ | |
932 | size 4 | |
933 | } | |
934 | SCB_CMDPTR { | |
935 | size 4 | |
936 | } | |
937 | SCB_CMDLEN { | |
938 | size 1 | |
939 | } | |
940 | SCB_TAG { | |
941 | size 1 | |
942 | } | |
943 | SCB_NEXT { | |
944 | size 1 | |
945 | } | |
946 | SCB_PREV { | |
947 | size 1 | |
948 | } | |
949 | SCB_BUSYTARGETS { | |
950 | size 4 | |
951 | } | |
952 | } | |
953 | ||
954 | const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ | |
955 | ||
956 | /* --------------------- AHA-2840-only definitions -------------------- */ | |
957 | ||
958 | register SEECTL_2840 { | |
959 | address 0x0c0 | |
960 | access_mode RW | |
961 | bit CS_2840 0x04 | |
962 | bit CK_2840 0x02 | |
963 | bit DO_2840 0x01 | |
964 | } | |
965 | ||
966 | register STATUS_2840 { | |
967 | address 0x0c1 | |
968 | access_mode RW | |
969 | bit EEPROM_TF 0x80 | |
970 | mask BIOS_SEL 0x60 | |
971 | mask ADSEL 0x1e | |
972 | bit DI_2840 0x01 | |
973 | } | |
974 | ||
975 | /* --------------------- AIC-7870-only definitions -------------------- */ | |
976 | ||
977 | register DSPCISTATUS { | |
978 | address 0x086 | |
979 | mask DFTHRSH_100 0xc0 | |
980 | } | |
981 | ||
982 | register CCHADDR { | |
983 | address 0x0E0 | |
984 | size 8 | |
985 | } | |
986 | ||
987 | register CCHCNT { | |
988 | address 0x0E8 | |
989 | } | |
990 | ||
991 | register CCSGRAM { | |
992 | address 0x0E9 | |
993 | } | |
994 | ||
995 | register CCSGADDR { | |
996 | address 0x0EA | |
997 | } | |
998 | ||
999 | register CCSGCTL { | |
1000 | address 0x0EB | |
1001 | bit CCSGDONE 0x80 | |
1002 | bit CCSGEN 0x08 | |
1003 | bit FLAG 0x02 | |
1004 | bit CCSGRESET 0x01 | |
1005 | } | |
1006 | ||
1007 | register CCSCBCNT { | |
1008 | address 0xEF | |
1009 | } | |
1010 | ||
1011 | register CCSCBCTL { | |
1012 | address 0x0EE | |
1013 | bit CCSCBDONE 0x80 | |
1014 | bit ARRDONE 0x40 /* SCB Array prefetch done */ | |
1015 | bit CCARREN 0x10 | |
1016 | bit CCSCBEN 0x08 | |
1017 | bit CCSCBDIR 0x04 | |
1018 | bit CCSCBRESET 0x01 | |
1019 | } | |
1020 | ||
1021 | register CCSCBADDR { | |
1022 | address 0x0ED | |
1023 | } | |
1024 | ||
1025 | register CCSCBRAM { | |
1026 | address 0xEC | |
1027 | } | |
1028 | ||
1029 | register CCSCBPTR { | |
1030 | address 0x0F1 | |
1031 | } | |
1032 | ||
1033 | register HNSCB_QOFF { | |
1034 | address 0x0F4 | |
1035 | } | |
1036 | ||
1037 | register HESCB_QOFF { | |
1038 | address 0x0F5 | |
1039 | } | |
1040 | ||
1041 | register SNSCB_QOFF { | |
1042 | address 0x0F6 | |
1043 | } | |
1044 | ||
1045 | register SESCB_QOFF { | |
1046 | address 0x0F7 | |
1047 | } | |
1048 | ||
1049 | register SDSCB_QOFF { | |
1050 | address 0x0F8 | |
1051 | } | |
1052 | ||
1053 | register QOFF_CTLSTA { | |
1054 | address 0x0FA | |
1055 | bit ESTABLISH_SCB_AVAIL 0x80 | |
1056 | bit SCB_AVAIL 0x40 | |
1057 | bit SNSCB_ROLLOVER 0x20 | |
1058 | bit SDSCB_ROLLOVER 0x10 | |
1059 | bit SESCB_ROLLOVER 0x08 | |
1060 | mask SCB_QSIZE 0x07 | |
1061 | mask SCB_QSIZE_256 0x06 | |
1062 | } | |
1063 | ||
1064 | register DFF_THRSH { | |
1065 | address 0x0FB | |
1066 | mask WR_DFTHRSH 0x70 | |
1067 | mask RD_DFTHRSH 0x07 | |
1068 | mask RD_DFTHRSH_MIN 0x00 | |
1069 | mask RD_DFTHRSH_25 0x01 | |
1070 | mask RD_DFTHRSH_50 0x02 | |
1071 | mask RD_DFTHRSH_63 0x03 | |
1072 | mask RD_DFTHRSH_75 0x04 | |
1073 | mask RD_DFTHRSH_85 0x05 | |
1074 | mask RD_DFTHRSH_90 0x06 | |
1075 | mask RD_DFTHRSH_MAX 0x07 | |
1076 | mask WR_DFTHRSH_MIN 0x00 | |
1077 | mask WR_DFTHRSH_25 0x10 | |
1078 | mask WR_DFTHRSH_50 0x20 | |
1079 | mask WR_DFTHRSH_63 0x30 | |
1080 | mask WR_DFTHRSH_75 0x40 | |
1081 | mask WR_DFTHRSH_85 0x50 | |
1082 | mask WR_DFTHRSH_90 0x60 | |
1083 | mask WR_DFTHRSH_MAX 0x70 | |
1084 | } | |
1085 | ||
1086 | register SG_CACHEPTR { | |
1087 | access_mode RW | |
1088 | address 0x0fc | |
1089 | mask SG_USER_DATA 0xfc | |
1090 | bit LAST_SEG 0x02 | |
1091 | bit LAST_SEG_DONE 0x01 | |
1092 | } | |
1093 | ||
1094 | register BRDCTL { | |
1095 | address 0x01d | |
1096 | bit BRDDAT7 0x80 | |
1097 | bit BRDDAT6 0x40 | |
1098 | bit BRDDAT5 0x20 | |
1099 | bit BRDSTB 0x10 | |
1100 | bit BRDCS 0x08 | |
1101 | bit BRDRW 0x04 | |
1102 | bit BRDCTL1 0x02 | |
1103 | bit BRDCTL0 0x01 | |
1104 | /* 7890 Definitions */ | |
1105 | bit BRDDAT4 0x10 | |
1106 | bit BRDDAT3 0x08 | |
1107 | bit BRDDAT2 0x04 | |
1108 | bit BRDRW_ULTRA2 0x02 | |
1109 | bit BRDSTB_ULTRA2 0x01 | |
1110 | } | |
1111 | ||
1112 | /* | |
1113 | * Serial EEPROM Control (p. 4-92 in 7870 Databook) | |
1114 | * Controls the reading and writing of an external serial 1-bit | |
1115 | * EEPROM Device. In order to access the serial EEPROM, you must | |
1116 | * first set the SEEMS bit that generates a request to the memory | |
1117 | * port for access to the serial EEPROM device. When the memory | |
1118 | * port is not busy servicing another request, it reconfigures | |
1119 | * to allow access to the serial EEPROM. When this happens, SEERDY | |
1120 | * gets set high to verify that the memory port access has been | |
1121 | * granted. | |
1122 | * | |
1123 | * After successful arbitration for the memory port, the SEECS bit of | |
1124 | * the SEECTL register is connected to the chip select. The SEECK, | |
1125 | * SEEDO, and SEEDI are connected to the clock, data out, and data in | |
1126 | * lines respectively. The SEERDY bit of SEECTL is useful in that it | |
1127 | * gives us an 800 nsec timer. After a write to the SEECTL register, | |
1128 | * the SEERDY goes high 800 nsec later. The one exception to this is | |
1129 | * when we first request access to the memory port. The SEERDY goes | |
1130 | * high to signify that access has been granted and, for this case, has | |
1131 | * no implied timing. | |
1132 | * | |
1133 | * See 93cx6.c for detailed information on the protocol necessary to | |
1134 | * read the serial EEPROM. | |
1135 | */ | |
1136 | register SEECTL { | |
1137 | address 0x01e | |
1138 | bit EXTARBACK 0x80 | |
1139 | bit EXTARBREQ 0x40 | |
1140 | bit SEEMS 0x20 | |
1141 | bit SEERDY 0x10 | |
1142 | bit SEECS 0x08 | |
1143 | bit SEECK 0x04 | |
1144 | bit SEEDO 0x02 | |
1145 | bit SEEDI 0x01 | |
1146 | } | |
1147 | /* ---------------------- Scratch RAM Offsets ------------------------- */ | |
1148 | /* These offsets are either to values that are initialized by the board's | |
1149 | * BIOS or are specified by the sequencer code. | |
1150 | * | |
1151 | * The host adapter card (at least the BIOS) uses 20-2f for SCSI | |
1152 | * device information, 32-33 and 5a-5f as well. As it turns out, the | |
1153 | * BIOS trashes 20-2f, writing the synchronous negotiation results | |
1154 | * on top of the BIOS values, so we re-use those for our per-target | |
1155 | * scratchspace (actually a value that can be copied directly into | |
1156 | * SCSIRATE). The kernel driver will enable synchronous negotiation | |
1157 | * for all targets that have a value other than 0 in the lower four | |
1158 | * bits of the target scratch space. This should work regardless of | |
1159 | * whether the bios has been installed. | |
1160 | */ | |
1161 | ||
1162 | scratch_ram { | |
1163 | address 0x020 | |
1164 | ||
1165 | /* | |
1166 | * 1 byte per target starting at this address for configuration values | |
1167 | */ | |
1168 | TARG_SCSIRATE { | |
1169 | size 16 | |
1170 | } | |
1171 | /* | |
1172 | * Bit vector of targets that have ULTRA enabled. | |
1173 | */ | |
1174 | ULTRA_ENB { | |
1175 | size 2 | |
1176 | } | |
1177 | /* | |
1178 | * Bit vector of targets that have disconnection disabled. | |
1179 | */ | |
1180 | DISC_DSB { | |
1181 | size 2 | |
1182 | } | |
1183 | /* | |
1184 | * Single byte buffer used to designate the type or message | |
1185 | * to send to a target. | |
1186 | */ | |
1187 | MSG_OUT { | |
1188 | size 1 | |
1189 | } | |
1190 | /* Parameters for DMA Logic */ | |
1191 | DMAPARAMS { | |
1192 | size 1 | |
1193 | bit PRELOADEN 0x80 | |
1194 | bit WIDEODD 0x40 | |
1195 | bit SCSIEN 0x20 | |
1196 | bit SDMAEN 0x10 | |
1197 | bit SDMAENACK 0x10 | |
1198 | bit HDMAEN 0x08 | |
1199 | bit HDMAENACK 0x08 | |
1200 | bit DIRECTION 0x04 | |
1201 | bit FIFOFLUSH 0x02 | |
1202 | bit FIFORESET 0x01 | |
1203 | } | |
1204 | SEQ_FLAGS { | |
1205 | size 1 | |
1206 | bit IDENTIFY_SEEN 0x80 | |
1207 | bit SCBPTR_VALID 0x20 | |
1208 | bit DPHASE 0x10 | |
1209 | bit AMTARGET 0x08 | |
1210 | bit WIDE_BUS 0x02 | |
1211 | bit TWIN_BUS 0x01 | |
1212 | } | |
1213 | /* | |
1214 | * Temporary storage for the | |
1215 | * target/channel/lun of a | |
1216 | * reconnecting target | |
1217 | */ | |
1218 | SAVED_TCL { | |
1219 | size 1 | |
1220 | } | |
1221 | /* Working value of the number of SG segments left */ | |
1222 | SG_COUNT { | |
1223 | size 1 | |
1224 | } | |
1225 | /* Working value of SG pointer */ | |
1226 | SG_NEXT { | |
1227 | size 4 | |
1228 | } | |
1229 | /* | |
1230 | * The last bus phase as seen by the sequencer. | |
1231 | */ | |
1232 | LASTPHASE { | |
1233 | size 1 | |
1234 | bit CDI 0x80 | |
1235 | bit IOI 0x40 | |
1236 | bit MSGI 0x20 | |
1237 | mask PHASE_MASK CDI|IOI|MSGI | |
1238 | mask P_DATAOUT 0x00 | |
1239 | mask P_DATAIN IOI | |
1240 | mask P_COMMAND CDI | |
1241 | mask P_MESGOUT CDI|MSGI | |
1242 | mask P_STATUS CDI|IOI | |
1243 | mask P_MESGIN CDI|IOI|MSGI | |
1244 | mask P_BUSFREE 0x01 | |
1245 | } | |
1246 | /* | |
1247 | * head of list of SCBs awaiting | |
1248 | * selection | |
1249 | */ | |
1250 | WAITING_SCBH { | |
1251 | size 1 | |
1252 | } | |
1253 | /* | |
1254 | * head of list of SCBs that are | |
1255 | * disconnected. Used for SCB | |
1256 | * paging. | |
1257 | */ | |
1258 | DISCONNECTED_SCBH { | |
1259 | size 1 | |
1260 | } | |
1261 | /* | |
1262 | * head of list of SCBs that are | |
1263 | * not in use. Used for SCB paging. | |
1264 | */ | |
1265 | FREE_SCBH { | |
1266 | size 1 | |
1267 | } | |
1268 | /* | |
1269 | * Address of the hardware scb array in the host. | |
1270 | */ | |
1271 | HSCB_ADDR { | |
1272 | size 4 | |
1273 | } | |
1274 | /* | |
1275 | * Address of the 256 byte array storing the SCBID of outstanding | |
1276 | * untagged SCBs indexed by TCL. | |
1277 | */ | |
1278 | SCBID_ADDR { | |
1279 | size 4 | |
1280 | } | |
1281 | /* | |
1282 | * Address of the array of command descriptors used to store | |
1283 | * information about incoming selections. | |
1284 | */ | |
1285 | TMODE_CMDADDR { | |
1286 | size 4 | |
1287 | } | |
1288 | KERNEL_QINPOS { | |
1289 | size 1 | |
1290 | } | |
1291 | QINPOS { | |
1292 | size 1 | |
1293 | } | |
1294 | QOUTPOS { | |
1295 | size 1 | |
1296 | } | |
1297 | /* | |
1298 | * Offset into the command descriptor array for the next | |
1299 | * available desciptor to use. | |
1300 | */ | |
1301 | TMODE_CMDADDR_NEXT { | |
1302 | size 1 | |
1303 | } | |
1304 | ARG_1 { | |
1305 | size 1 | |
1306 | mask SEND_MSG 0x80 | |
1307 | mask SEND_SENSE 0x40 | |
1308 | mask SEND_REJ 0x20 | |
1309 | mask MSGOUT_PHASEMIS 0x10 | |
1310 | alias RETURN_1 | |
1311 | } | |
1312 | ARG_2 { | |
1313 | size 1 | |
1314 | alias RETURN_2 | |
1315 | } | |
1316 | ||
1317 | /* | |
1318 | * Snapshot of MSG_OUT taken after each message is sent. | |
1319 | */ | |
1320 | LAST_MSG { | |
1321 | size 1 | |
1322 | } | |
1323 | ||
1324 | /* | |
1325 | * Number of times we have filled the CCSGRAM with prefetched | |
1326 | * SG elements. | |
1327 | */ | |
1328 | PREFETCH_CNT { | |
1329 | size 1 | |
1330 | } | |
1331 | ||
1332 | ||
1333 | /* | |
1334 | * These are reserved registers in the card's scratch ram. Some of | |
1335 | * the values are specified in the AHA2742 technical reference manual | |
1336 | * and are initialized by the BIOS at boot time. | |
1337 | */ | |
1338 | SCSICONF { | |
1339 | address 0x05a | |
1340 | size 1 | |
1341 | bit TERM_ENB 0x80 | |
1342 | bit RESET_SCSI 0x40 | |
1343 | mask HSCSIID 0x07 /* our SCSI ID */ | |
1344 | mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ | |
1345 | } | |
1346 | HOSTCONF { | |
1347 | address 0x05d | |
1348 | size 1 | |
1349 | } | |
1350 | HA_274_BIOSCTRL { | |
1351 | address 0x05f | |
1352 | size 1 | |
1353 | mask BIOSMODE 0x30 | |
1354 | mask BIOSDISABLED 0x30 | |
1355 | bit CHANNEL_B_PRIMARY 0x08 | |
1356 | } | |
1357 | /* | |
1358 | * Per target SCSI offset values for Ultra2 controllers. | |
1359 | */ | |
1360 | TARG_OFFSET { | |
1361 | address 0x070 | |
1362 | size 16 | |
1363 | } | |
1364 | } | |
1365 | ||
1366 | const SCB_LIST_NULL 0xff | |
1367 | ||
1368 | const CCSGADDR_MAX 0x80 | |
1369 | const CCSGRAM_MAXSEGS 16 | |
1370 | ||
1371 | /* Offsets into the SCBID array where different data is stored */ | |
1372 | const UNTAGGEDSCB_OFFSET 0 | |
1373 | const QOUTFIFO_OFFSET 1 | |
1374 | const QINFIFO_OFFSET 2 | |
1375 | ||
1376 | /* WDTR Message values */ | |
1377 | const BUS_8_BIT 0x00 | |
1378 | const BUS_16_BIT 0x01 | |
1379 | const BUS_32_BIT 0x02 | |
1380 | ||
1381 | /* Offset maximums */ | |
1382 | const MAX_OFFSET_8BIT 0x0f | |
1383 | const MAX_OFFSET_16BIT 0x08 | |
1384 | const MAX_OFFSET_ULTRA2 0x7f | |
1385 | const HOST_MSG 0xff | |
1386 | ||
1387 | /* Target mode command processing constants */ | |
1388 | const CMD_GROUP_CODE_SHIFT 0x05 | |
1389 | const CMD_GROUP0_BYTE_DELTA -4 | |
1390 | const CMD_GROUP2_BYTE_DELTA -6 | |
1391 | const CMD_GROUP4_BYTE_DELTA 4 | |
1392 | const CMD_GROUP5_BYTE_DELTA 11 | |
1393 | ||
1394 | /* | |
1395 | * Downloaded (kernel inserted) constants | |
1396 | */ | |
1397 | ||
1398 | /* | |
1399 | * Number of command descriptors in the command descriptor array. | |
1400 | */ | |
1401 | const TMODE_NUMCMDS download |