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Commit | Line | Data |
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3a7e7be2 HR |
1 | /* |
2 | * AMD am53c974 driver. | |
3 | * Copyright (c) 2014 Hannes Reinecke, SUSE Linux GmbH | |
4 | */ | |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/delay.h> | |
10 | #include <linux/pci.h> | |
11 | #include <linux/interrupt.h> | |
12 | ||
13 | #include <scsi/scsi_host.h> | |
14 | ||
15 | #include "esp_scsi.h" | |
16 | ||
17 | #define DRV_MODULE_NAME "am53c974" | |
18 | #define DRV_MODULE_VERSION "1.00" | |
19 | ||
20 | static bool am53c974_debug; | |
e858d930 | 21 | static bool am53c974_fenab = true; |
3a7e7be2 HR |
22 | |
23 | #define esp_dma_log(f, a...) \ | |
24 | do { \ | |
25 | if (am53c974_debug) \ | |
26 | shost_printk(KERN_DEBUG, esp->host, f, ##a); \ | |
27 | } while (0) | |
28 | ||
29 | #define ESP_DMA_CMD 0x10 | |
30 | #define ESP_DMA_STC 0x11 | |
31 | #define ESP_DMA_SPA 0x12 | |
32 | #define ESP_DMA_WBC 0x13 | |
33 | #define ESP_DMA_WAC 0x14 | |
34 | #define ESP_DMA_STATUS 0x15 | |
35 | #define ESP_DMA_SMDLA 0x16 | |
36 | #define ESP_DMA_WMAC 0x17 | |
37 | ||
38 | #define ESP_DMA_CMD_IDLE 0x00 | |
39 | #define ESP_DMA_CMD_BLAST 0x01 | |
40 | #define ESP_DMA_CMD_ABORT 0x02 | |
41 | #define ESP_DMA_CMD_START 0x03 | |
42 | #define ESP_DMA_CMD_MASK 0x03 | |
43 | #define ESP_DMA_CMD_DIAG 0x04 | |
44 | #define ESP_DMA_CMD_MDL 0x10 | |
45 | #define ESP_DMA_CMD_INTE_P 0x20 | |
46 | #define ESP_DMA_CMD_INTE_D 0x40 | |
47 | #define ESP_DMA_CMD_DIR 0x80 | |
48 | ||
49 | #define ESP_DMA_STAT_PWDN 0x01 | |
50 | #define ESP_DMA_STAT_ERROR 0x02 | |
51 | #define ESP_DMA_STAT_ABORT 0x04 | |
52 | #define ESP_DMA_STAT_DONE 0x08 | |
53 | #define ESP_DMA_STAT_SCSIINT 0x10 | |
54 | #define ESP_DMA_STAT_BCMPLT 0x20 | |
55 | ||
56 | /* EEPROM is accessed with 16-bit values */ | |
57 | #define DC390_EEPROM_READ 0x80 | |
58 | #define DC390_EEPROM_LEN 0x40 | |
59 | ||
60 | /* | |
61 | * DC390 EEPROM | |
62 | * | |
63 | * 8 * 4 bytes of per-device options | |
64 | * followed by HBA specific options | |
65 | */ | |
66 | ||
67 | /* Per-device options */ | |
68 | #define DC390_EE_MODE1 0x00 | |
69 | #define DC390_EE_SPEED 0x01 | |
70 | ||
71 | /* HBA-specific options */ | |
72 | #define DC390_EE_ADAPT_SCSI_ID 0x40 | |
73 | #define DC390_EE_MODE2 0x41 | |
74 | #define DC390_EE_DELAY 0x42 | |
75 | #define DC390_EE_TAG_CMD_NUM 0x43 | |
76 | ||
77 | #define DC390_EE_MODE1_PARITY_CHK 0x01 | |
78 | #define DC390_EE_MODE1_SYNC_NEGO 0x02 | |
79 | #define DC390_EE_MODE1_EN_DISC 0x04 | |
80 | #define DC390_EE_MODE1_SEND_START 0x08 | |
81 | #define DC390_EE_MODE1_TCQ 0x10 | |
82 | ||
83 | #define DC390_EE_MODE2_MORE_2DRV 0x01 | |
84 | #define DC390_EE_MODE2_GREATER_1G 0x02 | |
85 | #define DC390_EE_MODE2_RST_SCSI_BUS 0x04 | |
86 | #define DC390_EE_MODE2_ACTIVE_NEGATION 0x08 | |
87 | #define DC390_EE_MODE2_NO_SEEK 0x10 | |
88 | #define DC390_EE_MODE2_LUN_CHECK 0x20 | |
89 | ||
90 | struct pci_esp_priv { | |
91 | struct esp *esp; | |
92 | u8 dma_status; | |
93 | }; | |
94 | ||
95 | static void pci_esp_dma_drain(struct esp *esp); | |
96 | ||
97 | static inline struct pci_esp_priv *pci_esp_get_priv(struct esp *esp) | |
98 | { | |
99 | struct pci_dev *pdev = esp->dev; | |
100 | ||
101 | return pci_get_drvdata(pdev); | |
102 | } | |
103 | ||
104 | static void pci_esp_write8(struct esp *esp, u8 val, unsigned long reg) | |
105 | { | |
106 | iowrite8(val, esp->regs + (reg * 4UL)); | |
107 | } | |
108 | ||
109 | static u8 pci_esp_read8(struct esp *esp, unsigned long reg) | |
110 | { | |
111 | return ioread8(esp->regs + (reg * 4UL)); | |
112 | } | |
113 | ||
114 | static void pci_esp_write32(struct esp *esp, u32 val, unsigned long reg) | |
115 | { | |
116 | return iowrite32(val, esp->regs + (reg * 4UL)); | |
117 | } | |
118 | ||
119 | static dma_addr_t pci_esp_map_single(struct esp *esp, void *buf, | |
120 | size_t sz, int dir) | |
121 | { | |
122 | return pci_map_single(esp->dev, buf, sz, dir); | |
123 | } | |
124 | ||
125 | static int pci_esp_map_sg(struct esp *esp, struct scatterlist *sg, | |
126 | int num_sg, int dir) | |
127 | { | |
128 | return pci_map_sg(esp->dev, sg, num_sg, dir); | |
129 | } | |
130 | ||
131 | static void pci_esp_unmap_single(struct esp *esp, dma_addr_t addr, | |
132 | size_t sz, int dir) | |
133 | { | |
134 | pci_unmap_single(esp->dev, addr, sz, dir); | |
135 | } | |
136 | ||
137 | static void pci_esp_unmap_sg(struct esp *esp, struct scatterlist *sg, | |
138 | int num_sg, int dir) | |
139 | { | |
140 | pci_unmap_sg(esp->dev, sg, num_sg, dir); | |
141 | } | |
142 | ||
143 | static int pci_esp_irq_pending(struct esp *esp) | |
144 | { | |
145 | struct pci_esp_priv *pep = pci_esp_get_priv(esp); | |
146 | ||
147 | pep->dma_status = pci_esp_read8(esp, ESP_DMA_STATUS); | |
148 | esp_dma_log("dma intr dreg[%02x]\n", pep->dma_status); | |
149 | ||
150 | if (pep->dma_status & (ESP_DMA_STAT_ERROR | | |
151 | ESP_DMA_STAT_ABORT | | |
152 | ESP_DMA_STAT_DONE | | |
153 | ESP_DMA_STAT_SCSIINT)) | |
154 | return 1; | |
155 | ||
156 | return 0; | |
157 | } | |
158 | ||
159 | static void pci_esp_reset_dma(struct esp *esp) | |
160 | { | |
161 | /* Nothing to do ? */ | |
162 | } | |
163 | ||
164 | static void pci_esp_dma_drain(struct esp *esp) | |
165 | { | |
166 | u8 resid; | |
167 | int lim = 1000; | |
168 | ||
169 | ||
170 | if ((esp->sreg & ESP_STAT_PMASK) == ESP_DOP || | |
171 | (esp->sreg & ESP_STAT_PMASK) == ESP_DIP) | |
172 | /* Data-In or Data-Out, nothing to be done */ | |
173 | return; | |
174 | ||
175 | while (--lim > 0) { | |
176 | resid = pci_esp_read8(esp, ESP_FFLAGS) & ESP_FF_FBYTES; | |
177 | if (resid <= 1) | |
178 | break; | |
179 | cpu_relax(); | |
180 | } | |
181 | if (resid > 1) { | |
182 | /* FIFO not cleared */ | |
183 | shost_printk(KERN_INFO, esp->host, | |
184 | "FIFO not cleared, %d bytes left\n", | |
185 | resid); | |
186 | } | |
187 | ||
188 | /* | |
189 | * When there is a residual BCMPLT will never be set | |
190 | * (obviously). But we still have to issue the BLAST | |
191 | * command, otherwise the data will not being transferred. | |
192 | * But we'll never know when the BLAST operation is | |
193 | * finished. So check for some time and give up eventually. | |
194 | */ | |
195 | lim = 1000; | |
196 | pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_BLAST, ESP_DMA_CMD); | |
197 | while (pci_esp_read8(esp, ESP_DMA_STATUS) & ESP_DMA_STAT_BCMPLT) { | |
198 | if (--lim == 0) | |
199 | break; | |
200 | cpu_relax(); | |
201 | } | |
202 | pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_IDLE, ESP_DMA_CMD); | |
203 | esp_dma_log("DMA blast done (%d tries, %d bytes left)\n", lim, resid); | |
6df388f2 HR |
204 | /* BLAST residual handling is currently untested */ |
205 | if (WARN_ON_ONCE(resid == 1)) { | |
206 | struct esp_cmd_entry *ent = esp->active_cmd; | |
207 | ||
208 | ent->flags |= ESP_CMD_FLAG_RESIDUAL; | |
209 | } | |
3a7e7be2 HR |
210 | } |
211 | ||
212 | static void pci_esp_dma_invalidate(struct esp *esp) | |
213 | { | |
214 | struct pci_esp_priv *pep = pci_esp_get_priv(esp); | |
215 | ||
216 | esp_dma_log("invalidate DMA\n"); | |
217 | ||
218 | pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD); | |
219 | pep->dma_status = 0; | |
220 | } | |
221 | ||
222 | static int pci_esp_dma_error(struct esp *esp) | |
223 | { | |
224 | struct pci_esp_priv *pep = pci_esp_get_priv(esp); | |
225 | ||
226 | if (pep->dma_status & ESP_DMA_STAT_ERROR) { | |
227 | u8 dma_cmd = pci_esp_read8(esp, ESP_DMA_CMD); | |
228 | ||
229 | if ((dma_cmd & ESP_DMA_CMD_MASK) == ESP_DMA_CMD_START) | |
230 | pci_esp_write8(esp, ESP_DMA_CMD_ABORT, ESP_DMA_CMD); | |
231 | ||
232 | return 1; | |
233 | } | |
234 | if (pep->dma_status & ESP_DMA_STAT_ABORT) { | |
235 | pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD); | |
236 | pep->dma_status = pci_esp_read8(esp, ESP_DMA_CMD); | |
237 | return 1; | |
238 | } | |
239 | return 0; | |
240 | } | |
241 | ||
242 | static void pci_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count, | |
243 | u32 dma_count, int write, u8 cmd) | |
244 | { | |
245 | struct pci_esp_priv *pep = pci_esp_get_priv(esp); | |
246 | u32 val = 0; | |
247 | ||
248 | BUG_ON(!(cmd & ESP_CMD_DMA)); | |
249 | ||
250 | pep->dma_status = 0; | |
251 | ||
252 | /* Set DMA engine to IDLE */ | |
253 | if (write) | |
254 | /* DMA write direction logic is inverted */ | |
255 | val |= ESP_DMA_CMD_DIR; | |
256 | pci_esp_write8(esp, ESP_DMA_CMD_IDLE | val, ESP_DMA_CMD); | |
257 | ||
258 | pci_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW); | |
259 | pci_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED); | |
e858d930 HR |
260 | if (esp->config2 & ESP_CONFIG2_FENAB) |
261 | pci_esp_write8(esp, (esp_count >> 16) & 0xff, ESP_TCHI); | |
3a7e7be2 HR |
262 | |
263 | pci_esp_write32(esp, esp_count, ESP_DMA_STC); | |
264 | pci_esp_write32(esp, addr, ESP_DMA_SPA); | |
265 | ||
266 | esp_dma_log("start dma addr[%x] count[%d:%d]\n", | |
267 | addr, esp_count, dma_count); | |
268 | ||
269 | scsi_esp_cmd(esp, cmd); | |
270 | /* Send DMA Start command */ | |
271 | pci_esp_write8(esp, ESP_DMA_CMD_START | val, ESP_DMA_CMD); | |
272 | } | |
273 | ||
e858d930 HR |
274 | static u32 pci_esp_dma_length_limit(struct esp *esp, u32 dma_addr, u32 dma_len) |
275 | { | |
276 | int dma_limit = 16; | |
277 | u32 base, end; | |
278 | ||
279 | /* | |
280 | * If CONFIG2_FENAB is set we can | |
281 | * handle up to 24 bit addresses | |
282 | */ | |
283 | if (esp->config2 & ESP_CONFIG2_FENAB) | |
284 | dma_limit = 24; | |
285 | ||
286 | if (dma_len > (1U << dma_limit)) | |
287 | dma_len = (1U << dma_limit); | |
288 | ||
289 | /* | |
290 | * Prevent crossing a 24-bit address boundary. | |
291 | */ | |
292 | base = dma_addr & ((1U << 24) - 1U); | |
293 | end = base + dma_len; | |
294 | if (end > (1U << 24)) | |
295 | end = (1U <<24); | |
296 | dma_len = end - base; | |
297 | ||
298 | return dma_len; | |
299 | } | |
300 | ||
3a7e7be2 HR |
301 | static const struct esp_driver_ops pci_esp_ops = { |
302 | .esp_write8 = pci_esp_write8, | |
303 | .esp_read8 = pci_esp_read8, | |
304 | .map_single = pci_esp_map_single, | |
305 | .map_sg = pci_esp_map_sg, | |
306 | .unmap_single = pci_esp_unmap_single, | |
307 | .unmap_sg = pci_esp_unmap_sg, | |
308 | .irq_pending = pci_esp_irq_pending, | |
309 | .reset_dma = pci_esp_reset_dma, | |
310 | .dma_drain = pci_esp_dma_drain, | |
311 | .dma_invalidate = pci_esp_dma_invalidate, | |
312 | .send_dma_cmd = pci_esp_send_dma_cmd, | |
313 | .dma_error = pci_esp_dma_error, | |
e858d930 | 314 | .dma_length_limit = pci_esp_dma_length_limit, |
3a7e7be2 HR |
315 | }; |
316 | ||
317 | /* | |
318 | * Read DC-390 eeprom | |
319 | */ | |
320 | static void dc390_eeprom_prepare_read(struct pci_dev *pdev, u8 cmd) | |
321 | { | |
322 | u8 carry_flag = 1, j = 0x80, bval; | |
323 | int i; | |
324 | ||
325 | for (i = 0; i < 9; i++) { | |
326 | if (carry_flag) { | |
327 | pci_write_config_byte(pdev, 0x80, 0x40); | |
328 | bval = 0xc0; | |
329 | } else | |
330 | bval = 0x80; | |
331 | ||
332 | udelay(160); | |
333 | pci_write_config_byte(pdev, 0x80, bval); | |
334 | udelay(160); | |
335 | pci_write_config_byte(pdev, 0x80, 0); | |
336 | udelay(160); | |
337 | ||
338 | carry_flag = (cmd & j) ? 1 : 0; | |
339 | j >>= 1; | |
340 | } | |
341 | } | |
342 | ||
343 | static u16 dc390_eeprom_get_data(struct pci_dev *pdev) | |
344 | { | |
345 | int i; | |
346 | u16 wval = 0; | |
347 | u8 bval; | |
348 | ||
349 | for (i = 0; i < 16; i++) { | |
350 | wval <<= 1; | |
351 | ||
352 | pci_write_config_byte(pdev, 0x80, 0x80); | |
353 | udelay(160); | |
354 | pci_write_config_byte(pdev, 0x80, 0x40); | |
355 | udelay(160); | |
356 | pci_read_config_byte(pdev, 0x00, &bval); | |
357 | ||
358 | if (bval == 0x22) | |
359 | wval |= 1; | |
360 | } | |
361 | ||
362 | return wval; | |
363 | } | |
364 | ||
365 | static void dc390_read_eeprom(struct pci_dev *pdev, u16 *ptr) | |
366 | { | |
367 | u8 cmd = DC390_EEPROM_READ, i; | |
368 | ||
369 | for (i = 0; i < DC390_EEPROM_LEN; i++) { | |
370 | pci_write_config_byte(pdev, 0xc0, 0); | |
371 | udelay(160); | |
372 | ||
373 | dc390_eeprom_prepare_read(pdev, cmd++); | |
374 | *ptr++ = dc390_eeprom_get_data(pdev); | |
375 | ||
376 | pci_write_config_byte(pdev, 0x80, 0); | |
377 | pci_write_config_byte(pdev, 0x80, 0); | |
378 | udelay(160); | |
379 | } | |
380 | } | |
381 | ||
382 | static void dc390_check_eeprom(struct esp *esp) | |
383 | { | |
384 | u8 EEbuf[128]; | |
385 | u16 *ptr = (u16 *)EEbuf, wval = 0; | |
386 | int i; | |
387 | ||
388 | dc390_read_eeprom((struct pci_dev *)esp->dev, ptr); | |
389 | ||
390 | for (i = 0; i < DC390_EEPROM_LEN; i++, ptr++) | |
391 | wval += *ptr; | |
392 | ||
393 | /* no Tekram EEprom found */ | |
394 | if (wval != 0x1234) { | |
395 | struct pci_dev *pdev = esp->dev; | |
396 | dev_printk(KERN_INFO, &pdev->dev, | |
397 | "No valid Tekram EEprom found\n"); | |
398 | return; | |
399 | } | |
400 | esp->scsi_id = EEbuf[DC390_EE_ADAPT_SCSI_ID]; | |
401 | esp->num_tags = 2 << EEbuf[DC390_EE_TAG_CMD_NUM]; | |
eeea2f9c HR |
402 | if (EEbuf[DC390_EE_MODE2] & DC390_EE_MODE2_ACTIVE_NEGATION) |
403 | esp->config4 |= ESP_CONFIG4_RADE | ESP_CONFIG4_RAE; | |
3a7e7be2 HR |
404 | } |
405 | ||
406 | static int pci_esp_probe_one(struct pci_dev *pdev, | |
407 | const struct pci_device_id *id) | |
408 | { | |
409 | struct scsi_host_template *hostt = &scsi_esp_template; | |
410 | int err = -ENODEV; | |
411 | struct Scsi_Host *shost; | |
412 | struct esp *esp; | |
413 | struct pci_esp_priv *pep; | |
414 | ||
415 | if (pci_enable_device(pdev)) { | |
416 | dev_printk(KERN_INFO, &pdev->dev, "cannot enable device\n"); | |
417 | return -ENODEV; | |
418 | } | |
419 | ||
420 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { | |
421 | dev_printk(KERN_INFO, &pdev->dev, | |
422 | "failed to set 32bit DMA mask\n"); | |
423 | goto fail_disable_device; | |
424 | } | |
425 | ||
426 | shost = scsi_host_alloc(hostt, sizeof(struct esp)); | |
427 | if (!shost) { | |
428 | dev_printk(KERN_INFO, &pdev->dev, | |
429 | "failed to allocate scsi host\n"); | |
430 | err = -ENOMEM; | |
431 | goto fail_disable_device; | |
432 | } | |
433 | ||
434 | pep = kzalloc(sizeof(struct pci_esp_priv), GFP_KERNEL); | |
435 | if (!pep) { | |
436 | dev_printk(KERN_INFO, &pdev->dev, | |
437 | "failed to allocate esp_priv\n"); | |
438 | err = -ENOMEM; | |
439 | goto fail_host_alloc; | |
440 | } | |
441 | ||
442 | esp = shost_priv(shost); | |
443 | esp->host = shost; | |
444 | esp->dev = pdev; | |
445 | esp->ops = &pci_esp_ops; | |
446 | /* | |
447 | * The am53c974 HBA has a design flaw of generating | |
448 | * spurious DMA completion interrupts when using | |
449 | * DMA for command submission. | |
450 | */ | |
451 | esp->flags |= ESP_FLAG_USE_FIFO; | |
e858d930 HR |
452 | /* |
453 | * Enable CONFIG2_FENAB to allow for large DMA transfers | |
454 | */ | |
455 | if (am53c974_fenab) | |
456 | esp->config2 |= ESP_CONFIG2_FENAB; | |
457 | ||
3a7e7be2 HR |
458 | pep->esp = esp; |
459 | ||
460 | if (pci_request_regions(pdev, DRV_MODULE_NAME)) { | |
461 | dev_printk(KERN_ERR, &pdev->dev, | |
462 | "pci memory selection failed\n"); | |
463 | goto fail_priv_alloc; | |
464 | } | |
465 | ||
466 | esp->regs = pci_iomap(pdev, 0, pci_resource_len(pdev, 0)); | |
467 | if (!esp->regs) { | |
468 | dev_printk(KERN_ERR, &pdev->dev, "pci I/O map failed\n"); | |
469 | err = -EINVAL; | |
470 | goto fail_release_regions; | |
471 | } | |
472 | esp->dma_regs = esp->regs; | |
473 | ||
474 | pci_set_master(pdev); | |
475 | ||
476 | esp->command_block = pci_alloc_consistent(pdev, 16, | |
477 | &esp->command_block_dma); | |
478 | if (!esp->command_block) { | |
479 | dev_printk(KERN_ERR, &pdev->dev, | |
480 | "failed to allocate command block\n"); | |
481 | err = -ENOMEM; | |
482 | goto fail_unmap_regs; | |
483 | } | |
484 | ||
485 | err = request_irq(pdev->irq, scsi_esp_intr, IRQF_SHARED, | |
486 | DRV_MODULE_NAME, esp); | |
487 | if (err < 0) { | |
488 | dev_printk(KERN_ERR, &pdev->dev, "failed to register IRQ\n"); | |
489 | goto fail_unmap_command_block; | |
490 | } | |
491 | ||
492 | esp->scsi_id = 7; | |
493 | dc390_check_eeprom(esp); | |
494 | ||
495 | shost->this_id = esp->scsi_id; | |
496 | shost->max_id = 8; | |
497 | shost->irq = pdev->irq; | |
498 | shost->io_port = pci_resource_start(pdev, 0); | |
499 | shost->n_io_port = pci_resource_len(pdev, 0); | |
500 | shost->unique_id = shost->io_port; | |
501 | esp->scsi_id_mask = (1 << esp->scsi_id); | |
502 | /* Assume 40MHz clock */ | |
503 | esp->cfreq = 40000000; | |
504 | ||
505 | pci_set_drvdata(pdev, pep); | |
506 | ||
507 | err = scsi_esp_register(esp, &pdev->dev); | |
508 | if (err) | |
509 | goto fail_free_irq; | |
510 | ||
511 | return 0; | |
512 | ||
513 | fail_free_irq: | |
514 | free_irq(pdev->irq, esp); | |
515 | fail_unmap_command_block: | |
516 | pci_free_consistent(pdev, 16, esp->command_block, | |
517 | esp->command_block_dma); | |
518 | fail_unmap_regs: | |
519 | pci_iounmap(pdev, esp->regs); | |
520 | fail_release_regions: | |
521 | pci_release_regions(pdev); | |
522 | fail_priv_alloc: | |
523 | kfree(pep); | |
524 | fail_host_alloc: | |
525 | scsi_host_put(shost); | |
526 | fail_disable_device: | |
527 | pci_disable_device(pdev); | |
528 | ||
529 | return err; | |
530 | } | |
531 | ||
532 | static void pci_esp_remove_one(struct pci_dev *pdev) | |
533 | { | |
534 | struct pci_esp_priv *pep = pci_get_drvdata(pdev); | |
535 | struct esp *esp = pep->esp; | |
536 | ||
537 | scsi_esp_unregister(esp); | |
538 | free_irq(pdev->irq, esp); | |
539 | pci_free_consistent(pdev, 16, esp->command_block, | |
540 | esp->command_block_dma); | |
541 | pci_iounmap(pdev, esp->regs); | |
542 | pci_release_regions(pdev); | |
543 | pci_disable_device(pdev); | |
544 | kfree(pep); | |
545 | ||
546 | scsi_host_put(esp->host); | |
547 | } | |
548 | ||
549 | static struct pci_device_id am53c974_pci_tbl[] = { | |
550 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_SCSI, | |
551 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
552 | { } | |
553 | }; | |
554 | MODULE_DEVICE_TABLE(pci, am53c974_pci_tbl); | |
555 | ||
556 | static struct pci_driver am53c974_driver = { | |
557 | .name = DRV_MODULE_NAME, | |
558 | .id_table = am53c974_pci_tbl, | |
559 | .probe = pci_esp_probe_one, | |
560 | .remove = pci_esp_remove_one, | |
561 | }; | |
562 | ||
563 | static int __init am53c974_module_init(void) | |
564 | { | |
565 | return pci_register_driver(&am53c974_driver); | |
566 | } | |
567 | ||
568 | static void __exit am53c974_module_exit(void) | |
569 | { | |
570 | pci_unregister_driver(&am53c974_driver); | |
571 | } | |
572 | ||
573 | MODULE_DESCRIPTION("AM53C974 SCSI driver"); | |
574 | MODULE_AUTHOR("Hannes Reinecke <hare@suse.de>"); | |
575 | MODULE_LICENSE("GPL"); | |
576 | MODULE_VERSION(DRV_MODULE_VERSION); | |
71bd849d | 577 | MODULE_ALIAS("tmscsim"); |
3a7e7be2 HR |
578 | |
579 | module_param(am53c974_debug, bool, 0644); | |
580 | MODULE_PARM_DESC(am53c974_debug, "Enable debugging"); | |
581 | ||
e858d930 HR |
582 | module_param(am53c974_fenab, bool, 0444); |
583 | MODULE_PARM_DESC(am53c974_fenab, "Enable 24-bit DMA transfer sizes"); | |
584 | ||
3a7e7be2 HR |
585 | module_init(am53c974_module_init); |
586 | module_exit(am53c974_module_exit); |