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[SCSI] remove flush_scheduled_work() usages
[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / arcmsr / arcmsr_hba.c
CommitLineData
1c57e86d
EC		 1/*
2*******************************************************************************
3** O.S : Linux
4** FILE NAME : arcmsr_hba.c
5** BY : Erich Chen
6** Description: SCSI RAID Device Driver for
7** ARECA RAID Host adapter
8*******************************************************************************
9** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved
10**
11** Web site: www.areca.com.tw
1a4f550a 12** E-mail: support@areca.com.tw
1c57e86d
EC		 13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License version 2 as
16** published by the Free Software Foundation.
17** This program is distributed in the hope that it will be useful,
18** but WITHOUT ANY WARRANTY; without even the implied warranty of
19** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20** GNU General Public License for more details.
21*******************************************************************************
22** Redistribution and use in source and binary forms, with or without
23** modification, are permitted provided that the following conditions
24** are met:
25** 1. Redistributions of source code must retain the above copyright
26** notice, this list of conditions and the following disclaimer.
27** 2. Redistributions in binary form must reproduce the above copyright
28** notice, this list of conditions and the following disclaimer in the
29** documentation and/or other materials provided with the distribution.
30** 3. The name of the author may not be used to endorse or promote products
31** derived from this software without specific prior written permission.
32**
33** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
34** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
35** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
36** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
37** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
38** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
40** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43*******************************************************************************
44** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
45** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
46*******************************************************************************
47*/
48#include <linux/module.h>
49#include <linux/reboot.h>
50#include <linux/spinlock.h>
51#include <linux/pci_ids.h>
52#include <linux/interrupt.h>
53#include <linux/moduleparam.h>
54#include <linux/errno.h>
55#include <linux/types.h>
56#include <linux/delay.h>
57#include <linux/dma-mapping.h>
58#include <linux/timer.h>
a7c8962b 59#include <linux/slab.h>
1c57e86d 60#include <linux/pci.h>
a1f6e021 61#include <linux/aer.h>
1c57e86d
EC		 62#include <asm/dma.h>
63#include <asm/io.h>
64#include <asm/system.h>
65#include <asm/uaccess.h>
66#include <scsi/scsi_host.h>
67#include <scsi/scsi.h>
68#include <scsi/scsi_cmnd.h>
69#include <scsi/scsi_tcq.h>
70#include <scsi/scsi_device.h>
71#include <scsi/scsi_transport.h>
72#include <scsi/scsicam.h>
73#include "arcmsr.h"
ae52e7f0 74MODULE_AUTHOR("Nick Cheng <support@areca.com.tw>");
cdd3cb15 75MODULE_DESCRIPTION("ARECA (ARC11xx/12xx/16xx/1880) SATA/SAS RAID Host Bus Adapter");
1c57e86d
EC		 76MODULE_LICENSE("Dual BSD/GPL");
77MODULE_VERSION(ARCMSR_DRIVER_VERSION);
cdd3cb15
NC		 78static int sleeptime = 10;
79static int retrycount = 30;
ae52e7f0 80wait_queue_head_t wait_q;
1a4f550a
NC		 81static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
82 struct scsi_cmnd *cmd);
83static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
1c57e86d
EC		 84static int arcmsr_abort(struct scsi_cmnd *);
85static int arcmsr_bus_reset(struct scsi_cmnd *);
86static int arcmsr_bios_param(struct scsi_device *sdev,
1a4f550a 87 struct block_device *bdev, sector_t capacity, int *info);
f281233d 88static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1c57e86d
EC		 89static int arcmsr_probe(struct pci_dev *pdev,
90 const struct pci_device_id *id);
91static void arcmsr_remove(struct pci_dev *pdev);
92static void arcmsr_shutdown(struct pci_dev *pdev);
93static void arcmsr_iop_init(struct AdapterControlBlock *acb);
94static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
1a4f550a 95static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
1c57e86d 96static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
1a4f550a
NC		 97static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb);
98static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb);
36b83ded
NC		 99static void arcmsr_request_device_map(unsigned long pacb);
100static void arcmsr_request_hba_device_map(struct AdapterControlBlock *acb);
101static void arcmsr_request_hbb_device_map(struct AdapterControlBlock *acb);
cdd3cb15 102static void arcmsr_request_hbc_device_map(struct AdapterControlBlock *acb);
36b83ded 103static void arcmsr_message_isr_bh_fn(struct work_struct *work);
ae52e7f0 104static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
36b83ded 105static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
cdd3cb15
NC		 106static void arcmsr_hbc_message_isr(struct AdapterControlBlock *pACB);
107static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
1c57e86d
EC		 108static const char *arcmsr_info(struct Scsi_Host *);
109static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
1a4f550a 110static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev,
e881a172 111 int queue_depth, int reason)
1c57e86d 112{
e881a172
MC		 113 if (reason != SCSI_QDEPTH_DEFAULT)
114 return -EOPNOTSUPP;
115
1c57e86d
EC		 116 if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
117 queue_depth = ARCMSR_MAX_CMD_PERLUN;
118 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, queue_depth);
119 return queue_depth;
120}
121
122static struct scsi_host_template arcmsr_scsi_host_template = {
123 .module = THIS_MODULE,
cdd3cb15
NC		 124 .name = "ARCMSR ARECA SATA/SAS RAID Controller"
125 ARCMSR_DRIVER_VERSION,
1c57e86d
EC		 126 .info = arcmsr_info,
127 .queuecommand = arcmsr_queue_command,
cdd3cb15 128 .eh_abort_handler = arcmsr_abort,
1c57e86d
EC		 129 .eh_bus_reset_handler = arcmsr_bus_reset,
130 .bios_param = arcmsr_bios_param,
131 .change_queue_depth = arcmsr_adjust_disk_queue_depth,
ae52e7f0 132 .can_queue = ARCMSR_MAX_FREECCB_NUM,
cdd3cb15
NC		 133 .this_id = ARCMSR_SCSI_INITIATOR_ID,
134 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
135 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
1c57e86d
EC		 136 .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
137 .use_clustering = ENABLE_CLUSTERING,
138 .shost_attrs = arcmsr_host_attrs,
139};
1c57e86d
EC		 140static struct pci_device_id arcmsr_device_id_table[] = {
141 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110)},
142 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120)},
143 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130)},
144 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160)},
145 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170)},
1a4f550a
NC		 146 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200)},
147 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201)},
148 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202)},
1c57e86d
EC		 149 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210)},
150 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220)},
151 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230)},
152 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260)},
153 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270)},
154 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280)},
155 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380)},
156 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381)},
157 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680)},
158 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681)},
ae52e7f0 159 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880)},
1c57e86d
EC		 160 {0, 0}, /* Terminating entry */
161};
162MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
163static struct pci_driver arcmsr_pci_driver = {
164 .name = "arcmsr",
cdd3cb15 165 .id_table = arcmsr_device_id_table,
1c57e86d
EC		 166 .probe = arcmsr_probe,
167 .remove = arcmsr_remove,
a1f6e021 168 .shutdown = arcmsr_shutdown,
1c57e86d 169};
cdd3cb15
NC		 170/*
171****************************************************************************
172****************************************************************************
173*/
174int arcmsr_sleep_for_bus_reset(struct scsi_cmnd *cmd)
175{
176 struct Scsi_Host *shost = NULL;
177 int i, isleep;
178 shost = cmd->device->host;
179 isleep = sleeptime / 10;
180 if (isleep > 0) {
181 for (i = 0; i < isleep; i++) {
182 msleep(10000);
183 }
184 }
185
186 isleep = sleeptime % 10;
187 if (isleep > 0) {
188 msleep(isleep*1000);
189 }
190 printk(KERN_NOTICE "wake-up\n");
191 return 0;
192}
1c57e86d 193
cdd3cb15 194static void arcmsr_free_hbb_mu(struct AdapterControlBlock *acb)
ae52e7f0
NC		 195{
196 switch (acb->adapter_type) {
197 case ACB_ADAPTER_TYPE_A:
cdd3cb15 198 case ACB_ADAPTER_TYPE_C:
ae52e7f0
NC		 199 break;
200 case ACB_ADAPTER_TYPE_B:{
cdd3cb15
NC		 201 dma_free_coherent(&acb->pdev->dev,
202 sizeof(struct MessageUnit_B),
203 acb->pmuB, acb->dma_coherent_handle_hbb_mu);
ae52e7f0
NC		 204 }
205 }
206}
207
208static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
209{
210 struct pci_dev *pdev = acb->pdev;
cdd3cb15 211 switch (acb->adapter_type){
ae52e7f0 212 case ACB_ADAPTER_TYPE_A:{
cdd3cb15 213 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
ae52e7f0
NC		 214 if (!acb->pmuA) {
215 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
216 return false;
217 }
218 break;
219 }
220 case ACB_ADAPTER_TYPE_B:{
221 void __iomem *mem_base0, *mem_base1;
222 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
223 if (!mem_base0) {
224 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
225 return false;
226 }
227 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
228 if (!mem_base1) {
229 iounmap(mem_base0);
230 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
231 return false;
232 }
233 acb->mem_base0 = mem_base0;
234 acb->mem_base1 = mem_base1;
cdd3cb15
NC		 235 break;
236 }
237 case ACB_ADAPTER_TYPE_C:{
238 acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
239 if (!acb->pmuC) {
240 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
241 return false;
242 }
243 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
244 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
245 return true;
246 }
247 break;
ae52e7f0
NC		 248 }
249 }
250 return true;
251}
252
253static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
254{
255 switch (acb->adapter_type) {
cdd3cb15
NC		 256 case ACB_ADAPTER_TYPE_A:{
257 iounmap(acb->pmuA);
258 }
259 break;
260 case ACB_ADAPTER_TYPE_B:{
261 iounmap(acb->mem_base0);
262 iounmap(acb->mem_base1);
263 }
264
265 break;
266 case ACB_ADAPTER_TYPE_C:{
267 iounmap(acb->pmuC);
268 }
ae52e7f0
NC		 269 }
270}
271
7d12e780 272static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
1c57e86d
EC		 273{
274 irqreturn_t handle_state;
1a4f550a 275 struct AdapterControlBlock *acb = dev_id;
1c57e86d 276
1c57e86d 277 handle_state = arcmsr_interrupt(acb);
1c57e86d
EC		 278 return handle_state;
279}
280
281static int arcmsr_bios_param(struct scsi_device *sdev,
282 struct block_device *bdev, sector_t capacity, int *geom)
283{
284 int ret, heads, sectors, cylinders, total_capacity;
285 unsigned char *buffer;/* return copy of block device's partition table */
286
287 buffer = scsi_bios_ptable(bdev);
288 if (buffer) {
289 ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
290 kfree(buffer);
291 if (ret != -1)
292 return ret;
293 }
294 total_capacity = capacity;
295 heads = 64;
296 sectors = 32;
297 cylinders = total_capacity / (heads * sectors);
298 if (cylinders > 1024) {
299 heads = 255;
300 sectors = 63;
301 cylinders = total_capacity / (heads * sectors);
302 }
303 geom[0] = heads;
304 geom[1] = sectors;
305 geom[2] = cylinders;
306 return 0;
307}
308
1a4f550a 309static void arcmsr_define_adapter_type(struct AdapterControlBlock *acb)
1c57e86d
EC		 310{
311 struct pci_dev *pdev = acb->pdev;
1a4f550a
NC		 312 u16 dev_id;
313 pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
ae52e7f0 314 acb->dev_id = dev_id;
1a4f550a 315 switch (dev_id) {
cdd3cb15
NC		 316 case 0x1880: {
317 acb->adapter_type = ACB_ADAPTER_TYPE_C;
318 }
319 break;
320 case 0x1201: {
1a4f550a
NC		 321 acb->adapter_type = ACB_ADAPTER_TYPE_B;
322 }
323 break;
324
cdd3cb15 325 default: acb->adapter_type = ACB_ADAPTER_TYPE_A;
1a4f550a 326 }
cdd3cb15 327}
1a4f550a 328
ae52e7f0
NC		 329static uint8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
330{
331 struct MessageUnit_A __iomem *reg = acb->pmuA;
332 uint32_t Index;
333 uint8_t Retries = 0x00;
ae52e7f0
NC		 334 do {
335 for (Index = 0; Index < 100; Index++) {
336 if (readl(&reg->outbound_intstatus) &
337 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
338 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
339 &reg->outbound_intstatus);
cdd3cb15 340 return true;
ae52e7f0
NC		 341 }
342 msleep(10);
cdd3cb15 343 }/*max 1 seconds*/
ae52e7f0
NC		 344
345 } while (Retries++ < 20);/*max 20 sec*/
cdd3cb15 346 return false;
ae52e7f0
NC		 347}
348
349static uint8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
1a4f550a 350{
ae52e7f0
NC		 351 struct MessageUnit_B *reg = acb->pmuB;
352 uint32_t Index;
353 uint8_t Retries = 0x00;
ae52e7f0
NC		 354 do {
355 for (Index = 0; Index < 100; Index++) {
356 if (readl(reg->iop2drv_doorbell)
357 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
358 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN
359 , reg->iop2drv_doorbell);
360 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
cdd3cb15 361 return true;
ae52e7f0
NC		 362 }
363 msleep(10);
cdd3cb15 364 }/*max 1 seconds*/
ae52e7f0
NC		 365
366 } while (Retries++ < 20);/*max 20 sec*/
cdd3cb15 367 return false;
ae52e7f0
NC		 368}
369
cdd3cb15
NC		 370static uint8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *pACB)
371{
372 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
373 unsigned char Retries = 0x00;
374 uint32_t Index;
375 do {
376 for (Index = 0; Index < 100; Index++) {
377 if (readl(&phbcmu->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
378 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &phbcmu->outbound_doorbell_clear);/*clear interrupt*/
379 return true;
380 }
381 /* one us delay */
382 msleep(10);
383 } /*max 1 seconds*/
384 } while (Retries++ < 20); /*max 20 sec*/
385 return false;
386}
ae52e7f0
NC		 387static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
388{
389 struct MessageUnit_A __iomem *reg = acb->pmuA;
390 int retry_count = 30;
ae52e7f0
NC		 391 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
392 do {
cdd3cb15 393 if (arcmsr_hba_wait_msgint_ready(acb))
ae52e7f0
NC		 394 break;
395 else {
396 retry_count--;
397 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
398 timeout, retry count down = %d \n", acb->host->host_no, retry_count);
399 }
400 } while (retry_count != 0);
401}
402
403static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
404{
405 struct MessageUnit_B *reg = acb->pmuB;
406 int retry_count = 30;
ae52e7f0
NC		 407 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
408 do {
cdd3cb15 409 if (arcmsr_hbb_wait_msgint_ready(acb))
ae52e7f0
NC		 410 break;
411 else {
412 retry_count--;
413 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
414 timeout,retry count down = %d \n", acb->host->host_no, retry_count);
415 }
416 } while (retry_count != 0);
417}
418
cdd3cb15
NC		 419static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *pACB)
420{
421 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
422 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
423 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
424 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
425 do {
426 if (arcmsr_hbc_wait_msgint_ready(pACB)) {
427 break;
428 } else {
429 retry_count--;
430 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
431 timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
432 }
433 } while (retry_count != 0);
434 return;
435}
ae52e7f0
NC		 436static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
437{
1a4f550a 438 switch (acb->adapter_type) {
1c57e86d 439
1a4f550a 440 case ACB_ADAPTER_TYPE_A: {
ae52e7f0
NC		 441 arcmsr_flush_hba_cache(acb);
442 }
443 break;
1a4f550a 444
ae52e7f0
NC		 445 case ACB_ADAPTER_TYPE_B: {
446 arcmsr_flush_hbb_cache(acb);
1a4f550a 447 }
cdd3cb15
NC		 448 break;
449 case ACB_ADAPTER_TYPE_C: {
450 arcmsr_flush_hbc_cache(acb);
451 }
ae52e7f0
NC		 452 }
453}
1a4f550a 454
ae52e7f0
NC		 455static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
456{
cdd3cb15
NC		 457 struct pci_dev *pdev = acb->pdev;
458 void *dma_coherent;
459 dma_addr_t dma_coherent_handle;
460 struct CommandControlBlock *ccb_tmp;
461 int i = 0, j = 0;
462 dma_addr_t cdb_phyaddr;
463 unsigned long roundup_ccbsize = 0, offset;
464 unsigned long max_xfer_len;
465 unsigned long max_sg_entrys;
466 uint32_t firm_config_version;
467 for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
468 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
469 acb->devstate[i][j] = ARECA_RAID_GONE;
470
471 max_xfer_len = ARCMSR_MAX_XFER_LEN;
472 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
473 firm_config_version = acb->firm_cfg_version;
474 if((firm_config_version & 0xFF) >= 3){
475 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
476 max_sg_entrys = (max_xfer_len/4096);
477 }
478 acb->host->max_sectors = max_xfer_len/512;
479 acb->host->sg_tablesize = max_sg_entrys;
480 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
481 acb->uncache_size = roundup_ccbsize * ARCMSR_MAX_FREECCB_NUM + 32;
482 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
483 if(!dma_coherent){
484 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error \n", acb->host->host_no);
485 return -ENOMEM;
486 }
487 acb->dma_coherent = dma_coherent;
488 acb->dma_coherent_handle = dma_coherent_handle;
489 memset(dma_coherent, 0, acb->uncache_size);
490 offset = roundup((unsigned long)dma_coherent, 32) - (unsigned long)dma_coherent;
491 dma_coherent_handle = dma_coherent_handle + offset;
492 dma_coherent = (struct CommandControlBlock *)dma_coherent + offset;
493 ccb_tmp = dma_coherent;
494 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
495 for(i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++){
496 cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
497 ccb_tmp->cdb_phyaddr_pattern = ((acb->adapter_type == ACB_ADAPTER_TYPE_C) ? cdb_phyaddr : (cdb_phyaddr >> 5));
498 acb->pccb_pool[i] = ccb_tmp;
499 ccb_tmp->acb = acb;
500 INIT_LIST_HEAD(&ccb_tmp->list);
501 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
502 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
503 dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;
1a4f550a 504 }
1c57e86d
EC		 505 return 0;
506}
36b83ded 507
cdd3cb15
NC		 508static void arcmsr_message_isr_bh_fn(struct work_struct *work)
509{
510 struct AdapterControlBlock *acb = container_of(work,struct AdapterControlBlock, arcmsr_do_message_isr_bh);
36b83ded
NC		 511 switch (acb->adapter_type) {
512 case ACB_ADAPTER_TYPE_A: {
513
514 struct MessageUnit_A __iomem *reg = acb->pmuA;
515 char *acb_dev_map = (char *)acb->device_map;
cdd3cb15
NC		 516 uint32_t __iomem *signature = (uint32_t __iomem*) (&reg->message_rwbuffer[0]);
517 char __iomem *devicemap = (char __iomem*) (&reg->message_rwbuffer[21]);
36b83ded
NC		 518 int target, lun;
519 struct scsi_device *psdev;
520 char diff;
521
522 atomic_inc(&acb->rq_map_token);
523 if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
cdd3cb15 524 for(target = 0; target < ARCMSR_MAX_TARGETID -1; target++) {
36b83ded
NC		 525 diff = (*acb_dev_map)^readb(devicemap);
526 if (diff != 0) {
527 char temp;
528 *acb_dev_map = readb(devicemap);
cdd3cb15
NC		 529 temp =*acb_dev_map;
530 for(lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
531 if((temp & 0x01)==1 && (diff & 0x01) == 1) {
36b83ded 532 scsi_add_device(acb->host, 0, target, lun);
cdd3cb15 533 }else if((temp & 0x01) == 0 && (diff & 0x01) == 1) {
36b83ded 534 psdev = scsi_device_lookup(acb->host, 0, target, lun);
cdd3cb15 535 if (psdev != NULL ) {
36b83ded
NC		 536 scsi_remove_device(psdev);
537 scsi_device_put(psdev);
538 }
539 }
540 temp >>= 1;
541 diff >>= 1;
542 }
543 }
544 devicemap++;
545 acb_dev_map++;
546 }
547 }
548 break;
549 }
550
551 case ACB_ADAPTER_TYPE_B: {
552 struct MessageUnit_B *reg = acb->pmuB;
553 char *acb_dev_map = (char *)acb->device_map;
cdd3cb15
NC		 554 uint32_t __iomem *signature = (uint32_t __iomem*)(&reg->message_rwbuffer[0]);
555 char __iomem *devicemap = (char __iomem*)(&reg->message_rwbuffer[21]);
556 int target, lun;
557 struct scsi_device *psdev;
558 char diff;
559
560 atomic_inc(&acb->rq_map_token);
561 if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
562 for(target = 0; target < ARCMSR_MAX_TARGETID -1; target++) {
563 diff = (*acb_dev_map)^readb(devicemap);
564 if (diff != 0) {
565 char temp;
566 *acb_dev_map = readb(devicemap);
567 temp =*acb_dev_map;
568 for(lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
569 if((temp & 0x01)==1 && (diff & 0x01) == 1) {
570 scsi_add_device(acb->host, 0, target, lun);
571 }else if((temp & 0x01) == 0 && (diff & 0x01) == 1) {
572 psdev = scsi_device_lookup(acb->host, 0, target, lun);
573 if (psdev != NULL ) {
574 scsi_remove_device(psdev);
575 scsi_device_put(psdev);
576 }
577 }
578 temp >>= 1;
579 diff >>= 1;
580 }
581 }
582 devicemap++;
583 acb_dev_map++;
584 }
585 }
586 }
587 break;
588 case ACB_ADAPTER_TYPE_C: {
589 struct MessageUnit_C *reg = acb->pmuC;
590 char *acb_dev_map = (char *)acb->device_map;
591 uint32_t __iomem *signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
592 char __iomem *devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
36b83ded
NC		 593 int target, lun;
594 struct scsi_device *psdev;
595 char diff;
596
597 atomic_inc(&acb->rq_map_token);
598 if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
599 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) {
600 diff = (*acb_dev_map)^readb(devicemap);
601 if (diff != 0) {
602 char temp;
603 *acb_dev_map = readb(devicemap);
604 temp = *acb_dev_map;
605 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
606 if ((temp & 0x01) == 1 && (diff & 0x01) == 1) {
607 scsi_add_device(acb->host, 0, target, lun);
608 } else if ((temp & 0x01) == 0 && (diff & 0x01) == 1) {
609 psdev = scsi_device_lookup(acb->host, 0, target, lun);
610 if (psdev != NULL) {
611 scsi_remove_device(psdev);
612 scsi_device_put(psdev);
613 }
614 }
615 temp >>= 1;
616 diff >>= 1;
617 }
618 }
619 devicemap++;
620 acb_dev_map++;
621 }
622 }
623 }
624 }
625}
1c57e86d 626
ae52e7f0 627static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1c57e86d
EC		 628{
629 struct Scsi_Host *host;
630 struct AdapterControlBlock *acb;
cdd3cb15 631 uint8_t bus,dev_fun;
1c57e86d 632 int error;
1c57e86d 633 error = pci_enable_device(pdev);
cdd3cb15 634 if(error){
ae52e7f0
NC		 635 return -ENODEV;
636 }
637 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
cdd3cb15
NC		 638 if(!host){
639 goto pci_disable_dev;
1c57e86d 640 }
6a35528a 641 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
cdd3cb15 642 if(error){
284901a9 643 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cdd3cb15 644 if(error){
1c57e86d
EC		 645 printk(KERN_WARNING
646 "scsi%d: No suitable DMA mask available\n",
647 host->host_no);
ae52e7f0 648 goto scsi_host_release;
1c57e86d
EC		 649 }
650 }
ae52e7f0 651 init_waitqueue_head(&wait_q);
1c57e86d
EC		 652 bus = pdev->bus->number;
653 dev_fun = pdev->devfn;
ae52e7f0 654 acb = (struct AdapterControlBlock *) host->hostdata;
cdd3cb15 655 memset(acb,0,sizeof(struct AdapterControlBlock));
1c57e86d 656 acb->pdev = pdev;
ae52e7f0 657 acb->host = host;
1c57e86d 658 host->max_lun = ARCMSR_MAX_TARGETLUN;
cdd3cb15
NC		 659 host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
660 host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
661 host->can_queue = ARCMSR_MAX_FREECCB_NUM; /* max simultaneous cmds */
662 host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
1c57e86d
EC		 663 host->this_id = ARCMSR_SCSI_INITIATOR_ID;
664 host->unique_id = (bus << 8) | dev_fun;
ae52e7f0
NC		 665 pci_set_drvdata(pdev, host);
666 pci_set_master(pdev);
1c57e86d 667 error = pci_request_regions(pdev, "arcmsr");
cdd3cb15 668 if(error){
ae52e7f0 669 goto scsi_host_release;
1c57e86d 670 }
ae52e7f0
NC		 671 spin_lock_init(&acb->eh_lock);
672 spin_lock_init(&acb->ccblist_lock);
1c57e86d 673 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
cdd3cb15
NC		 674 ACB_F_MESSAGE_RQBUFFER_CLEARED |
675 ACB_F_MESSAGE_WQBUFFER_READED);
1c57e86d
EC		 676 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
677 INIT_LIST_HEAD(&acb->ccb_free_list);
ae52e7f0
NC		 678 arcmsr_define_adapter_type(acb);
679 error = arcmsr_remap_pciregion(acb);
cdd3cb15 680 if(!error){
ae52e7f0
NC		 681 goto pci_release_regs;
682 }
683 error = arcmsr_get_firmware_spec(acb);
cdd3cb15 684 if(!error){
ae52e7f0
NC		 685 goto unmap_pci_region;
686 }
1c57e86d 687 error = arcmsr_alloc_ccb_pool(acb);
cdd3cb15 688 if(error){
ae52e7f0
NC		 689 goto free_hbb_mu;
690 }
36b83ded 691 arcmsr_iop_init(acb);
1c57e86d 692 error = scsi_add_host(host, &pdev->dev);
cdd3cb15 693 if(error){
ae52e7f0
NC		 694 goto RAID_controller_stop;
695 }
696 error = request_irq(pdev->irq, arcmsr_do_interrupt, IRQF_SHARED, "arcmsr", acb);
cdd3cb15 697 if(error){
ae52e7f0
NC		 698 goto scsi_host_remove;
699 }
700 host->irq = pdev->irq;
cdd3cb15 701 scsi_scan_host(host);
ae52e7f0 702 INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
36b83ded 703 atomic_set(&acb->rq_map_token, 16);
ae52e7f0
NC		 704 atomic_set(&acb->ante_token_value, 16);
705 acb->fw_flag = FW_NORMAL;
36b83ded 706 init_timer(&acb->eternal_timer);
ae52e7f0 707 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
36b83ded
NC		 708 acb->eternal_timer.data = (unsigned long) acb;
709 acb->eternal_timer.function = &arcmsr_request_device_map;
710 add_timer(&acb->eternal_timer);
cdd3cb15 711 if(arcmsr_alloc_sysfs_attr(acb))
ae52e7f0 712 goto out_free_sysfs;
1c57e86d 713 return 0;
cdd3cb15 714out_free_sysfs:
ae52e7f0
NC		 715scsi_host_remove:
716 scsi_remove_host(host);
717RAID_controller_stop:
718 arcmsr_stop_adapter_bgrb(acb);
719 arcmsr_flush_adapter_cache(acb);
1c57e86d 720 arcmsr_free_ccb_pool(acb);
ae52e7f0 721free_hbb_mu:
cdd3cb15 722 arcmsr_free_hbb_mu(acb);
ae52e7f0
NC		 723unmap_pci_region:
724 arcmsr_unmap_pciregion(acb);
725pci_release_regs:
1c57e86d 726 pci_release_regions(pdev);
ae52e7f0 727scsi_host_release:
1c57e86d 728 scsi_host_put(host);
ae52e7f0 729pci_disable_dev:
1c57e86d 730 pci_disable_device(pdev);
ae52e7f0 731 return -ENODEV;
1a4f550a
NC		 732}
733
36b83ded 734static uint8_t arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
1c57e86d 735{
80da1adb 736 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 737 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
cdd3cb15 738 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 739 printk(KERN_NOTICE
740 "arcmsr%d: wait 'abort all outstanding command' timeout \n"
741 , acb->host->host_no);
cdd3cb15 742 return false;
36b83ded 743 }
cdd3cb15 744 return true;
1a4f550a
NC		 745}
746
36b83ded 747static uint8_t arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
1a4f550a 748{
80da1adb 749 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 750
ae52e7f0 751 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
cdd3cb15 752 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1c57e86d
EC		 753 printk(KERN_NOTICE
754 "arcmsr%d: wait 'abort all outstanding command' timeout \n"
755 , acb->host->host_no);
cdd3cb15 756 return false;
36b83ded 757 }
cdd3cb15
NC		 758 return true;
759}
760static uint8_t arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *pACB)
761{
762 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
763 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
764 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
765 if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
766 printk(KERN_NOTICE
767 "arcmsr%d: wait 'abort all outstanding command' timeout \n"
768 , pACB->host->host_no);
769 return false;
770 }
771 return true;
1c57e86d 772}
36b83ded 773static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
1a4f550a 774{
36b83ded 775 uint8_t rtnval = 0;
1a4f550a
NC		 776 switch (acb->adapter_type) {
777 case ACB_ADAPTER_TYPE_A: {
36b83ded 778 rtnval = arcmsr_abort_hba_allcmd(acb);
1a4f550a
NC		 779 }
780 break;
781
782 case ACB_ADAPTER_TYPE_B: {
36b83ded 783 rtnval = arcmsr_abort_hbb_allcmd(acb);
1a4f550a 784 }
cdd3cb15
NC		 785 break;
786
787 case ACB_ADAPTER_TYPE_C: {
788 rtnval = arcmsr_abort_hbc_allcmd(acb);
789 }
1a4f550a 790 }
36b83ded 791 return rtnval;
1a4f550a
NC		 792}
793
ae52e7f0
NC		 794static bool arcmsr_hbb_enable_driver_mode(struct AdapterControlBlock *pacb)
795{
796 struct MessageUnit_B *reg = pacb->pmuB;
ae52e7f0 797 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
cdd3cb15 798 if (!arcmsr_hbb_wait_msgint_ready(pacb)) {
ae52e7f0
NC		 799 printk(KERN_ERR "arcmsr%d: can't set driver mode. \n", pacb->host->host_no);
800 return false;
cdd3cb15
NC		 801 }
802 return true;
ae52e7f0
NC		 803}
804
1c57e86d
EC		 805static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
806{
1c57e86d
EC		 807 struct scsi_cmnd *pcmd = ccb->pcmd;
808
deff2627 809 scsi_dma_unmap(pcmd);
cdd3cb15 810}
1c57e86d 811
ae52e7f0 812static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
1c57e86d
EC		 813{
814 struct AdapterControlBlock *acb = ccb->acb;
815 struct scsi_cmnd *pcmd = ccb->pcmd;
ae52e7f0 816 unsigned long flags;
ae52e7f0 817 atomic_dec(&acb->ccboutstandingcount);
1c57e86d 818 arcmsr_pci_unmap_dma(ccb);
1c57e86d 819 ccb->startdone = ARCMSR_CCB_DONE;
ae52e7f0 820 spin_lock_irqsave(&acb->ccblist_lock, flags);
1c57e86d 821 list_add_tail(&ccb->list, &acb->ccb_free_list);
ae52e7f0 822 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 823 pcmd->scsi_done(pcmd);
824}
825
1a4f550a
NC		 826static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
827{
828
829 struct scsi_cmnd *pcmd = ccb->pcmd;
830 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
1a4f550a
NC		 831 pcmd->result = DID_OK << 16;
832 if (sensebuffer) {
833 int sense_data_length =
b80ca4f7
FT		 834 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
835 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
836 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
1a4f550a
NC		 837 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
838 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
839 sensebuffer->Valid = 1;
840 }
841}
842
843static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
844{
845 u32 orig_mask = 0;
cdd3cb15 846 switch (acb->adapter_type) {
1a4f550a 847 case ACB_ADAPTER_TYPE_A : {
80da1adb 848 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 849 orig_mask = readl(&reg->outbound_intmask);
1a4f550a
NC		 850 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
851 &reg->outbound_intmask);
852 }
853 break;
1a4f550a 854 case ACB_ADAPTER_TYPE_B : {
80da1adb 855 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0
NC		 856 orig_mask = readl(reg->iop2drv_doorbell_mask);
857 writel(0, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 858 }
859 break;
cdd3cb15
NC		 860 case ACB_ADAPTER_TYPE_C:{
861 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
862 /* disable all outbound interrupt */
863 orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
864 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
865 }
866 break;
1a4f550a
NC		 867 }
868 return orig_mask;
869}
870
cdd3cb15
NC		 871static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
872 struct CommandControlBlock *ccb, bool error)
1a4f550a 873{
1a4f550a
NC		 874 uint8_t id, lun;
875 id = ccb->pcmd->device->id;
876 lun = ccb->pcmd->device->lun;
cdd3cb15 877 if (!error) {
1a4f550a
NC		 878 if (acb->devstate[id][lun] == ARECA_RAID_GONE)
879 acb->devstate[id][lun] = ARECA_RAID_GOOD;
7968f194
JL		 880 ccb->pcmd->result = DID_OK << 16;
881 arcmsr_ccb_complete(ccb);
cdd3cb15 882 }else{
1a4f550a
NC		 883 switch (ccb->arcmsr_cdb.DeviceStatus) {
884 case ARCMSR_DEV_SELECT_TIMEOUT: {
885 acb->devstate[id][lun] = ARECA_RAID_GONE;
886 ccb->pcmd->result = DID_NO_CONNECT << 16;
ae52e7f0 887 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 888 }
889 break;
890
891 case ARCMSR_DEV_ABORTED:
892
893 case ARCMSR_DEV_INIT_FAIL: {
894 acb->devstate[id][lun] = ARECA_RAID_GONE;
895 ccb->pcmd->result = DID_BAD_TARGET << 16;
ae52e7f0 896 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 897 }
898 break;
899
900 case ARCMSR_DEV_CHECK_CONDITION: {
901 acb->devstate[id][lun] = ARECA_RAID_GOOD;
902 arcmsr_report_sense_info(ccb);
ae52e7f0 903 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 904 }
905 break;
906
907 default:
cdd3cb15
NC		 908 printk(KERN_NOTICE
909 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
910 but got unknown DeviceStatus = 0x%x \n"
911 , acb->host->host_no
912 , id
913 , lun
914 , ccb->arcmsr_cdb.DeviceStatus);
915 acb->devstate[id][lun] = ARECA_RAID_GONE;
916 ccb->pcmd->result = DID_NO_CONNECT << 16;
917 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 918 break;
919 }
920 }
921}
922
cdd3cb15 923static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
1a4f550a
NC		 924
925{
ae52e7f0 926 int id, lun;
cdd3cb15
NC		 927 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
928 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
929 struct scsi_cmnd *abortcmd = pCCB->pcmd;
1a4f550a 930 if (abortcmd) {
ae52e7f0 931 id = abortcmd->device->id;
cdd3cb15 932 lun = abortcmd->device->lun;
1a4f550a 933 abortcmd->result |= DID_ABORT << 16;
cdd3cb15
NC		 934 arcmsr_ccb_complete(pCCB);
935 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
936 acb->host->host_no, pCCB);
1a4f550a 937 }
cdd3cb15 938 return;
1a4f550a
NC		 939 }
940 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
941 done acb = '0x%p'"
942 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
943 " ccboutstandingcount = %d \n"
944 , acb->host->host_no
945 , acb
cdd3cb15
NC		 946 , pCCB
947 , pCCB->acb
948 , pCCB->startdone
1a4f550a 949 , atomic_read(&acb->ccboutstandingcount));
cdd3cb15 950 return;
1a4f550a 951 }
cdd3cb15 952 arcmsr_report_ccb_state(acb, pCCB, error);
1a4f550a
NC		 953}
954
955static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
956{
957 int i = 0;
958 uint32_t flag_ccb;
cdd3cb15
NC		 959 struct ARCMSR_CDB *pARCMSR_CDB;
960 bool error;
961 struct CommandControlBlock *pCCB;
1a4f550a
NC		 962 switch (acb->adapter_type) {
963
964 case ACB_ADAPTER_TYPE_A: {
80da1adb 965 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 966 uint32_t outbound_intstatus;
80da1adb 967 outbound_intstatus = readl(&reg->outbound_intstatus) &
1a4f550a
NC		 968 acb->outbound_int_enable;
969 /*clear and abort all outbound posted Q*/
970 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
cdd3cb15 971 while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
1a4f550a 972 && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
cdd3cb15
NC		 973 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
974 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
975 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
976 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 977 }
978 }
979 break;
980
981 case ACB_ADAPTER_TYPE_B: {
80da1adb 982 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 983 /*clear all outbound posted Q*/
cdd3cb15 984 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, &reg->iop2drv_doorbell); /* clear doorbell interrupt */
1a4f550a
NC		 985 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
986 if ((flag_ccb = readl(&reg->done_qbuffer[i])) != 0) {
987 writel(0, &reg->done_qbuffer[i]);
cdd3cb15
NC		 988 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
989 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
990 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
991 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a 992 }
cdd3cb15 993 reg->post_qbuffer[i] = 0;
1a4f550a
NC		 994 }
995 reg->doneq_index = 0;
996 reg->postq_index = 0;
997 }
998 break;
cdd3cb15
NC		 999 case ACB_ADAPTER_TYPE_C: {
1000 struct MessageUnit_C *reg = acb->pmuC;
1001 struct ARCMSR_CDB *pARCMSR_CDB;
1002 uint32_t flag_ccb, ccb_cdb_phy;
1003 bool error;
1004 struct CommandControlBlock *pCCB;
1005 while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
1006 /*need to do*/
1007 flag_ccb = readl(&reg->outbound_queueport_low);
1008 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
1009 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/
1010 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1011 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
1012 arcmsr_drain_donequeue(acb, pCCB, error);
1013 }
1014 }
1a4f550a
NC		 1015 }
1016}
1c57e86d
EC		 1017static void arcmsr_remove(struct pci_dev *pdev)
1018{
1019 struct Scsi_Host *host = pci_get_drvdata(pdev);
1020 struct AdapterControlBlock *acb =
1021 (struct AdapterControlBlock *) host->hostdata;
1c57e86d 1022 int poll_count = 0;
1c57e86d
EC		 1023 arcmsr_free_sysfs_attr(acb);
1024 scsi_remove_host(host);
a684b8da 1025 flush_work_sync(&acb->arcmsr_do_message_isr_bh);
36b83ded
NC		 1026 del_timer_sync(&acb->eternal_timer);
1027 arcmsr_disable_outbound_ints(acb);
1c57e86d 1028 arcmsr_stop_adapter_bgrb(acb);
cdd3cb15 1029 arcmsr_flush_adapter_cache(acb);
1c57e86d
EC		 1030 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
1031 acb->acb_flags &= ~ACB_F_IOP_INITED;
1032
cdd3cb15 1033 for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++){
1c57e86d
EC		 1034 if (!atomic_read(&acb->ccboutstandingcount))
1035 break;
1a4f550a 1036 arcmsr_interrupt(acb);/* FIXME: need spinlock */
1c57e86d
EC		 1037 msleep(25);
1038 }
1039
1040 if (atomic_read(&acb->ccboutstandingcount)) {
1041 int i;
1042
1043 arcmsr_abort_allcmd(acb);
1a4f550a 1044 arcmsr_done4abort_postqueue(acb);
1c57e86d
EC		 1045 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
1046 struct CommandControlBlock *ccb = acb->pccb_pool[i];
1047 if (ccb->startdone == ARCMSR_CCB_START) {
1048 ccb->startdone = ARCMSR_CCB_ABORTED;
1049 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 1050 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 1051 }
1052 }
1053 }
1c57e86d 1054 free_irq(pdev->irq, acb);
1c57e86d 1055 arcmsr_free_ccb_pool(acb);
cdd3cb15
NC		 1056 arcmsr_free_hbb_mu(acb);
1057 arcmsr_unmap_pciregion(acb);
1c57e86d 1058 pci_release_regions(pdev);
cdd3cb15 1059 scsi_host_put(host);
1c57e86d
EC		 1060 pci_disable_device(pdev);
1061 pci_set_drvdata(pdev, NULL);
1062}
1063
1064static void arcmsr_shutdown(struct pci_dev *pdev)
1065{
1066 struct Scsi_Host *host = pci_get_drvdata(pdev);
1067 struct AdapterControlBlock *acb =
1068 (struct AdapterControlBlock *)host->hostdata;
36b83ded
NC		 1069 del_timer_sync(&acb->eternal_timer);
1070 arcmsr_disable_outbound_ints(acb);
a684b8da 1071 flush_work_sync(&acb->arcmsr_do_message_isr_bh);
1c57e86d
EC		 1072 arcmsr_stop_adapter_bgrb(acb);
1073 arcmsr_flush_adapter_cache(acb);
1074}
1075
1076static int arcmsr_module_init(void)
1077{
1078 int error = 0;
1c57e86d
EC		 1079 error = pci_register_driver(&arcmsr_pci_driver);
1080 return error;
1081}
1082
1083static void arcmsr_module_exit(void)
1084{
1085 pci_unregister_driver(&arcmsr_pci_driver);
1086}
1087module_init(arcmsr_module_init);
1088module_exit(arcmsr_module_exit);
1089
36b83ded 1090static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
1a4f550a 1091 u32 intmask_org)
1c57e86d 1092{
1c57e86d 1093 u32 mask;
1a4f550a 1094 switch (acb->adapter_type) {
1c57e86d 1095
cdd3cb15 1096 case ACB_ADAPTER_TYPE_A: {
80da1adb 1097 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 1098 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
36b83ded
NC		 1099 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
1100 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
1a4f550a
NC		 1101 writel(mask, &reg->outbound_intmask);
1102 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
1103 }
1104 break;
1c57e86d 1105
cdd3cb15 1106 case ACB_ADAPTER_TYPE_B: {
80da1adb 1107 struct MessageUnit_B *reg = acb->pmuB;
36b83ded
NC		 1108 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
1109 ARCMSR_IOP2DRV_DATA_READ_OK |
1110 ARCMSR_IOP2DRV_CDB_DONE |
1111 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
ae52e7f0 1112 writel(mask, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 1113 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
1114 }
cdd3cb15
NC		 1115 break;
1116 case ACB_ADAPTER_TYPE_C: {
1117 struct MessageUnit_C *reg = acb->pmuC;
1118 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
1119 writel(intmask_org & mask, &reg->host_int_mask);
1120 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
1121 }
1c57e86d
EC		 1122 }
1123}
1124
76d78300 1125static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
1a4f550a 1126 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
1c57e86d 1127{
1a4f550a
NC		 1128 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1129 int8_t *psge = (int8_t *)&arcmsr_cdb->u;
80da1adb 1130 __le32 address_lo, address_hi;
1a4f550a 1131 int arccdbsize = 0x30;
ae52e7f0 1132 __le32 length = 0;
cdd3cb15 1133 int i;
ae52e7f0 1134 struct scatterlist *sg;
1a4f550a 1135 int nseg;
1c57e86d 1136 ccb->pcmd = pcmd;
1a4f550a 1137 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1c57e86d
EC		 1138 arcmsr_cdb->TargetID = pcmd->device->id;
1139 arcmsr_cdb->LUN = pcmd->device->lun;
1140 arcmsr_cdb->Function = 1;
ae52e7f0 1141 arcmsr_cdb->Context = 0;
1c57e86d 1142 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
deff2627
FT		 1143
1144 nseg = scsi_dma_map(pcmd);
cdd3cb15 1145 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
76d78300 1146 return FAILED;
cdd3cb15
NC		 1147 scsi_for_each_sg(pcmd, sg, nseg, i) {
1148 /* Get the physical address of the current data pointer */
1149 length = cpu_to_le32(sg_dma_len(sg));
1150 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
1151 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
1152 if (address_hi == 0) {
1153 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1154
1155 pdma_sg->address = address_lo;
1156 pdma_sg->length = length;
1157 psge += sizeof (struct SG32ENTRY);
1158 arccdbsize += sizeof (struct SG32ENTRY);
1159 } else {
1160 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1c57e86d 1161
cdd3cb15
NC		 1162 pdma_sg->addresshigh = address_hi;
1163 pdma_sg->address = address_lo;
1164 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
1165 psge += sizeof (struct SG64ENTRY);
1166 arccdbsize += sizeof (struct SG64ENTRY);
1c57e86d 1167 }
cdd3cb15
NC		 1168 }
1169 arcmsr_cdb->sgcount = (uint8_t)nseg;
1170 arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
ae52e7f0 1171 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
cdd3cb15
NC		 1172 if ( arccdbsize > 256)
1173 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
c32e061f 1174 if (pcmd->sc_data_direction == DMA_TO_DEVICE)
1c57e86d 1175 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
cdd3cb15 1176 ccb->arc_cdb_size = arccdbsize;
76d78300 1177 return SUCCESS;
1c57e86d
EC		 1178}
1179
1180static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
1181{
cdd3cb15 1182 uint32_t cdb_phyaddr_pattern = ccb->cdb_phyaddr_pattern;
1c57e86d 1183 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1c57e86d
EC		 1184 atomic_inc(&acb->ccboutstandingcount);
1185 ccb->startdone = ARCMSR_CCB_START;
1a4f550a
NC		 1186 switch (acb->adapter_type) {
1187 case ACB_ADAPTER_TYPE_A: {
80da1adb 1188 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1189
1190 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
cdd3cb15 1191 writel(cdb_phyaddr_pattern | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
1c57e86d 1192 &reg->inbound_queueport);
1a4f550a 1193 else {
cdd3cb15 1194 writel(cdb_phyaddr_pattern, &reg->inbound_queueport);
1a4f550a
NC		 1195 }
1196 }
1197 break;
1c57e86d 1198
1a4f550a 1199 case ACB_ADAPTER_TYPE_B: {
80da1adb 1200 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1201 uint32_t ending_index, index = reg->postq_index;
1c57e86d 1202
1a4f550a
NC		 1203 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
1204 writel(0, &reg->post_qbuffer[ending_index]);
1205 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
cdd3cb15 1206 writel(cdb_phyaddr_pattern | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,\
1a4f550a 1207 &reg->post_qbuffer[index]);
cdd3cb15
NC		 1208 } else {
1209 writel(cdb_phyaddr_pattern, &reg->post_qbuffer[index]);
1a4f550a
NC		 1210 }
1211 index++;
1212 index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
1213 reg->postq_index = index;
ae52e7f0 1214 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
1c57e86d 1215 }
1a4f550a 1216 break;
cdd3cb15
NC		 1217 case ACB_ADAPTER_TYPE_C: {
1218 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)acb->pmuC;
1219 uint32_t ccb_post_stamp, arc_cdb_size;
1220
1221 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
1222 ccb_post_stamp = (cdb_phyaddr_pattern | ((arc_cdb_size - 1) >> 6) | 1);
1223 if (acb->cdb_phyaddr_hi32) {
1224 writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high);
1225 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1226 } else {
1227 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1228 }
1229 }
1c57e86d
EC		 1230 }
1231}
1232
1a4f550a 1233static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1c57e86d 1234{
80da1adb 1235 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d
EC		 1236 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1237 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
cdd3cb15 1238 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 1239 printk(KERN_NOTICE
1240 "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1241 , acb->host->host_no);
1242 }
1243}
1244
1245static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1246{
80da1adb 1247 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1248 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
ae52e7f0 1249 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
1a4f550a 1250
cdd3cb15 1251 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1c57e86d
EC		 1252 printk(KERN_NOTICE
1253 "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1254 , acb->host->host_no);
1a4f550a
NC		 1255 }
1256}
1257
cdd3cb15
NC		 1258static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *pACB)
1259{
1260 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
1261 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1262 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
1263 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
1264 if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
1265 printk(KERN_NOTICE
1266 "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1267 , pACB->host->host_no);
1268 }
1269 return;
1270}
1a4f550a
NC		 1271static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1272{
1273 switch (acb->adapter_type) {
1274 case ACB_ADAPTER_TYPE_A: {
1275 arcmsr_stop_hba_bgrb(acb);
1276 }
1277 break;
1278
1279 case ACB_ADAPTER_TYPE_B: {
1280 arcmsr_stop_hbb_bgrb(acb);
1281 }
1282 break;
cdd3cb15
NC		 1283 case ACB_ADAPTER_TYPE_C: {
1284 arcmsr_stop_hbc_bgrb(acb);
1285 }
1a4f550a 1286 }
1c57e86d
EC		 1287}
1288
1289static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
1290{
cdd3cb15 1291 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
1c57e86d
EC		 1292}
1293
1a4f550a 1294void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1c57e86d 1295{
1a4f550a
NC		 1296 switch (acb->adapter_type) {
1297 case ACB_ADAPTER_TYPE_A: {
80da1adb 1298 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1299 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
1300 }
1301 break;
1c57e86d 1302
1a4f550a 1303 case ACB_ADAPTER_TYPE_B: {
80da1adb 1304 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1305 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1c57e86d 1306 }
1a4f550a 1307 break;
cdd3cb15
NC		 1308 case ACB_ADAPTER_TYPE_C: {
1309 struct MessageUnit_C __iomem *reg = acb->pmuC;
1310 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
1311 }
1c57e86d 1312 }
1a4f550a
NC		 1313}
1314
1315static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1316{
1317 switch (acb->adapter_type) {
1318 case ACB_ADAPTER_TYPE_A: {
80da1adb 1319 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 1320 /*
1a4f550a
NC		 1321 ** push inbound doorbell tell iop, driver data write ok
1322 ** and wait reply on next hwinterrupt for next Qbuffer post
1c57e86d 1323 */
1a4f550a
NC		 1324 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
1325 }
1326 break;
1327
1328 case ACB_ADAPTER_TYPE_B: {
80da1adb 1329 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 1330 /*
1331 ** push inbound doorbell tell iop, driver data write ok
1332 ** and wait reply on next hwinterrupt for next Qbuffer post
1333 */
ae52e7f0 1334 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
1a4f550a
NC		 1335 }
1336 break;
cdd3cb15
NC		 1337 case ACB_ADAPTER_TYPE_C: {
1338 struct MessageUnit_C __iomem *reg = acb->pmuC;
1339 /*
1340 ** push inbound doorbell tell iop, driver data write ok
1341 ** and wait reply on next hwinterrupt for next Qbuffer post
1342 */
1343 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
1344 }
1345 break;
1a4f550a
NC		 1346 }
1347}
1348
80da1adb 1349struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
1a4f550a 1350{
0c7eb2eb 1351 struct QBUFFER __iomem *qbuffer = NULL;
1a4f550a
NC		 1352 switch (acb->adapter_type) {
1353
1354 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 1355 struct MessageUnit_A __iomem *reg = acb->pmuA;
1356 qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
1a4f550a
NC		 1357 }
1358 break;
1359
1360 case ACB_ADAPTER_TYPE_B: {
80da1adb 1361 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1362 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1a4f550a
NC		 1363 }
1364 break;
cdd3cb15
NC		 1365 case ACB_ADAPTER_TYPE_C: {
1366 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)acb->pmuC;
1367 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
1368 }
1a4f550a
NC		 1369 }
1370 return qbuffer;
1371}
1372
80da1adb 1373static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
1a4f550a 1374{
0c7eb2eb 1375 struct QBUFFER __iomem *pqbuffer = NULL;
1a4f550a
NC		 1376 switch (acb->adapter_type) {
1377
1378 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 1379 struct MessageUnit_A __iomem *reg = acb->pmuA;
1380 pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
1a4f550a
NC		 1381 }
1382 break;
1383
1384 case ACB_ADAPTER_TYPE_B: {
80da1adb 1385 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1386 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
1a4f550a
NC		 1387 }
1388 break;
cdd3cb15
NC		 1389 case ACB_ADAPTER_TYPE_C: {
1390 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
1391 pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
1392 }
1393
1a4f550a
NC		 1394 }
1395 return pqbuffer;
1396}
1397
1398static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1399{
80da1adb 1400 struct QBUFFER __iomem *prbuffer;
1a4f550a 1401 struct QBUFFER *pQbuffer;
80da1adb 1402 uint8_t __iomem *iop_data;
1a4f550a 1403 int32_t my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex;
1a4f550a
NC		 1404 rqbuf_lastindex = acb->rqbuf_lastindex;
1405 rqbuf_firstindex = acb->rqbuf_firstindex;
1406 prbuffer = arcmsr_get_iop_rqbuffer(acb);
80da1adb 1407 iop_data = (uint8_t __iomem *)prbuffer->data;
1a4f550a 1408 iop_len = prbuffer->data_len;
cdd3cb15 1409 my_empty_len = (rqbuf_firstindex - rqbuf_lastindex - 1) & (ARCMSR_MAX_QBUFFER - 1);
1a4f550a
NC		 1410
1411 if (my_empty_len >= iop_len)
1412 {
1413 while (iop_len > 0) {
1414 pQbuffer = (struct QBUFFER *)&acb->rqbuffer[rqbuf_lastindex];
cdd3cb15 1415 memcpy(pQbuffer, iop_data, 1);
1a4f550a
NC		 1416 rqbuf_lastindex++;
1417 rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1418 iop_data++;
1419 iop_len--;
1420 }
1421 acb->rqbuf_lastindex = rqbuf_lastindex;
1422 arcmsr_iop_message_read(acb);
1423 }
1424
1425 else {
1426 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1427 }
1428}
1429
1430static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1431{
1432 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
1433 if (acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1434 uint8_t *pQbuffer;
80da1adb
AV		 1435 struct QBUFFER __iomem *pwbuffer;
1436 uint8_t __iomem *iop_data;
1a4f550a
NC		 1437 int32_t allxfer_len = 0;
1438
1439 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1440 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1441 iop_data = (uint8_t __iomem *)pwbuffer->data;
1442
1443 while ((acb->wqbuf_firstindex != acb->wqbuf_lastindex) && \
1444 (allxfer_len < 124)) {
1445 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1446 memcpy(iop_data, pQbuffer, 1);
1447 acb->wqbuf_firstindex++;
1448 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1449 iop_data++;
1450 allxfer_len++;
1451 }
1452 pwbuffer->data_len = allxfer_len;
1453
1454 arcmsr_iop_message_wrote(acb);
1455 }
1456
1457 if (acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1458 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1459 }
1460}
1461
1462static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1463{
1464 uint32_t outbound_doorbell;
80da1adb 1465 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1466 outbound_doorbell = readl(&reg->outbound_doorbell);
1467 writel(outbound_doorbell, &reg->outbound_doorbell);
1468 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1469 arcmsr_iop2drv_data_wrote_handle(acb);
1470 }
1471
cdd3cb15 1472 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1a4f550a
NC		 1473 arcmsr_iop2drv_data_read_handle(acb);
1474 }
1475}
cdd3cb15
NC		 1476static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *pACB)
1477{
1478 uint32_t outbound_doorbell;
1479 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
1480 /*
1481 *******************************************************************
1482 ** Maybe here we need to check wrqbuffer_lock is lock or not
1483 ** DOORBELL: din! don!
1484 ** check if there are any mail need to pack from firmware
1485 *******************************************************************
1486 */
1487 outbound_doorbell = readl(&reg->outbound_doorbell);
1488 writel(outbound_doorbell, &reg->outbound_doorbell_clear);/*clear interrupt*/
1489 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1490 arcmsr_iop2drv_data_wrote_handle(pACB);
1491 }
1492 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1493 arcmsr_iop2drv_data_read_handle(pACB);
1494 }
1495 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1496 arcmsr_hbc_message_isr(pACB); /* messenger of "driver to iop commands" */
1497 }
1498 return;
1499}
1a4f550a
NC		 1500static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1501{
1502 uint32_t flag_ccb;
80da1adb 1503 struct MessageUnit_A __iomem *reg = acb->pmuA;
cdd3cb15
NC		 1504 struct ARCMSR_CDB *pARCMSR_CDB;
1505 struct CommandControlBlock *pCCB;
1506 bool error;
1a4f550a 1507 while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
cdd3cb15
NC		 1508 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
1509 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1510 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1511 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 1512 }
1513}
1514
1515static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
1516{
1517 uint32_t index;
1518 uint32_t flag_ccb;
80da1adb 1519 struct MessageUnit_B *reg = acb->pmuB;
cdd3cb15
NC		 1520 struct ARCMSR_CDB *pARCMSR_CDB;
1521 struct CommandControlBlock *pCCB;
1522 bool error;
1a4f550a 1523 index = reg->doneq_index;
1a4f550a
NC		 1524 while ((flag_ccb = readl(&reg->done_qbuffer[index])) != 0) {
1525 writel(0, &reg->done_qbuffer[index]);
cdd3cb15
NC		 1526 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
1527 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1528 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1529 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 1530 index++;
1531 index %= ARCMSR_MAX_HBB_POSTQUEUE;
1532 reg->doneq_index = index;
1533 }
1534}
cdd3cb15
NC		 1535
1536static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
1537{
1538 struct MessageUnit_C *phbcmu;
1539 struct ARCMSR_CDB *arcmsr_cdb;
1540 struct CommandControlBlock *ccb;
1541 uint32_t flag_ccb, ccb_cdb_phy, throttling = 0;
1542 int error;
1543
1544 phbcmu = (struct MessageUnit_C *)acb->pmuC;
1545 /* areca cdb command done */
1546 /* Use correct offset and size for syncing */
1547
1548 while (readl(&phbcmu->host_int_status) &
1549 ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR){
1550 /* check if command done with no error*/
1551 flag_ccb = readl(&phbcmu->outbound_queueport_low);
1552 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);/*frame must be 32 bytes aligned*/
1553 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
1554 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
1555 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
1556 /* check if command done with no error */
1557 arcmsr_drain_donequeue(acb, ccb, error);
1558 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1559 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING, &phbcmu->inbound_doorbell);
1560 break;
1561 }
1562 throttling++;
1563 }
1564}
36b83ded
NC		 1565/*
1566**********************************************************************************
1567** Handle a message interrupt
1568**
cdd3cb15 1569** The only message interrupt we expect is in response to a query for the current adapter config.
36b83ded
NC		 1570** We want this in order to compare the drivemap so that we can detect newly-attached drives.
1571**********************************************************************************
1572*/
1573static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb)
1574{
1575 struct MessageUnit_A *reg = acb->pmuA;
36b83ded
NC		 1576 /*clear interrupt and message state*/
1577 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
1578 schedule_work(&acb->arcmsr_do_message_isr_bh);
1579}
1580static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb)
1581{
1582 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1583
36b83ded 1584 /*clear interrupt and message state*/
ae52e7f0 1585 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
36b83ded
NC		 1586 schedule_work(&acb->arcmsr_do_message_isr_bh);
1587}
cdd3cb15
NC		 1588/*
1589**********************************************************************************
1590** Handle a message interrupt
1591**
1592** The only message interrupt we expect is in response to a query for the
1593** current adapter config.
1594** We want this in order to compare the drivemap so that we can detect newly-attached drives.
1595**********************************************************************************
1596*/
1597static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb)
1598{
1599 struct MessageUnit_C *reg = acb->pmuC;
1600 /*clear interrupt and message state*/
1601 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
1602 schedule_work(&acb->arcmsr_do_message_isr_bh);
1603}
1604
1a4f550a
NC		 1605static int arcmsr_handle_hba_isr(struct AdapterControlBlock *acb)
1606{
1607 uint32_t outbound_intstatus;
80da1adb 1608 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 1609 outbound_intstatus = readl(&reg->outbound_intstatus) &
cdd3cb15 1610 acb->outbound_int_enable;
1a4f550a
NC		 1611 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) {
1612 return 1;
1613 }
1614 writel(outbound_intstatus, &reg->outbound_intstatus);
1615 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
1616 arcmsr_hba_doorbell_isr(acb);
1617 }
1618 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
1619 arcmsr_hba_postqueue_isr(acb);
1620 }
cdd3cb15 1621 if(outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
36b83ded
NC		 1622 /* messenger of "driver to iop commands" */
1623 arcmsr_hba_message_isr(acb);
1624 }
1a4f550a
NC		 1625 return 0;
1626}
1627
1628static int arcmsr_handle_hbb_isr(struct AdapterControlBlock *acb)
1629{
1630 uint32_t outbound_doorbell;
80da1adb 1631 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1632 outbound_doorbell = readl(reg->iop2drv_doorbell) &
cdd3cb15 1633 acb->outbound_int_enable;
1a4f550a
NC		 1634 if (!outbound_doorbell)
1635 return 1;
1636
ae52e7f0 1637 writel(~outbound_doorbell, reg->iop2drv_doorbell);
36b83ded
NC		 1638 /*in case the last action of doorbell interrupt clearance is cached,
1639 this action can push HW to write down the clear bit*/
ae52e7f0
NC		 1640 readl(reg->iop2drv_doorbell);
1641 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
cdd3cb15 1642 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
1a4f550a
NC		 1643 arcmsr_iop2drv_data_wrote_handle(acb);
1644 }
1645 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
1646 arcmsr_iop2drv_data_read_handle(acb);
1647 }
1648 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
1649 arcmsr_hbb_postqueue_isr(acb);
1650 }
cdd3cb15 1651 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
36b83ded
NC		 1652 /* messenger of "driver to iop commands" */
1653 arcmsr_hbb_message_isr(acb);
1654 }
1a4f550a
NC		 1655 return 0;
1656}
1657
cdd3cb15
NC		 1658static int arcmsr_handle_hbc_isr(struct AdapterControlBlock *pACB)
1659{
1660 uint32_t host_interrupt_status;
1661 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
1662 /*
1663 *********************************************
1664 ** check outbound intstatus
1665 *********************************************
1666 */
1667 host_interrupt_status = readl(&phbcmu->host_int_status);
1668 if (!host_interrupt_status) {
1669 /*it must be share irq*/
1670 return 1;
1671 }
1672 /* MU ioctl transfer doorbell interrupts*/
1673 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
1674 arcmsr_hbc_doorbell_isr(pACB); /* messenger of "ioctl message read write" */
1675 }
1676 /* MU post queue interrupts*/
1677 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
1678 arcmsr_hbc_postqueue_isr(pACB); /* messenger of "scsi commands" */
1679 }
1680 return 0;
1681}
1a4f550a
NC		 1682static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
1683{
1684 switch (acb->adapter_type) {
1685 case ACB_ADAPTER_TYPE_A: {
1686 if (arcmsr_handle_hba_isr(acb)) {
1687 return IRQ_NONE;
1688 }
1689 }
1690 break;
1691
1692 case ACB_ADAPTER_TYPE_B: {
1693 if (arcmsr_handle_hbb_isr(acb)) {
1694 return IRQ_NONE;
1695 }
1696 }
1697 break;
cdd3cb15
NC		 1698 case ACB_ADAPTER_TYPE_C: {
1699 if (arcmsr_handle_hbc_isr(acb)) {
1700 return IRQ_NONE;
1701 }
1702 }
1c57e86d 1703 }
1c57e86d
EC		 1704 return IRQ_HANDLED;
1705}
1706
1707static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
1708{
1709 if (acb) {
1710 /* stop adapter background rebuild */
1711 if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
1a4f550a 1712 uint32_t intmask_org;
1c57e86d 1713 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1a4f550a 1714 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d
EC		 1715 arcmsr_stop_adapter_bgrb(acb);
1716 arcmsr_flush_adapter_cache(acb);
1a4f550a
NC		 1717 arcmsr_enable_outbound_ints(acb, intmask_org);
1718 }
1719 }
1720}
1721
1722void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb)
1723{
1724 int32_t wqbuf_firstindex, wqbuf_lastindex;
1725 uint8_t *pQbuffer;
80da1adb
AV		 1726 struct QBUFFER __iomem *pwbuffer;
1727 uint8_t __iomem *iop_data;
1a4f550a 1728 int32_t allxfer_len = 0;
1a4f550a
NC		 1729 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1730 iop_data = (uint8_t __iomem *)pwbuffer->data;
1731 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
1732 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1733 wqbuf_firstindex = acb->wqbuf_firstindex;
1734 wqbuf_lastindex = acb->wqbuf_lastindex;
1735 while ((wqbuf_firstindex != wqbuf_lastindex) && (allxfer_len < 124)) {
1736 pQbuffer = &acb->wqbuffer[wqbuf_firstindex];
1737 memcpy(iop_data, pQbuffer, 1);
1738 wqbuf_firstindex++;
1739 wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1740 iop_data++;
1741 allxfer_len++;
1c57e86d 1742 }
1a4f550a
NC		 1743 acb->wqbuf_firstindex = wqbuf_firstindex;
1744 pwbuffer->data_len = allxfer_len;
1745 arcmsr_iop_message_wrote(acb);
1c57e86d
EC		 1746 }
1747}
1748
36b83ded 1749static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
1a4f550a 1750 struct scsi_cmnd *cmd)
1c57e86d 1751{
1c57e86d
EC		 1752 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
1753 int retvalue = 0, transfer_len = 0;
1754 char *buffer;
deff2627 1755 struct scatterlist *sg;
1c57e86d
EC		 1756 uint32_t controlcode = (uint32_t ) cmd->cmnd[5] << 24 |
1757 (uint32_t ) cmd->cmnd[6] << 16 |
1758 (uint32_t ) cmd->cmnd[7] << 8 |
1759 (uint32_t ) cmd->cmnd[8];
1a4f550a 1760 /* 4 bytes: Areca io control code */
deff2627 1761 sg = scsi_sglist(cmd);
45711f1a 1762 buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
deff2627
FT		 1763 if (scsi_sg_count(cmd) > 1) {
1764 retvalue = ARCMSR_MESSAGE_FAIL;
1765 goto message_out;
1c57e86d 1766 }
deff2627
FT		 1767 transfer_len += sg->length;
1768
1c57e86d
EC		 1769 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
1770 retvalue = ARCMSR_MESSAGE_FAIL;
1771 goto message_out;
1772 }
1773 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
1774 switch(controlcode) {
1a4f550a 1775
1c57e86d 1776 case ARCMSR_MESSAGE_READ_RQBUFFER: {
69e562c2 1777 unsigned char *ver_addr;
1a4f550a
NC		 1778 uint8_t *pQbuffer, *ptmpQbuffer;
1779 int32_t allxfer_len = 0;
1780
69e562c2
DD		 1781 ver_addr = kmalloc(1032, GFP_ATOMIC);
1782 if (!ver_addr) {
1a4f550a
NC		 1783 retvalue = ARCMSR_MESSAGE_FAIL;
1784 goto message_out;
1785 }
cdd3cb15 1786
69e562c2 1787 ptmpQbuffer = ver_addr;
1a4f550a
NC		 1788 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
1789 && (allxfer_len < 1031)) {
1790 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
1791 memcpy(ptmpQbuffer, pQbuffer, 1);
1792 acb->rqbuf_firstindex++;
1793 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1794 ptmpQbuffer++;
1795 allxfer_len++;
1796 }
1797 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1c57e86d 1798
80da1adb
AV		 1799 struct QBUFFER __iomem *prbuffer;
1800 uint8_t __iomem *iop_data;
1a4f550a
NC		 1801 int32_t iop_len;
1802
1803 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1804 prbuffer = arcmsr_get_iop_rqbuffer(acb);
80da1adb 1805 iop_data = prbuffer->data;
1a4f550a
NC		 1806 iop_len = readl(&prbuffer->data_len);
1807 while (iop_len > 0) {
1808 acb->rqbuffer[acb->rqbuf_lastindex] = readb(iop_data);
1809 acb->rqbuf_lastindex++;
1810 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1811 iop_data++;
1812 iop_len--;
1c57e86d 1813 }
1a4f550a
NC		 1814 arcmsr_iop_message_read(acb);
1815 }
69e562c2 1816 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr, allxfer_len);
1a4f550a 1817 pcmdmessagefld->cmdmessage.Length = allxfer_len;
cdd3cb15 1818 if(acb->fw_flag == FW_DEADLOCK) {
ae52e7f0 1819 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15
NC		 1820 }else{
1821 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
ae52e7f0 1822 }
69e562c2 1823 kfree(ver_addr);
1c57e86d
EC		 1824 }
1825 break;
1c57e86d 1826
1a4f550a 1827 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
69e562c2 1828 unsigned char *ver_addr;
1a4f550a
NC		 1829 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
1830 uint8_t *pQbuffer, *ptmpuserbuffer;
1831
69e562c2
DD		 1832 ver_addr = kmalloc(1032, GFP_ATOMIC);
1833 if (!ver_addr) {
1a4f550a
NC		 1834 retvalue = ARCMSR_MESSAGE_FAIL;
1835 goto message_out;
1836 }
cdd3cb15
NC		 1837 if(acb->fw_flag == FW_DEADLOCK) {
1838 pcmdmessagefld->cmdmessage.ReturnCode =
36b83ded 1839 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15
NC		 1840 }else{
1841 pcmdmessagefld->cmdmessage.ReturnCode =
ae52e7f0 1842 ARCMSR_MESSAGE_RETURNCODE_OK;
36b83ded 1843 }
69e562c2 1844 ptmpuserbuffer = ver_addr;
1a4f550a
NC		 1845 user_len = pcmdmessagefld->cmdmessage.Length;
1846 memcpy(ptmpuserbuffer, pcmdmessagefld->messagedatabuffer, user_len);
1847 wqbuf_lastindex = acb->wqbuf_lastindex;
1848 wqbuf_firstindex = acb->wqbuf_firstindex;
1849 if (wqbuf_lastindex != wqbuf_firstindex) {
1850 struct SENSE_DATA *sensebuffer =
1851 (struct SENSE_DATA *)cmd->sense_buffer;
1852 arcmsr_post_ioctldata2iop(acb);
1853 /* has error report sensedata */
1854 sensebuffer->ErrorCode = 0x70;
1855 sensebuffer->SenseKey = ILLEGAL_REQUEST;
1856 sensebuffer->AdditionalSenseLength = 0x0A;
1857 sensebuffer->AdditionalSenseCode = 0x20;
1858 sensebuffer->Valid = 1;
1859 retvalue = ARCMSR_MESSAGE_FAIL;
1860 } else {
1861 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
1862 &(ARCMSR_MAX_QBUFFER - 1);
1863 if (my_empty_len >= user_len) {
1864 while (user_len > 0) {
1865 pQbuffer =
1866 &acb->wqbuffer[acb->wqbuf_lastindex];
1867 memcpy(pQbuffer, ptmpuserbuffer, 1);
1868 acb->wqbuf_lastindex++;
1869 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1870 ptmpuserbuffer++;
1871 user_len--;
1872 }
1873 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
1874 acb->acb_flags &=
1875 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
1876 arcmsr_post_ioctldata2iop(acb);
1877 }
1878 } else {
1879 /* has error report sensedata */
1c57e86d
EC		 1880 struct SENSE_DATA *sensebuffer =
1881 (struct SENSE_DATA *)cmd->sense_buffer;
1c57e86d
EC		 1882 sensebuffer->ErrorCode = 0x70;
1883 sensebuffer->SenseKey = ILLEGAL_REQUEST;
1884 sensebuffer->AdditionalSenseLength = 0x0A;
1885 sensebuffer->AdditionalSenseCode = 0x20;
1886 sensebuffer->Valid = 1;
1887 retvalue = ARCMSR_MESSAGE_FAIL;
1a4f550a 1888 }
1c57e86d 1889 }
69e562c2 1890 kfree(ver_addr);
1c57e86d
EC		 1891 }
1892 break;
1a4f550a 1893
1c57e86d 1894 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
1a4f550a 1895 uint8_t *pQbuffer = acb->rqbuffer;
1a4f550a
NC		 1896 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1897 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1898 arcmsr_iop_message_read(acb);
1899 }
1900 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
1901 acb->rqbuf_firstindex = 0;
1902 acb->rqbuf_lastindex = 0;
1903 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
cdd3cb15 1904 if(acb->fw_flag == FW_DEADLOCK) {
ae52e7f0
NC		 1905 pcmdmessagefld->cmdmessage.ReturnCode =
1906 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1907 }else{
ae52e7f0
NC		 1908 pcmdmessagefld->cmdmessage.ReturnCode =
1909 ARCMSR_MESSAGE_RETURNCODE_OK;
1910 }
1c57e86d
EC		 1911 }
1912 break;
1a4f550a 1913
1c57e86d 1914 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
1a4f550a 1915 uint8_t *pQbuffer = acb->wqbuffer;
cdd3cb15 1916 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1917 pcmdmessagefld->cmdmessage.ReturnCode =
1918 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1919 }else{
ae52e7f0
NC		 1920 pcmdmessagefld->cmdmessage.ReturnCode =
1921 ARCMSR_MESSAGE_RETURNCODE_OK;
36b83ded 1922 }
1c57e86d 1923
1a4f550a
NC		 1924 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1925 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1926 arcmsr_iop_message_read(acb);
1927 }
1928 acb->acb_flags |=
1929 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
1930 ACB_F_MESSAGE_WQBUFFER_READED);
1931 acb->wqbuf_firstindex = 0;
1932 acb->wqbuf_lastindex = 0;
1933 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
1c57e86d
EC		 1934 }
1935 break;
1a4f550a 1936
1c57e86d 1937 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
1a4f550a 1938 uint8_t *pQbuffer;
1c57e86d 1939
1a4f550a
NC		 1940 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1941 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1942 arcmsr_iop_message_read(acb);
1943 }
1944 acb->acb_flags |=
1945 (ACB_F_MESSAGE_WQBUFFER_CLEARED
1946 | ACB_F_MESSAGE_RQBUFFER_CLEARED
1947 | ACB_F_MESSAGE_WQBUFFER_READED);
1948 acb->rqbuf_firstindex = 0;
1949 acb->rqbuf_lastindex = 0;
1950 acb->wqbuf_firstindex = 0;
1951 acb->wqbuf_lastindex = 0;
1952 pQbuffer = acb->rqbuffer;
1953 memset(pQbuffer, 0, sizeof(struct QBUFFER));
1954 pQbuffer = acb->wqbuffer;
1955 memset(pQbuffer, 0, sizeof(struct QBUFFER));
cdd3cb15 1956 if(acb->fw_flag == FW_DEADLOCK) {
ae52e7f0
NC		 1957 pcmdmessagefld->cmdmessage.ReturnCode =
1958 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1959 }else{
ae52e7f0
NC		 1960 pcmdmessagefld->cmdmessage.ReturnCode =
1961 ARCMSR_MESSAGE_RETURNCODE_OK;
1962 }
1c57e86d
EC		 1963 }
1964 break;
1a4f550a 1965
1c57e86d 1966 case ARCMSR_MESSAGE_RETURN_CODE_3F: {
cdd3cb15 1967 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1968 pcmdmessagefld->cmdmessage.ReturnCode =
1969 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1970 }else{
ae52e7f0
NC		 1971 pcmdmessagefld->cmdmessage.ReturnCode =
1972 ARCMSR_MESSAGE_RETURNCODE_3F;
1c57e86d
EC		 1973 }
1974 break;
ae52e7f0 1975 }
1c57e86d 1976 case ARCMSR_MESSAGE_SAY_HELLO: {
1a4f550a 1977 int8_t *hello_string = "Hello! I am ARCMSR";
cdd3cb15 1978 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1979 pcmdmessagefld->cmdmessage.ReturnCode =
1980 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1981 }else{
ae52e7f0
NC		 1982 pcmdmessagefld->cmdmessage.ReturnCode =
1983 ARCMSR_MESSAGE_RETURNCODE_OK;
36b83ded 1984 }
1a4f550a
NC		 1985 memcpy(pcmdmessagefld->messagedatabuffer, hello_string
1986 , (int16_t)strlen(hello_string));
1c57e86d
EC		 1987 }
1988 break;
1a4f550a 1989
1c57e86d 1990 case ARCMSR_MESSAGE_SAY_GOODBYE:
cdd3cb15 1991 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1992 pcmdmessagefld->cmdmessage.ReturnCode =
1993 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
36b83ded 1994 }
1c57e86d
EC		 1995 arcmsr_iop_parking(acb);
1996 break;
1a4f550a 1997
1c57e86d 1998 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
cdd3cb15 1999 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 2000 pcmdmessagefld->cmdmessage.ReturnCode =
2001 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
36b83ded 2002 }
1c57e86d
EC		 2003 arcmsr_flush_adapter_cache(acb);
2004 break;
1a4f550a 2005
1c57e86d
EC		 2006 default:
2007 retvalue = ARCMSR_MESSAGE_FAIL;
2008 }
1a4f550a 2009 message_out:
deff2627
FT		 2010 sg = scsi_sglist(cmd);
2011 kunmap_atomic(buffer - sg->offset, KM_IRQ0);
1c57e86d
EC		 2012 return retvalue;
2013}
2014
2015static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
2016{
2017 struct list_head *head = &acb->ccb_free_list;
2018 struct CommandControlBlock *ccb = NULL;
ae52e7f0
NC		 2019 unsigned long flags;
2020 spin_lock_irqsave(&acb->ccblist_lock, flags);
1c57e86d
EC		 2021 if (!list_empty(head)) {
2022 ccb = list_entry(head->next, struct CommandControlBlock, list);
ae52e7f0 2023 list_del_init(&ccb->list);
cdd3cb15 2024 }else{
ae52e7f0
NC		 2025 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
2026 return 0;
1c57e86d 2027 }
ae52e7f0 2028 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 2029 return ccb;
2030}
2031
2032static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2033 struct scsi_cmnd *cmd)
2034{
2035 switch (cmd->cmnd[0]) {
2036 case INQUIRY: {
2037 unsigned char inqdata[36];
2038 char *buffer;
deff2627 2039 struct scatterlist *sg;
1c57e86d
EC		 2040
2041 if (cmd->device->lun) {
2042 cmd->result = (DID_TIME_OUT << 16);
2043 cmd->scsi_done(cmd);
2044 return;
2045 }
2046 inqdata[0] = TYPE_PROCESSOR;
2047 /* Periph Qualifier & Periph Dev Type */
2048 inqdata[1] = 0;
2049 /* rem media bit & Dev Type Modifier */
2050 inqdata[2] = 0;
a1f6e021 2051 /* ISO, ECMA, & ANSI versions */
1c57e86d
EC		 2052 inqdata[4] = 31;
2053 /* length of additional data */
2054 strncpy(&inqdata[8], "Areca ", 8);
2055 /* Vendor Identification */
2056 strncpy(&inqdata[16], "RAID controller ", 16);
2057 /* Product Identification */
2058 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
1c57e86d 2059
deff2627 2060 sg = scsi_sglist(cmd);
45711f1a 2061 buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
deff2627 2062
1c57e86d 2063 memcpy(buffer, inqdata, sizeof(inqdata));
deff2627
FT		 2064 sg = scsi_sglist(cmd);
2065 kunmap_atomic(buffer - sg->offset, KM_IRQ0);
1c57e86d 2066
1c57e86d
EC		 2067 cmd->scsi_done(cmd);
2068 }
2069 break;
2070 case WRITE_BUFFER:
2071 case READ_BUFFER: {
2072 if (arcmsr_iop_message_xfer(acb, cmd))
2073 cmd->result = (DID_ERROR << 16);
2074 cmd->scsi_done(cmd);
2075 }
2076 break;
2077 default:
2078 cmd->scsi_done(cmd);
2079 }
2080}
2081
f281233d 2082static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
1c57e86d
EC		 2083 void (* done)(struct scsi_cmnd *))
2084{
2085 struct Scsi_Host *host = cmd->device->host;
1a4f550a 2086 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
1c57e86d
EC		 2087 struct CommandControlBlock *ccb;
2088 int target = cmd->device->id;
2089 int lun = cmd->device->lun;
36b83ded 2090 uint8_t scsicmd = cmd->cmnd[0];
1c57e86d
EC		 2091 cmd->scsi_done = done;
2092 cmd->host_scribble = NULL;
2093 cmd->result = 0;
cdd3cb15
NC		 2094 if ((scsicmd == SYNCHRONIZE_CACHE) ||(scsicmd == SEND_DIAGNOSTIC)){
2095 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2096 cmd->result = (DID_NO_CONNECT << 16);
36b83ded
NC		 2097 }
2098 cmd->scsi_done(cmd);
2099 return 0;
2100 }
a1f6e021 2101 if (target == 16) {
1c57e86d
EC		 2102 /* virtual device for iop message transfer */
2103 arcmsr_handle_virtual_command(acb, cmd);
2104 return 0;
2105 }
1c57e86d
EC		 2106 if (atomic_read(&acb->ccboutstandingcount) >=
2107 ARCMSR_MAX_OUTSTANDING_CMD)
2108 return SCSI_MLQUEUE_HOST_BUSY;
cdd3cb15
NC		 2109 if ((scsicmd == SCSI_CMD_ARECA_SPECIFIC)) {
2110 printk(KERN_NOTICE "Receiveing SCSI_CMD_ARECA_SPECIFIC command..\n");
2111 return 0;
2112 }
1c57e86d
EC		 2113 ccb = arcmsr_get_freeccb(acb);
2114 if (!ccb)
2115 return SCSI_MLQUEUE_HOST_BUSY;
cdd3cb15 2116 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
76d78300
NC		 2117 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
2118 cmd->scsi_done(cmd);
2119 return 0;
2120 }
1c57e86d
EC		 2121 arcmsr_post_ccb(acb, ccb);
2122 return 0;
2123}
2124
f281233d
JG		 2125static DEF_SCSI_QCMD(arcmsr_queue_command)
2126
ae52e7f0 2127static bool arcmsr_get_hba_config(struct AdapterControlBlock *acb)
1c57e86d 2128{
80da1adb 2129 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d
EC		 2130 char *acb_firm_model = acb->firm_model;
2131 char *acb_firm_version = acb->firm_version;
36b83ded 2132 char *acb_device_map = acb->device_map;
80da1adb
AV		 2133 char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
2134 char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
cdd3cb15 2135 char __iomem *iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]);
1c57e86d 2136 int count;
1c57e86d 2137 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
cdd3cb15 2138 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 2139 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2140 miscellaneous data' timeout \n", acb->host->host_no);
ae52e7f0 2141 return false;
1a4f550a 2142 }
1c57e86d 2143 count = 8;
cdd3cb15 2144 while (count){
1c57e86d
EC		 2145 *acb_firm_model = readb(iop_firm_model);
2146 acb_firm_model++;
2147 iop_firm_model++;
2148 count--;
2149 }
1a4f550a 2150
1c57e86d 2151 count = 16;
cdd3cb15 2152 while (count){
1c57e86d
EC		 2153 *acb_firm_version = readb(iop_firm_version);
2154 acb_firm_version++;
2155 iop_firm_version++;
2156 count--;
2157 }
1a4f550a 2158
cdd3cb15
NC		 2159 count=16;
2160 while(count){
2161 *acb_device_map = readb(iop_device_map);
2162 acb_device_map++;
2163 iop_device_map++;
2164 count--;
2165 }
2166 printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
ae52e7f0
NC		 2167 acb->host->host_no,
2168 acb->firm_version,
2169 acb->firm_model);
cdd3cb15 2170 acb->signature = readl(&reg->message_rwbuffer[0]);
1c57e86d
EC		 2171 acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
2172 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
2173 acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
2174 acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
ae52e7f0
NC		 2175 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2176 return true;
1c57e86d 2177}
ae52e7f0 2178static bool arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
1a4f550a 2179{
80da1adb 2180 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0
NC		 2181 struct pci_dev *pdev = acb->pdev;
2182 void *dma_coherent;
2183 dma_addr_t dma_coherent_handle;
1a4f550a
NC		 2184 char *acb_firm_model = acb->firm_model;
2185 char *acb_firm_version = acb->firm_version;
36b83ded 2186 char *acb_device_map = acb->device_map;
ae52e7f0 2187 char __iomem *iop_firm_model;
1a4f550a 2188 /*firm_model,15,60-67*/
ae52e7f0 2189 char __iomem *iop_firm_version;
1a4f550a 2190 /*firm_version,17,68-83*/
ae52e7f0 2191 char __iomem *iop_device_map;
36b83ded 2192 /*firm_version,21,84-99*/
1a4f550a 2193 int count;
ae52e7f0 2194 dma_coherent = dma_alloc_coherent(&pdev->dev, sizeof(struct MessageUnit_B), &dma_coherent_handle, GFP_KERNEL);
cdd3cb15 2195 if (!dma_coherent){
ae52e7f0
NC		 2196 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error for hbb mu\n", acb->host->host_no);
2197 return false;
2198 }
2199 acb->dma_coherent_handle_hbb_mu = dma_coherent_handle;
2200 reg = (struct MessageUnit_B *)dma_coherent;
2201 acb->pmuB = reg;
cdd3cb15 2202 reg->drv2iop_doorbell= (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL);
ae52e7f0
NC		 2203 reg->drv2iop_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL_MASK);
2204 reg->iop2drv_doorbell = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL);
2205 reg->iop2drv_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL_MASK);
2206 reg->message_wbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_WBUFFER);
2207 reg->message_rbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RBUFFER);
2208 reg->message_rwbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RWBUFFER);
2209 iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]); /*firm_model,15,60-67*/
2210 iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]); /*firm_version,17,68-83*/
2211 iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]); /*firm_version,21,84-99*/
2212
2213 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
cdd3cb15 2214 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2215 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2216 miscellaneous data' timeout \n", acb->host->host_no);
ae52e7f0 2217 return false;
1a4f550a 2218 }
1a4f550a 2219 count = 8;
cdd3cb15 2220 while (count){
1a4f550a
NC		 2221 *acb_firm_model = readb(iop_firm_model);
2222 acb_firm_model++;
2223 iop_firm_model++;
2224 count--;
2225 }
1a4f550a 2226 count = 16;
cdd3cb15 2227 while (count){
1a4f550a
NC		 2228 *acb_firm_version = readb(iop_firm_version);
2229 acb_firm_version++;
2230 iop_firm_version++;
2231 count--;
2232 }
2233
cdd3cb15
NC		 2234 count = 16;
2235 while(count){
2236 *acb_device_map = readb(iop_device_map);
2237 acb_device_map++;
2238 iop_device_map++;
2239 count--;
2240 }
2241
ae52e7f0 2242 printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
cdd3cb15 2243 acb->host->host_no,
ae52e7f0
NC		 2244 acb->firm_version,
2245 acb->firm_model);
1a4f550a 2246
ae52e7f0 2247 acb->signature = readl(&reg->message_rwbuffer[1]);
cdd3cb15 2248 /*firm_signature,1,00-03*/
ae52e7f0 2249 acb->firm_request_len = readl(&reg->message_rwbuffer[2]);
1a4f550a 2250 /*firm_request_len,1,04-07*/
ae52e7f0 2251 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[3]);
1a4f550a 2252 /*firm_numbers_queue,2,08-11*/
ae52e7f0 2253 acb->firm_sdram_size = readl(&reg->message_rwbuffer[4]);
1a4f550a 2254 /*firm_sdram_size,3,12-15*/
ae52e7f0 2255 acb->firm_hd_channels = readl(&reg->message_rwbuffer[5]);
1a4f550a 2256 /*firm_ide_channels,4,16-19*/
ae52e7f0
NC		 2257 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2258 /*firm_ide_channels,4,16-19*/
2259 return true;
1a4f550a 2260}
cdd3cb15
NC		 2261
2262static bool arcmsr_get_hbc_config(struct AdapterControlBlock *pACB)
2263{
2264 uint32_t intmask_org, Index, firmware_state = 0;
2265 struct MessageUnit_C *reg = pACB->pmuC;
2266 char *acb_firm_model = pACB->firm_model;
2267 char *acb_firm_version = pACB->firm_version;
2268 char *iop_firm_model = (char *)(&reg->msgcode_rwbuffer[15]); /*firm_model,15,60-67*/
2269 char *iop_firm_version = (char *)(&reg->msgcode_rwbuffer[17]); /*firm_version,17,68-83*/
2270 int count;
2271 /* disable all outbound interrupt */
2272 intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
2273 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
2274 /* wait firmware ready */
2275 do {
2276 firmware_state = readl(&reg->outbound_msgaddr1);
2277 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
2278 /* post "get config" instruction */
2279 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
2280 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2281 /* wait message ready */
2282 for (Index = 0; Index < 2000; Index++) {
2283 if (readl(&reg->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
2284 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);/*clear interrupt*/
2285 break;
2286 }
2287 udelay(10);
2288 } /*max 1 seconds*/
2289 if (Index >= 2000) {
2290 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2291 miscellaneous data' timeout \n", pACB->host->host_no);
2292 return false;
2293 }
2294 count = 8;
2295 while (count) {
2296 *acb_firm_model = readb(iop_firm_model);
2297 acb_firm_model++;
2298 iop_firm_model++;
2299 count--;
2300 }
2301 count = 16;
2302 while (count) {
2303 *acb_firm_version = readb(iop_firm_version);
2304 acb_firm_version++;
2305 iop_firm_version++;
2306 count--;
2307 }
2308 printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
2309 pACB->host->host_no,
2310 pACB->firm_version,
2311 pACB->firm_model);
2312 pACB->firm_request_len = readl(&reg->msgcode_rwbuffer[1]); /*firm_request_len,1,04-07*/
2313 pACB->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[2]); /*firm_numbers_queue,2,08-11*/
2314 pACB->firm_sdram_size = readl(&reg->msgcode_rwbuffer[3]); /*firm_sdram_size,3,12-15*/
2315 pACB->firm_hd_channels = readl(&reg->msgcode_rwbuffer[4]); /*firm_ide_channels,4,16-19*/
2316 pACB->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2317 /*all interrupt service will be enable at arcmsr_iop_init*/
2318 return true;
2319}
ae52e7f0 2320static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
1a4f550a 2321{
ae52e7f0
NC		 2322 if (acb->adapter_type == ACB_ADAPTER_TYPE_A)
2323 return arcmsr_get_hba_config(acb);
cdd3cb15 2324 else if (acb->adapter_type == ACB_ADAPTER_TYPE_B)
ae52e7f0 2325 return arcmsr_get_hbb_config(acb);
cdd3cb15
NC		 2326 else
2327 return arcmsr_get_hbc_config(acb);
1a4f550a
NC		 2328}
2329
ae52e7f0 2330static int arcmsr_polling_hba_ccbdone(struct AdapterControlBlock *acb,
1c57e86d
EC		 2331 struct CommandControlBlock *poll_ccb)
2332{
80da1adb 2333 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 2334 struct CommandControlBlock *ccb;
ae52e7f0 2335 struct ARCMSR_CDB *arcmsr_cdb;
1c57e86d 2336 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 2337 int rtn;
cdd3cb15 2338 bool error;
1a4f550a 2339 polling_hba_ccb_retry:
1c57e86d 2340 poll_count++;
1a4f550a 2341 outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
1c57e86d
EC		 2342 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
2343 while (1) {
2344 if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
cdd3cb15 2345 if (poll_ccb_done){
ae52e7f0 2346 rtn = SUCCESS;
1c57e86d 2347 break;
cdd3cb15
NC		 2348 }else {
2349 msleep(25);
2350 if (poll_count > 100){
ae52e7f0 2351 rtn = FAILED;
1c57e86d 2352 break;
ae52e7f0 2353 }
1a4f550a 2354 goto polling_hba_ccb_retry;
1c57e86d
EC		 2355 }
2356 }
ae52e7f0
NC		 2357 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
2358 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
1a4f550a
NC		 2359 poll_ccb_done = (ccb == poll_ccb) ? 1:0;
2360 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
2361 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
2362 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
1c57e86d
EC		 2363 " poll command abort successfully \n"
2364 , acb->host->host_no
2365 , ccb->pcmd->device->id
2366 , ccb->pcmd->device->lun
2367 , ccb);
2368 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 2369 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 2370 continue;
2371 }
1a4f550a
NC		 2372 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2373 " command done ccb = '0x%p'"
a1f6e021 2374 "ccboutstandingcount = %d \n"
1c57e86d
EC		 2375 , acb->host->host_no
2376 , ccb
2377 , atomic_read(&acb->ccboutstandingcount));
2378 continue;
cdd3cb15
NC		 2379 }
2380 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2381 arcmsr_report_ccb_state(acb, ccb, error);
1a4f550a 2382 }
ae52e7f0
NC		 2383 return rtn;
2384}
1a4f550a 2385
ae52e7f0 2386static int arcmsr_polling_hbb_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 2387 struct CommandControlBlock *poll_ccb)
2388{
cdd3cb15 2389 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2390 struct ARCMSR_CDB *arcmsr_cdb;
cdd3cb15
NC		 2391 struct CommandControlBlock *ccb;
2392 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 2393 int index, rtn;
cdd3cb15 2394 bool error;
1a4f550a 2395 polling_hbb_ccb_retry:
cdd3cb15
NC		 2396 poll_count++;
2397 /* clear doorbell interrupt */
ae52e7f0 2398 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
cdd3cb15
NC		 2399 while(1){
2400 index = reg->doneq_index;
2401 if ((flag_ccb = readl(&reg->done_qbuffer[index])) == 0) {
2402 if (poll_ccb_done){
ae52e7f0 2403 rtn = SUCCESS;
cdd3cb15
NC		 2404 break;
2405 }else {
2406 msleep(25);
2407 if (poll_count > 100){
ae52e7f0 2408 rtn = FAILED;
cdd3cb15 2409 break;
1c57e86d 2410 }
cdd3cb15 2411 goto polling_hbb_ccb_retry;
1a4f550a 2412 }
cdd3cb15
NC		 2413 }
2414 writel(0, &reg->done_qbuffer[index]);
2415 index++;
2416 /*if last index number set it to 0 */
2417 index %= ARCMSR_MAX_HBB_POSTQUEUE;
2418 reg->doneq_index = index;
2419 /* check if command done with no error*/
ae52e7f0
NC		 2420 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
2421 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
cdd3cb15
NC		 2422 poll_ccb_done = (ccb == poll_ccb) ? 1:0;
2423 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
2424 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
ae52e7f0
NC		 2425 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
2426 " poll command abort successfully \n"
cdd3cb15
NC		 2427 ,acb->host->host_no
2428 ,ccb->pcmd->device->id
2429 ,ccb->pcmd->device->lun
2430 ,ccb);
2431 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 2432 arcmsr_ccb_complete(ccb);
cdd3cb15
NC		 2433 continue;
2434 }
2435 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2436 " command done ccb = '0x%p'"
2437 "ccboutstandingcount = %d \n"
2438 , acb->host->host_no
2439 , ccb
2440 , atomic_read(&acb->ccboutstandingcount));
2441 continue;
2442 }
2443 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2444 arcmsr_report_ccb_state(acb, ccb, error);
2445 }
2446 return rtn;
2447}
2448
2449static int arcmsr_polling_hbc_ccbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_ccb)
2450{
2451 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2452 uint32_t flag_ccb, ccb_cdb_phy;
2453 struct ARCMSR_CDB *arcmsr_cdb;
2454 bool error;
2455 struct CommandControlBlock *pCCB;
2456 uint32_t poll_ccb_done = 0, poll_count = 0;
2457 int rtn;
2458polling_hbc_ccb_retry:
2459 poll_count++;
2460 while (1) {
2461 if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
2462 if (poll_ccb_done) {
2463 rtn = SUCCESS;
2464 break;
2465 } else {
2466 msleep(25);
2467 if (poll_count > 100) {
2468 rtn = FAILED;
2469 break;
1c57e86d 2470 }
cdd3cb15
NC		 2471 goto polling_hbc_ccb_retry;
2472 }
2473 }
2474 flag_ccb = readl(&reg->outbound_queueport_low);
2475 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
2476 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/
2477 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
2478 poll_ccb_done = (pCCB == poll_ccb) ? 1 : 0;
2479 /* check ifcommand done with no error*/
2480 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
2481 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
2482 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
2483 " poll command abort successfully \n"
1c57e86d 2484 , acb->host->host_no
cdd3cb15
NC		 2485 , pCCB->pcmd->device->id
2486 , pCCB->pcmd->device->lun
2487 , pCCB);
2488 pCCB->pcmd->result = DID_ABORT << 16;
2489 arcmsr_ccb_complete(pCCB);
1a4f550a 2490 continue;
cdd3cb15
NC		 2491 }
2492 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2493 " command done ccb = '0x%p'"
2494 "ccboutstandingcount = %d \n"
2495 , acb->host->host_no
2496 , pCCB
2497 , atomic_read(&acb->ccboutstandingcount));
2498 continue;
ae52e7f0 2499 }
cdd3cb15
NC		 2500 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
2501 arcmsr_report_ccb_state(acb, pCCB, error);
2502 }
ae52e7f0 2503 return rtn;
1a4f550a 2504}
ae52e7f0 2505static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 2506 struct CommandControlBlock *poll_ccb)
2507{
ae52e7f0 2508 int rtn = 0;
1a4f550a
NC		 2509 switch (acb->adapter_type) {
2510
2511 case ACB_ADAPTER_TYPE_A: {
ae52e7f0 2512 rtn = arcmsr_polling_hba_ccbdone(acb, poll_ccb);
1a4f550a
NC		 2513 }
2514 break;
2515
2516 case ACB_ADAPTER_TYPE_B: {
ae52e7f0 2517 rtn = arcmsr_polling_hbb_ccbdone(acb, poll_ccb);
1c57e86d 2518 }
cdd3cb15
NC		 2519 break;
2520 case ACB_ADAPTER_TYPE_C: {
2521 rtn = arcmsr_polling_hbc_ccbdone(acb, poll_ccb);
2522 }
1c57e86d 2523 }
ae52e7f0 2524 return rtn;
1c57e86d 2525}
1a4f550a
NC		 2526
2527static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
a1f6e021 2528{
ae52e7f0 2529 uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
1a4f550a
NC		 2530 dma_addr_t dma_coherent_handle;
2531 /*
2532 ********************************************************************
2533 ** here we need to tell iop 331 our freeccb.HighPart
2534 ** if freeccb.HighPart is not zero
2535 ********************************************************************
2536 */
2537 dma_coherent_handle = acb->dma_coherent_handle;
2538 cdb_phyaddr = (uint32_t)(dma_coherent_handle);
ae52e7f0 2539 cdb_phyaddr_hi32 = (uint32_t)((cdb_phyaddr >> 16) >> 16);
cdd3cb15 2540 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
1a4f550a
NC		 2541 /*
2542 ***********************************************************************
2543 ** if adapter type B, set window of "post command Q"
2544 ***********************************************************************
2545 */
2546 switch (acb->adapter_type) {
2547
2548 case ACB_ADAPTER_TYPE_A: {
ae52e7f0 2549 if (cdb_phyaddr_hi32 != 0) {
80da1adb 2550 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2551 uint32_t intmask_org;
2552 intmask_org = arcmsr_disable_outbound_ints(acb);
2553 writel(ARCMSR_SIGNATURE_SET_CONFIG, \
2554 &reg->message_rwbuffer[0]);
ae52e7f0 2555 writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
1a4f550a
NC		 2556 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
2557 &reg->inbound_msgaddr0);
cdd3cb15 2558 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 2559 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
2560 part physical address timeout\n",
2561 acb->host->host_no);
2562 return 1;
a1f6e021 2563 }
1a4f550a
NC		 2564 arcmsr_enable_outbound_ints(acb, intmask_org);
2565 }
2566 }
2567 break;
a1f6e021 2568
1a4f550a
NC		 2569 case ACB_ADAPTER_TYPE_B: {
2570 unsigned long post_queue_phyaddr;
80da1adb 2571 uint32_t __iomem *rwbuffer;
a1f6e021 2572
80da1adb 2573 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 2574 uint32_t intmask_org;
2575 intmask_org = arcmsr_disable_outbound_ints(acb);
2576 reg->postq_index = 0;
2577 reg->doneq_index = 0;
ae52e7f0 2578 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
cdd3cb15 2579 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2580 printk(KERN_NOTICE "arcmsr%d:can not set diver mode\n", \
2581 acb->host->host_no);
2582 return 1;
2583 }
ae52e7f0
NC		 2584 post_queue_phyaddr = acb->dma_coherent_handle_hbb_mu;
2585 rwbuffer = reg->message_rwbuffer;
1a4f550a
NC		 2586 /* driver "set config" signature */
2587 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
2588 /* normal should be zero */
ae52e7f0 2589 writel(cdb_phyaddr_hi32, rwbuffer++);
1a4f550a
NC		 2590 /* postQ size (256 + 8)*4 */
2591 writel(post_queue_phyaddr, rwbuffer++);
2592 /* doneQ size (256 + 8)*4 */
2593 writel(post_queue_phyaddr + 1056, rwbuffer++);
2594 /* ccb maxQ size must be --> [(256 + 8)*4]*/
2595 writel(1056, rwbuffer);
2596
ae52e7f0 2597 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
cdd3cb15 2598 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2599 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
2600 timeout \n",acb->host->host_no);
2601 return 1;
2602 }
ae52e7f0 2603 arcmsr_hbb_enable_driver_mode(acb);
1a4f550a
NC		 2604 arcmsr_enable_outbound_ints(acb, intmask_org);
2605 }
2606 break;
cdd3cb15
NC		 2607 case ACB_ADAPTER_TYPE_C: {
2608 if (cdb_phyaddr_hi32 != 0) {
2609 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2610
2611 if (cdb_phyaddr_hi32 != 0) {
2612 unsigned char Retries = 0x00;
2613 do {
2614 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x \n", acb->adapter_index, cdb_phyaddr_hi32);
2615 } while (Retries++ < 100);
2616 }
2617 writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
2618 writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
2619 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
2620 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2621 if (!arcmsr_hbc_wait_msgint_ready(acb)) {
2622 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
2623 timeout \n", acb->host->host_no);
2624 return 1;
2625 }
2626 }
2627 }
1a4f550a
NC		 2628 }
2629 return 0;
2630}
a1f6e021 2631
1a4f550a
NC		 2632static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
2633{
2634 uint32_t firmware_state = 0;
1a4f550a
NC		 2635 switch (acb->adapter_type) {
2636
2637 case ACB_ADAPTER_TYPE_A: {
80da1adb 2638 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2639 do {
2640 firmware_state = readl(&reg->outbound_msgaddr1);
2641 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
2642 }
2643 break;
2644
2645 case ACB_ADAPTER_TYPE_B: {
80da1adb 2646 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2647 do {
ae52e7f0 2648 firmware_state = readl(reg->iop2drv_doorbell);
1a4f550a 2649 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
ae52e7f0 2650 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
1a4f550a
NC		 2651 }
2652 break;
cdd3cb15
NC		 2653 case ACB_ADAPTER_TYPE_C: {
2654 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2655 do {
2656 firmware_state = readl(&reg->outbound_msgaddr1);
2657 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
2658 }
a1f6e021 2659 }
1a4f550a
NC		 2660}
2661
36b83ded
NC		 2662static void arcmsr_request_hba_device_map(struct AdapterControlBlock *acb)
2663{
2664 struct MessageUnit_A __iomem *reg = acb->pmuA;
cdd3cb15 2665 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
ae52e7f0 2666 return;
36b83ded 2667 } else {
ae52e7f0 2668 acb->fw_flag = FW_NORMAL;
cdd3cb15 2669 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)){
36b83ded
NC		 2670 atomic_set(&acb->rq_map_token, 16);
2671 }
ae52e7f0
NC		 2672 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
2673 if (atomic_dec_and_test(&acb->rq_map_token))
2674 return;
36b83ded 2675 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
cdd3cb15 2676 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
36b83ded 2677 }
36b83ded
NC		 2678 return;
2679}
2680
2681static void arcmsr_request_hbb_device_map(struct AdapterControlBlock *acb)
2682{
2683 struct MessageUnit_B __iomem *reg = acb->pmuB;
cdd3cb15
NC		 2684 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
2685 return;
2686 } else {
2687 acb->fw_flag = FW_NORMAL;
2688 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
2689 atomic_set(&acb->rq_map_token,16);
2690 }
2691 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
2692 if(atomic_dec_and_test(&acb->rq_map_token))
2693 return;
2694 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
2695 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
2696 }
2697 return;
2698}
36b83ded 2699
cdd3cb15
NC		 2700static void arcmsr_request_hbc_device_map(struct AdapterControlBlock *acb)
2701{
2702 struct MessageUnit_C __iomem *reg = acb->pmuC;
ae52e7f0
NC		 2703 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0) || ((acb->acb_flags & ACB_F_ABORT) != 0)) {
2704 return;
36b83ded 2705 } else {
ae52e7f0
NC		 2706 acb->fw_flag = FW_NORMAL;
2707 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
36b83ded
NC		 2708 atomic_set(&acb->rq_map_token, 16);
2709 }
ae52e7f0
NC		 2710 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
2711 if (atomic_dec_and_test(&acb->rq_map_token))
2712 return;
cdd3cb15
NC		 2713 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
2714 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2715 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
36b83ded 2716 }
36b83ded
NC		 2717 return;
2718}
2719
2720static void arcmsr_request_device_map(unsigned long pacb)
2721{
2722 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)pacb;
36b83ded
NC		 2723 switch (acb->adapter_type) {
2724 case ACB_ADAPTER_TYPE_A: {
2725 arcmsr_request_hba_device_map(acb);
2726 }
2727 break;
2728 case ACB_ADAPTER_TYPE_B: {
2729 arcmsr_request_hbb_device_map(acb);
2730 }
2731 break;
cdd3cb15
NC		 2732 case ACB_ADAPTER_TYPE_C: {
2733 arcmsr_request_hbc_device_map(acb);
2734 }
36b83ded
NC		 2735 }
2736}
2737
1a4f550a
NC		 2738static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
2739{
80da1adb 2740 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2741 acb->acb_flags |= ACB_F_MSG_START_BGRB;
2742 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
cdd3cb15 2743 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 2744 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
2745 rebulid' timeout \n", acb->host->host_no);
a1f6e021 2746 }
a1f6e021 2747}
2748
1a4f550a
NC		 2749static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
2750{
80da1adb 2751 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2752 acb->acb_flags |= ACB_F_MSG_START_BGRB;
ae52e7f0 2753 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
cdd3cb15 2754 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2755 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
2756 rebulid' timeout \n",acb->host->host_no);
2757 }
2758}
1c57e86d 2759
cdd3cb15
NC		 2760static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *pACB)
2761{
2762 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
2763 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
2764 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
2765 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
2766 if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
2767 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
2768 rebulid' timeout \n", pACB->host->host_no);
2769 }
2770 return;
2771}
1a4f550a 2772static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
1c57e86d 2773{
1a4f550a
NC		 2774 switch (acb->adapter_type) {
2775 case ACB_ADAPTER_TYPE_A:
2776 arcmsr_start_hba_bgrb(acb);
2777 break;
2778 case ACB_ADAPTER_TYPE_B:
2779 arcmsr_start_hbb_bgrb(acb);
2780 break;
cdd3cb15
NC		 2781 case ACB_ADAPTER_TYPE_C:
2782 arcmsr_start_hbc_bgrb(acb);
1a4f550a
NC		 2783 }
2784}
1c57e86d 2785
1a4f550a
NC		 2786static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
2787{
2788 switch (acb->adapter_type) {
2789 case ACB_ADAPTER_TYPE_A: {
80da1adb 2790 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2791 uint32_t outbound_doorbell;
2792 /* empty doorbell Qbuffer if door bell ringed */
2793 outbound_doorbell = readl(&reg->outbound_doorbell);
2794 /*clear doorbell interrupt */
2795 writel(outbound_doorbell, &reg->outbound_doorbell);
2796 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
2797 }
2798 break;
1c57e86d 2799
1a4f550a 2800 case ACB_ADAPTER_TYPE_B: {
80da1adb 2801 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2802 /*clear interrupt and message state*/
ae52e7f0
NC		 2803 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
2804 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1a4f550a
NC		 2805 /* let IOP know data has been read */
2806 }
2807 break;
cdd3cb15
NC		 2808 case ACB_ADAPTER_TYPE_C: {
2809 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2810 uint32_t outbound_doorbell;
2811 /* empty doorbell Qbuffer if door bell ringed */
2812 outbound_doorbell = readl(&reg->outbound_doorbell);
2813 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
2814 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
2815 }
1c57e86d 2816 }
1a4f550a 2817}
1c57e86d 2818
76d78300
NC		 2819static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
2820{
2821 switch (acb->adapter_type) {
2822 case ACB_ADAPTER_TYPE_A:
2823 return;
2824 case ACB_ADAPTER_TYPE_B:
2825 {
2826 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2827 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
cdd3cb15 2828 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
76d78300
NC		 2829 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
2830 return;
2831 }
2832 }
2833 break;
cdd3cb15
NC		 2834 case ACB_ADAPTER_TYPE_C:
2835 return;
76d78300
NC		 2836 }
2837 return;
2838}
2839
36b83ded
NC		 2840static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
2841{
2842 uint8_t value[64];
cdd3cb15
NC		 2843 int i, count = 0;
2844 struct MessageUnit_A __iomem *pmuA = acb->pmuA;
2845 struct MessageUnit_C __iomem *pmuC = acb->pmuC;
2846 u32 temp = 0;
36b83ded 2847 /* backup pci config data */
cdd3cb15 2848 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
36b83ded
NC		 2849 for (i = 0; i < 64; i++) {
2850 pci_read_config_byte(acb->pdev, i, &value[i]);
2851 }
2852 /* hardware reset signal */
ae52e7f0 2853 if ((acb->dev_id == 0x1680)) {
cdd3cb15
NC		 2854 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
2855 } else if ((acb->dev_id == 0x1880)) {
2856 do {
2857 count++;
2858 writel(0xF, &pmuC->write_sequence);
2859 writel(0x4, &pmuC->write_sequence);
2860 writel(0xB, &pmuC->write_sequence);
2861 writel(0x2, &pmuC->write_sequence);
2862 writel(0x7, &pmuC->write_sequence);
2863 writel(0xD, &pmuC->write_sequence);
2864 } while ((((temp = readl(&pmuC->host_diagnostic)) | ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
2865 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
ae52e7f0 2866 } else {
cdd3cb15 2867 pci_write_config_byte(acb->pdev, 0x84, 0x20);
ae52e7f0 2868 }
cdd3cb15 2869 msleep(2000);
36b83ded
NC		 2870 /* write back pci config data */
2871 for (i = 0; i < 64; i++) {
2872 pci_write_config_byte(acb->pdev, i, value[i]);
2873 }
2874 msleep(1000);
2875 return;
2876}
1a4f550a
NC		 2877static void arcmsr_iop_init(struct AdapterControlBlock *acb)
2878{
2879 uint32_t intmask_org;
cdd3cb15
NC		 2880 /* disable all outbound interrupt */
2881 intmask_org = arcmsr_disable_outbound_ints(acb);
76d78300
NC		 2882 arcmsr_wait_firmware_ready(acb);
2883 arcmsr_iop_confirm(acb);
1a4f550a
NC		 2884 /*start background rebuild*/
2885 arcmsr_start_adapter_bgrb(acb);
2886 /* empty doorbell Qbuffer if door bell ringed */
2887 arcmsr_clear_doorbell_queue_buffer(acb);
76d78300 2888 arcmsr_enable_eoi_mode(acb);
1a4f550a
NC		 2889 /* enable outbound Post Queue,outbound doorbell Interrupt */
2890 arcmsr_enable_outbound_ints(acb, intmask_org);
1c57e86d
EC		 2891 acb->acb_flags |= ACB_F_IOP_INITED;
2892}
2893
36b83ded 2894static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
1c57e86d 2895{
1c57e86d
EC		 2896 struct CommandControlBlock *ccb;
2897 uint32_t intmask_org;
36b83ded 2898 uint8_t rtnval = 0x00;
1c57e86d 2899 int i = 0;
1c57e86d 2900 if (atomic_read(&acb->ccboutstandingcount) != 0) {
36b83ded
NC		 2901 /* disable all outbound interrupt */
2902 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d 2903 /* talk to iop 331 outstanding command aborted */
36b83ded 2904 rtnval = arcmsr_abort_allcmd(acb);
1c57e86d 2905 /* clear all outbound posted Q */
1a4f550a 2906 arcmsr_done4abort_postqueue(acb);
1c57e86d
EC		 2907 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
2908 ccb = acb->pccb_pool[i];
a1f6e021 2909 if (ccb->startdone == ARCMSR_CCB_START) {
ae52e7f0 2910 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 2911 }
2912 }
36b83ded 2913 atomic_set(&acb->ccboutstandingcount, 0);
1c57e86d
EC		 2914 /* enable all outbound interrupt */
2915 arcmsr_enable_outbound_ints(acb, intmask_org);
36b83ded 2916 return rtnval;
1c57e86d 2917 }
36b83ded 2918 return rtnval;
1c57e86d
EC		 2919}
2920
2921static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
2922{
2923 struct AdapterControlBlock *acb =
2924 (struct AdapterControlBlock *)cmd->device->host->hostdata;
ae52e7f0
NC		 2925 uint32_t intmask_org, outbound_doorbell;
2926 int retry_count = 0;
2927 int rtn = FAILED;
ae52e7f0 2928 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
cdd3cb15 2929 printk(KERN_ERR "arcmsr: executing bus reset eh.....num_resets = %d, num_aborts = %d \n", acb->num_resets, acb->num_aborts);
36b83ded 2930 acb->num_resets++;
36b83ded 2931
cdd3cb15
NC		 2932 switch(acb->adapter_type){
2933 case ACB_ADAPTER_TYPE_A:{
2934 if (acb->acb_flags & ACB_F_BUS_RESET){
ae52e7f0 2935 long timeout;
cdd3cb15
NC		 2936 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
2937 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
ae52e7f0
NC		 2938 if (timeout) {
2939 return SUCCESS;
2940 }
2941 }
2942 acb->acb_flags |= ACB_F_BUS_RESET;
cdd3cb15 2943 if (!arcmsr_iop_reset(acb)) {
ae52e7f0
NC		 2944 struct MessageUnit_A __iomem *reg;
2945 reg = acb->pmuA;
cdd3cb15
NC		 2946 arcmsr_hardware_reset(acb);
2947 acb->acb_flags &= ~ACB_F_IOP_INITED;
36b83ded 2948sleep_again:
cdd3cb15 2949 arcmsr_sleep_for_bus_reset(cmd);
ae52e7f0 2950 if ((readl(&reg->outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) {
cdd3cb15
NC		 2951 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d \n", acb->host->host_no, retry_count);
2952 if (retry_count > retrycount) {
ae52e7f0 2953 acb->fw_flag = FW_DEADLOCK;
cdd3cb15 2954 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!! \n", acb->host->host_no);
ae52e7f0 2955 return FAILED;
cdd3cb15
NC		 2956 }
2957 retry_count++;
2958 goto sleep_again;
2959 }
2960 acb->acb_flags |= ACB_F_IOP_INITED;
2961 /* disable all outbound interrupt */
2962 intmask_org = arcmsr_disable_outbound_ints(acb);
ae52e7f0 2963 arcmsr_get_firmware_spec(acb);
cdd3cb15
NC		 2964 arcmsr_start_adapter_bgrb(acb);
2965 /* clear Qbuffer if door bell ringed */
2966 outbound_doorbell = readl(&reg->outbound_doorbell);
2967 writel(outbound_doorbell, &reg->outbound_doorbell); /*clear interrupt */
2968 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
2969 /* enable outbound Post Queue,outbound doorbell Interrupt */
2970 arcmsr_enable_outbound_ints(acb, intmask_org);
2971 atomic_set(&acb->rq_map_token, 16);
ae52e7f0
NC		 2972 atomic_set(&acb->ante_token_value, 16);
2973 acb->fw_flag = FW_NORMAL;
2974 init_timer(&acb->eternal_timer);
2975 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6*HZ);
2976 acb->eternal_timer.data = (unsigned long) acb;
2977 acb->eternal_timer.function = &arcmsr_request_device_map;
2978 add_timer(&acb->eternal_timer);
2979 acb->acb_flags &= ~ACB_F_BUS_RESET;
2980 rtn = SUCCESS;
cdd3cb15 2981 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
ae52e7f0
NC		 2982 } else {
2983 acb->acb_flags &= ~ACB_F_BUS_RESET;
2984 if (atomic_read(&acb->rq_map_token) == 0) {
2985 atomic_set(&acb->rq_map_token, 16);
2986 atomic_set(&acb->ante_token_value, 16);
2987 acb->fw_flag = FW_NORMAL;
cdd3cb15 2988 init_timer(&acb->eternal_timer);
ae52e7f0 2989 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6*HZ);
cdd3cb15
NC		 2990 acb->eternal_timer.data = (unsigned long) acb;
2991 acb->eternal_timer.function = &arcmsr_request_device_map;
2992 add_timer(&acb->eternal_timer);
ae52e7f0
NC		 2993 } else {
2994 atomic_set(&acb->rq_map_token, 16);
2995 atomic_set(&acb->ante_token_value, 16);
2996 acb->fw_flag = FW_NORMAL;
2997 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
cdd3cb15 2998 }
ae52e7f0 2999 rtn = SUCCESS;
cdd3cb15 3000 }
ae52e7f0 3001 break;
36b83ded 3002 }
ae52e7f0
NC		 3003 case ACB_ADAPTER_TYPE_B:{
3004 acb->acb_flags |= ACB_F_BUS_RESET;
cdd3cb15 3005 if (!arcmsr_iop_reset(acb)) {
ae52e7f0
NC		 3006 acb->acb_flags &= ~ACB_F_BUS_RESET;
3007 rtn = FAILED;
cdd3cb15
NC		 3008 } else {
3009 acb->acb_flags &= ~ACB_F_BUS_RESET;
ae52e7f0
NC		 3010 if (atomic_read(&acb->rq_map_token) == 0) {
3011 atomic_set(&acb->rq_map_token, 16);
3012 atomic_set(&acb->ante_token_value, 16);
3013 acb->fw_flag = FW_NORMAL;
3014 init_timer(&acb->eternal_timer);
3015 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6*HZ);
3016 acb->eternal_timer.data = (unsigned long) acb;
3017 acb->eternal_timer.function = &arcmsr_request_device_map;
3018 add_timer(&acb->eternal_timer);
3019 } else {
3020 atomic_set(&acb->rq_map_token, 16);
3021 atomic_set(&acb->ante_token_value, 16);
3022 acb->fw_flag = FW_NORMAL;
3023 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
3024 }
3025 rtn = SUCCESS;
cdd3cb15
NC		 3026 }
3027 break;
3028 }
3029 case ACB_ADAPTER_TYPE_C:{
3030 if (acb->acb_flags & ACB_F_BUS_RESET) {
3031 long timeout;
3032 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
3033 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
3034 if (timeout) {
3035 return SUCCESS;
3036 }
3037 }
3038 acb->acb_flags |= ACB_F_BUS_RESET;
3039 if (!arcmsr_iop_reset(acb)) {
3040 struct MessageUnit_C __iomem *reg;
3041 reg = acb->pmuC;
3042 arcmsr_hardware_reset(acb);
3043 acb->acb_flags &= ~ACB_F_IOP_INITED;
3044sleep:
3045 arcmsr_sleep_for_bus_reset(cmd);
3046 if ((readl(&reg->host_diagnostic) & 0x04) != 0) {
3047 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d \n", acb->host->host_no, retry_count);
3048 if (retry_count > retrycount) {
3049 acb->fw_flag = FW_DEADLOCK;
3050 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!! \n", acb->host->host_no);
3051 return FAILED;
3052 }
3053 retry_count++;
3054 goto sleep;
3055 }
3056 acb->acb_flags |= ACB_F_IOP_INITED;
3057 /* disable all outbound interrupt */
3058 intmask_org = arcmsr_disable_outbound_ints(acb);
3059 arcmsr_get_firmware_spec(acb);
3060 arcmsr_start_adapter_bgrb(acb);
3061 /* clear Qbuffer if door bell ringed */
3062 outbound_doorbell = readl(&reg->outbound_doorbell);
3063 writel(outbound_doorbell, &reg->outbound_doorbell_clear); /*clear interrupt */
3064 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
3065 /* enable outbound Post Queue,outbound doorbell Interrupt */
3066 arcmsr_enable_outbound_ints(acb, intmask_org);
3067 atomic_set(&acb->rq_map_token, 16);
3068 atomic_set(&acb->ante_token_value, 16);
3069 acb->fw_flag = FW_NORMAL;
3070 init_timer(&acb->eternal_timer);
3071 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
3072 acb->eternal_timer.data = (unsigned long) acb;
3073 acb->eternal_timer.function = &arcmsr_request_device_map;
3074 add_timer(&acb->eternal_timer);
3075 acb->acb_flags &= ~ACB_F_BUS_RESET;
3076 rtn = SUCCESS;
3077 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
3078 } else {
3079 acb->acb_flags &= ~ACB_F_BUS_RESET;
3080 if (atomic_read(&acb->rq_map_token) == 0) {
3081 atomic_set(&acb->rq_map_token, 16);
3082 atomic_set(&acb->ante_token_value, 16);
3083 acb->fw_flag = FW_NORMAL;
3084 init_timer(&acb->eternal_timer);
3085 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6*HZ);
3086 acb->eternal_timer.data = (unsigned long) acb;
3087 acb->eternal_timer.function = &arcmsr_request_device_map;
3088 add_timer(&acb->eternal_timer);
3089 } else {
3090 atomic_set(&acb->rq_map_token, 16);
3091 atomic_set(&acb->ante_token_value, 16);
3092 acb->fw_flag = FW_NORMAL;
3093 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
3094 }
3095 rtn = SUCCESS;
3096 }
3097 break;
ae52e7f0
NC		 3098 }
3099 }
3100 return rtn;
1c57e86d
EC		 3101}
3102
ae52e7f0 3103static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
1c57e86d
EC		 3104 struct CommandControlBlock *ccb)
3105{
ae52e7f0 3106 int rtn;
ae52e7f0 3107 rtn = arcmsr_polling_ccbdone(acb, ccb);
ae52e7f0 3108 return rtn;
1c57e86d
EC		 3109}
3110
3111static int arcmsr_abort(struct scsi_cmnd *cmd)
3112{
3113 struct AdapterControlBlock *acb =
3114 (struct AdapterControlBlock *)cmd->device->host->hostdata;
3115 int i = 0;
ae52e7f0 3116 int rtn = FAILED;
1c57e86d 3117 printk(KERN_NOTICE
a1f6e021 3118 "arcmsr%d: abort device command of scsi id = %d lun = %d \n",
1c57e86d 3119 acb->host->host_no, cmd->device->id, cmd->device->lun);
ae52e7f0 3120 acb->acb_flags |= ACB_F_ABORT;
1c57e86d 3121 acb->num_aborts++;
1c57e86d
EC		 3122 /*
3123 ************************************************
3124 ** the all interrupt service routine is locked
3125 ** we need to handle it as soon as possible and exit
3126 ************************************************
3127 */
3128 if (!atomic_read(&acb->ccboutstandingcount))
ae52e7f0 3129 return rtn;
1c57e86d
EC		 3130
3131 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
3132 struct CommandControlBlock *ccb = acb->pccb_pool[i];
3133 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
ae52e7f0
NC		 3134 ccb->startdone = ARCMSR_CCB_ABORTED;
3135 rtn = arcmsr_abort_one_cmd(acb, ccb);
1c57e86d
EC		 3136 break;
3137 }
3138 }
ae52e7f0
NC		 3139 acb->acb_flags &= ~ACB_F_ABORT;
3140 return rtn;
1c57e86d
EC		 3141}
3142
3143static const char *arcmsr_info(struct Scsi_Host *host)
3144{
3145 struct AdapterControlBlock *acb =
3146 (struct AdapterControlBlock *) host->hostdata;
3147 static char buf[256];
3148 char *type;
3149 int raid6 = 1;
1c57e86d
EC		 3150 switch (acb->pdev->device) {
3151 case PCI_DEVICE_ID_ARECA_1110:
1a4f550a
NC		 3152 case PCI_DEVICE_ID_ARECA_1200:
3153 case PCI_DEVICE_ID_ARECA_1202:
1c57e86d
EC		 3154 case PCI_DEVICE_ID_ARECA_1210:
3155 raid6 = 0;
3156 /*FALLTHRU*/
3157 case PCI_DEVICE_ID_ARECA_1120:
3158 case PCI_DEVICE_ID_ARECA_1130:
3159 case PCI_DEVICE_ID_ARECA_1160:
3160 case PCI_DEVICE_ID_ARECA_1170:
1a4f550a 3161 case PCI_DEVICE_ID_ARECA_1201:
1c57e86d
EC		 3162 case PCI_DEVICE_ID_ARECA_1220:
3163 case PCI_DEVICE_ID_ARECA_1230:
3164 case PCI_DEVICE_ID_ARECA_1260:
3165 case PCI_DEVICE_ID_ARECA_1270:
3166 case PCI_DEVICE_ID_ARECA_1280:
3167 type = "SATA";
3168 break;
3169 case PCI_DEVICE_ID_ARECA_1380:
3170 case PCI_DEVICE_ID_ARECA_1381:
3171 case PCI_DEVICE_ID_ARECA_1680:
3172 case PCI_DEVICE_ID_ARECA_1681:
cdd3cb15 3173 case PCI_DEVICE_ID_ARECA_1880:
1c57e86d
EC		 3174 type = "SAS";
3175 break;
3176 default:
3177 type = "X-TYPE";
3178 break;
3179 }
a1f6e021 3180 sprintf(buf, "Areca %s Host Adapter RAID Controller%s\n %s",
1c57e86d
EC		 3181 type, raid6 ? "( RAID6 capable)" : "",
3182 ARCMSR_DRIVER_VERSION);
3183 return buf;
3184}
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