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[SCSI] libsas: fix usage of ata_tf_to_fis
[mirror_ubuntu-hirsute-kernel.git] / drivers / scsi / arcmsr / arcmsr_hba.c
CommitLineData
1c57e86d
EC		 1/*
2*******************************************************************************
3** O.S : Linux
4** FILE NAME : arcmsr_hba.c
97b99127 5** BY : Nick Cheng
1c57e86d
EC		 6** Description: SCSI RAID Device Driver for
7** ARECA RAID Host adapter
8*******************************************************************************
9** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved
10**
11** Web site: www.areca.com.tw
1a4f550a 12** E-mail: support@areca.com.tw
1c57e86d
EC		 13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License version 2 as
16** published by the Free Software Foundation.
17** This program is distributed in the hope that it will be useful,
18** but WITHOUT ANY WARRANTY; without even the implied warranty of
19** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20** GNU General Public License for more details.
21*******************************************************************************
22** Redistribution and use in source and binary forms, with or without
23** modification, are permitted provided that the following conditions
24** are met:
25** 1. Redistributions of source code must retain the above copyright
26** notice, this list of conditions and the following disclaimer.
27** 2. Redistributions in binary form must reproduce the above copyright
28** notice, this list of conditions and the following disclaimer in the
29** documentation and/or other materials provided with the distribution.
30** 3. The name of the author may not be used to endorse or promote products
31** derived from this software without specific prior written permission.
32**
33** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
34** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
35** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
36** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
37** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
38** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
40** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43*******************************************************************************
44** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
45** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
46*******************************************************************************
47*/
48#include <linux/module.h>
49#include <linux/reboot.h>
50#include <linux/spinlock.h>
51#include <linux/pci_ids.h>
52#include <linux/interrupt.h>
53#include <linux/moduleparam.h>
54#include <linux/errno.h>
55#include <linux/types.h>
56#include <linux/delay.h>
57#include <linux/dma-mapping.h>
58#include <linux/timer.h>
a7c8962b 59#include <linux/slab.h>
1c57e86d 60#include <linux/pci.h>
a1f6e021 61#include <linux/aer.h>
1c57e86d
EC		 62#include <asm/dma.h>
63#include <asm/io.h>
1c57e86d
EC		 64#include <asm/uaccess.h>
65#include <scsi/scsi_host.h>
66#include <scsi/scsi.h>
67#include <scsi/scsi_cmnd.h>
68#include <scsi/scsi_tcq.h>
69#include <scsi/scsi_device.h>
70#include <scsi/scsi_transport.h>
71#include <scsi/scsicam.h>
72#include "arcmsr.h"
ae52e7f0 73MODULE_AUTHOR("Nick Cheng <support@areca.com.tw>");
cdd3cb15 74MODULE_DESCRIPTION("ARECA (ARC11xx/12xx/16xx/1880) SATA/SAS RAID Host Bus Adapter");
1c57e86d
EC		 75MODULE_LICENSE("Dual BSD/GPL");
76MODULE_VERSION(ARCMSR_DRIVER_VERSION);
8b7eb86f
TH		 77
78#define ARCMSR_SLEEPTIME 10
79#define ARCMSR_RETRYCOUNT 12
80
ae52e7f0 81wait_queue_head_t wait_q;
1a4f550a
NC		 82static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
83 struct scsi_cmnd *cmd);
84static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
1c57e86d
EC		 85static int arcmsr_abort(struct scsi_cmnd *);
86static int arcmsr_bus_reset(struct scsi_cmnd *);
87static int arcmsr_bios_param(struct scsi_device *sdev,
1a4f550a 88 struct block_device *bdev, sector_t capacity, int *info);
f281233d 89static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1c57e86d
EC		 90static int arcmsr_probe(struct pci_dev *pdev,
91 const struct pci_device_id *id);
92static void arcmsr_remove(struct pci_dev *pdev);
93static void arcmsr_shutdown(struct pci_dev *pdev);
94static void arcmsr_iop_init(struct AdapterControlBlock *acb);
95static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
1a4f550a 96static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
1c57e86d 97static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
1a4f550a
NC		 98static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb);
99static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb);
36b83ded
NC		 100static void arcmsr_request_device_map(unsigned long pacb);
101static void arcmsr_request_hba_device_map(struct AdapterControlBlock *acb);
102static void arcmsr_request_hbb_device_map(struct AdapterControlBlock *acb);
cdd3cb15 103static void arcmsr_request_hbc_device_map(struct AdapterControlBlock *acb);
36b83ded 104static void arcmsr_message_isr_bh_fn(struct work_struct *work);
ae52e7f0 105static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
36b83ded 106static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
cdd3cb15
NC		 107static void arcmsr_hbc_message_isr(struct AdapterControlBlock *pACB);
108static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
1c57e86d
EC		 109static const char *arcmsr_info(struct Scsi_Host *);
110static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
1a4f550a 111static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev,
e881a172 112 int queue_depth, int reason)
1c57e86d 113{
e881a172
MC		 114 if (reason != SCSI_QDEPTH_DEFAULT)
115 return -EOPNOTSUPP;
116
1c57e86d
EC		 117 if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
118 queue_depth = ARCMSR_MAX_CMD_PERLUN;
119 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, queue_depth);
120 return queue_depth;
121}
122
123static struct scsi_host_template arcmsr_scsi_host_template = {
124 .module = THIS_MODULE,
cdd3cb15
NC		 125 .name = "ARCMSR ARECA SATA/SAS RAID Controller"
126 ARCMSR_DRIVER_VERSION,
1c57e86d
EC		 127 .info = arcmsr_info,
128 .queuecommand = arcmsr_queue_command,
cdd3cb15 129 .eh_abort_handler = arcmsr_abort,
1c57e86d
EC		 130 .eh_bus_reset_handler = arcmsr_bus_reset,
131 .bios_param = arcmsr_bios_param,
132 .change_queue_depth = arcmsr_adjust_disk_queue_depth,
ae52e7f0 133 .can_queue = ARCMSR_MAX_FREECCB_NUM,
cdd3cb15
NC		 134 .this_id = ARCMSR_SCSI_INITIATOR_ID,
135 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
136 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
1c57e86d
EC		 137 .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
138 .use_clustering = ENABLE_CLUSTERING,
139 .shost_attrs = arcmsr_host_attrs,
140};
1c57e86d
EC		 141static struct pci_device_id arcmsr_device_id_table[] = {
142 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110)},
143 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120)},
144 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130)},
145 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160)},
146 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170)},
1a4f550a
NC		 147 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200)},
148 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201)},
149 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202)},
1c57e86d
EC		 150 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210)},
151 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220)},
152 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230)},
153 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260)},
154 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270)},
155 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280)},
156 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380)},
157 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381)},
158 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680)},
159 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681)},
ae52e7f0 160 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880)},
1c57e86d
EC		 161 {0, 0}, /* Terminating entry */
162};
163MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
164static struct pci_driver arcmsr_pci_driver = {
165 .name = "arcmsr",
cdd3cb15 166 .id_table = arcmsr_device_id_table,
1c57e86d
EC		 167 .probe = arcmsr_probe,
168 .remove = arcmsr_remove,
a1f6e021 169 .shutdown = arcmsr_shutdown,
1c57e86d 170};
cdd3cb15
NC		 171/*
172****************************************************************************
173****************************************************************************
174*/
1c57e86d 175
cdd3cb15 176static void arcmsr_free_hbb_mu(struct AdapterControlBlock *acb)
ae52e7f0
NC		 177{
178 switch (acb->adapter_type) {
179 case ACB_ADAPTER_TYPE_A:
cdd3cb15 180 case ACB_ADAPTER_TYPE_C:
ae52e7f0
NC		 181 break;
182 case ACB_ADAPTER_TYPE_B:{
cdd3cb15
NC		 183 dma_free_coherent(&acb->pdev->dev,
184 sizeof(struct MessageUnit_B),
185 acb->pmuB, acb->dma_coherent_handle_hbb_mu);
ae52e7f0
NC		 186 }
187 }
188}
189
190static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
191{
192 struct pci_dev *pdev = acb->pdev;
cdd3cb15 193 switch (acb->adapter_type){
ae52e7f0 194 case ACB_ADAPTER_TYPE_A:{
cdd3cb15 195 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
ae52e7f0
NC		 196 if (!acb->pmuA) {
197 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
198 return false;
199 }
200 break;
201 }
202 case ACB_ADAPTER_TYPE_B:{
203 void __iomem *mem_base0, *mem_base1;
204 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
205 if (!mem_base0) {
206 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
207 return false;
208 }
209 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
210 if (!mem_base1) {
211 iounmap(mem_base0);
212 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
213 return false;
214 }
215 acb->mem_base0 = mem_base0;
216 acb->mem_base1 = mem_base1;
cdd3cb15
NC		 217 break;
218 }
219 case ACB_ADAPTER_TYPE_C:{
220 acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
221 if (!acb->pmuC) {
222 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
223 return false;
224 }
225 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
226 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
227 return true;
228 }
229 break;
ae52e7f0
NC		 230 }
231 }
232 return true;
233}
234
235static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
236{
237 switch (acb->adapter_type) {
cdd3cb15
NC		 238 case ACB_ADAPTER_TYPE_A:{
239 iounmap(acb->pmuA);
240 }
241 break;
242 case ACB_ADAPTER_TYPE_B:{
243 iounmap(acb->mem_base0);
244 iounmap(acb->mem_base1);
245 }
246
247 break;
248 case ACB_ADAPTER_TYPE_C:{
249 iounmap(acb->pmuC);
250 }
ae52e7f0
NC		 251 }
252}
253
7d12e780 254static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
1c57e86d
EC		 255{
256 irqreturn_t handle_state;
1a4f550a 257 struct AdapterControlBlock *acb = dev_id;
1c57e86d 258
1c57e86d 259 handle_state = arcmsr_interrupt(acb);
1c57e86d
EC		 260 return handle_state;
261}
262
263static int arcmsr_bios_param(struct scsi_device *sdev,
264 struct block_device *bdev, sector_t capacity, int *geom)
265{
266 int ret, heads, sectors, cylinders, total_capacity;
267 unsigned char *buffer;/* return copy of block device's partition table */
268
269 buffer = scsi_bios_ptable(bdev);
270 if (buffer) {
271 ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
272 kfree(buffer);
273 if (ret != -1)
274 return ret;
275 }
276 total_capacity = capacity;
277 heads = 64;
278 sectors = 32;
279 cylinders = total_capacity / (heads * sectors);
280 if (cylinders > 1024) {
281 heads = 255;
282 sectors = 63;
283 cylinders = total_capacity / (heads * sectors);
284 }
285 geom[0] = heads;
286 geom[1] = sectors;
287 geom[2] = cylinders;
288 return 0;
289}
290
1a4f550a 291static void arcmsr_define_adapter_type(struct AdapterControlBlock *acb)
1c57e86d
EC		 292{
293 struct pci_dev *pdev = acb->pdev;
1a4f550a
NC		 294 u16 dev_id;
295 pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
ae52e7f0 296 acb->dev_id = dev_id;
1a4f550a 297 switch (dev_id) {
cdd3cb15
NC		 298 case 0x1880: {
299 acb->adapter_type = ACB_ADAPTER_TYPE_C;
300 }
301 break;
302 case 0x1201: {
1a4f550a
NC		 303 acb->adapter_type = ACB_ADAPTER_TYPE_B;
304 }
305 break;
306
cdd3cb15 307 default: acb->adapter_type = ACB_ADAPTER_TYPE_A;
1a4f550a 308 }
8b7eb86f 309}
1a4f550a 310
ae52e7f0
NC		 311static uint8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
312{
313 struct MessageUnit_A __iomem *reg = acb->pmuA;
8b7eb86f
TH		 314 int i;
315
316 for (i = 0; i < 2000; i++) {
317 if (readl(&reg->outbound_intstatus) &
318 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
319 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
320 &reg->outbound_intstatus);
321 return true;
322 }
323 msleep(10);
324 } /* max 20 seconds */
ae52e7f0 325
cdd3cb15 326 return false;
ae52e7f0
NC		 327}
328
329static uint8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
1a4f550a 330{
ae52e7f0 331 struct MessageUnit_B *reg = acb->pmuB;
8b7eb86f
TH		 332 int i;
333
334 for (i = 0; i < 2000; i++) {
335 if (readl(reg->iop2drv_doorbell)
336 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
337 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
338 reg->iop2drv_doorbell);
339 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
340 reg->drv2iop_doorbell);
341 return true;
342 }
343 msleep(10);
344 } /* max 20 seconds */
ae52e7f0 345
cdd3cb15 346 return false;
ae52e7f0
NC		 347}
348
cdd3cb15
NC		 349static uint8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *pACB)
350{
351 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
8b7eb86f
TH		 352 int i;
353
354 for (i = 0; i < 2000; i++) {
355 if (readl(&phbcmu->outbound_doorbell)
356 & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
357 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
358 &phbcmu->outbound_doorbell_clear); /*clear interrupt*/
359 return true;
360 }
361 msleep(10);
362 } /* max 20 seconds */
363
cdd3cb15
NC		 364 return false;
365}
8b7eb86f 366
ae52e7f0
NC		 367static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
368{
369 struct MessageUnit_A __iomem *reg = acb->pmuA;
370 int retry_count = 30;
ae52e7f0
NC		 371 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
372 do {
cdd3cb15 373 if (arcmsr_hba_wait_msgint_ready(acb))
ae52e7f0
NC		 374 break;
375 else {
376 retry_count--;
377 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
378 timeout, retry count down = %d \n", acb->host->host_no, retry_count);
379 }
380 } while (retry_count != 0);
381}
382
383static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
384{
385 struct MessageUnit_B *reg = acb->pmuB;
386 int retry_count = 30;
ae52e7f0
NC		 387 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
388 do {
cdd3cb15 389 if (arcmsr_hbb_wait_msgint_ready(acb))
ae52e7f0
NC		 390 break;
391 else {
392 retry_count--;
393 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
394 timeout,retry count down = %d \n", acb->host->host_no, retry_count);
395 }
396 } while (retry_count != 0);
397}
398
cdd3cb15
NC		 399static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *pACB)
400{
401 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
402 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
403 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
404 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
405 do {
406 if (arcmsr_hbc_wait_msgint_ready(pACB)) {
407 break;
408 } else {
409 retry_count--;
410 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
411 timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
412 }
413 } while (retry_count != 0);
414 return;
415}
ae52e7f0
NC		 416static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
417{
1a4f550a 418 switch (acb->adapter_type) {
1c57e86d 419
1a4f550a 420 case ACB_ADAPTER_TYPE_A: {
ae52e7f0
NC		 421 arcmsr_flush_hba_cache(acb);
422 }
423 break;
1a4f550a 424
ae52e7f0
NC		 425 case ACB_ADAPTER_TYPE_B: {
426 arcmsr_flush_hbb_cache(acb);
1a4f550a 427 }
cdd3cb15
NC		 428 break;
429 case ACB_ADAPTER_TYPE_C: {
430 arcmsr_flush_hbc_cache(acb);
431 }
ae52e7f0
NC		 432 }
433}
1a4f550a 434
ae52e7f0
NC		 435static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
436{
cdd3cb15
NC		 437 struct pci_dev *pdev = acb->pdev;
438 void *dma_coherent;
439 dma_addr_t dma_coherent_handle;
440 struct CommandControlBlock *ccb_tmp;
441 int i = 0, j = 0;
442 dma_addr_t cdb_phyaddr;
87f76152 443 unsigned long roundup_ccbsize;
cdd3cb15
NC		 444 unsigned long max_xfer_len;
445 unsigned long max_sg_entrys;
446 uint32_t firm_config_version;
87f76152 447
cdd3cb15
NC		 448 for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
449 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
450 acb->devstate[i][j] = ARECA_RAID_GONE;
451
452 max_xfer_len = ARCMSR_MAX_XFER_LEN;
453 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
454 firm_config_version = acb->firm_cfg_version;
455 if((firm_config_version & 0xFF) >= 3){
456 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
87f76152 457 max_sg_entrys = (max_xfer_len/4096);
cdd3cb15
NC		 458 }
459 acb->host->max_sectors = max_xfer_len/512;
460 acb->host->sg_tablesize = max_sg_entrys;
461 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
87f76152 462 acb->uncache_size = roundup_ccbsize * ARCMSR_MAX_FREECCB_NUM;
cdd3cb15
NC		 463 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
464 if(!dma_coherent){
87f76152 465 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
cdd3cb15
NC		 466 return -ENOMEM;
467 }
468 acb->dma_coherent = dma_coherent;
469 acb->dma_coherent_handle = dma_coherent_handle;
470 memset(dma_coherent, 0, acb->uncache_size);
cdd3cb15
NC		 471 ccb_tmp = dma_coherent;
472 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
473 for(i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++){
474 cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
475 ccb_tmp->cdb_phyaddr_pattern = ((acb->adapter_type == ACB_ADAPTER_TYPE_C) ? cdb_phyaddr : (cdb_phyaddr >> 5));
476 acb->pccb_pool[i] = ccb_tmp;
477 ccb_tmp->acb = acb;
478 INIT_LIST_HEAD(&ccb_tmp->list);
479 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
480 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
481 dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;
1a4f550a 482 }
1c57e86d
EC		 483 return 0;
484}
36b83ded 485
cdd3cb15
NC		 486static void arcmsr_message_isr_bh_fn(struct work_struct *work)
487{
488 struct AdapterControlBlock *acb = container_of(work,struct AdapterControlBlock, arcmsr_do_message_isr_bh);
36b83ded
NC		 489 switch (acb->adapter_type) {
490 case ACB_ADAPTER_TYPE_A: {
491
492 struct MessageUnit_A __iomem *reg = acb->pmuA;
493 char *acb_dev_map = (char *)acb->device_map;
cdd3cb15
NC		 494 uint32_t __iomem *signature = (uint32_t __iomem*) (&reg->message_rwbuffer[0]);
495 char __iomem *devicemap = (char __iomem*) (&reg->message_rwbuffer[21]);
36b83ded
NC		 496 int target, lun;
497 struct scsi_device *psdev;
498 char diff;
499
500 atomic_inc(&acb->rq_map_token);
501 if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
cdd3cb15 502 for(target = 0; target < ARCMSR_MAX_TARGETID -1; target++) {
36b83ded
NC		 503 diff = (*acb_dev_map)^readb(devicemap);
504 if (diff != 0) {
505 char temp;
506 *acb_dev_map = readb(devicemap);
cdd3cb15
NC		 507 temp =*acb_dev_map;
508 for(lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
509 if((temp & 0x01)==1 && (diff & 0x01) == 1) {
36b83ded 510 scsi_add_device(acb->host, 0, target, lun);
cdd3cb15 511 }else if((temp & 0x01) == 0 && (diff & 0x01) == 1) {
36b83ded 512 psdev = scsi_device_lookup(acb->host, 0, target, lun);
cdd3cb15 513 if (psdev != NULL ) {
36b83ded
NC		 514 scsi_remove_device(psdev);
515 scsi_device_put(psdev);
516 }
517 }
518 temp >>= 1;
519 diff >>= 1;
520 }
521 }
522 devicemap++;
523 acb_dev_map++;
524 }
525 }
526 break;
527 }
528
529 case ACB_ADAPTER_TYPE_B: {
530 struct MessageUnit_B *reg = acb->pmuB;
531 char *acb_dev_map = (char *)acb->device_map;
cdd3cb15
NC		 532 uint32_t __iomem *signature = (uint32_t __iomem*)(&reg->message_rwbuffer[0]);
533 char __iomem *devicemap = (char __iomem*)(&reg->message_rwbuffer[21]);
534 int target, lun;
535 struct scsi_device *psdev;
536 char diff;
537
538 atomic_inc(&acb->rq_map_token);
539 if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
540 for(target = 0; target < ARCMSR_MAX_TARGETID -1; target++) {
541 diff = (*acb_dev_map)^readb(devicemap);
542 if (diff != 0) {
543 char temp;
544 *acb_dev_map = readb(devicemap);
545 temp =*acb_dev_map;
546 for(lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
547 if((temp & 0x01)==1 && (diff & 0x01) == 1) {
548 scsi_add_device(acb->host, 0, target, lun);
549 }else if((temp & 0x01) == 0 && (diff & 0x01) == 1) {
550 psdev = scsi_device_lookup(acb->host, 0, target, lun);
551 if (psdev != NULL ) {
552 scsi_remove_device(psdev);
553 scsi_device_put(psdev);
554 }
555 }
556 temp >>= 1;
557 diff >>= 1;
558 }
559 }
560 devicemap++;
561 acb_dev_map++;
562 }
563 }
564 }
565 break;
566 case ACB_ADAPTER_TYPE_C: {
567 struct MessageUnit_C *reg = acb->pmuC;
568 char *acb_dev_map = (char *)acb->device_map;
569 uint32_t __iomem *signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
570 char __iomem *devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
36b83ded
NC		 571 int target, lun;
572 struct scsi_device *psdev;
573 char diff;
574
575 atomic_inc(&acb->rq_map_token);
576 if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
577 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) {
578 diff = (*acb_dev_map)^readb(devicemap);
579 if (diff != 0) {
580 char temp;
581 *acb_dev_map = readb(devicemap);
582 temp = *acb_dev_map;
583 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
584 if ((temp & 0x01) == 1 && (diff & 0x01) == 1) {
585 scsi_add_device(acb->host, 0, target, lun);
586 } else if ((temp & 0x01) == 0 && (diff & 0x01) == 1) {
587 psdev = scsi_device_lookup(acb->host, 0, target, lun);
588 if (psdev != NULL) {
589 scsi_remove_device(psdev);
590 scsi_device_put(psdev);
591 }
592 }
593 temp >>= 1;
594 diff >>= 1;
595 }
596 }
597 devicemap++;
598 acb_dev_map++;
599 }
600 }
601 }
602 }
603}
1c57e86d 604
ae52e7f0 605static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1c57e86d
EC		 606{
607 struct Scsi_Host *host;
608 struct AdapterControlBlock *acb;
cdd3cb15 609 uint8_t bus,dev_fun;
1c57e86d 610 int error;
1c57e86d 611 error = pci_enable_device(pdev);
cdd3cb15 612 if(error){
ae52e7f0
NC		 613 return -ENODEV;
614 }
615 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
cdd3cb15
NC		 616 if(!host){
617 goto pci_disable_dev;
1c57e86d 618 }
6a35528a 619 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
cdd3cb15 620 if(error){
284901a9 621 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cdd3cb15 622 if(error){
1c57e86d
EC		 623 printk(KERN_WARNING
624 "scsi%d: No suitable DMA mask available\n",
625 host->host_no);
ae52e7f0 626 goto scsi_host_release;
1c57e86d
EC		 627 }
628 }
ae52e7f0 629 init_waitqueue_head(&wait_q);
1c57e86d
EC		 630 bus = pdev->bus->number;
631 dev_fun = pdev->devfn;
ae52e7f0 632 acb = (struct AdapterControlBlock *) host->hostdata;
cdd3cb15 633 memset(acb,0,sizeof(struct AdapterControlBlock));
1c57e86d 634 acb->pdev = pdev;
ae52e7f0 635 acb->host = host;
1c57e86d 636 host->max_lun = ARCMSR_MAX_TARGETLUN;
cdd3cb15
NC		 637 host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
638 host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
639 host->can_queue = ARCMSR_MAX_FREECCB_NUM; /* max simultaneous cmds */
640 host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
1c57e86d
EC		 641 host->this_id = ARCMSR_SCSI_INITIATOR_ID;
642 host->unique_id = (bus << 8) | dev_fun;
ae52e7f0
NC		 643 pci_set_drvdata(pdev, host);
644 pci_set_master(pdev);
1c57e86d 645 error = pci_request_regions(pdev, "arcmsr");
cdd3cb15 646 if(error){
ae52e7f0 647 goto scsi_host_release;
1c57e86d 648 }
ae52e7f0
NC		 649 spin_lock_init(&acb->eh_lock);
650 spin_lock_init(&acb->ccblist_lock);
1c57e86d 651 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
cdd3cb15
NC		 652 ACB_F_MESSAGE_RQBUFFER_CLEARED |
653 ACB_F_MESSAGE_WQBUFFER_READED);
1c57e86d
EC		 654 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
655 INIT_LIST_HEAD(&acb->ccb_free_list);
ae52e7f0
NC		 656 arcmsr_define_adapter_type(acb);
657 error = arcmsr_remap_pciregion(acb);
cdd3cb15 658 if(!error){
ae52e7f0
NC		 659 goto pci_release_regs;
660 }
661 error = arcmsr_get_firmware_spec(acb);
cdd3cb15 662 if(!error){
ae52e7f0
NC		 663 goto unmap_pci_region;
664 }
1c57e86d 665 error = arcmsr_alloc_ccb_pool(acb);
cdd3cb15 666 if(error){
ae52e7f0
NC		 667 goto free_hbb_mu;
668 }
36b83ded 669 arcmsr_iop_init(acb);
1c57e86d 670 error = scsi_add_host(host, &pdev->dev);
cdd3cb15 671 if(error){
ae52e7f0
NC		 672 goto RAID_controller_stop;
673 }
674 error = request_irq(pdev->irq, arcmsr_do_interrupt, IRQF_SHARED, "arcmsr", acb);
cdd3cb15 675 if(error){
ae52e7f0
NC		 676 goto scsi_host_remove;
677 }
678 host->irq = pdev->irq;
cdd3cb15 679 scsi_scan_host(host);
ae52e7f0 680 INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
36b83ded 681 atomic_set(&acb->rq_map_token, 16);
ae52e7f0
NC		 682 atomic_set(&acb->ante_token_value, 16);
683 acb->fw_flag = FW_NORMAL;
36b83ded 684 init_timer(&acb->eternal_timer);
ae52e7f0 685 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
36b83ded
NC		 686 acb->eternal_timer.data = (unsigned long) acb;
687 acb->eternal_timer.function = &arcmsr_request_device_map;
688 add_timer(&acb->eternal_timer);
cdd3cb15 689 if(arcmsr_alloc_sysfs_attr(acb))
ae52e7f0 690 goto out_free_sysfs;
1c57e86d 691 return 0;
cdd3cb15 692out_free_sysfs:
ae52e7f0
NC		 693scsi_host_remove:
694 scsi_remove_host(host);
695RAID_controller_stop:
696 arcmsr_stop_adapter_bgrb(acb);
697 arcmsr_flush_adapter_cache(acb);
1c57e86d 698 arcmsr_free_ccb_pool(acb);
ae52e7f0 699free_hbb_mu:
cdd3cb15 700 arcmsr_free_hbb_mu(acb);
ae52e7f0
NC		 701unmap_pci_region:
702 arcmsr_unmap_pciregion(acb);
703pci_release_regs:
1c57e86d 704 pci_release_regions(pdev);
ae52e7f0 705scsi_host_release:
1c57e86d 706 scsi_host_put(host);
ae52e7f0 707pci_disable_dev:
1c57e86d 708 pci_disable_device(pdev);
ae52e7f0 709 return -ENODEV;
1a4f550a
NC		 710}
711
36b83ded 712static uint8_t arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
1c57e86d 713{
80da1adb 714 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 715 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
cdd3cb15 716 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 717 printk(KERN_NOTICE
718 "arcmsr%d: wait 'abort all outstanding command' timeout \n"
719 , acb->host->host_no);
cdd3cb15 720 return false;
36b83ded 721 }
cdd3cb15 722 return true;
1a4f550a
NC		 723}
724
36b83ded 725static uint8_t arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
1a4f550a 726{
80da1adb 727 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 728
ae52e7f0 729 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
cdd3cb15 730 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1c57e86d
EC		 731 printk(KERN_NOTICE
732 "arcmsr%d: wait 'abort all outstanding command' timeout \n"
733 , acb->host->host_no);
cdd3cb15 734 return false;
36b83ded 735 }
cdd3cb15
NC		 736 return true;
737}
738static uint8_t arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *pACB)
739{
740 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
741 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
742 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
743 if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
744 printk(KERN_NOTICE
745 "arcmsr%d: wait 'abort all outstanding command' timeout \n"
746 , pACB->host->host_no);
747 return false;
748 }
749 return true;
1c57e86d 750}
36b83ded 751static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
1a4f550a 752{
36b83ded 753 uint8_t rtnval = 0;
1a4f550a
NC		 754 switch (acb->adapter_type) {
755 case ACB_ADAPTER_TYPE_A: {
36b83ded 756 rtnval = arcmsr_abort_hba_allcmd(acb);
1a4f550a
NC		 757 }
758 break;
759
760 case ACB_ADAPTER_TYPE_B: {
36b83ded 761 rtnval = arcmsr_abort_hbb_allcmd(acb);
1a4f550a 762 }
cdd3cb15
NC		 763 break;
764
765 case ACB_ADAPTER_TYPE_C: {
766 rtnval = arcmsr_abort_hbc_allcmd(acb);
767 }
1a4f550a 768 }
36b83ded 769 return rtnval;
1a4f550a
NC		 770}
771
ae52e7f0
NC		 772static bool arcmsr_hbb_enable_driver_mode(struct AdapterControlBlock *pacb)
773{
774 struct MessageUnit_B *reg = pacb->pmuB;
ae52e7f0 775 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
cdd3cb15 776 if (!arcmsr_hbb_wait_msgint_ready(pacb)) {
ae52e7f0
NC		 777 printk(KERN_ERR "arcmsr%d: can't set driver mode. \n", pacb->host->host_no);
778 return false;
cdd3cb15
NC		 779 }
780 return true;
ae52e7f0
NC		 781}
782
1c57e86d
EC		 783static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
784{
1c57e86d
EC		 785 struct scsi_cmnd *pcmd = ccb->pcmd;
786
deff2627 787 scsi_dma_unmap(pcmd);
cdd3cb15 788}
1c57e86d 789
ae52e7f0 790static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
1c57e86d
EC		 791{
792 struct AdapterControlBlock *acb = ccb->acb;
793 struct scsi_cmnd *pcmd = ccb->pcmd;
ae52e7f0 794 unsigned long flags;
ae52e7f0 795 atomic_dec(&acb->ccboutstandingcount);
1c57e86d 796 arcmsr_pci_unmap_dma(ccb);
1c57e86d 797 ccb->startdone = ARCMSR_CCB_DONE;
ae52e7f0 798 spin_lock_irqsave(&acb->ccblist_lock, flags);
1c57e86d 799 list_add_tail(&ccb->list, &acb->ccb_free_list);
ae52e7f0 800 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 801 pcmd->scsi_done(pcmd);
802}
803
1a4f550a
NC		 804static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
805{
806
807 struct scsi_cmnd *pcmd = ccb->pcmd;
808 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
1a4f550a
NC		 809 pcmd->result = DID_OK << 16;
810 if (sensebuffer) {
811 int sense_data_length =
b80ca4f7
FT		 812 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
813 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
814 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
1a4f550a
NC		 815 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
816 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
817 sensebuffer->Valid = 1;
818 }
819}
820
821static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
822{
823 u32 orig_mask = 0;
cdd3cb15 824 switch (acb->adapter_type) {
1a4f550a 825 case ACB_ADAPTER_TYPE_A : {
80da1adb 826 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 827 orig_mask = readl(&reg->outbound_intmask);
1a4f550a
NC		 828 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
829 &reg->outbound_intmask);
830 }
831 break;
1a4f550a 832 case ACB_ADAPTER_TYPE_B : {
80da1adb 833 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0
NC		 834 orig_mask = readl(reg->iop2drv_doorbell_mask);
835 writel(0, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 836 }
837 break;
cdd3cb15
NC		 838 case ACB_ADAPTER_TYPE_C:{
839 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
840 /* disable all outbound interrupt */
841 orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
842 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
843 }
844 break;
1a4f550a
NC		 845 }
846 return orig_mask;
847}
848
cdd3cb15
NC		 849static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
850 struct CommandControlBlock *ccb, bool error)
1a4f550a 851{
1a4f550a
NC		 852 uint8_t id, lun;
853 id = ccb->pcmd->device->id;
854 lun = ccb->pcmd->device->lun;
cdd3cb15 855 if (!error) {
1a4f550a
NC		 856 if (acb->devstate[id][lun] == ARECA_RAID_GONE)
857 acb->devstate[id][lun] = ARECA_RAID_GOOD;
7968f194
JL		 858 ccb->pcmd->result = DID_OK << 16;
859 arcmsr_ccb_complete(ccb);
cdd3cb15 860 }else{
1a4f550a
NC		 861 switch (ccb->arcmsr_cdb.DeviceStatus) {
862 case ARCMSR_DEV_SELECT_TIMEOUT: {
863 acb->devstate[id][lun] = ARECA_RAID_GONE;
864 ccb->pcmd->result = DID_NO_CONNECT << 16;
ae52e7f0 865 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 866 }
867 break;
868
869 case ARCMSR_DEV_ABORTED:
870
871 case ARCMSR_DEV_INIT_FAIL: {
872 acb->devstate[id][lun] = ARECA_RAID_GONE;
873 ccb->pcmd->result = DID_BAD_TARGET << 16;
ae52e7f0 874 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 875 }
876 break;
877
878 case ARCMSR_DEV_CHECK_CONDITION: {
879 acb->devstate[id][lun] = ARECA_RAID_GOOD;
880 arcmsr_report_sense_info(ccb);
ae52e7f0 881 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 882 }
883 break;
884
885 default:
cdd3cb15
NC		 886 printk(KERN_NOTICE
887 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
888 but got unknown DeviceStatus = 0x%x \n"
889 , acb->host->host_no
890 , id
891 , lun
892 , ccb->arcmsr_cdb.DeviceStatus);
893 acb->devstate[id][lun] = ARECA_RAID_GONE;
894 ccb->pcmd->result = DID_NO_CONNECT << 16;
895 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 896 break;
897 }
898 }
899}
900
cdd3cb15 901static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
1a4f550a 902{
ae52e7f0 903 int id, lun;
cdd3cb15
NC		 904 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
905 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
906 struct scsi_cmnd *abortcmd = pCCB->pcmd;
1a4f550a 907 if (abortcmd) {
ae52e7f0 908 id = abortcmd->device->id;
cdd3cb15 909 lun = abortcmd->device->lun;
1a4f550a 910 abortcmd->result |= DID_ABORT << 16;
cdd3cb15
NC		 911 arcmsr_ccb_complete(pCCB);
912 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
913 acb->host->host_no, pCCB);
1a4f550a 914 }
cdd3cb15 915 return;
1a4f550a
NC		 916 }
917 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
918 done acb = '0x%p'"
919 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
920 " ccboutstandingcount = %d \n"
921 , acb->host->host_no
922 , acb
cdd3cb15
NC		 923 , pCCB
924 , pCCB->acb
925 , pCCB->startdone
1a4f550a 926 , atomic_read(&acb->ccboutstandingcount));
cdd3cb15 927 return;
97b99127 928 }
cdd3cb15 929 arcmsr_report_ccb_state(acb, pCCB, error);
1a4f550a
NC		 930}
931
932static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
933{
934 int i = 0;
935 uint32_t flag_ccb;
cdd3cb15
NC		 936 struct ARCMSR_CDB *pARCMSR_CDB;
937 bool error;
938 struct CommandControlBlock *pCCB;
1a4f550a
NC		 939 switch (acb->adapter_type) {
940
941 case ACB_ADAPTER_TYPE_A: {
80da1adb 942 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 943 uint32_t outbound_intstatus;
80da1adb 944 outbound_intstatus = readl(&reg->outbound_intstatus) &
1a4f550a
NC		 945 acb->outbound_int_enable;
946 /*clear and abort all outbound posted Q*/
947 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
cdd3cb15 948 while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
1a4f550a 949 && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
cdd3cb15
NC		 950 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
951 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
952 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
953 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 954 }
955 }
956 break;
957
958 case ACB_ADAPTER_TYPE_B: {
80da1adb 959 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 960 /*clear all outbound posted Q*/
97b99127 961 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
1a4f550a
NC		 962 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
963 if ((flag_ccb = readl(&reg->done_qbuffer[i])) != 0) {
964 writel(0, &reg->done_qbuffer[i]);
cdd3cb15
NC		 965 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
966 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
967 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
968 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a 969 }
cdd3cb15 970 reg->post_qbuffer[i] = 0;
1a4f550a
NC		 971 }
972 reg->doneq_index = 0;
973 reg->postq_index = 0;
974 }
975 break;
cdd3cb15
NC		 976 case ACB_ADAPTER_TYPE_C: {
977 struct MessageUnit_C *reg = acb->pmuC;
978 struct ARCMSR_CDB *pARCMSR_CDB;
979 uint32_t flag_ccb, ccb_cdb_phy;
980 bool error;
981 struct CommandControlBlock *pCCB;
982 while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
983 /*need to do*/
984 flag_ccb = readl(&reg->outbound_queueport_low);
985 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
986 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/
987 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
988 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
989 arcmsr_drain_donequeue(acb, pCCB, error);
990 }
991 }
1a4f550a
NC		 992 }
993}
1c57e86d
EC		 994static void arcmsr_remove(struct pci_dev *pdev)
995{
996 struct Scsi_Host *host = pci_get_drvdata(pdev);
997 struct AdapterControlBlock *acb =
998 (struct AdapterControlBlock *) host->hostdata;
1c57e86d 999 int poll_count = 0;
1c57e86d
EC		 1000 arcmsr_free_sysfs_attr(acb);
1001 scsi_remove_host(host);
43829731 1002 flush_work(&acb->arcmsr_do_message_isr_bh);
36b83ded
NC		 1003 del_timer_sync(&acb->eternal_timer);
1004 arcmsr_disable_outbound_ints(acb);
1c57e86d 1005 arcmsr_stop_adapter_bgrb(acb);
cdd3cb15 1006 arcmsr_flush_adapter_cache(acb);
1c57e86d
EC		 1007 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
1008 acb->acb_flags &= ~ACB_F_IOP_INITED;
1009
cdd3cb15 1010 for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++){
1c57e86d
EC		 1011 if (!atomic_read(&acb->ccboutstandingcount))
1012 break;
1a4f550a 1013 arcmsr_interrupt(acb);/* FIXME: need spinlock */
1c57e86d
EC		 1014 msleep(25);
1015 }
1016
1017 if (atomic_read(&acb->ccboutstandingcount)) {
1018 int i;
1019
1020 arcmsr_abort_allcmd(acb);
1a4f550a 1021 arcmsr_done4abort_postqueue(acb);
1c57e86d
EC		 1022 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
1023 struct CommandControlBlock *ccb = acb->pccb_pool[i];
1024 if (ccb->startdone == ARCMSR_CCB_START) {
1025 ccb->startdone = ARCMSR_CCB_ABORTED;
1026 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 1027 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 1028 }
1029 }
1030 }
1c57e86d 1031 free_irq(pdev->irq, acb);
1c57e86d 1032 arcmsr_free_ccb_pool(acb);
cdd3cb15
NC		 1033 arcmsr_free_hbb_mu(acb);
1034 arcmsr_unmap_pciregion(acb);
1c57e86d 1035 pci_release_regions(pdev);
cdd3cb15 1036 scsi_host_put(host);
1c57e86d 1037 pci_disable_device(pdev);
1c57e86d
EC		 1038}
1039
1040static void arcmsr_shutdown(struct pci_dev *pdev)
1041{
1042 struct Scsi_Host *host = pci_get_drvdata(pdev);
1043 struct AdapterControlBlock *acb =
1044 (struct AdapterControlBlock *)host->hostdata;
36b83ded
NC		 1045 del_timer_sync(&acb->eternal_timer);
1046 arcmsr_disable_outbound_ints(acb);
43829731 1047 flush_work(&acb->arcmsr_do_message_isr_bh);
1c57e86d
EC		 1048 arcmsr_stop_adapter_bgrb(acb);
1049 arcmsr_flush_adapter_cache(acb);
1050}
1051
1052static int arcmsr_module_init(void)
1053{
1054 int error = 0;
1c57e86d
EC		 1055 error = pci_register_driver(&arcmsr_pci_driver);
1056 return error;
1057}
1058
1059static void arcmsr_module_exit(void)
1060{
1061 pci_unregister_driver(&arcmsr_pci_driver);
1062}
1063module_init(arcmsr_module_init);
1064module_exit(arcmsr_module_exit);
1065
36b83ded 1066static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
1a4f550a 1067 u32 intmask_org)
1c57e86d 1068{
1c57e86d 1069 u32 mask;
1a4f550a 1070 switch (acb->adapter_type) {
1c57e86d 1071
cdd3cb15 1072 case ACB_ADAPTER_TYPE_A: {
80da1adb 1073 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 1074 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
36b83ded
NC		 1075 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
1076 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
1a4f550a
NC		 1077 writel(mask, &reg->outbound_intmask);
1078 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
1079 }
1080 break;
1c57e86d 1081
cdd3cb15 1082 case ACB_ADAPTER_TYPE_B: {
80da1adb 1083 struct MessageUnit_B *reg = acb->pmuB;
36b83ded
NC		 1084 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
1085 ARCMSR_IOP2DRV_DATA_READ_OK |
1086 ARCMSR_IOP2DRV_CDB_DONE |
1087 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
ae52e7f0 1088 writel(mask, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 1089 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
1090 }
cdd3cb15
NC		 1091 break;
1092 case ACB_ADAPTER_TYPE_C: {
1093 struct MessageUnit_C *reg = acb->pmuC;
1094 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
1095 writel(intmask_org & mask, &reg->host_int_mask);
1096 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
1097 }
1c57e86d
EC		 1098 }
1099}
1100
76d78300 1101static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
1a4f550a 1102 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
1c57e86d 1103{
1a4f550a
NC		 1104 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1105 int8_t *psge = (int8_t *)&arcmsr_cdb->u;
80da1adb 1106 __le32 address_lo, address_hi;
1a4f550a 1107 int arccdbsize = 0x30;
ae52e7f0 1108 __le32 length = 0;
cdd3cb15 1109 int i;
ae52e7f0 1110 struct scatterlist *sg;
1a4f550a 1111 int nseg;
1c57e86d 1112 ccb->pcmd = pcmd;
1a4f550a 1113 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1c57e86d
EC		 1114 arcmsr_cdb->TargetID = pcmd->device->id;
1115 arcmsr_cdb->LUN = pcmd->device->lun;
1116 arcmsr_cdb->Function = 1;
ae52e7f0 1117 arcmsr_cdb->Context = 0;
1c57e86d 1118 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
deff2627
FT		 1119
1120 nseg = scsi_dma_map(pcmd);
cdd3cb15 1121 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
76d78300 1122 return FAILED;
cdd3cb15
NC		 1123 scsi_for_each_sg(pcmd, sg, nseg, i) {
1124 /* Get the physical address of the current data pointer */
1125 length = cpu_to_le32(sg_dma_len(sg));
1126 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
1127 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
1128 if (address_hi == 0) {
1129 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1130
1131 pdma_sg->address = address_lo;
1132 pdma_sg->length = length;
1133 psge += sizeof (struct SG32ENTRY);
1134 arccdbsize += sizeof (struct SG32ENTRY);
1135 } else {
1136 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1c57e86d 1137
cdd3cb15
NC		 1138 pdma_sg->addresshigh = address_hi;
1139 pdma_sg->address = address_lo;
1140 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
1141 psge += sizeof (struct SG64ENTRY);
1142 arccdbsize += sizeof (struct SG64ENTRY);
1c57e86d 1143 }
cdd3cb15
NC		 1144 }
1145 arcmsr_cdb->sgcount = (uint8_t)nseg;
1146 arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
ae52e7f0 1147 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
cdd3cb15
NC		 1148 if ( arccdbsize > 256)
1149 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
c32e061f 1150 if (pcmd->sc_data_direction == DMA_TO_DEVICE)
1c57e86d 1151 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
cdd3cb15 1152 ccb->arc_cdb_size = arccdbsize;
76d78300 1153 return SUCCESS;
1c57e86d
EC		 1154}
1155
1156static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
1157{
cdd3cb15 1158 uint32_t cdb_phyaddr_pattern = ccb->cdb_phyaddr_pattern;
1c57e86d 1159 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1c57e86d
EC		 1160 atomic_inc(&acb->ccboutstandingcount);
1161 ccb->startdone = ARCMSR_CCB_START;
1a4f550a
NC		 1162 switch (acb->adapter_type) {
1163 case ACB_ADAPTER_TYPE_A: {
80da1adb 1164 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1165
1166 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
cdd3cb15 1167 writel(cdb_phyaddr_pattern | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
1c57e86d 1168 &reg->inbound_queueport);
1a4f550a 1169 else {
cdd3cb15 1170 writel(cdb_phyaddr_pattern, &reg->inbound_queueport);
1a4f550a
NC		 1171 }
1172 }
1173 break;
1c57e86d 1174
1a4f550a 1175 case ACB_ADAPTER_TYPE_B: {
80da1adb 1176 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1177 uint32_t ending_index, index = reg->postq_index;
1c57e86d 1178
1a4f550a
NC		 1179 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
1180 writel(0, &reg->post_qbuffer[ending_index]);
1181 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
cdd3cb15 1182 writel(cdb_phyaddr_pattern | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,\
1a4f550a 1183 &reg->post_qbuffer[index]);
cdd3cb15
NC		 1184 } else {
1185 writel(cdb_phyaddr_pattern, &reg->post_qbuffer[index]);
1a4f550a
NC		 1186 }
1187 index++;
1188 index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
1189 reg->postq_index = index;
ae52e7f0 1190 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
1c57e86d 1191 }
1a4f550a 1192 break;
cdd3cb15
NC		 1193 case ACB_ADAPTER_TYPE_C: {
1194 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)acb->pmuC;
1195 uint32_t ccb_post_stamp, arc_cdb_size;
1196
1197 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
1198 ccb_post_stamp = (cdb_phyaddr_pattern | ((arc_cdb_size - 1) >> 6) | 1);
1199 if (acb->cdb_phyaddr_hi32) {
1200 writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high);
1201 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1202 } else {
1203 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1204 }
1205 }
1c57e86d
EC		 1206 }
1207}
1208
1a4f550a 1209static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1c57e86d 1210{
80da1adb 1211 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d
EC		 1212 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1213 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
cdd3cb15 1214 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 1215 printk(KERN_NOTICE
1216 "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1217 , acb->host->host_no);
1218 }
1219}
1220
1221static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1222{
80da1adb 1223 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1224 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
ae52e7f0 1225 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
1a4f550a 1226
cdd3cb15 1227 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1c57e86d
EC		 1228 printk(KERN_NOTICE
1229 "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1230 , acb->host->host_no);
1a4f550a
NC		 1231 }
1232}
1233
cdd3cb15
NC		 1234static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *pACB)
1235{
1236 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
1237 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1238 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
1239 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
1240 if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
1241 printk(KERN_NOTICE
1242 "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1243 , pACB->host->host_no);
1244 }
1245 return;
1246}
1a4f550a
NC		 1247static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1248{
1249 switch (acb->adapter_type) {
1250 case ACB_ADAPTER_TYPE_A: {
1251 arcmsr_stop_hba_bgrb(acb);
1252 }
1253 break;
1254
1255 case ACB_ADAPTER_TYPE_B: {
1256 arcmsr_stop_hbb_bgrb(acb);
1257 }
1258 break;
cdd3cb15
NC		 1259 case ACB_ADAPTER_TYPE_C: {
1260 arcmsr_stop_hbc_bgrb(acb);
1261 }
1a4f550a 1262 }
1c57e86d
EC		 1263}
1264
1265static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
1266{
cdd3cb15 1267 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
1c57e86d
EC		 1268}
1269
1a4f550a 1270void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1c57e86d 1271{
1a4f550a
NC		 1272 switch (acb->adapter_type) {
1273 case ACB_ADAPTER_TYPE_A: {
80da1adb 1274 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1275 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
1276 }
1277 break;
1c57e86d 1278
1a4f550a 1279 case ACB_ADAPTER_TYPE_B: {
80da1adb 1280 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1281 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1c57e86d 1282 }
1a4f550a 1283 break;
cdd3cb15
NC		 1284 case ACB_ADAPTER_TYPE_C: {
1285 struct MessageUnit_C __iomem *reg = acb->pmuC;
1286 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
1287 }
1c57e86d 1288 }
1a4f550a
NC		 1289}
1290
1291static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1292{
1293 switch (acb->adapter_type) {
1294 case ACB_ADAPTER_TYPE_A: {
80da1adb 1295 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 1296 /*
1a4f550a
NC		 1297 ** push inbound doorbell tell iop, driver data write ok
1298 ** and wait reply on next hwinterrupt for next Qbuffer post
1c57e86d 1299 */
1a4f550a
NC		 1300 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
1301 }
1302 break;
1303
1304 case ACB_ADAPTER_TYPE_B: {
80da1adb 1305 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 1306 /*
1307 ** push inbound doorbell tell iop, driver data write ok
1308 ** and wait reply on next hwinterrupt for next Qbuffer post
1309 */
ae52e7f0 1310 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
1a4f550a
NC		 1311 }
1312 break;
cdd3cb15
NC		 1313 case ACB_ADAPTER_TYPE_C: {
1314 struct MessageUnit_C __iomem *reg = acb->pmuC;
1315 /*
1316 ** push inbound doorbell tell iop, driver data write ok
1317 ** and wait reply on next hwinterrupt for next Qbuffer post
1318 */
1319 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
1320 }
1321 break;
1a4f550a
NC		 1322 }
1323}
1324
80da1adb 1325struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
1a4f550a 1326{
0c7eb2eb 1327 struct QBUFFER __iomem *qbuffer = NULL;
1a4f550a
NC		 1328 switch (acb->adapter_type) {
1329
1330 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 1331 struct MessageUnit_A __iomem *reg = acb->pmuA;
1332 qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
1a4f550a
NC		 1333 }
1334 break;
1335
1336 case ACB_ADAPTER_TYPE_B: {
80da1adb 1337 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1338 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1a4f550a
NC		 1339 }
1340 break;
cdd3cb15
NC		 1341 case ACB_ADAPTER_TYPE_C: {
1342 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)acb->pmuC;
1343 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
1344 }
1a4f550a
NC		 1345 }
1346 return qbuffer;
1347}
1348
80da1adb 1349static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
1a4f550a 1350{
0c7eb2eb 1351 struct QBUFFER __iomem *pqbuffer = NULL;
1a4f550a
NC		 1352 switch (acb->adapter_type) {
1353
1354 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 1355 struct MessageUnit_A __iomem *reg = acb->pmuA;
1356 pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
1a4f550a
NC		 1357 }
1358 break;
1359
1360 case ACB_ADAPTER_TYPE_B: {
80da1adb 1361 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1362 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
1a4f550a
NC		 1363 }
1364 break;
cdd3cb15
NC		 1365 case ACB_ADAPTER_TYPE_C: {
1366 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
1367 pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
1368 }
1369
1a4f550a
NC		 1370 }
1371 return pqbuffer;
1372}
1373
1374static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1375{
80da1adb 1376 struct QBUFFER __iomem *prbuffer;
1a4f550a 1377 struct QBUFFER *pQbuffer;
80da1adb 1378 uint8_t __iomem *iop_data;
1a4f550a 1379 int32_t my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex;
1a4f550a
NC		 1380 rqbuf_lastindex = acb->rqbuf_lastindex;
1381 rqbuf_firstindex = acb->rqbuf_firstindex;
1382 prbuffer = arcmsr_get_iop_rqbuffer(acb);
80da1adb 1383 iop_data = (uint8_t __iomem *)prbuffer->data;
1a4f550a 1384 iop_len = prbuffer->data_len;
cdd3cb15 1385 my_empty_len = (rqbuf_firstindex - rqbuf_lastindex - 1) & (ARCMSR_MAX_QBUFFER - 1);
1a4f550a
NC		 1386
1387 if (my_empty_len >= iop_len)
1388 {
1389 while (iop_len > 0) {
1390 pQbuffer = (struct QBUFFER *)&acb->rqbuffer[rqbuf_lastindex];
cdd3cb15 1391 memcpy(pQbuffer, iop_data, 1);
1a4f550a
NC		 1392 rqbuf_lastindex++;
1393 rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1394 iop_data++;
1395 iop_len--;
1396 }
1397 acb->rqbuf_lastindex = rqbuf_lastindex;
1398 arcmsr_iop_message_read(acb);
1399 }
1400
1401 else {
1402 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1403 }
1404}
1405
1406static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1407{
1408 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
1409 if (acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1410 uint8_t *pQbuffer;
80da1adb
AV		 1411 struct QBUFFER __iomem *pwbuffer;
1412 uint8_t __iomem *iop_data;
1a4f550a
NC		 1413 int32_t allxfer_len = 0;
1414
1415 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1416 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1417 iop_data = (uint8_t __iomem *)pwbuffer->data;
1418
1419 while ((acb->wqbuf_firstindex != acb->wqbuf_lastindex) && \
1420 (allxfer_len < 124)) {
1421 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1422 memcpy(iop_data, pQbuffer, 1);
1423 acb->wqbuf_firstindex++;
1424 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1425 iop_data++;
1426 allxfer_len++;
1427 }
1428 pwbuffer->data_len = allxfer_len;
1429
1430 arcmsr_iop_message_wrote(acb);
1431 }
1432
1433 if (acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1434 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1435 }
1436}
1437
1438static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1439{
1440 uint32_t outbound_doorbell;
80da1adb 1441 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1442 outbound_doorbell = readl(&reg->outbound_doorbell);
1443 writel(outbound_doorbell, &reg->outbound_doorbell);
1444 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1445 arcmsr_iop2drv_data_wrote_handle(acb);
1446 }
1447
cdd3cb15 1448 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1a4f550a
NC		 1449 arcmsr_iop2drv_data_read_handle(acb);
1450 }
1451}
cdd3cb15
NC		 1452static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *pACB)
1453{
1454 uint32_t outbound_doorbell;
1455 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
1456 /*
1457 *******************************************************************
1458 ** Maybe here we need to check wrqbuffer_lock is lock or not
1459 ** DOORBELL: din! don!
1460 ** check if there are any mail need to pack from firmware
1461 *******************************************************************
1462 */
1463 outbound_doorbell = readl(&reg->outbound_doorbell);
1464 writel(outbound_doorbell, &reg->outbound_doorbell_clear);/*clear interrupt*/
1465 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1466 arcmsr_iop2drv_data_wrote_handle(pACB);
1467 }
1468 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1469 arcmsr_iop2drv_data_read_handle(pACB);
1470 }
1471 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1472 arcmsr_hbc_message_isr(pACB); /* messenger of "driver to iop commands" */
1473 }
1474 return;
1475}
1a4f550a
NC		 1476static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1477{
1478 uint32_t flag_ccb;
80da1adb 1479 struct MessageUnit_A __iomem *reg = acb->pmuA;
cdd3cb15
NC		 1480 struct ARCMSR_CDB *pARCMSR_CDB;
1481 struct CommandControlBlock *pCCB;
1482 bool error;
1a4f550a 1483 while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
cdd3cb15
NC		 1484 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
1485 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1486 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1487 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 1488 }
1489}
1a4f550a
NC		 1490static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
1491{
1492 uint32_t index;
1493 uint32_t flag_ccb;
80da1adb 1494 struct MessageUnit_B *reg = acb->pmuB;
cdd3cb15
NC		 1495 struct ARCMSR_CDB *pARCMSR_CDB;
1496 struct CommandControlBlock *pCCB;
1497 bool error;
1a4f550a 1498 index = reg->doneq_index;
1a4f550a
NC		 1499 while ((flag_ccb = readl(&reg->done_qbuffer[index])) != 0) {
1500 writel(0, &reg->done_qbuffer[index]);
cdd3cb15
NC		 1501 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
1502 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1503 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1504 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 1505 index++;
1506 index %= ARCMSR_MAX_HBB_POSTQUEUE;
1507 reg->doneq_index = index;
1508 }
1509}
cdd3cb15
NC		 1510
1511static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
1512{
1513 struct MessageUnit_C *phbcmu;
1514 struct ARCMSR_CDB *arcmsr_cdb;
1515 struct CommandControlBlock *ccb;
1516 uint32_t flag_ccb, ccb_cdb_phy, throttling = 0;
1517 int error;
1518
1519 phbcmu = (struct MessageUnit_C *)acb->pmuC;
1520 /* areca cdb command done */
1521 /* Use correct offset and size for syncing */
1522
1523 while (readl(&phbcmu->host_int_status) &
1524 ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR){
1525 /* check if command done with no error*/
1526 flag_ccb = readl(&phbcmu->outbound_queueport_low);
1527 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);/*frame must be 32 bytes aligned*/
1528 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
1529 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
1530 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
1531 /* check if command done with no error */
1532 arcmsr_drain_donequeue(acb, ccb, error);
1533 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1534 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING, &phbcmu->inbound_doorbell);
1535 break;
1536 }
1537 throttling++;
1538 }
1539}
36b83ded
NC		 1540/*
1541**********************************************************************************
1542** Handle a message interrupt
1543**
cdd3cb15 1544** The only message interrupt we expect is in response to a query for the current adapter config.
36b83ded
NC		 1545** We want this in order to compare the drivemap so that we can detect newly-attached drives.
1546**********************************************************************************
1547*/
1548static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb)
1549{
1550 struct MessageUnit_A *reg = acb->pmuA;
36b83ded
NC		 1551 /*clear interrupt and message state*/
1552 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
1553 schedule_work(&acb->arcmsr_do_message_isr_bh);
1554}
1555static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb)
1556{
1557 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1558
36b83ded 1559 /*clear interrupt and message state*/
ae52e7f0 1560 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
36b83ded
NC		 1561 schedule_work(&acb->arcmsr_do_message_isr_bh);
1562}
cdd3cb15
NC		 1563/*
1564**********************************************************************************
1565** Handle a message interrupt
1566**
1567** The only message interrupt we expect is in response to a query for the
1568** current adapter config.
1569** We want this in order to compare the drivemap so that we can detect newly-attached drives.
1570**********************************************************************************
1571*/
1572static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb)
1573{
1574 struct MessageUnit_C *reg = acb->pmuC;
1575 /*clear interrupt and message state*/
1576 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
1577 schedule_work(&acb->arcmsr_do_message_isr_bh);
1578}
1579
1a4f550a
NC		 1580static int arcmsr_handle_hba_isr(struct AdapterControlBlock *acb)
1581{
1582 uint32_t outbound_intstatus;
80da1adb 1583 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 1584 outbound_intstatus = readl(&reg->outbound_intstatus) &
cdd3cb15 1585 acb->outbound_int_enable;
1a4f550a
NC		 1586 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) {
1587 return 1;
1588 }
1589 writel(outbound_intstatus, &reg->outbound_intstatus);
1590 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
1591 arcmsr_hba_doorbell_isr(acb);
1592 }
1593 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
1594 arcmsr_hba_postqueue_isr(acb);
1595 }
cdd3cb15 1596 if(outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
36b83ded
NC		 1597 /* messenger of "driver to iop commands" */
1598 arcmsr_hba_message_isr(acb);
1599 }
1a4f550a
NC		 1600 return 0;
1601}
1602
1603static int arcmsr_handle_hbb_isr(struct AdapterControlBlock *acb)
1604{
1605 uint32_t outbound_doorbell;
80da1adb 1606 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1607 outbound_doorbell = readl(reg->iop2drv_doorbell) &
cdd3cb15 1608 acb->outbound_int_enable;
1a4f550a
NC		 1609 if (!outbound_doorbell)
1610 return 1;
1611
ae52e7f0 1612 writel(~outbound_doorbell, reg->iop2drv_doorbell);
36b83ded
NC		 1613 /*in case the last action of doorbell interrupt clearance is cached,
1614 this action can push HW to write down the clear bit*/
ae52e7f0
NC		 1615 readl(reg->iop2drv_doorbell);
1616 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
cdd3cb15 1617 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
1a4f550a
NC		 1618 arcmsr_iop2drv_data_wrote_handle(acb);
1619 }
1620 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
1621 arcmsr_iop2drv_data_read_handle(acb);
1622 }
1623 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
1624 arcmsr_hbb_postqueue_isr(acb);
1625 }
cdd3cb15 1626 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
36b83ded
NC		 1627 /* messenger of "driver to iop commands" */
1628 arcmsr_hbb_message_isr(acb);
1629 }
1a4f550a
NC		 1630 return 0;
1631}
1632
cdd3cb15
NC		 1633static int arcmsr_handle_hbc_isr(struct AdapterControlBlock *pACB)
1634{
1635 uint32_t host_interrupt_status;
1636 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
1637 /*
1638 *********************************************
1639 ** check outbound intstatus
1640 *********************************************
1641 */
1642 host_interrupt_status = readl(&phbcmu->host_int_status);
1643 if (!host_interrupt_status) {
1644 /*it must be share irq*/
1645 return 1;
1646 }
1647 /* MU ioctl transfer doorbell interrupts*/
1648 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
1649 arcmsr_hbc_doorbell_isr(pACB); /* messenger of "ioctl message read write" */
1650 }
1651 /* MU post queue interrupts*/
1652 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
1653 arcmsr_hbc_postqueue_isr(pACB); /* messenger of "scsi commands" */
1654 }
1655 return 0;
1656}
1a4f550a
NC		 1657static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
1658{
1659 switch (acb->adapter_type) {
1660 case ACB_ADAPTER_TYPE_A: {
1661 if (arcmsr_handle_hba_isr(acb)) {
1662 return IRQ_NONE;
1663 }
1664 }
1665 break;
1666
1667 case ACB_ADAPTER_TYPE_B: {
1668 if (arcmsr_handle_hbb_isr(acb)) {
1669 return IRQ_NONE;
1670 }
1671 }
1672 break;
cdd3cb15
NC		 1673 case ACB_ADAPTER_TYPE_C: {
1674 if (arcmsr_handle_hbc_isr(acb)) {
1675 return IRQ_NONE;
1676 }
1677 }
1c57e86d 1678 }
1c57e86d
EC		 1679 return IRQ_HANDLED;
1680}
1681
1682static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
1683{
1684 if (acb) {
1685 /* stop adapter background rebuild */
1686 if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
1a4f550a 1687 uint32_t intmask_org;
1c57e86d 1688 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1a4f550a 1689 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d
EC		 1690 arcmsr_stop_adapter_bgrb(acb);
1691 arcmsr_flush_adapter_cache(acb);
1a4f550a
NC		 1692 arcmsr_enable_outbound_ints(acb, intmask_org);
1693 }
1694 }
1695}
1696
1697void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb)
1698{
1699 int32_t wqbuf_firstindex, wqbuf_lastindex;
1700 uint8_t *pQbuffer;
80da1adb
AV		 1701 struct QBUFFER __iomem *pwbuffer;
1702 uint8_t __iomem *iop_data;
1a4f550a 1703 int32_t allxfer_len = 0;
1a4f550a
NC		 1704 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1705 iop_data = (uint8_t __iomem *)pwbuffer->data;
1706 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
1707 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1708 wqbuf_firstindex = acb->wqbuf_firstindex;
1709 wqbuf_lastindex = acb->wqbuf_lastindex;
1710 while ((wqbuf_firstindex != wqbuf_lastindex) && (allxfer_len < 124)) {
1711 pQbuffer = &acb->wqbuffer[wqbuf_firstindex];
1712 memcpy(iop_data, pQbuffer, 1);
1713 wqbuf_firstindex++;
1714 wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1715 iop_data++;
1716 allxfer_len++;
1c57e86d 1717 }
1a4f550a
NC		 1718 acb->wqbuf_firstindex = wqbuf_firstindex;
1719 pwbuffer->data_len = allxfer_len;
1720 arcmsr_iop_message_wrote(acb);
1c57e86d
EC		 1721 }
1722}
1723
36b83ded 1724static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
1a4f550a 1725 struct scsi_cmnd *cmd)
1c57e86d 1726{
1c57e86d
EC		 1727 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
1728 int retvalue = 0, transfer_len = 0;
1729 char *buffer;
deff2627 1730 struct scatterlist *sg;
1c57e86d
EC		 1731 uint32_t controlcode = (uint32_t ) cmd->cmnd[5] << 24 |
1732 (uint32_t ) cmd->cmnd[6] << 16 |
1733 (uint32_t ) cmd->cmnd[7] << 8 |
1734 (uint32_t ) cmd->cmnd[8];
1a4f550a 1735 /* 4 bytes: Areca io control code */
deff2627 1736 sg = scsi_sglist(cmd);
77dfce07 1737 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
deff2627
FT		 1738 if (scsi_sg_count(cmd) > 1) {
1739 retvalue = ARCMSR_MESSAGE_FAIL;
1740 goto message_out;
1c57e86d 1741 }
deff2627
FT		 1742 transfer_len += sg->length;
1743
1c57e86d
EC		 1744 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
1745 retvalue = ARCMSR_MESSAGE_FAIL;
1746 goto message_out;
1747 }
1748 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
1749 switch(controlcode) {
1a4f550a 1750
1c57e86d 1751 case ARCMSR_MESSAGE_READ_RQBUFFER: {
69e562c2 1752 unsigned char *ver_addr;
1a4f550a
NC		 1753 uint8_t *pQbuffer, *ptmpQbuffer;
1754 int32_t allxfer_len = 0;
1755
69e562c2
DD		 1756 ver_addr = kmalloc(1032, GFP_ATOMIC);
1757 if (!ver_addr) {
1a4f550a
NC		 1758 retvalue = ARCMSR_MESSAGE_FAIL;
1759 goto message_out;
1760 }
cdd3cb15 1761
69e562c2 1762 ptmpQbuffer = ver_addr;
1a4f550a
NC		 1763 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
1764 && (allxfer_len < 1031)) {
1765 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
1766 memcpy(ptmpQbuffer, pQbuffer, 1);
1767 acb->rqbuf_firstindex++;
1768 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1769 ptmpQbuffer++;
1770 allxfer_len++;
1771 }
1772 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1c57e86d 1773
80da1adb
AV		 1774 struct QBUFFER __iomem *prbuffer;
1775 uint8_t __iomem *iop_data;
1a4f550a
NC		 1776 int32_t iop_len;
1777
1778 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1779 prbuffer = arcmsr_get_iop_rqbuffer(acb);
80da1adb 1780 iop_data = prbuffer->data;
1a4f550a
NC		 1781 iop_len = readl(&prbuffer->data_len);
1782 while (iop_len > 0) {
1783 acb->rqbuffer[acb->rqbuf_lastindex] = readb(iop_data);
1784 acb->rqbuf_lastindex++;
1785 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1786 iop_data++;
1787 iop_len--;
1c57e86d 1788 }
1a4f550a
NC		 1789 arcmsr_iop_message_read(acb);
1790 }
69e562c2 1791 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr, allxfer_len);
1a4f550a 1792 pcmdmessagefld->cmdmessage.Length = allxfer_len;
cdd3cb15 1793 if(acb->fw_flag == FW_DEADLOCK) {
ae52e7f0 1794 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15
NC		 1795 }else{
1796 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
ae52e7f0 1797 }
69e562c2 1798 kfree(ver_addr);
1c57e86d
EC		 1799 }
1800 break;
1c57e86d 1801
1a4f550a 1802 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
69e562c2 1803 unsigned char *ver_addr;
1a4f550a
NC		 1804 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
1805 uint8_t *pQbuffer, *ptmpuserbuffer;
1806
69e562c2
DD		 1807 ver_addr = kmalloc(1032, GFP_ATOMIC);
1808 if (!ver_addr) {
1a4f550a
NC		 1809 retvalue = ARCMSR_MESSAGE_FAIL;
1810 goto message_out;
1811 }
cdd3cb15
NC		 1812 if(acb->fw_flag == FW_DEADLOCK) {
1813 pcmdmessagefld->cmdmessage.ReturnCode =
36b83ded 1814 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15
NC		 1815 }else{
1816 pcmdmessagefld->cmdmessage.ReturnCode =
ae52e7f0 1817 ARCMSR_MESSAGE_RETURNCODE_OK;
36b83ded 1818 }
69e562c2 1819 ptmpuserbuffer = ver_addr;
1a4f550a
NC		 1820 user_len = pcmdmessagefld->cmdmessage.Length;
1821 memcpy(ptmpuserbuffer, pcmdmessagefld->messagedatabuffer, user_len);
1822 wqbuf_lastindex = acb->wqbuf_lastindex;
1823 wqbuf_firstindex = acb->wqbuf_firstindex;
1824 if (wqbuf_lastindex != wqbuf_firstindex) {
1825 struct SENSE_DATA *sensebuffer =
1826 (struct SENSE_DATA *)cmd->sense_buffer;
1827 arcmsr_post_ioctldata2iop(acb);
1828 /* has error report sensedata */
1829 sensebuffer->ErrorCode = 0x70;
1830 sensebuffer->SenseKey = ILLEGAL_REQUEST;
1831 sensebuffer->AdditionalSenseLength = 0x0A;
1832 sensebuffer->AdditionalSenseCode = 0x20;
1833 sensebuffer->Valid = 1;
1834 retvalue = ARCMSR_MESSAGE_FAIL;
1835 } else {
1836 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
1837 &(ARCMSR_MAX_QBUFFER - 1);
1838 if (my_empty_len >= user_len) {
1839 while (user_len > 0) {
1840 pQbuffer =
1841 &acb->wqbuffer[acb->wqbuf_lastindex];
1842 memcpy(pQbuffer, ptmpuserbuffer, 1);
1843 acb->wqbuf_lastindex++;
1844 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1845 ptmpuserbuffer++;
1846 user_len--;
1847 }
1848 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
1849 acb->acb_flags &=
1850 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
1851 arcmsr_post_ioctldata2iop(acb);
1852 }
1853 } else {
1854 /* has error report sensedata */
1c57e86d
EC		 1855 struct SENSE_DATA *sensebuffer =
1856 (struct SENSE_DATA *)cmd->sense_buffer;
1c57e86d
EC		 1857 sensebuffer->ErrorCode = 0x70;
1858 sensebuffer->SenseKey = ILLEGAL_REQUEST;
1859 sensebuffer->AdditionalSenseLength = 0x0A;
1860 sensebuffer->AdditionalSenseCode = 0x20;
1861 sensebuffer->Valid = 1;
1862 retvalue = ARCMSR_MESSAGE_FAIL;
1a4f550a 1863 }
1c57e86d 1864 }
69e562c2 1865 kfree(ver_addr);
1c57e86d
EC		 1866 }
1867 break;
1a4f550a 1868
1c57e86d 1869 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
1a4f550a 1870 uint8_t *pQbuffer = acb->rqbuffer;
1a4f550a
NC		 1871 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1872 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1873 arcmsr_iop_message_read(acb);
1874 }
1875 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
1876 acb->rqbuf_firstindex = 0;
1877 acb->rqbuf_lastindex = 0;
1878 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
cdd3cb15 1879 if(acb->fw_flag == FW_DEADLOCK) {
ae52e7f0
NC		 1880 pcmdmessagefld->cmdmessage.ReturnCode =
1881 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1882 }else{
ae52e7f0
NC		 1883 pcmdmessagefld->cmdmessage.ReturnCode =
1884 ARCMSR_MESSAGE_RETURNCODE_OK;
1885 }
1c57e86d
EC		 1886 }
1887 break;
1a4f550a 1888
1c57e86d 1889 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
1a4f550a 1890 uint8_t *pQbuffer = acb->wqbuffer;
cdd3cb15 1891 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1892 pcmdmessagefld->cmdmessage.ReturnCode =
1893 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1894 }else{
ae52e7f0
NC		 1895 pcmdmessagefld->cmdmessage.ReturnCode =
1896 ARCMSR_MESSAGE_RETURNCODE_OK;
36b83ded 1897 }
1c57e86d 1898
1a4f550a
NC		 1899 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1900 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1901 arcmsr_iop_message_read(acb);
1902 }
1903 acb->acb_flags |=
1904 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
1905 ACB_F_MESSAGE_WQBUFFER_READED);
1906 acb->wqbuf_firstindex = 0;
1907 acb->wqbuf_lastindex = 0;
1908 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
1c57e86d
EC		 1909 }
1910 break;
1a4f550a 1911
1c57e86d 1912 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
1a4f550a 1913 uint8_t *pQbuffer;
1c57e86d 1914
1a4f550a
NC		 1915 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1916 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1917 arcmsr_iop_message_read(acb);
1918 }
1919 acb->acb_flags |=
1920 (ACB_F_MESSAGE_WQBUFFER_CLEARED
1921 | ACB_F_MESSAGE_RQBUFFER_CLEARED
1922 | ACB_F_MESSAGE_WQBUFFER_READED);
1923 acb->rqbuf_firstindex = 0;
1924 acb->rqbuf_lastindex = 0;
1925 acb->wqbuf_firstindex = 0;
1926 acb->wqbuf_lastindex = 0;
1927 pQbuffer = acb->rqbuffer;
1928 memset(pQbuffer, 0, sizeof(struct QBUFFER));
1929 pQbuffer = acb->wqbuffer;
1930 memset(pQbuffer, 0, sizeof(struct QBUFFER));
cdd3cb15 1931 if(acb->fw_flag == FW_DEADLOCK) {
ae52e7f0
NC		 1932 pcmdmessagefld->cmdmessage.ReturnCode =
1933 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1934 }else{
ae52e7f0
NC		 1935 pcmdmessagefld->cmdmessage.ReturnCode =
1936 ARCMSR_MESSAGE_RETURNCODE_OK;
1937 }
1c57e86d
EC		 1938 }
1939 break;
1a4f550a 1940
1c57e86d 1941 case ARCMSR_MESSAGE_RETURN_CODE_3F: {
cdd3cb15 1942 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1943 pcmdmessagefld->cmdmessage.ReturnCode =
1944 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1945 }else{
ae52e7f0
NC		 1946 pcmdmessagefld->cmdmessage.ReturnCode =
1947 ARCMSR_MESSAGE_RETURNCODE_3F;
1c57e86d
EC		 1948 }
1949 break;
ae52e7f0 1950 }
1c57e86d 1951 case ARCMSR_MESSAGE_SAY_HELLO: {
1a4f550a 1952 int8_t *hello_string = "Hello! I am ARCMSR";
cdd3cb15 1953 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1954 pcmdmessagefld->cmdmessage.ReturnCode =
1955 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1956 }else{
ae52e7f0
NC		 1957 pcmdmessagefld->cmdmessage.ReturnCode =
1958 ARCMSR_MESSAGE_RETURNCODE_OK;
36b83ded 1959 }
1a4f550a
NC		 1960 memcpy(pcmdmessagefld->messagedatabuffer, hello_string
1961 , (int16_t)strlen(hello_string));
1c57e86d
EC		 1962 }
1963 break;
1a4f550a 1964
1c57e86d 1965 case ARCMSR_MESSAGE_SAY_GOODBYE:
cdd3cb15 1966 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1967 pcmdmessagefld->cmdmessage.ReturnCode =
1968 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
36b83ded 1969 }
1c57e86d
EC		 1970 arcmsr_iop_parking(acb);
1971 break;
1a4f550a 1972
1c57e86d 1973 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
cdd3cb15 1974 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1975 pcmdmessagefld->cmdmessage.ReturnCode =
1976 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
36b83ded 1977 }
1c57e86d
EC		 1978 arcmsr_flush_adapter_cache(acb);
1979 break;
1a4f550a 1980
1c57e86d
EC		 1981 default:
1982 retvalue = ARCMSR_MESSAGE_FAIL;
1983 }
1a4f550a 1984 message_out:
deff2627 1985 sg = scsi_sglist(cmd);
77dfce07 1986 kunmap_atomic(buffer - sg->offset);
1c57e86d
EC		 1987 return retvalue;
1988}
1989
1990static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
1991{
1992 struct list_head *head = &acb->ccb_free_list;
1993 struct CommandControlBlock *ccb = NULL;
ae52e7f0
NC		 1994 unsigned long flags;
1995 spin_lock_irqsave(&acb->ccblist_lock, flags);
1c57e86d
EC		 1996 if (!list_empty(head)) {
1997 ccb = list_entry(head->next, struct CommandControlBlock, list);
ae52e7f0 1998 list_del_init(&ccb->list);
cdd3cb15 1999 }else{
ae52e7f0
NC		 2000 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
2001 return 0;
1c57e86d 2002 }
ae52e7f0 2003 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 2004 return ccb;
2005}
2006
2007static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2008 struct scsi_cmnd *cmd)
2009{
2010 switch (cmd->cmnd[0]) {
2011 case INQUIRY: {
2012 unsigned char inqdata[36];
2013 char *buffer;
deff2627 2014 struct scatterlist *sg;
1c57e86d
EC		 2015
2016 if (cmd->device->lun) {
2017 cmd->result = (DID_TIME_OUT << 16);
2018 cmd->scsi_done(cmd);
2019 return;
2020 }
2021 inqdata[0] = TYPE_PROCESSOR;
2022 /* Periph Qualifier & Periph Dev Type */
2023 inqdata[1] = 0;
2024 /* rem media bit & Dev Type Modifier */
2025 inqdata[2] = 0;
a1f6e021 2026 /* ISO, ECMA, & ANSI versions */
1c57e86d
EC		 2027 inqdata[4] = 31;
2028 /* length of additional data */
2029 strncpy(&inqdata[8], "Areca ", 8);
2030 /* Vendor Identification */
2031 strncpy(&inqdata[16], "RAID controller ", 16);
2032 /* Product Identification */
2033 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
1c57e86d 2034
deff2627 2035 sg = scsi_sglist(cmd);
77dfce07 2036 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
deff2627 2037
1c57e86d 2038 memcpy(buffer, inqdata, sizeof(inqdata));
deff2627 2039 sg = scsi_sglist(cmd);
77dfce07 2040 kunmap_atomic(buffer - sg->offset);
1c57e86d 2041
1c57e86d
EC		 2042 cmd->scsi_done(cmd);
2043 }
2044 break;
2045 case WRITE_BUFFER:
2046 case READ_BUFFER: {
2047 if (arcmsr_iop_message_xfer(acb, cmd))
2048 cmd->result = (DID_ERROR << 16);
2049 cmd->scsi_done(cmd);
2050 }
2051 break;
2052 default:
2053 cmd->scsi_done(cmd);
2054 }
2055}
2056
f281233d 2057static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
1c57e86d
EC		 2058 void (* done)(struct scsi_cmnd *))
2059{
2060 struct Scsi_Host *host = cmd->device->host;
1a4f550a 2061 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
1c57e86d
EC		 2062 struct CommandControlBlock *ccb;
2063 int target = cmd->device->id;
2064 int lun = cmd->device->lun;
36b83ded 2065 uint8_t scsicmd = cmd->cmnd[0];
1c57e86d
EC		 2066 cmd->scsi_done = done;
2067 cmd->host_scribble = NULL;
2068 cmd->result = 0;
cdd3cb15
NC		 2069 if ((scsicmd == SYNCHRONIZE_CACHE) ||(scsicmd == SEND_DIAGNOSTIC)){
2070 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2071 cmd->result = (DID_NO_CONNECT << 16);
36b83ded
NC		 2072 }
2073 cmd->scsi_done(cmd);
2074 return 0;
2075 }
a1f6e021 2076 if (target == 16) {
1c57e86d
EC		 2077 /* virtual device for iop message transfer */
2078 arcmsr_handle_virtual_command(acb, cmd);
2079 return 0;
2080 }
1c57e86d
EC		 2081 if (atomic_read(&acb->ccboutstandingcount) >=
2082 ARCMSR_MAX_OUTSTANDING_CMD)
2083 return SCSI_MLQUEUE_HOST_BUSY;
1c57e86d
EC		 2084 ccb = arcmsr_get_freeccb(acb);
2085 if (!ccb)
2086 return SCSI_MLQUEUE_HOST_BUSY;
cdd3cb15 2087 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
76d78300
NC		 2088 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
2089 cmd->scsi_done(cmd);
2090 return 0;
2091 }
1c57e86d
EC		 2092 arcmsr_post_ccb(acb, ccb);
2093 return 0;
2094}
2095
f281233d
JG		 2096static DEF_SCSI_QCMD(arcmsr_queue_command)
2097
ae52e7f0 2098static bool arcmsr_get_hba_config(struct AdapterControlBlock *acb)
1c57e86d 2099{
80da1adb 2100 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d
EC		 2101 char *acb_firm_model = acb->firm_model;
2102 char *acb_firm_version = acb->firm_version;
36b83ded 2103 char *acb_device_map = acb->device_map;
80da1adb
AV		 2104 char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
2105 char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
cdd3cb15 2106 char __iomem *iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]);
1c57e86d 2107 int count;
1c57e86d 2108 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
cdd3cb15 2109 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 2110 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2111 miscellaneous data' timeout \n", acb->host->host_no);
ae52e7f0 2112 return false;
1a4f550a 2113 }
1c57e86d 2114 count = 8;
cdd3cb15 2115 while (count){
1c57e86d
EC		 2116 *acb_firm_model = readb(iop_firm_model);
2117 acb_firm_model++;
2118 iop_firm_model++;
2119 count--;
2120 }
1a4f550a 2121
1c57e86d 2122 count = 16;
cdd3cb15 2123 while (count){
1c57e86d
EC		 2124 *acb_firm_version = readb(iop_firm_version);
2125 acb_firm_version++;
2126 iop_firm_version++;
2127 count--;
2128 }
1a4f550a 2129
cdd3cb15
NC		 2130 count=16;
2131 while(count){
2132 *acb_device_map = readb(iop_device_map);
2133 acb_device_map++;
2134 iop_device_map++;
2135 count--;
2136 }
2137 printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
ae52e7f0
NC		 2138 acb->host->host_no,
2139 acb->firm_version,
2140 acb->firm_model);
cdd3cb15 2141 acb->signature = readl(&reg->message_rwbuffer[0]);
1c57e86d
EC		 2142 acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
2143 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
2144 acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
2145 acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
ae52e7f0
NC		 2146 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2147 return true;
1c57e86d 2148}
ae52e7f0 2149static bool arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
1a4f550a 2150{
80da1adb 2151 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0
NC		 2152 struct pci_dev *pdev = acb->pdev;
2153 void *dma_coherent;
2154 dma_addr_t dma_coherent_handle;
1a4f550a
NC		 2155 char *acb_firm_model = acb->firm_model;
2156 char *acb_firm_version = acb->firm_version;
36b83ded 2157 char *acb_device_map = acb->device_map;
ae52e7f0 2158 char __iomem *iop_firm_model;
1a4f550a 2159 /*firm_model,15,60-67*/
ae52e7f0 2160 char __iomem *iop_firm_version;
1a4f550a 2161 /*firm_version,17,68-83*/
ae52e7f0 2162 char __iomem *iop_device_map;
36b83ded 2163 /*firm_version,21,84-99*/
1a4f550a 2164 int count;
ae52e7f0 2165 dma_coherent = dma_alloc_coherent(&pdev->dev, sizeof(struct MessageUnit_B), &dma_coherent_handle, GFP_KERNEL);
cdd3cb15 2166 if (!dma_coherent){
ae52e7f0
NC		 2167 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error for hbb mu\n", acb->host->host_no);
2168 return false;
2169 }
2170 acb->dma_coherent_handle_hbb_mu = dma_coherent_handle;
2171 reg = (struct MessageUnit_B *)dma_coherent;
2172 acb->pmuB = reg;
cdd3cb15 2173 reg->drv2iop_doorbell= (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL);
ae52e7f0
NC		 2174 reg->drv2iop_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL_MASK);
2175 reg->iop2drv_doorbell = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL);
2176 reg->iop2drv_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL_MASK);
2177 reg->message_wbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_WBUFFER);
2178 reg->message_rbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RBUFFER);
2179 reg->message_rwbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RWBUFFER);
2180 iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]); /*firm_model,15,60-67*/
2181 iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]); /*firm_version,17,68-83*/
2182 iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]); /*firm_version,21,84-99*/
2183
2184 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
cdd3cb15 2185 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2186 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2187 miscellaneous data' timeout \n", acb->host->host_no);
ae52e7f0 2188 return false;
1a4f550a 2189 }
1a4f550a 2190 count = 8;
cdd3cb15 2191 while (count){
1a4f550a
NC		 2192 *acb_firm_model = readb(iop_firm_model);
2193 acb_firm_model++;
2194 iop_firm_model++;
2195 count--;
2196 }
1a4f550a 2197 count = 16;
cdd3cb15 2198 while (count){
1a4f550a
NC		 2199 *acb_firm_version = readb(iop_firm_version);
2200 acb_firm_version++;
2201 iop_firm_version++;
2202 count--;
2203 }
2204
cdd3cb15
NC		 2205 count = 16;
2206 while(count){
2207 *acb_device_map = readb(iop_device_map);
2208 acb_device_map++;
2209 iop_device_map++;
2210 count--;
2211 }
2212
ae52e7f0 2213 printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
cdd3cb15 2214 acb->host->host_no,
ae52e7f0
NC		 2215 acb->firm_version,
2216 acb->firm_model);
1a4f550a 2217
ae52e7f0 2218 acb->signature = readl(&reg->message_rwbuffer[1]);
cdd3cb15 2219 /*firm_signature,1,00-03*/
ae52e7f0 2220 acb->firm_request_len = readl(&reg->message_rwbuffer[2]);
1a4f550a 2221 /*firm_request_len,1,04-07*/
ae52e7f0 2222 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[3]);
1a4f550a 2223 /*firm_numbers_queue,2,08-11*/
ae52e7f0 2224 acb->firm_sdram_size = readl(&reg->message_rwbuffer[4]);
1a4f550a 2225 /*firm_sdram_size,3,12-15*/
ae52e7f0 2226 acb->firm_hd_channels = readl(&reg->message_rwbuffer[5]);
1a4f550a 2227 /*firm_ide_channels,4,16-19*/
ae52e7f0
NC		 2228 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2229 /*firm_ide_channels,4,16-19*/
2230 return true;
1a4f550a 2231}
cdd3cb15
NC		 2232
2233static bool arcmsr_get_hbc_config(struct AdapterControlBlock *pACB)
2234{
2235 uint32_t intmask_org, Index, firmware_state = 0;
2236 struct MessageUnit_C *reg = pACB->pmuC;
2237 char *acb_firm_model = pACB->firm_model;
2238 char *acb_firm_version = pACB->firm_version;
2239 char *iop_firm_model = (char *)(&reg->msgcode_rwbuffer[15]); /*firm_model,15,60-67*/
2240 char *iop_firm_version = (char *)(&reg->msgcode_rwbuffer[17]); /*firm_version,17,68-83*/
2241 int count;
2242 /* disable all outbound interrupt */
2243 intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
2244 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
2245 /* wait firmware ready */
2246 do {
2247 firmware_state = readl(&reg->outbound_msgaddr1);
2248 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
2249 /* post "get config" instruction */
2250 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
2251 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2252 /* wait message ready */
2253 for (Index = 0; Index < 2000; Index++) {
2254 if (readl(&reg->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
2255 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);/*clear interrupt*/
2256 break;
2257 }
2258 udelay(10);
2259 } /*max 1 seconds*/
2260 if (Index >= 2000) {
2261 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2262 miscellaneous data' timeout \n", pACB->host->host_no);
2263 return false;
2264 }
2265 count = 8;
2266 while (count) {
2267 *acb_firm_model = readb(iop_firm_model);
2268 acb_firm_model++;
2269 iop_firm_model++;
2270 count--;
2271 }
2272 count = 16;
2273 while (count) {
2274 *acb_firm_version = readb(iop_firm_version);
2275 acb_firm_version++;
2276 iop_firm_version++;
2277 count--;
2278 }
2279 printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
2280 pACB->host->host_no,
2281 pACB->firm_version,
2282 pACB->firm_model);
2283 pACB->firm_request_len = readl(&reg->msgcode_rwbuffer[1]); /*firm_request_len,1,04-07*/
2284 pACB->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[2]); /*firm_numbers_queue,2,08-11*/
2285 pACB->firm_sdram_size = readl(&reg->msgcode_rwbuffer[3]); /*firm_sdram_size,3,12-15*/
2286 pACB->firm_hd_channels = readl(&reg->msgcode_rwbuffer[4]); /*firm_ide_channels,4,16-19*/
2287 pACB->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2288 /*all interrupt service will be enable at arcmsr_iop_init*/
2289 return true;
2290}
ae52e7f0 2291static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
1a4f550a 2292{
ae52e7f0
NC		 2293 if (acb->adapter_type == ACB_ADAPTER_TYPE_A)
2294 return arcmsr_get_hba_config(acb);
cdd3cb15 2295 else if (acb->adapter_type == ACB_ADAPTER_TYPE_B)
ae52e7f0 2296 return arcmsr_get_hbb_config(acb);
cdd3cb15
NC		 2297 else
2298 return arcmsr_get_hbc_config(acb);
1a4f550a
NC		 2299}
2300
ae52e7f0 2301static int arcmsr_polling_hba_ccbdone(struct AdapterControlBlock *acb,
1c57e86d
EC		 2302 struct CommandControlBlock *poll_ccb)
2303{
80da1adb 2304 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 2305 struct CommandControlBlock *ccb;
ae52e7f0 2306 struct ARCMSR_CDB *arcmsr_cdb;
1c57e86d 2307 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 2308 int rtn;
cdd3cb15 2309 bool error;
1a4f550a 2310 polling_hba_ccb_retry:
1c57e86d 2311 poll_count++;
1a4f550a 2312 outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
1c57e86d
EC		 2313 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
2314 while (1) {
2315 if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
cdd3cb15 2316 if (poll_ccb_done){
ae52e7f0 2317 rtn = SUCCESS;
1c57e86d 2318 break;
cdd3cb15
NC		 2319 }else {
2320 msleep(25);
2321 if (poll_count > 100){
ae52e7f0 2322 rtn = FAILED;
1c57e86d 2323 break;
ae52e7f0 2324 }
1a4f550a 2325 goto polling_hba_ccb_retry;
1c57e86d
EC		 2326 }
2327 }
ae52e7f0
NC		 2328 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
2329 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
1a4f550a
NC		 2330 poll_ccb_done = (ccb == poll_ccb) ? 1:0;
2331 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
2332 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
2333 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
1c57e86d
EC		 2334 " poll command abort successfully \n"
2335 , acb->host->host_no
2336 , ccb->pcmd->device->id
2337 , ccb->pcmd->device->lun
2338 , ccb);
2339 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 2340 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 2341 continue;
2342 }
1a4f550a
NC		 2343 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2344 " command done ccb = '0x%p'"
a1f6e021 2345 "ccboutstandingcount = %d \n"
1c57e86d
EC		 2346 , acb->host->host_no
2347 , ccb
2348 , atomic_read(&acb->ccboutstandingcount));
2349 continue;
cdd3cb15
NC		 2350 }
2351 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2352 arcmsr_report_ccb_state(acb, ccb, error);
1a4f550a 2353 }
ae52e7f0
NC		 2354 return rtn;
2355}
1a4f550a 2356
ae52e7f0 2357static int arcmsr_polling_hbb_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 2358 struct CommandControlBlock *poll_ccb)
2359{
cdd3cb15 2360 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2361 struct ARCMSR_CDB *arcmsr_cdb;
cdd3cb15
NC		 2362 struct CommandControlBlock *ccb;
2363 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 2364 int index, rtn;
cdd3cb15 2365 bool error;
1a4f550a 2366 polling_hbb_ccb_retry:
97b99127 2367
cdd3cb15
NC		 2368 poll_count++;
2369 /* clear doorbell interrupt */
ae52e7f0 2370 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
cdd3cb15
NC		 2371 while(1){
2372 index = reg->doneq_index;
2373 if ((flag_ccb = readl(&reg->done_qbuffer[index])) == 0) {
2374 if (poll_ccb_done){
ae52e7f0 2375 rtn = SUCCESS;
cdd3cb15
NC		 2376 break;
2377 }else {
2378 msleep(25);
2379 if (poll_count > 100){
ae52e7f0 2380 rtn = FAILED;
cdd3cb15 2381 break;
1c57e86d 2382 }
cdd3cb15 2383 goto polling_hbb_ccb_retry;
1a4f550a 2384 }
cdd3cb15
NC		 2385 }
2386 writel(0, &reg->done_qbuffer[index]);
2387 index++;
2388 /*if last index number set it to 0 */
2389 index %= ARCMSR_MAX_HBB_POSTQUEUE;
2390 reg->doneq_index = index;
2391 /* check if command done with no error*/
ae52e7f0
NC		 2392 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
2393 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
cdd3cb15
NC		 2394 poll_ccb_done = (ccb == poll_ccb) ? 1:0;
2395 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
2396 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
ae52e7f0
NC		 2397 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
2398 " poll command abort successfully \n"
cdd3cb15
NC		 2399 ,acb->host->host_no
2400 ,ccb->pcmd->device->id
2401 ,ccb->pcmd->device->lun
2402 ,ccb);
2403 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 2404 arcmsr_ccb_complete(ccb);
cdd3cb15
NC		 2405 continue;
2406 }
2407 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2408 " command done ccb = '0x%p'"
2409 "ccboutstandingcount = %d \n"
2410 , acb->host->host_no
2411 , ccb
2412 , atomic_read(&acb->ccboutstandingcount));
2413 continue;
2414 }
2415 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2416 arcmsr_report_ccb_state(acb, ccb, error);
2417 }
2418 return rtn;
2419}
2420
2421static int arcmsr_polling_hbc_ccbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_ccb)
2422{
2423 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2424 uint32_t flag_ccb, ccb_cdb_phy;
2425 struct ARCMSR_CDB *arcmsr_cdb;
2426 bool error;
2427 struct CommandControlBlock *pCCB;
2428 uint32_t poll_ccb_done = 0, poll_count = 0;
2429 int rtn;
2430polling_hbc_ccb_retry:
2431 poll_count++;
2432 while (1) {
2433 if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
2434 if (poll_ccb_done) {
2435 rtn = SUCCESS;
2436 break;
2437 } else {
2438 msleep(25);
2439 if (poll_count > 100) {
2440 rtn = FAILED;
2441 break;
1c57e86d 2442 }
cdd3cb15
NC		 2443 goto polling_hbc_ccb_retry;
2444 }
2445 }
2446 flag_ccb = readl(&reg->outbound_queueport_low);
2447 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
2448 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/
2449 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
2450 poll_ccb_done = (pCCB == poll_ccb) ? 1 : 0;
2451 /* check ifcommand done with no error*/
2452 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
2453 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
2454 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
2455 " poll command abort successfully \n"
1c57e86d 2456 , acb->host->host_no
cdd3cb15
NC		 2457 , pCCB->pcmd->device->id
2458 , pCCB->pcmd->device->lun
2459 , pCCB);
2460 pCCB->pcmd->result = DID_ABORT << 16;
2461 arcmsr_ccb_complete(pCCB);
1a4f550a 2462 continue;
cdd3cb15
NC		 2463 }
2464 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2465 " command done ccb = '0x%p'"
2466 "ccboutstandingcount = %d \n"
2467 , acb->host->host_no
2468 , pCCB
2469 , atomic_read(&acb->ccboutstandingcount));
2470 continue;
ae52e7f0 2471 }
cdd3cb15
NC		 2472 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
2473 arcmsr_report_ccb_state(acb, pCCB, error);
2474 }
ae52e7f0 2475 return rtn;
1a4f550a 2476}
ae52e7f0 2477static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 2478 struct CommandControlBlock *poll_ccb)
2479{
ae52e7f0 2480 int rtn = 0;
1a4f550a
NC		 2481 switch (acb->adapter_type) {
2482
2483 case ACB_ADAPTER_TYPE_A: {
ae52e7f0 2484 rtn = arcmsr_polling_hba_ccbdone(acb, poll_ccb);
1a4f550a
NC		 2485 }
2486 break;
2487
2488 case ACB_ADAPTER_TYPE_B: {
ae52e7f0 2489 rtn = arcmsr_polling_hbb_ccbdone(acb, poll_ccb);
1c57e86d 2490 }
cdd3cb15
NC		 2491 break;
2492 case ACB_ADAPTER_TYPE_C: {
2493 rtn = arcmsr_polling_hbc_ccbdone(acb, poll_ccb);
2494 }
1c57e86d 2495 }
ae52e7f0 2496 return rtn;
1c57e86d 2497}
1a4f550a
NC		 2498
2499static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
a1f6e021 2500{
ae52e7f0 2501 uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
1a4f550a
NC		 2502 dma_addr_t dma_coherent_handle;
2503 /*
2504 ********************************************************************
2505 ** here we need to tell iop 331 our freeccb.HighPart
2506 ** if freeccb.HighPart is not zero
2507 ********************************************************************
2508 */
2509 dma_coherent_handle = acb->dma_coherent_handle;
2510 cdb_phyaddr = (uint32_t)(dma_coherent_handle);
ae52e7f0 2511 cdb_phyaddr_hi32 = (uint32_t)((cdb_phyaddr >> 16) >> 16);
cdd3cb15 2512 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
1a4f550a
NC		 2513 /*
2514 ***********************************************************************
2515 ** if adapter type B, set window of "post command Q"
2516 ***********************************************************************
2517 */
2518 switch (acb->adapter_type) {
2519
2520 case ACB_ADAPTER_TYPE_A: {
ae52e7f0 2521 if (cdb_phyaddr_hi32 != 0) {
80da1adb 2522 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2523 uint32_t intmask_org;
2524 intmask_org = arcmsr_disable_outbound_ints(acb);
2525 writel(ARCMSR_SIGNATURE_SET_CONFIG, \
2526 &reg->message_rwbuffer[0]);
ae52e7f0 2527 writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
1a4f550a
NC		 2528 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
2529 &reg->inbound_msgaddr0);
cdd3cb15 2530 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 2531 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
2532 part physical address timeout\n",
2533 acb->host->host_no);
2534 return 1;
a1f6e021 2535 }
1a4f550a
NC		 2536 arcmsr_enable_outbound_ints(acb, intmask_org);
2537 }
2538 }
2539 break;
a1f6e021 2540
1a4f550a
NC		 2541 case ACB_ADAPTER_TYPE_B: {
2542 unsigned long post_queue_phyaddr;
80da1adb 2543 uint32_t __iomem *rwbuffer;
a1f6e021 2544
80da1adb 2545 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 2546 uint32_t intmask_org;
2547 intmask_org = arcmsr_disable_outbound_ints(acb);
2548 reg->postq_index = 0;
2549 reg->doneq_index = 0;
ae52e7f0 2550 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
cdd3cb15 2551 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2552 printk(KERN_NOTICE "arcmsr%d:can not set diver mode\n", \
2553 acb->host->host_no);
2554 return 1;
2555 }
ae52e7f0
NC		 2556 post_queue_phyaddr = acb->dma_coherent_handle_hbb_mu;
2557 rwbuffer = reg->message_rwbuffer;
1a4f550a
NC		 2558 /* driver "set config" signature */
2559 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
2560 /* normal should be zero */
ae52e7f0 2561 writel(cdb_phyaddr_hi32, rwbuffer++);
1a4f550a
NC		 2562 /* postQ size (256 + 8)*4 */
2563 writel(post_queue_phyaddr, rwbuffer++);
2564 /* doneQ size (256 + 8)*4 */
2565 writel(post_queue_phyaddr + 1056, rwbuffer++);
2566 /* ccb maxQ size must be --> [(256 + 8)*4]*/
2567 writel(1056, rwbuffer);
2568
ae52e7f0 2569 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
cdd3cb15 2570 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2571 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
2572 timeout \n",acb->host->host_no);
2573 return 1;
2574 }
ae52e7f0 2575 arcmsr_hbb_enable_driver_mode(acb);
1a4f550a
NC		 2576 arcmsr_enable_outbound_ints(acb, intmask_org);
2577 }
2578 break;
cdd3cb15
NC		 2579 case ACB_ADAPTER_TYPE_C: {
2580 if (cdb_phyaddr_hi32 != 0) {
2581 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2582
8b7eb86f
TH		 2583 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
2584 acb->adapter_index, cdb_phyaddr_hi32);
cdd3cb15
NC		 2585 writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
2586 writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
2587 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
2588 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2589 if (!arcmsr_hbc_wait_msgint_ready(acb)) {
2590 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
2591 timeout \n", acb->host->host_no);
2592 return 1;
2593 }
2594 }
2595 }
1a4f550a
NC		 2596 }
2597 return 0;
2598}
a1f6e021 2599
1a4f550a
NC		 2600static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
2601{
2602 uint32_t firmware_state = 0;
1a4f550a
NC		 2603 switch (acb->adapter_type) {
2604
2605 case ACB_ADAPTER_TYPE_A: {
80da1adb 2606 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2607 do {
2608 firmware_state = readl(&reg->outbound_msgaddr1);
2609 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
2610 }
2611 break;
2612
2613 case ACB_ADAPTER_TYPE_B: {
80da1adb 2614 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2615 do {
ae52e7f0 2616 firmware_state = readl(reg->iop2drv_doorbell);
1a4f550a 2617 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
ae52e7f0 2618 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
1a4f550a
NC		 2619 }
2620 break;
cdd3cb15
NC		 2621 case ACB_ADAPTER_TYPE_C: {
2622 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2623 do {
2624 firmware_state = readl(&reg->outbound_msgaddr1);
2625 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
2626 }
a1f6e021 2627 }
1a4f550a
NC		 2628}
2629
36b83ded
NC		 2630static void arcmsr_request_hba_device_map(struct AdapterControlBlock *acb)
2631{
2632 struct MessageUnit_A __iomem *reg = acb->pmuA;
cdd3cb15 2633 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
97b99127 2634 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 2635 return;
36b83ded 2636 } else {
ae52e7f0 2637 acb->fw_flag = FW_NORMAL;
cdd3cb15 2638 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)){
36b83ded
NC		 2639 atomic_set(&acb->rq_map_token, 16);
2640 }
ae52e7f0 2641 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
97b99127
N		 2642 if (atomic_dec_and_test(&acb->rq_map_token)) {
2643 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 2644 return;
97b99127 2645 }
36b83ded 2646 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
cdd3cb15 2647 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
36b83ded 2648 }
36b83ded
NC		 2649 return;
2650}
2651
2652static void arcmsr_request_hbb_device_map(struct AdapterControlBlock *acb)
2653{
2654 struct MessageUnit_B __iomem *reg = acb->pmuB;
cdd3cb15 2655 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
97b99127 2656 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
cdd3cb15
NC		 2657 return;
2658 } else {
2659 acb->fw_flag = FW_NORMAL;
2660 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
97b99127 2661 atomic_set(&acb->rq_map_token, 16);
cdd3cb15
NC		 2662 }
2663 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
97b99127
N		 2664 if (atomic_dec_and_test(&acb->rq_map_token)) {
2665 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
cdd3cb15 2666 return;
97b99127 2667 }
cdd3cb15
NC		 2668 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
2669 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
2670 }
2671 return;
2672}
36b83ded 2673
cdd3cb15
NC		 2674static void arcmsr_request_hbc_device_map(struct AdapterControlBlock *acb)
2675{
2676 struct MessageUnit_C __iomem *reg = acb->pmuC;
ae52e7f0 2677 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0) || ((acb->acb_flags & ACB_F_ABORT) != 0)) {
97b99127 2678 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 2679 return;
36b83ded 2680 } else {
ae52e7f0
NC		 2681 acb->fw_flag = FW_NORMAL;
2682 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
36b83ded
NC		 2683 atomic_set(&acb->rq_map_token, 16);
2684 }
ae52e7f0 2685 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
97b99127
N		 2686 if (atomic_dec_and_test(&acb->rq_map_token)) {
2687 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 2688 return;
97b99127 2689 }
cdd3cb15
NC		 2690 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
2691 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2692 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
36b83ded 2693 }
36b83ded
NC		 2694 return;
2695}
2696
2697static void arcmsr_request_device_map(unsigned long pacb)
2698{
2699 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)pacb;
36b83ded
NC		 2700 switch (acb->adapter_type) {
2701 case ACB_ADAPTER_TYPE_A: {
2702 arcmsr_request_hba_device_map(acb);
2703 }
2704 break;
2705 case ACB_ADAPTER_TYPE_B: {
2706 arcmsr_request_hbb_device_map(acb);
2707 }
2708 break;
cdd3cb15
NC		 2709 case ACB_ADAPTER_TYPE_C: {
2710 arcmsr_request_hbc_device_map(acb);
2711 }
36b83ded
NC		 2712 }
2713}
2714
1a4f550a
NC		 2715static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
2716{
80da1adb 2717 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2718 acb->acb_flags |= ACB_F_MSG_START_BGRB;
2719 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
cdd3cb15 2720 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 2721 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
2722 rebulid' timeout \n", acb->host->host_no);
a1f6e021 2723 }
a1f6e021 2724}
2725
1a4f550a
NC		 2726static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
2727{
80da1adb 2728 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2729 acb->acb_flags |= ACB_F_MSG_START_BGRB;
ae52e7f0 2730 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
cdd3cb15 2731 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2732 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
2733 rebulid' timeout \n",acb->host->host_no);
2734 }
2735}
1c57e86d 2736
cdd3cb15
NC		 2737static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *pACB)
2738{
2739 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
2740 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
2741 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
2742 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
2743 if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
2744 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
2745 rebulid' timeout \n", pACB->host->host_no);
2746 }
2747 return;
2748}
1a4f550a 2749static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
1c57e86d 2750{
1a4f550a
NC		 2751 switch (acb->adapter_type) {
2752 case ACB_ADAPTER_TYPE_A:
2753 arcmsr_start_hba_bgrb(acb);
2754 break;
2755 case ACB_ADAPTER_TYPE_B:
2756 arcmsr_start_hbb_bgrb(acb);
2757 break;
cdd3cb15
NC		 2758 case ACB_ADAPTER_TYPE_C:
2759 arcmsr_start_hbc_bgrb(acb);
1a4f550a
NC		 2760 }
2761}
1c57e86d 2762
1a4f550a
NC		 2763static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
2764{
2765 switch (acb->adapter_type) {
2766 case ACB_ADAPTER_TYPE_A: {
80da1adb 2767 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2768 uint32_t outbound_doorbell;
2769 /* empty doorbell Qbuffer if door bell ringed */
2770 outbound_doorbell = readl(&reg->outbound_doorbell);
2771 /*clear doorbell interrupt */
2772 writel(outbound_doorbell, &reg->outbound_doorbell);
2773 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
2774 }
2775 break;
1c57e86d 2776
1a4f550a 2777 case ACB_ADAPTER_TYPE_B: {
80da1adb 2778 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2779 /*clear interrupt and message state*/
ae52e7f0
NC		 2780 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
2781 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1a4f550a
NC		 2782 /* let IOP know data has been read */
2783 }
2784 break;
cdd3cb15
NC		 2785 case ACB_ADAPTER_TYPE_C: {
2786 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2787 uint32_t outbound_doorbell;
2788 /* empty doorbell Qbuffer if door bell ringed */
2789 outbound_doorbell = readl(&reg->outbound_doorbell);
2790 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
2791 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
2792 }
1c57e86d 2793 }
1a4f550a 2794}
1c57e86d 2795
76d78300
NC		 2796static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
2797{
2798 switch (acb->adapter_type) {
2799 case ACB_ADAPTER_TYPE_A:
2800 return;
2801 case ACB_ADAPTER_TYPE_B:
2802 {
2803 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2804 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
cdd3cb15 2805 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
76d78300
NC		 2806 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
2807 return;
2808 }
2809 }
2810 break;
cdd3cb15
NC		 2811 case ACB_ADAPTER_TYPE_C:
2812 return;
76d78300
NC		 2813 }
2814 return;
2815}
2816
36b83ded
NC		 2817static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
2818{
2819 uint8_t value[64];
cdd3cb15
NC		 2820 int i, count = 0;
2821 struct MessageUnit_A __iomem *pmuA = acb->pmuA;
2822 struct MessageUnit_C __iomem *pmuC = acb->pmuC;
6ad819b0 2823
36b83ded 2824 /* backup pci config data */
cdd3cb15 2825 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
36b83ded
NC		 2826 for (i = 0; i < 64; i++) {
2827 pci_read_config_byte(acb->pdev, i, &value[i]);
2828 }
2829 /* hardware reset signal */
ae52e7f0 2830 if ((acb->dev_id == 0x1680)) {
cdd3cb15
NC		 2831 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
2832 } else if ((acb->dev_id == 0x1880)) {
2833 do {
2834 count++;
2835 writel(0xF, &pmuC->write_sequence);
2836 writel(0x4, &pmuC->write_sequence);
2837 writel(0xB, &pmuC->write_sequence);
2838 writel(0x2, &pmuC->write_sequence);
2839 writel(0x7, &pmuC->write_sequence);
2840 writel(0xD, &pmuC->write_sequence);
6ad819b0 2841 } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
cdd3cb15 2842 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
ae52e7f0 2843 } else {
cdd3cb15 2844 pci_write_config_byte(acb->pdev, 0x84, 0x20);
ae52e7f0 2845 }
cdd3cb15 2846 msleep(2000);
36b83ded
NC		 2847 /* write back pci config data */
2848 for (i = 0; i < 64; i++) {
2849 pci_write_config_byte(acb->pdev, i, value[i]);
2850 }
2851 msleep(1000);
2852 return;
2853}
1a4f550a
NC		 2854static void arcmsr_iop_init(struct AdapterControlBlock *acb)
2855{
2856 uint32_t intmask_org;
cdd3cb15
NC		 2857 /* disable all outbound interrupt */
2858 intmask_org = arcmsr_disable_outbound_ints(acb);
76d78300
NC		 2859 arcmsr_wait_firmware_ready(acb);
2860 arcmsr_iop_confirm(acb);
1a4f550a
NC		 2861 /*start background rebuild*/
2862 arcmsr_start_adapter_bgrb(acb);
2863 /* empty doorbell Qbuffer if door bell ringed */
2864 arcmsr_clear_doorbell_queue_buffer(acb);
76d78300 2865 arcmsr_enable_eoi_mode(acb);
1a4f550a
NC		 2866 /* enable outbound Post Queue,outbound doorbell Interrupt */
2867 arcmsr_enable_outbound_ints(acb, intmask_org);
1c57e86d
EC		 2868 acb->acb_flags |= ACB_F_IOP_INITED;
2869}
2870
36b83ded 2871static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
1c57e86d 2872{
1c57e86d
EC		 2873 struct CommandControlBlock *ccb;
2874 uint32_t intmask_org;
36b83ded 2875 uint8_t rtnval = 0x00;
1c57e86d 2876 int i = 0;
97b99127
N		 2877 unsigned long flags;
2878
1c57e86d 2879 if (atomic_read(&acb->ccboutstandingcount) != 0) {
36b83ded
NC		 2880 /* disable all outbound interrupt */
2881 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d 2882 /* talk to iop 331 outstanding command aborted */
36b83ded 2883 rtnval = arcmsr_abort_allcmd(acb);
1c57e86d 2884 /* clear all outbound posted Q */
1a4f550a 2885 arcmsr_done4abort_postqueue(acb);
1c57e86d
EC		 2886 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
2887 ccb = acb->pccb_pool[i];
a1f6e021 2888 if (ccb->startdone == ARCMSR_CCB_START) {
97b99127
N		 2889 scsi_dma_unmap(ccb->pcmd);
2890 ccb->startdone = ARCMSR_CCB_DONE;
2891 ccb->ccb_flags = 0;
2892 spin_lock_irqsave(&acb->ccblist_lock, flags);
2893 list_add_tail(&ccb->list, &acb->ccb_free_list);
2894 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 2895 }
2896 }
36b83ded 2897 atomic_set(&acb->ccboutstandingcount, 0);
1c57e86d
EC		 2898 /* enable all outbound interrupt */
2899 arcmsr_enable_outbound_ints(acb, intmask_org);
36b83ded 2900 return rtnval;
1c57e86d 2901 }
36b83ded 2902 return rtnval;
1c57e86d
EC		 2903}
2904
2905static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
2906{
97b99127 2907 struct AdapterControlBlock *acb;
ae52e7f0
NC		 2908 uint32_t intmask_org, outbound_doorbell;
2909 int retry_count = 0;
2910 int rtn = FAILED;
ae52e7f0 2911 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
cdd3cb15 2912 printk(KERN_ERR "arcmsr: executing bus reset eh.....num_resets = %d, num_aborts = %d \n", acb->num_resets, acb->num_aborts);
36b83ded 2913 acb->num_resets++;
36b83ded 2914
cdd3cb15
NC		 2915 switch(acb->adapter_type){
2916 case ACB_ADAPTER_TYPE_A:{
2917 if (acb->acb_flags & ACB_F_BUS_RESET){
ae52e7f0 2918 long timeout;
cdd3cb15
NC		 2919 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
2920 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
ae52e7f0
NC		 2921 if (timeout) {
2922 return SUCCESS;
2923 }
2924 }
2925 acb->acb_flags |= ACB_F_BUS_RESET;
cdd3cb15 2926 if (!arcmsr_iop_reset(acb)) {
ae52e7f0
NC		 2927 struct MessageUnit_A __iomem *reg;
2928 reg = acb->pmuA;
cdd3cb15
NC		 2929 arcmsr_hardware_reset(acb);
2930 acb->acb_flags &= ~ACB_F_IOP_INITED;
36b83ded 2931sleep_again:
8b7eb86f 2932 ssleep(ARCMSR_SLEEPTIME);
ae52e7f0 2933 if ((readl(&reg->outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) {
8b7eb86f
TH		 2934 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
2935 if (retry_count > ARCMSR_RETRYCOUNT) {
ae52e7f0 2936 acb->fw_flag = FW_DEADLOCK;
8b7eb86f 2937 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
ae52e7f0 2938 return FAILED;
cdd3cb15
NC		 2939 }
2940 retry_count++;
2941 goto sleep_again;
2942 }
2943 acb->acb_flags |= ACB_F_IOP_INITED;
2944 /* disable all outbound interrupt */
2945 intmask_org = arcmsr_disable_outbound_ints(acb);
ae52e7f0 2946 arcmsr_get_firmware_spec(acb);
cdd3cb15
NC		 2947 arcmsr_start_adapter_bgrb(acb);
2948 /* clear Qbuffer if door bell ringed */
2949 outbound_doorbell = readl(&reg->outbound_doorbell);
2950 writel(outbound_doorbell, &reg->outbound_doorbell); /*clear interrupt */
2951 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
2952 /* enable outbound Post Queue,outbound doorbell Interrupt */
2953 arcmsr_enable_outbound_ints(acb, intmask_org);
2954 atomic_set(&acb->rq_map_token, 16);
ae52e7f0
NC		 2955 atomic_set(&acb->ante_token_value, 16);
2956 acb->fw_flag = FW_NORMAL;
97b99127 2957 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0
NC		 2958 acb->acb_flags &= ~ACB_F_BUS_RESET;
2959 rtn = SUCCESS;
cdd3cb15 2960 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
ae52e7f0
NC		 2961 } else {
2962 acb->acb_flags &= ~ACB_F_BUS_RESET;
97b99127
N		 2963 atomic_set(&acb->rq_map_token, 16);
2964 atomic_set(&acb->ante_token_value, 16);
2965 acb->fw_flag = FW_NORMAL;
2966 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
ae52e7f0 2967 rtn = SUCCESS;
cdd3cb15 2968 }
ae52e7f0 2969 break;
36b83ded 2970 }
ae52e7f0
NC		 2971 case ACB_ADAPTER_TYPE_B:{
2972 acb->acb_flags |= ACB_F_BUS_RESET;
cdd3cb15 2973 if (!arcmsr_iop_reset(acb)) {
ae52e7f0
NC		 2974 acb->acb_flags &= ~ACB_F_BUS_RESET;
2975 rtn = FAILED;
cdd3cb15
NC		 2976 } else {
2977 acb->acb_flags &= ~ACB_F_BUS_RESET;
97b99127
N		 2978 atomic_set(&acb->rq_map_token, 16);
2979 atomic_set(&acb->ante_token_value, 16);
2980 acb->fw_flag = FW_NORMAL;
2981 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 2982 rtn = SUCCESS;
cdd3cb15
NC		 2983 }
2984 break;
2985 }
2986 case ACB_ADAPTER_TYPE_C:{
2987 if (acb->acb_flags & ACB_F_BUS_RESET) {
2988 long timeout;
2989 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
2990 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
2991 if (timeout) {
2992 return SUCCESS;
2993 }
2994 }
2995 acb->acb_flags |= ACB_F_BUS_RESET;
2996 if (!arcmsr_iop_reset(acb)) {
2997 struct MessageUnit_C __iomem *reg;
2998 reg = acb->pmuC;
2999 arcmsr_hardware_reset(acb);
3000 acb->acb_flags &= ~ACB_F_IOP_INITED;
3001sleep:
8b7eb86f 3002 ssleep(ARCMSR_SLEEPTIME);
cdd3cb15 3003 if ((readl(&reg->host_diagnostic) & 0x04) != 0) {
8b7eb86f
TH		 3004 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
3005 if (retry_count > ARCMSR_RETRYCOUNT) {
cdd3cb15 3006 acb->fw_flag = FW_DEADLOCK;
8b7eb86f 3007 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
cdd3cb15
NC		 3008 return FAILED;
3009 }
3010 retry_count++;
3011 goto sleep;
3012 }
3013 acb->acb_flags |= ACB_F_IOP_INITED;
3014 /* disable all outbound interrupt */
3015 intmask_org = arcmsr_disable_outbound_ints(acb);
3016 arcmsr_get_firmware_spec(acb);
3017 arcmsr_start_adapter_bgrb(acb);
3018 /* clear Qbuffer if door bell ringed */
3019 outbound_doorbell = readl(&reg->outbound_doorbell);
3020 writel(outbound_doorbell, &reg->outbound_doorbell_clear); /*clear interrupt */
3021 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
3022 /* enable outbound Post Queue,outbound doorbell Interrupt */
3023 arcmsr_enable_outbound_ints(acb, intmask_org);
3024 atomic_set(&acb->rq_map_token, 16);
3025 atomic_set(&acb->ante_token_value, 16);
3026 acb->fw_flag = FW_NORMAL;
97b99127 3027 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
cdd3cb15
NC		 3028 acb->acb_flags &= ~ACB_F_BUS_RESET;
3029 rtn = SUCCESS;
3030 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
3031 } else {
3032 acb->acb_flags &= ~ACB_F_BUS_RESET;
97b99127
N		 3033 atomic_set(&acb->rq_map_token, 16);
3034 atomic_set(&acb->ante_token_value, 16);
3035 acb->fw_flag = FW_NORMAL;
3036 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
cdd3cb15
NC		 3037 rtn = SUCCESS;
3038 }
3039 break;
ae52e7f0
NC		 3040 }
3041 }
3042 return rtn;
1c57e86d
EC		 3043}
3044
ae52e7f0 3045static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
1c57e86d
EC		 3046 struct CommandControlBlock *ccb)
3047{
ae52e7f0 3048 int rtn;
ae52e7f0 3049 rtn = arcmsr_polling_ccbdone(acb, ccb);
ae52e7f0 3050 return rtn;
1c57e86d
EC		 3051}
3052
3053static int arcmsr_abort(struct scsi_cmnd *cmd)
3054{
3055 struct AdapterControlBlock *acb =
3056 (struct AdapterControlBlock *)cmd->device->host->hostdata;
3057 int i = 0;
ae52e7f0 3058 int rtn = FAILED;
1c57e86d 3059 printk(KERN_NOTICE
a1f6e021 3060 "arcmsr%d: abort device command of scsi id = %d lun = %d \n",
1c57e86d 3061 acb->host->host_no, cmd->device->id, cmd->device->lun);
ae52e7f0 3062 acb->acb_flags |= ACB_F_ABORT;
1c57e86d 3063 acb->num_aborts++;
1c57e86d
EC		 3064 /*
3065 ************************************************
3066 ** the all interrupt service routine is locked
3067 ** we need to handle it as soon as possible and exit
3068 ************************************************
3069 */
3070 if (!atomic_read(&acb->ccboutstandingcount))
ae52e7f0 3071 return rtn;
1c57e86d
EC		 3072
3073 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
3074 struct CommandControlBlock *ccb = acb->pccb_pool[i];
3075 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
ae52e7f0
NC		 3076 ccb->startdone = ARCMSR_CCB_ABORTED;
3077 rtn = arcmsr_abort_one_cmd(acb, ccb);
1c57e86d
EC		 3078 break;
3079 }
3080 }
ae52e7f0
NC		 3081 acb->acb_flags &= ~ACB_F_ABORT;
3082 return rtn;
1c57e86d
EC		 3083}
3084
3085static const char *arcmsr_info(struct Scsi_Host *host)
3086{
3087 struct AdapterControlBlock *acb =
3088 (struct AdapterControlBlock *) host->hostdata;
3089 static char buf[256];
3090 char *type;
3091 int raid6 = 1;
1c57e86d
EC		 3092 switch (acb->pdev->device) {
3093 case PCI_DEVICE_ID_ARECA_1110:
1a4f550a
NC		 3094 case PCI_DEVICE_ID_ARECA_1200:
3095 case PCI_DEVICE_ID_ARECA_1202:
1c57e86d
EC		 3096 case PCI_DEVICE_ID_ARECA_1210:
3097 raid6 = 0;
3098 /*FALLTHRU*/
3099 case PCI_DEVICE_ID_ARECA_1120:
3100 case PCI_DEVICE_ID_ARECA_1130:
3101 case PCI_DEVICE_ID_ARECA_1160:
3102 case PCI_DEVICE_ID_ARECA_1170:
1a4f550a 3103 case PCI_DEVICE_ID_ARECA_1201:
1c57e86d
EC		 3104 case PCI_DEVICE_ID_ARECA_1220:
3105 case PCI_DEVICE_ID_ARECA_1230:
3106 case PCI_DEVICE_ID_ARECA_1260:
3107 case PCI_DEVICE_ID_ARECA_1270:
3108 case PCI_DEVICE_ID_ARECA_1280:
3109 type = "SATA";
3110 break;
3111 case PCI_DEVICE_ID_ARECA_1380:
3112 case PCI_DEVICE_ID_ARECA_1381:
3113 case PCI_DEVICE_ID_ARECA_1680:
3114 case PCI_DEVICE_ID_ARECA_1681:
cdd3cb15 3115 case PCI_DEVICE_ID_ARECA_1880:
1c57e86d
EC		 3116 type = "SAS";
3117 break;
3118 default:
3119 type = "X-TYPE";
3120 break;
3121 }
a1f6e021 3122 sprintf(buf, "Areca %s Host Adapter RAID Controller%s\n %s",
1c57e86d
EC		 3123 type, raid6 ? "( RAID6 capable)" : "",
3124 ARCMSR_DRIVER_VERSION);
3125 return buf;
3126}
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