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Fix unprotected access to task credentials in waitid()
[mirror_ubuntu-hirsute-kernel.git] / drivers / scsi / arcmsr / arcmsr_hba.c
CommitLineData
1c57e86d
EC		 1/*
2*******************************************************************************
3** O.S : Linux
4** FILE NAME : arcmsr_hba.c
5** BY : Erich Chen
6** Description: SCSI RAID Device Driver for
7** ARECA RAID Host adapter
8*******************************************************************************
9** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved
10**
11** Web site: www.areca.com.tw
1a4f550a 12** E-mail: support@areca.com.tw
1c57e86d
EC		 13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License version 2 as
16** published by the Free Software Foundation.
17** This program is distributed in the hope that it will be useful,
18** but WITHOUT ANY WARRANTY; without even the implied warranty of
19** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20** GNU General Public License for more details.
21*******************************************************************************
22** Redistribution and use in source and binary forms, with or without
23** modification, are permitted provided that the following conditions
24** are met:
25** 1. Redistributions of source code must retain the above copyright
26** notice, this list of conditions and the following disclaimer.
27** 2. Redistributions in binary form must reproduce the above copyright
28** notice, this list of conditions and the following disclaimer in the
29** documentation and/or other materials provided with the distribution.
30** 3. The name of the author may not be used to endorse or promote products
31** derived from this software without specific prior written permission.
32**
33** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
34** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
35** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
36** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
37** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
38** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
40** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43*******************************************************************************
44** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
45** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
46*******************************************************************************
47*/
48#include <linux/module.h>
49#include <linux/reboot.h>
50#include <linux/spinlock.h>
51#include <linux/pci_ids.h>
52#include <linux/interrupt.h>
53#include <linux/moduleparam.h>
54#include <linux/errno.h>
55#include <linux/types.h>
56#include <linux/delay.h>
57#include <linux/dma-mapping.h>
58#include <linux/timer.h>
59#include <linux/pci.h>
a1f6e021 60#include <linux/aer.h>
1c57e86d
EC		 61#include <asm/dma.h>
62#include <asm/io.h>
63#include <asm/system.h>
64#include <asm/uaccess.h>
65#include <scsi/scsi_host.h>
66#include <scsi/scsi.h>
67#include <scsi/scsi_cmnd.h>
68#include <scsi/scsi_tcq.h>
69#include <scsi/scsi_device.h>
70#include <scsi/scsi_transport.h>
71#include <scsi/scsicam.h>
72#include "arcmsr.h"
ae52e7f0 73MODULE_AUTHOR("Nick Cheng <support@areca.com.tw>");
cdd3cb15 74MODULE_DESCRIPTION("ARECA (ARC11xx/12xx/16xx/1880) SATA/SAS RAID Host Bus Adapter");
1c57e86d
EC		 75MODULE_LICENSE("Dual BSD/GPL");
76MODULE_VERSION(ARCMSR_DRIVER_VERSION);
cdd3cb15
NC		 77static int sleeptime = 10;
78static int retrycount = 30;
ae52e7f0 79wait_queue_head_t wait_q;
1a4f550a
NC		 80static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
81 struct scsi_cmnd *cmd);
82static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
1c57e86d
EC		 83static int arcmsr_abort(struct scsi_cmnd *);
84static int arcmsr_bus_reset(struct scsi_cmnd *);
85static int arcmsr_bios_param(struct scsi_device *sdev,
1a4f550a
NC		 86 struct block_device *bdev, sector_t capacity, int *info);
87static int arcmsr_queue_command(struct scsi_cmnd *cmd,
88 void (*done) (struct scsi_cmnd *));
1c57e86d
EC		 89static int arcmsr_probe(struct pci_dev *pdev,
90 const struct pci_device_id *id);
91static void arcmsr_remove(struct pci_dev *pdev);
92static void arcmsr_shutdown(struct pci_dev *pdev);
93static void arcmsr_iop_init(struct AdapterControlBlock *acb);
94static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
1a4f550a 95static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
1c57e86d 96static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
1a4f550a
NC		 97static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb);
98static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb);
36b83ded
NC		 99static void arcmsr_request_device_map(unsigned long pacb);
100static void arcmsr_request_hba_device_map(struct AdapterControlBlock *acb);
101static void arcmsr_request_hbb_device_map(struct AdapterControlBlock *acb);
cdd3cb15 102static void arcmsr_request_hbc_device_map(struct AdapterControlBlock *acb);
36b83ded 103static void arcmsr_message_isr_bh_fn(struct work_struct *work);
ae52e7f0 104static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
36b83ded 105static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
cdd3cb15
NC		 106static void arcmsr_hbc_message_isr(struct AdapterControlBlock *pACB);
107static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
1c57e86d
EC		 108static const char *arcmsr_info(struct Scsi_Host *);
109static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
1a4f550a 110static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev,
e881a172 111 int queue_depth, int reason)
1c57e86d 112{
e881a172
MC		 113 if (reason != SCSI_QDEPTH_DEFAULT)
114 return -EOPNOTSUPP;
115
1c57e86d
EC		 116 if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
117 queue_depth = ARCMSR_MAX_CMD_PERLUN;
118 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, queue_depth);
119 return queue_depth;
120}
121
122static struct scsi_host_template arcmsr_scsi_host_template = {
123 .module = THIS_MODULE,
cdd3cb15
NC		 124 .name = "ARCMSR ARECA SATA/SAS RAID Controller"
125 ARCMSR_DRIVER_VERSION,
1c57e86d
EC		 126 .info = arcmsr_info,
127 .queuecommand = arcmsr_queue_command,
cdd3cb15 128 .eh_abort_handler = arcmsr_abort,
1c57e86d
EC		 129 .eh_bus_reset_handler = arcmsr_bus_reset,
130 .bios_param = arcmsr_bios_param,
131 .change_queue_depth = arcmsr_adjust_disk_queue_depth,
ae52e7f0 132 .can_queue = ARCMSR_MAX_FREECCB_NUM,
cdd3cb15
NC		 133 .this_id = ARCMSR_SCSI_INITIATOR_ID,
134 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
135 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
1c57e86d
EC		 136 .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
137 .use_clustering = ENABLE_CLUSTERING,
138 .shost_attrs = arcmsr_host_attrs,
139};
1c57e86d
EC		 140static struct pci_device_id arcmsr_device_id_table[] = {
141 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110)},
142 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120)},
143 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130)},
144 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160)},
145 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170)},
1a4f550a
NC		 146 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200)},
147 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201)},
148 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202)},
1c57e86d
EC		 149 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210)},
150 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220)},
151 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230)},
152 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260)},
153 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270)},
154 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280)},
155 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380)},
156 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381)},
157 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680)},
158 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681)},
ae52e7f0 159 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880)},
1c57e86d
EC		 160 {0, 0}, /* Terminating entry */
161};
162MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
163static struct pci_driver arcmsr_pci_driver = {
164 .name = "arcmsr",
cdd3cb15 165 .id_table = arcmsr_device_id_table,
1c57e86d
EC		 166 .probe = arcmsr_probe,
167 .remove = arcmsr_remove,
a1f6e021 168 .shutdown = arcmsr_shutdown,
1c57e86d 169};
cdd3cb15
NC		 170/*
171****************************************************************************
172****************************************************************************
173*/
174int arcmsr_sleep_for_bus_reset(struct scsi_cmnd *cmd)
175{
176 struct Scsi_Host *shost = NULL;
177 int i, isleep;
178 shost = cmd->device->host;
179 isleep = sleeptime / 10;
180 if (isleep > 0) {
181 for (i = 0; i < isleep; i++) {
182 msleep(10000);
183 }
184 }
185
186 isleep = sleeptime % 10;
187 if (isleep > 0) {
188 msleep(isleep*1000);
189 }
190 printk(KERN_NOTICE "wake-up\n");
191 return 0;
192}
1c57e86d 193
cdd3cb15 194static void arcmsr_free_hbb_mu(struct AdapterControlBlock *acb)
ae52e7f0
NC		 195{
196 switch (acb->adapter_type) {
197 case ACB_ADAPTER_TYPE_A:
cdd3cb15 198 case ACB_ADAPTER_TYPE_C:
ae52e7f0
NC		 199 break;
200 case ACB_ADAPTER_TYPE_B:{
cdd3cb15
NC		 201 dma_free_coherent(&acb->pdev->dev,
202 sizeof(struct MessageUnit_B),
203 acb->pmuB, acb->dma_coherent_handle_hbb_mu);
ae52e7f0
NC		 204 }
205 }
206}
207
208static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
209{
210 struct pci_dev *pdev = acb->pdev;
cdd3cb15 211 switch (acb->adapter_type){
ae52e7f0 212 case ACB_ADAPTER_TYPE_A:{
cdd3cb15 213 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
ae52e7f0
NC		 214 if (!acb->pmuA) {
215 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
216 return false;
217 }
218 break;
219 }
220 case ACB_ADAPTER_TYPE_B:{
221 void __iomem *mem_base0, *mem_base1;
222 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
223 if (!mem_base0) {
224 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
225 return false;
226 }
227 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
228 if (!mem_base1) {
229 iounmap(mem_base0);
230 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
231 return false;
232 }
233 acb->mem_base0 = mem_base0;
234 acb->mem_base1 = mem_base1;
cdd3cb15
NC		 235 break;
236 }
237 case ACB_ADAPTER_TYPE_C:{
238 acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
239 if (!acb->pmuC) {
240 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
241 return false;
242 }
243 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
244 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
245 return true;
246 }
247 break;
ae52e7f0
NC		 248 }
249 }
250 return true;
251}
252
253static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
254{
255 switch (acb->adapter_type) {
cdd3cb15
NC		 256 case ACB_ADAPTER_TYPE_A:{
257 iounmap(acb->pmuA);
258 }
259 break;
260 case ACB_ADAPTER_TYPE_B:{
261 iounmap(acb->mem_base0);
262 iounmap(acb->mem_base1);
263 }
264
265 break;
266 case ACB_ADAPTER_TYPE_C:{
267 iounmap(acb->pmuC);
268 }
ae52e7f0
NC		 269 }
270}
271
7d12e780 272static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
1c57e86d
EC		 273{
274 irqreturn_t handle_state;
1a4f550a 275 struct AdapterControlBlock *acb = dev_id;
1c57e86d 276
1c57e86d 277 handle_state = arcmsr_interrupt(acb);
1c57e86d
EC		 278 return handle_state;
279}
280
281static int arcmsr_bios_param(struct scsi_device *sdev,
282 struct block_device *bdev, sector_t capacity, int *geom)
283{
284 int ret, heads, sectors, cylinders, total_capacity;
285 unsigned char *buffer;/* return copy of block device's partition table */
286
287 buffer = scsi_bios_ptable(bdev);
288 if (buffer) {
289 ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
290 kfree(buffer);
291 if (ret != -1)
292 return ret;
293 }
294 total_capacity = capacity;
295 heads = 64;
296 sectors = 32;
297 cylinders = total_capacity / (heads * sectors);
298 if (cylinders > 1024) {
299 heads = 255;
300 sectors = 63;
301 cylinders = total_capacity / (heads * sectors);
302 }
303 geom[0] = heads;
304 geom[1] = sectors;
305 geom[2] = cylinders;
306 return 0;
307}
308
1a4f550a 309static void arcmsr_define_adapter_type(struct AdapterControlBlock *acb)
1c57e86d
EC		 310{
311 struct pci_dev *pdev = acb->pdev;
1a4f550a
NC		 312 u16 dev_id;
313 pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
ae52e7f0 314 acb->dev_id = dev_id;
1a4f550a 315 switch (dev_id) {
cdd3cb15
NC		 316 case 0x1880: {
317 acb->adapter_type = ACB_ADAPTER_TYPE_C;
318 }
319 break;
320 case 0x1201: {
1a4f550a
NC		 321 acb->adapter_type = ACB_ADAPTER_TYPE_B;
322 }
323 break;
324
cdd3cb15 325 default: acb->adapter_type = ACB_ADAPTER_TYPE_A;
1a4f550a 326 }
cdd3cb15 327}
1a4f550a 328
ae52e7f0
NC		 329static uint8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
330{
331 struct MessageUnit_A __iomem *reg = acb->pmuA;
332 uint32_t Index;
333 uint8_t Retries = 0x00;
ae52e7f0
NC		 334 do {
335 for (Index = 0; Index < 100; Index++) {
336 if (readl(&reg->outbound_intstatus) &
337 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
338 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
339 &reg->outbound_intstatus);
cdd3cb15 340 return true;
ae52e7f0
NC		 341 }
342 msleep(10);
cdd3cb15 343 }/*max 1 seconds*/
ae52e7f0
NC		 344
345 } while (Retries++ < 20);/*max 20 sec*/
cdd3cb15 346 return false;
ae52e7f0
NC		 347}
348
349static uint8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
1a4f550a 350{
ae52e7f0
NC		 351 struct MessageUnit_B *reg = acb->pmuB;
352 uint32_t Index;
353 uint8_t Retries = 0x00;
ae52e7f0
NC		 354 do {
355 for (Index = 0; Index < 100; Index++) {
356 if (readl(reg->iop2drv_doorbell)
357 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
358 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN
359 , reg->iop2drv_doorbell);
360 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
cdd3cb15 361 return true;
ae52e7f0
NC		 362 }
363 msleep(10);
cdd3cb15 364 }/*max 1 seconds*/
ae52e7f0
NC		 365
366 } while (Retries++ < 20);/*max 20 sec*/
cdd3cb15 367 return false;
ae52e7f0
NC		 368}
369
cdd3cb15
NC		 370static uint8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *pACB)
371{
372 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
373 unsigned char Retries = 0x00;
374 uint32_t Index;
375 do {
376 for (Index = 0; Index < 100; Index++) {
377 if (readl(&phbcmu->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
378 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &phbcmu->outbound_doorbell_clear);/*clear interrupt*/
379 return true;
380 }
381 /* one us delay */
382 msleep(10);
383 } /*max 1 seconds*/
384 } while (Retries++ < 20); /*max 20 sec*/
385 return false;
386}
ae52e7f0
NC		 387static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
388{
389 struct MessageUnit_A __iomem *reg = acb->pmuA;
390 int retry_count = 30;
ae52e7f0
NC		 391 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
392 do {
cdd3cb15 393 if (arcmsr_hba_wait_msgint_ready(acb))
ae52e7f0
NC		 394 break;
395 else {
396 retry_count--;
397 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
398 timeout, retry count down = %d \n", acb->host->host_no, retry_count);
399 }
400 } while (retry_count != 0);
401}
402
403static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
404{
405 struct MessageUnit_B *reg = acb->pmuB;
406 int retry_count = 30;
ae52e7f0
NC		 407 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
408 do {
cdd3cb15 409 if (arcmsr_hbb_wait_msgint_ready(acb))
ae52e7f0
NC		 410 break;
411 else {
412 retry_count--;
413 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
414 timeout,retry count down = %d \n", acb->host->host_no, retry_count);
415 }
416 } while (retry_count != 0);
417}
418
cdd3cb15
NC		 419static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *pACB)
420{
421 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
422 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
423 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
424 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
425 do {
426 if (arcmsr_hbc_wait_msgint_ready(pACB)) {
427 break;
428 } else {
429 retry_count--;
430 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
431 timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
432 }
433 } while (retry_count != 0);
434 return;
435}
ae52e7f0
NC		 436static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
437{
1a4f550a 438 switch (acb->adapter_type) {
1c57e86d 439
1a4f550a 440 case ACB_ADAPTER_TYPE_A: {
ae52e7f0
NC		 441 arcmsr_flush_hba_cache(acb);
442 }
443 break;
1a4f550a 444
ae52e7f0
NC		 445 case ACB_ADAPTER_TYPE_B: {
446 arcmsr_flush_hbb_cache(acb);
1a4f550a 447 }
cdd3cb15
NC		 448 break;
449 case ACB_ADAPTER_TYPE_C: {
450 arcmsr_flush_hbc_cache(acb);
451 }
ae52e7f0
NC		 452 }
453}
1a4f550a 454
ae52e7f0
NC		 455static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
456{
cdd3cb15
NC		 457 struct pci_dev *pdev = acb->pdev;
458 void *dma_coherent;
459 dma_addr_t dma_coherent_handle;
460 struct CommandControlBlock *ccb_tmp;
461 int i = 0, j = 0;
462 dma_addr_t cdb_phyaddr;
463 unsigned long roundup_ccbsize = 0, offset;
464 unsigned long max_xfer_len;
465 unsigned long max_sg_entrys;
466 uint32_t firm_config_version;
467 for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
468 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
469 acb->devstate[i][j] = ARECA_RAID_GONE;
470
471 max_xfer_len = ARCMSR_MAX_XFER_LEN;
472 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
473 firm_config_version = acb->firm_cfg_version;
474 if((firm_config_version & 0xFF) >= 3){
475 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
476 max_sg_entrys = (max_xfer_len/4096);
477 }
478 acb->host->max_sectors = max_xfer_len/512;
479 acb->host->sg_tablesize = max_sg_entrys;
480 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
481 acb->uncache_size = roundup_ccbsize * ARCMSR_MAX_FREECCB_NUM + 32;
482 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
483 if(!dma_coherent){
484 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error \n", acb->host->host_no);
485 return -ENOMEM;
486 }
487 acb->dma_coherent = dma_coherent;
488 acb->dma_coherent_handle = dma_coherent_handle;
489 memset(dma_coherent, 0, acb->uncache_size);
490 offset = roundup((unsigned long)dma_coherent, 32) - (unsigned long)dma_coherent;
491 dma_coherent_handle = dma_coherent_handle + offset;
492 dma_coherent = (struct CommandControlBlock *)dma_coherent + offset;
493 ccb_tmp = dma_coherent;
494 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
495 for(i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++){
496 cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
497 ccb_tmp->cdb_phyaddr_pattern = ((acb->adapter_type == ACB_ADAPTER_TYPE_C) ? cdb_phyaddr : (cdb_phyaddr >> 5));
498 acb->pccb_pool[i] = ccb_tmp;
499 ccb_tmp->acb = acb;
500 INIT_LIST_HEAD(&ccb_tmp->list);
501 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
502 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
503 dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;
1a4f550a 504 }
1c57e86d
EC		 505 return 0;
506}
36b83ded 507
cdd3cb15
NC		 508static void arcmsr_message_isr_bh_fn(struct work_struct *work)
509{
510 struct AdapterControlBlock *acb = container_of(work,struct AdapterControlBlock, arcmsr_do_message_isr_bh);
36b83ded
NC		 511 switch (acb->adapter_type) {
512 case ACB_ADAPTER_TYPE_A: {
513
514 struct MessageUnit_A __iomem *reg = acb->pmuA;
515 char *acb_dev_map = (char *)acb->device_map;
cdd3cb15
NC		 516 uint32_t __iomem *signature = (uint32_t __iomem*) (&reg->message_rwbuffer[0]);
517 char __iomem *devicemap = (char __iomem*) (&reg->message_rwbuffer[21]);
36b83ded
NC		 518 int target, lun;
519 struct scsi_device *psdev;
520 char diff;
521
522 atomic_inc(&acb->rq_map_token);
523 if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
cdd3cb15 524 for(target = 0; target < ARCMSR_MAX_TARGETID -1; target++) {
36b83ded
NC		 525 diff = (*acb_dev_map)^readb(devicemap);
526 if (diff != 0) {
527 char temp;
528 *acb_dev_map = readb(devicemap);
cdd3cb15
NC		 529 temp =*acb_dev_map;
530 for(lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
531 if((temp & 0x01)==1 && (diff & 0x01) == 1) {
36b83ded 532 scsi_add_device(acb->host, 0, target, lun);
cdd3cb15 533 }else if((temp & 0x01) == 0 && (diff & 0x01) == 1) {
36b83ded 534 psdev = scsi_device_lookup(acb->host, 0, target, lun);
cdd3cb15 535 if (psdev != NULL ) {
36b83ded
NC		 536 scsi_remove_device(psdev);
537 scsi_device_put(psdev);
538 }
539 }
540 temp >>= 1;
541 diff >>= 1;
542 }
543 }
544 devicemap++;
545 acb_dev_map++;
546 }
547 }
548 break;
549 }
550
551 case ACB_ADAPTER_TYPE_B: {
552 struct MessageUnit_B *reg = acb->pmuB;
553 char *acb_dev_map = (char *)acb->device_map;
cdd3cb15
NC		 554 uint32_t __iomem *signature = (uint32_t __iomem*)(&reg->message_rwbuffer[0]);
555 char __iomem *devicemap = (char __iomem*)(&reg->message_rwbuffer[21]);
556 int target, lun;
557 struct scsi_device *psdev;
558 char diff;
559
560 atomic_inc(&acb->rq_map_token);
561 if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
562 for(target = 0; target < ARCMSR_MAX_TARGETID -1; target++) {
563 diff = (*acb_dev_map)^readb(devicemap);
564 if (diff != 0) {
565 char temp;
566 *acb_dev_map = readb(devicemap);
567 temp =*acb_dev_map;
568 for(lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
569 if((temp & 0x01)==1 && (diff & 0x01) == 1) {
570 scsi_add_device(acb->host, 0, target, lun);
571 }else if((temp & 0x01) == 0 && (diff & 0x01) == 1) {
572 psdev = scsi_device_lookup(acb->host, 0, target, lun);
573 if (psdev != NULL ) {
574 scsi_remove_device(psdev);
575 scsi_device_put(psdev);
576 }
577 }
578 temp >>= 1;
579 diff >>= 1;
580 }
581 }
582 devicemap++;
583 acb_dev_map++;
584 }
585 }
586 }
587 break;
588 case ACB_ADAPTER_TYPE_C: {
589 struct MessageUnit_C *reg = acb->pmuC;
590 char *acb_dev_map = (char *)acb->device_map;
591 uint32_t __iomem *signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
592 char __iomem *devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
36b83ded
NC		 593 int target, lun;
594 struct scsi_device *psdev;
595 char diff;
596
597 atomic_inc(&acb->rq_map_token);
598 if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
599 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) {
600 diff = (*acb_dev_map)^readb(devicemap);
601 if (diff != 0) {
602 char temp;
603 *acb_dev_map = readb(devicemap);
604 temp = *acb_dev_map;
605 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
606 if ((temp & 0x01) == 1 && (diff & 0x01) == 1) {
607 scsi_add_device(acb->host, 0, target, lun);
608 } else if ((temp & 0x01) == 0 && (diff & 0x01) == 1) {
609 psdev = scsi_device_lookup(acb->host, 0, target, lun);
610 if (psdev != NULL) {
611 scsi_remove_device(psdev);
612 scsi_device_put(psdev);
613 }
614 }
615 temp >>= 1;
616 diff >>= 1;
617 }
618 }
619 devicemap++;
620 acb_dev_map++;
621 }
622 }
623 }
624 }
625}
1c57e86d 626
ae52e7f0 627static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1c57e86d
EC		 628{
629 struct Scsi_Host *host;
630 struct AdapterControlBlock *acb;
cdd3cb15 631 uint8_t bus,dev_fun;
1c57e86d 632 int error;
1c57e86d 633 error = pci_enable_device(pdev);
cdd3cb15 634 if(error){
ae52e7f0
NC		 635 return -ENODEV;
636 }
637 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
cdd3cb15
NC		 638 if(!host){
639 goto pci_disable_dev;
1c57e86d 640 }
6a35528a 641 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
cdd3cb15 642 if(error){
284901a9 643 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cdd3cb15 644 if(error){
1c57e86d
EC		 645 printk(KERN_WARNING
646 "scsi%d: No suitable DMA mask available\n",
647 host->host_no);
ae52e7f0 648 goto scsi_host_release;
1c57e86d
EC		 649 }
650 }
ae52e7f0 651 init_waitqueue_head(&wait_q);
1c57e86d
EC		 652 bus = pdev->bus->number;
653 dev_fun = pdev->devfn;
ae52e7f0 654 acb = (struct AdapterControlBlock *) host->hostdata;
cdd3cb15 655 memset(acb,0,sizeof(struct AdapterControlBlock));
1c57e86d 656 acb->pdev = pdev;
ae52e7f0 657 acb->host = host;
1c57e86d 658 host->max_lun = ARCMSR_MAX_TARGETLUN;
cdd3cb15
NC		 659 host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
660 host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
661 host->can_queue = ARCMSR_MAX_FREECCB_NUM; /* max simultaneous cmds */
662 host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
1c57e86d
EC		 663 host->this_id = ARCMSR_SCSI_INITIATOR_ID;
664 host->unique_id = (bus << 8) | dev_fun;
ae52e7f0
NC		 665 pci_set_drvdata(pdev, host);
666 pci_set_master(pdev);
1c57e86d 667 error = pci_request_regions(pdev, "arcmsr");
cdd3cb15 668 if(error){
ae52e7f0 669 goto scsi_host_release;
1c57e86d 670 }
ae52e7f0
NC		 671 spin_lock_init(&acb->eh_lock);
672 spin_lock_init(&acb->ccblist_lock);
1c57e86d 673 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
cdd3cb15
NC		 674 ACB_F_MESSAGE_RQBUFFER_CLEARED |
675 ACB_F_MESSAGE_WQBUFFER_READED);
1c57e86d
EC		 676 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
677 INIT_LIST_HEAD(&acb->ccb_free_list);
ae52e7f0
NC		 678 arcmsr_define_adapter_type(acb);
679 error = arcmsr_remap_pciregion(acb);
cdd3cb15 680 if(!error){
ae52e7f0
NC		 681 goto pci_release_regs;
682 }
683 error = arcmsr_get_firmware_spec(acb);
cdd3cb15 684 if(!error){
ae52e7f0
NC		 685 goto unmap_pci_region;
686 }
1c57e86d 687 error = arcmsr_alloc_ccb_pool(acb);
cdd3cb15 688 if(error){
ae52e7f0
NC		 689 goto free_hbb_mu;
690 }
36b83ded 691 arcmsr_iop_init(acb);
1c57e86d 692 error = scsi_add_host(host, &pdev->dev);
cdd3cb15 693 if(error){
ae52e7f0
NC		 694 goto RAID_controller_stop;
695 }
696 error = request_irq(pdev->irq, arcmsr_do_interrupt, IRQF_SHARED, "arcmsr", acb);
cdd3cb15 697 if(error){
ae52e7f0
NC		 698 goto scsi_host_remove;
699 }
700 host->irq = pdev->irq;
cdd3cb15 701 scsi_scan_host(host);
ae52e7f0 702 INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
36b83ded 703 atomic_set(&acb->rq_map_token, 16);
ae52e7f0
NC		 704 atomic_set(&acb->ante_token_value, 16);
705 acb->fw_flag = FW_NORMAL;
36b83ded 706 init_timer(&acb->eternal_timer);
ae52e7f0 707 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
36b83ded
NC		 708 acb->eternal_timer.data = (unsigned long) acb;
709 acb->eternal_timer.function = &arcmsr_request_device_map;
710 add_timer(&acb->eternal_timer);
cdd3cb15 711 if(arcmsr_alloc_sysfs_attr(acb))
ae52e7f0 712 goto out_free_sysfs;
1c57e86d 713 return 0;
cdd3cb15 714out_free_sysfs:
ae52e7f0
NC		 715scsi_host_remove:
716 scsi_remove_host(host);
717RAID_controller_stop:
718 arcmsr_stop_adapter_bgrb(acb);
719 arcmsr_flush_adapter_cache(acb);
1c57e86d 720 arcmsr_free_ccb_pool(acb);
ae52e7f0 721free_hbb_mu:
cdd3cb15 722 arcmsr_free_hbb_mu(acb);
ae52e7f0
NC		 723unmap_pci_region:
724 arcmsr_unmap_pciregion(acb);
725pci_release_regs:
1c57e86d 726 pci_release_regions(pdev);
ae52e7f0 727scsi_host_release:
1c57e86d 728 scsi_host_put(host);
ae52e7f0 729pci_disable_dev:
1c57e86d 730 pci_disable_device(pdev);
ae52e7f0 731 return -ENODEV;
1a4f550a
NC		 732}
733
36b83ded 734static uint8_t arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
1c57e86d 735{
80da1adb 736 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 737 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
cdd3cb15 738 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 739 printk(KERN_NOTICE
740 "arcmsr%d: wait 'abort all outstanding command' timeout \n"
741 , acb->host->host_no);
cdd3cb15 742 return false;
36b83ded 743 }
cdd3cb15 744 return true;
1a4f550a
NC		 745}
746
36b83ded 747static uint8_t arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
1a4f550a 748{
80da1adb 749 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 750
ae52e7f0 751 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
cdd3cb15 752 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1c57e86d
EC		 753 printk(KERN_NOTICE
754 "arcmsr%d: wait 'abort all outstanding command' timeout \n"
755 , acb->host->host_no);
cdd3cb15 756 return false;
36b83ded 757 }
cdd3cb15
NC		 758 return true;
759}
760static uint8_t arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *pACB)
761{
762 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
763 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
764 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
765 if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
766 printk(KERN_NOTICE
767 "arcmsr%d: wait 'abort all outstanding command' timeout \n"
768 , pACB->host->host_no);
769 return false;
770 }
771 return true;
1c57e86d 772}
36b83ded 773static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
1a4f550a 774{
36b83ded 775 uint8_t rtnval = 0;
1a4f550a
NC		 776 switch (acb->adapter_type) {
777 case ACB_ADAPTER_TYPE_A: {
36b83ded 778 rtnval = arcmsr_abort_hba_allcmd(acb);
1a4f550a
NC		 779 }
780 break;
781
782 case ACB_ADAPTER_TYPE_B: {
36b83ded 783 rtnval = arcmsr_abort_hbb_allcmd(acb);
1a4f550a 784 }
cdd3cb15
NC		 785 break;
786
787 case ACB_ADAPTER_TYPE_C: {
788 rtnval = arcmsr_abort_hbc_allcmd(acb);
789 }
1a4f550a 790 }
36b83ded 791 return rtnval;
1a4f550a
NC		 792}
793
ae52e7f0
NC		 794static bool arcmsr_hbb_enable_driver_mode(struct AdapterControlBlock *pacb)
795{
796 struct MessageUnit_B *reg = pacb->pmuB;
ae52e7f0 797 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
cdd3cb15 798 if (!arcmsr_hbb_wait_msgint_ready(pacb)) {
ae52e7f0
NC		 799 printk(KERN_ERR "arcmsr%d: can't set driver mode. \n", pacb->host->host_no);
800 return false;
cdd3cb15
NC		 801 }
802 return true;
ae52e7f0
NC		 803}
804
1c57e86d
EC		 805static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
806{
1c57e86d
EC		 807 struct scsi_cmnd *pcmd = ccb->pcmd;
808
deff2627 809 scsi_dma_unmap(pcmd);
cdd3cb15 810}
1c57e86d 811
ae52e7f0 812static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
1c57e86d
EC		 813{
814 struct AdapterControlBlock *acb = ccb->acb;
815 struct scsi_cmnd *pcmd = ccb->pcmd;
ae52e7f0 816 unsigned long flags;
ae52e7f0 817 atomic_dec(&acb->ccboutstandingcount);
1c57e86d 818 arcmsr_pci_unmap_dma(ccb);
1c57e86d 819 ccb->startdone = ARCMSR_CCB_DONE;
ae52e7f0 820 spin_lock_irqsave(&acb->ccblist_lock, flags);
1c57e86d 821 list_add_tail(&ccb->list, &acb->ccb_free_list);
ae52e7f0 822 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 823 pcmd->scsi_done(pcmd);
824}
825
1a4f550a
NC		 826static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
827{
828
829 struct scsi_cmnd *pcmd = ccb->pcmd;
830 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
1a4f550a
NC		 831 pcmd->result = DID_OK << 16;
832 if (sensebuffer) {
833 int sense_data_length =
b80ca4f7
FT		 834 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
835 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
836 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
1a4f550a
NC		 837 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
838 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
839 sensebuffer->Valid = 1;
840 }
841}
842
843static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
844{
845 u32 orig_mask = 0;
cdd3cb15 846 switch (acb->adapter_type) {
1a4f550a 847 case ACB_ADAPTER_TYPE_A : {
80da1adb 848 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 849 orig_mask = readl(&reg->outbound_intmask);
1a4f550a
NC		 850 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
851 &reg->outbound_intmask);
852 }
853 break;
1a4f550a 854 case ACB_ADAPTER_TYPE_B : {
80da1adb 855 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0
NC		 856 orig_mask = readl(reg->iop2drv_doorbell_mask);
857 writel(0, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 858 }
859 break;
cdd3cb15
NC		 860 case ACB_ADAPTER_TYPE_C:{
861 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
862 /* disable all outbound interrupt */
863 orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
864 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
865 }
866 break;
1a4f550a
NC		 867 }
868 return orig_mask;
869}
870
cdd3cb15
NC		 871static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
872 struct CommandControlBlock *ccb, bool error)
1a4f550a 873{
1a4f550a
NC		 874 uint8_t id, lun;
875 id = ccb->pcmd->device->id;
876 lun = ccb->pcmd->device->lun;
cdd3cb15 877 if (!error) {
1a4f550a
NC		 878 if (acb->devstate[id][lun] == ARECA_RAID_GONE)
879 acb->devstate[id][lun] = ARECA_RAID_GOOD;
880 ccb->pcmd->result = DID_OK << 16;
ae52e7f0 881 arcmsr_ccb_complete(ccb);
cdd3cb15 882 }else{
1a4f550a
NC		 883 switch (ccb->arcmsr_cdb.DeviceStatus) {
884 case ARCMSR_DEV_SELECT_TIMEOUT: {
885 acb->devstate[id][lun] = ARECA_RAID_GONE;
886 ccb->pcmd->result = DID_NO_CONNECT << 16;
ae52e7f0 887 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 888 }
889 break;
890
891 case ARCMSR_DEV_ABORTED:
892
893 case ARCMSR_DEV_INIT_FAIL: {
894 acb->devstate[id][lun] = ARECA_RAID_GONE;
895 ccb->pcmd->result = DID_BAD_TARGET << 16;
ae52e7f0 896 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 897 }
898 break;
899
900 case ARCMSR_DEV_CHECK_CONDITION: {
901 acb->devstate[id][lun] = ARECA_RAID_GOOD;
902 arcmsr_report_sense_info(ccb);
ae52e7f0 903 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 904 }
905 break;
906
907 default:
cdd3cb15
NC		 908 printk(KERN_NOTICE
909 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
910 but got unknown DeviceStatus = 0x%x \n"
911 , acb->host->host_no
912 , id
913 , lun
914 , ccb->arcmsr_cdb.DeviceStatus);
915 acb->devstate[id][lun] = ARECA_RAID_GONE;
916 ccb->pcmd->result = DID_NO_CONNECT << 16;
917 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 918 break;
919 }
920 }
921}
922
cdd3cb15 923static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
1a4f550a
NC		 924
925{
ae52e7f0 926 int id, lun;
cdd3cb15
NC		 927 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
928 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
929 struct scsi_cmnd *abortcmd = pCCB->pcmd;
1a4f550a 930 if (abortcmd) {
ae52e7f0 931 id = abortcmd->device->id;
cdd3cb15 932 lun = abortcmd->device->lun;
1a4f550a 933 abortcmd->result |= DID_ABORT << 16;
cdd3cb15
NC		 934 arcmsr_ccb_complete(pCCB);
935 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
936 acb->host->host_no, pCCB);
1a4f550a 937 }
cdd3cb15 938 return;
1a4f550a
NC		 939 }
940 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
941 done acb = '0x%p'"
942 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
943 " ccboutstandingcount = %d \n"
944 , acb->host->host_no
945 , acb
cdd3cb15
NC		 946 , pCCB
947 , pCCB->acb
948 , pCCB->startdone
1a4f550a 949 , atomic_read(&acb->ccboutstandingcount));
cdd3cb15 950 return;
1a4f550a 951 }
cdd3cb15 952 arcmsr_report_ccb_state(acb, pCCB, error);
1a4f550a
NC		 953}
954
955static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
956{
957 int i = 0;
958 uint32_t flag_ccb;
cdd3cb15
NC		 959 struct ARCMSR_CDB *pARCMSR_CDB;
960 bool error;
961 struct CommandControlBlock *pCCB;
1a4f550a
NC		 962 switch (acb->adapter_type) {
963
964 case ACB_ADAPTER_TYPE_A: {
80da1adb 965 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 966 uint32_t outbound_intstatus;
80da1adb 967 outbound_intstatus = readl(&reg->outbound_intstatus) &
1a4f550a
NC		 968 acb->outbound_int_enable;
969 /*clear and abort all outbound posted Q*/
970 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
cdd3cb15 971 while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
1a4f550a 972 && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
cdd3cb15
NC		 973 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
974 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
975 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
976 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 977 }
978 }
979 break;
980
981 case ACB_ADAPTER_TYPE_B: {
80da1adb 982 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 983 /*clear all outbound posted Q*/
cdd3cb15 984 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, &reg->iop2drv_doorbell); /* clear doorbell interrupt */
1a4f550a
NC		 985 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
986 if ((flag_ccb = readl(&reg->done_qbuffer[i])) != 0) {
987 writel(0, &reg->done_qbuffer[i]);
cdd3cb15
NC		 988 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
989 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
990 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
991 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a 992 }
cdd3cb15 993 reg->post_qbuffer[i] = 0;
1a4f550a
NC		 994 }
995 reg->doneq_index = 0;
996 reg->postq_index = 0;
997 }
998 break;
cdd3cb15
NC		 999 case ACB_ADAPTER_TYPE_C: {
1000 struct MessageUnit_C *reg = acb->pmuC;
1001 struct ARCMSR_CDB *pARCMSR_CDB;
1002 uint32_t flag_ccb, ccb_cdb_phy;
1003 bool error;
1004 struct CommandControlBlock *pCCB;
1005 while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
1006 /*need to do*/
1007 flag_ccb = readl(&reg->outbound_queueport_low);
1008 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
1009 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/
1010 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1011 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
1012 arcmsr_drain_donequeue(acb, pCCB, error);
1013 }
1014 }
1a4f550a
NC		 1015 }
1016}
1c57e86d
EC		 1017static void arcmsr_remove(struct pci_dev *pdev)
1018{
1019 struct Scsi_Host *host = pci_get_drvdata(pdev);
1020 struct AdapterControlBlock *acb =
1021 (struct AdapterControlBlock *) host->hostdata;
1c57e86d 1022 int poll_count = 0;
1c57e86d
EC		 1023 arcmsr_free_sysfs_attr(acb);
1024 scsi_remove_host(host);
36b83ded
NC		 1025 flush_scheduled_work();
1026 del_timer_sync(&acb->eternal_timer);
1027 arcmsr_disable_outbound_ints(acb);
1c57e86d 1028 arcmsr_stop_adapter_bgrb(acb);
cdd3cb15 1029 arcmsr_flush_adapter_cache(acb);
1c57e86d
EC		 1030 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
1031 acb->acb_flags &= ~ACB_F_IOP_INITED;
1032
cdd3cb15 1033 for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++){
1c57e86d
EC		 1034 if (!atomic_read(&acb->ccboutstandingcount))
1035 break;
1a4f550a 1036 arcmsr_interrupt(acb);/* FIXME: need spinlock */
1c57e86d
EC		 1037 msleep(25);
1038 }
1039
1040 if (atomic_read(&acb->ccboutstandingcount)) {
1041 int i;
1042
1043 arcmsr_abort_allcmd(acb);
1a4f550a 1044 arcmsr_done4abort_postqueue(acb);
1c57e86d
EC		 1045 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
1046 struct CommandControlBlock *ccb = acb->pccb_pool[i];
1047 if (ccb->startdone == ARCMSR_CCB_START) {
1048 ccb->startdone = ARCMSR_CCB_ABORTED;
1049 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 1050 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 1051 }
1052 }
1053 }
1c57e86d 1054 free_irq(pdev->irq, acb);
1c57e86d 1055 arcmsr_free_ccb_pool(acb);
cdd3cb15
NC		 1056 arcmsr_free_hbb_mu(acb);
1057 arcmsr_unmap_pciregion(acb);
1c57e86d 1058 pci_release_regions(pdev);
cdd3cb15 1059 scsi_host_put(host);
1c57e86d
EC		 1060 pci_disable_device(pdev);
1061 pci_set_drvdata(pdev, NULL);
1062}
1063
1064static void arcmsr_shutdown(struct pci_dev *pdev)
1065{
1066 struct Scsi_Host *host = pci_get_drvdata(pdev);
1067 struct AdapterControlBlock *acb =
1068 (struct AdapterControlBlock *)host->hostdata;
36b83ded
NC		 1069 del_timer_sync(&acb->eternal_timer);
1070 arcmsr_disable_outbound_ints(acb);
1071 flush_scheduled_work();
1c57e86d
EC		 1072 arcmsr_stop_adapter_bgrb(acb);
1073 arcmsr_flush_adapter_cache(acb);
1074}
1075
1076static int arcmsr_module_init(void)
1077{
1078 int error = 0;
1c57e86d
EC		 1079 error = pci_register_driver(&arcmsr_pci_driver);
1080 return error;
1081}
1082
1083static void arcmsr_module_exit(void)
1084{
1085 pci_unregister_driver(&arcmsr_pci_driver);
1086}
1087module_init(arcmsr_module_init);
1088module_exit(arcmsr_module_exit);
1089
36b83ded 1090static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
1a4f550a 1091 u32 intmask_org)
1c57e86d 1092{
1c57e86d 1093 u32 mask;
1a4f550a 1094 switch (acb->adapter_type) {
1c57e86d 1095
cdd3cb15 1096 case ACB_ADAPTER_TYPE_A: {
80da1adb 1097 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 1098 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
36b83ded
NC		 1099 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
1100 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
1a4f550a
NC		 1101 writel(mask, &reg->outbound_intmask);
1102 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
1103 }
1104 break;
1c57e86d 1105
cdd3cb15 1106 case ACB_ADAPTER_TYPE_B: {
80da1adb 1107 struct MessageUnit_B *reg = acb->pmuB;
36b83ded
NC		 1108 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
1109 ARCMSR_IOP2DRV_DATA_READ_OK |
1110 ARCMSR_IOP2DRV_CDB_DONE |
1111 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
ae52e7f0 1112 writel(mask, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 1113 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
1114 }
cdd3cb15
NC		 1115 break;
1116 case ACB_ADAPTER_TYPE_C: {
1117 struct MessageUnit_C *reg = acb->pmuC;
1118 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
1119 writel(intmask_org & mask, &reg->host_int_mask);
1120 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
1121 }
1c57e86d
EC		 1122 }
1123}
1124
76d78300 1125static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
1a4f550a 1126 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
1c57e86d 1127{
1a4f550a
NC		 1128 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1129 int8_t *psge = (int8_t *)&arcmsr_cdb->u;
80da1adb 1130 __le32 address_lo, address_hi;
1a4f550a 1131 int arccdbsize = 0x30;
ae52e7f0 1132 __le32 length = 0;
cdd3cb15 1133 int i;
ae52e7f0 1134 struct scatterlist *sg;
1a4f550a 1135 int nseg;
1c57e86d 1136 ccb->pcmd = pcmd;
1a4f550a 1137 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1c57e86d
EC		 1138 arcmsr_cdb->TargetID = pcmd->device->id;
1139 arcmsr_cdb->LUN = pcmd->device->lun;
1140 arcmsr_cdb->Function = 1;
ae52e7f0 1141 arcmsr_cdb->Context = 0;
1c57e86d 1142 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
deff2627
FT		 1143
1144 nseg = scsi_dma_map(pcmd);
cdd3cb15 1145 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
76d78300 1146 return FAILED;
cdd3cb15
NC		 1147 scsi_for_each_sg(pcmd, sg, nseg, i) {
1148 /* Get the physical address of the current data pointer */
1149 length = cpu_to_le32(sg_dma_len(sg));
1150 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
1151 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
1152 if (address_hi == 0) {
1153 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1154
1155 pdma_sg->address = address_lo;
1156 pdma_sg->length = length;
1157 psge += sizeof (struct SG32ENTRY);
1158 arccdbsize += sizeof (struct SG32ENTRY);
1159 } else {
1160 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1c57e86d 1161
cdd3cb15
NC		 1162 pdma_sg->addresshigh = address_hi;
1163 pdma_sg->address = address_lo;
1164 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
1165 psge += sizeof (struct SG64ENTRY);
1166 arccdbsize += sizeof (struct SG64ENTRY);
1c57e86d 1167 }
cdd3cb15
NC		 1168 }
1169 arcmsr_cdb->sgcount = (uint8_t)nseg;
1170 arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
ae52e7f0 1171 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
cdd3cb15
NC		 1172 if ( arccdbsize > 256)
1173 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1174 if (pcmd->cmnd[0]|WRITE_6 || pcmd->cmnd[0]|WRITE_10 || pcmd->cmnd[0]|WRITE_12 ){
1c57e86d 1175 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1c57e86d 1176 }
cdd3cb15 1177 ccb->arc_cdb_size = arccdbsize;
76d78300 1178 return SUCCESS;
1c57e86d
EC		 1179}
1180
1181static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
1182{
cdd3cb15 1183 uint32_t cdb_phyaddr_pattern = ccb->cdb_phyaddr_pattern;
1c57e86d 1184 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1c57e86d
EC		 1185 atomic_inc(&acb->ccboutstandingcount);
1186 ccb->startdone = ARCMSR_CCB_START;
1a4f550a
NC		 1187 switch (acb->adapter_type) {
1188 case ACB_ADAPTER_TYPE_A: {
80da1adb 1189 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1190
1191 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
cdd3cb15 1192 writel(cdb_phyaddr_pattern | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
1c57e86d 1193 &reg->inbound_queueport);
1a4f550a 1194 else {
cdd3cb15 1195 writel(cdb_phyaddr_pattern, &reg->inbound_queueport);
1a4f550a
NC		 1196 }
1197 }
1198 break;
1c57e86d 1199
1a4f550a 1200 case ACB_ADAPTER_TYPE_B: {
80da1adb 1201 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1202 uint32_t ending_index, index = reg->postq_index;
1c57e86d 1203
1a4f550a
NC		 1204 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
1205 writel(0, &reg->post_qbuffer[ending_index]);
1206 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
cdd3cb15 1207 writel(cdb_phyaddr_pattern | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,\
1a4f550a 1208 &reg->post_qbuffer[index]);
cdd3cb15
NC		 1209 } else {
1210 writel(cdb_phyaddr_pattern, &reg->post_qbuffer[index]);
1a4f550a
NC		 1211 }
1212 index++;
1213 index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
1214 reg->postq_index = index;
ae52e7f0 1215 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
1c57e86d 1216 }
1a4f550a 1217 break;
cdd3cb15
NC		 1218 case ACB_ADAPTER_TYPE_C: {
1219 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)acb->pmuC;
1220 uint32_t ccb_post_stamp, arc_cdb_size;
1221
1222 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
1223 ccb_post_stamp = (cdb_phyaddr_pattern | ((arc_cdb_size - 1) >> 6) | 1);
1224 if (acb->cdb_phyaddr_hi32) {
1225 writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high);
1226 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1227 } else {
1228 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1229 }
1230 }
1c57e86d
EC		 1231 }
1232}
1233
1a4f550a 1234static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1c57e86d 1235{
80da1adb 1236 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d
EC		 1237 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1238 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
cdd3cb15 1239 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 1240 printk(KERN_NOTICE
1241 "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1242 , acb->host->host_no);
1243 }
1244}
1245
1246static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1247{
80da1adb 1248 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1249 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
ae52e7f0 1250 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
1a4f550a 1251
cdd3cb15 1252 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1c57e86d
EC		 1253 printk(KERN_NOTICE
1254 "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1255 , acb->host->host_no);
1a4f550a
NC		 1256 }
1257}
1258
cdd3cb15
NC		 1259static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *pACB)
1260{
1261 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
1262 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1263 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
1264 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
1265 if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
1266 printk(KERN_NOTICE
1267 "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1268 , pACB->host->host_no);
1269 }
1270 return;
1271}
1a4f550a
NC		 1272static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1273{
1274 switch (acb->adapter_type) {
1275 case ACB_ADAPTER_TYPE_A: {
1276 arcmsr_stop_hba_bgrb(acb);
1277 }
1278 break;
1279
1280 case ACB_ADAPTER_TYPE_B: {
1281 arcmsr_stop_hbb_bgrb(acb);
1282 }
1283 break;
cdd3cb15
NC		 1284 case ACB_ADAPTER_TYPE_C: {
1285 arcmsr_stop_hbc_bgrb(acb);
1286 }
1a4f550a 1287 }
1c57e86d
EC		 1288}
1289
1290static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
1291{
cdd3cb15 1292 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
1c57e86d
EC		 1293}
1294
1a4f550a 1295void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1c57e86d 1296{
1a4f550a
NC		 1297 switch (acb->adapter_type) {
1298 case ACB_ADAPTER_TYPE_A: {
80da1adb 1299 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1300 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
1301 }
1302 break;
1c57e86d 1303
1a4f550a 1304 case ACB_ADAPTER_TYPE_B: {
80da1adb 1305 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1306 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1c57e86d 1307 }
1a4f550a 1308 break;
cdd3cb15
NC		 1309 case ACB_ADAPTER_TYPE_C: {
1310 struct MessageUnit_C __iomem *reg = acb->pmuC;
1311 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
1312 }
1c57e86d 1313 }
1a4f550a
NC		 1314}
1315
1316static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1317{
1318 switch (acb->adapter_type) {
1319 case ACB_ADAPTER_TYPE_A: {
80da1adb 1320 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 1321 /*
1a4f550a
NC		 1322 ** push inbound doorbell tell iop, driver data write ok
1323 ** and wait reply on next hwinterrupt for next Qbuffer post
1c57e86d 1324 */
1a4f550a
NC		 1325 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
1326 }
1327 break;
1328
1329 case ACB_ADAPTER_TYPE_B: {
80da1adb 1330 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 1331 /*
1332 ** push inbound doorbell tell iop, driver data write ok
1333 ** and wait reply on next hwinterrupt for next Qbuffer post
1334 */
ae52e7f0 1335 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
1a4f550a
NC		 1336 }
1337 break;
cdd3cb15
NC		 1338 case ACB_ADAPTER_TYPE_C: {
1339 struct MessageUnit_C __iomem *reg = acb->pmuC;
1340 /*
1341 ** push inbound doorbell tell iop, driver data write ok
1342 ** and wait reply on next hwinterrupt for next Qbuffer post
1343 */
1344 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
1345 }
1346 break;
1a4f550a
NC		 1347 }
1348}
1349
80da1adb 1350struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
1a4f550a 1351{
0c7eb2eb 1352 struct QBUFFER __iomem *qbuffer = NULL;
1a4f550a
NC		 1353 switch (acb->adapter_type) {
1354
1355 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 1356 struct MessageUnit_A __iomem *reg = acb->pmuA;
1357 qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
1a4f550a
NC		 1358 }
1359 break;
1360
1361 case ACB_ADAPTER_TYPE_B: {
80da1adb 1362 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1363 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1a4f550a
NC		 1364 }
1365 break;
cdd3cb15
NC		 1366 case ACB_ADAPTER_TYPE_C: {
1367 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)acb->pmuC;
1368 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
1369 }
1a4f550a
NC		 1370 }
1371 return qbuffer;
1372}
1373
80da1adb 1374static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
1a4f550a 1375{
0c7eb2eb 1376 struct QBUFFER __iomem *pqbuffer = NULL;
1a4f550a
NC		 1377 switch (acb->adapter_type) {
1378
1379 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 1380 struct MessageUnit_A __iomem *reg = acb->pmuA;
1381 pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
1a4f550a
NC		 1382 }
1383 break;
1384
1385 case ACB_ADAPTER_TYPE_B: {
80da1adb 1386 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1387 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
1a4f550a
NC		 1388 }
1389 break;
cdd3cb15
NC		 1390 case ACB_ADAPTER_TYPE_C: {
1391 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
1392 pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
1393 }
1394
1a4f550a
NC		 1395 }
1396 return pqbuffer;
1397}
1398
1399static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1400{
80da1adb 1401 struct QBUFFER __iomem *prbuffer;
1a4f550a 1402 struct QBUFFER *pQbuffer;
80da1adb 1403 uint8_t __iomem *iop_data;
1a4f550a 1404 int32_t my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex;
1a4f550a
NC		 1405 rqbuf_lastindex = acb->rqbuf_lastindex;
1406 rqbuf_firstindex = acb->rqbuf_firstindex;
1407 prbuffer = arcmsr_get_iop_rqbuffer(acb);
80da1adb 1408 iop_data = (uint8_t __iomem *)prbuffer->data;
1a4f550a 1409 iop_len = prbuffer->data_len;
cdd3cb15 1410 my_empty_len = (rqbuf_firstindex - rqbuf_lastindex - 1) & (ARCMSR_MAX_QBUFFER - 1);
1a4f550a
NC		 1411
1412 if (my_empty_len >= iop_len)
1413 {
1414 while (iop_len > 0) {
1415 pQbuffer = (struct QBUFFER *)&acb->rqbuffer[rqbuf_lastindex];
cdd3cb15 1416 memcpy(pQbuffer, iop_data, 1);
1a4f550a
NC		 1417 rqbuf_lastindex++;
1418 rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1419 iop_data++;
1420 iop_len--;
1421 }
1422 acb->rqbuf_lastindex = rqbuf_lastindex;
1423 arcmsr_iop_message_read(acb);
1424 }
1425
1426 else {
1427 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1428 }
1429}
1430
1431static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1432{
1433 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
1434 if (acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1435 uint8_t *pQbuffer;
80da1adb
AV		 1436 struct QBUFFER __iomem *pwbuffer;
1437 uint8_t __iomem *iop_data;
1a4f550a
NC		 1438 int32_t allxfer_len = 0;
1439
1440 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1441 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1442 iop_data = (uint8_t __iomem *)pwbuffer->data;
1443
1444 while ((acb->wqbuf_firstindex != acb->wqbuf_lastindex) && \
1445 (allxfer_len < 124)) {
1446 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1447 memcpy(iop_data, pQbuffer, 1);
1448 acb->wqbuf_firstindex++;
1449 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1450 iop_data++;
1451 allxfer_len++;
1452 }
1453 pwbuffer->data_len = allxfer_len;
1454
1455 arcmsr_iop_message_wrote(acb);
1456 }
1457
1458 if (acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1459 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1460 }
1461}
1462
1463static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1464{
1465 uint32_t outbound_doorbell;
80da1adb 1466 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1467 outbound_doorbell = readl(&reg->outbound_doorbell);
1468 writel(outbound_doorbell, &reg->outbound_doorbell);
1469 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1470 arcmsr_iop2drv_data_wrote_handle(acb);
1471 }
1472
cdd3cb15 1473 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1a4f550a
NC		 1474 arcmsr_iop2drv_data_read_handle(acb);
1475 }
1476}
cdd3cb15
NC		 1477static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *pACB)
1478{
1479 uint32_t outbound_doorbell;
1480 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
1481 /*
1482 *******************************************************************
1483 ** Maybe here we need to check wrqbuffer_lock is lock or not
1484 ** DOORBELL: din! don!
1485 ** check if there are any mail need to pack from firmware
1486 *******************************************************************
1487 */
1488 outbound_doorbell = readl(&reg->outbound_doorbell);
1489 writel(outbound_doorbell, &reg->outbound_doorbell_clear);/*clear interrupt*/
1490 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1491 arcmsr_iop2drv_data_wrote_handle(pACB);
1492 }
1493 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1494 arcmsr_iop2drv_data_read_handle(pACB);
1495 }
1496 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1497 arcmsr_hbc_message_isr(pACB); /* messenger of "driver to iop commands" */
1498 }
1499 return;
1500}
1a4f550a
NC		 1501static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1502{
1503 uint32_t flag_ccb;
80da1adb 1504 struct MessageUnit_A __iomem *reg = acb->pmuA;
cdd3cb15
NC		 1505 struct ARCMSR_CDB *pARCMSR_CDB;
1506 struct CommandControlBlock *pCCB;
1507 bool error;
1a4f550a 1508 while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
cdd3cb15
NC		 1509 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
1510 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1511 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1512 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 1513 }
1514}
1515
1516static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
1517{
1518 uint32_t index;
1519 uint32_t flag_ccb;
80da1adb 1520 struct MessageUnit_B *reg = acb->pmuB;
cdd3cb15
NC		 1521 struct ARCMSR_CDB *pARCMSR_CDB;
1522 struct CommandControlBlock *pCCB;
1523 bool error;
1a4f550a 1524 index = reg->doneq_index;
1a4f550a
NC		 1525 while ((flag_ccb = readl(&reg->done_qbuffer[index])) != 0) {
1526 writel(0, &reg->done_qbuffer[index]);
cdd3cb15
NC		 1527 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
1528 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1529 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1530 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 1531 index++;
1532 index %= ARCMSR_MAX_HBB_POSTQUEUE;
1533 reg->doneq_index = index;
1534 }
1535}
cdd3cb15
NC		 1536
1537static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
1538{
1539 struct MessageUnit_C *phbcmu;
1540 struct ARCMSR_CDB *arcmsr_cdb;
1541 struct CommandControlBlock *ccb;
1542 uint32_t flag_ccb, ccb_cdb_phy, throttling = 0;
1543 int error;
1544
1545 phbcmu = (struct MessageUnit_C *)acb->pmuC;
1546 /* areca cdb command done */
1547 /* Use correct offset and size for syncing */
1548
1549 while (readl(&phbcmu->host_int_status) &
1550 ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR){
1551 /* check if command done with no error*/
1552 flag_ccb = readl(&phbcmu->outbound_queueport_low);
1553 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);/*frame must be 32 bytes aligned*/
1554 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
1555 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
1556 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
1557 /* check if command done with no error */
1558 arcmsr_drain_donequeue(acb, ccb, error);
1559 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1560 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING, &phbcmu->inbound_doorbell);
1561 break;
1562 }
1563 throttling++;
1564 }
1565}
36b83ded
NC		 1566/*
1567**********************************************************************************
1568** Handle a message interrupt
1569**
cdd3cb15 1570** The only message interrupt we expect is in response to a query for the current adapter config.
36b83ded
NC		 1571** We want this in order to compare the drivemap so that we can detect newly-attached drives.
1572**********************************************************************************
1573*/
1574static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb)
1575{
1576 struct MessageUnit_A *reg = acb->pmuA;
36b83ded
NC		 1577 /*clear interrupt and message state*/
1578 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
1579 schedule_work(&acb->arcmsr_do_message_isr_bh);
1580}
1581static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb)
1582{
1583 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1584
36b83ded 1585 /*clear interrupt and message state*/
ae52e7f0 1586 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
36b83ded
NC		 1587 schedule_work(&acb->arcmsr_do_message_isr_bh);
1588}
cdd3cb15
NC		 1589/*
1590**********************************************************************************
1591** Handle a message interrupt
1592**
1593** The only message interrupt we expect is in response to a query for the
1594** current adapter config.
1595** We want this in order to compare the drivemap so that we can detect newly-attached drives.
1596**********************************************************************************
1597*/
1598static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb)
1599{
1600 struct MessageUnit_C *reg = acb->pmuC;
1601 /*clear interrupt and message state*/
1602 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
1603 schedule_work(&acb->arcmsr_do_message_isr_bh);
1604}
1605
1a4f550a
NC		 1606static int arcmsr_handle_hba_isr(struct AdapterControlBlock *acb)
1607{
1608 uint32_t outbound_intstatus;
80da1adb 1609 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 1610 outbound_intstatus = readl(&reg->outbound_intstatus) &
cdd3cb15 1611 acb->outbound_int_enable;
1a4f550a
NC		 1612 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) {
1613 return 1;
1614 }
1615 writel(outbound_intstatus, &reg->outbound_intstatus);
1616 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
1617 arcmsr_hba_doorbell_isr(acb);
1618 }
1619 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
1620 arcmsr_hba_postqueue_isr(acb);
1621 }
cdd3cb15 1622 if(outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
36b83ded
NC		 1623 /* messenger of "driver to iop commands" */
1624 arcmsr_hba_message_isr(acb);
1625 }
1a4f550a
NC		 1626 return 0;
1627}
1628
1629static int arcmsr_handle_hbb_isr(struct AdapterControlBlock *acb)
1630{
1631 uint32_t outbound_doorbell;
80da1adb 1632 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1633 outbound_doorbell = readl(reg->iop2drv_doorbell) &
cdd3cb15 1634 acb->outbound_int_enable;
1a4f550a
NC		 1635 if (!outbound_doorbell)
1636 return 1;
1637
ae52e7f0 1638 writel(~outbound_doorbell, reg->iop2drv_doorbell);
36b83ded
NC		 1639 /*in case the last action of doorbell interrupt clearance is cached,
1640 this action can push HW to write down the clear bit*/
ae52e7f0
NC		 1641 readl(reg->iop2drv_doorbell);
1642 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
cdd3cb15 1643 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
1a4f550a
NC		 1644 arcmsr_iop2drv_data_wrote_handle(acb);
1645 }
1646 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
1647 arcmsr_iop2drv_data_read_handle(acb);
1648 }
1649 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
1650 arcmsr_hbb_postqueue_isr(acb);
1651 }
cdd3cb15 1652 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
36b83ded
NC		 1653 /* messenger of "driver to iop commands" */
1654 arcmsr_hbb_message_isr(acb);
1655 }
1a4f550a
NC		 1656 return 0;
1657}
1658
cdd3cb15
NC		 1659static int arcmsr_handle_hbc_isr(struct AdapterControlBlock *pACB)
1660{
1661 uint32_t host_interrupt_status;
1662 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
1663 /*
1664 *********************************************
1665 ** check outbound intstatus
1666 *********************************************
1667 */
1668 host_interrupt_status = readl(&phbcmu->host_int_status);
1669 if (!host_interrupt_status) {
1670 /*it must be share irq*/
1671 return 1;
1672 }
1673 /* MU ioctl transfer doorbell interrupts*/
1674 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
1675 arcmsr_hbc_doorbell_isr(pACB); /* messenger of "ioctl message read write" */
1676 }
1677 /* MU post queue interrupts*/
1678 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
1679 arcmsr_hbc_postqueue_isr(pACB); /* messenger of "scsi commands" */
1680 }
1681 return 0;
1682}
1a4f550a
NC		 1683static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
1684{
1685 switch (acb->adapter_type) {
1686 case ACB_ADAPTER_TYPE_A: {
1687 if (arcmsr_handle_hba_isr(acb)) {
1688 return IRQ_NONE;
1689 }
1690 }
1691 break;
1692
1693 case ACB_ADAPTER_TYPE_B: {
1694 if (arcmsr_handle_hbb_isr(acb)) {
1695 return IRQ_NONE;
1696 }
1697 }
1698 break;
cdd3cb15
NC		 1699 case ACB_ADAPTER_TYPE_C: {
1700 if (arcmsr_handle_hbc_isr(acb)) {
1701 return IRQ_NONE;
1702 }
1703 }
1c57e86d 1704 }
1c57e86d
EC		 1705 return IRQ_HANDLED;
1706}
1707
1708static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
1709{
1710 if (acb) {
1711 /* stop adapter background rebuild */
1712 if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
1a4f550a 1713 uint32_t intmask_org;
1c57e86d 1714 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1a4f550a 1715 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d
EC		 1716 arcmsr_stop_adapter_bgrb(acb);
1717 arcmsr_flush_adapter_cache(acb);
1a4f550a
NC		 1718 arcmsr_enable_outbound_ints(acb, intmask_org);
1719 }
1720 }
1721}
1722
1723void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb)
1724{
1725 int32_t wqbuf_firstindex, wqbuf_lastindex;
1726 uint8_t *pQbuffer;
80da1adb
AV		 1727 struct QBUFFER __iomem *pwbuffer;
1728 uint8_t __iomem *iop_data;
1a4f550a 1729 int32_t allxfer_len = 0;
1a4f550a
NC		 1730 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1731 iop_data = (uint8_t __iomem *)pwbuffer->data;
1732 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
1733 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1734 wqbuf_firstindex = acb->wqbuf_firstindex;
1735 wqbuf_lastindex = acb->wqbuf_lastindex;
1736 while ((wqbuf_firstindex != wqbuf_lastindex) && (allxfer_len < 124)) {
1737 pQbuffer = &acb->wqbuffer[wqbuf_firstindex];
1738 memcpy(iop_data, pQbuffer, 1);
1739 wqbuf_firstindex++;
1740 wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1741 iop_data++;
1742 allxfer_len++;
1c57e86d 1743 }
1a4f550a
NC		 1744 acb->wqbuf_firstindex = wqbuf_firstindex;
1745 pwbuffer->data_len = allxfer_len;
1746 arcmsr_iop_message_wrote(acb);
1c57e86d
EC		 1747 }
1748}
1749
36b83ded 1750static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
1a4f550a 1751 struct scsi_cmnd *cmd)
1c57e86d 1752{
1c57e86d
EC		 1753 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
1754 int retvalue = 0, transfer_len = 0;
1755 char *buffer;
deff2627 1756 struct scatterlist *sg;
1c57e86d
EC		 1757 uint32_t controlcode = (uint32_t ) cmd->cmnd[5] << 24 |
1758 (uint32_t ) cmd->cmnd[6] << 16 |
1759 (uint32_t ) cmd->cmnd[7] << 8 |
1760 (uint32_t ) cmd->cmnd[8];
1a4f550a 1761 /* 4 bytes: Areca io control code */
deff2627 1762 sg = scsi_sglist(cmd);
45711f1a 1763 buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
deff2627
FT		 1764 if (scsi_sg_count(cmd) > 1) {
1765 retvalue = ARCMSR_MESSAGE_FAIL;
1766 goto message_out;
1c57e86d 1767 }
deff2627
FT		 1768 transfer_len += sg->length;
1769
1c57e86d
EC		 1770 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
1771 retvalue = ARCMSR_MESSAGE_FAIL;
1772 goto message_out;
1773 }
1774 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
1775 switch(controlcode) {
1a4f550a 1776
1c57e86d 1777 case ARCMSR_MESSAGE_READ_RQBUFFER: {
69e562c2 1778 unsigned char *ver_addr;
1a4f550a
NC		 1779 uint8_t *pQbuffer, *ptmpQbuffer;
1780 int32_t allxfer_len = 0;
1781
69e562c2
DD		 1782 ver_addr = kmalloc(1032, GFP_ATOMIC);
1783 if (!ver_addr) {
1a4f550a
NC		 1784 retvalue = ARCMSR_MESSAGE_FAIL;
1785 goto message_out;
1786 }
cdd3cb15 1787
69e562c2 1788 ptmpQbuffer = ver_addr;
1a4f550a
NC		 1789 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
1790 && (allxfer_len < 1031)) {
1791 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
1792 memcpy(ptmpQbuffer, pQbuffer, 1);
1793 acb->rqbuf_firstindex++;
1794 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1795 ptmpQbuffer++;
1796 allxfer_len++;
1797 }
1798 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1c57e86d 1799
80da1adb
AV		 1800 struct QBUFFER __iomem *prbuffer;
1801 uint8_t __iomem *iop_data;
1a4f550a
NC		 1802 int32_t iop_len;
1803
1804 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1805 prbuffer = arcmsr_get_iop_rqbuffer(acb);
80da1adb 1806 iop_data = prbuffer->data;
1a4f550a
NC		 1807 iop_len = readl(&prbuffer->data_len);
1808 while (iop_len > 0) {
1809 acb->rqbuffer[acb->rqbuf_lastindex] = readb(iop_data);
1810 acb->rqbuf_lastindex++;
1811 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1812 iop_data++;
1813 iop_len--;
1c57e86d 1814 }
1a4f550a
NC		 1815 arcmsr_iop_message_read(acb);
1816 }
69e562c2 1817 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr, allxfer_len);
1a4f550a 1818 pcmdmessagefld->cmdmessage.Length = allxfer_len;
cdd3cb15 1819 if(acb->fw_flag == FW_DEADLOCK) {
ae52e7f0 1820 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15
NC		 1821 }else{
1822 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
ae52e7f0 1823 }
69e562c2 1824 kfree(ver_addr);
1c57e86d
EC		 1825 }
1826 break;
1c57e86d 1827
1a4f550a 1828 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
69e562c2 1829 unsigned char *ver_addr;
1a4f550a
NC		 1830 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
1831 uint8_t *pQbuffer, *ptmpuserbuffer;
1832
69e562c2
DD		 1833 ver_addr = kmalloc(1032, GFP_ATOMIC);
1834 if (!ver_addr) {
1a4f550a
NC		 1835 retvalue = ARCMSR_MESSAGE_FAIL;
1836 goto message_out;
1837 }
cdd3cb15
NC		 1838 if(acb->fw_flag == FW_DEADLOCK) {
1839 pcmdmessagefld->cmdmessage.ReturnCode =
36b83ded 1840 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15
NC		 1841 }else{
1842 pcmdmessagefld->cmdmessage.ReturnCode =
ae52e7f0 1843 ARCMSR_MESSAGE_RETURNCODE_OK;
36b83ded 1844 }
69e562c2 1845 ptmpuserbuffer = ver_addr;
1a4f550a
NC		 1846 user_len = pcmdmessagefld->cmdmessage.Length;
1847 memcpy(ptmpuserbuffer, pcmdmessagefld->messagedatabuffer, user_len);
1848 wqbuf_lastindex = acb->wqbuf_lastindex;
1849 wqbuf_firstindex = acb->wqbuf_firstindex;
1850 if (wqbuf_lastindex != wqbuf_firstindex) {
1851 struct SENSE_DATA *sensebuffer =
1852 (struct SENSE_DATA *)cmd->sense_buffer;
1853 arcmsr_post_ioctldata2iop(acb);
1854 /* has error report sensedata */
1855 sensebuffer->ErrorCode = 0x70;
1856 sensebuffer->SenseKey = ILLEGAL_REQUEST;
1857 sensebuffer->AdditionalSenseLength = 0x0A;
1858 sensebuffer->AdditionalSenseCode = 0x20;
1859 sensebuffer->Valid = 1;
1860 retvalue = ARCMSR_MESSAGE_FAIL;
1861 } else {
1862 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
1863 &(ARCMSR_MAX_QBUFFER - 1);
1864 if (my_empty_len >= user_len) {
1865 while (user_len > 0) {
1866 pQbuffer =
1867 &acb->wqbuffer[acb->wqbuf_lastindex];
1868 memcpy(pQbuffer, ptmpuserbuffer, 1);
1869 acb->wqbuf_lastindex++;
1870 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1871 ptmpuserbuffer++;
1872 user_len--;
1873 }
1874 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
1875 acb->acb_flags &=
1876 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
1877 arcmsr_post_ioctldata2iop(acb);
1878 }
1879 } else {
1880 /* has error report sensedata */
1c57e86d
EC		 1881 struct SENSE_DATA *sensebuffer =
1882 (struct SENSE_DATA *)cmd->sense_buffer;
1c57e86d
EC		 1883 sensebuffer->ErrorCode = 0x70;
1884 sensebuffer->SenseKey = ILLEGAL_REQUEST;
1885 sensebuffer->AdditionalSenseLength = 0x0A;
1886 sensebuffer->AdditionalSenseCode = 0x20;
1887 sensebuffer->Valid = 1;
1888 retvalue = ARCMSR_MESSAGE_FAIL;
1a4f550a 1889 }
1c57e86d 1890 }
69e562c2 1891 kfree(ver_addr);
1c57e86d
EC		 1892 }
1893 break;
1a4f550a 1894
1c57e86d 1895 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
1a4f550a 1896 uint8_t *pQbuffer = acb->rqbuffer;
1a4f550a
NC		 1897 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1898 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1899 arcmsr_iop_message_read(acb);
1900 }
1901 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
1902 acb->rqbuf_firstindex = 0;
1903 acb->rqbuf_lastindex = 0;
1904 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
cdd3cb15 1905 if(acb->fw_flag == FW_DEADLOCK) {
ae52e7f0
NC		 1906 pcmdmessagefld->cmdmessage.ReturnCode =
1907 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1908 }else{
ae52e7f0
NC		 1909 pcmdmessagefld->cmdmessage.ReturnCode =
1910 ARCMSR_MESSAGE_RETURNCODE_OK;
1911 }
1c57e86d
EC		 1912 }
1913 break;
1a4f550a 1914
1c57e86d 1915 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
1a4f550a 1916 uint8_t *pQbuffer = acb->wqbuffer;
cdd3cb15 1917 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1918 pcmdmessagefld->cmdmessage.ReturnCode =
1919 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1920 }else{
ae52e7f0
NC		 1921 pcmdmessagefld->cmdmessage.ReturnCode =
1922 ARCMSR_MESSAGE_RETURNCODE_OK;
36b83ded 1923 }
1c57e86d 1924
1a4f550a
NC		 1925 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1926 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1927 arcmsr_iop_message_read(acb);
1928 }
1929 acb->acb_flags |=
1930 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
1931 ACB_F_MESSAGE_WQBUFFER_READED);
1932 acb->wqbuf_firstindex = 0;
1933 acb->wqbuf_lastindex = 0;
1934 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
1c57e86d
EC		 1935 }
1936 break;
1a4f550a 1937
1c57e86d 1938 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
1a4f550a 1939 uint8_t *pQbuffer;
1c57e86d 1940
1a4f550a
NC		 1941 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1942 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1943 arcmsr_iop_message_read(acb);
1944 }
1945 acb->acb_flags |=
1946 (ACB_F_MESSAGE_WQBUFFER_CLEARED
1947 | ACB_F_MESSAGE_RQBUFFER_CLEARED
1948 | ACB_F_MESSAGE_WQBUFFER_READED);
1949 acb->rqbuf_firstindex = 0;
1950 acb->rqbuf_lastindex = 0;
1951 acb->wqbuf_firstindex = 0;
1952 acb->wqbuf_lastindex = 0;
1953 pQbuffer = acb->rqbuffer;
1954 memset(pQbuffer, 0, sizeof(struct QBUFFER));
1955 pQbuffer = acb->wqbuffer;
1956 memset(pQbuffer, 0, sizeof(struct QBUFFER));
cdd3cb15 1957 if(acb->fw_flag == FW_DEADLOCK) {
ae52e7f0
NC		 1958 pcmdmessagefld->cmdmessage.ReturnCode =
1959 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1960 }else{
ae52e7f0
NC		 1961 pcmdmessagefld->cmdmessage.ReturnCode =
1962 ARCMSR_MESSAGE_RETURNCODE_OK;
1963 }
1c57e86d
EC		 1964 }
1965 break;
1a4f550a 1966
1c57e86d 1967 case ARCMSR_MESSAGE_RETURN_CODE_3F: {
cdd3cb15 1968 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1969 pcmdmessagefld->cmdmessage.ReturnCode =
1970 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1971 }else{
ae52e7f0
NC		 1972 pcmdmessagefld->cmdmessage.ReturnCode =
1973 ARCMSR_MESSAGE_RETURNCODE_3F;
1c57e86d
EC		 1974 }
1975 break;
ae52e7f0 1976 }
1c57e86d 1977 case ARCMSR_MESSAGE_SAY_HELLO: {
1a4f550a 1978 int8_t *hello_string = "Hello! I am ARCMSR";
cdd3cb15 1979 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1980 pcmdmessagefld->cmdmessage.ReturnCode =
1981 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1982 }else{
ae52e7f0
NC		 1983 pcmdmessagefld->cmdmessage.ReturnCode =
1984 ARCMSR_MESSAGE_RETURNCODE_OK;
36b83ded 1985 }
1a4f550a
NC		 1986 memcpy(pcmdmessagefld->messagedatabuffer, hello_string
1987 , (int16_t)strlen(hello_string));
1c57e86d
EC		 1988 }
1989 break;
1a4f550a 1990
1c57e86d 1991 case ARCMSR_MESSAGE_SAY_GOODBYE:
cdd3cb15 1992 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1993 pcmdmessagefld->cmdmessage.ReturnCode =
1994 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
36b83ded 1995 }
1c57e86d
EC		 1996 arcmsr_iop_parking(acb);
1997 break;
1a4f550a 1998
1c57e86d 1999 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
cdd3cb15 2000 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 2001 pcmdmessagefld->cmdmessage.ReturnCode =
2002 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
36b83ded 2003 }
1c57e86d
EC		 2004 arcmsr_flush_adapter_cache(acb);
2005 break;
1a4f550a 2006
1c57e86d
EC		 2007 default:
2008 retvalue = ARCMSR_MESSAGE_FAIL;
2009 }
1a4f550a 2010 message_out:
deff2627
FT		 2011 sg = scsi_sglist(cmd);
2012 kunmap_atomic(buffer - sg->offset, KM_IRQ0);
1c57e86d
EC		 2013 return retvalue;
2014}
2015
2016static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
2017{
2018 struct list_head *head = &acb->ccb_free_list;
2019 struct CommandControlBlock *ccb = NULL;
ae52e7f0
NC		 2020 unsigned long flags;
2021 spin_lock_irqsave(&acb->ccblist_lock, flags);
1c57e86d
EC		 2022 if (!list_empty(head)) {
2023 ccb = list_entry(head->next, struct CommandControlBlock, list);
ae52e7f0 2024 list_del_init(&ccb->list);
cdd3cb15 2025 }else{
ae52e7f0
NC		 2026 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
2027 return 0;
1c57e86d 2028 }
ae52e7f0 2029 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 2030 return ccb;
2031}
2032
2033static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2034 struct scsi_cmnd *cmd)
2035{
2036 switch (cmd->cmnd[0]) {
2037 case INQUIRY: {
2038 unsigned char inqdata[36];
2039 char *buffer;
deff2627 2040 struct scatterlist *sg;
1c57e86d
EC		 2041
2042 if (cmd->device->lun) {
2043 cmd->result = (DID_TIME_OUT << 16);
2044 cmd->scsi_done(cmd);
2045 return;
2046 }
2047 inqdata[0] = TYPE_PROCESSOR;
2048 /* Periph Qualifier & Periph Dev Type */
2049 inqdata[1] = 0;
2050 /* rem media bit & Dev Type Modifier */
2051 inqdata[2] = 0;
a1f6e021 2052 /* ISO, ECMA, & ANSI versions */
1c57e86d
EC		 2053 inqdata[4] = 31;
2054 /* length of additional data */
2055 strncpy(&inqdata[8], "Areca ", 8);
2056 /* Vendor Identification */
2057 strncpy(&inqdata[16], "RAID controller ", 16);
2058 /* Product Identification */
2059 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
1c57e86d 2060
deff2627 2061 sg = scsi_sglist(cmd);
45711f1a 2062 buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
deff2627 2063
1c57e86d 2064 memcpy(buffer, inqdata, sizeof(inqdata));
deff2627
FT		 2065 sg = scsi_sglist(cmd);
2066 kunmap_atomic(buffer - sg->offset, KM_IRQ0);
1c57e86d 2067
1c57e86d
EC		 2068 cmd->scsi_done(cmd);
2069 }
2070 break;
2071 case WRITE_BUFFER:
2072 case READ_BUFFER: {
2073 if (arcmsr_iop_message_xfer(acb, cmd))
2074 cmd->result = (DID_ERROR << 16);
2075 cmd->scsi_done(cmd);
2076 }
2077 break;
2078 default:
2079 cmd->scsi_done(cmd);
2080 }
2081}
2082
2083static int arcmsr_queue_command(struct scsi_cmnd *cmd,
2084 void (* done)(struct scsi_cmnd *))
2085{
2086 struct Scsi_Host *host = cmd->device->host;
1a4f550a 2087 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
1c57e86d
EC		 2088 struct CommandControlBlock *ccb;
2089 int target = cmd->device->id;
2090 int lun = cmd->device->lun;
36b83ded 2091 uint8_t scsicmd = cmd->cmnd[0];
1c57e86d
EC		 2092 cmd->scsi_done = done;
2093 cmd->host_scribble = NULL;
2094 cmd->result = 0;
cdd3cb15
NC		 2095 if ((scsicmd == SYNCHRONIZE_CACHE) ||(scsicmd == SEND_DIAGNOSTIC)){
2096 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2097 cmd->result = (DID_NO_CONNECT << 16);
36b83ded
NC		 2098 }
2099 cmd->scsi_done(cmd);
2100 return 0;
2101 }
a1f6e021 2102 if (target == 16) {
1c57e86d
EC		 2103 /* virtual device for iop message transfer */
2104 arcmsr_handle_virtual_command(acb, cmd);
2105 return 0;
2106 }
1c57e86d
EC		 2107 if (atomic_read(&acb->ccboutstandingcount) >=
2108 ARCMSR_MAX_OUTSTANDING_CMD)
2109 return SCSI_MLQUEUE_HOST_BUSY;
cdd3cb15
NC		 2110 if ((scsicmd == SCSI_CMD_ARECA_SPECIFIC)) {
2111 printk(KERN_NOTICE "Receiveing SCSI_CMD_ARECA_SPECIFIC command..\n");
2112 return 0;
2113 }
1c57e86d
EC		 2114 ccb = arcmsr_get_freeccb(acb);
2115 if (!ccb)
2116 return SCSI_MLQUEUE_HOST_BUSY;
cdd3cb15 2117 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
76d78300
NC		 2118 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
2119 cmd->scsi_done(cmd);
2120 return 0;
2121 }
1c57e86d
EC		 2122 arcmsr_post_ccb(acb, ccb);
2123 return 0;
2124}
2125
ae52e7f0 2126static bool arcmsr_get_hba_config(struct AdapterControlBlock *acb)
1c57e86d 2127{
80da1adb 2128 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d
EC		 2129 char *acb_firm_model = acb->firm_model;
2130 char *acb_firm_version = acb->firm_version;
36b83ded 2131 char *acb_device_map = acb->device_map;
80da1adb
AV		 2132 char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
2133 char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
cdd3cb15 2134 char __iomem *iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]);
1c57e86d 2135 int count;
1c57e86d 2136 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
cdd3cb15 2137 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 2138 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2139 miscellaneous data' timeout \n", acb->host->host_no);
ae52e7f0 2140 return false;
1a4f550a 2141 }
1c57e86d 2142 count = 8;
cdd3cb15 2143 while (count){
1c57e86d
EC		 2144 *acb_firm_model = readb(iop_firm_model);
2145 acb_firm_model++;
2146 iop_firm_model++;
2147 count--;
2148 }
1a4f550a 2149
1c57e86d 2150 count = 16;
cdd3cb15 2151 while (count){
1c57e86d
EC		 2152 *acb_firm_version = readb(iop_firm_version);
2153 acb_firm_version++;
2154 iop_firm_version++;
2155 count--;
2156 }
1a4f550a 2157
cdd3cb15
NC		 2158 count=16;
2159 while(count){
2160 *acb_device_map = readb(iop_device_map);
2161 acb_device_map++;
2162 iop_device_map++;
2163 count--;
2164 }
2165 printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
ae52e7f0
NC		 2166 acb->host->host_no,
2167 acb->firm_version,
2168 acb->firm_model);
cdd3cb15 2169 acb->signature = readl(&reg->message_rwbuffer[0]);
1c57e86d
EC		 2170 acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
2171 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
2172 acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
2173 acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
ae52e7f0
NC		 2174 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2175 return true;
1c57e86d 2176}
ae52e7f0 2177static bool arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
1a4f550a 2178{
80da1adb 2179 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0
NC		 2180 struct pci_dev *pdev = acb->pdev;
2181 void *dma_coherent;
2182 dma_addr_t dma_coherent_handle;
1a4f550a
NC		 2183 char *acb_firm_model = acb->firm_model;
2184 char *acb_firm_version = acb->firm_version;
36b83ded 2185 char *acb_device_map = acb->device_map;
ae52e7f0 2186 char __iomem *iop_firm_model;
1a4f550a 2187 /*firm_model,15,60-67*/
ae52e7f0 2188 char __iomem *iop_firm_version;
1a4f550a 2189 /*firm_version,17,68-83*/
ae52e7f0 2190 char __iomem *iop_device_map;
36b83ded 2191 /*firm_version,21,84-99*/
1a4f550a 2192 int count;
ae52e7f0 2193 dma_coherent = dma_alloc_coherent(&pdev->dev, sizeof(struct MessageUnit_B), &dma_coherent_handle, GFP_KERNEL);
cdd3cb15 2194 if (!dma_coherent){
ae52e7f0
NC		 2195 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error for hbb mu\n", acb->host->host_no);
2196 return false;
2197 }
2198 acb->dma_coherent_handle_hbb_mu = dma_coherent_handle;
2199 reg = (struct MessageUnit_B *)dma_coherent;
2200 acb->pmuB = reg;
cdd3cb15 2201 reg->drv2iop_doorbell= (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL);
ae52e7f0
NC		 2202 reg->drv2iop_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL_MASK);
2203 reg->iop2drv_doorbell = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL);
2204 reg->iop2drv_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL_MASK);
2205 reg->message_wbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_WBUFFER);
2206 reg->message_rbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RBUFFER);
2207 reg->message_rwbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RWBUFFER);
2208 iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]); /*firm_model,15,60-67*/
2209 iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]); /*firm_version,17,68-83*/
2210 iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]); /*firm_version,21,84-99*/
2211
2212 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
cdd3cb15 2213 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2214 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2215 miscellaneous data' timeout \n", acb->host->host_no);
ae52e7f0 2216 return false;
1a4f550a 2217 }
1a4f550a 2218 count = 8;
cdd3cb15 2219 while (count){
1a4f550a
NC		 2220 *acb_firm_model = readb(iop_firm_model);
2221 acb_firm_model++;
2222 iop_firm_model++;
2223 count--;
2224 }
1a4f550a 2225 count = 16;
cdd3cb15 2226 while (count){
1a4f550a
NC		 2227 *acb_firm_version = readb(iop_firm_version);
2228 acb_firm_version++;
2229 iop_firm_version++;
2230 count--;
2231 }
2232
cdd3cb15
NC		 2233 count = 16;
2234 while(count){
2235 *acb_device_map = readb(iop_device_map);
2236 acb_device_map++;
2237 iop_device_map++;
2238 count--;
2239 }
2240
ae52e7f0 2241 printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
cdd3cb15 2242 acb->host->host_no,
ae52e7f0
NC		 2243 acb->firm_version,
2244 acb->firm_model);
1a4f550a 2245
ae52e7f0 2246 acb->signature = readl(&reg->message_rwbuffer[1]);
cdd3cb15 2247 /*firm_signature,1,00-03*/
ae52e7f0 2248 acb->firm_request_len = readl(&reg->message_rwbuffer[2]);
1a4f550a 2249 /*firm_request_len,1,04-07*/
ae52e7f0 2250 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[3]);
1a4f550a 2251 /*firm_numbers_queue,2,08-11*/
ae52e7f0 2252 acb->firm_sdram_size = readl(&reg->message_rwbuffer[4]);
1a4f550a 2253 /*firm_sdram_size,3,12-15*/
ae52e7f0 2254 acb->firm_hd_channels = readl(&reg->message_rwbuffer[5]);
1a4f550a 2255 /*firm_ide_channels,4,16-19*/
ae52e7f0
NC		 2256 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2257 /*firm_ide_channels,4,16-19*/
2258 return true;
1a4f550a 2259}
cdd3cb15
NC		 2260
2261static bool arcmsr_get_hbc_config(struct AdapterControlBlock *pACB)
2262{
2263 uint32_t intmask_org, Index, firmware_state = 0;
2264 struct MessageUnit_C *reg = pACB->pmuC;
2265 char *acb_firm_model = pACB->firm_model;
2266 char *acb_firm_version = pACB->firm_version;
2267 char *iop_firm_model = (char *)(&reg->msgcode_rwbuffer[15]); /*firm_model,15,60-67*/
2268 char *iop_firm_version = (char *)(&reg->msgcode_rwbuffer[17]); /*firm_version,17,68-83*/
2269 int count;
2270 /* disable all outbound interrupt */
2271 intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
2272 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
2273 /* wait firmware ready */
2274 do {
2275 firmware_state = readl(&reg->outbound_msgaddr1);
2276 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
2277 /* post "get config" instruction */
2278 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
2279 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2280 /* wait message ready */
2281 for (Index = 0; Index < 2000; Index++) {
2282 if (readl(&reg->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
2283 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);/*clear interrupt*/
2284 break;
2285 }
2286 udelay(10);
2287 } /*max 1 seconds*/
2288 if (Index >= 2000) {
2289 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2290 miscellaneous data' timeout \n", pACB->host->host_no);
2291 return false;
2292 }
2293 count = 8;
2294 while (count) {
2295 *acb_firm_model = readb(iop_firm_model);
2296 acb_firm_model++;
2297 iop_firm_model++;
2298 count--;
2299 }
2300 count = 16;
2301 while (count) {
2302 *acb_firm_version = readb(iop_firm_version);
2303 acb_firm_version++;
2304 iop_firm_version++;
2305 count--;
2306 }
2307 printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
2308 pACB->host->host_no,
2309 pACB->firm_version,
2310 pACB->firm_model);
2311 pACB->firm_request_len = readl(&reg->msgcode_rwbuffer[1]); /*firm_request_len,1,04-07*/
2312 pACB->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[2]); /*firm_numbers_queue,2,08-11*/
2313 pACB->firm_sdram_size = readl(&reg->msgcode_rwbuffer[3]); /*firm_sdram_size,3,12-15*/
2314 pACB->firm_hd_channels = readl(&reg->msgcode_rwbuffer[4]); /*firm_ide_channels,4,16-19*/
2315 pACB->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2316 /*all interrupt service will be enable at arcmsr_iop_init*/
2317 return true;
2318}
ae52e7f0 2319static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
1a4f550a 2320{
ae52e7f0
NC		 2321 if (acb->adapter_type == ACB_ADAPTER_TYPE_A)
2322 return arcmsr_get_hba_config(acb);
cdd3cb15 2323 else if (acb->adapter_type == ACB_ADAPTER_TYPE_B)
ae52e7f0 2324 return arcmsr_get_hbb_config(acb);
cdd3cb15
NC		 2325 else
2326 return arcmsr_get_hbc_config(acb);
1a4f550a
NC		 2327}
2328
ae52e7f0 2329static int arcmsr_polling_hba_ccbdone(struct AdapterControlBlock *acb,
1c57e86d
EC		 2330 struct CommandControlBlock *poll_ccb)
2331{
80da1adb 2332 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 2333 struct CommandControlBlock *ccb;
ae52e7f0 2334 struct ARCMSR_CDB *arcmsr_cdb;
1c57e86d 2335 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 2336 int rtn;
cdd3cb15 2337 bool error;
1a4f550a 2338 polling_hba_ccb_retry:
1c57e86d 2339 poll_count++;
1a4f550a 2340 outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
1c57e86d
EC		 2341 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
2342 while (1) {
2343 if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
cdd3cb15 2344 if (poll_ccb_done){
ae52e7f0 2345 rtn = SUCCESS;
1c57e86d 2346 break;
cdd3cb15
NC		 2347 }else {
2348 msleep(25);
2349 if (poll_count > 100){
ae52e7f0 2350 rtn = FAILED;
1c57e86d 2351 break;
ae52e7f0 2352 }
1a4f550a 2353 goto polling_hba_ccb_retry;
1c57e86d
EC		 2354 }
2355 }
ae52e7f0
NC		 2356 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
2357 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
1a4f550a
NC		 2358 poll_ccb_done = (ccb == poll_ccb) ? 1:0;
2359 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
2360 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
2361 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
1c57e86d
EC		 2362 " poll command abort successfully \n"
2363 , acb->host->host_no
2364 , ccb->pcmd->device->id
2365 , ccb->pcmd->device->lun
2366 , ccb);
2367 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 2368 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 2369 continue;
2370 }
1a4f550a
NC		 2371 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2372 " command done ccb = '0x%p'"
a1f6e021 2373 "ccboutstandingcount = %d \n"
1c57e86d
EC		 2374 , acb->host->host_no
2375 , ccb
2376 , atomic_read(&acb->ccboutstandingcount));
2377 continue;
cdd3cb15
NC		 2378 }
2379 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2380 arcmsr_report_ccb_state(acb, ccb, error);
1a4f550a 2381 }
ae52e7f0
NC		 2382 return rtn;
2383}
1a4f550a 2384
ae52e7f0 2385static int arcmsr_polling_hbb_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 2386 struct CommandControlBlock *poll_ccb)
2387{
cdd3cb15 2388 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2389 struct ARCMSR_CDB *arcmsr_cdb;
cdd3cb15
NC		 2390 struct CommandControlBlock *ccb;
2391 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 2392 int index, rtn;
cdd3cb15 2393 bool error;
1a4f550a 2394 polling_hbb_ccb_retry:
cdd3cb15
NC		 2395 poll_count++;
2396 /* clear doorbell interrupt */
ae52e7f0 2397 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
cdd3cb15
NC		 2398 while(1){
2399 index = reg->doneq_index;
2400 if ((flag_ccb = readl(&reg->done_qbuffer[index])) == 0) {
2401 if (poll_ccb_done){
ae52e7f0 2402 rtn = SUCCESS;
cdd3cb15
NC		 2403 break;
2404 }else {
2405 msleep(25);
2406 if (poll_count > 100){
ae52e7f0 2407 rtn = FAILED;
cdd3cb15 2408 break;
1c57e86d 2409 }
cdd3cb15 2410 goto polling_hbb_ccb_retry;
1a4f550a 2411 }
cdd3cb15
NC		 2412 }
2413 writel(0, &reg->done_qbuffer[index]);
2414 index++;
2415 /*if last index number set it to 0 */
2416 index %= ARCMSR_MAX_HBB_POSTQUEUE;
2417 reg->doneq_index = index;
2418 /* check if command done with no error*/
ae52e7f0
NC		 2419 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
2420 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
cdd3cb15
NC		 2421 poll_ccb_done = (ccb == poll_ccb) ? 1:0;
2422 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
2423 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
ae52e7f0
NC		 2424 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
2425 " poll command abort successfully \n"
cdd3cb15
NC		 2426 ,acb->host->host_no
2427 ,ccb->pcmd->device->id
2428 ,ccb->pcmd->device->lun
2429 ,ccb);
2430 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 2431 arcmsr_ccb_complete(ccb);
cdd3cb15
NC		 2432 continue;
2433 }
2434 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2435 " command done ccb = '0x%p'"
2436 "ccboutstandingcount = %d \n"
2437 , acb->host->host_no
2438 , ccb
2439 , atomic_read(&acb->ccboutstandingcount));
2440 continue;
2441 }
2442 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2443 arcmsr_report_ccb_state(acb, ccb, error);
2444 }
2445 return rtn;
2446}
2447
2448static int arcmsr_polling_hbc_ccbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_ccb)
2449{
2450 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2451 uint32_t flag_ccb, ccb_cdb_phy;
2452 struct ARCMSR_CDB *arcmsr_cdb;
2453 bool error;
2454 struct CommandControlBlock *pCCB;
2455 uint32_t poll_ccb_done = 0, poll_count = 0;
2456 int rtn;
2457polling_hbc_ccb_retry:
2458 poll_count++;
2459 while (1) {
2460 if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
2461 if (poll_ccb_done) {
2462 rtn = SUCCESS;
2463 break;
2464 } else {
2465 msleep(25);
2466 if (poll_count > 100) {
2467 rtn = FAILED;
2468 break;
1c57e86d 2469 }
cdd3cb15
NC		 2470 goto polling_hbc_ccb_retry;
2471 }
2472 }
2473 flag_ccb = readl(&reg->outbound_queueport_low);
2474 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
2475 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/
2476 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
2477 poll_ccb_done = (pCCB == poll_ccb) ? 1 : 0;
2478 /* check ifcommand done with no error*/
2479 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
2480 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
2481 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
2482 " poll command abort successfully \n"
1c57e86d 2483 , acb->host->host_no
cdd3cb15
NC		 2484 , pCCB->pcmd->device->id
2485 , pCCB->pcmd->device->lun
2486 , pCCB);
2487 pCCB->pcmd->result = DID_ABORT << 16;
2488 arcmsr_ccb_complete(pCCB);
1a4f550a 2489 continue;
cdd3cb15
NC		 2490 }
2491 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2492 " command done ccb = '0x%p'"
2493 "ccboutstandingcount = %d \n"
2494 , acb->host->host_no
2495 , pCCB
2496 , atomic_read(&acb->ccboutstandingcount));
2497 continue;
ae52e7f0 2498 }
cdd3cb15
NC		 2499 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
2500 arcmsr_report_ccb_state(acb, pCCB, error);
2501 }
ae52e7f0 2502 return rtn;
1a4f550a 2503}
ae52e7f0 2504static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 2505 struct CommandControlBlock *poll_ccb)
2506{
ae52e7f0 2507 int rtn = 0;
1a4f550a
NC		 2508 switch (acb->adapter_type) {
2509
2510 case ACB_ADAPTER_TYPE_A: {
ae52e7f0 2511 rtn = arcmsr_polling_hba_ccbdone(acb, poll_ccb);
1a4f550a
NC		 2512 }
2513 break;
2514
2515 case ACB_ADAPTER_TYPE_B: {
ae52e7f0 2516 rtn = arcmsr_polling_hbb_ccbdone(acb, poll_ccb);
1c57e86d 2517 }
cdd3cb15
NC		 2518 break;
2519 case ACB_ADAPTER_TYPE_C: {
2520 rtn = arcmsr_polling_hbc_ccbdone(acb, poll_ccb);
2521 }
1c57e86d 2522 }
ae52e7f0 2523 return rtn;
1c57e86d 2524}
1a4f550a
NC		 2525
2526static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
a1f6e021 2527{
ae52e7f0 2528 uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
1a4f550a
NC		 2529 dma_addr_t dma_coherent_handle;
2530 /*
2531 ********************************************************************
2532 ** here we need to tell iop 331 our freeccb.HighPart
2533 ** if freeccb.HighPart is not zero
2534 ********************************************************************
2535 */
2536 dma_coherent_handle = acb->dma_coherent_handle;
2537 cdb_phyaddr = (uint32_t)(dma_coherent_handle);
ae52e7f0 2538 cdb_phyaddr_hi32 = (uint32_t)((cdb_phyaddr >> 16) >> 16);
cdd3cb15 2539 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
1a4f550a
NC		 2540 /*
2541 ***********************************************************************
2542 ** if adapter type B, set window of "post command Q"
2543 ***********************************************************************
2544 */
2545 switch (acb->adapter_type) {
2546
2547 case ACB_ADAPTER_TYPE_A: {
ae52e7f0 2548 if (cdb_phyaddr_hi32 != 0) {
80da1adb 2549 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2550 uint32_t intmask_org;
2551 intmask_org = arcmsr_disable_outbound_ints(acb);
2552 writel(ARCMSR_SIGNATURE_SET_CONFIG, \
2553 &reg->message_rwbuffer[0]);
ae52e7f0 2554 writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
1a4f550a
NC		 2555 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
2556 &reg->inbound_msgaddr0);
cdd3cb15 2557 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 2558 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
2559 part physical address timeout\n",
2560 acb->host->host_no);
2561 return 1;
a1f6e021 2562 }
1a4f550a
NC		 2563 arcmsr_enable_outbound_ints(acb, intmask_org);
2564 }
2565 }
2566 break;
a1f6e021 2567
1a4f550a
NC		 2568 case ACB_ADAPTER_TYPE_B: {
2569 unsigned long post_queue_phyaddr;
80da1adb 2570 uint32_t __iomem *rwbuffer;
a1f6e021 2571
80da1adb 2572 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 2573 uint32_t intmask_org;
2574 intmask_org = arcmsr_disable_outbound_ints(acb);
2575 reg->postq_index = 0;
2576 reg->doneq_index = 0;
ae52e7f0 2577 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
cdd3cb15 2578 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2579 printk(KERN_NOTICE "arcmsr%d:can not set diver mode\n", \
2580 acb->host->host_no);
2581 return 1;
2582 }
ae52e7f0
NC		 2583 post_queue_phyaddr = acb->dma_coherent_handle_hbb_mu;
2584 rwbuffer = reg->message_rwbuffer;
1a4f550a
NC		 2585 /* driver "set config" signature */
2586 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
2587 /* normal should be zero */
ae52e7f0 2588 writel(cdb_phyaddr_hi32, rwbuffer++);
1a4f550a
NC		 2589 /* postQ size (256 + 8)*4 */
2590 writel(post_queue_phyaddr, rwbuffer++);
2591 /* doneQ size (256 + 8)*4 */
2592 writel(post_queue_phyaddr + 1056, rwbuffer++);
2593 /* ccb maxQ size must be --> [(256 + 8)*4]*/
2594 writel(1056, rwbuffer);
2595
ae52e7f0 2596 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
cdd3cb15 2597 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2598 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
2599 timeout \n",acb->host->host_no);
2600 return 1;
2601 }
ae52e7f0 2602 arcmsr_hbb_enable_driver_mode(acb);
1a4f550a
NC		 2603 arcmsr_enable_outbound_ints(acb, intmask_org);
2604 }
2605 break;
cdd3cb15
NC		 2606 case ACB_ADAPTER_TYPE_C: {
2607 if (cdb_phyaddr_hi32 != 0) {
2608 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2609
2610 if (cdb_phyaddr_hi32 != 0) {
2611 unsigned char Retries = 0x00;
2612 do {
2613 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x \n", acb->adapter_index, cdb_phyaddr_hi32);
2614 } while (Retries++ < 100);
2615 }
2616 writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
2617 writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
2618 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
2619 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2620 if (!arcmsr_hbc_wait_msgint_ready(acb)) {
2621 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
2622 timeout \n", acb->host->host_no);
2623 return 1;
2624 }
2625 }
2626 }
1a4f550a
NC		 2627 }
2628 return 0;
2629}
a1f6e021 2630
1a4f550a
NC		 2631static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
2632{
2633 uint32_t firmware_state = 0;
1a4f550a
NC		 2634 switch (acb->adapter_type) {
2635
2636 case ACB_ADAPTER_TYPE_A: {
80da1adb 2637 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2638 do {
2639 firmware_state = readl(&reg->outbound_msgaddr1);
2640 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
2641 }
2642 break;
2643
2644 case ACB_ADAPTER_TYPE_B: {
80da1adb 2645 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2646 do {
ae52e7f0 2647 firmware_state = readl(reg->iop2drv_doorbell);
1a4f550a 2648 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
ae52e7f0 2649 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
1a4f550a
NC		 2650 }
2651 break;
cdd3cb15
NC		 2652 case ACB_ADAPTER_TYPE_C: {
2653 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2654 do {
2655 firmware_state = readl(&reg->outbound_msgaddr1);
2656 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
2657 }
a1f6e021 2658 }
1a4f550a
NC		 2659}
2660
36b83ded
NC		 2661static void arcmsr_request_hba_device_map(struct AdapterControlBlock *acb)
2662{
2663 struct MessageUnit_A __iomem *reg = acb->pmuA;
cdd3cb15 2664 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
ae52e7f0 2665 return;
36b83ded 2666 } else {
ae52e7f0 2667 acb->fw_flag = FW_NORMAL;
cdd3cb15 2668 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)){
36b83ded
NC		 2669 atomic_set(&acb->rq_map_token, 16);
2670 }
ae52e7f0
NC		 2671 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
2672 if (atomic_dec_and_test(&acb->rq_map_token))
2673 return;
36b83ded 2674 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
cdd3cb15 2675 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
36b83ded 2676 }
36b83ded
NC		 2677 return;
2678}
2679
2680static void arcmsr_request_hbb_device_map(struct AdapterControlBlock *acb)
2681{
2682 struct MessageUnit_B __iomem *reg = acb->pmuB;
cdd3cb15
NC		 2683 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
2684 return;
2685 } else {
2686 acb->fw_flag = FW_NORMAL;
2687 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
2688 atomic_set(&acb->rq_map_token,16);
2689 }
2690 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
2691 if(atomic_dec_and_test(&acb->rq_map_token))
2692 return;
2693 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
2694 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
2695 }
2696 return;
2697}
36b83ded 2698
cdd3cb15
NC		 2699static void arcmsr_request_hbc_device_map(struct AdapterControlBlock *acb)
2700{
2701 struct MessageUnit_C __iomem *reg = acb->pmuC;
ae52e7f0
NC		 2702 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0) || ((acb->acb_flags & ACB_F_ABORT) != 0)) {
2703 return;
36b83ded 2704 } else {
ae52e7f0
NC		 2705 acb->fw_flag = FW_NORMAL;
2706 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
36b83ded
NC		 2707 atomic_set(&acb->rq_map_token, 16);
2708 }
ae52e7f0
NC		 2709 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
2710 if (atomic_dec_and_test(&acb->rq_map_token))
2711 return;
cdd3cb15
NC		 2712 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
2713 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2714 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
36b83ded 2715 }
36b83ded
NC		 2716 return;
2717}
2718
2719static void arcmsr_request_device_map(unsigned long pacb)
2720{
2721 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)pacb;
36b83ded
NC		 2722 switch (acb->adapter_type) {
2723 case ACB_ADAPTER_TYPE_A: {
2724 arcmsr_request_hba_device_map(acb);
2725 }
2726 break;
2727 case ACB_ADAPTER_TYPE_B: {
2728 arcmsr_request_hbb_device_map(acb);
2729 }
2730 break;
cdd3cb15
NC		 2731 case ACB_ADAPTER_TYPE_C: {
2732 arcmsr_request_hbc_device_map(acb);
2733 }
36b83ded
NC		 2734 }
2735}
2736
1a4f550a
NC		 2737static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
2738{
80da1adb 2739 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2740 acb->acb_flags |= ACB_F_MSG_START_BGRB;
2741 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
cdd3cb15 2742 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 2743 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
2744 rebulid' timeout \n", acb->host->host_no);
a1f6e021 2745 }
a1f6e021 2746}
2747
1a4f550a
NC		 2748static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
2749{
80da1adb 2750 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2751 acb->acb_flags |= ACB_F_MSG_START_BGRB;
ae52e7f0 2752 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
cdd3cb15 2753 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2754 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
2755 rebulid' timeout \n",acb->host->host_no);
2756 }
2757}
1c57e86d 2758
cdd3cb15
NC		 2759static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *pACB)
2760{
2761 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
2762 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
2763 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
2764 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
2765 if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
2766 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
2767 rebulid' timeout \n", pACB->host->host_no);
2768 }
2769 return;
2770}
1a4f550a 2771static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
1c57e86d 2772{
1a4f550a
NC		 2773 switch (acb->adapter_type) {
2774 case ACB_ADAPTER_TYPE_A:
2775 arcmsr_start_hba_bgrb(acb);
2776 break;
2777 case ACB_ADAPTER_TYPE_B:
2778 arcmsr_start_hbb_bgrb(acb);
2779 break;
cdd3cb15
NC		 2780 case ACB_ADAPTER_TYPE_C:
2781 arcmsr_start_hbc_bgrb(acb);
1a4f550a
NC		 2782 }
2783}
1c57e86d 2784
1a4f550a
NC		 2785static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
2786{
2787 switch (acb->adapter_type) {
2788 case ACB_ADAPTER_TYPE_A: {
80da1adb 2789 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2790 uint32_t outbound_doorbell;
2791 /* empty doorbell Qbuffer if door bell ringed */
2792 outbound_doorbell = readl(&reg->outbound_doorbell);
2793 /*clear doorbell interrupt */
2794 writel(outbound_doorbell, &reg->outbound_doorbell);
2795 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
2796 }
2797 break;
1c57e86d 2798
1a4f550a 2799 case ACB_ADAPTER_TYPE_B: {
80da1adb 2800 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2801 /*clear interrupt and message state*/
ae52e7f0
NC		 2802 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
2803 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1a4f550a
NC		 2804 /* let IOP know data has been read */
2805 }
2806 break;
cdd3cb15
NC		 2807 case ACB_ADAPTER_TYPE_C: {
2808 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2809 uint32_t outbound_doorbell;
2810 /* empty doorbell Qbuffer if door bell ringed */
2811 outbound_doorbell = readl(&reg->outbound_doorbell);
2812 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
2813 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
2814 }
1c57e86d 2815 }
1a4f550a 2816}
1c57e86d 2817
76d78300
NC		 2818static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
2819{
2820 switch (acb->adapter_type) {
2821 case ACB_ADAPTER_TYPE_A:
2822 return;
2823 case ACB_ADAPTER_TYPE_B:
2824 {
2825 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2826 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
cdd3cb15 2827 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
76d78300
NC		 2828 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
2829 return;
2830 }
2831 }
2832 break;
cdd3cb15
NC		 2833 case ACB_ADAPTER_TYPE_C:
2834 return;
76d78300
NC		 2835 }
2836 return;
2837}
2838
36b83ded
NC		 2839static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
2840{
2841 uint8_t value[64];
cdd3cb15
NC		 2842 int i, count = 0;
2843 struct MessageUnit_A __iomem *pmuA = acb->pmuA;
2844 struct MessageUnit_C __iomem *pmuC = acb->pmuC;
2845 u32 temp = 0;
36b83ded 2846 /* backup pci config data */
cdd3cb15 2847 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
36b83ded
NC		 2848 for (i = 0; i < 64; i++) {
2849 pci_read_config_byte(acb->pdev, i, &value[i]);
2850 }
2851 /* hardware reset signal */
ae52e7f0 2852 if ((acb->dev_id == 0x1680)) {
cdd3cb15
NC		 2853 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
2854 } else if ((acb->dev_id == 0x1880)) {
2855 do {
2856 count++;
2857 writel(0xF, &pmuC->write_sequence);
2858 writel(0x4, &pmuC->write_sequence);
2859 writel(0xB, &pmuC->write_sequence);
2860 writel(0x2, &pmuC->write_sequence);
2861 writel(0x7, &pmuC->write_sequence);
2862 writel(0xD, &pmuC->write_sequence);
2863 } while ((((temp = readl(&pmuC->host_diagnostic)) | ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
2864 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
ae52e7f0 2865 } else {
cdd3cb15 2866 pci_write_config_byte(acb->pdev, 0x84, 0x20);
ae52e7f0 2867 }
cdd3cb15 2868 msleep(2000);
36b83ded
NC		 2869 /* write back pci config data */
2870 for (i = 0; i < 64; i++) {
2871 pci_write_config_byte(acb->pdev, i, value[i]);
2872 }
2873 msleep(1000);
2874 return;
2875}
1a4f550a
NC		 2876static void arcmsr_iop_init(struct AdapterControlBlock *acb)
2877{
2878 uint32_t intmask_org;
cdd3cb15
NC		 2879 /* disable all outbound interrupt */
2880 intmask_org = arcmsr_disable_outbound_ints(acb);
76d78300
NC		 2881 arcmsr_wait_firmware_ready(acb);
2882 arcmsr_iop_confirm(acb);
1a4f550a
NC		 2883 /*start background rebuild*/
2884 arcmsr_start_adapter_bgrb(acb);
2885 /* empty doorbell Qbuffer if door bell ringed */
2886 arcmsr_clear_doorbell_queue_buffer(acb);
76d78300 2887 arcmsr_enable_eoi_mode(acb);
1a4f550a
NC		 2888 /* enable outbound Post Queue,outbound doorbell Interrupt */
2889 arcmsr_enable_outbound_ints(acb, intmask_org);
1c57e86d
EC		 2890 acb->acb_flags |= ACB_F_IOP_INITED;
2891}
2892
36b83ded 2893static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
1c57e86d 2894{
1c57e86d
EC		 2895 struct CommandControlBlock *ccb;
2896 uint32_t intmask_org;
36b83ded 2897 uint8_t rtnval = 0x00;
1c57e86d 2898 int i = 0;
1c57e86d 2899 if (atomic_read(&acb->ccboutstandingcount) != 0) {
36b83ded
NC		 2900 /* disable all outbound interrupt */
2901 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d 2902 /* talk to iop 331 outstanding command aborted */
36b83ded 2903 rtnval = arcmsr_abort_allcmd(acb);
1c57e86d 2904 /* clear all outbound posted Q */
1a4f550a 2905 arcmsr_done4abort_postqueue(acb);
1c57e86d
EC		 2906 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
2907 ccb = acb->pccb_pool[i];
a1f6e021 2908 if (ccb->startdone == ARCMSR_CCB_START) {
ae52e7f0 2909 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 2910 }
2911 }
36b83ded 2912 atomic_set(&acb->ccboutstandingcount, 0);
1c57e86d
EC		 2913 /* enable all outbound interrupt */
2914 arcmsr_enable_outbound_ints(acb, intmask_org);
36b83ded 2915 return rtnval;
1c57e86d 2916 }
36b83ded 2917 return rtnval;
1c57e86d
EC		 2918}
2919
2920static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
2921{
2922 struct AdapterControlBlock *acb =
2923 (struct AdapterControlBlock *)cmd->device->host->hostdata;
ae52e7f0
NC		 2924 uint32_t intmask_org, outbound_doorbell;
2925 int retry_count = 0;
2926 int rtn = FAILED;
ae52e7f0 2927 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
cdd3cb15 2928 printk(KERN_ERR "arcmsr: executing bus reset eh.....num_resets = %d, num_aborts = %d \n", acb->num_resets, acb->num_aborts);
36b83ded 2929 acb->num_resets++;
36b83ded 2930
cdd3cb15
NC		 2931 switch(acb->adapter_type){
2932 case ACB_ADAPTER_TYPE_A:{
2933 if (acb->acb_flags & ACB_F_BUS_RESET){
ae52e7f0 2934 long timeout;
cdd3cb15
NC		 2935 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
2936 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
ae52e7f0
NC		 2937 if (timeout) {
2938 return SUCCESS;
2939 }
2940 }
2941 acb->acb_flags |= ACB_F_BUS_RESET;
cdd3cb15 2942 if (!arcmsr_iop_reset(acb)) {
ae52e7f0
NC		 2943 struct MessageUnit_A __iomem *reg;
2944 reg = acb->pmuA;
cdd3cb15
NC		 2945 arcmsr_hardware_reset(acb);
2946 acb->acb_flags &= ~ACB_F_IOP_INITED;
36b83ded 2947sleep_again:
cdd3cb15 2948 arcmsr_sleep_for_bus_reset(cmd);
ae52e7f0 2949 if ((readl(&reg->outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) {
cdd3cb15
NC		 2950 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d \n", acb->host->host_no, retry_count);
2951 if (retry_count > retrycount) {
ae52e7f0 2952 acb->fw_flag = FW_DEADLOCK;
cdd3cb15 2953 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!! \n", acb->host->host_no);
ae52e7f0 2954 return FAILED;
cdd3cb15
NC		 2955 }
2956 retry_count++;
2957 goto sleep_again;
2958 }
2959 acb->acb_flags |= ACB_F_IOP_INITED;
2960 /* disable all outbound interrupt */
2961 intmask_org = arcmsr_disable_outbound_ints(acb);
ae52e7f0 2962 arcmsr_get_firmware_spec(acb);
cdd3cb15
NC		 2963 arcmsr_start_adapter_bgrb(acb);
2964 /* clear Qbuffer if door bell ringed */
2965 outbound_doorbell = readl(&reg->outbound_doorbell);
2966 writel(outbound_doorbell, &reg->outbound_doorbell); /*clear interrupt */
2967 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
2968 /* enable outbound Post Queue,outbound doorbell Interrupt */
2969 arcmsr_enable_outbound_ints(acb, intmask_org);
2970 atomic_set(&acb->rq_map_token, 16);
ae52e7f0
NC		 2971 atomic_set(&acb->ante_token_value, 16);
2972 acb->fw_flag = FW_NORMAL;
2973 init_timer(&acb->eternal_timer);
2974 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6*HZ);
2975 acb->eternal_timer.data = (unsigned long) acb;
2976 acb->eternal_timer.function = &arcmsr_request_device_map;
2977 add_timer(&acb->eternal_timer);
2978 acb->acb_flags &= ~ACB_F_BUS_RESET;
2979 rtn = SUCCESS;
cdd3cb15 2980 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
ae52e7f0
NC		 2981 } else {
2982 acb->acb_flags &= ~ACB_F_BUS_RESET;
2983 if (atomic_read(&acb->rq_map_token) == 0) {
2984 atomic_set(&acb->rq_map_token, 16);
2985 atomic_set(&acb->ante_token_value, 16);
2986 acb->fw_flag = FW_NORMAL;
cdd3cb15 2987 init_timer(&acb->eternal_timer);
ae52e7f0 2988 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6*HZ);
cdd3cb15
NC		 2989 acb->eternal_timer.data = (unsigned long) acb;
2990 acb->eternal_timer.function = &arcmsr_request_device_map;
2991 add_timer(&acb->eternal_timer);
ae52e7f0
NC		 2992 } else {
2993 atomic_set(&acb->rq_map_token, 16);
2994 atomic_set(&acb->ante_token_value, 16);
2995 acb->fw_flag = FW_NORMAL;
2996 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
cdd3cb15 2997 }
ae52e7f0 2998 rtn = SUCCESS;
cdd3cb15 2999 }
ae52e7f0 3000 break;
36b83ded 3001 }
ae52e7f0
NC		 3002 case ACB_ADAPTER_TYPE_B:{
3003 acb->acb_flags |= ACB_F_BUS_RESET;
cdd3cb15 3004 if (!arcmsr_iop_reset(acb)) {
ae52e7f0
NC		 3005 acb->acb_flags &= ~ACB_F_BUS_RESET;
3006 rtn = FAILED;
cdd3cb15
NC		 3007 } else {
3008 acb->acb_flags &= ~ACB_F_BUS_RESET;
ae52e7f0
NC		 3009 if (atomic_read(&acb->rq_map_token) == 0) {
3010 atomic_set(&acb->rq_map_token, 16);
3011 atomic_set(&acb->ante_token_value, 16);
3012 acb->fw_flag = FW_NORMAL;
3013 init_timer(&acb->eternal_timer);
3014 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6*HZ);
3015 acb->eternal_timer.data = (unsigned long) acb;
3016 acb->eternal_timer.function = &arcmsr_request_device_map;
3017 add_timer(&acb->eternal_timer);
3018 } else {
3019 atomic_set(&acb->rq_map_token, 16);
3020 atomic_set(&acb->ante_token_value, 16);
3021 acb->fw_flag = FW_NORMAL;
3022 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
3023 }
3024 rtn = SUCCESS;
cdd3cb15
NC		 3025 }
3026 break;
3027 }
3028 case ACB_ADAPTER_TYPE_C:{
3029 if (acb->acb_flags & ACB_F_BUS_RESET) {
3030 long timeout;
3031 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
3032 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
3033 if (timeout) {
3034 return SUCCESS;
3035 }
3036 }
3037 acb->acb_flags |= ACB_F_BUS_RESET;
3038 if (!arcmsr_iop_reset(acb)) {
3039 struct MessageUnit_C __iomem *reg;
3040 reg = acb->pmuC;
3041 arcmsr_hardware_reset(acb);
3042 acb->acb_flags &= ~ACB_F_IOP_INITED;
3043sleep:
3044 arcmsr_sleep_for_bus_reset(cmd);
3045 if ((readl(&reg->host_diagnostic) & 0x04) != 0) {
3046 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d \n", acb->host->host_no, retry_count);
3047 if (retry_count > retrycount) {
3048 acb->fw_flag = FW_DEADLOCK;
3049 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!! \n", acb->host->host_no);
3050 return FAILED;
3051 }
3052 retry_count++;
3053 goto sleep;
3054 }
3055 acb->acb_flags |= ACB_F_IOP_INITED;
3056 /* disable all outbound interrupt */
3057 intmask_org = arcmsr_disable_outbound_ints(acb);
3058 arcmsr_get_firmware_spec(acb);
3059 arcmsr_start_adapter_bgrb(acb);
3060 /* clear Qbuffer if door bell ringed */
3061 outbound_doorbell = readl(&reg->outbound_doorbell);
3062 writel(outbound_doorbell, &reg->outbound_doorbell_clear); /*clear interrupt */
3063 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
3064 /* enable outbound Post Queue,outbound doorbell Interrupt */
3065 arcmsr_enable_outbound_ints(acb, intmask_org);
3066 atomic_set(&acb->rq_map_token, 16);
3067 atomic_set(&acb->ante_token_value, 16);
3068 acb->fw_flag = FW_NORMAL;
3069 init_timer(&acb->eternal_timer);
3070 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
3071 acb->eternal_timer.data = (unsigned long) acb;
3072 acb->eternal_timer.function = &arcmsr_request_device_map;
3073 add_timer(&acb->eternal_timer);
3074 acb->acb_flags &= ~ACB_F_BUS_RESET;
3075 rtn = SUCCESS;
3076 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
3077 } else {
3078 acb->acb_flags &= ~ACB_F_BUS_RESET;
3079 if (atomic_read(&acb->rq_map_token) == 0) {
3080 atomic_set(&acb->rq_map_token, 16);
3081 atomic_set(&acb->ante_token_value, 16);
3082 acb->fw_flag = FW_NORMAL;
3083 init_timer(&acb->eternal_timer);
3084 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6*HZ);
3085 acb->eternal_timer.data = (unsigned long) acb;
3086 acb->eternal_timer.function = &arcmsr_request_device_map;
3087 add_timer(&acb->eternal_timer);
3088 } else {
3089 atomic_set(&acb->rq_map_token, 16);
3090 atomic_set(&acb->ante_token_value, 16);
3091 acb->fw_flag = FW_NORMAL;
3092 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
3093 }
3094 rtn = SUCCESS;
3095 }
3096 break;
ae52e7f0
NC		 3097 }
3098 }
3099 return rtn;
1c57e86d
EC		 3100}
3101
ae52e7f0 3102static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
1c57e86d
EC		 3103 struct CommandControlBlock *ccb)
3104{
ae52e7f0 3105 int rtn;
ae52e7f0 3106 rtn = arcmsr_polling_ccbdone(acb, ccb);
ae52e7f0 3107 return rtn;
1c57e86d
EC		 3108}
3109
3110static int arcmsr_abort(struct scsi_cmnd *cmd)
3111{
3112 struct AdapterControlBlock *acb =
3113 (struct AdapterControlBlock *)cmd->device->host->hostdata;
3114 int i = 0;
ae52e7f0 3115 int rtn = FAILED;
1c57e86d 3116 printk(KERN_NOTICE
a1f6e021 3117 "arcmsr%d: abort device command of scsi id = %d lun = %d \n",
1c57e86d 3118 acb->host->host_no, cmd->device->id, cmd->device->lun);
ae52e7f0 3119 acb->acb_flags |= ACB_F_ABORT;
1c57e86d 3120 acb->num_aborts++;
1c57e86d
EC		 3121 /*
3122 ************************************************
3123 ** the all interrupt service routine is locked
3124 ** we need to handle it as soon as possible and exit
3125 ************************************************
3126 */
3127 if (!atomic_read(&acb->ccboutstandingcount))
ae52e7f0 3128 return rtn;
1c57e86d
EC		 3129
3130 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
3131 struct CommandControlBlock *ccb = acb->pccb_pool[i];
3132 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
ae52e7f0
NC		 3133 ccb->startdone = ARCMSR_CCB_ABORTED;
3134 rtn = arcmsr_abort_one_cmd(acb, ccb);
1c57e86d
EC		 3135 break;
3136 }
3137 }
ae52e7f0
NC		 3138 acb->acb_flags &= ~ACB_F_ABORT;
3139 return rtn;
1c57e86d
EC		 3140}
3141
3142static const char *arcmsr_info(struct Scsi_Host *host)
3143{
3144 struct AdapterControlBlock *acb =
3145 (struct AdapterControlBlock *) host->hostdata;
3146 static char buf[256];
3147 char *type;
3148 int raid6 = 1;
1c57e86d
EC		 3149 switch (acb->pdev->device) {
3150 case PCI_DEVICE_ID_ARECA_1110:
1a4f550a
NC		 3151 case PCI_DEVICE_ID_ARECA_1200:
3152 case PCI_DEVICE_ID_ARECA_1202:
1c57e86d
EC		 3153 case PCI_DEVICE_ID_ARECA_1210:
3154 raid6 = 0;
3155 /*FALLTHRU*/
3156 case PCI_DEVICE_ID_ARECA_1120:
3157 case PCI_DEVICE_ID_ARECA_1130:
3158 case PCI_DEVICE_ID_ARECA_1160:
3159 case PCI_DEVICE_ID_ARECA_1170:
1a4f550a 3160 case PCI_DEVICE_ID_ARECA_1201:
1c57e86d
EC		 3161 case PCI_DEVICE_ID_ARECA_1220:
3162 case PCI_DEVICE_ID_ARECA_1230:
3163 case PCI_DEVICE_ID_ARECA_1260:
3164 case PCI_DEVICE_ID_ARECA_1270:
3165 case PCI_DEVICE_ID_ARECA_1280:
3166 type = "SATA";
3167 break;
3168 case PCI_DEVICE_ID_ARECA_1380:
3169 case PCI_DEVICE_ID_ARECA_1381:
3170 case PCI_DEVICE_ID_ARECA_1680:
3171 case PCI_DEVICE_ID_ARECA_1681:
cdd3cb15 3172 case PCI_DEVICE_ID_ARECA_1880:
1c57e86d
EC		 3173 type = "SAS";
3174 break;
3175 default:
3176 type = "X-TYPE";
3177 break;
3178 }
a1f6e021 3179 sprintf(buf, "Areca %s Host Adapter RAID Controller%s\n %s",
1c57e86d
EC		 3180 type, raid6 ? "( RAID6 capable)" : "",
3181 ARCMSR_DRIVER_VERSION);
3182 return buf;
3183}
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