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1da177e4 LT |
1 | /* |
2 | ||
3 | ata_piix.c - Intel PATA/SATA controllers | |
4 | ||
5 | Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
6 | Please ALWAYS copy linux-ide@vger.kernel.org | |
7 | on emails. | |
8 | ||
9 | ||
10 | Copyright 2003-2004 Red Hat Inc | |
11 | Copyright 2003-2004 Jeff Garzik | |
12 | ||
13 | ||
14 | Copyright header from piix.c: | |
15 | ||
16 | Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
17 | Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
18 | Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
19 | ||
20 | May be copied or modified under the terms of the GNU General Public License | |
21 | ||
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/blkdev.h> | |
29 | #include <linux/delay.h> | |
30 | #include "scsi.h" | |
31 | #include <scsi/scsi_host.h> | |
32 | #include <linux/libata.h> | |
33 | ||
34 | #define DRV_NAME "ata_piix" | |
35 | #define DRV_VERSION "1.03" | |
36 | ||
37 | enum { | |
38 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ | |
39 | ICH5_PMR = 0x90, /* port mapping register */ | |
40 | ICH5_PCS = 0x92, /* port control and status */ | |
41 | ||
42 | PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */ | |
43 | PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */ | |
44 | PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */ | |
45 | ||
46 | /* combined mode. if set, PATA is channel 0. | |
47 | * if clear, PATA is channel 1. | |
48 | */ | |
49 | PIIX_COMB_PATA_P0 = (1 << 1), | |
50 | PIIX_COMB = (1 << 2), /* combined mode enabled? */ | |
51 | ||
52 | PIIX_PORT_PRESENT = (1 << 0), | |
53 | PIIX_PORT_ENABLED = (1 << 4), | |
54 | ||
55 | PIIX_80C_PRI = (1 << 5) | (1 << 4), | |
56 | PIIX_80C_SEC = (1 << 7) | (1 << 6), | |
57 | ||
58 | ich5_pata = 0, | |
59 | ich5_sata = 1, | |
60 | piix4_pata = 2, | |
61 | ich6_sata = 3, | |
62 | ich6_sata_rm = 4, | |
63 | ich7_sata = 5, | |
64 | }; | |
65 | ||
66 | static int piix_init_one (struct pci_dev *pdev, | |
67 | const struct pci_device_id *ent); | |
68 | ||
69 | static void piix_pata_phy_reset(struct ata_port *ap); | |
70 | static void piix_sata_phy_reset(struct ata_port *ap); | |
71 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); | |
72 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); | |
73 | ||
74 | static unsigned int in_module_init = 1; | |
75 | ||
76 | static struct pci_device_id piix_pci_tbl[] = { | |
77 | #ifdef ATA_ENABLE_PATA | |
78 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata }, | |
79 | { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, | |
80 | { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, | |
81 | #endif | |
82 | ||
83 | /* NOTE: The following PCI ids must be kept in sync with the | |
84 | * list in drivers/pci/quirks.c. | |
85 | */ | |
86 | ||
87 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, | |
88 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, | |
89 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, | |
90 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, | |
91 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, | |
92 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm }, | |
93 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm }, | |
94 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata }, | |
95 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata }, | |
96 | ||
97 | { } /* terminate list */ | |
98 | }; | |
99 | ||
100 | static struct pci_driver piix_pci_driver = { | |
101 | .name = DRV_NAME, | |
102 | .id_table = piix_pci_tbl, | |
103 | .probe = piix_init_one, | |
104 | .remove = ata_pci_remove_one, | |
105 | }; | |
106 | ||
107 | static Scsi_Host_Template piix_sht = { | |
108 | .module = THIS_MODULE, | |
109 | .name = DRV_NAME, | |
110 | .ioctl = ata_scsi_ioctl, | |
111 | .queuecommand = ata_scsi_queuecmd, | |
112 | .eh_strategy_handler = ata_scsi_error, | |
113 | .can_queue = ATA_DEF_QUEUE, | |
114 | .this_id = ATA_SHT_THIS_ID, | |
115 | .sg_tablesize = LIBATA_MAX_PRD, | |
116 | .max_sectors = ATA_MAX_SECTORS, | |
117 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
118 | .emulated = ATA_SHT_EMULATED, | |
119 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
120 | .proc_name = DRV_NAME, | |
121 | .dma_boundary = ATA_DMA_BOUNDARY, | |
122 | .slave_configure = ata_scsi_slave_config, | |
123 | .bios_param = ata_std_bios_param, | |
124 | .ordered_flush = 1, | |
125 | }; | |
126 | ||
127 | static struct ata_port_operations piix_pata_ops = { | |
128 | .port_disable = ata_port_disable, | |
129 | .set_piomode = piix_set_piomode, | |
130 | .set_dmamode = piix_set_dmamode, | |
131 | ||
132 | .tf_load = ata_tf_load, | |
133 | .tf_read = ata_tf_read, | |
134 | .check_status = ata_check_status, | |
135 | .exec_command = ata_exec_command, | |
136 | .dev_select = ata_std_dev_select, | |
137 | ||
138 | .phy_reset = piix_pata_phy_reset, | |
139 | ||
140 | .bmdma_setup = ata_bmdma_setup, | |
141 | .bmdma_start = ata_bmdma_start, | |
142 | .bmdma_stop = ata_bmdma_stop, | |
143 | .bmdma_status = ata_bmdma_status, | |
144 | .qc_prep = ata_qc_prep, | |
145 | .qc_issue = ata_qc_issue_prot, | |
146 | ||
147 | .eng_timeout = ata_eng_timeout, | |
148 | ||
149 | .irq_handler = ata_interrupt, | |
150 | .irq_clear = ata_bmdma_irq_clear, | |
151 | ||
152 | .port_start = ata_port_start, | |
153 | .port_stop = ata_port_stop, | |
154 | }; | |
155 | ||
156 | static struct ata_port_operations piix_sata_ops = { | |
157 | .port_disable = ata_port_disable, | |
158 | ||
159 | .tf_load = ata_tf_load, | |
160 | .tf_read = ata_tf_read, | |
161 | .check_status = ata_check_status, | |
162 | .exec_command = ata_exec_command, | |
163 | .dev_select = ata_std_dev_select, | |
164 | ||
165 | .phy_reset = piix_sata_phy_reset, | |
166 | ||
167 | .bmdma_setup = ata_bmdma_setup, | |
168 | .bmdma_start = ata_bmdma_start, | |
169 | .bmdma_stop = ata_bmdma_stop, | |
170 | .bmdma_status = ata_bmdma_status, | |
171 | .qc_prep = ata_qc_prep, | |
172 | .qc_issue = ata_qc_issue_prot, | |
173 | ||
174 | .eng_timeout = ata_eng_timeout, | |
175 | ||
176 | .irq_handler = ata_interrupt, | |
177 | .irq_clear = ata_bmdma_irq_clear, | |
178 | ||
179 | .port_start = ata_port_start, | |
180 | .port_stop = ata_port_stop, | |
181 | }; | |
182 | ||
183 | static struct ata_port_info piix_port_info[] = { | |
184 | /* ich5_pata */ | |
185 | { | |
186 | .sht = &piix_sht, | |
187 | .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | | |
188 | PIIX_FLAG_CHECKINTR, | |
189 | .pio_mask = 0x1f, /* pio0-4 */ | |
190 | #if 0 | |
191 | .mwdma_mask = 0x06, /* mwdma1-2 */ | |
192 | #else | |
193 | .mwdma_mask = 0x00, /* mwdma broken */ | |
194 | #endif | |
195 | .udma_mask = 0x3f, /* udma0-5 */ | |
196 | .port_ops = &piix_pata_ops, | |
197 | }, | |
198 | ||
199 | /* ich5_sata */ | |
200 | { | |
201 | .sht = &piix_sht, | |
202 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST | | |
203 | PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR, | |
204 | .pio_mask = 0x1f, /* pio0-4 */ | |
205 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
206 | .udma_mask = 0x7f, /* udma0-6 */ | |
207 | .port_ops = &piix_sata_ops, | |
208 | }, | |
209 | ||
210 | /* piix4_pata */ | |
211 | { | |
212 | .sht = &piix_sht, | |
213 | .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
214 | .pio_mask = 0x1f, /* pio0-4 */ | |
215 | #if 0 | |
216 | .mwdma_mask = 0x06, /* mwdma1-2 */ | |
217 | #else | |
218 | .mwdma_mask = 0x00, /* mwdma broken */ | |
219 | #endif | |
220 | .udma_mask = ATA_UDMA_MASK_40C, | |
221 | .port_ops = &piix_pata_ops, | |
222 | }, | |
223 | ||
224 | /* ich6_sata */ | |
225 | { | |
226 | .sht = &piix_sht, | |
227 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST | | |
228 | PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR | | |
229 | ATA_FLAG_SLAVE_POSS, | |
230 | .pio_mask = 0x1f, /* pio0-4 */ | |
231 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
232 | .udma_mask = 0x7f, /* udma0-6 */ | |
233 | .port_ops = &piix_sata_ops, | |
234 | }, | |
235 | ||
236 | /* ich6_sata_rm */ | |
237 | { | |
238 | .sht = &piix_sht, | |
239 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST | | |
240 | PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR | | |
241 | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI, | |
242 | .pio_mask = 0x1f, /* pio0-4 */ | |
243 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
244 | .udma_mask = 0x7f, /* udma0-6 */ | |
245 | .port_ops = &piix_sata_ops, | |
246 | }, | |
247 | ||
248 | /* ich7_sata */ | |
249 | { | |
250 | .sht = &piix_sht, | |
251 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST | | |
252 | PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR | | |
253 | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI, | |
254 | .pio_mask = 0x1f, /* pio0-4 */ | |
255 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
256 | .udma_mask = 0x7f, /* udma0-6 */ | |
257 | .port_ops = &piix_sata_ops, | |
258 | }, | |
259 | }; | |
260 | ||
261 | static struct pci_bits piix_enable_bits[] = { | |
262 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ | |
263 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ | |
264 | }; | |
265 | ||
266 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); | |
267 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); | |
268 | MODULE_LICENSE("GPL"); | |
269 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
270 | MODULE_VERSION(DRV_VERSION); | |
271 | ||
272 | /** | |
273 | * piix_pata_cbl_detect - Probe host controller cable detect info | |
274 | * @ap: Port for which cable detect info is desired | |
275 | * | |
276 | * Read 80c cable indicator from ATA PCI device's PCI config | |
277 | * register. This register is normally set by firmware (BIOS). | |
278 | * | |
279 | * LOCKING: | |
280 | * None (inherited from caller). | |
281 | */ | |
282 | static void piix_pata_cbl_detect(struct ata_port *ap) | |
283 | { | |
284 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
285 | u8 tmp, mask; | |
286 | ||
287 | /* no 80c support in host controller? */ | |
288 | if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0) | |
289 | goto cbl40; | |
290 | ||
291 | /* check BIOS cable detect results */ | |
292 | mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; | |
293 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); | |
294 | if ((tmp & mask) == 0) | |
295 | goto cbl40; | |
296 | ||
297 | ap->cbl = ATA_CBL_PATA80; | |
298 | return; | |
299 | ||
300 | cbl40: | |
301 | ap->cbl = ATA_CBL_PATA40; | |
302 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
303 | } | |
304 | ||
305 | /** | |
306 | * piix_pata_phy_reset - Probe specified port on PATA host controller | |
307 | * @ap: Port to probe | |
308 | * | |
309 | * Probe PATA phy. | |
310 | * | |
311 | * LOCKING: | |
312 | * None (inherited from caller). | |
313 | */ | |
314 | ||
315 | static void piix_pata_phy_reset(struct ata_port *ap) | |
316 | { | |
317 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
318 | ||
319 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) { | |
320 | ata_port_disable(ap); | |
321 | printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id); | |
322 | return; | |
323 | } | |
324 | ||
325 | piix_pata_cbl_detect(ap); | |
326 | ||
327 | ata_port_probe(ap); | |
328 | ||
329 | ata_bus_reset(ap); | |
330 | } | |
331 | ||
332 | /** | |
333 | * piix_sata_probe - Probe PCI device for present SATA devices | |
334 | * @ap: Port associated with the PCI device we wish to probe | |
335 | * | |
336 | * Reads SATA PCI device's PCI config register Port Configuration | |
337 | * and Status (PCS) to determine port and device availability. | |
338 | * | |
339 | * LOCKING: | |
340 | * None (inherited from caller). | |
341 | * | |
342 | * RETURNS: | |
343 | * Non-zero if device detected, zero otherwise. | |
344 | */ | |
345 | static int piix_sata_probe (struct ata_port *ap) | |
346 | { | |
347 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
348 | int combined = (ap->flags & ATA_FLAG_SLAVE_POSS); | |
349 | int orig_mask, mask, i; | |
350 | u8 pcs; | |
351 | ||
352 | mask = (PIIX_PORT_PRESENT << ap->hard_port_no) | | |
353 | (PIIX_PORT_ENABLED << ap->hard_port_no); | |
354 | ||
355 | pci_read_config_byte(pdev, ICH5_PCS, &pcs); | |
356 | orig_mask = (int) pcs & 0xff; | |
357 | ||
358 | /* TODO: this is vaguely wrong for ICH6 combined mode, | |
359 | * where only two of the four SATA ports are mapped | |
360 | * onto a single ATA channel. It is also vaguely inaccurate | |
361 | * for ICH5, which has only two ports. However, this is ok, | |
362 | * as further device presence detection code will handle | |
363 | * any false positives produced here. | |
364 | */ | |
365 | ||
366 | for (i = 0; i < 4; i++) { | |
367 | mask = (PIIX_PORT_PRESENT << i) | (PIIX_PORT_ENABLED << i); | |
368 | ||
369 | if ((orig_mask & mask) == mask) | |
370 | if (combined || (i == ap->hard_port_no)) | |
371 | return 1; | |
372 | } | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | /** | |
378 | * piix_sata_phy_reset - Probe specified port on SATA host controller | |
379 | * @ap: Port to probe | |
380 | * | |
381 | * Probe SATA phy. | |
382 | * | |
383 | * LOCKING: | |
384 | * None (inherited from caller). | |
385 | */ | |
386 | ||
387 | static void piix_sata_phy_reset(struct ata_port *ap) | |
388 | { | |
389 | if (!piix_sata_probe(ap)) { | |
390 | ata_port_disable(ap); | |
391 | printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id); | |
392 | return; | |
393 | } | |
394 | ||
395 | ap->cbl = ATA_CBL_SATA; | |
396 | ||
397 | ata_port_probe(ap); | |
398 | ||
399 | ata_bus_reset(ap); | |
400 | } | |
401 | ||
402 | /** | |
403 | * piix_set_piomode - Initialize host controller PATA PIO timings | |
404 | * @ap: Port whose timings we are configuring | |
405 | * @adev: um | |
406 | * @pio: PIO mode, 0 - 4 | |
407 | * | |
408 | * Set PIO mode for device, in host controller PCI config space. | |
409 | * | |
410 | * LOCKING: | |
411 | * None (inherited from caller). | |
412 | */ | |
413 | ||
414 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
415 | { | |
416 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
417 | struct pci_dev *dev = to_pci_dev(ap->host_set->dev); | |
418 | unsigned int is_slave = (adev->devno != 0); | |
419 | unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40; | |
420 | unsigned int slave_port = 0x44; | |
421 | u16 master_data; | |
422 | u8 slave_data; | |
423 | ||
424 | static const /* ISP RTC */ | |
425 | u8 timings[][2] = { { 0, 0 }, | |
426 | { 0, 0 }, | |
427 | { 1, 0 }, | |
428 | { 2, 1 }, | |
429 | { 2, 3 }, }; | |
430 | ||
431 | pci_read_config_word(dev, master_port, &master_data); | |
432 | if (is_slave) { | |
433 | master_data |= 0x4000; | |
434 | /* enable PPE, IE and TIME */ | |
435 | master_data |= 0x0070; | |
436 | pci_read_config_byte(dev, slave_port, &slave_data); | |
437 | slave_data &= (ap->hard_port_no ? 0x0f : 0xf0); | |
438 | slave_data |= | |
439 | (timings[pio][0] << 2) | | |
440 | (timings[pio][1] << (ap->hard_port_no ? 4 : 0)); | |
441 | } else { | |
442 | master_data &= 0xccf8; | |
443 | /* enable PPE, IE and TIME */ | |
444 | master_data |= 0x0007; | |
445 | master_data |= | |
446 | (timings[pio][0] << 12) | | |
447 | (timings[pio][1] << 8); | |
448 | } | |
449 | pci_write_config_word(dev, master_port, master_data); | |
450 | if (is_slave) | |
451 | pci_write_config_byte(dev, slave_port, slave_data); | |
452 | } | |
453 | ||
454 | /** | |
455 | * piix_set_dmamode - Initialize host controller PATA PIO timings | |
456 | * @ap: Port whose timings we are configuring | |
457 | * @adev: um | |
458 | * @udma: udma mode, 0 - 6 | |
459 | * | |
460 | * Set UDMA mode for device, in host controller PCI config space. | |
461 | * | |
462 | * LOCKING: | |
463 | * None (inherited from caller). | |
464 | */ | |
465 | ||
466 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
467 | { | |
468 | unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */ | |
469 | struct pci_dev *dev = to_pci_dev(ap->host_set->dev); | |
470 | u8 maslave = ap->hard_port_no ? 0x42 : 0x40; | |
471 | u8 speed = udma; | |
472 | unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno; | |
473 | int a_speed = 3 << (drive_dn * 4); | |
474 | int u_flag = 1 << drive_dn; | |
475 | int v_flag = 0x01 << drive_dn; | |
476 | int w_flag = 0x10 << drive_dn; | |
477 | int u_speed = 0; | |
478 | int sitre; | |
479 | u16 reg4042, reg4a; | |
480 | u8 reg48, reg54, reg55; | |
481 | ||
482 | pci_read_config_word(dev, maslave, ®4042); | |
483 | DPRINTK("reg4042 = 0x%04x\n", reg4042); | |
484 | sitre = (reg4042 & 0x4000) ? 1 : 0; | |
485 | pci_read_config_byte(dev, 0x48, ®48); | |
486 | pci_read_config_word(dev, 0x4a, ®4a); | |
487 | pci_read_config_byte(dev, 0x54, ®54); | |
488 | pci_read_config_byte(dev, 0x55, ®55); | |
489 | ||
490 | switch(speed) { | |
491 | case XFER_UDMA_4: | |
492 | case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break; | |
493 | case XFER_UDMA_6: | |
494 | case XFER_UDMA_5: | |
495 | case XFER_UDMA_3: | |
496 | case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break; | |
497 | case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break; | |
498 | case XFER_MW_DMA_2: | |
499 | case XFER_MW_DMA_1: break; | |
500 | default: | |
501 | BUG(); | |
502 | return; | |
503 | } | |
504 | ||
505 | if (speed >= XFER_UDMA_0) { | |
506 | if (!(reg48 & u_flag)) | |
507 | pci_write_config_byte(dev, 0x48, reg48 | u_flag); | |
508 | if (speed == XFER_UDMA_5) { | |
509 | pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); | |
510 | } else { | |
511 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
512 | } | |
513 | if ((reg4a & a_speed) != u_speed) | |
514 | pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); | |
515 | if (speed > XFER_UDMA_2) { | |
516 | if (!(reg54 & v_flag)) | |
517 | pci_write_config_byte(dev, 0x54, reg54 | v_flag); | |
518 | } else | |
519 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
520 | } else { | |
521 | if (reg48 & u_flag) | |
522 | pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); | |
523 | if (reg4a & a_speed) | |
524 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
525 | if (reg54 & v_flag) | |
526 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
527 | if (reg55 & w_flag) | |
528 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
529 | } | |
530 | } | |
531 | ||
532 | /* move to PCI layer, integrate w/ MSI stuff */ | |
533 | static void pci_enable_intx(struct pci_dev *pdev) | |
534 | { | |
535 | u16 pci_command; | |
536 | ||
537 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
538 | if (pci_command & PCI_COMMAND_INTX_DISABLE) { | |
539 | pci_command &= ~PCI_COMMAND_INTX_DISABLE; | |
540 | pci_write_config_word(pdev, PCI_COMMAND, pci_command); | |
541 | } | |
542 | } | |
543 | ||
544 | #define AHCI_PCI_BAR 5 | |
545 | #define AHCI_GLOBAL_CTL 0x04 | |
546 | #define AHCI_ENABLE (1 << 31) | |
547 | static int piix_disable_ahci(struct pci_dev *pdev) | |
548 | { | |
549 | void *mmio; | |
550 | unsigned long addr; | |
551 | u32 tmp; | |
552 | int rc = 0; | |
553 | ||
554 | /* BUG: pci_enable_device has not yet been called. This | |
555 | * works because this device is usually set up by BIOS. | |
556 | */ | |
557 | ||
558 | addr = pci_resource_start(pdev, AHCI_PCI_BAR); | |
559 | if (!addr || !pci_resource_len(pdev, AHCI_PCI_BAR)) | |
560 | return 0; | |
561 | ||
562 | mmio = ioremap(addr, 64); | |
563 | if (!mmio) | |
564 | return -ENOMEM; | |
565 | ||
566 | tmp = readl(mmio + AHCI_GLOBAL_CTL); | |
567 | if (tmp & AHCI_ENABLE) { | |
568 | tmp &= ~AHCI_ENABLE; | |
569 | writel(tmp, mmio + AHCI_GLOBAL_CTL); | |
570 | ||
571 | tmp = readl(mmio + AHCI_GLOBAL_CTL); | |
572 | if (tmp & AHCI_ENABLE) | |
573 | rc = -EIO; | |
574 | } | |
575 | ||
576 | iounmap(mmio); | |
577 | return rc; | |
578 | } | |
579 | ||
580 | /** | |
581 | * piix_init_one - Register PIIX ATA PCI device with kernel services | |
582 | * @pdev: PCI device to register | |
583 | * @ent: Entry in piix_pci_tbl matching with @pdev | |
584 | * | |
585 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
586 | * and then hand over control to libata, for it to do the rest. | |
587 | * | |
588 | * LOCKING: | |
589 | * Inherited from PCI layer (may sleep). | |
590 | * | |
591 | * RETURNS: | |
592 | * Zero on success, or -ERRNO value. | |
593 | */ | |
594 | ||
595 | static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
596 | { | |
597 | static int printed_version; | |
598 | struct ata_port_info *port_info[2]; | |
599 | unsigned int combined = 0, n_ports = 1; | |
600 | unsigned int pata_chan = 0, sata_chan = 0; | |
601 | ||
602 | if (!printed_version++) | |
603 | printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); | |
604 | ||
605 | /* no hotplugging support (FIXME) */ | |
606 | if (!in_module_init) | |
607 | return -ENODEV; | |
608 | ||
609 | port_info[0] = &piix_port_info[ent->driver_data]; | |
610 | port_info[1] = NULL; | |
611 | ||
612 | if (port_info[0]->host_flags & PIIX_FLAG_AHCI) { | |
613 | int rc = piix_disable_ahci(pdev); | |
614 | if (rc) | |
615 | return rc; | |
616 | } | |
617 | ||
618 | if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) { | |
619 | u8 tmp; | |
620 | pci_read_config_byte(pdev, ICH5_PMR, &tmp); | |
621 | ||
622 | if (tmp & PIIX_COMB) { | |
623 | combined = 1; | |
624 | if (tmp & PIIX_COMB_PATA_P0) | |
625 | sata_chan = 1; | |
626 | else | |
627 | pata_chan = 1; | |
628 | } | |
629 | } | |
630 | ||
631 | /* On ICH5, some BIOSen disable the interrupt using the | |
632 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. | |
633 | * On ICH6, this bit has the same effect, but only when | |
634 | * MSI is disabled (and it is disabled, as we don't use | |
635 | * message-signalled interrupts currently). | |
636 | */ | |
637 | if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR) | |
638 | pci_enable_intx(pdev); | |
639 | ||
640 | if (combined) { | |
641 | port_info[sata_chan] = &piix_port_info[ent->driver_data]; | |
642 | port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS; | |
643 | port_info[pata_chan] = &piix_port_info[ich5_pata]; | |
644 | n_ports++; | |
645 | ||
646 | printk(KERN_WARNING DRV_NAME ": combined mode detected\n"); | |
647 | } | |
648 | ||
649 | return ata_pci_init_one(pdev, port_info, n_ports); | |
650 | } | |
651 | ||
652 | /** | |
653 | * piix_init - | |
654 | * | |
655 | * LOCKING: | |
656 | * | |
657 | * RETURNS: | |
658 | * | |
659 | */ | |
660 | ||
661 | static int __init piix_init(void) | |
662 | { | |
663 | int rc; | |
664 | ||
665 | DPRINTK("pci_module_init\n"); | |
666 | rc = pci_module_init(&piix_pci_driver); | |
667 | if (rc) | |
668 | return rc; | |
669 | ||
670 | in_module_init = 0; | |
671 | ||
672 | DPRINTK("done\n"); | |
673 | return 0; | |
674 | } | |
675 | ||
676 | /** | |
677 | * piix_exit - | |
678 | * | |
679 | * LOCKING: | |
680 | * | |
681 | */ | |
682 | ||
683 | static void __exit piix_exit(void) | |
684 | { | |
685 | pci_unregister_driver(&piix_pci_driver); | |
686 | } | |
687 | ||
688 | module_init(piix_init); | |
689 | module_exit(piix_exit); | |
690 |