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atp870u: Untangle tmport #8
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / atp870u.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (C) 1997 Wu Ching Chen
3 * 2.1.x update (C) 1998 Krzysztof G. Baranowski
fa195afe
AC		 4 * 2.5.x update (C) 2002 Red Hat
5 * 2.6.x update (C) 2004 Red Hat
1da177e4
LT		 6 *
7 * Marcelo Tosatti <marcelo@conectiva.com.br> : SMP fixes
8 *
9 * Wu Ching Chen : NULL pointer fixes 2000/06/02
10 * support atp876 chip
11 * enable 32 bit fifo transfer
12 * support cdrom & remove device run ultra speed
13 * fix disconnect bug 2000/12/21
14 * support atp880 chip lvd u160 2001/05/15
15 * fix prd table bug 2001/09/12 (7.1)
16 *
17 * atp885 support add by ACARD Hao Ping Lian 2005/01/05
18 */
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/string.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
27#include <linux/proc_fs.h>
28#include <linux/spinlock.h>
29#include <linux/pci.h>
30#include <linux/blkdev.h>
910638ae 31#include <linux/dma-mapping.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include <asm/io.h>
34
35#include <scsi/scsi.h>
36#include <scsi/scsi_cmnd.h>
37#include <scsi/scsi_device.h>
38#include <scsi/scsi_host.h>
39
40#include "atp870u.h"
41
42static struct scsi_host_template atp870u_template;
43static void send_s870(struct atp_unit *dev,unsigned char c);
44static void is885(struct atp_unit *dev, unsigned int wkport,unsigned char c);
45static void tscam_885(void);
46
7d12e780 47static irqreturn_t atp870u_intr_handle(int irq, void *dev_id)
1da177e4
LT		 48{
49 unsigned long flags;
50 unsigned short int tmpcip, id;
51 unsigned char i, j, c, target_id, lun,cmdp;
52 unsigned char *prd;
53 struct scsi_cmnd *workreq;
1da177e4
LT		 54 unsigned long adrcnt, k;
55#ifdef ED_DBGP
56 unsigned long l;
57#endif
58 int errstus;
59 struct Scsi_Host *host = dev_id;
60 struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
61
62 for (c = 0; c < 2; c++) {
3a38e53e 63 j = inb(dev->ioport[c] + 0x1f);
1da177e4
LT		 64 if ((j & 0x80) != 0)
65 {
66 goto ch_sel;
67 }
68 dev->in_int[c] = 0;
69 }
70 return IRQ_NONE;
71ch_sel:
72#ifdef ED_DBGP
73 printk("atp870u_intr_handle enter\n");
74#endif
75 dev->in_int[c] = 1;
76 cmdp = inb(dev->ioport[c] + 0x10);
1da177e4
LT		 77 if (dev->working[c] != 0) {
78 if (dev->dev_id == ATP885_DEVID) {
b4263b3c
OZ		 79 if ((inb(dev->ioport[c] + 0x16) & 0x80) == 0)
80 outb((inb(dev->ioport[c] + 0x16) | 0x80), dev->ioport[c] + 0x16);
1da177e4
LT		 81 }
82 tmpcip = dev->pciport[c];
83 if ((inb(tmpcip) & 0x08) != 0)
84 {
85 tmpcip += 0x2;
86 for (k=0; k < 1000; k++) {
87 if ((inb(tmpcip) & 0x08) == 0) {
88 goto stop_dma;
89 }
90 if ((inb(tmpcip) & 0x01) == 0) {
91 goto stop_dma;
92 }
93 }
94 }
95stop_dma:
96 tmpcip = dev->pciport[c];
97 outb(0x00, tmpcip);
1da177e4 98
3a38e53e 99 i = inb(dev->ioport[c] + 0x17);
1da177e4
LT		 100
101 if (dev->dev_id == ATP885_DEVID) {
102 tmpcip += 2;
103 outb(0x06, tmpcip);
104 tmpcip -= 2;
105 }
106
3a38e53e 107 target_id = inb(dev->ioport[c] + 0x15);
1da177e4
LT		 108
109 /*
110 * Remap wide devices onto id numbers
111 */
112
113 if ((target_id & 0x40) != 0) {
114 target_id = (target_id & 0x07) | 0x08;
115 } else {
116 target_id &= 0x07;
117 }
118
119 if ((j & 0x40) != 0) {
120 if (dev->last_cmd[c] == 0xff) {
121 dev->last_cmd[c] = target_id;
122 }
123 dev->last_cmd[c] |= 0x40;
124 }
125 if (dev->dev_id == ATP885_DEVID)
126 dev->r1f[c][target_id] |= j;
127#ifdef ED_DBGP
128 printk("atp870u_intr_handle status = %x\n",i);
129#endif
130 if (i == 0x85) {
131 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
132 dev->last_cmd[c] = 0xff;
133 }
134 if (dev->dev_id == ATP885_DEVID) {
1da177e4 135 adrcnt = 0;
3a38e53e
OZ		 136 ((unsigned char *) &adrcnt)[2] = inb(dev->ioport[c] + 0x12);
137 ((unsigned char *) &adrcnt)[1] = inb(dev->ioport[c] + 0x13);
138 ((unsigned char *) &adrcnt)[0] = inb(dev->ioport[c] + 0x14);
1da177e4
LT		 139 if (dev->id[c][target_id].last_len != adrcnt)
140 {
141 k = dev->id[c][target_id].last_len;
142 k -= adrcnt;
143 dev->id[c][target_id].tran_len = k;
144 dev->id[c][target_id].last_len = adrcnt;
145 }
146#ifdef ED_DBGP
3a38e53e 147 printk("dev->id[c][target_id].last_len = %d dev->id[c][target_id].tran_len = %d\n",dev->id[c][target_id].last_len,dev->id[c][target_id].tran_len);
1da177e4
LT		 148#endif
149 }
150
151 /*
152 * Flip wide
153 */
154 if (dev->wide_id[c] != 0) {
3a38e53e
OZ		 155 outb(0x01, dev->ioport[c] + 0x1b);
156 while ((inb(dev->ioport[c] + 0x1b) & 0x01) != 0x01) {
157 outb(0x01, dev->ioport[c] + 0x1b);
1da177e4
LT		 158 }
159 }
160 /*
161 * Issue more commands
162 */
163 spin_lock_irqsave(dev->host->host_lock, flags);
164 if (((dev->quhd[c] != dev->quend[c]) || (dev->last_cmd[c] != 0xff)) &&
165 (dev->in_snd[c] == 0)) {
166#ifdef ED_DBGP
167 printk("Call sent_s870\n");
168#endif
169 send_s870(dev,c);
170 }
171 spin_unlock_irqrestore(dev->host->host_lock, flags);
172 /*
173 * Done
174 */
175 dev->in_int[c] = 0;
176#ifdef ED_DBGP
177 printk("Status 0x85 return\n");
178#endif
179 goto handled;
180 }
181
182 if (i == 0x40) {
183 dev->last_cmd[c] |= 0x40;
184 dev->in_int[c] = 0;
185 goto handled;
186 }
187
188 if (i == 0x21) {
189 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
190 dev->last_cmd[c] = 0xff;
191 }
1da177e4 192 adrcnt = 0;
3a38e53e
OZ		 193 ((unsigned char *) &adrcnt)[2] = inb(dev->ioport[c] + 0x12);
194 ((unsigned char *) &adrcnt)[1] = inb(dev->ioport[c] + 0x13);
195 ((unsigned char *) &adrcnt)[0] = inb(dev->ioport[c] + 0x14);
1da177e4
LT		 196 k = dev->id[c][target_id].last_len;
197 k -= adrcnt;
198 dev->id[c][target_id].tran_len = k;
199 dev->id[c][target_id].last_len = adrcnt;
3a38e53e
OZ		 200 outb(0x41, dev->ioport[c] + 0x10);
201 outb(0x08, dev->ioport[c] + 0x18);
1da177e4
LT		 202 dev->in_int[c] = 0;
203 goto handled;
204 }
205
206 if (dev->dev_id == ATP885_DEVID) {
207 if ((i == 0x4c) || (i == 0x4d) || (i == 0x8c) || (i == 0x8d)) {
208 if ((i == 0x4c) || (i == 0x8c))
209 i=0x48;
210 else
211 i=0x49;
212 }
213
214 }
215 if ((i == 0x80) || (i == 0x8f)) {
216#ifdef ED_DBGP
217 printk(KERN_DEBUG "Device reselect\n");
218#endif
219 lun = 0;
1da177e4 220 if (cmdp == 0x44 || i==0x80) {
3a38e53e 221 lun = inb(dev->ioport[c] + 0x1d) & 0x07;
1da177e4
LT		 222 } else {
223 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
224 dev->last_cmd[c] = 0xff;
225 }
226 if (cmdp == 0x41) {
227#ifdef ED_DBGP
228 printk("cmdp = 0x41\n");
229#endif
1da177e4 230 adrcnt = 0;
3a38e53e
OZ		 231 ((unsigned char *) &adrcnt)[2] = inb(dev->ioport[c] + 0x12);
232 ((unsigned char *) &adrcnt)[1] = inb(dev->ioport[c] + 0x13);
233 ((unsigned char *) &adrcnt)[0] = inb(dev->ioport[c] + 0x14);
1da177e4
LT		 234 k = dev->id[c][target_id].last_len;
235 k -= adrcnt;
236 dev->id[c][target_id].tran_len = k;
237 dev->id[c][target_id].last_len = adrcnt;
3a38e53e 238 outb(0x08, dev->ioport[c] + 0x18);
1da177e4
LT		 239 dev->in_int[c] = 0;
240 goto handled;
241 } else {
242#ifdef ED_DBGP
243 printk("cmdp != 0x41\n");
244#endif
3a38e53e 245 outb(0x46, dev->ioport[c] + 0x10);
1da177e4 246 dev->id[c][target_id].dirct = 0x00;
3a38e53e
OZ		 247 outb(0x00, dev->ioport[c] + 0x12);
248 outb(0x00, dev->ioport[c] + 0x13);
249 outb(0x00, dev->ioport[c] + 0x14);
250 outb(0x08, dev->ioport[c] + 0x18);
1da177e4
LT		 251 dev->in_int[c] = 0;
252 goto handled;
253 }
254 }
255 if (dev->last_cmd[c] != 0xff) {
256 dev->last_cmd[c] |= 0x40;
257 }
258 if (dev->dev_id == ATP885_DEVID) {
259 j = inb(dev->baseport + 0x29) & 0xfe;
260 outb(j, dev->baseport + 0x29);
3a38e53e
OZ		 261 } else
262 outb(0x45, dev->ioport[c] + 0x10);
263
264 target_id = inb(dev->ioport[c] + 0x16);
1da177e4
LT		 265 /*
266 * Remap wide identifiers
267 */
268 if ((target_id & 0x10) != 0) {
269 target_id = (target_id & 0x07) | 0x08;
270 } else {
271 target_id &= 0x07;
272 }
3a38e53e
OZ		 273 if (dev->dev_id == ATP885_DEVID)
274 outb(0x45, dev->ioport[c] + 0x10);
1da177e4
LT		 275 workreq = dev->id[c][target_id].curr_req;
276#ifdef ED_DBGP
017560fc
JG		 277 scmd_printk(KERN_DEBUG, workreq, "CDB");
278 for (l = 0; l < workreq->cmd_len; l++)
1da177e4 279 printk(KERN_DEBUG " %x",workreq->cmnd[l]);
017560fc 280 printk("\n");
1da177e4
LT		 281#endif
282
3a38e53e
OZ		 283 outb(lun, dev->ioport[c] + 0x0f);
284 outb(dev->id[c][target_id].devsp, dev->ioport[c] + 0x11);
1da177e4
LT		 285 adrcnt = dev->id[c][target_id].tran_len;
286 k = dev->id[c][target_id].last_len;
287
3a38e53e
OZ		 288 outb(((unsigned char *) &k)[2], dev->ioport[c] + 0x12);
289 outb(((unsigned char *) &k)[1], dev->ioport[c] + 0x13);
290 outb(((unsigned char *) &k)[0], dev->ioport[c] + 0x14);
1da177e4 291#ifdef ED_DBGP
3a38e53e 292 printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k, inb(dev->ioport[c] + 0x14), inb(dev->ioport[c] + 0x13), inb(dev->ioport[c] + 0x12));
1da177e4
LT		 293#endif
294 /* Remap wide */
295 j = target_id;
296 if (target_id > 7) {
297 j = (j & 0x07) | 0x40;
298 }
299 /* Add direction */
300 j |= dev->id[c][target_id].dirct;
3a38e53e
OZ		 301 outb(j, dev->ioport[c] + 0x15);
302 outb(0x80, dev->ioport[c] + 0x16);
1da177e4
LT		 303
304 /* enable 32 bit fifo transfer */
305 if (dev->dev_id == ATP885_DEVID) {
306 tmpcip = dev->pciport[c] + 1;
307 i=inb(tmpcip) & 0xf3;
308 //j=workreq->cmnd[0];
309 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
310 i |= 0x0c;
311 }
312 outb(i,tmpcip);
313 } else if ((dev->dev_id == ATP880_DEVID1) ||
314 (dev->dev_id == ATP880_DEVID2) ) {
1da177e4 315 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
3a38e53e 316 outb((unsigned char) ((inb(dev->ioport[c] - 0x05) & 0x3f) | 0xc0), dev->ioport[c] - 0x05);///minus 0x05???
1da177e4 317 } else {
3a38e53e 318 outb((unsigned char) (inb(dev->ioport[c] - 0x05) & 0x3f), dev->ioport[c] - 0x05);///minus 0x05???
1da177e4
LT		 319 }
320 } else {
1da177e4 321 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
3a38e53e 322 outb((unsigned char) ((inb(dev->ioport[c] + 0x3a) & 0xf3) | 0x08), dev->ioport[c] + 0x3a);
1da177e4 323 } else {
3a38e53e 324 outb((unsigned char) (inb(dev->ioport[c] + 0x3a) & 0xf3), dev->ioport[c] + 0x3a);
1da177e4
LT		 325 }
326 }
1da177e4
LT		 327 j = 0;
328 id = 1;
329 id = id << target_id;
330 /*
331 * Is this a wide device
332 */
333 if ((id & dev->wide_id[c]) != 0) {
334 j |= 0x01;
335 }
3a38e53e
OZ		 336 outb(j, dev->ioport[c] + 0x1b);
337 while ((inb(dev->ioport[c] + 0x1b) & 0x01) != j) {
338 outb(j,dev->ioport[c] + 0x1b);
1da177e4
LT		 339 }
340 if (dev->id[c][target_id].last_len == 0) {
3a38e53e 341 outb(0x08, dev->ioport[c] + 0x18);
1da177e4
LT		 342 dev->in_int[c] = 0;
343#ifdef ED_DBGP
344 printk("dev->id[c][target_id].last_len = 0\n");
345#endif
346 goto handled;
347 }
348#ifdef ED_DBGP
349 printk("target_id = %d adrcnt = %d\n",target_id,adrcnt);
350#endif
351 prd = dev->id[c][target_id].prd_pos;
352 while (adrcnt != 0) {
353 id = ((unsigned short int *)prd)[2];
354 if (id == 0) {
355 k = 0x10000;
356 } else {
357 k = id;
358 }
359 if (k > adrcnt) {
360 ((unsigned short int *)prd)[2] = (unsigned short int)
361 (k - adrcnt);
362 ((unsigned long *)prd)[0] += adrcnt;
363 adrcnt = 0;
364 dev->id[c][target_id].prd_pos = prd;
365 } else {
366 adrcnt -= k;
367 dev->id[c][target_id].prdaddr += 0x08;
368 prd += 0x08;
369 if (adrcnt == 0) {
370 dev->id[c][target_id].prd_pos = prd;
371 }
372 }
373 }
374 tmpcip = dev->pciport[c] + 0x04;
375 outl(dev->id[c][target_id].prdaddr, tmpcip);
376#ifdef ED_DBGP
377 printk("dev->id[%d][%d].prdaddr 0x%8x\n", c, target_id, dev->id[c][target_id].prdaddr);
378#endif
379 if (dev->dev_id == ATP885_DEVID) {
380 tmpcip -= 0x04;
381 } else {
382 tmpcip -= 0x02;
383 outb(0x06, tmpcip);
384 outb(0x00, tmpcip);
385 tmpcip -= 0x02;
386 }
1da177e4
LT		 387 /*
388 * Check transfer direction
389 */
390 if (dev->id[c][target_id].dirct != 0) {
3a38e53e 391 outb(0x08, dev->ioport[c] + 0x18);
1da177e4
LT		 392 outb(0x01, tmpcip);
393 dev->in_int[c] = 0;
394#ifdef ED_DBGP
395 printk("status 0x80 return dirct != 0\n");
396#endif
397 goto handled;
398 }
3a38e53e 399 outb(0x08, dev->ioport[c] + 0x18);
1da177e4
LT		 400 outb(0x09, tmpcip);
401 dev->in_int[c] = 0;
402#ifdef ED_DBGP
403 printk("status 0x80 return dirct = 0\n");
404#endif
405 goto handled;
406 }
407
408 /*
409 * Current scsi request on this target
410 */
411
412 workreq = dev->id[c][target_id].curr_req;
413
414 if (i == 0x42) {
415 if ((dev->last_cmd[c] & 0xf0) != 0x40)
416 {
417 dev->last_cmd[c] = 0xff;
418 }
419 errstus = 0x02;
420 workreq->result = errstus;
421 goto go_42;
422 }
423 if (i == 0x16) {
424 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
425 dev->last_cmd[c] = 0xff;
426 }
427 errstus = 0;
3a38e53e 428 errstus = inb(dev->ioport[c] + 0x0f);
1da177e4
LT		 429 if (((dev->r1f[c][target_id] & 0x10) != 0)&&(dev->dev_id==ATP885_DEVID)) {
430 printk(KERN_WARNING "AEC67162 CRC ERROR !\n");
431 errstus = 0x02;
432 }
433 workreq->result = errstus;
434go_42:
435 if (dev->dev_id == ATP885_DEVID) {
436 j = inb(dev->baseport + 0x29) | 0x01;
437 outb(j, dev->baseport + 0x29);
438 }
439 /*
440 * Complete the command
441 */
fe7ed98f
BH		 442 scsi_dma_unmap(workreq);
443
1da177e4
LT		 444 spin_lock_irqsave(dev->host->host_lock, flags);
445 (*workreq->scsi_done) (workreq);
446#ifdef ED_DBGP
447 printk("workreq->scsi_done\n");
448#endif
449 /*
450 * Clear it off the queue
451 */
452 dev->id[c][target_id].curr_req = NULL;
453 dev->working[c]--;
454 spin_unlock_irqrestore(dev->host->host_lock, flags);
455 /*
456 * Take it back wide
457 */
458 if (dev->wide_id[c] != 0) {
3a38e53e
OZ		 459 outb(0x01, dev->ioport[c] + 0x1b);
460 while ((inb(dev->ioport[c] + 0x1b) & 0x01) != 0x01) {
461 outb(0x01, dev->ioport[c] + 0x1b);
1da177e4
LT		 462 }
463 }
464 /*
465 * If there is stuff to send and nothing going then send it
466 */
467 spin_lock_irqsave(dev->host->host_lock, flags);
468 if (((dev->last_cmd[c] != 0xff) || (dev->quhd[c] != dev->quend[c])) &&
469 (dev->in_snd[c] == 0)) {
470#ifdef ED_DBGP
471 printk("Call sent_s870(scsi_done)\n");
472#endif
473 send_s870(dev,c);
474 }
475 spin_unlock_irqrestore(dev->host->host_lock, flags);
476 dev->in_int[c] = 0;
477 goto handled;
478 }
479 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
480 dev->last_cmd[c] = 0xff;
481 }
482 if (i == 0x4f) {
483 i = 0x89;
484 }
485 i &= 0x0f;
486 if (i == 0x09) {
487 tmpcip += 4;
488 outl(dev->id[c][target_id].prdaddr, tmpcip);
489 tmpcip = tmpcip - 2;
490 outb(0x06, tmpcip);
491 outb(0x00, tmpcip);
492 tmpcip = tmpcip - 2;
3a38e53e 493 outb(0x41, dev->ioport[c] + 0x10);
1da177e4 494 if (dev->dev_id == ATP885_DEVID) {
1da177e4 495 k = dev->id[c][target_id].last_len;
3a38e53e
OZ		 496 outb((unsigned char) (((unsigned char *) (&k))[2]), dev->ioport[c] + 0x12);
497 outb((unsigned char) (((unsigned char *) (&k))[1]), dev->ioport[c] + 0x13);
498 outb((unsigned char) (((unsigned char *) (&k))[0]), dev->ioport[c] + 0x14);
1da177e4 499 dev->id[c][target_id].dirct = 0x00;
1da177e4
LT		 500 } else {
501 dev->id[c][target_id].dirct = 0x00;
1da177e4 502 }
3a38e53e 503 outb(0x08, dev->ioport[c] + 0x18);
1da177e4
LT		 504 outb(0x09, tmpcip);
505 dev->in_int[c] = 0;
506 goto handled;
507 }
508 if (i == 0x08) {
509 tmpcip += 4;
510 outl(dev->id[c][target_id].prdaddr, tmpcip);
511 tmpcip = tmpcip - 2;
512 outb(0x06, tmpcip);
513 outb(0x00, tmpcip);
514 tmpcip = tmpcip - 2;
3a38e53e 515 outb(0x41, dev->ioport[c] + 0x10);
1da177e4 516 if (dev->dev_id == ATP885_DEVID) {
1da177e4 517 k = dev->id[c][target_id].last_len;
3a38e53e
OZ		 518 outb((unsigned char) (((unsigned char *) (&k))[2]), dev->ioport[c] + 0x12);
519 outb((unsigned char) (((unsigned char *) (&k))[1]), dev->ioport[c] + 0x13);
520 outb((unsigned char) (((unsigned char *) (&k))[0]), dev->ioport[c] + 0x14);
1da177e4 521 }
3a38e53e 522 outb((unsigned char) (inb(dev->ioport[c] + 0x15) | 0x20), dev->ioport[c] + 0x15);
1da177e4 523 dev->id[c][target_id].dirct = 0x20;
3a38e53e 524 outb(0x08, dev->ioport[c] + 0x18);
1da177e4
LT		 525 outb(0x01, tmpcip);
526 dev->in_int[c] = 0;
527 goto handled;
528 }
1da177e4 529 if (i == 0x0a) {
3a38e53e 530 outb(0x30, dev->ioport[c] + 0x10);
1da177e4 531 } else {
3a38e53e 532 outb(0x46, dev->ioport[c] + 0x10);
1da177e4
LT		 533 }
534 dev->id[c][target_id].dirct = 0x00;
3a38e53e
OZ		 535 outb(0x00, dev->ioport[c] + 0x12);
536 outb(0x00, dev->ioport[c] + 0x13);
537 outb(0x00, dev->ioport[c] + 0x14);
538 outb(0x08, dev->ioport[c] + 0x18);
1da177e4
LT		 539 dev->in_int[c] = 0;
540 goto handled;
541 } else {
3a38e53e 542// inb(dev->ioport[c] + 0x17);
1da177e4
LT		 543// dev->working[c] = 0;
544 dev->in_int[c] = 0;
545 goto handled;
546 }
547
548handled:
549#ifdef ED_DBGP
550 printk("atp870u_intr_handle exit\n");
551#endif
552 return IRQ_HANDLED;
553}
554/**
555 * atp870u_queuecommand - Queue SCSI command
556 * @req_p: request block
557 * @done: completion function
558 *
559 * Queue a command to the ATP queue. Called with the host lock held.
560 */
f281233d 561static int atp870u_queuecommand_lck(struct scsi_cmnd *req_p,
1da177e4
LT		 562 void (*done) (struct scsi_cmnd *))
563{
564 unsigned char c;
3b836464 565 unsigned int m;
1da177e4
LT		 566 struct atp_unit *dev;
567 struct Scsi_Host *host;
568
422c0d61 569 c = scmd_channel(req_p);
1da177e4 570 req_p->sense_buffer[0]=0;
fe7ed98f 571 scsi_set_resid(req_p, 0);
422c0d61 572 if (scmd_channel(req_p) > 1) {
1da177e4
LT		 573 req_p->result = 0x00040000;
574 done(req_p);
575#ifdef ED_DBGP
576 printk("atp870u_queuecommand : req_p->device->channel > 1\n");
577#endif
578 return 0;
579 }
580
581 host = req_p->device->host;
582 dev = (struct atp_unit *)&host->hostdata;
583
584
585
586 m = 1;
422c0d61 587 m = m << scmd_id(req_p);
1da177e4
LT		 588
589 /*
590 * Fake a timeout for missing targets
591 */
592
593 if ((m & dev->active_id[c]) == 0) {
594 req_p->result = 0x00040000;
595 done(req_p);
596 return 0;
597 }
598
599 if (done) {
600 req_p->scsi_done = done;
601 } else {
602#ifdef ED_DBGP
603 printk( "atp870u_queuecommand: done can't be NULL\n");
604#endif
605 req_p->result = 0;
606 done(req_p);
607 return 0;
608 }
609
610 /*
611 * Count new command
612 */
613 dev->quend[c]++;
614 if (dev->quend[c] >= qcnt) {
615 dev->quend[c] = 0;
616 }
617
618 /*
619 * Check queue state
620 */
621 if (dev->quhd[c] == dev->quend[c]) {
622 if (dev->quend[c] == 0) {
623 dev->quend[c] = qcnt;
624 }
625#ifdef ED_DBGP
626 printk("atp870u_queuecommand : dev->quhd[c] == dev->quend[c]\n");
627#endif
628 dev->quend[c]--;
629 req_p->result = 0x00020000;
630 done(req_p);
631 return 0;
632 }
633 dev->quereq[c][dev->quend[c]] = req_p;
1da177e4 634#ifdef ED_DBGP
3b836464 635 printk("dev->ioport[c] = %x inb(dev->ioport[c] + 0x1c) = %x dev->in_int[%d] = %d dev->in_snd[%d] = %d\n",dev->ioport[c],inb(dev->ioport[c] + 0x1c),c,dev->in_int[c],c,dev->in_snd[c]);
1da177e4 636#endif
3b836464 637 if ((inb(dev->ioport[c] + 0x1c) == 0) && (dev->in_int[c] == 0) && (dev->in_snd[c] == 0)) {
1da177e4
LT		 638#ifdef ED_DBGP
639 printk("Call sent_s870(atp870u_queuecommand)\n");
640#endif
641 send_s870(dev,c);
642 }
643#ifdef ED_DBGP
644 printk("atp870u_queuecommand : exit\n");
645#endif
646 return 0;
647}
648
f281233d
JG		 649static DEF_SCSI_QCMD(atp870u_queuecommand)
650
1da177e4
LT		 651/**
652 * send_s870 - send a command to the controller
653 * @host: host
654 *
655 * On entry there is work queued to be done. We move some of that work to the
656 * controller itself.
657 *
658 * Caller holds the host lock.
659 */
660static void send_s870(struct atp_unit *dev,unsigned char c)
661{
1da177e4
LT		 662 struct scsi_cmnd *workreq;
663 unsigned int i;//,k;
664 unsigned char j, target_id;
665 unsigned char *prd;
666 unsigned short int tmpcip, w;
667 unsigned long l, bttl = 0;
1da177e4
LT		 668 unsigned long sg_count;
669
670 if (dev->in_snd[c] != 0) {
671#ifdef ED_DBGP
672 printk("cmnd in_snd\n");
673#endif
674 return;
675 }
676#ifdef ED_DBGP
677 printk("Sent_s870 enter\n");
678#endif
679 dev->in_snd[c] = 1;
680 if ((dev->last_cmd[c] != 0xff) && ((dev->last_cmd[c] & 0x40) != 0)) {
681 dev->last_cmd[c] &= 0x0f;
682 workreq = dev->id[c][dev->last_cmd[c]].curr_req;
683 if (workreq != NULL) { /* check NULL pointer */
684 goto cmd_subp;
685 }
686 dev->last_cmd[c] = 0xff;
687 if (dev->quhd[c] == dev->quend[c]) {
688 dev->in_snd[c] = 0;
689 return ;
690 }
691 }
692 if ((dev->last_cmd[c] != 0xff) && (dev->working[c] != 0)) {
693 dev->in_snd[c] = 0;
694 return ;
695 }
696 dev->working[c]++;
697 j = dev->quhd[c];
698 dev->quhd[c]++;
699 if (dev->quhd[c] >= qcnt) {
700 dev->quhd[c] = 0;
701 }
702 workreq = dev->quereq[c][dev->quhd[c]];
9bcf0910 703 if (dev->id[c][scmd_id(workreq)].curr_req == NULL) {
422c0d61
JG		 704 dev->id[c][scmd_id(workreq)].curr_req = workreq;
705 dev->last_cmd[c] = scmd_id(workreq);
1da177e4
LT		 706 goto cmd_subp;
707 }
708 dev->quhd[c] = j;
709 dev->working[c]--;
710 dev->in_snd[c] = 0;
711 return;
712cmd_subp:
3b836464 713 if ((inb(dev->ioport[c] + 0x1f) & 0xb0) != 0) {
1da177e4
LT		 714 goto abortsnd;
715 }
3b836464 716 if (inb(dev->ioport[c] + 0x1c) == 0) {
1da177e4
LT		 717 goto oktosend;
718 }
719abortsnd:
720#ifdef ED_DBGP
721 printk("Abort to Send\n");
722#endif
723 dev->last_cmd[c] |= 0x40;
724 dev->in_snd[c] = 0;
725 return;
726oktosend:
727#ifdef ED_DBGP
728 printk("OK to Send\n");
422c0d61 729 scmd_printk(KERN_DEBUG, workreq, "CDB");
1da177e4
LT		 730 for(i=0;i<workreq->cmd_len;i++) {
731 printk(" %x",workreq->cmnd[i]);
732 }
422c0d61 733 printk("\n");
1da177e4 734#endif
fe7ed98f
BH		 735 l = scsi_bufflen(workreq);
736
1da177e4
LT		 737 if (dev->dev_id == ATP885_DEVID) {
738 j = inb(dev->baseport + 0x29) & 0xfe;
739 outb(j, dev->baseport + 0x29);
422c0d61 740 dev->r1f[c][scmd_id(workreq)] = 0;
1da177e4
LT		 741 }
742
743 if (workreq->cmnd[0] == READ_CAPACITY) {
fe7ed98f
BH		 744 if (l > 8)
745 l = 8;
1da177e4
LT		 746 }
747 if (workreq->cmnd[0] == 0x00) {
fe7ed98f 748 l = 0;
1da177e4
LT		 749 }
750
1da177e4 751 j = 0;
422c0d61 752 target_id = scmd_id(workreq);
1da177e4
LT		 753
754 /*
755 * Wide ?
756 */
757 w = 1;
758 w = w << target_id;
759 if ((w & dev->wide_id[c]) != 0) {
760 j |= 0x01;
761 }
3b836464
OZ		 762 outb(j, dev->ioport[c] + 0x1b);
763 while ((inb(dev->ioport[c] + 0x1b) & 0x01) != j) {
764 outb(j,dev->ioport[c] + 0x1b);
1da177e4
LT		 765#ifdef ED_DBGP
766 printk("send_s870 while loop 1\n");
767#endif
768 }
769 /*
770 * Write the command
771 */
772
3b836464
OZ		 773 outb(workreq->cmd_len, dev->ioport[c] + 0x00);
774 outb(0x2c, dev->ioport[c] + 0x01);
1da177e4 775 if (dev->dev_id == ATP885_DEVID) {
3b836464 776 outb(0x7f, dev->ioport[c] + 0x02);
1da177e4 777 } else {
3b836464 778 outb(0xcf, dev->ioport[c] + 0x02);
1da177e4
LT		 779 }
780 for (i = 0; i < workreq->cmd_len; i++) {
3b836464 781 outb(workreq->cmnd[i], dev->ioport[c] + 0x03 + i);
1da177e4 782 }
3b836464 783 outb(workreq->device->lun, dev->ioport[c] + 0x0f);
1da177e4
LT		 784 /*
785 * Write the target
786 */
3b836464 787 outb(dev->id[c][target_id].devsp, dev->ioport[c] + 0x11);
1da177e4
LT		 788#ifdef ED_DBGP
789 printk("dev->id[%d][%d].devsp = %2x\n",c,target_id,dev->id[c][target_id].devsp);
790#endif
fe7ed98f
BH		 791
792 sg_count = scsi_dma_map(workreq);
1da177e4
LT		 793 /*
794 * Write transfer size
795 */
3b836464
OZ		 796 outb((unsigned char) (((unsigned char *) (&l))[2]), dev->ioport[c] + 0x12);
797 outb((unsigned char) (((unsigned char *) (&l))[1]), dev->ioport[c] + 0x13);
798 outb((unsigned char) (((unsigned char *) (&l))[0]), dev->ioport[c] + 0x14);
1da177e4
LT		 799 j = target_id;
800 dev->id[c][j].last_len = l;
801 dev->id[c][j].tran_len = 0;
802#ifdef ED_DBGP
803 printk("dev->id[%2d][%2d].last_len = %d\n",c,j,dev->id[c][j].last_len);
804#endif
805 /*
806 * Flip the wide bits
807 */
808 if ((j & 0x08) != 0) {
809 j = (j & 0x07) | 0x40;
810 }
811 /*
812 * Check transfer direction
813 */
814 if (workreq->sc_data_direction == DMA_TO_DEVICE) {
3b836464 815 outb((unsigned char) (j | 0x20), dev->ioport[c] + 0x15);
1da177e4 816 } else {
3b836464 817 outb(j, dev->ioport[c] + 0x15);
1da177e4 818 }
3b836464
OZ		 819 outb((unsigned char) (inb(dev->ioport[c] + 0x16) | 0x80), dev->ioport[c] + 0x16);
820 outb(0x80, dev->ioport[c] + 0x16);
1da177e4
LT		 821 dev->id[c][target_id].dirct = 0;
822 if (l == 0) {
3b836464 823 if (inb(dev->ioport[c] + 0x1c) == 0) {
1da177e4
LT		 824#ifdef ED_DBGP
825 printk("change SCSI_CMD_REG 0x08\n");
826#endif
3b836464 827 outb(0x08, dev->ioport[c] + 0x18);
1da177e4
LT		 828 } else {
829 dev->last_cmd[c] |= 0x40;
830 }
831 dev->in_snd[c] = 0;
832 return;
833 }
834 tmpcip = dev->pciport[c];
835 prd = dev->id[c][target_id].prd_table;
836 dev->id[c][target_id].prd_pos = prd;
837
838 /*
839 * Now write the request list. Either as scatter/gather or as
840 * a linear chain.
841 */
842
fe7ed98f
BH		 843 if (l) {
844 struct scatterlist *sgpnt;
1da177e4 845 i = 0;
fe7ed98f
BH		 846 scsi_for_each_sg(workreq, sgpnt, sg_count, j) {
847 bttl = sg_dma_address(sgpnt);
848 l=sg_dma_len(sgpnt);
1da177e4 849#ifdef ED_DBGP
fe7ed98f 850 printk("1. bttl %x, l %x\n",bttl, l);
1da177e4 851#endif
fe7ed98f 852 while (l > 0x10000) {
1da177e4
LT		 853 (((u16 *) (prd))[i + 3]) = 0x0000;
854 (((u16 *) (prd))[i + 2]) = 0x0000;
855 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
856 l -= 0x10000;
857 bttl += 0x10000;
858 i += 0x04;
859 }
860 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
861 (((u16 *) (prd))[i + 2]) = cpu_to_le16(l);
862 (((u16 *) (prd))[i + 3]) = 0;
863 i += 0x04;
864 }
865 (((u16 *) (prd))[i - 1]) = cpu_to_le16(0x8000);
866#ifdef ED_DBGP
867 printk("prd %4x %4x %4x %4x\n",(((unsigned short int *)prd)[0]),(((unsigned short int *)prd)[1]),(((unsigned short int *)prd)[2]),(((unsigned short int *)prd)[3]));
868 printk("2. bttl %x, l %x\n",bttl, l);
869#endif
1da177e4
LT		 870 }
871 tmpcip += 4;
872#ifdef ED_DBGP
873 printk("send_s870: prdaddr_2 0x%8x tmpcip %x target_id %d\n", dev->id[c][target_id].prdaddr,tmpcip,target_id);
874#endif
b5683557 875 dev->id[c][target_id].prdaddr = dev->id[c][target_id].prd_bus;
1da177e4
LT		 876 outl(dev->id[c][target_id].prdaddr, tmpcip);
877 tmpcip = tmpcip - 2;
878 outb(0x06, tmpcip);
879 outb(0x00, tmpcip);
880 if (dev->dev_id == ATP885_DEVID) {
881 tmpcip--;
882 j=inb(tmpcip) & 0xf3;
883 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) ||
884 (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
885 j |= 0x0c;
886 }
887 outb(j,tmpcip);
888 tmpcip--;
889 } else if ((dev->dev_id == ATP880_DEVID1) ||
890 (dev->dev_id == ATP880_DEVID2)) {
891 tmpcip =tmpcip -2;
1da177e4 892 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
3b836464 893 outb((unsigned char) ((inb(dev->ioport[c] - 0x05) & 0x3f) | 0xc0), dev->ioport[c] - 0x05);
1da177e4 894 } else {
3b836464 895 outb((unsigned char) (inb(dev->ioport[c] - 0x05) & 0x3f), dev->ioport[c] - 0x05);
1da177e4
LT		 896 }
897 } else {
898 tmpcip =tmpcip -2;
1da177e4 899 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
3b836464 900 outb((inb(dev->ioport[c] + 0x3a) & 0xf3) | 0x08, dev->ioport[c] + 0x3a);
1da177e4 901 } else {
3b836464 902 outb(inb(dev->ioport[c] + 0x3a) & 0xf3, dev->ioport[c] + 0x3a);
1da177e4
LT		 903 }
904 }
1da177e4
LT		 905
906 if(workreq->sc_data_direction == DMA_TO_DEVICE) {
907 dev->id[c][target_id].dirct = 0x20;
3b836464
OZ		 908 if (inb(dev->ioport[c] + 0x1c) == 0) {
909 outb(0x08, dev->ioport[c] + 0x18);
1da177e4
LT		 910 outb(0x01, tmpcip);
911#ifdef ED_DBGP
912 printk( "start DMA(to target)\n");
913#endif
914 } else {
915 dev->last_cmd[c] |= 0x40;
916 }
917 dev->in_snd[c] = 0;
918 return;
919 }
3b836464
OZ		 920 if (inb(dev->ioport[c] + 0x1c) == 0) {
921 outb(0x08, dev->ioport[c] + 0x18);
1da177e4
LT		 922 outb(0x09, tmpcip);
923#ifdef ED_DBGP
924 printk( "start DMA(to host)\n");
925#endif
926 } else {
927 dev->last_cmd[c] |= 0x40;
928 }
929 dev->in_snd[c] = 0;
930 return;
931
932}
933
934static unsigned char fun_scam(struct atp_unit *dev, unsigned short int *val)
935{
1da177e4
LT		 936 unsigned short int i, k;
937 unsigned char j;
938
1940ed62 939 outw(*val, dev->ioport[0] + 0x1c);
1da177e4
LT		 940FUN_D7:
941 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
1940ed62 942 k = inw(dev->ioport[0] + 0x1c);
1da177e4
LT		 943 j = (unsigned char) (k >> 8);
944 if ((k & 0x8000) != 0) { /* DB7 all release? */
945 goto FUN_D7;
946 }
947 }
948 *val |= 0x4000; /* assert DB6 */
1940ed62 949 outw(*val, dev->ioport[0] + 0x1c);
1da177e4 950 *val &= 0xdfff; /* assert DB5 */
1940ed62 951 outw(*val, dev->ioport[0] + 0x1c);
1da177e4
LT		 952FUN_D5:
953 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
1940ed62 954 if ((inw(dev->ioport[0] + 0x1c) & 0x2000) != 0) { /* DB5 all release? */
1da177e4
LT		 955 goto FUN_D5;
956 }
957 }
958 *val |= 0x8000; /* no DB4-0, assert DB7 */
959 *val &= 0xe0ff;
1940ed62 960 outw(*val, dev->ioport[0] + 0x1c);
1da177e4 961 *val &= 0xbfff; /* release DB6 */
1940ed62 962 outw(*val, dev->ioport[0] + 0x1c);
1da177e4
LT		 963FUN_D6:
964 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
1940ed62 965 if ((inw(dev->ioport[0] + 0x1c) & 0x4000) != 0) { /* DB6 all release? */
1da177e4
LT		 966 goto FUN_D6;
967 }
968 }
969
970 return j;
971}
972
973static void tscam(struct Scsi_Host *host)
974{
975
1da177e4
LT		 976 unsigned char i, j, k;
977 unsigned long n;
978 unsigned short int m, assignid_map, val;
979 unsigned char mbuf[33], quintet[2];
980 struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
981 static unsigned char g2q_tab[8] = {
982 0x38, 0x31, 0x32, 0x2b, 0x34, 0x2d, 0x2e, 0x27
983 };
984
985/* I can't believe we need this before we've even done anything. Remove it
986 * and see if anyone bitches.
987 for (i = 0; i < 0x10; i++) {
988 udelay(0xffff);
989 }
990 */
991
1940ed62
OZ		 992 outb(0x08, dev->ioport[0] + 1);
993 outb(0x7f, dev->ioport[0] + 2);
994 outb(0x20, dev->ioport[0] + 0x11);
1da177e4
LT		 995
996 if ((dev->scam_on & 0x40) == 0) {
997 return;
998 }
999 m = 1;
1000 m <<= dev->host_id[0];
1001 j = 16;
1002 if (dev->chip_ver < 4) {
1003 m |= 0xff00;
1004 j = 8;
1005 }
1006 assignid_map = m;
1940ed62
OZ		 1007 outb(0x02, dev->ioport[0] + 0x02); /* 2*2=4ms,3EH 2/32*3E=3.9ms */
1008 outb(0, dev->ioport[0] + 0x03);
1009 outb(0, dev->ioport[0] + 0x04);
1010 outb(0, dev->ioport[0] + 0x05);
1011 outb(0, dev->ioport[0] + 0x06);
1012 outb(0, dev->ioport[0] + 0x07);
1013 outb(0, dev->ioport[0] + 0x08);
1da177e4
LT		 1014
1015 for (i = 0; i < j; i++) {
1016 m = 1;
1017 m = m << i;
1018 if ((m & assignid_map) != 0) {
1019 continue;
1020 }
1940ed62
OZ		 1021 outb(0, dev->ioport[0] + 0x0f);
1022 outb(0, dev->ioport[0] + 0x12);
1023 outb(0, dev->ioport[0] + 0x13);
1024 outb(0, dev->ioport[0] + 0x14);
1da177e4
LT		 1025 if (i > 7) {
1026 k = (i & 0x07) | 0x40;
1027 } else {
1028 k = i;
1029 }
1940ed62 1030 outb(k, dev->ioport[0] + 0x15);
1da177e4 1031 if (dev->chip_ver == 4) {
1940ed62 1032 outb(0x01, dev->ioport[0] + 0x1b);
1da177e4 1033 } else {
1940ed62 1034 outb(0x00, dev->ioport[0] + 0x1b);
1da177e4
LT		 1035 }
1036wait_rdyok:
1940ed62 1037 outb(0x09, dev->ioport[0] + 0x18);
1da177e4 1038
1940ed62 1039 while ((inb(dev->ioport[0] + 0x1f) & 0x80) == 0x00)
1da177e4 1040 cpu_relax();
1940ed62 1041 k = inb(dev->ioport[0] + 0x17);
1da177e4
LT		 1042 if (k != 0x16) {
1043 if ((k == 0x85) || (k == 0x42)) {
1044 continue;
1045 }
1940ed62 1046 outb(0x41, dev->ioport[0] + 0x10);
1da177e4
LT		 1047 goto wait_rdyok;
1048 }
1049 assignid_map |= m;
1050
1051 }
1940ed62
OZ		 1052 outb(0x7f, dev->ioport[0] + 0x02);
1053 outb(0x02, dev->ioport[0] + 0x1b);
1da177e4
LT		 1054
1055 outb(0, 0x80);
1056
1057 val = 0x0080; /* bsy */
1940ed62 1058 outw(val, dev->ioport[0] + 0x1c);
1da177e4 1059 val |= 0x0040; /* sel */
1940ed62 1060 outw(val, dev->ioport[0] + 0x1c);
1da177e4 1061 val |= 0x0004; /* msg */
1940ed62 1062 outw(val, dev->ioport[0] + 0x1c);
1da177e4
LT		 1063 inb(0x80); /* 2 deskew delay(45ns*2=90ns) */
1064 val &= 0x007f; /* no bsy */
1940ed62 1065 outw(val, dev->ioport[0] + 0x1c);
1da177e4
LT		 1066 mdelay(128);
1067 val &= 0x00fb; /* after 1ms no msg */
1940ed62 1068 outw(val, dev->ioport[0] + 0x1c);
1da177e4 1069wait_nomsg:
1940ed62 1070 if ((inb(dev->ioport[0] + 0x1c) & 0x04) != 0) {
1da177e4
LT		 1071 goto wait_nomsg;
1072 }
1073 outb(1, 0x80);
1074 udelay(100);
1075 for (n = 0; n < 0x30000; n++) {
1940ed62 1076 if ((inb(dev->ioport[0] + 0x1c) & 0x80) != 0) { /* bsy ? */
1da177e4
LT		 1077 goto wait_io;
1078 }
1079 }
1080 goto TCM_SYNC;
1081wait_io:
1082 for (n = 0; n < 0x30000; n++) {
1940ed62 1083 if ((inb(dev->ioport[0] + 0x1c) & 0x81) == 0x0081) {
1da177e4
LT		 1084 goto wait_io1;
1085 }
1086 }
1087 goto TCM_SYNC;
1088wait_io1:
1089 inb(0x80);
1090 val |= 0x8003; /* io,cd,db7 */
1940ed62 1091 outw(val, dev->ioport[0] + 0x1c);
1da177e4
LT		 1092 inb(0x80);
1093 val &= 0x00bf; /* no sel */
1940ed62 1094 outw(val, dev->ioport[0] + 0x1c);
1da177e4
LT		 1095 outb(2, 0x80);
1096TCM_SYNC:
0f6d93aa
MM		 1097 /*
1098 * The funny division into multiple delays is to accomodate
1099 * arches like ARM where udelay() multiplies its argument by
1100 * a large number to initialize a loop counter. To avoid
1101 * overflow, the maximum supported udelay is 2000 microseconds.
1102 *
1103 * XXX it would be more polite to find a way to use msleep()
1104 */
1105 mdelay(2);
1106 udelay(48);
1940ed62
OZ		 1107 if ((inb(dev->ioport[0] + 0x1c) & 0x80) == 0x00) { /* bsy ? */
1108 outw(0, dev->ioport[0] + 0x1c);
1109 outb(0, dev->ioport[0] + 0x1b);
1110 outb(0, dev->ioport[0] + 0x15);
1111 outb(0x09, dev->ioport[0] + 0x18);
1112 while ((inb(dev->ioport[0] + 0x1f) & 0x80) == 0)
1da177e4 1113 cpu_relax();
1940ed62 1114 inb(dev->ioport[0] + 0x17);
1da177e4
LT		 1115 return;
1116 }
1117 val &= 0x00ff; /* synchronization */
1118 val |= 0x3f00;
1119 fun_scam(dev, &val);
1120 outb(3, 0x80);
1121 val &= 0x00ff; /* isolation */
1122 val |= 0x2000;
1123 fun_scam(dev, &val);
1124 outb(4, 0x80);
1125 i = 8;
1126 j = 0;
1127TCM_ID:
1940ed62 1128 if ((inw(dev->ioport[0] + 0x1c) & 0x2000) == 0) {
1da177e4
LT		 1129 goto TCM_ID;
1130 }
1131 outb(5, 0x80);
1132 val &= 0x00ff; /* get ID_STRING */
1133 val |= 0x2000;
1134 k = fun_scam(dev, &val);
1135 if ((k & 0x03) == 0) {
1136 goto TCM_5;
1137 }
1138 mbuf[j] <<= 0x01;
1139 mbuf[j] &= 0xfe;
1140 if ((k & 0x02) != 0) {
1141 mbuf[j] |= 0x01;
1142 }
1143 i--;
1144 if (i > 0) {
1145 goto TCM_ID;
1146 }
1147 j++;
1148 i = 8;
1149 goto TCM_ID;
1150
1151TCM_5: /* isolation complete.. */
1152/* mbuf[32]=0;
1153 printk(" \n%x %x %x %s\n ",assignid_map,mbuf[0],mbuf[1],&mbuf[2]); */
1154 i = 15;
1155 j = mbuf[0];
25985edc 1156 if ((j & 0x20) != 0) { /* bit5=1:ID up to 7 */
1da177e4
LT		 1157 i = 7;
1158 }
1159 if ((j & 0x06) == 0) { /* IDvalid? */
1160 goto G2Q5;
1161 }
1162 k = mbuf[1];
1163small_id:
1164 m = 1;
1165 m <<= k;
1166 if ((m & assignid_map) == 0) {
1167 goto G2Q_QUIN;
1168 }
1169 if (k > 0) {
1170 k--;
1171 goto small_id;
1172 }
1173G2Q5: /* srch from max acceptable ID# */
1174 k = i; /* max acceptable ID# */
1175G2Q_LP:
1176 m = 1;
1177 m <<= k;
1178 if ((m & assignid_map) == 0) {
1179 goto G2Q_QUIN;
1180 }
1181 if (k > 0) {
1182 k--;
1183 goto G2Q_LP;
1184 }
1185G2Q_QUIN: /* k=binID#, */
1186 assignid_map |= m;
1187 if (k < 8) {
1188 quintet[0] = 0x38; /* 1st dft ID<8 */
1189 } else {
1190 quintet[0] = 0x31; /* 1st ID>=8 */
1191 }
1192 k &= 0x07;
1193 quintet[1] = g2q_tab[k];
1194
1195 val &= 0x00ff; /* AssignID 1stQuintet,AH=001xxxxx */
1196 m = quintet[0] << 8;
1197 val |= m;
1198 fun_scam(dev, &val);
1199 val &= 0x00ff; /* AssignID 2ndQuintet,AH=001xxxxx */
1200 m = quintet[1] << 8;
1201 val |= m;
1202 fun_scam(dev, &val);
1203
1204 goto TCM_SYNC;
1205
1206}
1207
1208static void is870(struct atp_unit *dev, unsigned int wkport)
1209{
1da177e4
LT		 1210 unsigned char i, j, k, rmb, n;
1211 unsigned short int m;
1212 static unsigned char mbuf[512];
1213 static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
1214 static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
1215 static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1216 static unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0c, 0x0e };
1217 static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x0c, 0x07 };
1218 static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
1219
ea41ed60 1220 outb((unsigned char) (inb(wkport + 0x3a) | 0x10), wkport + 0x3a);
1da177e4
LT		 1221
1222 for (i = 0; i < 16; i++) {
1223 if ((dev->chip_ver != 4) && (i > 7)) {
1224 break;
1225 }
1226 m = 1;
1227 m = m << i;
1228 if ((m & dev->active_id[0]) != 0) {
1229 continue;
1230 }
1231 if (i == dev->host_id[0]) {
1232 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[0]);
1233 continue;
1234 }
1da177e4 1235 if (dev->chip_ver == 4) {
ea41ed60 1236 outb(0x01, wkport + 0x1b);
1da177e4 1237 } else {
ea41ed60
OZ		 1238 outb(0x00, wkport + 0x1b);
1239 }
1240 outb(0x08, wkport + 1);
1241 outb(0x7f, wkport + 2);
1242 outb(satn[0], wkport + 3);
1243 outb(satn[1], wkport + 4);
1244 outb(satn[2], wkport + 5);
1245 outb(satn[3], wkport + 6);
1246 outb(satn[4], wkport + 7);
1247 outb(satn[5], wkport + 8);
1248 outb(0, wkport + 0x0f);
1249 outb(dev->id[0][i].devsp, wkport + 0x11);
1250 outb(0, wkport + 0x12);
1251 outb(satn[6], wkport + 0x13);
1252 outb(satn[7], wkport + 0x14);
1da177e4
LT		 1253 j = i;
1254 if ((j & 0x08) != 0) {
1255 j = (j & 0x07) | 0x40;
1256 }
ea41ed60
OZ		 1257 outb(j, wkport + 0x15);
1258 outb(satn[8], wkport + 0x18);
1da177e4 1259
ea41ed60 1260 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1261 cpu_relax();
1262
ea41ed60 1263 if (inb(wkport + 0x17) != 0x11 && inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 1264 continue;
1265
ea41ed60 1266 while (inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 1267 cpu_relax();
1268
1269 dev->active_id[0] |= m;
1270
ea41ed60
OZ		 1271 outb(0x30, wkport + 0x10);
1272 outb(0x00, wkport + 0x04);
1da177e4
LT		 1273
1274phase_cmd:
ea41ed60
OZ		 1275 outb(0x08, wkport + 0x18);
1276 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 1277 cpu_relax();
ea41ed60 1278 j = inb(wkport + 0x17);
1da177e4 1279 if (j != 0x16) {
ea41ed60 1280 outb(0x41, wkport + 0x10);
1da177e4
LT		 1281 goto phase_cmd;
1282 }
1283sel_ok:
ea41ed60
OZ		 1284 outb(inqd[0], wkport + 3);
1285 outb(inqd[1], wkport + 4);
1286 outb(inqd[2], wkport + 5);
1287 outb(inqd[3], wkport + 6);
1288 outb(inqd[4], wkport + 7);
1289 outb(inqd[5], wkport + 8);
1290 outb(0, wkport + 0x0f);
1291 outb(dev->id[0][i].devsp, wkport + 0x11);
1292 outb(0, wkport + 0x12);
1293 outb(inqd[6], wkport + 0x13);
1294 outb(inqd[7], wkport + 0x14);
1295 outb(inqd[8], wkport + 0x18);
1296
1297 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1298 cpu_relax();
1299
ea41ed60 1300 if (inb(wkport + 0x17) != 0x11 && inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 1301 continue;
1302
ea41ed60 1303 while (inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 1304 cpu_relax();
1305
1da177e4 1306 if (dev->chip_ver == 4)
ea41ed60 1307 outb(0x00, wkport + 0x1b);
1da177e4 1308
ea41ed60 1309 outb(0x08, wkport + 0x18);
1da177e4
LT		 1310 j = 0;
1311rd_inq_data:
ea41ed60 1312 k = inb(wkport + 0x1f);
1da177e4 1313 if ((k & 0x01) != 0) {
ea41ed60 1314 mbuf[j++] = inb(wkport + 0x19);
1da177e4
LT		 1315 goto rd_inq_data;
1316 }
1317 if ((k & 0x80) == 0) {
1318 goto rd_inq_data;
1319 }
ea41ed60 1320 j = inb(wkport + 0x17);
1da177e4
LT		 1321 if (j == 0x16) {
1322 goto inq_ok;
1323 }
ea41ed60
OZ		 1324 outb(0x46, wkport + 0x10);
1325 outb(0, wkport + 0x12);
1326 outb(0, wkport + 0x13);
1327 outb(0, wkport + 0x14);
1328 outb(0x08, wkport + 0x18);
1329
1330 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1331 cpu_relax();
1332
ea41ed60 1333 if (inb(wkport + 0x17) != 0x16) {
1da177e4
LT		 1334 goto sel_ok;
1335 }
1336inq_ok:
1337 mbuf[36] = 0;
1338 printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]);
1339 dev->id[0][i].devtype = mbuf[0];
1340 rmb = mbuf[1];
1341 n = mbuf[7];
1342 if (dev->chip_ver != 4) {
1343 goto not_wide;
1344 }
1345 if ((mbuf[7] & 0x60) == 0) {
1346 goto not_wide;
1347 }
1348 if ((dev->global_map[0] & 0x20) == 0) {
1349 goto not_wide;
1350 }
ea41ed60
OZ		 1351 outb(0x01, wkport + 0x1b);
1352 outb(satn[0], wkport + 3);
1353 outb(satn[1], wkport + 4);
1354 outb(satn[2], wkport + 5);
1355 outb(satn[3], wkport + 6);
1356 outb(satn[4], wkport + 7);
1357 outb(satn[5], wkport + 8);
1358 outb(0, wkport + 0x0f);
1359 outb(dev->id[0][i].devsp, wkport + 0x11);
1360 outb(0, wkport + 0x12);
1361 outb(satn[6], wkport + 0x13);
1362 outb(satn[7], wkport + 0x14);
1363 outb(satn[8], wkport + 0x18);
1364
1365 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1366 cpu_relax();
1367
ea41ed60 1368 if (inb(wkport + 0x17) != 0x11 && inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 1369 continue;
1370
ea41ed60 1371 while (inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 1372 cpu_relax();
1373
1374try_wide:
1375 j = 0;
ea41ed60
OZ		 1376 outb(0x05, wkport + 0x14);
1377 outb(0x20, wkport + 0x18);
1378
1379 while ((inb(wkport + 0x1f) & 0x80) == 0) {
1380 if ((inb(wkport + 0x1f) & 0x01) != 0)
1381 outb(wide[j++], wkport + 0x19);
1da177e4 1382 }
1da177e4 1383
ea41ed60 1384 while ((inb(wkport + 0x17) & 0x80) == 0x00)
1da177e4
LT		 1385 cpu_relax();
1386
ea41ed60 1387 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 1388 if (j == 0x0f) {
1389 goto widep_in;
1390 }
1391 if (j == 0x0a) {
1392 goto widep_cmd;
1393 }
1394 if (j == 0x0e) {
1395 goto try_wide;
1396 }
1397 continue;
1398widep_out:
ea41ed60
OZ		 1399 outb(0x20, wkport + 0x18);
1400 while ((inb(wkport + 0x1f) & 0x80) == 0) {
1401 if ((inb(wkport + 0x1f) & 0x01) != 0)
1402 outb(0, wkport + 0x19);
1da177e4 1403 }
ea41ed60 1404 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 1405 if (j == 0x0f) {
1406 goto widep_in;
1407 }
1408 if (j == 0x0a) {
1409 goto widep_cmd;
1410 }
1411 if (j == 0x0e) {
1412 goto widep_out;
1413 }
1414 continue;
1415widep_in:
ea41ed60
OZ		 1416 outb(0xff, wkport + 0x14);
1417 outb(0x20, wkport + 0x18);
1da177e4
LT		 1418 k = 0;
1419widep_in1:
ea41ed60 1420 j = inb(wkport + 0x1f);
1da177e4 1421 if ((j & 0x01) != 0) {
ea41ed60 1422 mbuf[k++] = inb(wkport + 0x19);
1da177e4
LT		 1423 goto widep_in1;
1424 }
1425 if ((j & 0x80) == 0x00) {
1426 goto widep_in1;
1427 }
ea41ed60 1428 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 1429 if (j == 0x0f) {
1430 goto widep_in;
1431 }
1432 if (j == 0x0a) {
1433 goto widep_cmd;
1434 }
1435 if (j == 0x0e) {
1436 goto widep_out;
1437 }
1438 continue;
1439widep_cmd:
ea41ed60
OZ		 1440 outb(0x30, wkport + 0x10);
1441 outb(0x00, wkport + 0x14);
1442 outb(0x08, wkport + 0x18);
1da177e4 1443
ea41ed60 1444 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1445 cpu_relax();
1446
ea41ed60 1447 j = inb(wkport + 0x17);
1da177e4
LT		 1448 if (j != 0x16) {
1449 if (j == 0x4e) {
1450 goto widep_out;
1451 }
1452 continue;
1453 }
1454 if (mbuf[0] != 0x01) {
1455 goto not_wide;
1456 }
1457 if (mbuf[1] != 0x02) {
1458 goto not_wide;
1459 }
1460 if (mbuf[2] != 0x03) {
1461 goto not_wide;
1462 }
1463 if (mbuf[3] != 0x01) {
1464 goto not_wide;
1465 }
1466 m = 1;
1467 m = m << i;
1468 dev->wide_id[0] |= m;
1469not_wide:
1470 if ((dev->id[0][i].devtype == 0x00) || (dev->id[0][i].devtype == 0x07) || ((dev->id[0][i].devtype == 0x05) && ((n & 0x10) != 0))) {
1471 goto set_sync;
1472 }
1473 continue;
1474set_sync:
1da177e4
LT		 1475 j = 0;
1476 if ((m & dev->wide_id[0]) != 0) {
1477 j |= 0x01;
1478 }
ea41ed60
OZ		 1479 outb(j, wkport + 0x1b);
1480 outb(satn[0], wkport + 3);
1481 outb(satn[1], wkport + 4);
1482 outb(satn[2], wkport + 5);
1483 outb(satn[3], wkport + 6);
1484 outb(satn[4], wkport + 7);
1485 outb(satn[5], wkport + 8);
1486 outb(0, wkport + 0x0f);
1487 outb(dev->id[0][i].devsp, wkport + 0x11);
1488 outb(0, wkport + 0x12);
1489 outb(satn[6], wkport + 0x13);
1490 outb(satn[7], wkport + 0x14);
1491 outb(satn[8], wkport + 0x18);
1492
1493 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1494 cpu_relax();
1495
ea41ed60 1496 if (inb(wkport + 0x17) != 0x11 && inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 1497 continue;
1498
ea41ed60 1499 while (inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 1500 cpu_relax();
1501
1502try_sync:
1503 j = 0;
ea41ed60
OZ		 1504 outb(0x06, wkport + 0x14);
1505 outb(0x20, wkport + 0x18);
1506
1507 while ((inb(wkport + 0x1f) & 0x80) == 0) {
1508 if ((inb(wkport + 0x1f) & 0x01) != 0) {
1da177e4 1509 if ((m & dev->wide_id[0]) != 0) {
ea41ed60 1510 outb(synw[j++], wkport + 0x19);
1da177e4
LT		 1511 } else {
1512 if ((m & dev->ultra_map[0]) != 0) {
ea41ed60 1513 outb(synu[j++], wkport + 0x19);
1da177e4 1514 } else {
ea41ed60 1515 outb(synn[j++], wkport + 0x19);
1da177e4
LT		 1516 }
1517 }
1da177e4
LT		 1518 }
1519 }
1da177e4 1520
ea41ed60 1521 while ((inb(wkport + 0x17) & 0x80) == 0x00)
1da177e4
LT		 1522 cpu_relax();
1523
ea41ed60 1524 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 1525 if (j == 0x0f) {
1526 goto phase_ins;
1527 }
1528 if (j == 0x0a) {
1529 goto phase_cmds;
1530 }
1531 if (j == 0x0e) {
1532 goto try_sync;
1533 }
1534 continue;
1535phase_outs:
ea41ed60
OZ		 1536 outb(0x20, wkport + 0x18);
1537 while ((inb(wkport + 0x1f) & 0x80) == 0x00) {
1538 if ((inb(wkport + 0x1f) & 0x01) != 0x00)
1539 outb(0x00, wkport + 0x19);
1da177e4 1540 }
ea41ed60 1541 j = inb(wkport + 0x17);
1da177e4
LT		 1542 if (j == 0x85) {
1543 goto tar_dcons;
1544 }
1545 j &= 0x0f;
1546 if (j == 0x0f) {
1547 goto phase_ins;
1548 }
1549 if (j == 0x0a) {
1550 goto phase_cmds;
1551 }
1552 if (j == 0x0e) {
1553 goto phase_outs;
1554 }
1555 continue;
1556phase_ins:
ea41ed60
OZ		 1557 outb(0xff, wkport + 0x14);
1558 outb(0x20, wkport + 0x18);
1da177e4
LT		 1559 k = 0;
1560phase_ins1:
ea41ed60 1561 j = inb(wkport + 0x1f);
1da177e4 1562 if ((j & 0x01) != 0x00) {
ea41ed60 1563 mbuf[k++] = inb(wkport + 0x19);
1da177e4
LT		 1564 goto phase_ins1;
1565 }
1566 if ((j & 0x80) == 0x00) {
1567 goto phase_ins1;
1568 }
1da177e4 1569
ea41ed60 1570 while ((inb(wkport + 0x17) & 0x80) == 0x00)
1da177e4
LT		 1571 cpu_relax();
1572
ea41ed60 1573 j = inb(wkport + 0x17);
1da177e4
LT		 1574 if (j == 0x85) {
1575 goto tar_dcons;
1576 }
1577 j &= 0x0f;
1578 if (j == 0x0f) {
1579 goto phase_ins;
1580 }
1581 if (j == 0x0a) {
1582 goto phase_cmds;
1583 }
1584 if (j == 0x0e) {
1585 goto phase_outs;
1586 }
1587 continue;
1588phase_cmds:
ea41ed60 1589 outb(0x30, wkport + 0x10);
1da177e4 1590tar_dcons:
ea41ed60
OZ		 1591 outb(0x00, wkport + 0x14);
1592 outb(0x08, wkport + 0x18);
1da177e4 1593
ea41ed60 1594 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1595 cpu_relax();
1596
ea41ed60 1597 j = inb(wkport + 0x17);
1da177e4
LT		 1598 if (j != 0x16) {
1599 continue;
1600 }
1601 if (mbuf[0] != 0x01) {
1602 continue;
1603 }
1604 if (mbuf[1] != 0x03) {
1605 continue;
1606 }
1607 if (mbuf[4] == 0x00) {
1608 continue;
1609 }
1610 if (mbuf[3] > 0x64) {
1611 continue;
1612 }
1613 if (mbuf[4] > 0x0c) {
1614 mbuf[4] = 0x0c;
1615 }
1616 dev->id[0][i].devsp = mbuf[4];
1617 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
1618 j = 0xa0;
1619 goto set_syn_ok;
1620 }
1621 if (mbuf[3] < 0x1a) {
1622 j = 0x20;
1623 goto set_syn_ok;
1624 }
1625 if (mbuf[3] < 0x33) {
1626 j = 0x40;
1627 goto set_syn_ok;
1628 }
1629 if (mbuf[3] < 0x4c) {
1630 j = 0x50;
1631 goto set_syn_ok;
1632 }
1633 j = 0x60;
1634set_syn_ok:
1635 dev->id[0][i].devsp = (dev->id[0][i].devsp & 0x0f) | j;
1636 }
ea41ed60 1637 outb((unsigned char) (inb(wkport + 0x3a) & 0xef), wkport + 0x3a);
1da177e4
LT		 1638}
1639
1640static void is880(struct atp_unit *dev, unsigned int wkport)
1641{
1da177e4
LT		 1642 unsigned char i, j, k, rmb, n, lvdmode;
1643 unsigned short int m;
1644 static unsigned char mbuf[512];
1645 static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
1646 static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
1647 static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1648 unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
1649 static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1650 unsigned char synuw[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
1651 static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
1652 static unsigned char u3[9] = { 0x80, 1, 6, 4, 0x09, 00, 0x0e, 0x01, 0x02 };
1653
1654 lvdmode = inb(wkport + 0x3f) & 0x40;
1655
1656 for (i = 0; i < 16; i++) {
1657 m = 1;
1658 m = m << i;
1659 if ((m & dev->active_id[0]) != 0) {
1660 continue;
1661 }
1662 if (i == dev->host_id[0]) {
1663 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[0]);
1664 continue;
1665 }
3b30acf6
OZ		 1666 outb(0x01, wkport + 0x5b);
1667 outb(0x08, wkport + 0x41);
1668 outb(0x7f, wkport + 0x42);
1669 outb(satn[0], wkport + 0x43);
1670 outb(satn[1], wkport + 0x44);
1671 outb(satn[2], wkport + 0x45);
1672 outb(satn[3], wkport + 0x46);
1673 outb(satn[4], wkport + 0x47);
1674 outb(satn[5], wkport + 0x48);
1675 outb(0, wkport + 0x4f);
1676 outb(dev->id[0][i].devsp, wkport + 0x51);
1677 outb(0, wkport + 0x52);
1678 outb(satn[6], wkport + 0x53);
1679 outb(satn[7], wkport + 0x54);
1da177e4
LT		 1680 j = i;
1681 if ((j & 0x08) != 0) {
1682 j = (j & 0x07) | 0x40;
1683 }
3b30acf6
OZ		 1684 outb(j, wkport + 0x55);
1685 outb(satn[8], wkport + 0x58);
1da177e4 1686
3b30acf6 1687 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1da177e4
LT		 1688 cpu_relax();
1689
3b30acf6 1690 if (inb(wkport + 0x57) != 0x11 && inb(wkport + 0x57) != 0x8e)
1da177e4
LT		 1691 continue;
1692
3b30acf6 1693 while (inb(wkport + 0x57) != 0x8e)
1da177e4
LT		 1694 cpu_relax();
1695
1696 dev->active_id[0] |= m;
1697
3b30acf6
OZ		 1698 outb(0x30, wkport + 0x50);
1699 outb(0x00, wkport + 0x54);
1da177e4
LT		 1700
1701phase_cmd:
3b30acf6 1702 outb(0x08, wkport + 0x58);
1da177e4 1703
3b30acf6 1704 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1da177e4
LT		 1705 cpu_relax();
1706
3b30acf6 1707 j = inb(wkport + 0x57);
1da177e4 1708 if (j != 0x16) {
3b30acf6 1709 outb(0x41, wkport + 0x50);
1da177e4
LT		 1710 goto phase_cmd;
1711 }
1712sel_ok:
3b30acf6
OZ		 1713 outb(inqd[0], wkport + 0x43);
1714 outb(inqd[1], wkport + 0x44);
1715 outb(inqd[2], wkport + 0x45);
1716 outb(inqd[3], wkport + 0x46);
1717 outb(inqd[4], wkport + 0x47);
1718 outb(inqd[5], wkport + 0x48);
1719 outb(0, wkport + 0x4f);
1720 outb(dev->id[0][i].devsp, wkport + 0x51);
1721 outb(0, wkport + 0x52);
1722 outb(inqd[6], wkport + 0x53);
1723 outb(inqd[7], wkport + 0x54);
1724 outb(inqd[8], wkport + 0x58);
1da177e4 1725
3b30acf6 1726 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1da177e4
LT		 1727 cpu_relax();
1728
3b30acf6 1729 if (inb(wkport + 0x57) != 0x11 && inb(wkport + 0x57) != 0x8e)
1da177e4
LT		 1730 continue;
1731
3b30acf6 1732 while (inb(wkport + 0x57) != 0x8e)
1da177e4
LT		 1733 cpu_relax();
1734
3b30acf6
OZ		 1735 outb(0x00, wkport + 0x5b);
1736 outb(0x08, wkport + 0x58);
1da177e4
LT		 1737 j = 0;
1738rd_inq_data:
3b30acf6 1739 k = inb(wkport + 0x5f);
1da177e4 1740 if ((k & 0x01) != 0) {
3b30acf6 1741 mbuf[j++] = inb(wkport + 0x59);
1da177e4
LT		 1742 goto rd_inq_data;
1743 }
1744 if ((k & 0x80) == 0) {
1745 goto rd_inq_data;
1746 }
3b30acf6 1747 j = inb(wkport + 0x57);
1da177e4
LT		 1748 if (j == 0x16) {
1749 goto inq_ok;
1750 }
3b30acf6
OZ		 1751 outb(0x46, wkport + 0x50);
1752 outb(0, wkport + 0x52);
1753 outb(0, wkport + 0x53);
1754 outb(0, wkport + 0x54);
1755 outb(0x08, wkport + 0x58);
1756 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1da177e4
LT		 1757 cpu_relax();
1758
3b30acf6 1759 if (inb(wkport + 0x57) != 0x16)
1da177e4
LT		 1760 goto sel_ok;
1761
1762inq_ok:
1763 mbuf[36] = 0;
1764 printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]);
1765 dev->id[0][i].devtype = mbuf[0];
1766 rmb = mbuf[1];
1767 n = mbuf[7];
1768 if ((mbuf[7] & 0x60) == 0) {
1769 goto not_wide;
1770 }
1771 if ((i < 8) && ((dev->global_map[0] & 0x20) == 0)) {
1772 goto not_wide;
1773 }
1774 if (lvdmode == 0) {
1775 goto chg_wide;
1776 }
1777 if (dev->sp[0][i] != 0x04) // force u2
1778 {
1779 goto chg_wide;
1780 }
1781
3b30acf6
OZ		 1782 outb(0x01, wkport + 0x5b);
1783 outb(satn[0], wkport + 0x43);
1784 outb(satn[1], wkport + 0x44);
1785 outb(satn[2], wkport + 0x45);
1786 outb(satn[3], wkport + 0x46);
1787 outb(satn[4], wkport + 0x47);
1788 outb(satn[5], wkport + 0x48);
1789 outb(0, wkport + 0x4f);
1790 outb(dev->id[0][i].devsp, wkport + 0x51);
1791 outb(0, wkport + 0x52);
1792 outb(satn[6], wkport + 0x53);
1793 outb(satn[7], wkport + 0x54);
1794 outb(satn[8], wkport + 0x58);
1795
1796 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1da177e4
LT		 1797 cpu_relax();
1798
3b30acf6 1799 if (inb(wkport + 0x57) != 0x11 && inb(wkport + 0x57) != 0x8e)
1da177e4
LT		 1800 continue;
1801
3b30acf6 1802 while (inb(wkport + 0x57) != 0x8e)
1da177e4
LT		 1803 cpu_relax();
1804
1805try_u3:
1806 j = 0;
3b30acf6
OZ		 1807 outb(0x09, wkport + 0x54);
1808 outb(0x20, wkport + 0x58);
1809
1810 while ((inb(wkport + 0x5f) & 0x80) == 0) {
1811 if ((inb(wkport + 0x5f) & 0x01) != 0)
1812 outb(u3[j++], wkport + 0x59);
1da177e4 1813 }
1da177e4 1814
3b30acf6 1815 while ((inb(wkport + 0x57) & 0x80) == 0x00)
1da177e4
LT		 1816 cpu_relax();
1817
3b30acf6 1818 j = inb(wkport + 0x57) & 0x0f;
1da177e4
LT		 1819 if (j == 0x0f) {
1820 goto u3p_in;
1821 }
1822 if (j == 0x0a) {
1823 goto u3p_cmd;
1824 }
1825 if (j == 0x0e) {
1826 goto try_u3;
1827 }
1828 continue;
1829u3p_out:
3b30acf6
OZ		 1830 outb(0x20, wkport + 0x58);
1831 while ((inb(wkport + 0x5f) & 0x80) == 0) {
1832 if ((inb(wkport + 0x5f) & 0x01) != 0)
1833 outb(0, wkport + 0x59);
1da177e4 1834 }
3b30acf6 1835 j = inb(wkport + 0x57) & 0x0f;
1da177e4
LT		 1836 if (j == 0x0f) {
1837 goto u3p_in;
1838 }
1839 if (j == 0x0a) {
1840 goto u3p_cmd;
1841 }
1842 if (j == 0x0e) {
1843 goto u3p_out;
1844 }
1845 continue;
1846u3p_in:
3b30acf6
OZ		 1847 outb(0x09, wkport + 0x54);
1848 outb(0x20, wkport + 0x58);
1da177e4
LT		 1849 k = 0;
1850u3p_in1:
3b30acf6 1851 j = inb(wkport + 0x5f);
1da177e4 1852 if ((j & 0x01) != 0) {
3b30acf6 1853 mbuf[k++] = inb(wkport + 0x59);
1da177e4
LT		 1854 goto u3p_in1;
1855 }
1856 if ((j & 0x80) == 0x00) {
1857 goto u3p_in1;
1858 }
3b30acf6 1859 j = inb(wkport + 0x57) & 0x0f;
1da177e4
LT		 1860 if (j == 0x0f) {
1861 goto u3p_in;
1862 }
1863 if (j == 0x0a) {
1864 goto u3p_cmd;
1865 }
1866 if (j == 0x0e) {
1867 goto u3p_out;
1868 }
1869 continue;
1870u3p_cmd:
3b30acf6
OZ		 1871 outb(0x30, wkport + 0x50);
1872 outb(0x00, wkport + 0x54);
1873 outb(0x08, wkport + 0x58);
1da177e4 1874
3b30acf6 1875 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1da177e4
LT		 1876 cpu_relax();
1877
3b30acf6 1878 j = inb(wkport + 0x57);
1da177e4
LT		 1879 if (j != 0x16) {
1880 if (j == 0x4e) {
1881 goto u3p_out;
1882 }
1883 continue;
1884 }
1885 if (mbuf[0] != 0x01) {
1886 goto chg_wide;
1887 }
1888 if (mbuf[1] != 0x06) {
1889 goto chg_wide;
1890 }
1891 if (mbuf[2] != 0x04) {
1892 goto chg_wide;
1893 }
1894 if (mbuf[3] == 0x09) {
1895 m = 1;
1896 m = m << i;
1897 dev->wide_id[0] |= m;
1898 dev->id[0][i].devsp = 0xce;
1899 continue;
1900 }
1901chg_wide:
3b30acf6
OZ		 1902 outb(0x01, wkport + 0x5b);
1903 outb(satn[0], wkport + 0x43);
1904 outb(satn[1], wkport + 0x44);
1905 outb(satn[2], wkport + 0x45);
1906 outb(satn[3], wkport + 0x46);
1907 outb(satn[4], wkport + 0x47);
1908 outb(satn[5], wkport + 0x48);
1909 outb(0, wkport + 0x4f);
1910 outb(dev->id[0][i].devsp, wkport + 0x51);
1911 outb(0, wkport + 0x52);
1912 outb(satn[6], wkport + 0x53);
1913 outb(satn[7], wkport + 0x54);
1914 outb(satn[8], wkport + 0x58);
1915
1916 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1da177e4
LT		 1917 cpu_relax();
1918
3b30acf6 1919 if (inb(wkport + 0x57) != 0x11 && inb(wkport + 0x57) != 0x8e)
1da177e4
LT		 1920 continue;
1921
3b30acf6 1922 while (inb(wkport + 0x57) != 0x8e)
1da177e4
LT		 1923 cpu_relax();
1924
1925try_wide:
1926 j = 0;
3b30acf6
OZ		 1927 outb(0x05, wkport + 0x54);
1928 outb(0x20, wkport + 0x58);
1929
1930 while ((inb(wkport + 0x5f) & 0x80) == 0) {
1931 if ((inb(wkport + 0x5f) & 0x01) != 0)
1932 outb(wide[j++], wkport + 0x59);
1da177e4 1933 }
3b30acf6 1934 while ((inb(wkport + 0x57) & 0x80) == 0x00)
1da177e4
LT		 1935 cpu_relax();
1936
3b30acf6 1937 j = inb(wkport + 0x57) & 0x0f;
1da177e4
LT		 1938 if (j == 0x0f) {
1939 goto widep_in;
1940 }
1941 if (j == 0x0a) {
1942 goto widep_cmd;
1943 }
1944 if (j == 0x0e) {
1945 goto try_wide;
1946 }
1947 continue;
1948widep_out:
3b30acf6
OZ		 1949 outb(0x20, wkport + 0x58);
1950 while ((inb(wkport + 0x5f) & 0x80) == 0) {
1951 if ((inb(wkport + 0x5f) & 0x01) != 0)
1952 outb(0, wkport + 0x59);
1da177e4 1953 }
3b30acf6 1954 j = inb(wkport + 0x57) & 0x0f;
1da177e4
LT		 1955 if (j == 0x0f) {
1956 goto widep_in;
1957 }
1958 if (j == 0x0a) {
1959 goto widep_cmd;
1960 }
1961 if (j == 0x0e) {
1962 goto widep_out;
1963 }
1964 continue;
1965widep_in:
3b30acf6
OZ		 1966 outb(0xff, wkport + 0x54);
1967 outb(0x20, wkport + 0x58);
1da177e4
LT		 1968 k = 0;
1969widep_in1:
3b30acf6 1970 j = inb(wkport + 0x5f);
1da177e4 1971 if ((j & 0x01) != 0) {
3b30acf6 1972 mbuf[k++] = inb(wkport + 0x59);
1da177e4
LT		 1973 goto widep_in1;
1974 }
1975 if ((j & 0x80) == 0x00) {
1976 goto widep_in1;
1977 }
3b30acf6 1978 j = inb(wkport + 0x57) & 0x0f;
1da177e4
LT		 1979 if (j == 0x0f) {
1980 goto widep_in;
1981 }
1982 if (j == 0x0a) {
1983 goto widep_cmd;
1984 }
1985 if (j == 0x0e) {
1986 goto widep_out;
1987 }
1988 continue;
1989widep_cmd:
3b30acf6
OZ		 1990 outb(0x30, wkport + 0x50);
1991 outb(0x00, wkport + 0x54);
1992 outb(0x08, wkport + 0x58);
1993
1994 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1da177e4
LT		 1995 cpu_relax();
1996
3b30acf6 1997 j = inb(wkport + 0x57);
1da177e4
LT		 1998 if (j != 0x16) {
1999 if (j == 0x4e) {
2000 goto widep_out;
2001 }
2002 continue;
2003 }
2004 if (mbuf[0] != 0x01) {
2005 goto not_wide;
2006 }
2007 if (mbuf[1] != 0x02) {
2008 goto not_wide;
2009 }
2010 if (mbuf[2] != 0x03) {
2011 goto not_wide;
2012 }
2013 if (mbuf[3] != 0x01) {
2014 goto not_wide;
2015 }
2016 m = 1;
2017 m = m << i;
2018 dev->wide_id[0] |= m;
2019not_wide:
2020 if ((dev->id[0][i].devtype == 0x00) || (dev->id[0][i].devtype == 0x07) || ((dev->id[0][i].devtype == 0x05) && ((n & 0x10) != 0))) {
2021 m = 1;
2022 m = m << i;
2023 if ((dev->async[0] & m) != 0) {
2024 goto set_sync;
2025 }
2026 }
2027 continue;
2028set_sync:
2029 if (dev->sp[0][i] == 0x02) {
2030 synu[4] = 0x0c;
2031 synuw[4] = 0x0c;
2032 } else {
2033 if (dev->sp[0][i] >= 0x03) {
2034 synu[4] = 0x0a;
2035 synuw[4] = 0x0a;
2036 }
2037 }
1da177e4
LT		 2038 j = 0;
2039 if ((m & dev->wide_id[0]) != 0) {
2040 j |= 0x01;
2041 }
3b30acf6
OZ		 2042 outb(j, wkport + 0x5b);
2043 outb(satn[0], wkport + 0x43);
2044 outb(satn[1], wkport + 0x44);
2045 outb(satn[2], wkport + 0x45);
2046 outb(satn[3], wkport + 0x46);
2047 outb(satn[4], wkport + 0x47);
2048 outb(satn[5], wkport + 0x48);
2049 outb(0, wkport + 0x4f);
2050 outb(dev->id[0][i].devsp, wkport + 0x51);
2051 outb(0, wkport + 0x52);
2052 outb(satn[6], wkport + 0x53);
2053 outb(satn[7], wkport + 0x54);
2054 outb(satn[8], wkport + 0x58);
2055
2056 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1da177e4
LT		 2057 cpu_relax();
2058
3b30acf6 2059 if ((inb(wkport + 0x57) != 0x11) && (inb(wkport + 0x57) != 0x8e)) {
1da177e4
LT		 2060 continue;
2061 }
3b30acf6 2062 while (inb(wkport + 0x57) != 0x8e)
1da177e4
LT		 2063 cpu_relax();
2064
2065try_sync:
2066 j = 0;
3b30acf6
OZ		 2067 outb(0x06, wkport + 0x54);
2068 outb(0x20, wkport + 0x58);
2069
2070 while ((inb(wkport + 0x5f) & 0x80) == 0) {
2071 if ((inb(wkport + 0x5f) & 0x01) != 0) {
1da177e4
LT		 2072 if ((m & dev->wide_id[0]) != 0) {
2073 if ((m & dev->ultra_map[0]) != 0) {
3b30acf6 2074 outb(synuw[j++], wkport + 0x59);
1da177e4 2075 } else {
3b30acf6 2076 outb(synw[j++], wkport + 0x59);
1da177e4
LT		 2077 }
2078 } else {
2079 if ((m & dev->ultra_map[0]) != 0) {
3b30acf6 2080 outb(synu[j++], wkport + 0x59);
1da177e4 2081 } else {
3b30acf6 2082 outb(synn[j++], wkport + 0x59);
1da177e4
LT		 2083 }
2084 }
1da177e4
LT		 2085 }
2086 }
1da177e4 2087
3b30acf6 2088 while ((inb(wkport + 0x57) & 0x80) == 0x00)
1da177e4
LT		 2089 cpu_relax();
2090
3b30acf6 2091 j = inb(wkport + 0x57) & 0x0f;
1da177e4
LT		 2092 if (j == 0x0f) {
2093 goto phase_ins;
2094 }
2095 if (j == 0x0a) {
2096 goto phase_cmds;
2097 }
2098 if (j == 0x0e) {
2099 goto try_sync;
2100 }
2101 continue;
2102phase_outs:
3b30acf6
OZ		 2103 outb(0x20, wkport + 0x58);
2104 while ((inb(wkport + 0x5f) & 0x80) == 0x00) {
2105 if ((inb(wkport + 0x5f) & 0x01) != 0x00)
2106 outb(0x00, wkport + 0x59);
1da177e4 2107 }
3b30acf6 2108 j = inb(wkport + 0x57);
1da177e4
LT		 2109 if (j == 0x85) {
2110 goto tar_dcons;
2111 }
2112 j &= 0x0f;
2113 if (j == 0x0f) {
2114 goto phase_ins;
2115 }
2116 if (j == 0x0a) {
2117 goto phase_cmds;
2118 }
2119 if (j == 0x0e) {
2120 goto phase_outs;
2121 }
2122 continue;
2123phase_ins:
3b30acf6
OZ		 2124 outb(0x06, wkport + 0x54);
2125 outb(0x20, wkport + 0x58);
1da177e4
LT		 2126 k = 0;
2127phase_ins1:
3b30acf6 2128 j = inb(wkport + 0x5f);
1da177e4 2129 if ((j & 0x01) != 0x00) {
3b30acf6 2130 mbuf[k++] = inb(wkport + 0x59);
1da177e4
LT		 2131 goto phase_ins1;
2132 }
2133 if ((j & 0x80) == 0x00) {
2134 goto phase_ins1;
2135 }
1da177e4 2136
3b30acf6 2137 while ((inb(wkport + 0x57) & 0x80) == 0x00)
1da177e4
LT		 2138 cpu_relax();
2139
3b30acf6 2140 j = inb(wkport + 0x57);
1da177e4
LT		 2141 if (j == 0x85) {
2142 goto tar_dcons;
2143 }
2144 j &= 0x0f;
2145 if (j == 0x0f) {
2146 goto phase_ins;
2147 }
2148 if (j == 0x0a) {
2149 goto phase_cmds;
2150 }
2151 if (j == 0x0e) {
2152 goto phase_outs;
2153 }
2154 continue;
2155phase_cmds:
3b30acf6 2156 outb(0x30, wkport + 0x50);
1da177e4 2157tar_dcons:
3b30acf6
OZ		 2158 outb(0x00, wkport + 0x54);
2159 outb(0x08, wkport + 0x58);
1da177e4 2160
3b30acf6 2161 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1da177e4
LT		 2162 cpu_relax();
2163
3b30acf6 2164 j = inb(wkport + 0x57);
1da177e4
LT		 2165 if (j != 0x16) {
2166 continue;
2167 }
2168 if (mbuf[0] != 0x01) {
2169 continue;
2170 }
2171 if (mbuf[1] != 0x03) {
2172 continue;
2173 }
2174 if (mbuf[4] == 0x00) {
2175 continue;
2176 }
2177 if (mbuf[3] > 0x64) {
2178 continue;
2179 }
2180 if (mbuf[4] > 0x0e) {
2181 mbuf[4] = 0x0e;
2182 }
2183 dev->id[0][i].devsp = mbuf[4];
2184 if (mbuf[3] < 0x0c) {
2185 j = 0xb0;
2186 goto set_syn_ok;
2187 }
2188 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
2189 j = 0xa0;
2190 goto set_syn_ok;
2191 }
2192 if (mbuf[3] < 0x1a) {
2193 j = 0x20;
2194 goto set_syn_ok;
2195 }
2196 if (mbuf[3] < 0x33) {
2197 j = 0x40;
2198 goto set_syn_ok;
2199 }
2200 if (mbuf[3] < 0x4c) {
2201 j = 0x50;
2202 goto set_syn_ok;
2203 }
2204 j = 0x60;
2205set_syn_ok:
2206 dev->id[0][i].devsp = (dev->id[0][i].devsp & 0x0f) | j;
2207 }
2208}
2209
2210static void atp870u_free_tables(struct Scsi_Host *host)
2211{
2212 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
2213 int j, k;
2214 for (j=0; j < 2; j++) {
2215 for (k = 0; k < 16; k++) {
2216 if (!atp_dev->id[j][k].prd_table)
2217 continue;
b5683557 2218 pci_free_consistent(atp_dev->pdev, 1024, atp_dev->id[j][k].prd_table, atp_dev->id[j][k].prd_bus);
1da177e4
LT		 2219 atp_dev->id[j][k].prd_table = NULL;
2220 }
2221 }
2222}
2223
2224static int atp870u_init_tables(struct Scsi_Host *host)
2225{
2226 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
2227 int c,k;
2228 for(c=0;c < 2;c++) {
2229 for(k=0;k<16;k++) {
b5683557 2230 atp_dev->id[c][k].prd_table = pci_alloc_consistent(atp_dev->pdev, 1024, &(atp_dev->id[c][k].prd_bus));
1da177e4
LT		 2231 if (!atp_dev->id[c][k].prd_table) {
2232 printk("atp870u_init_tables fail\n");
2233 atp870u_free_tables(host);
2234 return -ENOMEM;
2235 }
b5683557 2236 atp_dev->id[c][k].prdaddr = atp_dev->id[c][k].prd_bus;
1da177e4
LT		 2237 atp_dev->id[c][k].devsp=0x20;
2238 atp_dev->id[c][k].devtype = 0x7f;
2239 atp_dev->id[c][k].curr_req = NULL;
2240 }
2241
2242 atp_dev->active_id[c] = 0;
2243 atp_dev->wide_id[c] = 0;
2244 atp_dev->host_id[c] = 0x07;
2245 atp_dev->quhd[c] = 0;
2246 atp_dev->quend[c] = 0;
2247 atp_dev->last_cmd[c] = 0xff;
2248 atp_dev->in_snd[c] = 0;
2249 atp_dev->in_int[c] = 0;
2250
2251 for (k = 0; k < qcnt; k++) {
2252 atp_dev->quereq[c][k] = NULL;
2253 }
2254 for (k = 0; k < 16; k++) {
2255 atp_dev->id[c][k].curr_req = NULL;
2256 atp_dev->sp[c][k] = 0x04;
2257 }
2258 }
2259 return 0;
2260}
2261
2262/* return non-zero on detection */
2263static int atp870u_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2264{
2265 unsigned char k, m, c;
2266 unsigned long flags;
493c5201 2267 unsigned int base_io, error,n;
1da177e4
LT		 2268 unsigned char host_id;
2269 struct Scsi_Host *shpnt = NULL;
dc6a78f1 2270 struct atp_unit *atpdev, *p;
1da177e4
LT		 2271 unsigned char setupdata[2][16];
2272 int count = 0;
dc6a78f1
RD		 2273
2274 atpdev = kzalloc(sizeof(*atpdev), GFP_KERNEL);
2275 if (!atpdev)
2276 return -ENOMEM;
2277
1da177e4 2278 if (pci_enable_device(pdev))
dc6a78f1 2279 goto err_eio;
1da177e4 2280
284901a9 2281 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 2282 printk(KERN_INFO "atp870u: use 32bit DMA mask.\n");
2283 } else {
2284 printk(KERN_ERR "atp870u: DMA mask required but not available.\n");
dc6a78f1 2285 goto err_eio;
1da177e4
LT		 2286 }
2287
1da177e4
LT		 2288 /*
2289 * It's probably easier to weed out some revisions like
2290 * this than via the PCI device table
2291 */
2292 if (ent->device == PCI_DEVICE_ID_ARTOP_AEC7610) {
7d7311c4 2293 atpdev->chip_ver = pdev->revision;
dc6a78f1
RD		 2294 if (atpdev->chip_ver < 2)
2295 goto err_eio;
1da177e4
LT		 2296 }
2297
2298 switch (ent->device) {
2299 case PCI_DEVICE_ID_ARTOP_AEC7612UW:
2300 case PCI_DEVICE_ID_ARTOP_AEC7612SUW:
2301 case ATP880_DEVID1:
2302 case ATP880_DEVID2:
2303 case ATP885_DEVID:
dc6a78f1 2304 atpdev->chip_ver = 0x04;
1da177e4
LT		 2305 default:
2306 break;
2307 }
2308 base_io = pci_resource_start(pdev, 0);
2309 base_io &= 0xfffffff8;
dc6a78f1 2310
1da177e4 2311 if ((ent->device == ATP880_DEVID1)||(ent->device == ATP880_DEVID2)) {
7d7311c4 2312 atpdev->chip_ver = pdev->revision;
1da177e4
LT		 2313 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);//JCC082803
2314
2315 host_id = inb(base_io + 0x39);
2316 host_id >>= 0x04;
2317
2318 printk(KERN_INFO " ACARD AEC-67160 PCI Ultra3 LVD Host Adapter: %d"
2319 " IO:%x, IRQ:%d.\n", count, base_io, pdev->irq);
dc6a78f1
RD		 2320 atpdev->ioport[0] = base_io + 0x40;
2321 atpdev->pciport[0] = base_io + 0x28;
2322 atpdev->dev_id = ent->device;
2323 atpdev->host_id[0] = host_id;
1da177e4 2324
493c5201
OZ		 2325 atpdev->scam_on = inb(base_io + 0x22);
2326 atpdev->global_map[0] = inb(base_io + 0x35);
2327 atpdev->ultra_map[0] = inw(base_io + 0x3c);
1da177e4
LT		 2328
2329 n = 0x3f09;
2330next_fblk_880:
2331 if (n >= 0x4000)
2332 goto flash_ok_880;
2333
2334 m = 0;
2335 outw(n, base_io + 0x34);
2336 n += 0x0002;
2337 if (inb(base_io + 0x30) == 0xff)
2338 goto flash_ok_880;
2339
dc6a78f1
RD		 2340 atpdev->sp[0][m++] = inb(base_io + 0x30);
2341 atpdev->sp[0][m++] = inb(base_io + 0x31);
2342 atpdev->sp[0][m++] = inb(base_io + 0x32);
2343 atpdev->sp[0][m++] = inb(base_io + 0x33);
1da177e4
LT		 2344 outw(n, base_io + 0x34);
2345 n += 0x0002;
dc6a78f1
RD		 2346 atpdev->sp[0][m++] = inb(base_io + 0x30);
2347 atpdev->sp[0][m++] = inb(base_io + 0x31);
2348 atpdev->sp[0][m++] = inb(base_io + 0x32);
2349 atpdev->sp[0][m++] = inb(base_io + 0x33);
1da177e4
LT		 2350 outw(n, base_io + 0x34);
2351 n += 0x0002;
dc6a78f1
RD		 2352 atpdev->sp[0][m++] = inb(base_io + 0x30);
2353 atpdev->sp[0][m++] = inb(base_io + 0x31);
2354 atpdev->sp[0][m++] = inb(base_io + 0x32);
2355 atpdev->sp[0][m++] = inb(base_io + 0x33);
1da177e4
LT		 2356 outw(n, base_io + 0x34);
2357 n += 0x0002;
dc6a78f1
RD		 2358 atpdev->sp[0][m++] = inb(base_io + 0x30);
2359 atpdev->sp[0][m++] = inb(base_io + 0x31);
2360 atpdev->sp[0][m++] = inb(base_io + 0x32);
2361 atpdev->sp[0][m++] = inb(base_io + 0x33);
1da177e4
LT		 2362 n += 0x0018;
2363 goto next_fblk_880;
2364flash_ok_880:
2365 outw(0, base_io + 0x34);
dc6a78f1
RD		 2366 atpdev->ultra_map[0] = 0;
2367 atpdev->async[0] = 0;
1da177e4
LT		 2368 for (k = 0; k < 16; k++) {
2369 n = 1;
2370 n = n << k;
dc6a78f1
RD		 2371 if (atpdev->sp[0][k] > 1) {
2372 atpdev->ultra_map[0] |= n;
1da177e4 2373 } else {
dc6a78f1
RD		 2374 if (atpdev->sp[0][k] == 0)
2375 atpdev->async[0] |= n;
1da177e4
LT		 2376 }
2377 }
dc6a78f1
RD		 2378 atpdev->async[0] = ~(atpdev->async[0]);
2379 outb(atpdev->global_map[0], base_io + 0x35);
1da177e4
LT		 2380
2381 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2382 if (!shpnt)
dc6a78f1 2383 goto err_nomem;
1da177e4
LT		 2384
2385 p = (struct atp_unit *)&shpnt->hostdata;
2386
dc6a78f1
RD		 2387 atpdev->host = shpnt;
2388 atpdev->pdev = pdev;
1da177e4 2389 pci_set_drvdata(pdev, p);
dc6a78f1 2390 memcpy(p, atpdev, sizeof(*atpdev));
1da177e4
LT		 2391 if (atp870u_init_tables(shpnt) < 0) {
2392 printk(KERN_ERR "Unable to allocate tables for Acard controller\n");
2393 goto unregister;
2394 }
2395
1d6f359a 2396 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp880i", shpnt)) {
1da177e4
LT		 2397 printk(KERN_ERR "Unable to allocate IRQ%d for Acard controller.\n", pdev->irq);
2398 goto free_tables;
2399 }
2400
2401 spin_lock_irqsave(shpnt->host_lock, flags);
493c5201
OZ		 2402 k = inb(base_io + 0x38) & 0x80;
2403 outb(k, base_io + 0x38);
2404 outb(0x20, base_io + 0x3b);
1da177e4 2405 mdelay(32);
493c5201 2406 outb(0, base_io + 0x3b);
1da177e4 2407 mdelay(32);
493c5201
OZ		 2408 inb(base_io + 0x5b);
2409 inb(base_io + 0x57);
2410 outb((host_id | 0x08), base_io + 0x40);
2411 outb(0, base_io + 0x58);
2412 while ((inb(base_io + 0x5f) & 0x80) == 0)
1da177e4 2413 mdelay(1);
493c5201
OZ		 2414 inb(base_io + 0x57);
2415 outb(8, base_io + 0x41);
2416 outb(0x7f, base_io + 0x42);
2417 outb(0x20, base_io + 0x51);
1da177e4
LT		 2418
2419 tscam(shpnt);
2420 is880(p, base_io);
493c5201 2421 outb(0xb0, base_io + 0x38);
1da177e4
LT		 2422 shpnt->max_id = 16;
2423 shpnt->this_id = host_id;
2424 shpnt->unique_id = base_io;
2425 shpnt->io_port = base_io;
2426 shpnt->n_io_port = 0x60; /* Number of bytes of I/O space used */
2427 shpnt->irq = pdev->irq;
2428 } else if (ent->device == ATP885_DEVID) {
2429 printk(KERN_INFO " ACARD AEC-67162 PCI Ultra3 LVD Host Adapter: IO:%x, IRQ:%d.\n"
2430 , base_io, pdev->irq);
2431
dc6a78f1
RD		 2432 atpdev->pdev = pdev;
2433 atpdev->dev_id = ent->device;
2434 atpdev->baseport = base_io;
2435 atpdev->ioport[0] = base_io + 0x80;
2436 atpdev->ioport[1] = base_io + 0xc0;
2437 atpdev->pciport[0] = base_io + 0x40;
2438 atpdev->pciport[1] = base_io + 0x50;
1da177e4
LT		 2439
2440 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2441 if (!shpnt)
dc6a78f1 2442 goto err_nomem;
1da177e4
LT		 2443
2444 p = (struct atp_unit *)&shpnt->hostdata;
2445
dc6a78f1
RD		 2446 atpdev->host = shpnt;
2447 atpdev->pdev = pdev;
1da177e4 2448 pci_set_drvdata(pdev, p);
dc6a78f1 2449 memcpy(p, atpdev, sizeof(struct atp_unit));
1da177e4
LT		 2450 if (atp870u_init_tables(shpnt) < 0)
2451 goto unregister;
2452
2453#ifdef ED_DBGP
2454 printk("request_irq() shpnt %p hostdata %p\n", shpnt, p);
2455#endif
1d6f359a 2456 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp870u", shpnt)) {
1da177e4
LT		 2457 printk(KERN_ERR "Unable to allocate IRQ for Acard controller.\n");
2458 goto free_tables;
2459 }
2460
2461 spin_lock_irqsave(shpnt->host_lock, flags);
2462
2463 c=inb(base_io + 0x29);
2464 outb((c | 0x04),base_io + 0x29);
2465
2466 n=0x1f80;
2467next_fblk_885:
2468 if (n >= 0x2000) {
2469 goto flash_ok_885;
2470 }
2471 outw(n,base_io + 0x3c);
2472 if (inl(base_io + 0x38) == 0xffffffff) {
2473 goto flash_ok_885;
2474 }
2475 for (m=0; m < 2; m++) {
2476 p->global_map[m]= 0;
2477 for (k=0; k < 4; k++) {
2478 outw(n++,base_io + 0x3c);
2479 ((unsigned long *)&setupdata[m][0])[k]=inl(base_io + 0x38);
2480 }
2481 for (k=0; k < 4; k++) {
2482 outw(n++,base_io + 0x3c);
2483 ((unsigned long *)&p->sp[m][0])[k]=inl(base_io + 0x38);
2484 }
2485 n += 8;
2486 }
2487 goto next_fblk_885;
2488flash_ok_885:
2489#ifdef ED_DBGP
2490 printk( "Flash Read OK\n");
2491#endif
2492 c=inb(base_io + 0x29);
2493 outb((c & 0xfb),base_io + 0x29);
2494 for (c=0;c < 2;c++) {
2495 p->ultra_map[c]=0;
2496 p->async[c] = 0;
2497 for (k=0; k < 16; k++) {
2498 n=1;
2499 n = n << k;
2500 if (p->sp[c][k] > 1) {
2501 p->ultra_map[c] |= n;
2502 } else {
2503 if (p->sp[c][k] == 0) {
2504 p->async[c] |= n;
2505 }
2506 }
2507 }
2508 p->async[c] = ~(p->async[c]);
2509
2510 if (p->global_map[c] == 0) {
2511 k=setupdata[c][1];
2512 if ((k & 0x40) != 0)
2513 p->global_map[c] |= 0x20;
2514 k &= 0x07;
2515 p->global_map[c] |= k;
2516 if ((setupdata[c][2] & 0x04) != 0)
2517 p->global_map[c] |= 0x08;
2518 p->host_id[c] = setupdata[c][0] & 0x07;
2519 }
2520 }
2521
2522 k = inb(base_io + 0x28) & 0x8f;
2523 k |= 0x10;
2524 outb(k, base_io + 0x28);
2525 outb(0x80, base_io + 0x41);
2526 outb(0x80, base_io + 0x51);
2527 mdelay(100);
2528 outb(0, base_io + 0x41);
2529 outb(0, base_io + 0x51);
2530 mdelay(1000);
2531 inb(base_io + 0x9b);
2532 inb(base_io + 0x97);
2533 inb(base_io + 0xdb);
2534 inb(base_io + 0xd7);
1da177e4
LT		 2535 k=p->host_id[0];
2536 if (k > 7)
2537 k = (k & 0x07) | 0x40;
2538 k |= 0x08;
493c5201
OZ		 2539 outb(k, base_io + 0x80);
2540 outb(0, base_io + 0x98);
1da177e4 2541
493c5201 2542 while ((inb(base_io + 0x9f) & 0x80) == 0)
1da177e4
LT		 2543 cpu_relax();
2544
493c5201
OZ		 2545 inb(base_io + 0x97);
2546 outb(8, base_io + 0x81);
2547 outb(0x7f, base_io + 0x82);
2548 outb(0x20, base_io + 0x91);
2549
1da177e4
LT		 2550 k=p->host_id[1];
2551 if (k > 7)
2552 k = (k & 0x07) | 0x40;
2553 k |= 0x08;
493c5201
OZ		 2554 outb(k, base_io + 0xc0);
2555 outb(0, base_io + 0xd8);
1da177e4 2556
493c5201 2557 while ((inb(base_io + 0xdf) & 0x80) == 0)
1da177e4
LT		 2558 cpu_relax();
2559
493c5201
OZ		 2560 inb(base_io + 0xd7);
2561 outb(8, base_io + 0xc1);
2562 outb(0x7f, base_io + 0xc2);
2563 outb(0x20, base_io + 0xd1);
1da177e4
LT		 2564
2565 tscam_885();
2566 printk(KERN_INFO " Scanning Channel A SCSI Device ...\n");
2567 is885(p, base_io + 0x80, 0);
2568 printk(KERN_INFO " Scanning Channel B SCSI Device ...\n");
2569 is885(p, base_io + 0xc0, 1);
2570
2571 k = inb(base_io + 0x28) & 0xcf;
2572 k |= 0xc0;
2573 outb(k, base_io + 0x28);
2574 k = inb(base_io + 0x1f) | 0x80;
2575 outb(k, base_io + 0x1f);
2576 k = inb(base_io + 0x29) | 0x01;
2577 outb(k, base_io + 0x29);
2578#ifdef ED_DBGP
2579 //printk("atp885: atp_host[0] 0x%p\n", atp_host[0]);
2580#endif
2581 shpnt->max_id = 16;
2582 shpnt->max_lun = (p->global_map[0] & 0x07) + 1;
2583 shpnt->max_channel = 1;
2584 shpnt->this_id = p->host_id[0];
2585 shpnt->unique_id = base_io;
2586 shpnt->io_port = base_io;
2587 shpnt->n_io_port = 0xff; /* Number of bytes of I/O space used */
2588 shpnt->irq = pdev->irq;
2589
2590 } else {
2591 error = pci_read_config_byte(pdev, 0x49, &host_id);
2592
2593 printk(KERN_INFO " ACARD AEC-671X PCI Ultra/W SCSI-2/3 Host Adapter: %d "
2594 "IO:%x, IRQ:%d.\n", count, base_io, pdev->irq);
2595
dc6a78f1
RD		 2596 atpdev->ioport[0] = base_io;
2597 atpdev->pciport[0] = base_io + 0x20;
2598 atpdev->dev_id = ent->device;
1da177e4 2599 host_id &= 0x07;
dc6a78f1 2600 atpdev->host_id[0] = host_id;
493c5201
OZ		 2601 atpdev->scam_on = inb(base_io + 0x22);
2602 atpdev->global_map[0] = inb(base_io + 0x2d);
2603 atpdev->ultra_map[0] = inw(base_io + 0x2e);
1da177e4 2604
dc6a78f1
RD		 2605 if (atpdev->ultra_map[0] == 0) {
2606 atpdev->scam_on = 0x00;
2607 atpdev->global_map[0] = 0x20;
2608 atpdev->ultra_map[0] = 0xffff;
1da177e4
LT		 2609 }
2610
2611 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2612 if (!shpnt)
dc6a78f1 2613 goto err_nomem;
1da177e4
LT		 2614
2615 p = (struct atp_unit *)&shpnt->hostdata;
2616
dc6a78f1
RD		 2617 atpdev->host = shpnt;
2618 atpdev->pdev = pdev;
1da177e4 2619 pci_set_drvdata(pdev, p);
dc6a78f1 2620 memcpy(p, atpdev, sizeof(*atpdev));
1da177e4
LT		 2621 if (atp870u_init_tables(shpnt) < 0)
2622 goto unregister;
2623
1d6f359a 2624 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp870i", shpnt)) {
1da177e4
LT		 2625 printk(KERN_ERR "Unable to allocate IRQ%d for Acard controller.\n", pdev->irq);
2626 goto free_tables;
2627 }
2628
2629 spin_lock_irqsave(shpnt->host_lock, flags);
dc6a78f1 2630 if (atpdev->chip_ver > 0x07) { /* check if atp876 chip then enable terminator */
493c5201 2631 outb(0x00, base_io + 0x3e);
1da177e4
LT		 2632 }
2633
493c5201
OZ		 2634 k = (inb(base_io + 0x3a) & 0xf3) | 0x10;
2635 outb(k, base_io + 0x3a);
2636 outb((k & 0xdf), base_io + 0x3a);
1da177e4 2637 mdelay(32);
493c5201 2638 outb(k, base_io + 0x3a);
1da177e4 2639 mdelay(32);
493c5201
OZ		 2640 outb((host_id | 0x08), base_io + 0);
2641 outb(0, base_io + 0x18);
2642 while ((inb(base_io + 0x1f) & 0x80) == 0)
1da177e4
LT		 2643 mdelay(1);
2644
493c5201
OZ		 2645 inb(base_io + 0x17);
2646 outb(8, base_io + 1);
2647 outb(0x7f, base_io + 2);
2648 outb(0x20, base_io + 0x11);
1da177e4
LT		 2649
2650 tscam(shpnt);
2651 is870(p, base_io);
493c5201
OZ		 2652 outb((inb(base_io + 0x3a) & 0xef), base_io + 0x3a);
2653 outb((inb(base_io + 0x3b) | 0x20), base_io + 0x3b);
dc6a78f1 2654 if (atpdev->chip_ver == 4)
1da177e4
LT		 2655 shpnt->max_id = 16;
2656 else
2b89dad0 2657 shpnt->max_id = 8;
1da177e4
LT		 2658 shpnt->this_id = host_id;
2659 shpnt->unique_id = base_io;
2660 shpnt->io_port = base_io;
2661 shpnt->n_io_port = 0x40; /* Number of bytes of I/O space used */
2662 shpnt->irq = pdev->irq;
2663 }
2664 spin_unlock_irqrestore(shpnt->host_lock, flags);
2665 if(ent->device==ATP885_DEVID) {
2666 if(!request_region(base_io, 0xff, "atp870u")) /* Register the IO ports that we use */
2667 goto request_io_fail;
2668 } else if((ent->device==ATP880_DEVID1)||(ent->device==ATP880_DEVID2)) {
2669 if(!request_region(base_io, 0x60, "atp870u")) /* Register the IO ports that we use */
2670 goto request_io_fail;
2671 } else {
2672 if(!request_region(base_io, 0x40, "atp870u")) /* Register the IO ports that we use */
2673 goto request_io_fail;
2674 }
2675 count++;
2676 if (scsi_add_host(shpnt, &pdev->dev))
2677 goto scsi_add_fail;
2678 scsi_scan_host(shpnt);
2679#ifdef ED_DBGP
2680 printk("atp870u_prob : exit\n");
2681#endif
2682 return 0;
2683
2684scsi_add_fail:
2685 printk("atp870u_prob:scsi_add_fail\n");
2686 if(ent->device==ATP885_DEVID) {
2687 release_region(base_io, 0xff);
2688 } else if((ent->device==ATP880_DEVID1)||(ent->device==ATP880_DEVID2)) {
2689 release_region(base_io, 0x60);
2690 } else {
2691 release_region(base_io, 0x40);
2692 }
2693request_io_fail:
2694 printk("atp870u_prob:request_io_fail\n");
2695 free_irq(pdev->irq, shpnt);
2696free_tables:
2697 printk("atp870u_prob:free_table\n");
2698 atp870u_free_tables(shpnt);
2699unregister:
2700 printk("atp870u_prob:unregister\n");
2701 scsi_host_put(shpnt);
2702 return -1;
dc6a78f1
RD		 2703err_eio:
2704 kfree(atpdev);
2705 return -EIO;
2706err_nomem:
2707 kfree(atpdev);
2708 return -ENOMEM;
1da177e4
LT		 2709}
2710
2711/* The abort command does not leave the device in a clean state where
2712 it is available to be used again. Until this gets worked out, we will
2713 leave it commented out. */
2714
2715static int atp870u_abort(struct scsi_cmnd * SCpnt)
2716{
2717 unsigned char j, k, c;
2718 struct scsi_cmnd *workrequ;
1da177e4
LT		 2719 struct atp_unit *dev;
2720 struct Scsi_Host *host;
2721 host = SCpnt->device->host;
2722
2723 dev = (struct atp_unit *)&host->hostdata;
422c0d61 2724 c = scmd_channel(SCpnt);
1da177e4
LT		 2725 printk(" atp870u: abort Channel = %x \n", c);
2726 printk("working=%x last_cmd=%x ", dev->working[c], dev->last_cmd[c]);
2727 printk(" quhdu=%x quendu=%x ", dev->quhd[c], dev->quend[c]);
1da177e4 2728 for (j = 0; j < 0x18; j++) {
2eabdf22 2729 printk(" r%2x=%2x", j, inb(dev->ioport[c] + j));
1da177e4 2730 }
2eabdf22
OZ		 2731 printk(" r1c=%2x", inb(dev->ioport[c] + 0x1c));
2732 printk(" r1f=%2x in_snd=%2x ", inb(dev->ioport[c] + 0x1f), dev->in_snd[c]);
2733 printk(" d00=%2x", inb(dev->pciport[c]));
2734 printk(" d02=%2x", inb(dev->pciport[c] + 0x02));
1da177e4
LT		 2735 for(j=0;j<16;j++) {
2736 if (dev->id[c][j].curr_req != NULL) {
2737 workrequ = dev->id[c][j].curr_req;
2738 printk("\n que cdb= ");
2739 for (k=0; k < workrequ->cmd_len; k++) {
2740 printk(" %2x ",workrequ->cmnd[k]);
2741 }
2742 printk(" last_lenu= %x ",(unsigned int)dev->id[c][j].last_len);
2743 }
2744 }
2745 return SUCCESS;
2746}
2747
2748static const char *atp870u_info(struct Scsi_Host *notused)
2749{
2750 static char buffer[128];
2751
2752 strcpy(buffer, "ACARD AEC-6710/6712/67160 PCI Ultra/W/LVD SCSI-3 Adapter Driver V2.6+ac ");
2753
2754 return buffer;
2755}
2756
d773e422 2757static int atp870u_show_info(struct seq_file *m, struct Scsi_Host *HBAptr)
1da177e4 2758{
3d30079c
RV		 2759 seq_puts(m, "ACARD AEC-671X Driver Version: 2.6+ac\n\n"
2760 "Adapter Configuration:\n");
d773e422
AV		 2761 seq_printf(m, " Base IO: %#.4lx\n", HBAptr->io_port);
2762 seq_printf(m, " IRQ: %d\n", HBAptr->irq);
2763 return 0;
1da177e4
LT		 2764}
2765
2766
2767static int atp870u_biosparam(struct scsi_device *disk, struct block_device *dev,
2768 sector_t capacity, int *ip)
2769{
2770 int heads, sectors, cylinders;
2771
2772 heads = 64;
2773 sectors = 32;
2774 cylinders = (unsigned long)capacity / (heads * sectors);
2775 if (cylinders > 1024) {
2776 heads = 255;
2777 sectors = 63;
2778 cylinders = (unsigned long)capacity / (heads * sectors);
2779 }
2780 ip[0] = heads;
2781 ip[1] = sectors;
2782 ip[2] = cylinders;
2783
2784 return 0;
2785}
2786
2787static void atp870u_remove (struct pci_dev *pdev)
2788{
2789 struct atp_unit *devext = pci_get_drvdata(pdev);
2790 struct Scsi_Host *pshost = devext->host;
2791
2792
2793 scsi_remove_host(pshost);
2794 printk(KERN_INFO "free_irq : %d\n",pshost->irq);
2795 free_irq(pshost->irq, pshost);
2796 release_region(pshost->io_port, pshost->n_io_port);
2797 printk(KERN_INFO "atp870u_free_tables : %p\n",pshost);
2798 atp870u_free_tables(pshost);
2799 printk(KERN_INFO "scsi_host_put : %p\n",pshost);
2800 scsi_host_put(pshost);
1da177e4
LT		 2801}
2802MODULE_LICENSE("GPL");
2803
2804static struct scsi_host_template atp870u_template = {
2805 .module = THIS_MODULE,
2806 .name = "atp870u" /* name */,
2807 .proc_name = "atp870u",
d773e422 2808 .show_info = atp870u_show_info,
1da177e4
LT		 2809 .info = atp870u_info /* info */,
2810 .queuecommand = atp870u_queuecommand /* queuecommand */,
2811 .eh_abort_handler = atp870u_abort /* abort */,
2812 .bios_param = atp870u_biosparam /* biosparm */,
2813 .can_queue = qcnt /* can_queue */,
2814 .this_id = 7 /* SCSI ID */,
2815 .sg_tablesize = ATP870U_SCATTER /*SG_ALL*/ /*SG_NONE*/,
1da177e4
LT		 2816 .use_clustering = ENABLE_CLUSTERING,
2817 .max_sectors = ATP870U_MAX_SECTORS,
2818};
2819
2820static struct pci_device_id atp870u_id_table[] = {
2821 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP885_DEVID) },
2822 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID1) },
2823 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID2) },
2824 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7610) },
2825 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612UW) },
2826 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612U) },
2827 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612S) },
2828 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612D) },
2829 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612SUW) },
2830 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_8060) },
2831 { 0, },
2832};
2833
2834MODULE_DEVICE_TABLE(pci, atp870u_id_table);
2835
2836static struct pci_driver atp870u_driver = {
2837 .id_table = atp870u_id_table,
2838 .name = "atp870u",
2839 .probe = atp870u_probe,
6f039790 2840 .remove = atp870u_remove,
1da177e4
LT		 2841};
2842
2843static int __init atp870u_init(void)
2844{
2845#ifdef ED_DBGP
2846 printk("atp870u_init: Entry\n");
2847#endif
2848 return pci_register_driver(&atp870u_driver);
2849}
2850
2851static void __exit atp870u_exit(void)
2852{
2853#ifdef ED_DBGP
2854 printk("atp870u_exit: Entry\n");
2855#endif
2856 pci_unregister_driver(&atp870u_driver);
2857}
2858
2859static void tscam_885(void)
2860{
2861 unsigned char i;
2862
2863 for (i = 0; i < 0x2; i++) {
2864 mdelay(300);
2865 }
2866 return;
2867}
2868
2869
2870
2871static void is885(struct atp_unit *dev, unsigned int wkport,unsigned char c)
2872{
1da177e4
LT		 2873 unsigned char i, j, k, rmb, n, lvdmode;
2874 unsigned short int m;
2875 static unsigned char mbuf[512];
2876 static unsigned char satn[9] = {0, 0, 0, 0, 0, 0, 0, 6, 6};
2877 static unsigned char inqd[9] = {0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6};
2878 static unsigned char synn[6] = {0x80, 1, 3, 1, 0x19, 0x0e};
2879 unsigned char synu[6] = {0x80, 1, 3, 1, 0x0a, 0x0e};
2880 static unsigned char synw[6] = {0x80, 1, 3, 1, 0x19, 0x0e};
2881 unsigned char synuw[6] = {0x80, 1, 3, 1, 0x0a, 0x0e};
2882 static unsigned char wide[6] = {0x80, 1, 2, 3, 1, 0};
2883 static unsigned char u3[9] = { 0x80,1,6,4,0x09,00,0x0e,0x01,0x02 };
2884
2885 lvdmode=inb(wkport + 0x1b) >> 7;
2886
2887 for (i = 0; i < 16; i++) {
2888 m = 1;
2889 m = m << i;
2890 if ((m & dev->active_id[c]) != 0) {
2891 continue;
2892 }
2893 if (i == dev->host_id[c]) {
2894 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[c]);
2895 continue;
2896 }
e2c22b45
OZ		 2897 outb(0x01, wkport + 0x1b);
2898 outb(0x08, wkport + 0x01);
2899 outb(0x7f, wkport + 0x02);
2900 outb(satn[0], wkport + 0x03);
2901 outb(satn[1], wkport + 0x04);
2902 outb(satn[2], wkport + 0x05);
2903 outb(satn[3], wkport + 0x06);
2904 outb(satn[4], wkport + 0x07);
2905 outb(satn[5], wkport + 0x08);
2906 outb(0, wkport + 0x0f);
2907 outb(dev->id[c][i].devsp, wkport + 0x11);
1da177e4 2908
e2c22b45
OZ		 2909 outb(0, wkport + 0x12);
2910 outb(satn[6], wkport + 0x13);
2911 outb(satn[7], wkport + 0x14);
1da177e4
LT		 2912 j = i;
2913 if ((j & 0x08) != 0) {
2914 j = (j & 0x07) | 0x40;
2915 }
e2c22b45
OZ		 2916 outb(j, wkport + 0x15);
2917 outb(satn[8], wkport + 0x18);
1da177e4 2918
e2c22b45 2919 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 2920 cpu_relax();
e2c22b45 2921 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
1da177e4
LT		 2922 continue;
2923 }
e2c22b45 2924 while (inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 2925 cpu_relax();
2926 dev->active_id[c] |= m;
2927
e2c22b45
OZ		 2928 outb(0x30, wkport + 0x10);
2929 outb(0x00, wkport + 0x14);
1da177e4
LT		 2930
2931phase_cmd:
e2c22b45
OZ		 2932 outb(0x08, wkport + 0x18);
2933 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 2934 cpu_relax();
e2c22b45 2935 j = inb(wkport + 0x17);
1da177e4 2936 if (j != 0x16) {
e2c22b45 2937 outb(0x41, wkport + 0x10);
1da177e4
LT		 2938 goto phase_cmd;
2939 }
2940sel_ok:
e2c22b45
OZ		 2941 outb(inqd[0], wkport + 0x03);
2942 outb(inqd[1], wkport + 0x04);
2943 outb(inqd[2], wkport + 0x05);
2944 outb(inqd[3], wkport + 0x06);
2945 outb(inqd[4], wkport + 0x07);
2946 outb(inqd[5], wkport + 0x08);
2947 outb(0, wkport + 0x0f);
2948 outb(dev->id[c][i].devsp, wkport + 0x11);
2949 outb(0, wkport + 0x12);
2950 outb(inqd[6], wkport + 0x13);
2951 outb(inqd[7], wkport + 0x14);
2952 outb(inqd[8], wkport + 0x18);
2953 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 2954 cpu_relax();
e2c22b45 2955 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
1da177e4
LT		 2956 continue;
2957 }
e2c22b45 2958 while (inb(wkport + 0x17) != 0x8e)
1da177e4 2959 cpu_relax();
e2c22b45
OZ		 2960 outb(0x00, wkport + 0x1b);
2961 outb(0x08, wkport + 0x18);
1da177e4
LT		 2962 j = 0;
2963rd_inq_data:
e2c22b45 2964 k = inb(wkport + 0x1f);
1da177e4 2965 if ((k & 0x01) != 0) {
e2c22b45 2966 mbuf[j++] = inb(wkport + 0x19);
1da177e4
LT		 2967 goto rd_inq_data;
2968 }
2969 if ((k & 0x80) == 0) {
2970 goto rd_inq_data;
2971 }
e2c22b45 2972 j = inb(wkport + 0x17);
1da177e4
LT		 2973 if (j == 0x16) {
2974 goto inq_ok;
2975 }
e2c22b45
OZ		 2976 outb(0x46, wkport + 0x10);
2977 outb(0, wkport + 0x12);
2978 outb(0, wkport + 0x13);
2979 outb(0, wkport + 0x14);
2980 outb(0x08, wkport + 0x18);
2981 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 2982 cpu_relax();
e2c22b45 2983 if (inb(wkport + 0x17) != 0x16) {
1da177e4
LT		 2984 goto sel_ok;
2985 }
2986inq_ok:
2987 mbuf[36] = 0;
2988 printk( KERN_INFO" ID: %2d %s\n", i, &mbuf[8]);
2989 dev->id[c][i].devtype = mbuf[0];
2990 rmb = mbuf[1];
2991 n = mbuf[7];
2992 if ((mbuf[7] & 0x60) == 0) {
2993 goto not_wide;
2994 }
2995 if ((i < 8) && ((dev->global_map[c] & 0x20) == 0)) {
2996 goto not_wide;
2997 }
2998 if (lvdmode == 0) {
2999 goto chg_wide;
3000 }
3001 if (dev->sp[c][i] != 0x04) { // force u2
3002 goto chg_wide;
3003 }
3004
e2c22b45
OZ		 3005 outb(0x01, wkport + 0x1b);
3006 outb(satn[0], wkport + 0x03);
3007 outb(satn[1], wkport + 0x04);
3008 outb(satn[2], wkport + 0x05);
3009 outb(satn[3], wkport + 0x06);
3010 outb(satn[4], wkport + 0x07);
3011 outb(satn[5], wkport + 0x08);
3012 outb(0, wkport + 0x0f);
3013 outb(dev->id[c][i].devsp, wkport + 0x11);
3014 outb(0, wkport + 0x12);
3015 outb(satn[6], wkport + 0x13);
3016 outb(satn[7], wkport + 0x14);
3017 outb(satn[8], wkport + 0x18);
3018
3019 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 3020 cpu_relax();
e2c22b45 3021 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
1da177e4
LT		 3022 continue;
3023 }
e2c22b45 3024 while (inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 3025 cpu_relax();
3026try_u3:
3027 j = 0;
e2c22b45
OZ		 3028 outb(0x09, wkport + 0x14);
3029 outb(0x20, wkport + 0x18);
3030
3031 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3032 if ((inb(wkport + 0x1f) & 0x01) != 0)
3033 outb(u3[j++], wkport + 0x19);
1da177e4
LT		 3034 cpu_relax();
3035 }
e2c22b45 3036 while ((inb(wkport + 0x17) & 0x80) == 0x00)
1da177e4 3037 cpu_relax();
e2c22b45 3038 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 3039 if (j == 0x0f) {
3040 goto u3p_in;
3041 }
3042 if (j == 0x0a) {
3043 goto u3p_cmd;
3044 }
3045 if (j == 0x0e) {
3046 goto try_u3;
3047 }
3048 continue;
3049u3p_out:
e2c22b45
OZ		 3050 outb(0x20, wkport + 0x18);
3051 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3052 if ((inb(wkport + 0x1f) & 0x01) != 0)
3053 outb(0, wkport + 0x19);
1da177e4
LT		 3054 cpu_relax();
3055 }
e2c22b45 3056 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 3057 if (j == 0x0f) {
3058 goto u3p_in;
3059 }
3060 if (j == 0x0a) {
3061 goto u3p_cmd;
3062 }
3063 if (j == 0x0e) {
3064 goto u3p_out;
3065 }
3066 continue;
3067u3p_in:
e2c22b45
OZ		 3068 outb(0x09, wkport + 0x14);
3069 outb(0x20, wkport + 0x18);
1da177e4
LT		 3070 k = 0;
3071u3p_in1:
e2c22b45 3072 j = inb(wkport + 0x1f);
1da177e4 3073 if ((j & 0x01) != 0) {
e2c22b45 3074 mbuf[k++] = inb(wkport + 0x19);
1da177e4
LT		 3075 goto u3p_in1;
3076 }
3077 if ((j & 0x80) == 0x00) {
3078 goto u3p_in1;
3079 }
e2c22b45 3080 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 3081 if (j == 0x0f) {
3082 goto u3p_in;
3083 }
3084 if (j == 0x0a) {
3085 goto u3p_cmd;
3086 }
3087 if (j == 0x0e) {
3088 goto u3p_out;
3089 }
3090 continue;
3091u3p_cmd:
e2c22b45
OZ		 3092 outb(0x30, wkport + 0x10);
3093 outb(0x00, wkport + 0x14);
3094 outb(0x08, wkport + 0x18);
3095 while ((inb(wkport + 0x1f) & 0x80) == 0x00);
3096 j = inb(wkport + 0x17);
1da177e4
LT		 3097 if (j != 0x16) {
3098 if (j == 0x4e) {
3099 goto u3p_out;
3100 }
3101 continue;
3102 }
3103 if (mbuf[0] != 0x01) {
3104 goto chg_wide;
3105 }
3106 if (mbuf[1] != 0x06) {
3107 goto chg_wide;
3108 }
3109 if (mbuf[2] != 0x04) {
3110 goto chg_wide;
3111 }
3112 if (mbuf[3] == 0x09) {
3113 m = 1;
3114 m = m << i;
3115 dev->wide_id[c] |= m;
3116 dev->id[c][i].devsp = 0xce;
3117#ifdef ED_DBGP
3118 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
3119#endif
3120 continue;
3121 }
3122chg_wide:
e2c22b45
OZ		 3123 outb(0x01, wkport + 0x1b);
3124 outb(satn[0], wkport + 0x03);
3125 outb(satn[1], wkport + 0x04);
3126 outb(satn[2], wkport + 0x05);
3127 outb(satn[3], wkport + 0x06);
3128 outb(satn[4], wkport + 0x07);
3129 outb(satn[5], wkport + 0x08);
3130 outb(0, wkport + 0x0f);
3131 outb(dev->id[c][i].devsp, wkport + 0x11);
3132 outb(0, wkport + 0x12);
3133 outb(satn[6], wkport + 0x13);
3134 outb(satn[7], wkport + 0x14);
3135 outb(satn[8], wkport + 0x18);
3136
3137 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 3138 cpu_relax();
e2c22b45 3139 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
1da177e4
LT		 3140 continue;
3141 }
e2c22b45 3142 while (inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 3143 cpu_relax();
3144try_wide:
3145 j = 0;
e2c22b45
OZ		 3146 outb(0x05, wkport + 0x14);
3147 outb(0x20, wkport + 0x18);
3148
3149 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3150 if ((inb(wkport + 0x1f) & 0x01) != 0)
3151 outb(wide[j++], wkport + 0x19);
1da177e4
LT		 3152 cpu_relax();
3153 }
e2c22b45 3154 while ((inb(wkport + 0x17) & 0x80) == 0x00)
1da177e4 3155 cpu_relax();
e2c22b45 3156 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 3157 if (j == 0x0f) {
3158 goto widep_in;
3159 }
3160 if (j == 0x0a) {
3161 goto widep_cmd;
3162 }
3163 if (j == 0x0e) {
3164 goto try_wide;
3165 }
3166 continue;
3167widep_out:
e2c22b45
OZ		 3168 outb(0x20, wkport + 0x18);
3169 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3170 if ((inb(wkport + 0x1f) & 0x01) != 0)
3171 outb(0, wkport + 0x19);
1da177e4
LT		 3172 cpu_relax();
3173 }
e2c22b45 3174 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 3175 if (j == 0x0f) {
3176 goto widep_in;
3177 }
3178 if (j == 0x0a) {
3179 goto widep_cmd;
3180 }
3181 if (j == 0x0e) {
3182 goto widep_out;
3183 }
3184 continue;
3185widep_in:
e2c22b45
OZ		 3186 outb(0xff, wkport + 0x14);
3187 outb(0x20, wkport + 0x18);
1da177e4
LT		 3188 k = 0;
3189widep_in1:
e2c22b45 3190 j = inb(wkport + 0x1f);
1da177e4 3191 if ((j & 0x01) != 0) {
e2c22b45 3192 mbuf[k++] = inb(wkport + 0x19);
1da177e4
LT		 3193 goto widep_in1;
3194 }
3195 if ((j & 0x80) == 0x00) {
3196 goto widep_in1;
3197 }
e2c22b45 3198 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 3199 if (j == 0x0f) {
3200 goto widep_in;
3201 }
3202 if (j == 0x0a) {
3203 goto widep_cmd;
3204 }
3205 if (j == 0x0e) {
3206 goto widep_out;
3207 }
3208 continue;
3209widep_cmd:
e2c22b45
OZ		 3210 outb(0x30, wkport + 0x10);
3211 outb(0x00, wkport + 0x14);
3212 outb(0x08, wkport + 0x18);
3213 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 3214 cpu_relax();
e2c22b45 3215 j = inb(wkport + 0x17);
1da177e4
LT		 3216 if (j != 0x16) {
3217 if (j == 0x4e) {
3218 goto widep_out;
3219 }
3220 continue;
3221 }
3222 if (mbuf[0] != 0x01) {
3223 goto not_wide;
3224 }
3225 if (mbuf[1] != 0x02) {
3226 goto not_wide;
3227 }
3228 if (mbuf[2] != 0x03) {
3229 goto not_wide;
3230 }
3231 if (mbuf[3] != 0x01) {
3232 goto not_wide;
3233 }
3234 m = 1;
3235 m = m << i;
3236 dev->wide_id[c] |= m;
3237not_wide:
3238 if ((dev->id[c][i].devtype == 0x00) || (dev->id[c][i].devtype == 0x07) ||
3239 ((dev->id[c][i].devtype == 0x05) && ((n & 0x10) != 0))) {
3240 m = 1;
3241 m = m << i;
3242 if ((dev->async[c] & m) != 0) {
3243 goto set_sync;
3244 }
3245 }
3246 continue;
3247set_sync:
3248 if (dev->sp[c][i] == 0x02) {
3249 synu[4]=0x0c;
3250 synuw[4]=0x0c;
3251 } else {
3252 if (dev->sp[c][i] >= 0x03) {
3253 synu[4]=0x0a;
3254 synuw[4]=0x0a;
3255 }
3256 }
1da177e4
LT		 3257 j = 0;
3258 if ((m & dev->wide_id[c]) != 0) {
3259 j |= 0x01;
3260 }
e2c22b45
OZ		 3261 outb(j, wkport + 0x1b);
3262 outb(satn[0], wkport + 0x03);
3263 outb(satn[1], wkport + 0x04);
3264 outb(satn[2], wkport + 0x05);
3265 outb(satn[3], wkport + 0x06);
3266 outb(satn[4], wkport + 0x07);
3267 outb(satn[5], wkport + 0x08);
3268 outb(0, wkport + 0x0f);
3269 outb(dev->id[c][i].devsp, wkport + 0x11);
3270 outb(0, wkport + 0x12);
3271 outb(satn[6], wkport + 0x13);
3272 outb(satn[7], wkport + 0x14);
3273 outb(satn[8], wkport + 0x18);
3274
3275 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 3276 cpu_relax();
e2c22b45 3277 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
1da177e4
LT		 3278 continue;
3279 }
e2c22b45 3280 while (inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 3281 cpu_relax();
3282try_sync:
3283 j = 0;
e2c22b45
OZ		 3284 outb(0x06, wkport + 0x14);
3285 outb(0x20, wkport + 0x18);
3286
3287 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3288 if ((inb(wkport + 0x1f) & 0x01) != 0) {
1da177e4
LT		 3289 if ((m & dev->wide_id[c]) != 0) {
3290 if ((m & dev->ultra_map[c]) != 0) {
e2c22b45 3291 outb(synuw[j++], wkport + 0x19);
1da177e4 3292 } else {
e2c22b45 3293 outb(synw[j++], wkport + 0x19);
1da177e4
LT		 3294 }
3295 } else {
3296 if ((m & dev->ultra_map[c]) != 0) {
e2c22b45 3297 outb(synu[j++], wkport + 0x19);
1da177e4 3298 } else {
e2c22b45 3299 outb(synn[j++], wkport + 0x19);
1da177e4
LT		 3300 }
3301 }
1da177e4
LT		 3302 }
3303 }
e2c22b45 3304 while ((inb(wkport + 0x17) & 0x80) == 0x00)
1da177e4 3305 cpu_relax();
e2c22b45 3306 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 3307 if (j == 0x0f) {
3308 goto phase_ins;
3309 }
3310 if (j == 0x0a) {
3311 goto phase_cmds;
3312 }
3313 if (j == 0x0e) {
3314 goto try_sync;
3315 }
3316 continue;
3317phase_outs:
e2c22b45
OZ		 3318 outb(0x20, wkport + 0x18);
3319 while ((inb(wkport + 0x1f) & 0x80) == 0x00) {
3320 if ((inb(wkport + 0x1f) & 0x01) != 0x00)
3321 outb(0x00, wkport + 0x19);
1da177e4
LT		 3322 cpu_relax();
3323 }
e2c22b45 3324 j = inb(wkport + 0x17);
1da177e4
LT		 3325 if (j == 0x85) {
3326 goto tar_dcons;
3327 }
3328 j &= 0x0f;
3329 if (j == 0x0f) {
3330 goto phase_ins;
3331 }
3332 if (j == 0x0a) {
3333 goto phase_cmds;
3334 }
3335 if (j == 0x0e) {
3336 goto phase_outs;
3337 }
3338 continue;
3339phase_ins:
e2c22b45
OZ		 3340 outb(0x06, wkport + 0x14);
3341 outb(0x20, wkport + 0x18);
1da177e4
LT		 3342 k = 0;
3343phase_ins1:
e2c22b45 3344 j = inb(wkport + 0x1f);
1da177e4 3345 if ((j & 0x01) != 0x00) {
e2c22b45 3346 mbuf[k++] = inb(wkport + 0x19);
1da177e4
LT		 3347 goto phase_ins1;
3348 }
3349 if ((j & 0x80) == 0x00) {
3350 goto phase_ins1;
3351 }
e2c22b45
OZ		 3352 while ((inb(wkport + 0x17) & 0x80) == 0x00);
3353 j = inb(wkport + 0x17);
1da177e4
LT		 3354 if (j == 0x85) {
3355 goto tar_dcons;
3356 }
3357 j &= 0x0f;
3358 if (j == 0x0f) {
3359 goto phase_ins;
3360 }
3361 if (j == 0x0a) {
3362 goto phase_cmds;
3363 }
3364 if (j == 0x0e) {
3365 goto phase_outs;
3366 }
3367 continue;
3368phase_cmds:
e2c22b45 3369 outb(0x30, wkport + 0x10);
1da177e4 3370tar_dcons:
e2c22b45
OZ		 3371 outb(0x00, wkport + 0x14);
3372 outb(0x08, wkport + 0x18);
3373 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 3374 cpu_relax();
e2c22b45 3375 j = inb(wkport + 0x17);
1da177e4
LT		 3376 if (j != 0x16) {
3377 continue;
3378 }
3379 if (mbuf[0] != 0x01) {
3380 continue;
3381 }
3382 if (mbuf[1] != 0x03) {
3383 continue;
3384 }
3385 if (mbuf[4] == 0x00) {
3386 continue;
3387 }
3388 if (mbuf[3] > 0x64) {
3389 continue;
3390 }
3391 if (mbuf[4] > 0x0e) {
3392 mbuf[4] = 0x0e;
3393 }
3394 dev->id[c][i].devsp = mbuf[4];
3395 if (mbuf[3] < 0x0c){
3396 j = 0xb0;
3397 goto set_syn_ok;
3398 }
3399 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
3400 j = 0xa0;
3401 goto set_syn_ok;
3402 }
3403 if (mbuf[3] < 0x1a) {
3404 j = 0x20;
3405 goto set_syn_ok;
3406 }
3407 if (mbuf[3] < 0x33) {
3408 j = 0x40;
3409 goto set_syn_ok;
3410 }
3411 if (mbuf[3] < 0x4c) {
3412 j = 0x50;
3413 goto set_syn_ok;
3414 }
3415 j = 0x60;
3416 set_syn_ok:
3417 dev->id[c][i].devsp = (dev->id[c][i].devsp & 0x0f) | j;
3418#ifdef ED_DBGP
3419 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
3420#endif
3421 }
e2c22b45 3422 outb(0x80, wkport + 0x16);
1da177e4
LT		 3423}
3424
3425module_init(atp870u_init);
3426module_exit(atp870u_exit);
3427
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