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scsi: be2iscsi: Move functions to right files
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / be2iscsi / be_cmds.c
CommitLineData
6733b39a 1/**
c4f39bda 2 * Copyright (C) 2005 - 2015 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
4627de93 11 * linux-drivers@avagotech.com
6733b39a 12 *
c4f39bda 13 * Emulex
255fa9a3
JK		 14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6733b39a
JK		 16 */
17
2177199d
JSJ		 18#include <scsi/iscsi_proto.h>
19
4eea99d5 20#include "be_main.h"
6733b39a
JK		 21#include "be.h"
22#include "be_mgmt.h"
6733b39a 23
e9b91193
JK		 24int be_chk_reset_complete(struct beiscsi_hba *phba)
25{
26 unsigned int num_loop;
27 u8 *mpu_sem = 0;
28 u32 status;
29
30 num_loop = 1000;
31 mpu_sem = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
32 msleep(5000);
33
34 while (num_loop) {
35 status = readl((void *)mpu_sem);
36
37 if ((status & 0x80000000) || (status & 0x0000FFFF) == 0xC000)
38 break;
39 msleep(60);
40 num_loop--;
41 }
42
43 if ((status & 0x80000000) || (!num_loop)) {
99bc5d55
JSJ		 44 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
45 "BC_%d : Failed in be_chk_reset_complete"
46 "status = 0x%x\n", status);
e9b91193
JK		 47 return -EIO;
48 }
49
50 return 0;
51}
52
090e2184
JB		 53struct be_mcc_wrb *alloc_mcc_wrb(struct beiscsi_hba *phba,
54 unsigned int *ref_tag)
69fd6d7b 55{
090e2184
JB		 56 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
57 struct be_mcc_wrb *wrb = NULL;
58 unsigned int tag;
59
96eb8d4d 60 spin_lock(&phba->ctrl.mcc_lock);
090e2184
JB		 61 if (mccq->used == mccq->len) {
62 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT |
63 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
64 "BC_%d : MCC queue full: WRB used %u tag avail %u\n",
65 mccq->used, phba->ctrl.mcc_tag_available);
66 goto alloc_failed;
67 }
68
69 if (!phba->ctrl.mcc_tag_available)
70 goto alloc_failed;
71
72 tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index];
73 if (!tag) {
74 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT |
75 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
76 "BC_%d : MCC tag 0 allocated: tag avail %u alloc index %u\n",
77 phba->ctrl.mcc_tag_available,
78 phba->ctrl.mcc_alloc_index);
79 goto alloc_failed;
80 }
81
82 /* return this tag for further reference */
83 *ref_tag = tag;
84 phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0;
85 phba->ctrl.mcc_tag_status[tag] = 0;
86 phba->ctrl.ptag_state[tag].tag_state = 0;
50a4b824 87 phba->ctrl.ptag_state[tag].cbfn = NULL;
090e2184
JB		 88 phba->ctrl.mcc_tag_available--;
89 if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1))
90 phba->ctrl.mcc_alloc_index = 0;
91 else
92 phba->ctrl.mcc_alloc_index++;
93
94 wrb = queue_head_node(mccq);
95 memset(wrb, 0, sizeof(*wrb));
96 wrb->tag0 = tag;
97 wrb->tag0 |= (mccq->head << MCC_Q_WRB_IDX_SHIFT) & MCC_Q_WRB_IDX_MASK;
98 queue_head_inc(mccq);
99 mccq->used++;
100
101alloc_failed:
96eb8d4d 102 spin_unlock(&phba->ctrl.mcc_lock);
090e2184
JB		 103 return wrb;
104}
105
106void free_mcc_wrb(struct be_ctrl_info *ctrl, unsigned int tag)
107{
108 struct be_queue_info *mccq = &ctrl->mcc_obj.q;
109
96eb8d4d 110 spin_lock(&ctrl->mcc_lock);
69fd6d7b
JB		 111 tag = tag & MCC_Q_CMD_TAG_MASK;
112 ctrl->mcc_tag[ctrl->mcc_free_index] = tag;
113 if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1))
114 ctrl->mcc_free_index = 0;
115 else
116 ctrl->mcc_free_index++;
117 ctrl->mcc_tag_available++;
090e2184 118 mccq->used--;
96eb8d4d 119 spin_unlock(&ctrl->mcc_lock);
69fd6d7b
JB		 120}
121
50a4b824
JB		 122/*
123 * beiscsi_mcc_compl_status - Return the status of MCC completion
124 * @phba: Driver private structure
125 * @tag: Tag for the MBX Command
126 * @wrb: the WRB used for the MBX Command
127 * @mbx_cmd_mem: ptr to memory allocated for MBX Cmd
128 *
129 * return
130 * Success: 0
131 * Failure: Non-Zero
132 */
133int __beiscsi_mcc_compl_status(struct beiscsi_hba *phba,
134 unsigned int tag,
135 struct be_mcc_wrb **wrb,
136 struct be_dma_mem *mbx_cmd_mem)
137{
138 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
139 uint16_t status = 0, addl_status = 0, wrb_num = 0;
140 struct be_cmd_resp_hdr *mbx_resp_hdr;
141 struct be_cmd_req_hdr *mbx_hdr;
142 struct be_mcc_wrb *temp_wrb;
143 uint32_t mcc_tag_status;
144 int rc = 0;
145
146 mcc_tag_status = phba->ctrl.mcc_tag_status[tag];
147 status = (mcc_tag_status & CQE_STATUS_MASK);
148 addl_status = ((mcc_tag_status & CQE_STATUS_ADDL_MASK) >>
149 CQE_STATUS_ADDL_SHIFT);
150
151 if (mbx_cmd_mem) {
152 mbx_hdr = (struct be_cmd_req_hdr *)mbx_cmd_mem->va;
153 } else {
154 wrb_num = (mcc_tag_status & CQE_STATUS_WRB_MASK) >>
155 CQE_STATUS_WRB_SHIFT;
156 temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num);
157 mbx_hdr = embedded_payload(temp_wrb);
158
159 if (wrb)
160 *wrb = temp_wrb;
161 }
162
163 if (status || addl_status) {
164 beiscsi_log(phba, KERN_WARNING,
165 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
166 BEISCSI_LOG_CONFIG,
167 "BC_%d : MBX Cmd Failed for Subsys : %d Opcode : %d with Status : %d and Extd_Status : %d\n",
168 mbx_hdr->subsystem, mbx_hdr->opcode,
169 status, addl_status);
170 rc = -EIO;
171 if (status == MCC_STATUS_INSUFFICIENT_BUFFER) {
172 mbx_resp_hdr = (struct be_cmd_resp_hdr *)mbx_hdr;
173 beiscsi_log(phba, KERN_WARNING,
174 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
175 BEISCSI_LOG_CONFIG,
176 "BC_%d : Insufficient Buffer Error Resp_Len : %d Actual_Resp_Len : %d\n",
177 mbx_resp_hdr->response_length,
178 mbx_resp_hdr->actual_resp_len);
179 rc = -EAGAIN;
180 }
181 }
182
183 return rc;
184}
185
e175defe 186/*
88840332 187 * beiscsi_mccq_compl_wait()- Process completion in MCC CQ
e175defe
JSJ		 188 * @phba: Driver private structure
189 * @tag: Tag for the MBX Command
190 * @wrb: the WRB used for the MBX Command
1957aa7f 191 * @mbx_cmd_mem: ptr to memory allocated for MBX Cmd
e175defe
JSJ		 192 *
193 * Waits for MBX completion with the passed TAG.
194 *
195 * return
196 * Success: 0
197 * Failure: Non-Zero
198 **/
88840332 199int beiscsi_mccq_compl_wait(struct beiscsi_hba *phba,
50a4b824
JB		 200 unsigned int tag,
201 struct be_mcc_wrb **wrb,
88840332 202 struct be_dma_mem *mbx_cmd_mem)
e175defe
JSJ		 203{
204 int rc = 0;
e175defe 205
9122e991
JB		 206 if (beiscsi_hba_in_error(phba)) {
207 clear_bit(MCC_TAG_STATE_RUNNING,
208 &phba->ctrl.ptag_state[tag].tag_state);
209 return -EIO;
210 }
7a158003 211
e175defe 212 /* wait for the mccq completion */
50a4b824
JB		 213 rc = wait_event_interruptible_timeout(phba->ctrl.mcc_wait[tag],
214 phba->ctrl.mcc_tag_status[tag],
215 msecs_to_jiffies(
216 BEISCSI_HOST_MBX_TIMEOUT));
217
cdde6682
JB		 218 /**
219 * If MBOX cmd timeout expired, tag and resource allocated
220 * for cmd is not freed until FW returns completion.
221 */
e175defe 222 if (rc <= 0) {
1957aa7f 223 struct be_dma_mem *tag_mem;
1957aa7f 224
cdde6682
JB		 225 /**
226 * PCI/DMA memory allocated and posted in non-embedded mode
227 * will have mbx_cmd_mem != NULL.
228 * Save virtual and bus addresses for the command so that it
229 * can be freed later.
230 **/
1957aa7f
JK		 231 tag_mem = &phba->ctrl.ptag_state[tag].tag_mem_state;
232 if (mbx_cmd_mem) {
233 tag_mem->size = mbx_cmd_mem->size;
234 tag_mem->va = mbx_cmd_mem->va;
235 tag_mem->dma = mbx_cmd_mem->dma;
236 } else
237 tag_mem->size = 0;
238
cdde6682
JB		 239 /* first make tag_mem_state visible to all */
240 wmb();
241 set_bit(MCC_TAG_STATE_TIMEOUT,
242 &phba->ctrl.ptag_state[tag].tag_state);
243
e175defe
JSJ		 244 beiscsi_log(phba, KERN_ERR,
245 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
246 BEISCSI_LOG_CONFIG,
247 "BC_%d : MBX Cmd Completion timed out\n");
1957aa7f 248 return -EBUSY;
1957aa7f 249 }
e175defe 250
50a4b824 251 rc = __beiscsi_mcc_compl_status(phba, tag, wrb, mbx_cmd_mem);
e175defe 252
090e2184 253 free_mcc_wrb(&phba->ctrl, tag);
e175defe
JSJ		 254 return rc;
255}
256
e175defe 257/*
88840332 258 * beiscsi_process_mbox_compl()- Check the MBX completion status
e175defe
JSJ		 259 * @ctrl: Function specific MBX data structure
260 * @compl: Completion status of MBX Command
261 *
262 * Check for the MBX completion status when BMBX method used
263 *
264 * return
265 * Success: Zero
266 * Failure: Non-Zero
267 **/
88840332
JB		 268static int beiscsi_process_mbox_compl(struct be_ctrl_info *ctrl,
269 struct be_mcc_compl *compl)
6733b39a 270{
e175defe 271 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
99bc5d55 272 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
e175defe 273 struct be_cmd_req_hdr *hdr = embedded_payload(wrb);
6694095b 274 u16 compl_status, extd_status;
6733b39a 275
c448427b
JB		 276 /**
277 * To check if valid bit is set, check the entire word as we don't know
278 * the endianness of the data (old entry is host endian while a new
279 * entry is little endian)
280 */
281 if (!compl->flags) {
282 beiscsi_log(phba, KERN_ERR,
283 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
284 "BC_%d : BMBX busy, no completion\n");
285 return -EBUSY;
286 }
287 compl->flags = le32_to_cpu(compl->flags);
288 WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
6733b39a 289
c448427b
JB		 290 /**
291 * Just swap the status to host endian;
292 * mcc tag is opaquely copied from mcc_wrb.
293 */
294 be_dws_le_to_cpu(compl, 4);
6733b39a 295 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
c448427b
JB		 296 CQE_STATUS_COMPL_MASK;
297 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
298 CQE_STATUS_EXTD_MASK;
299 /* Need to reset the entire word that houses the valid bit */
300 compl->flags = 0;
99bc5d55 301
c448427b
JB		 302 if (compl_status == MCC_STATUS_SUCCESS)
303 return 0;
304
305 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
306 "BC_%d : error in cmd completion: Subsystem : %d Opcode : %d status(compl/extd)=%d/%d\n",
307 hdr->subsystem, hdr->opcode, compl_status, extd_status);
6694095b 308 return compl_status;
6733b39a
JK		 309}
310
9c4f8b01
JB		 311static void beiscsi_process_async_link(struct beiscsi_hba *phba,
312 struct be_mcc_compl *compl)
bfead3b2 313{
9c4f8b01 314 struct be_async_event_link_state *evt;
6ea9b3b0 315
9c4f8b01 316 evt = (struct be_async_event_link_state *)compl;
99bc5d55 317
9c4f8b01
JB		 318 phba->port_speed = evt->port_speed;
319 /**
320 * Check logical link status in ASYNC event.
321 * This has been newly introduced in SKH-R Firmware 10.0.338.45.
322 **/
323 if (evt->port_link_status & BE_ASYNC_LINK_UP_MASK) {
50a4b824
JB		 324 set_bit(BEISCSI_HBA_LINK_UP, &phba->state);
325 if (test_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state))
326 beiscsi_start_boot_work(phba, BE_BOOT_INVALID_SHANDLE);
9c4f8b01
JB		 327 __beiscsi_log(phba, KERN_ERR,
328 "BC_%d : Link Up on Port %d tag 0x%x\n",
329 evt->physical_port, evt->event_tag);
330 } else {
9122e991 331 clear_bit(BEISCSI_HBA_LINK_UP, &phba->state);
9c4f8b01
JB		 332 __beiscsi_log(phba, KERN_ERR,
333 "BC_%d : Link Down on Port %d tag 0x%x\n",
334 evt->physical_port, evt->event_tag);
335 iscsi_host_for_each_session(phba->shost,
480195c2 336 beiscsi_session_fail);
bfead3b2 337 }
6733b39a
JK		 338}
339
53aefe25
JB		 340static char *beiscsi_port_misconf_event_msg[] = {
341 "Physical Link is functional.",
342 "Optics faulted/incorrectly installed/not installed - Reseat optics, if issue not resolved, replace.",
343 "Optics of two types installed - Remove one optic or install matching pair of optics.",
344 "Incompatible optics - Replace with compatible optics for card to function.",
345 "Unqualified optics - Replace with Avago optics for Warranty and Technical Support.",
346 "Uncertified optics - Replace with Avago Certified optics to enable link operation."
347};
348
349static void beiscsi_process_async_sli(struct beiscsi_hba *phba,
350 struct be_mcc_compl *compl)
351{
352 struct be_async_event_sli *async_sli;
353 u8 evt_type, state, old_state, le;
354 char *sev = KERN_WARNING;
355 char *msg = NULL;
356
357 evt_type = compl->flags >> ASYNC_TRAILER_EVENT_TYPE_SHIFT;
358 evt_type &= ASYNC_TRAILER_EVENT_TYPE_MASK;
359
360 /* processing only MISCONFIGURED physical port event */
361 if (evt_type != ASYNC_SLI_EVENT_TYPE_MISCONFIGURED)
362 return;
363
364 async_sli = (struct be_async_event_sli *)compl;
365 state = async_sli->event_data1 >>
366 (phba->fw_config.phys_port * 8) & 0xff;
367 le = async_sli->event_data2 >>
368 (phba->fw_config.phys_port * 8) & 0xff;
369
370 old_state = phba->optic_state;
371 phba->optic_state = state;
372
373 if (state >= ARRAY_SIZE(beiscsi_port_misconf_event_msg)) {
374 /* fw is reporting a state we don't know, log and return */
375 __beiscsi_log(phba, KERN_ERR,
376 "BC_%d : Port %c: Unrecognized optic state 0x%x\n",
377 phba->port_name, async_sli->event_data1);
378 return;
379 }
380
381 if (ASYNC_SLI_LINK_EFFECT_VALID(le)) {
382 /* log link effect for unqualified-4, uncertified-5 optics */
383 if (state > 3)
384 msg = (ASYNC_SLI_LINK_EFFECT_STATE(le)) ?
385 " Link is non-operational." :
386 " Link is operational.";
387 /* 1 - info */
388 if (ASYNC_SLI_LINK_EFFECT_SEV(le) == 1)
389 sev = KERN_INFO;
390 /* 2 - error */
391 if (ASYNC_SLI_LINK_EFFECT_SEV(le) == 2)
392 sev = KERN_ERR;
393 }
394
395 if (old_state != phba->optic_state)
396 __beiscsi_log(phba, sev, "BC_%d : Port %c: %s%s\n",
397 phba->port_name,
398 beiscsi_port_misconf_event_msg[state],
399 !msg ? "" : msg);
400}
401
402void beiscsi_process_async_event(struct beiscsi_hba *phba,
403 struct be_mcc_compl *compl)
404{
405 char *sev = KERN_INFO;
406 u8 evt_code;
407
408 /* interpret flags as an async trailer */
409 evt_code = compl->flags >> ASYNC_TRAILER_EVENT_CODE_SHIFT;
410 evt_code &= ASYNC_TRAILER_EVENT_CODE_MASK;
411 switch (evt_code) {
412 case ASYNC_EVENT_CODE_LINK_STATE:
9c4f8b01 413 beiscsi_process_async_link(phba, compl);
53aefe25
JB		 414 break;
415 case ASYNC_EVENT_CODE_ISCSI:
50a4b824
JB		 416 if (test_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state))
417 beiscsi_start_boot_work(phba, BE_BOOT_INVALID_SHANDLE);
53aefe25
JB		 418 sev = KERN_ERR;
419 break;
420 case ASYNC_EVENT_CODE_SLI:
421 beiscsi_process_async_sli(phba, compl);
422 break;
423 default:
424 /* event not registered */
425 sev = KERN_ERR;
426 }
427
428 beiscsi_log(phba, sev, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
9c4f8b01
JB		 429 "BC_%d : ASYNC Event %x: status 0x%08x flags 0x%08x\n",
430 evt_code, compl->status, compl->flags);
53aefe25
JB		 431}
432
2e4e8f65
JB		 433int beiscsi_process_mcc_compl(struct be_ctrl_info *ctrl,
434 struct be_mcc_compl *compl)
bfead3b2 435{
2e4e8f65
JB		 436 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
437 u16 compl_status, extd_status;
438 struct be_dma_mem *tag_mem;
439 unsigned int tag, wrb_idx;
440
2e4e8f65
JB		 441 be_dws_le_to_cpu(compl, 4);
442 tag = (compl->tag0 & MCC_Q_CMD_TAG_MASK);
443 wrb_idx = (compl->tag0 & CQE_STATUS_WRB_MASK) >> CQE_STATUS_WRB_SHIFT;
444
445 if (!test_bit(MCC_TAG_STATE_RUNNING,
446 &ctrl->ptag_state[tag].tag_state)) {
447 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX |
448 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
449 "BC_%d : MBX cmd completed but not posted\n");
450 return 0;
451 }
452
50a4b824
JB		 453 /* end MCC with this tag */
454 clear_bit(MCC_TAG_STATE_RUNNING, &ctrl->ptag_state[tag].tag_state);
455
2e4e8f65
JB		 456 if (test_bit(MCC_TAG_STATE_TIMEOUT, &ctrl->ptag_state[tag].tag_state)) {
457 beiscsi_log(phba, KERN_WARNING,
458 BEISCSI_LOG_MBOX | BEISCSI_LOG_INIT |
459 BEISCSI_LOG_CONFIG,
460 "BC_%d : MBX Completion for timeout Command from FW\n");
461 /**
462 * Check for the size before freeing resource.
463 * Only for non-embedded cmd, PCI resource is allocated.
464 **/
465 tag_mem = &ctrl->ptag_state[tag].tag_mem_state;
50a4b824 466 if (tag_mem->size) {
2e4e8f65
JB		 467 pci_free_consistent(ctrl->pdev, tag_mem->size,
468 tag_mem->va, tag_mem->dma);
50a4b824
JB		 469 tag_mem->size = 0;
470 }
090e2184 471 free_mcc_wrb(ctrl, tag);
2e4e8f65 472 return 0;
bfead3b2
JK		 473 }
474
2e4e8f65
JB		 475 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
476 CQE_STATUS_COMPL_MASK;
477 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
478 CQE_STATUS_EXTD_MASK;
479 /* The ctrl.mcc_tag_status[tag] is filled with
480 * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
481 * [7:0] = compl_status
482 */
483 ctrl->mcc_tag_status[tag] = CQE_VALID_MASK;
484 ctrl->mcc_tag_status[tag] |= (wrb_idx << CQE_STATUS_WRB_SHIFT);
485 ctrl->mcc_tag_status[tag] |= (extd_status << CQE_STATUS_ADDL_SHIFT) &
486 CQE_STATUS_ADDL_MASK;
487 ctrl->mcc_tag_status[tag] |= (compl_status & CQE_STATUS_MASK);
bfead3b2 488
50a4b824
JB		 489 if (test_bit(MCC_TAG_STATE_ASYNC, &ctrl->ptag_state[tag].tag_state)) {
490 if (ctrl->ptag_state[tag].cbfn)
491 ctrl->ptag_state[tag].cbfn(phba, tag);
492 else
6694095b
JB		 493 __beiscsi_log(phba, KERN_ERR,
494 "BC_%d : MBX ASYNC command with no callback\n");
50a4b824
JB		 495 free_mcc_wrb(ctrl, tag);
496 return 0;
497 }
498
10bcd47d
JB		 499 if (test_bit(MCC_TAG_STATE_IGNORE, &ctrl->ptag_state[tag].tag_state)) {
500 /* just check completion status and free wrb */
501 __beiscsi_mcc_compl_status(phba, tag, NULL, NULL);
502 free_mcc_wrb(ctrl, tag);
503 return 0;
504 }
505
2e4e8f65
JB		 506 wake_up_interruptible(&ctrl->mcc_wait[tag]);
507 return 0;
bfead3b2
JK		 508}
509
e175defe 510/*
88840332 511 * be_mcc_compl_poll()- Wait for MBX completion
e175defe
JSJ		 512 * @phba: driver private structure
513 *
514 * Wait till no more pending mcc requests are present
515 *
516 * return
517 * Success: 0
518 * Failure: Non-Zero
519 *
520 **/
2e4e8f65 521int be_mcc_compl_poll(struct beiscsi_hba *phba, unsigned int tag)
bfead3b2 522{
69fd6d7b 523 struct be_ctrl_info *ctrl = &phba->ctrl;
2e4e8f65
JB		 524 int i;
525
090e2184
JB		 526 if (!test_bit(MCC_TAG_STATE_RUNNING,
527 &ctrl->ptag_state[tag].tag_state)) {
528 beiscsi_log(phba, KERN_ERR,
529 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
530 "BC_%d: tag %u state not running\n", tag);
531 return 0;
532 }
bfead3b2 533 for (i = 0; i < mcc_timeout; i++) {
9122e991 534 if (beiscsi_hba_in_error(phba))
e175defe
JSJ		 535 return -EIO;
536
2e4e8f65 537 beiscsi_process_mcc_cq(phba);
090e2184 538 /* after polling, wrb and tag need to be released */
69fd6d7b 539 if (!test_bit(MCC_TAG_STATE_RUNNING,
090e2184
JB		 540 &ctrl->ptag_state[tag].tag_state)) {
541 free_mcc_wrb(ctrl, tag);
bfead3b2 542 break;
090e2184 543 }
bfead3b2
JK		 544 udelay(100);
545 }
69fd6d7b
JB		 546
547 if (i < mcc_timeout)
548 return 0;
549
550 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
551 "BC_%d : FW Timed Out\n");
9122e991 552 set_bit(BEISCSI_HBA_FW_TIMEOUT, &phba->state);
69fd6d7b
JB		 553 beiscsi_ue_detect(phba);
554 return -EBUSY;
555}
556
557void be_mcc_notify(struct beiscsi_hba *phba, unsigned int tag)
558{
559 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
560 u32 val = 0;
561
562 set_bit(MCC_TAG_STATE_RUNNING, &phba->ctrl.ptag_state[tag].tag_state);
563 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
564 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
565 /* make request available for DMA */
566 wmb();
567 iowrite32(val, phba->db_va + DB_MCCQ_OFFSET);
bfead3b2
JK		 568}
569
e175defe 570/*
88840332 571 * be_mbox_db_ready_poll()- Check ready status
e175defe
JSJ		 572 * @ctrl: Function specific MBX data structure
573 *
574 * Check for the ready status of FW to send BMBX
575 * commands to adapter.
576 *
577 * return
578 * Success: 0
579 * Failure: Non-Zero
580 **/
88840332 581static int be_mbox_db_ready_poll(struct be_ctrl_info *ctrl)
6733b39a 582{
9ec6f6b8
JB		 583 /* wait 30s for generic non-flash MBOX operation */
584#define BEISCSI_MBX_RDY_BIT_TIMEOUT 30000
6733b39a 585 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
e175defe 586 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
92665a66 587 unsigned long timeout;
6733b39a
JK		 588 u32 ready;
589
6ac999ef
JB		 590 /*
591 * This BMBX busy wait path is used during init only.
592 * For the commands executed during init, 5s should suffice.
593 */
594 timeout = jiffies + msecs_to_jiffies(BEISCSI_MBX_RDY_BIT_TIMEOUT);
595 do {
9122e991 596 if (beiscsi_hba_in_error(phba))
6ac999ef 597 return -EIO;
7a158003 598
6ac999ef
JB		 599 ready = ioread32(db);
600 if (ready == 0xffffffff)
601 return -EIO;
e175defe 602
6ac999ef
JB		 603 ready &= MPU_MAILBOX_DB_RDY_MASK;
604 if (ready)
605 return 0;
6733b39a 606
6ac999ef
JB		 607 if (time_after(jiffies, timeout))
608 break;
3c9e36a9
JB		 609 /* 1ms sleep is enough in most cases */
610 schedule_timeout_uninterruptible(msecs_to_jiffies(1));
6ac999ef 611 } while (!ready);
92665a66 612
6ac999ef
JB		 613 beiscsi_log(phba, KERN_ERR,
614 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
615 "BC_%d : FW Timed Out\n");
9122e991 616 set_bit(BEISCSI_HBA_FW_TIMEOUT, &phba->state);
6ac999ef 617 beiscsi_ue_detect(phba);
6ac999ef 618 return -EBUSY;
6733b39a
JK		 619}
620
e175defe
JSJ		 621/*
622 * be_mbox_notify: Notify adapter of new BMBX command
623 * @ctrl: Function specific MBX data structure
624 *
625 * Ring doorbell to inform adapter of a BMBX command
626 * to process
627 *
628 * return
629 * Success: 0
630 * Failure: Non-Zero
631 **/
480195c2 632static int be_mbox_notify(struct be_ctrl_info *ctrl)
6733b39a
JK		 633{
634 int status;
635 u32 val = 0;
636 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
637 struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
638 struct be_mcc_mailbox *mbox = mbox_mem->va;
6733b39a 639
88840332 640 status = be_mbox_db_ready_poll(ctrl);
1e234bbb
JK		 641 if (status)
642 return status;
643
6733b39a
JK		 644 val &= ~MPU_MAILBOX_DB_RDY_MASK;
645 val |= MPU_MAILBOX_DB_HI_MASK;
646 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
647 iowrite32(val, db);
648
88840332 649 status = be_mbox_db_ready_poll(ctrl);
e175defe 650 if (status)
6733b39a 651 return status;
e175defe 652
6733b39a
JK		 653 val = 0;
654 val &= ~MPU_MAILBOX_DB_RDY_MASK;
655 val &= ~MPU_MAILBOX_DB_HI_MASK;
656 val |= (u32) (mbox_mem->dma >> 4) << 2;
657 iowrite32(val, db);
658
88840332 659 status = be_mbox_db_ready_poll(ctrl);
e175defe 660 if (status)
6733b39a 661 return status;
e175defe 662
6ac999ef
JB		 663 /* RDY is set; small delay before CQE read. */
664 udelay(1);
665
a264f5e8
JB		 666 status = beiscsi_process_mbox_compl(ctrl, &mbox->compl);
667 return status;
bfead3b2
JK		 668}
669
6733b39a
JK		 670void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
671 bool embedded, u8 sge_cnt)
672{
673 if (embedded)
674 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
675 else
676 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
677 MCC_WRB_SGE_CNT_SHIFT;
678 wrb->payload_length = payload_len;
679 be_dws_cpu_to_le(wrb, 8);
680}
681
682void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
683 u8 subsystem, u8 opcode, int cmd_len)
684{
685 req_hdr->opcode = opcode;
686 req_hdr->subsystem = subsystem;
687 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
e175defe 688 req_hdr->timeout = BEISCSI_FW_MBX_TIMEOUT;
6733b39a
JK		 689}
690
691static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
692 struct be_dma_mem *mem)
693{
694 int i, buf_pages;
695 u64 dma = (u64) mem->dma;
696
697 buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
698 for (i = 0; i < buf_pages; i++) {
699 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
700 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
701 dma += PAGE_SIZE_4K;
702 }
703}
704
705static u32 eq_delay_to_mult(u32 usec_delay)
706{
707#define MAX_INTR_RATE 651042
708 const u32 round = 10;
709 u32 multiplier;
710
711 if (usec_delay == 0)
712 multiplier = 0;
713 else {
714 u32 interrupt_rate = 1000000 / usec_delay;
715 if (interrupt_rate == 0)
716 multiplier = 1023;
717 else {
718 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
719 multiplier /= interrupt_rate;
720 multiplier = (multiplier + round / 2) / round;
721 multiplier = min(multiplier, (u32) 1023);
722 }
723 }
724 return multiplier;
725}
726
727struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
728{
729 return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
730}
731
732int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
733 struct be_queue_info *eq, int eq_delay)
734{
735 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
736 struct be_cmd_req_eq_create *req = embedded_payload(wrb);
737 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
738 struct be_dma_mem *q_mem = &eq->dma_mem;
739 int status;
740
c03a50f7 741 mutex_lock(&ctrl->mbox_lock);
6733b39a
JK		 742 memset(wrb, 0, sizeof(*wrb));
743
744 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
745
746 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
747 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
748
749 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
750
751 AMAP_SET_BITS(struct amap_eq_context, func, req->context,
752 PCI_FUNC(ctrl->pdev->devfn));
753 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
754 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
755 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
756 __ilog2_u32(eq->len / 256));
757 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
758 eq_delay_to_mult(eq_delay));
759 be_dws_cpu_to_le(req->context, sizeof(req->context));
760
761 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
762
763 status = be_mbox_notify(ctrl);
764 if (!status) {
765 eq->id = le16_to_cpu(resp->eq_id);
766 eq->created = true;
767 }
c03a50f7 768 mutex_unlock(&ctrl->mbox_lock);
6733b39a
JK		 769 return status;
770}
771
0283fbb1
JK		 772/**
773 * be_cmd_fw_initialize()- Initialize FW
774 * @ctrl: Pointer to function control structure
775 *
776 * Send FW initialize pattern for the function.
777 *
778 * return
779 * Success: 0
780 * Failure: Non-Zero value
781 **/
6733b39a
JK		 782int be_cmd_fw_initialize(struct be_ctrl_info *ctrl)
783{
784 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
99bc5d55 785 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 786 int status;
787 u8 *endian_check;
788
c03a50f7 789 mutex_lock(&ctrl->mbox_lock);
6733b39a
JK		 790 memset(wrb, 0, sizeof(*wrb));
791
792 endian_check = (u8 *) wrb;
793 *endian_check++ = 0xFF;
794 *endian_check++ = 0x12;
795 *endian_check++ = 0x34;
796 *endian_check++ = 0xFF;
797 *endian_check++ = 0xFF;
798 *endian_check++ = 0x56;
799 *endian_check++ = 0x78;
800 *endian_check++ = 0xFF;
801 be_dws_cpu_to_le(wrb, sizeof(*wrb));
802
803 status = be_mbox_notify(ctrl);
804 if (status)
99bc5d55
JSJ		 805 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
806 "BC_%d : be_cmd_fw_initialize Failed\n");
6733b39a 807
c03a50f7 808 mutex_unlock(&ctrl->mbox_lock);
6733b39a
JK		 809 return status;
810}
811
0283fbb1
JK		 812/**
813 * be_cmd_fw_uninit()- Uinitialize FW
814 * @ctrl: Pointer to function control structure
815 *
816 * Send FW uninitialize pattern for the function
817 *
818 * return
819 * Success: 0
820 * Failure: Non-Zero value
821 **/
822int be_cmd_fw_uninit(struct be_ctrl_info *ctrl)
823{
824 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
825 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
826 int status;
827 u8 *endian_check;
828
c03a50f7 829 mutex_lock(&ctrl->mbox_lock);
0283fbb1
JK		 830 memset(wrb, 0, sizeof(*wrb));
831
832 endian_check = (u8 *) wrb;
833 *endian_check++ = 0xFF;
834 *endian_check++ = 0xAA;
835 *endian_check++ = 0xBB;
836 *endian_check++ = 0xFF;
837 *endian_check++ = 0xFF;
838 *endian_check++ = 0xCC;
839 *endian_check++ = 0xDD;
840 *endian_check = 0xFF;
841
842 be_dws_cpu_to_le(wrb, sizeof(*wrb));
843
844 status = be_mbox_notify(ctrl);
845 if (status)
846 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
847 "BC_%d : be_cmd_fw_uninit Failed\n");
848
c03a50f7 849 mutex_unlock(&ctrl->mbox_lock);
0283fbb1
JK		 850 return status;
851}
852
6733b39a
JK		 853int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
854 struct be_queue_info *cq, struct be_queue_info *eq,
855 bool sol_evts, bool no_delay, int coalesce_wm)
856{
857 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
858 struct be_cmd_req_cq_create *req = embedded_payload(wrb);
859 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
99bc5d55 860 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 861 struct be_dma_mem *q_mem = &cq->dma_mem;
862 void *ctxt = &req->context;
863 int status;
864
c03a50f7 865 mutex_lock(&ctrl->mbox_lock);
6733b39a
JK		 866 memset(wrb, 0, sizeof(*wrb));
867
868 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
869
870 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
871 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
6733b39a
JK		 872
873 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
2c9dfd36 874 if (is_chip_be2_be3r(phba)) {
eaae5267
JSJ		 875 AMAP_SET_BITS(struct amap_cq_context, coalescwm,
876 ctxt, coalesce_wm);
877 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
878 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
879 __ilog2_u32(cq->len / 256));
880 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
881 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
882 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
883 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
884 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
885 AMAP_SET_BITS(struct amap_cq_context, func, ctxt,
886 PCI_FUNC(ctrl->pdev->devfn));
2c9dfd36
JK		 887 } else {
888 req->hdr.version = MBX_CMD_VER2;
889 req->page_size = 1;
890 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
891 ctxt, coalesce_wm);
892 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay,
893 ctxt, no_delay);
894 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
895 __ilog2_u32(cq->len / 256));
896 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
897 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
898 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
899 AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1);
eaae5267 900 }
6733b39a 901
6733b39a
JK		 902 be_dws_cpu_to_le(ctxt, sizeof(req->context));
903
904 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
905
906 status = be_mbox_notify(ctrl);
907 if (!status) {
908 cq->id = le16_to_cpu(resp->cq_id);
909 cq->created = true;
910 } else
99bc5d55
JSJ		 911 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
912 "BC_%d : In be_cmd_cq_create, status=ox%08x\n",
913 status);
914
c03a50f7 915 mutex_unlock(&ctrl->mbox_lock);
6733b39a
JK		 916
917 return status;
918}
919
920static u32 be_encoded_q_len(int q_len)
921{
922 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
923 if (len_encoded == 16)
924 len_encoded = 0;
925 return len_encoded;
926}
bfead3b2 927
35e66019 928int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba,
bfead3b2
JK		 929 struct be_queue_info *mccq,
930 struct be_queue_info *cq)
931{
932 struct be_mcc_wrb *wrb;
53aefe25 933 struct be_cmd_req_mcc_create_ext *req;
bfead3b2
JK		 934 struct be_dma_mem *q_mem = &mccq->dma_mem;
935 struct be_ctrl_info *ctrl;
936 void *ctxt;
937 int status;
938
c03a50f7 939 mutex_lock(&phba->ctrl.mbox_lock);
bfead3b2
JK		 940 ctrl = &phba->ctrl;
941 wrb = wrb_from_mbox(&ctrl->mbox_mem);
37609766 942 memset(wrb, 0, sizeof(*wrb));
bfead3b2
JK		 943 req = embedded_payload(wrb);
944 ctxt = &req->context;
945
946 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
947
948 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
53aefe25 949 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
bfead3b2
JK		 950
951 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
53aefe25
JB		 952 req->async_evt_bitmap = 1 << ASYNC_EVENT_CODE_LINK_STATE;
953 req->async_evt_bitmap |= 1 << ASYNC_EVENT_CODE_ISCSI;
954 req->async_evt_bitmap |= 1 << ASYNC_EVENT_CODE_SLI;
bfead3b2
JK		 955
956 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt,
957 PCI_FUNC(phba->pcidev->devfn));
958 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
959 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
960 be_encoded_q_len(mccq->len));
961 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
962
963 be_dws_cpu_to_le(ctxt, sizeof(req->context));
964
965 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
966
a264f5e8 967 status = be_mbox_notify(ctrl);
bfead3b2
JK		 968 if (!status) {
969 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
970 mccq->id = le16_to_cpu(resp->id);
971 mccq->created = true;
972 }
c03a50f7 973 mutex_unlock(&phba->ctrl.mbox_lock);
bfead3b2
JK		 974
975 return status;
976}
977
6733b39a
JK		 978int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
979 int queue_type)
980{
981 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
982 struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
99bc5d55 983 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 984 u8 subsys = 0, opcode = 0;
985 int status;
986
99bc5d55
JSJ		 987 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
988 "BC_%d : In beiscsi_cmd_q_destroy "
989 "queue_type : %d\n", queue_type);
990
c03a50f7 991 mutex_lock(&ctrl->mbox_lock);
6733b39a
JK		 992 memset(wrb, 0, sizeof(*wrb));
993 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
994
995 switch (queue_type) {
996 case QTYPE_EQ:
997 subsys = CMD_SUBSYSTEM_COMMON;
998 opcode = OPCODE_COMMON_EQ_DESTROY;
999 break;
1000 case QTYPE_CQ:
1001 subsys = CMD_SUBSYSTEM_COMMON;
1002 opcode = OPCODE_COMMON_CQ_DESTROY;
1003 break;
bfead3b2
JK		 1004 case QTYPE_MCCQ:
1005 subsys = CMD_SUBSYSTEM_COMMON;
1006 opcode = OPCODE_COMMON_MCC_DESTROY;
1007 break;
6733b39a
JK		 1008 case QTYPE_WRBQ:
1009 subsys = CMD_SUBSYSTEM_ISCSI;
1010 opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY;
1011 break;
1012 case QTYPE_DPDUQ:
1013 subsys = CMD_SUBSYSTEM_ISCSI;
1014 opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY;
1015 break;
1016 case QTYPE_SGL:
1017 subsys = CMD_SUBSYSTEM_ISCSI;
1018 opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES;
1019 break;
1020 default:
c03a50f7 1021 mutex_unlock(&ctrl->mbox_lock);
6733b39a 1022 BUG();
d3ad2bb3 1023 return -ENXIO;
6733b39a
JK		 1024 }
1025 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
1026 if (queue_type != QTYPE_SGL)
1027 req->id = cpu_to_le16(q->id);
1028
1029 status = be_mbox_notify(ctrl);
1030
c03a50f7 1031 mutex_unlock(&ctrl->mbox_lock);
6733b39a
JK		 1032 return status;
1033}
1034
8a86e833
JK		 1035/**
1036 * be_cmd_create_default_pdu_queue()- Create DEFQ for the adapter
1037 * @ctrl: ptr to ctrl_info
1038 * @cq: Completion Queue
1039 * @dq: Default Queue
1040 * @lenght: ring size
1041 * @entry_size: size of each entry in DEFQ
1042 * @is_header: Header or Data DEFQ
1043 * @ulp_num: Bind to which ULP
1044 *
1045 * Create HDR/Data DEFQ for the passed ULP. Unsol PDU are posted
1046 * on this queue by the FW
1047 *
1048 * return
1049 * Success: 0
1050 * Failure: Non-Zero Value
1051 *
1052 **/
6733b39a
JK		 1053int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
1054 struct be_queue_info *cq,
1055 struct be_queue_info *dq, int length,
8a86e833
JK		 1056 int entry_size, uint8_t is_header,
1057 uint8_t ulp_num)
6733b39a
JK		 1058{
1059 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1060 struct be_defq_create_req *req = embedded_payload(wrb);
1061 struct be_dma_mem *q_mem = &dq->dma_mem;
ef9e1b9b 1062 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 1063 void *ctxt = &req->context;
1064 int status;
1065
c03a50f7 1066 mutex_lock(&ctrl->mbox_lock);
6733b39a
JK		 1067 memset(wrb, 0, sizeof(*wrb));
1068
1069 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1070
1071 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1072 OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req));
1073
1074 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
8a86e833
JK		 1075 if (phba->fw_config.dual_ulp_aware) {
1076 req->ulp_num = ulp_num;
1077 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
1078 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
1079 }
ef9e1b9b
JK		 1080
1081 if (is_chip_be2_be3r(phba)) {
1082 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1083 rx_pdid, ctxt, 0);
1084 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1085 rx_pdid_valid, ctxt, 1);
1086 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1087 pci_func_id, ctxt, PCI_FUNC(ctrl->pdev->devfn));
1088 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1089 ring_size, ctxt,
1090 be_encoded_q_len(length /
1091 sizeof(struct phys_addr)));
1092 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1093 default_buffer_size, ctxt, entry_size);
1094 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1095 cq_id_recv, ctxt, cq->id);
1096 } else {
1097 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1098 rx_pdid, ctxt, 0);
1099 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1100 rx_pdid_valid, ctxt, 1);
1101 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1102 ring_size, ctxt,
1103 be_encoded_q_len(length /
1104 sizeof(struct phys_addr)));
1105 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1106 default_buffer_size, ctxt, entry_size);
1107 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1108 cq_id_recv, ctxt, cq->id);
1109 }
6733b39a
JK		 1110
1111 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1112
1113 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1114
1115 status = be_mbox_notify(ctrl);
1116 if (!status) {
8a86e833 1117 struct be_ring *defq_ring;
6733b39a
JK		 1118 struct be_defq_create_resp *resp = embedded_payload(wrb);
1119
1120 dq->id = le16_to_cpu(resp->id);
1121 dq->created = true;
8a86e833
JK		 1122 if (is_header)
1123 defq_ring = &phba->phwi_ctrlr->default_pdu_hdr[ulp_num];
1124 else
1125 defq_ring = &phba->phwi_ctrlr->
1126 default_pdu_data[ulp_num];
1127
1128 defq_ring->id = dq->id;
1129
1130 if (!phba->fw_config.dual_ulp_aware) {
1131 defq_ring->ulp_num = BEISCSI_ULP0;
1132 defq_ring->doorbell_offset = DB_RXULP0_OFFSET;
1133 } else {
1134 defq_ring->ulp_num = resp->ulp_num;
1135 defq_ring->doorbell_offset = resp->doorbell_offset;
1136 }
6733b39a 1137 }
c03a50f7 1138 mutex_unlock(&ctrl->mbox_lock);
6733b39a
JK		 1139
1140 return status;
1141}
1142
4eea99d5
JK		 1143/**
1144 * be_cmd_wrbq_create()- Create WRBQ
1145 * @ctrl: ptr to ctrl_info
1146 * @q_mem: memory details for the queue
1147 * @wrbq: queue info
1148 * @pwrb_context: ptr to wrb_context
1149 * @ulp_num: ULP on which the WRBQ is to be created
1150 *
1151 * Create WRBQ on the passed ULP_NUM.
1152 *
1153 **/
1154int be_cmd_wrbq_create(struct be_ctrl_info *ctrl,
1155 struct be_dma_mem *q_mem,
1156 struct be_queue_info *wrbq,
1157 struct hwi_wrb_context *pwrb_context,
1158 uint8_t ulp_num)
6733b39a
JK		 1159{
1160 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1161 struct be_wrbq_create_req *req = embedded_payload(wrb);
1162 struct be_wrbq_create_resp *resp = embedded_payload(wrb);
4eea99d5 1163 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 1164 int status;
1165
c03a50f7 1166 mutex_lock(&ctrl->mbox_lock);
6733b39a
JK		 1167 memset(wrb, 0, sizeof(*wrb));
1168
1169 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1170
1171 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1172 OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req));
1173 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
4eea99d5
JK		 1174
1175 if (phba->fw_config.dual_ulp_aware) {
1176 req->ulp_num = ulp_num;
1177 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
1178 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
1179 }
1180
6733b39a
JK		 1181 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1182
1183 status = be_mbox_notify(ctrl);
bfead3b2 1184 if (!status) {
6733b39a 1185 wrbq->id = le16_to_cpu(resp->cid);
bfead3b2 1186 wrbq->created = true;
4eea99d5
JK		 1187
1188 pwrb_context->cid = wrbq->id;
1189 if (!phba->fw_config.dual_ulp_aware) {
1190 pwrb_context->doorbell_offset = DB_TXULP0_OFFSET;
1191 pwrb_context->ulp_num = BEISCSI_ULP0;
1192 } else {
1193 pwrb_context->ulp_num = resp->ulp_num;
1194 pwrb_context->doorbell_offset = resp->doorbell_offset;
1195 }
bfead3b2 1196 }
c03a50f7 1197 mutex_unlock(&ctrl->mbox_lock);
6733b39a
JK		 1198 return status;
1199}
1200
15a90fe0
JK		 1201int be_cmd_iscsi_post_template_hdr(struct be_ctrl_info *ctrl,
1202 struct be_dma_mem *q_mem)
1203{
1204 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1205 struct be_post_template_pages_req *req = embedded_payload(wrb);
1206 int status;
1207
c03a50f7 1208 mutex_lock(&ctrl->mbox_lock);
15a90fe0
JK		 1209
1210 memset(wrb, 0, sizeof(*wrb));
1211 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1212 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1213 OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS,
1214 sizeof(*req));
1215
1216 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1217 req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
1218 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1219
1220 status = be_mbox_notify(ctrl);
c03a50f7 1221 mutex_unlock(&ctrl->mbox_lock);
15a90fe0
JK		 1222 return status;
1223}
1224
1225int be_cmd_iscsi_remove_template_hdr(struct be_ctrl_info *ctrl)
1226{
1227 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1228 struct be_remove_template_pages_req *req = embedded_payload(wrb);
1229 int status;
1230
c03a50f7 1231 mutex_lock(&ctrl->mbox_lock);
15a90fe0
JK		 1232
1233 memset(wrb, 0, sizeof(*wrb));
1234 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1235 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1236 OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS,
1237 sizeof(*req));
1238
1239 req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
1240
1241 status = be_mbox_notify(ctrl);
c03a50f7 1242 mutex_unlock(&ctrl->mbox_lock);
15a90fe0
JK		 1243 return status;
1244}
1245
6733b39a
JK		 1246int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
1247 struct be_dma_mem *q_mem,
1248 u32 page_offset, u32 num_pages)
1249{
1250 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1251 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
99bc5d55 1252 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 1253 int status;
1254 unsigned int curr_pages;
1255 u32 internal_page_offset = 0;
1256 u32 temp_num_pages = num_pages;
1257
1258 if (num_pages == 0xff)
1259 num_pages = 1;
1260
c03a50f7 1261 mutex_lock(&ctrl->mbox_lock);
6733b39a
JK		 1262 do {
1263 memset(wrb, 0, sizeof(*wrb));
1264 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1265 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1266 OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES,
1267 sizeof(*req));
1268 curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req,
1269 pages);
1270 req->num_pages = min(num_pages, curr_pages);
1271 req->page_offset = page_offset;
1272 be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem);
1273 q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE);
1274 internal_page_offset += req->num_pages;
1275 page_offset += req->num_pages;
1276 num_pages -= req->num_pages;
1277
1278 if (temp_num_pages == 0xff)
1279 req->num_pages = temp_num_pages;
1280
1281 status = be_mbox_notify(ctrl);
1282 if (status) {
99bc5d55
JSJ		 1283 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1284 "BC_%d : FW CMD to map iscsi frags failed.\n");
1285
6733b39a
JK		 1286 goto error;
1287 }
1288 } while (num_pages > 0);
1289error:
c03a50f7 1290 mutex_unlock(&ctrl->mbox_lock);
6733b39a
JK		 1291 if (status != 0)
1292 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
1293 return status;
1294}
e5285860
JK		 1295
1296int beiscsi_cmd_reset_function(struct beiscsi_hba *phba)
1297{
1298 struct be_ctrl_info *ctrl = &phba->ctrl;
1299 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1300 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
1301 int status;
1302
c03a50f7 1303 mutex_lock(&ctrl->mbox_lock);
e5285860
JK		 1304
1305 req = embedded_payload(wrb);
1306 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1307 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1308 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
a264f5e8 1309 status = be_mbox_notify(ctrl);
e5285860 1310
c03a50f7 1311 mutex_unlock(&ctrl->mbox_lock);
e5285860
JK		 1312 return status;
1313}
6f72238e
JSJ		 1314
1315/**
1316 * be_cmd_set_vlan()- Configure VLAN paramters on the adapter
1317 * @phba: device priv structure instance
1318 * @vlan_tag: TAG to be set
1319 *
1320 * Set the VLAN_TAG for the adapter or Disable VLAN on adapter
1321 *
1322 * returns
1323 * TAG for the MBX Cmd
1324 * **/
1325int be_cmd_set_vlan(struct beiscsi_hba *phba,
1326 uint16_t vlan_tag)
1327{
090e2184 1328 unsigned int tag;
6f72238e
JSJ		 1329 struct be_mcc_wrb *wrb;
1330 struct be_cmd_set_vlan_req *req;
1331 struct be_ctrl_info *ctrl = &phba->ctrl;
1332
c03a50f7
JB		 1333 if (mutex_lock_interruptible(&ctrl->mbox_lock))
1334 return 0;
090e2184
JB		 1335 wrb = alloc_mcc_wrb(phba, &tag);
1336 if (!wrb) {
c03a50f7 1337 mutex_unlock(&ctrl->mbox_lock);
090e2184 1338 return 0;
6f72238e
JSJ		 1339 }
1340
6f72238e 1341 req = embedded_payload(wrb);
6f72238e
JSJ		 1342 be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0);
1343 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1344 OPCODE_COMMON_ISCSI_NTWK_SET_VLAN,
1345 sizeof(*req));
1346
1347 req->interface_hndl = phba->interface_handle;
1348 req->vlan_priority = vlan_tag;
1349
cdde6682 1350 be_mcc_notify(phba, tag);
c03a50f7 1351 mutex_unlock(&ctrl->mbox_lock);
6f72238e
JSJ		 1352
1353 return tag;
1354}
6694095b 1355
480195c2
JB		 1356int beiscsi_check_supported_fw(struct be_ctrl_info *ctrl,
1357 struct beiscsi_hba *phba)
1358{
1359 struct be_dma_mem nonemb_cmd;
1360 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1361 struct be_mgmt_controller_attributes *req;
1362 struct be_sge *sge = nonembedded_sgl(wrb);
1363 int status = 0;
1364
1365 nonemb_cmd.va = pci_alloc_consistent(ctrl->pdev,
1366 sizeof(struct be_mgmt_controller_attributes),
1367 &nonemb_cmd.dma);
1368 if (nonemb_cmd.va == NULL) {
1369 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1370 "BG_%d : pci_alloc_consistent failed in %s\n",
1371 __func__);
1372 return -ENOMEM;
1373 }
1374 nonemb_cmd.size = sizeof(struct be_mgmt_controller_attributes);
1375 req = nonemb_cmd.va;
1376 memset(req, 0, sizeof(*req));
1377 mutex_lock(&ctrl->mbox_lock);
1378 memset(wrb, 0, sizeof(*wrb));
1379 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1);
1380 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1381 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, sizeof(*req));
1382 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd.dma));
1383 sge->pa_lo = cpu_to_le32(nonemb_cmd.dma & 0xFFFFFFFF);
1384 sge->len = cpu_to_le32(nonemb_cmd.size);
1385 status = be_mbox_notify(ctrl);
1386 if (!status) {
1387 struct be_mgmt_controller_attributes_resp *resp = nonemb_cmd.va;
1388
1389 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1390 "BG_%d : Firmware Version of CMD : %s\n"
1391 "Firmware Version is : %s\n"
1392 "Developer Build, not performing version check...\n",
1393 resp->params.hba_attribs
1394 .flashrom_version_string,
1395 resp->params.hba_attribs.
1396 firmware_version_string);
1397
1398 phba->fw_config.iscsi_features =
1399 resp->params.hba_attribs.iscsi_features;
1400 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1401 "BM_%d : phba->fw_config.iscsi_features = %d\n",
1402 phba->fw_config.iscsi_features);
1403 memcpy(phba->fw_ver_str, resp->params.hba_attribs.
1404 firmware_version_string, BEISCSI_VER_STRLEN);
1405 } else
1406 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1407 "BG_%d : Failed in beiscsi_check_supported_fw\n");
1408 mutex_unlock(&ctrl->mbox_lock);
1409 if (nonemb_cmd.va)
1410 pci_free_consistent(ctrl->pdev, nonemb_cmd.size,
1411 nonemb_cmd.va, nonemb_cmd.dma);
1412
1413 return status;
1414}
1415
1416/**
1417 * beiscsi_get_fw_config()- Get the FW config for the function
1418 * @ctrl: ptr to Ctrl Info
1419 * @phba: ptr to the dev priv structure
1420 *
1421 * Get the FW config and resources available for the function.
1422 * The resources are created based on the count received here.
1423 *
1424 * return
1425 * Success: 0
1426 * Failure: Non-Zero Value
1427 **/
1428int beiscsi_get_fw_config(struct be_ctrl_info *ctrl,
1429 struct beiscsi_hba *phba)
1430{
1431 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1432 struct be_fw_cfg *pfw_cfg = embedded_payload(wrb);
1433 uint32_t cid_count, icd_count;
1434 int status = -EINVAL;
1435 uint8_t ulp_num = 0;
1436
1437 mutex_lock(&ctrl->mbox_lock);
1438 memset(wrb, 0, sizeof(*wrb));
1439 be_wrb_hdr_prepare(wrb, sizeof(*pfw_cfg), true, 0);
1440
1441 be_cmd_hdr_prepare(&pfw_cfg->hdr, CMD_SUBSYSTEM_COMMON,
1442 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
1443 EMBED_MBX_MAX_PAYLOAD_SIZE);
1444
1445 if (be_mbox_notify(ctrl)) {
1446 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1447 "BG_%d : Failed in beiscsi_get_fw_config\n");
1448 goto fail_init;
1449 }
1450
1451 /* FW response formats depend on port id */
1452 phba->fw_config.phys_port = pfw_cfg->phys_port;
1453 if (phba->fw_config.phys_port >= BEISCSI_PHYS_PORT_MAX) {
1454 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1455 "BG_%d : invalid physical port id %d\n",
1456 phba->fw_config.phys_port);
1457 goto fail_init;
1458 }
1459
1460 /* populate and check FW config against min and max values */
1461 if (!is_chip_be2_be3r(phba)) {
1462 phba->fw_config.eqid_count = pfw_cfg->eqid_count;
1463 phba->fw_config.cqid_count = pfw_cfg->cqid_count;
1464 if (phba->fw_config.eqid_count == 0 ||
1465 phba->fw_config.eqid_count > 2048) {
1466 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1467 "BG_%d : invalid EQ count %d\n",
1468 phba->fw_config.eqid_count);
1469 goto fail_init;
1470 }
1471 if (phba->fw_config.cqid_count == 0 ||
1472 phba->fw_config.cqid_count > 4096) {
1473 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1474 "BG_%d : invalid CQ count %d\n",
1475 phba->fw_config.cqid_count);
1476 goto fail_init;
1477 }
1478 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1479 "BG_%d : EQ_Count : %d CQ_Count : %d\n",
1480 phba->fw_config.eqid_count,
1481 phba->fw_config.cqid_count);
1482 }
1483
1484 /**
1485 * Check on which all ULP iSCSI Protocol is loaded.
1486 * Set the Bit for those ULP. This set flag is used
1487 * at all places in the code to check on which ULP
1488 * iSCSi Protocol is loaded
1489 **/
1490 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
1491 if (pfw_cfg->ulp[ulp_num].ulp_mode &
1492 BEISCSI_ULP_ISCSI_INI_MODE) {
1493 set_bit(ulp_num, &phba->fw_config.ulp_supported);
1494
1495 /* Get the CID, ICD and Chain count for each ULP */
1496 phba->fw_config.iscsi_cid_start[ulp_num] =
1497 pfw_cfg->ulp[ulp_num].sq_base;
1498 phba->fw_config.iscsi_cid_count[ulp_num] =
1499 pfw_cfg->ulp[ulp_num].sq_count;
1500
1501 phba->fw_config.iscsi_icd_start[ulp_num] =
1502 pfw_cfg->ulp[ulp_num].icd_base;
1503 phba->fw_config.iscsi_icd_count[ulp_num] =
1504 pfw_cfg->ulp[ulp_num].icd_count;
1505
1506 phba->fw_config.iscsi_chain_start[ulp_num] =
1507 pfw_cfg->chain_icd[ulp_num].chain_base;
1508 phba->fw_config.iscsi_chain_count[ulp_num] =
1509 pfw_cfg->chain_icd[ulp_num].chain_count;
1510
1511 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1512 "BG_%d : Function loaded on ULP : %d\n"
1513 "\tiscsi_cid_count : %d\n"
1514 "\tiscsi_cid_start : %d\n"
1515 "\t iscsi_icd_count : %d\n"
1516 "\t iscsi_icd_start : %d\n",
1517 ulp_num,
1518 phba->fw_config.
1519 iscsi_cid_count[ulp_num],
1520 phba->fw_config.
1521 iscsi_cid_start[ulp_num],
1522 phba->fw_config.
1523 iscsi_icd_count[ulp_num],
1524 phba->fw_config.
1525 iscsi_icd_start[ulp_num]);
1526 }
1527 }
1528
1529 if (phba->fw_config.ulp_supported == 0) {
1530 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1531 "BG_%d : iSCSI initiator mode not set: ULP0 %x ULP1 %x\n",
1532 pfw_cfg->ulp[BEISCSI_ULP0].ulp_mode,
1533 pfw_cfg->ulp[BEISCSI_ULP1].ulp_mode);
1534 goto fail_init;
1535 }
1536
1537 /**
1538 * ICD is shared among ULPs. Use icd_count of any one loaded ULP
1539 **/
1540 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
1541 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
1542 break;
1543 icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
1544 if (icd_count == 0 || icd_count > 65536) {
1545 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1546 "BG_%d: invalid ICD count %d\n", icd_count);
1547 goto fail_init;
1548 }
1549
1550 cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) +
1551 BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1);
1552 if (cid_count == 0 || cid_count > 4096) {
1553 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1554 "BG_%d: invalid CID count %d\n", cid_count);
1555 goto fail_init;
1556 }
1557
1558 /**
1559 * Check FW is dual ULP aware i.e. can handle either
1560 * of the protocols.
1561 */
1562 phba->fw_config.dual_ulp_aware = (pfw_cfg->function_mode &
1563 BEISCSI_FUNC_DUA_MODE);
1564
1565 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1566 "BG_%d : DUA Mode : 0x%x\n",
1567 phba->fw_config.dual_ulp_aware);
1568
1569 /* all set, continue using this FW config */
1570 status = 0;
1571fail_init:
1572 mutex_unlock(&ctrl->mbox_lock);
1573 return status;
1574}
1575
1576/**
1577 * beiscsi_get_port_name()- Get port name for the function
1578 * @ctrl: ptr to Ctrl Info
1579 * @phba: ptr to the dev priv structure
1580 *
1581 * Get the alphanumeric character for port
1582 *
1583 **/
1584int beiscsi_get_port_name(struct be_ctrl_info *ctrl, struct beiscsi_hba *phba)
1585{
1586 int ret = 0;
1587 struct be_mcc_wrb *wrb;
1588 struct be_cmd_get_port_name *ioctl;
1589
1590 mutex_lock(&ctrl->mbox_lock);
1591 wrb = wrb_from_mbox(&ctrl->mbox_mem);
1592 memset(wrb, 0, sizeof(*wrb));
1593 ioctl = embedded_payload(wrb);
1594
1595 be_wrb_hdr_prepare(wrb, sizeof(*ioctl), true, 0);
1596 be_cmd_hdr_prepare(&ioctl->h.req_hdr, CMD_SUBSYSTEM_COMMON,
1597 OPCODE_COMMON_GET_PORT_NAME,
1598 EMBED_MBX_MAX_PAYLOAD_SIZE);
1599 ret = be_mbox_notify(ctrl);
1600 phba->port_name = 0;
1601 if (!ret) {
1602 phba->port_name = ioctl->p.resp.port_names >>
1603 (phba->fw_config.phys_port * 8) & 0xff;
1604 } else {
1605 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1606 "BG_%d : GET_PORT_NAME ret 0x%x status 0x%x\n",
1607 ret, ioctl->h.resp_hdr.status);
1608 }
1609
1610 if (phba->port_name == 0)
1611 phba->port_name = '?';
1612
1613 mutex_unlock(&ctrl->mbox_lock);
1614 return ret;
1615}
1616
6694095b
JB		 1617int beiscsi_set_uer_feature(struct beiscsi_hba *phba)
1618{
1619 struct be_ctrl_info *ctrl = &phba->ctrl;
1620 struct be_cmd_set_features *ioctl;
1621 struct be_mcc_wrb *wrb;
1622 int ret = 0;
1623
1624 mutex_lock(&ctrl->mbox_lock);
1625 wrb = wrb_from_mbox(&ctrl->mbox_mem);
1626 memset(wrb, 0, sizeof(*wrb));
1627 ioctl = embedded_payload(wrb);
1628
1629 be_wrb_hdr_prepare(wrb, sizeof(*ioctl), true, 0);
1630 be_cmd_hdr_prepare(&ioctl->h.req_hdr, CMD_SUBSYSTEM_COMMON,
1631 OPCODE_COMMON_SET_FEATURES,
1632 EMBED_MBX_MAX_PAYLOAD_SIZE);
1633 ioctl->feature = BE_CMD_SET_FEATURE_UER;
1634 ioctl->param_len = sizeof(ioctl->param.req);
1635 ioctl->param.req.uer = BE_CMD_UER_SUPP_BIT;
1636 ret = be_mbox_notify(ctrl);
1637 if (!ret) {
1638 phba->ue2rp = ioctl->param.resp.ue2rp;
1639 set_bit(BEISCSI_HBA_UER_SUPP, &phba->state);
1640 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1641 "BG_%d : HBA error recovery supported\n");
1642 } else {
1643 /**
1644 * Check "MCC_STATUS_INVALID_LENGTH" for SKH.
1645 * Older FW versions return this error.
1646 */
1647 if (ret == MCC_STATUS_ILLEGAL_REQUEST ||
1648 ret == MCC_STATUS_INVALID_LENGTH)
1649 __beiscsi_log(phba, KERN_INFO,
1650 "BG_%d : HBA error recovery not supported\n");
1651 }
1652
1653 mutex_unlock(&ctrl->mbox_lock);
1654 return ret;
1655}
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