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[SCSI] be2iscsi: Fix returning Failure when MBX fails with Insufficient buffer error
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / be2iscsi / be_cmds.c
CommitLineData
6733b39a 1/**
5faf17b4 2 * Copyright (C) 2005 - 2012 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
255fa9a3 11 * linux-drivers@emulex.com
6733b39a 12 *
255fa9a3
JK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6733b39a
JK		 16 */
17
2177199d
JSJ		 18#include <scsi/iscsi_proto.h>
19
6733b39a
JK		 20#include "be.h"
21#include "be_mgmt.h"
22#include "be_main.h"
23
e9b91193
JK		 24int beiscsi_pci_soft_reset(struct beiscsi_hba *phba)
25{
26 u32 sreset;
27 u8 *pci_reset_offset = 0;
28 u8 *pci_online0_offset = 0;
29 u8 *pci_online1_offset = 0;
30 u32 pconline0 = 0;
31 u32 pconline1 = 0;
32 u32 i;
33
34 pci_reset_offset = (u8 *)phba->pci_va + BE2_SOFT_RESET;
35 pci_online0_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE0;
36 pci_online1_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE1;
37 sreset = readl((void *)pci_reset_offset);
38 sreset |= BE2_SET_RESET;
39 writel(sreset, (void *)pci_reset_offset);
40
41 i = 0;
42 while (sreset & BE2_SET_RESET) {
43 if (i > 64)
44 break;
45 msleep(100);
46 sreset = readl((void *)pci_reset_offset);
47 i++;
48 }
49
50 if (sreset & BE2_SET_RESET) {
99bc5d55
JSJ		 51 printk(KERN_ERR DRV_NAME
52 " Soft Reset did not deassert\n");
e9b91193
JK		 53 return -EIO;
54 }
55 pconline1 = BE2_MPU_IRAM_ONLINE;
56 writel(pconline0, (void *)pci_online0_offset);
57 writel(pconline1, (void *)pci_online1_offset);
58
1d8bc70a 59 sreset |= BE2_SET_RESET;
e9b91193
JK		 60 writel(sreset, (void *)pci_reset_offset);
61
62 i = 0;
63 while (sreset & BE2_SET_RESET) {
64 if (i > 64)
65 break;
66 msleep(1);
67 sreset = readl((void *)pci_reset_offset);
68 i++;
69 }
70 if (sreset & BE2_SET_RESET) {
99bc5d55
JSJ		 71 printk(KERN_ERR DRV_NAME
72 " MPU Online Soft Reset did not deassert\n");
e9b91193
JK		 73 return -EIO;
74 }
75 return 0;
76}
77
78int be_chk_reset_complete(struct beiscsi_hba *phba)
79{
80 unsigned int num_loop;
81 u8 *mpu_sem = 0;
82 u32 status;
83
84 num_loop = 1000;
85 mpu_sem = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
86 msleep(5000);
87
88 while (num_loop) {
89 status = readl((void *)mpu_sem);
90
91 if ((status & 0x80000000) || (status & 0x0000FFFF) == 0xC000)
92 break;
93 msleep(60);
94 num_loop--;
95 }
96
97 if ((status & 0x80000000) || (!num_loop)) {
99bc5d55
JSJ		 98 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
99 "BC_%d : Failed in be_chk_reset_complete"
100 "status = 0x%x\n", status);
e9b91193
JK		 101 return -EIO;
102 }
103
104 return 0;
105}
106
756d29c8 107void be_mcc_notify(struct beiscsi_hba *phba)
bfead3b2
JK		 108{
109 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
110 u32 val = 0;
111
112 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
113 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
114 iowrite32(val, phba->db_va + DB_MCCQ_OFFSET);
115}
116
756d29c8
JK		 117unsigned int alloc_mcc_tag(struct beiscsi_hba *phba)
118{
119 unsigned int tag = 0;
756d29c8 120
756d29c8
JK		 121 if (phba->ctrl.mcc_tag_available) {
122 tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index];
123 phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0;
124 phba->ctrl.mcc_numtag[tag] = 0;
756d29c8
JK		 125 }
126 if (tag) {
127 phba->ctrl.mcc_tag_available--;
128 if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1))
129 phba->ctrl.mcc_alloc_index = 0;
130 else
131 phba->ctrl.mcc_alloc_index++;
132 }
133 return tag;
134}
135
e175defe
JSJ		 136/*
137 * beiscsi_mccq_compl()- Wait for completion of MBX
138 * @phba: Driver private structure
139 * @tag: Tag for the MBX Command
140 * @wrb: the WRB used for the MBX Command
141 * @cmd_hdr: IOCTL Hdr for the MBX Cmd
142 *
143 * Waits for MBX completion with the passed TAG.
144 *
145 * return
146 * Success: 0
147 * Failure: Non-Zero
148 **/
149int beiscsi_mccq_compl(struct beiscsi_hba *phba,
150 uint32_t tag, struct be_mcc_wrb **wrb,
151 void *cmd_hdr)
152{
153 int rc = 0;
154 uint32_t mcc_tag_response;
155 uint16_t status = 0, addl_status = 0, wrb_num = 0;
156 struct be_mcc_wrb *temp_wrb;
157 struct be_cmd_req_hdr *ioctl_hdr;
a8081e34 158 struct be_cmd_resp_hdr *ioctl_resp_hdr;
e175defe
JSJ		 159 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
160
7a158003
JSJ		 161 if (beiscsi_error(phba))
162 return -EIO;
163
e175defe
JSJ		 164 /* wait for the mccq completion */
165 rc = wait_event_interruptible_timeout(
166 phba->ctrl.mcc_wait[tag],
167 phba->ctrl.mcc_numtag[tag],
168 msecs_to_jiffies(
169 BEISCSI_HOST_MBX_TIMEOUT));
170
171 if (rc <= 0) {
172 beiscsi_log(phba, KERN_ERR,
173 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
174 BEISCSI_LOG_CONFIG,
175 "BC_%d : MBX Cmd Completion timed out\n");
176 rc = -EAGAIN;
177 goto release_mcc_tag;
178 } else
179 rc = 0;
180
181 mcc_tag_response = phba->ctrl.mcc_numtag[tag];
182 status = (mcc_tag_response & CQE_STATUS_MASK);
183 addl_status = ((mcc_tag_response & CQE_STATUS_ADDL_MASK) >>
184 CQE_STATUS_ADDL_SHIFT);
185
186 if (cmd_hdr) {
187 ioctl_hdr = (struct be_cmd_req_hdr *)cmd_hdr;
188 } else {
189 wrb_num = (mcc_tag_response & CQE_STATUS_WRB_MASK) >>
190 CQE_STATUS_WRB_SHIFT;
191 temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num);
192 ioctl_hdr = embedded_payload(temp_wrb);
193
194 if (wrb)
195 *wrb = temp_wrb;
196 }
197
198 if (status || addl_status) {
199 beiscsi_log(phba, KERN_ERR,
200 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
201 BEISCSI_LOG_CONFIG,
202 "BC_%d : MBX Cmd Failed for "
203 "Subsys : %d Opcode : %d with "
204 "Status : %d and Extd_Status : %d\n",
205 ioctl_hdr->subsystem,
206 ioctl_hdr->opcode,
207 status, addl_status);
a8081e34
JK		 208
209 if (status == MCC_STATUS_INSUFFICIENT_BUFFER) {
210 ioctl_resp_hdr = (struct be_cmd_resp_hdr *) ioctl_hdr;
211 if (ioctl_resp_hdr->response_length)
212 goto release_mcc_tag;
213 }
e175defe
JSJ		 214 rc = -EAGAIN;
215 }
216
217release_mcc_tag:
218 /* Release the MCC entry */
219 free_mcc_tag(&phba->ctrl, tag);
220
221 return rc;
222}
223
756d29c8
JK		 224void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag)
225{
226 spin_lock(&ctrl->mbox_lock);
227 tag = tag & 0x000000FF;
228 ctrl->mcc_tag[ctrl->mcc_free_index] = tag;
229 if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1))
230 ctrl->mcc_free_index = 0;
231 else
232 ctrl->mcc_free_index++;
233 ctrl->mcc_tag_available++;
234 spin_unlock(&ctrl->mbox_lock);
235}
236
237bool is_link_state_evt(u32 trailer)
238{
239 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
240 ASYNC_TRAILER_EVENT_CODE_MASK) ==
241 ASYNC_EVENT_CODE_LINK_STATE);
242}
243
6733b39a
JK		 244static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
245{
246 if (compl->flags != 0) {
247 compl->flags = le32_to_cpu(compl->flags);
248 WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
249 return true;
250 } else
251 return false;
252}
253
254static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
255{
256 compl->flags = 0;
257}
258
e175defe
JSJ		 259/*
260 * be_mcc_compl_process()- Check the MBX comapletion status
261 * @ctrl: Function specific MBX data structure
262 * @compl: Completion status of MBX Command
263 *
264 * Check for the MBX completion status when BMBX method used
265 *
266 * return
267 * Success: Zero
268 * Failure: Non-Zero
269 **/
6733b39a
JK		 270static int be_mcc_compl_process(struct be_ctrl_info *ctrl,
271 struct be_mcc_compl *compl)
272{
273 u16 compl_status, extd_status;
e175defe 274 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
99bc5d55 275 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
e175defe 276 struct be_cmd_req_hdr *hdr = embedded_payload(wrb);
a8081e34 277 struct be_cmd_resp_hdr *resp_hdr;
6733b39a
JK		 278
279 be_dws_le_to_cpu(compl, 4);
280
281 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
282 CQE_STATUS_COMPL_MASK;
283 if (compl_status != MCC_STATUS_SUCCESS) {
284 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
285 CQE_STATUS_EXTD_MASK;
99bc5d55
JSJ		 286
287 beiscsi_log(phba, KERN_ERR,
288 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
e175defe
JSJ		 289 "BC_%d : error in cmd completion: "
290 "Subsystem : %d Opcode : %d "
291 "status(compl/extd)=%d/%d\n",
292 hdr->subsystem, hdr->opcode,
99bc5d55
JSJ		 293 compl_status, extd_status);
294
a8081e34
JK		 295 if (compl_status == MCC_STATUS_INSUFFICIENT_BUFFER) {
296 resp_hdr = (struct be_cmd_resp_hdr *) hdr;
297 if (resp_hdr->response_length)
298 return 0;
299 }
d3ad2bb3 300 return -EBUSY;
6733b39a
JK		 301 }
302 return 0;
303}
304
756d29c8
JK		 305int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl,
306 struct be_mcc_compl *compl)
6733b39a 307{
756d29c8
JK		 308 u16 compl_status, extd_status;
309 unsigned short tag;
310
311 be_dws_le_to_cpu(compl, 4);
312
313 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
314 CQE_STATUS_COMPL_MASK;
315 /* The ctrl.mcc_numtag[tag] is filled with
316 * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
317 * [7:0] = compl_status
318 */
319 tag = (compl->tag0 & 0x000000FF);
320 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
321 CQE_STATUS_EXTD_MASK;
322
323 ctrl->mcc_numtag[tag] = 0x80000000;
324 ctrl->mcc_numtag[tag] |= (compl->tag0 & 0x00FF0000);
325 ctrl->mcc_numtag[tag] |= (extd_status & 0x000000FF) << 8;
326 ctrl->mcc_numtag[tag] |= (compl_status & 0x000000FF);
327 wake_up_interruptible(&ctrl->mcc_wait[tag]);
328 return 0;
bfead3b2
JK		 329}
330
331static struct be_mcc_compl *be_mcc_compl_get(struct beiscsi_hba *phba)
332{
333 struct be_queue_info *mcc_cq = &phba->ctrl.mcc_obj.cq;
334 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
335
336 if (be_mcc_compl_is_new(compl)) {
337 queue_tail_inc(mcc_cq);
338 return compl;
339 }
340 return NULL;
341}
342
343static void be2iscsi_fail_session(struct iscsi_cls_session *cls_session)
344{
345 iscsi_session_failure(cls_session->dd_data, ISCSI_ERR_CONN_FAILED);
346}
347
756d29c8 348void beiscsi_async_link_state_process(struct beiscsi_hba *phba,
bfead3b2
JK		 349 struct be_async_event_link_state *evt)
350{
351 switch (evt->port_link_status) {
352 case ASYNC_EVENT_LINK_DOWN:
99bc5d55
JSJ		 353 beiscsi_log(phba, KERN_ERR,
354 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
355 "BC_%d : Link Down on Physical Port %d\n",
356 evt->physical_port);
357
bfead3b2 358 phba->state |= BE_ADAPTER_LINK_DOWN;
da7408c8
JK		 359 iscsi_host_for_each_session(phba->shost,
360 be2iscsi_fail_session);
bfead3b2
JK		 361 break;
362 case ASYNC_EVENT_LINK_UP:
363 phba->state = BE_ADAPTER_UP;
99bc5d55
JSJ		 364 beiscsi_log(phba, KERN_ERR,
365 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
366 "BC_%d : Link UP on Physical Port %d\n",
367 evt->physical_port);
bfead3b2
JK		 368 break;
369 default:
99bc5d55
JSJ		 370 beiscsi_log(phba, KERN_ERR,
371 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
372 "BC_%d : Unexpected Async Notification %d on"
373 "Physical Port %d\n",
374 evt->port_link_status,
375 evt->physical_port);
bfead3b2 376 }
6733b39a
JK		 377}
378
bfead3b2 379static void beiscsi_cq_notify(struct beiscsi_hba *phba, u16 qid, bool arm,
6733b39a
JK		 380 u16 num_popped)
381{
382 u32 val = 0;
383 val |= qid & DB_CQ_RING_ID_MASK;
384 if (arm)
385 val |= 1 << DB_CQ_REARM_SHIFT;
386 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
bfead3b2
JK		 387 iowrite32(val, phba->db_va + DB_CQ_OFFSET);
388}
389
390
35e66019 391int beiscsi_process_mcc(struct beiscsi_hba *phba)
bfead3b2
JK		 392{
393 struct be_mcc_compl *compl;
394 int num = 0, status = 0;
395 struct be_ctrl_info *ctrl = &phba->ctrl;
396
397 spin_lock_bh(&phba->ctrl.mcc_cq_lock);
398 while ((compl = be_mcc_compl_get(phba))) {
399 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
400 /* Interpret flags as an async trailer */
78b9fb6d
JK		 401 if (is_link_state_evt(compl->flags))
402 /* Interpret compl as a async link evt */
403 beiscsi_async_link_state_process(phba,
404 (struct be_async_event_link_state *) compl);
405 else
99bc5d55
JSJ		 406 beiscsi_log(phba, KERN_ERR,
407 BEISCSI_LOG_CONFIG |
408 BEISCSI_LOG_MBOX,
409 "BC_%d : Unsupported Async Event, flags"
410 " = 0x%08x\n", compl->flags);
bfead3b2 411
bfead3b2
JK		 412 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
413 status = be_mcc_compl_process(ctrl, compl);
414 atomic_dec(&phba->ctrl.mcc_obj.q.used);
415 }
416 be_mcc_compl_use(compl);
417 num++;
418 }
419
420 if (num)
421 beiscsi_cq_notify(phba, phba->ctrl.mcc_obj.cq.id, true, num);
422
423 spin_unlock_bh(&phba->ctrl.mcc_cq_lock);
424 return status;
425}
426
e175defe
JSJ		 427/*
428 * be_mcc_wait_compl()- Wait for MBX completion
429 * @phba: driver private structure
430 *
431 * Wait till no more pending mcc requests are present
432 *
433 * return
434 * Success: 0
435 * Failure: Non-Zero
436 *
437 **/
bfead3b2
JK		 438static int be_mcc_wait_compl(struct beiscsi_hba *phba)
439{
bfead3b2
JK		 440 int i, status;
441 for (i = 0; i < mcc_timeout; i++) {
7a158003 442 if (beiscsi_error(phba))
e175defe
JSJ		 443 return -EIO;
444
35e66019 445 status = beiscsi_process_mcc(phba);
bfead3b2
JK		 446 if (status)
447 return status;
448
449 if (atomic_read(&phba->ctrl.mcc_obj.q.used) == 0)
450 break;
451 udelay(100);
452 }
453 if (i == mcc_timeout) {
99bc5d55
JSJ		 454 beiscsi_log(phba, KERN_ERR,
455 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
e175defe
JSJ		 456 "BC_%d : FW Timed Out\n");
457 phba->fw_timeout = true;
7a158003 458 beiscsi_ue_detect(phba);
d3ad2bb3 459 return -EBUSY;
bfead3b2
JK		 460 }
461 return 0;
462}
463
e175defe
JSJ		 464/*
465 * be_mcc_notify_wait()- Notify and wait for Compl
466 * @phba: driver private structure
467 *
468 * Notify MCC requests and wait for completion
469 *
470 * return
471 * Success: 0
472 * Failure: Non-Zero
473 **/
bfead3b2
JK		 474int be_mcc_notify_wait(struct beiscsi_hba *phba)
475{
476 be_mcc_notify(phba);
477 return be_mcc_wait_compl(phba);
6733b39a
JK		 478}
479
e175defe
JSJ		 480/*
481 * be_mbox_db_ready_wait()- Check ready status
482 * @ctrl: Function specific MBX data structure
483 *
484 * Check for the ready status of FW to send BMBX
485 * commands to adapter.
486 *
487 * return
488 * Success: 0
489 * Failure: Non-Zero
490 **/
6733b39a
JK		 491static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl)
492{
6733b39a 493 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
e175defe
JSJ		 494 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
495 int wait = 0;
6733b39a
JK		 496 u32 ready;
497
498 do {
7a158003
JSJ		 499
500 if (beiscsi_error(phba))
e175defe
JSJ		 501 return -EIO;
502
6733b39a
JK		 503 ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
504 if (ready)
505 break;
506
e175defe 507 if (wait > BEISCSI_HOST_MBX_TIMEOUT) {
99bc5d55
JSJ		 508 beiscsi_log(phba, KERN_ERR,
509 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
e175defe
JSJ		 510 "BC_%d : FW Timed Out\n");
511 phba->fw_timeout = true;
7a158003 512 beiscsi_ue_detect(phba);
d3ad2bb3 513 return -EBUSY;
6733b39a
JK		 514 }
515
e175defe
JSJ		 516 mdelay(1);
517 wait++;
6733b39a
JK		 518 } while (true);
519 return 0;
520}
521
e175defe
JSJ		 522/*
523 * be_mbox_notify: Notify adapter of new BMBX command
524 * @ctrl: Function specific MBX data structure
525 *
526 * Ring doorbell to inform adapter of a BMBX command
527 * to process
528 *
529 * return
530 * Success: 0
531 * Failure: Non-Zero
532 **/
6733b39a
JK		 533int be_mbox_notify(struct be_ctrl_info *ctrl)
534{
535 int status;
536 u32 val = 0;
537 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
538 struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
539 struct be_mcc_mailbox *mbox = mbox_mem->va;
540 struct be_mcc_compl *compl = &mbox->compl;
99bc5d55 541 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 542
543 val &= ~MPU_MAILBOX_DB_RDY_MASK;
544 val |= MPU_MAILBOX_DB_HI_MASK;
545 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
546 iowrite32(val, db);
547
548 status = be_mbox_db_ready_wait(ctrl);
e175defe 549 if (status)
6733b39a 550 return status;
e175defe 551
6733b39a
JK		 552 val = 0;
553 val &= ~MPU_MAILBOX_DB_RDY_MASK;
554 val &= ~MPU_MAILBOX_DB_HI_MASK;
555 val |= (u32) (mbox_mem->dma >> 4) << 2;
556 iowrite32(val, db);
557
558 status = be_mbox_db_ready_wait(ctrl);
e175defe 559 if (status)
6733b39a 560 return status;
e175defe 561
6733b39a
JK		 562 if (be_mcc_compl_is_new(compl)) {
563 status = be_mcc_compl_process(ctrl, &mbox->compl);
564 be_mcc_compl_use(compl);
565 if (status) {
99bc5d55
JSJ		 566 beiscsi_log(phba, KERN_ERR,
567 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
568 "BC_%d : After be_mcc_compl_process\n");
569
6733b39a
JK		 570 return status;
571 }
572 } else {
99bc5d55
JSJ		 573 beiscsi_log(phba, KERN_ERR,
574 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
575 "BC_%d : Invalid Mailbox Completion\n");
576
d3ad2bb3 577 return -EBUSY;
6733b39a
JK		 578 }
579 return 0;
580}
581
bfead3b2
JK		 582/*
583 * Insert the mailbox address into the doorbell in two steps
584 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
585 */
586static int be_mbox_notify_wait(struct beiscsi_hba *phba)
587{
588 int status;
589 u32 val = 0;
590 void __iomem *db = phba->ctrl.db + MPU_MAILBOX_DB_OFFSET;
591 struct be_dma_mem *mbox_mem = &phba->ctrl.mbox_mem;
592 struct be_mcc_mailbox *mbox = mbox_mem->va;
593 struct be_mcc_compl *compl = &mbox->compl;
594 struct be_ctrl_info *ctrl = &phba->ctrl;
595
596 val |= MPU_MAILBOX_DB_HI_MASK;
597 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
598 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
599 iowrite32(val, db);
600
601 /* wait for ready to be set */
602 status = be_mbox_db_ready_wait(ctrl);
603 if (status != 0)
604 return status;
605
606 val = 0;
607 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
608 val |= (u32)(mbox_mem->dma >> 4) << 2;
609 iowrite32(val, db);
610
611 status = be_mbox_db_ready_wait(ctrl);
612 if (status != 0)
613 return status;
614
615 /* A cq entry has been made now */
616 if (be_mcc_compl_is_new(compl)) {
617 status = be_mcc_compl_process(ctrl, &mbox->compl);
618 be_mcc_compl_use(compl);
619 if (status)
620 return status;
621 } else {
99bc5d55
JSJ		 622 beiscsi_log(phba, KERN_ERR,
623 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
624 "BC_%d : invalid mailbox completion\n");
625
d3ad2bb3 626 return -EBUSY;
bfead3b2
JK		 627 }
628 return 0;
629}
630
6733b39a
JK		 631void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
632 bool embedded, u8 sge_cnt)
633{
634 if (embedded)
635 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
636 else
637 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
638 MCC_WRB_SGE_CNT_SHIFT;
639 wrb->payload_length = payload_len;
640 be_dws_cpu_to_le(wrb, 8);
641}
642
643void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
644 u8 subsystem, u8 opcode, int cmd_len)
645{
646 req_hdr->opcode = opcode;
647 req_hdr->subsystem = subsystem;
648 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
e175defe 649 req_hdr->timeout = BEISCSI_FW_MBX_TIMEOUT;
6733b39a
JK		 650}
651
652static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
653 struct be_dma_mem *mem)
654{
655 int i, buf_pages;
656 u64 dma = (u64) mem->dma;
657
658 buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
659 for (i = 0; i < buf_pages; i++) {
660 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
661 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
662 dma += PAGE_SIZE_4K;
663 }
664}
665
666static u32 eq_delay_to_mult(u32 usec_delay)
667{
668#define MAX_INTR_RATE 651042
669 const u32 round = 10;
670 u32 multiplier;
671
672 if (usec_delay == 0)
673 multiplier = 0;
674 else {
675 u32 interrupt_rate = 1000000 / usec_delay;
676 if (interrupt_rate == 0)
677 multiplier = 1023;
678 else {
679 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
680 multiplier /= interrupt_rate;
681 multiplier = (multiplier + round / 2) / round;
682 multiplier = min(multiplier, (u32) 1023);
683 }
684 }
685 return multiplier;
686}
687
688struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
689{
690 return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
691}
692
bfead3b2
JK		 693struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba)
694{
695 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
696 struct be_mcc_wrb *wrb;
697
698 BUG_ON(atomic_read(&mccq->used) >= mccq->len);
699 wrb = queue_head_node(mccq);
756d29c8
JK		 700 memset(wrb, 0, sizeof(*wrb));
701 wrb->tag0 = (mccq->head & 0x000000FF) << 16;
bfead3b2
JK		 702 queue_head_inc(mccq);
703 atomic_inc(&mccq->used);
bfead3b2
JK		 704 return wrb;
705}
706
707
6733b39a
JK		 708int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
709 struct be_queue_info *eq, int eq_delay)
710{
711 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
712 struct be_cmd_req_eq_create *req = embedded_payload(wrb);
713 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
714 struct be_dma_mem *q_mem = &eq->dma_mem;
715 int status;
716
717 spin_lock(&ctrl->mbox_lock);
718 memset(wrb, 0, sizeof(*wrb));
719
720 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
721
722 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
723 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
724
725 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
726
727 AMAP_SET_BITS(struct amap_eq_context, func, req->context,
728 PCI_FUNC(ctrl->pdev->devfn));
729 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
730 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
731 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
732 __ilog2_u32(eq->len / 256));
733 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
734 eq_delay_to_mult(eq_delay));
735 be_dws_cpu_to_le(req->context, sizeof(req->context));
736
737 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
738
739 status = be_mbox_notify(ctrl);
740 if (!status) {
741 eq->id = le16_to_cpu(resp->eq_id);
742 eq->created = true;
743 }
744 spin_unlock(&ctrl->mbox_lock);
745 return status;
746}
747
0283fbb1
JK		 748/**
749 * be_cmd_fw_initialize()- Initialize FW
750 * @ctrl: Pointer to function control structure
751 *
752 * Send FW initialize pattern for the function.
753 *
754 * return
755 * Success: 0
756 * Failure: Non-Zero value
757 **/
6733b39a
JK		 758int be_cmd_fw_initialize(struct be_ctrl_info *ctrl)
759{
760 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
99bc5d55 761 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 762 int status;
763 u8 *endian_check;
764
765 spin_lock(&ctrl->mbox_lock);
766 memset(wrb, 0, sizeof(*wrb));
767
768 endian_check = (u8 *) wrb;
769 *endian_check++ = 0xFF;
770 *endian_check++ = 0x12;
771 *endian_check++ = 0x34;
772 *endian_check++ = 0xFF;
773 *endian_check++ = 0xFF;
774 *endian_check++ = 0x56;
775 *endian_check++ = 0x78;
776 *endian_check++ = 0xFF;
777 be_dws_cpu_to_le(wrb, sizeof(*wrb));
778
779 status = be_mbox_notify(ctrl);
780 if (status)
99bc5d55
JSJ		 781 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
782 "BC_%d : be_cmd_fw_initialize Failed\n");
6733b39a
JK		 783
784 spin_unlock(&ctrl->mbox_lock);
785 return status;
786}
787
0283fbb1
JK		 788/**
789 * be_cmd_fw_uninit()- Uinitialize FW
790 * @ctrl: Pointer to function control structure
791 *
792 * Send FW uninitialize pattern for the function
793 *
794 * return
795 * Success: 0
796 * Failure: Non-Zero value
797 **/
798int be_cmd_fw_uninit(struct be_ctrl_info *ctrl)
799{
800 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
801 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
802 int status;
803 u8 *endian_check;
804
805 spin_lock(&ctrl->mbox_lock);
806 memset(wrb, 0, sizeof(*wrb));
807
808 endian_check = (u8 *) wrb;
809 *endian_check++ = 0xFF;
810 *endian_check++ = 0xAA;
811 *endian_check++ = 0xBB;
812 *endian_check++ = 0xFF;
813 *endian_check++ = 0xFF;
814 *endian_check++ = 0xCC;
815 *endian_check++ = 0xDD;
816 *endian_check = 0xFF;
817
818 be_dws_cpu_to_le(wrb, sizeof(*wrb));
819
820 status = be_mbox_notify(ctrl);
821 if (status)
822 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
823 "BC_%d : be_cmd_fw_uninit Failed\n");
824
825 spin_unlock(&ctrl->mbox_lock);
826 return status;
827}
828
6733b39a
JK		 829int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
830 struct be_queue_info *cq, struct be_queue_info *eq,
831 bool sol_evts, bool no_delay, int coalesce_wm)
832{
833 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
834 struct be_cmd_req_cq_create *req = embedded_payload(wrb);
835 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
99bc5d55 836 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 837 struct be_dma_mem *q_mem = &cq->dma_mem;
838 void *ctxt = &req->context;
839 int status;
840
841 spin_lock(&ctrl->mbox_lock);
842 memset(wrb, 0, sizeof(*wrb));
843
844 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
845
846 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
847 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
6733b39a
JK		 848
849 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
eaae5267
JSJ		 850 if (chip_skh_r(ctrl->pdev)) {
851 req->hdr.version = MBX_CMD_VER2;
852 req->page_size = 1;
853 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
854 ctxt, coalesce_wm);
855 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay,
856 ctxt, no_delay);
857 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
858 __ilog2_u32(cq->len / 256));
859 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
860 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
861 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
862 AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1);
863 } else {
864 AMAP_SET_BITS(struct amap_cq_context, coalescwm,
865 ctxt, coalesce_wm);
866 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
867 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
868 __ilog2_u32(cq->len / 256));
869 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
870 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
871 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
872 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
873 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
874 AMAP_SET_BITS(struct amap_cq_context, func, ctxt,
875 PCI_FUNC(ctrl->pdev->devfn));
876 }
6733b39a 877
6733b39a
JK		 878 be_dws_cpu_to_le(ctxt, sizeof(req->context));
879
880 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
881
882 status = be_mbox_notify(ctrl);
883 if (!status) {
884 cq->id = le16_to_cpu(resp->cq_id);
885 cq->created = true;
886 } else
99bc5d55
JSJ		 887 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
888 "BC_%d : In be_cmd_cq_create, status=ox%08x\n",
889 status);
890
6733b39a
JK		 891 spin_unlock(&ctrl->mbox_lock);
892
893 return status;
894}
895
896static u32 be_encoded_q_len(int q_len)
897{
898 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
899 if (len_encoded == 16)
900 len_encoded = 0;
901 return len_encoded;
902}
bfead3b2 903
35e66019 904int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba,
bfead3b2
JK		 905 struct be_queue_info *mccq,
906 struct be_queue_info *cq)
907{
908 struct be_mcc_wrb *wrb;
909 struct be_cmd_req_mcc_create *req;
910 struct be_dma_mem *q_mem = &mccq->dma_mem;
911 struct be_ctrl_info *ctrl;
912 void *ctxt;
913 int status;
914
915 spin_lock(&phba->ctrl.mbox_lock);
916 ctrl = &phba->ctrl;
917 wrb = wrb_from_mbox(&ctrl->mbox_mem);
37609766 918 memset(wrb, 0, sizeof(*wrb));
bfead3b2
JK		 919 req = embedded_payload(wrb);
920 ctxt = &req->context;
921
922 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
923
924 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
925 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
926
927 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
928
929 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt,
930 PCI_FUNC(phba->pcidev->devfn));
931 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
932 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
933 be_encoded_q_len(mccq->len));
934 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
935
936 be_dws_cpu_to_le(ctxt, sizeof(req->context));
937
938 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
939
940 status = be_mbox_notify_wait(phba);
941 if (!status) {
942 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
943 mccq->id = le16_to_cpu(resp->id);
944 mccq->created = true;
945 }
946 spin_unlock(&phba->ctrl.mbox_lock);
947
948 return status;
949}
950
6733b39a
JK		 951int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
952 int queue_type)
953{
954 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
955 struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
99bc5d55 956 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 957 u8 subsys = 0, opcode = 0;
958 int status;
959
99bc5d55
JSJ		 960 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
961 "BC_%d : In beiscsi_cmd_q_destroy "
962 "queue_type : %d\n", queue_type);
963
6733b39a
JK		 964 spin_lock(&ctrl->mbox_lock);
965 memset(wrb, 0, sizeof(*wrb));
966 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
967
968 switch (queue_type) {
969 case QTYPE_EQ:
970 subsys = CMD_SUBSYSTEM_COMMON;
971 opcode = OPCODE_COMMON_EQ_DESTROY;
972 break;
973 case QTYPE_CQ:
974 subsys = CMD_SUBSYSTEM_COMMON;
975 opcode = OPCODE_COMMON_CQ_DESTROY;
976 break;
bfead3b2
JK		 977 case QTYPE_MCCQ:
978 subsys = CMD_SUBSYSTEM_COMMON;
979 opcode = OPCODE_COMMON_MCC_DESTROY;
980 break;
6733b39a
JK		 981 case QTYPE_WRBQ:
982 subsys = CMD_SUBSYSTEM_ISCSI;
983 opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY;
984 break;
985 case QTYPE_DPDUQ:
986 subsys = CMD_SUBSYSTEM_ISCSI;
987 opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY;
988 break;
989 case QTYPE_SGL:
990 subsys = CMD_SUBSYSTEM_ISCSI;
991 opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES;
992 break;
993 default:
994 spin_unlock(&ctrl->mbox_lock);
995 BUG();
d3ad2bb3 996 return -ENXIO;
6733b39a
JK		 997 }
998 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
999 if (queue_type != QTYPE_SGL)
1000 req->id = cpu_to_le16(q->id);
1001
1002 status = be_mbox_notify(ctrl);
1003
1004 spin_unlock(&ctrl->mbox_lock);
1005 return status;
1006}
1007
6733b39a
JK		 1008int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
1009 struct be_queue_info *cq,
1010 struct be_queue_info *dq, int length,
1011 int entry_size)
1012{
1013 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1014 struct be_defq_create_req *req = embedded_payload(wrb);
1015 struct be_dma_mem *q_mem = &dq->dma_mem;
1016 void *ctxt = &req->context;
1017 int status;
1018
1019 spin_lock(&ctrl->mbox_lock);
1020 memset(wrb, 0, sizeof(*wrb));
1021
1022 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1023
1024 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1025 OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req));
1026
1027 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1028 AMAP_SET_BITS(struct amap_be_default_pdu_context, rx_pdid, ctxt, 0);
1029 AMAP_SET_BITS(struct amap_be_default_pdu_context, rx_pdid_valid, ctxt,
1030 1);
1031 AMAP_SET_BITS(struct amap_be_default_pdu_context, pci_func_id, ctxt,
1032 PCI_FUNC(ctrl->pdev->devfn));
1033 AMAP_SET_BITS(struct amap_be_default_pdu_context, ring_size, ctxt,
1034 be_encoded_q_len(length / sizeof(struct phys_addr)));
1035 AMAP_SET_BITS(struct amap_be_default_pdu_context, default_buffer_size,
1036 ctxt, entry_size);
1037 AMAP_SET_BITS(struct amap_be_default_pdu_context, cq_id_recv, ctxt,
1038 cq->id);
1039
1040 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1041
1042 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1043
1044 status = be_mbox_notify(ctrl);
1045 if (!status) {
1046 struct be_defq_create_resp *resp = embedded_payload(wrb);
1047
1048 dq->id = le16_to_cpu(resp->id);
1049 dq->created = true;
1050 }
1051 spin_unlock(&ctrl->mbox_lock);
1052
1053 return status;
1054}
1055
1056int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, struct be_dma_mem *q_mem,
1057 struct be_queue_info *wrbq)
1058{
1059 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1060 struct be_wrbq_create_req *req = embedded_payload(wrb);
1061 struct be_wrbq_create_resp *resp = embedded_payload(wrb);
1062 int status;
1063
1064 spin_lock(&ctrl->mbox_lock);
1065 memset(wrb, 0, sizeof(*wrb));
1066
1067 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1068
1069 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1070 OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req));
1071 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1072 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1073
1074 status = be_mbox_notify(ctrl);
bfead3b2 1075 if (!status) {
6733b39a 1076 wrbq->id = le16_to_cpu(resp->cid);
bfead3b2
JK		 1077 wrbq->created = true;
1078 }
6733b39a
JK		 1079 spin_unlock(&ctrl->mbox_lock);
1080 return status;
1081}
1082
1083int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
1084 struct be_dma_mem *q_mem,
1085 u32 page_offset, u32 num_pages)
1086{
1087 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1088 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
99bc5d55 1089 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 1090 int status;
1091 unsigned int curr_pages;
1092 u32 internal_page_offset = 0;
1093 u32 temp_num_pages = num_pages;
1094
1095 if (num_pages == 0xff)
1096 num_pages = 1;
1097
1098 spin_lock(&ctrl->mbox_lock);
1099 do {
1100 memset(wrb, 0, sizeof(*wrb));
1101 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1102 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1103 OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES,
1104 sizeof(*req));
1105 curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req,
1106 pages);
1107 req->num_pages = min(num_pages, curr_pages);
1108 req->page_offset = page_offset;
1109 be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem);
1110 q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE);
1111 internal_page_offset += req->num_pages;
1112 page_offset += req->num_pages;
1113 num_pages -= req->num_pages;
1114
1115 if (temp_num_pages == 0xff)
1116 req->num_pages = temp_num_pages;
1117
1118 status = be_mbox_notify(ctrl);
1119 if (status) {
99bc5d55
JSJ		 1120 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1121 "BC_%d : FW CMD to map iscsi frags failed.\n");
1122
6733b39a
JK		 1123 goto error;
1124 }
1125 } while (num_pages > 0);
1126error:
1127 spin_unlock(&ctrl->mbox_lock);
1128 if (status != 0)
1129 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
1130 return status;
1131}
e5285860
JK		 1132
1133int beiscsi_cmd_reset_function(struct beiscsi_hba *phba)
1134{
1135 struct be_ctrl_info *ctrl = &phba->ctrl;
1136 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1137 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
1138 int status;
1139
1140 spin_lock(&ctrl->mbox_lock);
1141
1142 req = embedded_payload(wrb);
1143 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1144 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1145 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1146 status = be_mbox_notify_wait(phba);
1147
1148 spin_unlock(&ctrl->mbox_lock);
1149 return status;
1150}
6f72238e
JSJ		 1151
1152/**
1153 * be_cmd_set_vlan()- Configure VLAN paramters on the adapter
1154 * @phba: device priv structure instance
1155 * @vlan_tag: TAG to be set
1156 *
1157 * Set the VLAN_TAG for the adapter or Disable VLAN on adapter
1158 *
1159 * returns
1160 * TAG for the MBX Cmd
1161 * **/
1162int be_cmd_set_vlan(struct beiscsi_hba *phba,
1163 uint16_t vlan_tag)
1164{
1165 unsigned int tag = 0;
1166 struct be_mcc_wrb *wrb;
1167 struct be_cmd_set_vlan_req *req;
1168 struct be_ctrl_info *ctrl = &phba->ctrl;
1169
1170 spin_lock(&ctrl->mbox_lock);
1171 tag = alloc_mcc_tag(phba);
1172 if (!tag) {
1173 spin_unlock(&ctrl->mbox_lock);
1174 return tag;
1175 }
1176
1177 wrb = wrb_from_mccq(phba);
1178 req = embedded_payload(wrb);
1179 wrb->tag0 |= tag;
1180 be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0);
1181 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1182 OPCODE_COMMON_ISCSI_NTWK_SET_VLAN,
1183 sizeof(*req));
1184
1185 req->interface_hndl = phba->interface_handle;
1186 req->vlan_priority = vlan_tag;
1187
1188 be_mcc_notify(phba);
1189 spin_unlock(&ctrl->mbox_lock);
1190
1191 return tag;
1192}
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