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6733b39a | 1 | /** |
c4f39bda | 2 | * Copyright (C) 2005 - 2015 Emulex |
6733b39a JK |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
4627de93 | 11 | * linux-drivers@avagotech.com |
6733b39a | 12 | * |
c4f39bda | 13 | * Emulex |
255fa9a3 JK |
14 | * 3333 Susan Street |
15 | * Costa Mesa, CA 92626 | |
6733b39a JK |
16 | */ |
17 | ||
2177199d JSJ |
18 | #include <scsi/iscsi_proto.h> |
19 | ||
4eea99d5 | 20 | #include "be_main.h" |
6733b39a JK |
21 | #include "be.h" |
22 | #include "be_mgmt.h" | |
6733b39a | 23 | |
e9b91193 JK |
24 | int beiscsi_pci_soft_reset(struct beiscsi_hba *phba) |
25 | { | |
26 | u32 sreset; | |
27 | u8 *pci_reset_offset = 0; | |
28 | u8 *pci_online0_offset = 0; | |
29 | u8 *pci_online1_offset = 0; | |
30 | u32 pconline0 = 0; | |
31 | u32 pconline1 = 0; | |
32 | u32 i; | |
33 | ||
34 | pci_reset_offset = (u8 *)phba->pci_va + BE2_SOFT_RESET; | |
35 | pci_online0_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE0; | |
36 | pci_online1_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE1; | |
37 | sreset = readl((void *)pci_reset_offset); | |
38 | sreset |= BE2_SET_RESET; | |
39 | writel(sreset, (void *)pci_reset_offset); | |
40 | ||
41 | i = 0; | |
42 | while (sreset & BE2_SET_RESET) { | |
43 | if (i > 64) | |
44 | break; | |
45 | msleep(100); | |
46 | sreset = readl((void *)pci_reset_offset); | |
47 | i++; | |
48 | } | |
49 | ||
50 | if (sreset & BE2_SET_RESET) { | |
99bc5d55 JSJ |
51 | printk(KERN_ERR DRV_NAME |
52 | " Soft Reset did not deassert\n"); | |
e9b91193 JK |
53 | return -EIO; |
54 | } | |
55 | pconline1 = BE2_MPU_IRAM_ONLINE; | |
56 | writel(pconline0, (void *)pci_online0_offset); | |
57 | writel(pconline1, (void *)pci_online1_offset); | |
58 | ||
1d8bc70a | 59 | sreset |= BE2_SET_RESET; |
e9b91193 JK |
60 | writel(sreset, (void *)pci_reset_offset); |
61 | ||
62 | i = 0; | |
63 | while (sreset & BE2_SET_RESET) { | |
64 | if (i > 64) | |
65 | break; | |
66 | msleep(1); | |
67 | sreset = readl((void *)pci_reset_offset); | |
68 | i++; | |
69 | } | |
70 | if (sreset & BE2_SET_RESET) { | |
99bc5d55 JSJ |
71 | printk(KERN_ERR DRV_NAME |
72 | " MPU Online Soft Reset did not deassert\n"); | |
e9b91193 JK |
73 | return -EIO; |
74 | } | |
75 | return 0; | |
76 | } | |
77 | ||
78 | int be_chk_reset_complete(struct beiscsi_hba *phba) | |
79 | { | |
80 | unsigned int num_loop; | |
81 | u8 *mpu_sem = 0; | |
82 | u32 status; | |
83 | ||
84 | num_loop = 1000; | |
85 | mpu_sem = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE; | |
86 | msleep(5000); | |
87 | ||
88 | while (num_loop) { | |
89 | status = readl((void *)mpu_sem); | |
90 | ||
91 | if ((status & 0x80000000) || (status & 0x0000FFFF) == 0xC000) | |
92 | break; | |
93 | msleep(60); | |
94 | num_loop--; | |
95 | } | |
96 | ||
97 | if ((status & 0x80000000) || (!num_loop)) { | |
99bc5d55 JSJ |
98 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
99 | "BC_%d : Failed in be_chk_reset_complete" | |
100 | "status = 0x%x\n", status); | |
e9b91193 JK |
101 | return -EIO; |
102 | } | |
103 | ||
104 | return 0; | |
105 | } | |
106 | ||
756d29c8 JK |
107 | unsigned int alloc_mcc_tag(struct beiscsi_hba *phba) |
108 | { | |
109 | unsigned int tag = 0; | |
756d29c8 | 110 | |
12843f03 | 111 | spin_lock(&phba->ctrl.mcc_lock); |
756d29c8 JK |
112 | if (phba->ctrl.mcc_tag_available) { |
113 | tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index]; | |
114 | phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0; | |
67296ad9 | 115 | phba->ctrl.mcc_tag_status[tag] = 0; |
cdde6682 | 116 | phba->ctrl.ptag_state[tag].tag_state = 0; |
756d29c8 JK |
117 | } |
118 | if (tag) { | |
119 | phba->ctrl.mcc_tag_available--; | |
120 | if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1)) | |
121 | phba->ctrl.mcc_alloc_index = 0; | |
122 | else | |
123 | phba->ctrl.mcc_alloc_index++; | |
124 | } | |
12843f03 | 125 | spin_unlock(&phba->ctrl.mcc_lock); |
756d29c8 JK |
126 | return tag; |
127 | } | |
128 | ||
69fd6d7b JB |
129 | void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag) |
130 | { | |
131 | spin_lock_bh(&ctrl->mcc_lock); | |
132 | tag = tag & MCC_Q_CMD_TAG_MASK; | |
133 | ctrl->mcc_tag[ctrl->mcc_free_index] = tag; | |
134 | if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1)) | |
135 | ctrl->mcc_free_index = 0; | |
136 | else | |
137 | ctrl->mcc_free_index++; | |
138 | ctrl->mcc_tag_available++; | |
139 | spin_unlock_bh(&ctrl->mcc_lock); | |
140 | } | |
141 | ||
142 | /** | |
143 | * beiscsi_fail_session(): Closing session with appropriate error | |
144 | * @cls_session: ptr to session | |
145 | **/ | |
146 | void beiscsi_fail_session(struct iscsi_cls_session *cls_session) | |
147 | { | |
148 | iscsi_session_failure(cls_session->dd_data, ISCSI_ERR_CONN_FAILED); | |
149 | } | |
150 | ||
e175defe | 151 | /* |
88840332 | 152 | * beiscsi_mccq_compl_wait()- Process completion in MCC CQ |
e175defe JSJ |
153 | * @phba: Driver private structure |
154 | * @tag: Tag for the MBX Command | |
155 | * @wrb: the WRB used for the MBX Command | |
1957aa7f | 156 | * @mbx_cmd_mem: ptr to memory allocated for MBX Cmd |
e175defe JSJ |
157 | * |
158 | * Waits for MBX completion with the passed TAG. | |
159 | * | |
160 | * return | |
161 | * Success: 0 | |
162 | * Failure: Non-Zero | |
163 | **/ | |
88840332 JB |
164 | int beiscsi_mccq_compl_wait(struct beiscsi_hba *phba, |
165 | uint32_t tag, struct be_mcc_wrb **wrb, | |
166 | struct be_dma_mem *mbx_cmd_mem) | |
e175defe JSJ |
167 | { |
168 | int rc = 0; | |
67296ad9 | 169 | uint32_t mcc_tag_status; |
e175defe JSJ |
170 | uint16_t status = 0, addl_status = 0, wrb_num = 0; |
171 | struct be_mcc_wrb *temp_wrb; | |
1957aa7f JK |
172 | struct be_cmd_req_hdr *mbx_hdr; |
173 | struct be_cmd_resp_hdr *mbx_resp_hdr; | |
e175defe JSJ |
174 | struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; |
175 | ||
1f536d49 JK |
176 | if (beiscsi_error(phba)) { |
177 | free_mcc_tag(&phba->ctrl, tag); | |
1957aa7f | 178 | return -EPERM; |
1f536d49 | 179 | } |
7a158003 | 180 | |
e175defe JSJ |
181 | /* wait for the mccq completion */ |
182 | rc = wait_event_interruptible_timeout( | |
183 | phba->ctrl.mcc_wait[tag], | |
67296ad9 | 184 | phba->ctrl.mcc_tag_status[tag], |
e175defe JSJ |
185 | msecs_to_jiffies( |
186 | BEISCSI_HOST_MBX_TIMEOUT)); | |
cdde6682 JB |
187 | /** |
188 | * If MBOX cmd timeout expired, tag and resource allocated | |
189 | * for cmd is not freed until FW returns completion. | |
190 | */ | |
e175defe | 191 | if (rc <= 0) { |
1957aa7f | 192 | struct be_dma_mem *tag_mem; |
1957aa7f | 193 | |
cdde6682 JB |
194 | /** |
195 | * PCI/DMA memory allocated and posted in non-embedded mode | |
196 | * will have mbx_cmd_mem != NULL. | |
197 | * Save virtual and bus addresses for the command so that it | |
198 | * can be freed later. | |
199 | **/ | |
1957aa7f JK |
200 | tag_mem = &phba->ctrl.ptag_state[tag].tag_mem_state; |
201 | if (mbx_cmd_mem) { | |
202 | tag_mem->size = mbx_cmd_mem->size; | |
203 | tag_mem->va = mbx_cmd_mem->va; | |
204 | tag_mem->dma = mbx_cmd_mem->dma; | |
205 | } else | |
206 | tag_mem->size = 0; | |
207 | ||
cdde6682 JB |
208 | /* first make tag_mem_state visible to all */ |
209 | wmb(); | |
210 | set_bit(MCC_TAG_STATE_TIMEOUT, | |
211 | &phba->ctrl.ptag_state[tag].tag_state); | |
212 | ||
e175defe JSJ |
213 | beiscsi_log(phba, KERN_ERR, |
214 | BEISCSI_LOG_INIT | BEISCSI_LOG_EH | | |
215 | BEISCSI_LOG_CONFIG, | |
216 | "BC_%d : MBX Cmd Completion timed out\n"); | |
1957aa7f | 217 | return -EBUSY; |
1957aa7f | 218 | } |
e175defe | 219 | |
cdde6682 | 220 | rc = 0; |
67296ad9 JB |
221 | mcc_tag_status = phba->ctrl.mcc_tag_status[tag]; |
222 | status = (mcc_tag_status & CQE_STATUS_MASK); | |
223 | addl_status = ((mcc_tag_status & CQE_STATUS_ADDL_MASK) >> | |
e175defe JSJ |
224 | CQE_STATUS_ADDL_SHIFT); |
225 | ||
1957aa7f JK |
226 | if (mbx_cmd_mem) { |
227 | mbx_hdr = (struct be_cmd_req_hdr *)mbx_cmd_mem->va; | |
e175defe | 228 | } else { |
67296ad9 | 229 | wrb_num = (mcc_tag_status & CQE_STATUS_WRB_MASK) >> |
e175defe JSJ |
230 | CQE_STATUS_WRB_SHIFT; |
231 | temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num); | |
1957aa7f | 232 | mbx_hdr = embedded_payload(temp_wrb); |
e175defe JSJ |
233 | |
234 | if (wrb) | |
235 | *wrb = temp_wrb; | |
236 | } | |
237 | ||
238 | if (status || addl_status) { | |
1957aa7f | 239 | beiscsi_log(phba, KERN_WARNING, |
e175defe JSJ |
240 | BEISCSI_LOG_INIT | BEISCSI_LOG_EH | |
241 | BEISCSI_LOG_CONFIG, | |
242 | "BC_%d : MBX Cmd Failed for " | |
243 | "Subsys : %d Opcode : %d with " | |
244 | "Status : %d and Extd_Status : %d\n", | |
1957aa7f JK |
245 | mbx_hdr->subsystem, |
246 | mbx_hdr->opcode, | |
e175defe | 247 | status, addl_status); |
cdde6682 | 248 | rc = -EIO; |
a8081e34 | 249 | if (status == MCC_STATUS_INSUFFICIENT_BUFFER) { |
1957aa7f | 250 | mbx_resp_hdr = (struct be_cmd_resp_hdr *) mbx_hdr; |
1f536d49 JK |
251 | beiscsi_log(phba, KERN_WARNING, |
252 | BEISCSI_LOG_INIT | BEISCSI_LOG_EH | | |
253 | BEISCSI_LOG_CONFIG, | |
d939be3a | 254 | "BC_%d : Insufficient Buffer Error " |
1f536d49 | 255 | "Resp_Len : %d Actual_Resp_Len : %d\n", |
1957aa7f JK |
256 | mbx_resp_hdr->response_length, |
257 | mbx_resp_hdr->actual_resp_len); | |
1f536d49 | 258 | rc = -EAGAIN; |
a8081e34 | 259 | } |
e175defe JSJ |
260 | } |
261 | ||
e175defe | 262 | free_mcc_tag(&phba->ctrl, tag); |
e175defe JSJ |
263 | return rc; |
264 | } | |
265 | ||
e175defe | 266 | /* |
88840332 | 267 | * beiscsi_process_mbox_compl()- Check the MBX completion status |
e175defe JSJ |
268 | * @ctrl: Function specific MBX data structure |
269 | * @compl: Completion status of MBX Command | |
270 | * | |
271 | * Check for the MBX completion status when BMBX method used | |
272 | * | |
273 | * return | |
274 | * Success: Zero | |
275 | * Failure: Non-Zero | |
276 | **/ | |
88840332 JB |
277 | static int beiscsi_process_mbox_compl(struct be_ctrl_info *ctrl, |
278 | struct be_mcc_compl *compl) | |
6733b39a JK |
279 | { |
280 | u16 compl_status, extd_status; | |
e175defe | 281 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); |
99bc5d55 | 282 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
e175defe | 283 | struct be_cmd_req_hdr *hdr = embedded_payload(wrb); |
a8081e34 | 284 | struct be_cmd_resp_hdr *resp_hdr; |
6733b39a | 285 | |
c448427b JB |
286 | /** |
287 | * To check if valid bit is set, check the entire word as we don't know | |
288 | * the endianness of the data (old entry is host endian while a new | |
289 | * entry is little endian) | |
290 | */ | |
291 | if (!compl->flags) { | |
292 | beiscsi_log(phba, KERN_ERR, | |
293 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, | |
294 | "BC_%d : BMBX busy, no completion\n"); | |
295 | return -EBUSY; | |
296 | } | |
297 | compl->flags = le32_to_cpu(compl->flags); | |
298 | WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0); | |
6733b39a | 299 | |
c448427b JB |
300 | /** |
301 | * Just swap the status to host endian; | |
302 | * mcc tag is opaquely copied from mcc_wrb. | |
303 | */ | |
304 | be_dws_le_to_cpu(compl, 4); | |
6733b39a | 305 | compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & |
c448427b JB |
306 | CQE_STATUS_COMPL_MASK; |
307 | extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & | |
308 | CQE_STATUS_EXTD_MASK; | |
309 | /* Need to reset the entire word that houses the valid bit */ | |
310 | compl->flags = 0; | |
99bc5d55 | 311 | |
c448427b JB |
312 | if (compl_status == MCC_STATUS_SUCCESS) |
313 | return 0; | |
314 | ||
315 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, | |
316 | "BC_%d : error in cmd completion: Subsystem : %d Opcode : %d status(compl/extd)=%d/%d\n", | |
317 | hdr->subsystem, hdr->opcode, compl_status, extd_status); | |
318 | ||
319 | if (compl_status == MCC_STATUS_INSUFFICIENT_BUFFER) { | |
320 | /* if status is insufficient buffer, check the length */ | |
321 | resp_hdr = (struct be_cmd_resp_hdr *) hdr; | |
322 | if (resp_hdr->response_length) | |
323 | return 0; | |
6733b39a | 324 | } |
c448427b | 325 | return -EINVAL; |
6733b39a JK |
326 | } |
327 | ||
9c4f8b01 JB |
328 | static void beiscsi_process_async_link(struct beiscsi_hba *phba, |
329 | struct be_mcc_compl *compl) | |
bfead3b2 | 330 | { |
9c4f8b01 | 331 | struct be_async_event_link_state *evt; |
6ea9b3b0 | 332 | |
9c4f8b01 | 333 | evt = (struct be_async_event_link_state *)compl; |
99bc5d55 | 334 | |
9c4f8b01 JB |
335 | phba->port_speed = evt->port_speed; |
336 | /** | |
337 | * Check logical link status in ASYNC event. | |
338 | * This has been newly introduced in SKH-R Firmware 10.0.338.45. | |
339 | **/ | |
340 | if (evt->port_link_status & BE_ASYNC_LINK_UP_MASK) { | |
a3d313ea | 341 | phba->state = BE_ADAPTER_LINK_UP | BE_ADAPTER_CHECK_BOOT; |
3efde862 | 342 | phba->get_boot = BE_GET_BOOT_RETRIES; |
9c4f8b01 JB |
343 | __beiscsi_log(phba, KERN_ERR, |
344 | "BC_%d : Link Up on Port %d tag 0x%x\n", | |
345 | evt->physical_port, evt->event_tag); | |
346 | } else { | |
347 | phba->state = BE_ADAPTER_LINK_DOWN; | |
348 | __beiscsi_log(phba, KERN_ERR, | |
349 | "BC_%d : Link Down on Port %d tag 0x%x\n", | |
350 | evt->physical_port, evt->event_tag); | |
351 | iscsi_host_for_each_session(phba->shost, | |
352 | beiscsi_fail_session); | |
bfead3b2 | 353 | } |
6733b39a JK |
354 | } |
355 | ||
53aefe25 JB |
356 | static char *beiscsi_port_misconf_event_msg[] = { |
357 | "Physical Link is functional.", | |
358 | "Optics faulted/incorrectly installed/not installed - Reseat optics, if issue not resolved, replace.", | |
359 | "Optics of two types installed - Remove one optic or install matching pair of optics.", | |
360 | "Incompatible optics - Replace with compatible optics for card to function.", | |
361 | "Unqualified optics - Replace with Avago optics for Warranty and Technical Support.", | |
362 | "Uncertified optics - Replace with Avago Certified optics to enable link operation." | |
363 | }; | |
364 | ||
365 | static void beiscsi_process_async_sli(struct beiscsi_hba *phba, | |
366 | struct be_mcc_compl *compl) | |
367 | { | |
368 | struct be_async_event_sli *async_sli; | |
369 | u8 evt_type, state, old_state, le; | |
370 | char *sev = KERN_WARNING; | |
371 | char *msg = NULL; | |
372 | ||
373 | evt_type = compl->flags >> ASYNC_TRAILER_EVENT_TYPE_SHIFT; | |
374 | evt_type &= ASYNC_TRAILER_EVENT_TYPE_MASK; | |
375 | ||
376 | /* processing only MISCONFIGURED physical port event */ | |
377 | if (evt_type != ASYNC_SLI_EVENT_TYPE_MISCONFIGURED) | |
378 | return; | |
379 | ||
380 | async_sli = (struct be_async_event_sli *)compl; | |
381 | state = async_sli->event_data1 >> | |
382 | (phba->fw_config.phys_port * 8) & 0xff; | |
383 | le = async_sli->event_data2 >> | |
384 | (phba->fw_config.phys_port * 8) & 0xff; | |
385 | ||
386 | old_state = phba->optic_state; | |
387 | phba->optic_state = state; | |
388 | ||
389 | if (state >= ARRAY_SIZE(beiscsi_port_misconf_event_msg)) { | |
390 | /* fw is reporting a state we don't know, log and return */ | |
391 | __beiscsi_log(phba, KERN_ERR, | |
392 | "BC_%d : Port %c: Unrecognized optic state 0x%x\n", | |
393 | phba->port_name, async_sli->event_data1); | |
394 | return; | |
395 | } | |
396 | ||
397 | if (ASYNC_SLI_LINK_EFFECT_VALID(le)) { | |
398 | /* log link effect for unqualified-4, uncertified-5 optics */ | |
399 | if (state > 3) | |
400 | msg = (ASYNC_SLI_LINK_EFFECT_STATE(le)) ? | |
401 | " Link is non-operational." : | |
402 | " Link is operational."; | |
403 | /* 1 - info */ | |
404 | if (ASYNC_SLI_LINK_EFFECT_SEV(le) == 1) | |
405 | sev = KERN_INFO; | |
406 | /* 2 - error */ | |
407 | if (ASYNC_SLI_LINK_EFFECT_SEV(le) == 2) | |
408 | sev = KERN_ERR; | |
409 | } | |
410 | ||
411 | if (old_state != phba->optic_state) | |
412 | __beiscsi_log(phba, sev, "BC_%d : Port %c: %s%s\n", | |
413 | phba->port_name, | |
414 | beiscsi_port_misconf_event_msg[state], | |
415 | !msg ? "" : msg); | |
416 | } | |
417 | ||
418 | void beiscsi_process_async_event(struct beiscsi_hba *phba, | |
419 | struct be_mcc_compl *compl) | |
420 | { | |
421 | char *sev = KERN_INFO; | |
422 | u8 evt_code; | |
423 | ||
424 | /* interpret flags as an async trailer */ | |
425 | evt_code = compl->flags >> ASYNC_TRAILER_EVENT_CODE_SHIFT; | |
426 | evt_code &= ASYNC_TRAILER_EVENT_CODE_MASK; | |
427 | switch (evt_code) { | |
428 | case ASYNC_EVENT_CODE_LINK_STATE: | |
9c4f8b01 | 429 | beiscsi_process_async_link(phba, compl); |
53aefe25 JB |
430 | break; |
431 | case ASYNC_EVENT_CODE_ISCSI: | |
432 | phba->state |= BE_ADAPTER_CHECK_BOOT; | |
433 | phba->get_boot = BE_GET_BOOT_RETRIES; | |
434 | sev = KERN_ERR; | |
435 | break; | |
436 | case ASYNC_EVENT_CODE_SLI: | |
437 | beiscsi_process_async_sli(phba, compl); | |
438 | break; | |
439 | default: | |
440 | /* event not registered */ | |
441 | sev = KERN_ERR; | |
442 | } | |
443 | ||
444 | beiscsi_log(phba, sev, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, | |
9c4f8b01 JB |
445 | "BC_%d : ASYNC Event %x: status 0x%08x flags 0x%08x\n", |
446 | evt_code, compl->status, compl->flags); | |
53aefe25 JB |
447 | } |
448 | ||
2e4e8f65 JB |
449 | int beiscsi_process_mcc_compl(struct be_ctrl_info *ctrl, |
450 | struct be_mcc_compl *compl) | |
bfead3b2 | 451 | { |
2e4e8f65 JB |
452 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
453 | u16 compl_status, extd_status; | |
454 | struct be_dma_mem *tag_mem; | |
455 | unsigned int tag, wrb_idx; | |
456 | ||
2e4e8f65 JB |
457 | be_dws_le_to_cpu(compl, 4); |
458 | tag = (compl->tag0 & MCC_Q_CMD_TAG_MASK); | |
459 | wrb_idx = (compl->tag0 & CQE_STATUS_WRB_MASK) >> CQE_STATUS_WRB_SHIFT; | |
460 | ||
461 | if (!test_bit(MCC_TAG_STATE_RUNNING, | |
462 | &ctrl->ptag_state[tag].tag_state)) { | |
463 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX | | |
464 | BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, | |
465 | "BC_%d : MBX cmd completed but not posted\n"); | |
466 | return 0; | |
467 | } | |
468 | ||
469 | if (test_bit(MCC_TAG_STATE_TIMEOUT, &ctrl->ptag_state[tag].tag_state)) { | |
470 | beiscsi_log(phba, KERN_WARNING, | |
471 | BEISCSI_LOG_MBOX | BEISCSI_LOG_INIT | | |
472 | BEISCSI_LOG_CONFIG, | |
473 | "BC_%d : MBX Completion for timeout Command from FW\n"); | |
474 | /** | |
475 | * Check for the size before freeing resource. | |
476 | * Only for non-embedded cmd, PCI resource is allocated. | |
477 | **/ | |
478 | tag_mem = &ctrl->ptag_state[tag].tag_mem_state; | |
479 | if (tag_mem->size) | |
480 | pci_free_consistent(ctrl->pdev, tag_mem->size, | |
481 | tag_mem->va, tag_mem->dma); | |
482 | free_mcc_tag(ctrl, tag); | |
483 | return 0; | |
bfead3b2 JK |
484 | } |
485 | ||
2e4e8f65 JB |
486 | compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & |
487 | CQE_STATUS_COMPL_MASK; | |
488 | extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & | |
489 | CQE_STATUS_EXTD_MASK; | |
490 | /* The ctrl.mcc_tag_status[tag] is filled with | |
491 | * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status, | |
492 | * [7:0] = compl_status | |
493 | */ | |
494 | ctrl->mcc_tag_status[tag] = CQE_VALID_MASK; | |
495 | ctrl->mcc_tag_status[tag] |= (wrb_idx << CQE_STATUS_WRB_SHIFT); | |
496 | ctrl->mcc_tag_status[tag] |= (extd_status << CQE_STATUS_ADDL_SHIFT) & | |
497 | CQE_STATUS_ADDL_MASK; | |
498 | ctrl->mcc_tag_status[tag] |= (compl_status & CQE_STATUS_MASK); | |
bfead3b2 | 499 | |
2e4e8f65 JB |
500 | /* write ordering forced in wake_up_interruptible */ |
501 | clear_bit(MCC_TAG_STATE_RUNNING, &ctrl->ptag_state[tag].tag_state); | |
502 | wake_up_interruptible(&ctrl->mcc_wait[tag]); | |
503 | return 0; | |
bfead3b2 JK |
504 | } |
505 | ||
e175defe | 506 | /* |
88840332 | 507 | * be_mcc_compl_poll()- Wait for MBX completion |
e175defe JSJ |
508 | * @phba: driver private structure |
509 | * | |
510 | * Wait till no more pending mcc requests are present | |
511 | * | |
512 | * return | |
513 | * Success: 0 | |
514 | * Failure: Non-Zero | |
515 | * | |
516 | **/ | |
2e4e8f65 | 517 | int be_mcc_compl_poll(struct beiscsi_hba *phba, unsigned int tag) |
bfead3b2 | 518 | { |
69fd6d7b | 519 | struct be_ctrl_info *ctrl = &phba->ctrl; |
2e4e8f65 JB |
520 | int i; |
521 | ||
bfead3b2 | 522 | for (i = 0; i < mcc_timeout; i++) { |
7a158003 | 523 | if (beiscsi_error(phba)) |
e175defe JSJ |
524 | return -EIO; |
525 | ||
2e4e8f65 | 526 | beiscsi_process_mcc_cq(phba); |
bfead3b2 | 527 | |
69fd6d7b JB |
528 | if (!test_bit(MCC_TAG_STATE_RUNNING, |
529 | &ctrl->ptag_state[tag].tag_state)) | |
bfead3b2 JK |
530 | break; |
531 | udelay(100); | |
532 | } | |
69fd6d7b JB |
533 | |
534 | if (i < mcc_timeout) | |
535 | return 0; | |
536 | ||
537 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, | |
538 | "BC_%d : FW Timed Out\n"); | |
539 | phba->fw_timeout = true; | |
540 | beiscsi_ue_detect(phba); | |
541 | return -EBUSY; | |
542 | } | |
543 | ||
544 | void be_mcc_notify(struct beiscsi_hba *phba, unsigned int tag) | |
545 | { | |
546 | struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; | |
547 | u32 val = 0; | |
548 | ||
549 | set_bit(MCC_TAG_STATE_RUNNING, &phba->ctrl.ptag_state[tag].tag_state); | |
550 | val |= mccq->id & DB_MCCQ_RING_ID_MASK; | |
551 | val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; | |
552 | /* make request available for DMA */ | |
553 | wmb(); | |
554 | iowrite32(val, phba->db_va + DB_MCCQ_OFFSET); | |
bfead3b2 JK |
555 | } |
556 | ||
e175defe | 557 | /* |
88840332 | 558 | * be_mbox_db_ready_poll()- Check ready status |
e175defe JSJ |
559 | * @ctrl: Function specific MBX data structure |
560 | * | |
561 | * Check for the ready status of FW to send BMBX | |
562 | * commands to adapter. | |
563 | * | |
564 | * return | |
565 | * Success: 0 | |
566 | * Failure: Non-Zero | |
567 | **/ | |
88840332 | 568 | static int be_mbox_db_ready_poll(struct be_ctrl_info *ctrl) |
6733b39a | 569 | { |
9ec6f6b8 JB |
570 | /* wait 30s for generic non-flash MBOX operation */ |
571 | #define BEISCSI_MBX_RDY_BIT_TIMEOUT 30000 | |
6733b39a | 572 | void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET; |
e175defe | 573 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
92665a66 | 574 | unsigned long timeout; |
6733b39a JK |
575 | u32 ready; |
576 | ||
6ac999ef JB |
577 | /* |
578 | * This BMBX busy wait path is used during init only. | |
579 | * For the commands executed during init, 5s should suffice. | |
580 | */ | |
581 | timeout = jiffies + msecs_to_jiffies(BEISCSI_MBX_RDY_BIT_TIMEOUT); | |
582 | do { | |
583 | if (beiscsi_error(phba)) | |
584 | return -EIO; | |
7a158003 | 585 | |
6ac999ef JB |
586 | ready = ioread32(db); |
587 | if (ready == 0xffffffff) | |
588 | return -EIO; | |
e175defe | 589 | |
6ac999ef JB |
590 | ready &= MPU_MAILBOX_DB_RDY_MASK; |
591 | if (ready) | |
592 | return 0; | |
6733b39a | 593 | |
6ac999ef JB |
594 | if (time_after(jiffies, timeout)) |
595 | break; | |
9ec6f6b8 | 596 | msleep(20); |
6ac999ef | 597 | } while (!ready); |
92665a66 | 598 | |
6ac999ef JB |
599 | beiscsi_log(phba, KERN_ERR, |
600 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, | |
601 | "BC_%d : FW Timed Out\n"); | |
6733b39a | 602 | |
6ac999ef JB |
603 | phba->fw_timeout = true; |
604 | beiscsi_ue_detect(phba); | |
605 | ||
606 | return -EBUSY; | |
6733b39a JK |
607 | } |
608 | ||
e175defe JSJ |
609 | /* |
610 | * be_mbox_notify: Notify adapter of new BMBX command | |
611 | * @ctrl: Function specific MBX data structure | |
612 | * | |
613 | * Ring doorbell to inform adapter of a BMBX command | |
614 | * to process | |
615 | * | |
616 | * return | |
617 | * Success: 0 | |
618 | * Failure: Non-Zero | |
619 | **/ | |
6733b39a JK |
620 | int be_mbox_notify(struct be_ctrl_info *ctrl) |
621 | { | |
622 | int status; | |
623 | u32 val = 0; | |
624 | void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET; | |
625 | struct be_dma_mem *mbox_mem = &ctrl->mbox_mem; | |
626 | struct be_mcc_mailbox *mbox = mbox_mem->va; | |
6733b39a | 627 | |
88840332 | 628 | status = be_mbox_db_ready_poll(ctrl); |
1e234bbb JK |
629 | if (status) |
630 | return status; | |
631 | ||
6733b39a JK |
632 | val &= ~MPU_MAILBOX_DB_RDY_MASK; |
633 | val |= MPU_MAILBOX_DB_HI_MASK; | |
634 | val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; | |
635 | iowrite32(val, db); | |
636 | ||
88840332 | 637 | status = be_mbox_db_ready_poll(ctrl); |
e175defe | 638 | if (status) |
6733b39a | 639 | return status; |
e175defe | 640 | |
6733b39a JK |
641 | val = 0; |
642 | val &= ~MPU_MAILBOX_DB_RDY_MASK; | |
643 | val &= ~MPU_MAILBOX_DB_HI_MASK; | |
644 | val |= (u32) (mbox_mem->dma >> 4) << 2; | |
645 | iowrite32(val, db); | |
646 | ||
88840332 | 647 | status = be_mbox_db_ready_poll(ctrl); |
e175defe | 648 | if (status) |
6733b39a | 649 | return status; |
e175defe | 650 | |
6ac999ef JB |
651 | /* RDY is set; small delay before CQE read. */ |
652 | udelay(1); | |
653 | ||
a264f5e8 JB |
654 | status = beiscsi_process_mbox_compl(ctrl, &mbox->compl); |
655 | return status; | |
bfead3b2 JK |
656 | } |
657 | ||
6733b39a JK |
658 | void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, |
659 | bool embedded, u8 sge_cnt) | |
660 | { | |
661 | if (embedded) | |
662 | wrb->embedded |= MCC_WRB_EMBEDDED_MASK; | |
663 | else | |
664 | wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) << | |
665 | MCC_WRB_SGE_CNT_SHIFT; | |
666 | wrb->payload_length = payload_len; | |
667 | be_dws_cpu_to_le(wrb, 8); | |
668 | } | |
669 | ||
670 | void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, | |
671 | u8 subsystem, u8 opcode, int cmd_len) | |
672 | { | |
673 | req_hdr->opcode = opcode; | |
674 | req_hdr->subsystem = subsystem; | |
675 | req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); | |
e175defe | 676 | req_hdr->timeout = BEISCSI_FW_MBX_TIMEOUT; |
6733b39a JK |
677 | } |
678 | ||
679 | static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, | |
680 | struct be_dma_mem *mem) | |
681 | { | |
682 | int i, buf_pages; | |
683 | u64 dma = (u64) mem->dma; | |
684 | ||
685 | buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); | |
686 | for (i = 0; i < buf_pages; i++) { | |
687 | pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); | |
688 | pages[i].hi = cpu_to_le32(upper_32_bits(dma)); | |
689 | dma += PAGE_SIZE_4K; | |
690 | } | |
691 | } | |
692 | ||
693 | static u32 eq_delay_to_mult(u32 usec_delay) | |
694 | { | |
695 | #define MAX_INTR_RATE 651042 | |
696 | const u32 round = 10; | |
697 | u32 multiplier; | |
698 | ||
699 | if (usec_delay == 0) | |
700 | multiplier = 0; | |
701 | else { | |
702 | u32 interrupt_rate = 1000000 / usec_delay; | |
703 | if (interrupt_rate == 0) | |
704 | multiplier = 1023; | |
705 | else { | |
706 | multiplier = (MAX_INTR_RATE - interrupt_rate) * round; | |
707 | multiplier /= interrupt_rate; | |
708 | multiplier = (multiplier + round / 2) / round; | |
709 | multiplier = min(multiplier, (u32) 1023); | |
710 | } | |
711 | } | |
712 | return multiplier; | |
713 | } | |
714 | ||
715 | struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem) | |
716 | { | |
717 | return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; | |
718 | } | |
719 | ||
bfead3b2 JK |
720 | struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba) |
721 | { | |
722 | struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; | |
723 | struct be_mcc_wrb *wrb; | |
724 | ||
e074d20f | 725 | WARN_ON(atomic_read(&mccq->used) >= mccq->len); |
bfead3b2 | 726 | wrb = queue_head_node(mccq); |
756d29c8 | 727 | memset(wrb, 0, sizeof(*wrb)); |
67296ad9 | 728 | wrb->tag0 = (mccq->head << MCC_Q_WRB_IDX_SHIFT) & MCC_Q_WRB_IDX_MASK; |
bfead3b2 JK |
729 | queue_head_inc(mccq); |
730 | atomic_inc(&mccq->used); | |
bfead3b2 JK |
731 | return wrb; |
732 | } | |
733 | ||
734 | ||
6733b39a JK |
735 | int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl, |
736 | struct be_queue_info *eq, int eq_delay) | |
737 | { | |
738 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
739 | struct be_cmd_req_eq_create *req = embedded_payload(wrb); | |
740 | struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); | |
741 | struct be_dma_mem *q_mem = &eq->dma_mem; | |
742 | int status; | |
743 | ||
c03a50f7 | 744 | mutex_lock(&ctrl->mbox_lock); |
6733b39a JK |
745 | memset(wrb, 0, sizeof(*wrb)); |
746 | ||
747 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
748 | ||
749 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
750 | OPCODE_COMMON_EQ_CREATE, sizeof(*req)); | |
751 | ||
752 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
753 | ||
754 | AMAP_SET_BITS(struct amap_eq_context, func, req->context, | |
755 | PCI_FUNC(ctrl->pdev->devfn)); | |
756 | AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); | |
757 | AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); | |
758 | AMAP_SET_BITS(struct amap_eq_context, count, req->context, | |
759 | __ilog2_u32(eq->len / 256)); | |
760 | AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context, | |
761 | eq_delay_to_mult(eq_delay)); | |
762 | be_dws_cpu_to_le(req->context, sizeof(req->context)); | |
763 | ||
764 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
765 | ||
766 | status = be_mbox_notify(ctrl); | |
767 | if (!status) { | |
768 | eq->id = le16_to_cpu(resp->eq_id); | |
769 | eq->created = true; | |
770 | } | |
c03a50f7 | 771 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a JK |
772 | return status; |
773 | } | |
774 | ||
0283fbb1 JK |
775 | /** |
776 | * be_cmd_fw_initialize()- Initialize FW | |
777 | * @ctrl: Pointer to function control structure | |
778 | * | |
779 | * Send FW initialize pattern for the function. | |
780 | * | |
781 | * return | |
782 | * Success: 0 | |
783 | * Failure: Non-Zero value | |
784 | **/ | |
6733b39a JK |
785 | int be_cmd_fw_initialize(struct be_ctrl_info *ctrl) |
786 | { | |
787 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
99bc5d55 | 788 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
6733b39a JK |
789 | int status; |
790 | u8 *endian_check; | |
791 | ||
c03a50f7 | 792 | mutex_lock(&ctrl->mbox_lock); |
6733b39a JK |
793 | memset(wrb, 0, sizeof(*wrb)); |
794 | ||
795 | endian_check = (u8 *) wrb; | |
796 | *endian_check++ = 0xFF; | |
797 | *endian_check++ = 0x12; | |
798 | *endian_check++ = 0x34; | |
799 | *endian_check++ = 0xFF; | |
800 | *endian_check++ = 0xFF; | |
801 | *endian_check++ = 0x56; | |
802 | *endian_check++ = 0x78; | |
803 | *endian_check++ = 0xFF; | |
804 | be_dws_cpu_to_le(wrb, sizeof(*wrb)); | |
805 | ||
806 | status = be_mbox_notify(ctrl); | |
807 | if (status) | |
99bc5d55 JSJ |
808 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
809 | "BC_%d : be_cmd_fw_initialize Failed\n"); | |
6733b39a | 810 | |
c03a50f7 | 811 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a JK |
812 | return status; |
813 | } | |
814 | ||
0283fbb1 JK |
815 | /** |
816 | * be_cmd_fw_uninit()- Uinitialize FW | |
817 | * @ctrl: Pointer to function control structure | |
818 | * | |
819 | * Send FW uninitialize pattern for the function | |
820 | * | |
821 | * return | |
822 | * Success: 0 | |
823 | * Failure: Non-Zero value | |
824 | **/ | |
825 | int be_cmd_fw_uninit(struct be_ctrl_info *ctrl) | |
826 | { | |
827 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
828 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); | |
829 | int status; | |
830 | u8 *endian_check; | |
831 | ||
c03a50f7 | 832 | mutex_lock(&ctrl->mbox_lock); |
0283fbb1 JK |
833 | memset(wrb, 0, sizeof(*wrb)); |
834 | ||
835 | endian_check = (u8 *) wrb; | |
836 | *endian_check++ = 0xFF; | |
837 | *endian_check++ = 0xAA; | |
838 | *endian_check++ = 0xBB; | |
839 | *endian_check++ = 0xFF; | |
840 | *endian_check++ = 0xFF; | |
841 | *endian_check++ = 0xCC; | |
842 | *endian_check++ = 0xDD; | |
843 | *endian_check = 0xFF; | |
844 | ||
845 | be_dws_cpu_to_le(wrb, sizeof(*wrb)); | |
846 | ||
847 | status = be_mbox_notify(ctrl); | |
848 | if (status) | |
849 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
850 | "BC_%d : be_cmd_fw_uninit Failed\n"); | |
851 | ||
c03a50f7 | 852 | mutex_unlock(&ctrl->mbox_lock); |
0283fbb1 JK |
853 | return status; |
854 | } | |
855 | ||
6733b39a JK |
856 | int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl, |
857 | struct be_queue_info *cq, struct be_queue_info *eq, | |
858 | bool sol_evts, bool no_delay, int coalesce_wm) | |
859 | { | |
860 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
861 | struct be_cmd_req_cq_create *req = embedded_payload(wrb); | |
862 | struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); | |
99bc5d55 | 863 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
6733b39a JK |
864 | struct be_dma_mem *q_mem = &cq->dma_mem; |
865 | void *ctxt = &req->context; | |
866 | int status; | |
867 | ||
c03a50f7 | 868 | mutex_lock(&ctrl->mbox_lock); |
6733b39a JK |
869 | memset(wrb, 0, sizeof(*wrb)); |
870 | ||
871 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
872 | ||
873 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
874 | OPCODE_COMMON_CQ_CREATE, sizeof(*req)); | |
6733b39a JK |
875 | |
876 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
2c9dfd36 | 877 | if (is_chip_be2_be3r(phba)) { |
eaae5267 JSJ |
878 | AMAP_SET_BITS(struct amap_cq_context, coalescwm, |
879 | ctxt, coalesce_wm); | |
880 | AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay); | |
881 | AMAP_SET_BITS(struct amap_cq_context, count, ctxt, | |
882 | __ilog2_u32(cq->len / 256)); | |
883 | AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1); | |
884 | AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts); | |
885 | AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); | |
886 | AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); | |
887 | AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1); | |
888 | AMAP_SET_BITS(struct amap_cq_context, func, ctxt, | |
889 | PCI_FUNC(ctrl->pdev->devfn)); | |
2c9dfd36 JK |
890 | } else { |
891 | req->hdr.version = MBX_CMD_VER2; | |
892 | req->page_size = 1; | |
893 | AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm, | |
894 | ctxt, coalesce_wm); | |
895 | AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, | |
896 | ctxt, no_delay); | |
897 | AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt, | |
898 | __ilog2_u32(cq->len / 256)); | |
899 | AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1); | |
900 | AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1); | |
901 | AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id); | |
902 | AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1); | |
eaae5267 | 903 | } |
6733b39a | 904 | |
6733b39a JK |
905 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); |
906 | ||
907 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
908 | ||
909 | status = be_mbox_notify(ctrl); | |
910 | if (!status) { | |
911 | cq->id = le16_to_cpu(resp->cq_id); | |
912 | cq->created = true; | |
913 | } else | |
99bc5d55 JSJ |
914 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
915 | "BC_%d : In be_cmd_cq_create, status=ox%08x\n", | |
916 | status); | |
917 | ||
c03a50f7 | 918 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a JK |
919 | |
920 | return status; | |
921 | } | |
922 | ||
923 | static u32 be_encoded_q_len(int q_len) | |
924 | { | |
925 | u32 len_encoded = fls(q_len); /* log2(len) + 1 */ | |
926 | if (len_encoded == 16) | |
927 | len_encoded = 0; | |
928 | return len_encoded; | |
929 | } | |
bfead3b2 | 930 | |
35e66019 | 931 | int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba, |
bfead3b2 JK |
932 | struct be_queue_info *mccq, |
933 | struct be_queue_info *cq) | |
934 | { | |
935 | struct be_mcc_wrb *wrb; | |
53aefe25 | 936 | struct be_cmd_req_mcc_create_ext *req; |
bfead3b2 JK |
937 | struct be_dma_mem *q_mem = &mccq->dma_mem; |
938 | struct be_ctrl_info *ctrl; | |
939 | void *ctxt; | |
940 | int status; | |
941 | ||
c03a50f7 | 942 | mutex_lock(&phba->ctrl.mbox_lock); |
bfead3b2 JK |
943 | ctrl = &phba->ctrl; |
944 | wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
37609766 | 945 | memset(wrb, 0, sizeof(*wrb)); |
bfead3b2 JK |
946 | req = embedded_payload(wrb); |
947 | ctxt = &req->context; | |
948 | ||
949 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
950 | ||
951 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
53aefe25 | 952 | OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req)); |
bfead3b2 JK |
953 | |
954 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
53aefe25 JB |
955 | req->async_evt_bitmap = 1 << ASYNC_EVENT_CODE_LINK_STATE; |
956 | req->async_evt_bitmap |= 1 << ASYNC_EVENT_CODE_ISCSI; | |
957 | req->async_evt_bitmap |= 1 << ASYNC_EVENT_CODE_SLI; | |
bfead3b2 JK |
958 | |
959 | AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, | |
960 | PCI_FUNC(phba->pcidev->devfn)); | |
961 | AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1); | |
962 | AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt, | |
963 | be_encoded_q_len(mccq->len)); | |
964 | AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id); | |
965 | ||
966 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
967 | ||
968 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
969 | ||
a264f5e8 | 970 | status = be_mbox_notify(ctrl); |
bfead3b2 JK |
971 | if (!status) { |
972 | struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); | |
973 | mccq->id = le16_to_cpu(resp->id); | |
974 | mccq->created = true; | |
975 | } | |
c03a50f7 | 976 | mutex_unlock(&phba->ctrl.mbox_lock); |
bfead3b2 JK |
977 | |
978 | return status; | |
979 | } | |
980 | ||
6733b39a JK |
981 | int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, |
982 | int queue_type) | |
983 | { | |
984 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
985 | struct be_cmd_req_q_destroy *req = embedded_payload(wrb); | |
99bc5d55 | 986 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
6733b39a JK |
987 | u8 subsys = 0, opcode = 0; |
988 | int status; | |
989 | ||
99bc5d55 JSJ |
990 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
991 | "BC_%d : In beiscsi_cmd_q_destroy " | |
992 | "queue_type : %d\n", queue_type); | |
993 | ||
c03a50f7 | 994 | mutex_lock(&ctrl->mbox_lock); |
6733b39a JK |
995 | memset(wrb, 0, sizeof(*wrb)); |
996 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
997 | ||
998 | switch (queue_type) { | |
999 | case QTYPE_EQ: | |
1000 | subsys = CMD_SUBSYSTEM_COMMON; | |
1001 | opcode = OPCODE_COMMON_EQ_DESTROY; | |
1002 | break; | |
1003 | case QTYPE_CQ: | |
1004 | subsys = CMD_SUBSYSTEM_COMMON; | |
1005 | opcode = OPCODE_COMMON_CQ_DESTROY; | |
1006 | break; | |
bfead3b2 JK |
1007 | case QTYPE_MCCQ: |
1008 | subsys = CMD_SUBSYSTEM_COMMON; | |
1009 | opcode = OPCODE_COMMON_MCC_DESTROY; | |
1010 | break; | |
6733b39a JK |
1011 | case QTYPE_WRBQ: |
1012 | subsys = CMD_SUBSYSTEM_ISCSI; | |
1013 | opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY; | |
1014 | break; | |
1015 | case QTYPE_DPDUQ: | |
1016 | subsys = CMD_SUBSYSTEM_ISCSI; | |
1017 | opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY; | |
1018 | break; | |
1019 | case QTYPE_SGL: | |
1020 | subsys = CMD_SUBSYSTEM_ISCSI; | |
1021 | opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES; | |
1022 | break; | |
1023 | default: | |
c03a50f7 | 1024 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a | 1025 | BUG(); |
d3ad2bb3 | 1026 | return -ENXIO; |
6733b39a JK |
1027 | } |
1028 | be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); | |
1029 | if (queue_type != QTYPE_SGL) | |
1030 | req->id = cpu_to_le16(q->id); | |
1031 | ||
1032 | status = be_mbox_notify(ctrl); | |
1033 | ||
c03a50f7 | 1034 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a JK |
1035 | return status; |
1036 | } | |
1037 | ||
8a86e833 JK |
1038 | /** |
1039 | * be_cmd_create_default_pdu_queue()- Create DEFQ for the adapter | |
1040 | * @ctrl: ptr to ctrl_info | |
1041 | * @cq: Completion Queue | |
1042 | * @dq: Default Queue | |
1043 | * @lenght: ring size | |
1044 | * @entry_size: size of each entry in DEFQ | |
1045 | * @is_header: Header or Data DEFQ | |
1046 | * @ulp_num: Bind to which ULP | |
1047 | * | |
1048 | * Create HDR/Data DEFQ for the passed ULP. Unsol PDU are posted | |
1049 | * on this queue by the FW | |
1050 | * | |
1051 | * return | |
1052 | * Success: 0 | |
1053 | * Failure: Non-Zero Value | |
1054 | * | |
1055 | **/ | |
6733b39a JK |
1056 | int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl, |
1057 | struct be_queue_info *cq, | |
1058 | struct be_queue_info *dq, int length, | |
8a86e833 JK |
1059 | int entry_size, uint8_t is_header, |
1060 | uint8_t ulp_num) | |
6733b39a JK |
1061 | { |
1062 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1063 | struct be_defq_create_req *req = embedded_payload(wrb); | |
1064 | struct be_dma_mem *q_mem = &dq->dma_mem; | |
ef9e1b9b | 1065 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
6733b39a JK |
1066 | void *ctxt = &req->context; |
1067 | int status; | |
1068 | ||
c03a50f7 | 1069 | mutex_lock(&ctrl->mbox_lock); |
6733b39a JK |
1070 | memset(wrb, 0, sizeof(*wrb)); |
1071 | ||
1072 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1073 | ||
1074 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, | |
1075 | OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req)); | |
1076 | ||
1077 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
8a86e833 JK |
1078 | if (phba->fw_config.dual_ulp_aware) { |
1079 | req->ulp_num = ulp_num; | |
1080 | req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT); | |
1081 | req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT); | |
1082 | } | |
ef9e1b9b JK |
1083 | |
1084 | if (is_chip_be2_be3r(phba)) { | |
1085 | AMAP_SET_BITS(struct amap_be_default_pdu_context, | |
1086 | rx_pdid, ctxt, 0); | |
1087 | AMAP_SET_BITS(struct amap_be_default_pdu_context, | |
1088 | rx_pdid_valid, ctxt, 1); | |
1089 | AMAP_SET_BITS(struct amap_be_default_pdu_context, | |
1090 | pci_func_id, ctxt, PCI_FUNC(ctrl->pdev->devfn)); | |
1091 | AMAP_SET_BITS(struct amap_be_default_pdu_context, | |
1092 | ring_size, ctxt, | |
1093 | be_encoded_q_len(length / | |
1094 | sizeof(struct phys_addr))); | |
1095 | AMAP_SET_BITS(struct amap_be_default_pdu_context, | |
1096 | default_buffer_size, ctxt, entry_size); | |
1097 | AMAP_SET_BITS(struct amap_be_default_pdu_context, | |
1098 | cq_id_recv, ctxt, cq->id); | |
1099 | } else { | |
1100 | AMAP_SET_BITS(struct amap_default_pdu_context_ext, | |
1101 | rx_pdid, ctxt, 0); | |
1102 | AMAP_SET_BITS(struct amap_default_pdu_context_ext, | |
1103 | rx_pdid_valid, ctxt, 1); | |
1104 | AMAP_SET_BITS(struct amap_default_pdu_context_ext, | |
1105 | ring_size, ctxt, | |
1106 | be_encoded_q_len(length / | |
1107 | sizeof(struct phys_addr))); | |
1108 | AMAP_SET_BITS(struct amap_default_pdu_context_ext, | |
1109 | default_buffer_size, ctxt, entry_size); | |
1110 | AMAP_SET_BITS(struct amap_default_pdu_context_ext, | |
1111 | cq_id_recv, ctxt, cq->id); | |
1112 | } | |
6733b39a JK |
1113 | |
1114 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
1115 | ||
1116 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
1117 | ||
1118 | status = be_mbox_notify(ctrl); | |
1119 | if (!status) { | |
8a86e833 | 1120 | struct be_ring *defq_ring; |
6733b39a JK |
1121 | struct be_defq_create_resp *resp = embedded_payload(wrb); |
1122 | ||
1123 | dq->id = le16_to_cpu(resp->id); | |
1124 | dq->created = true; | |
8a86e833 JK |
1125 | if (is_header) |
1126 | defq_ring = &phba->phwi_ctrlr->default_pdu_hdr[ulp_num]; | |
1127 | else | |
1128 | defq_ring = &phba->phwi_ctrlr-> | |
1129 | default_pdu_data[ulp_num]; | |
1130 | ||
1131 | defq_ring->id = dq->id; | |
1132 | ||
1133 | if (!phba->fw_config.dual_ulp_aware) { | |
1134 | defq_ring->ulp_num = BEISCSI_ULP0; | |
1135 | defq_ring->doorbell_offset = DB_RXULP0_OFFSET; | |
1136 | } else { | |
1137 | defq_ring->ulp_num = resp->ulp_num; | |
1138 | defq_ring->doorbell_offset = resp->doorbell_offset; | |
1139 | } | |
6733b39a | 1140 | } |
c03a50f7 | 1141 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a JK |
1142 | |
1143 | return status; | |
1144 | } | |
1145 | ||
4eea99d5 JK |
1146 | /** |
1147 | * be_cmd_wrbq_create()- Create WRBQ | |
1148 | * @ctrl: ptr to ctrl_info | |
1149 | * @q_mem: memory details for the queue | |
1150 | * @wrbq: queue info | |
1151 | * @pwrb_context: ptr to wrb_context | |
1152 | * @ulp_num: ULP on which the WRBQ is to be created | |
1153 | * | |
1154 | * Create WRBQ on the passed ULP_NUM. | |
1155 | * | |
1156 | **/ | |
1157 | int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, | |
1158 | struct be_dma_mem *q_mem, | |
1159 | struct be_queue_info *wrbq, | |
1160 | struct hwi_wrb_context *pwrb_context, | |
1161 | uint8_t ulp_num) | |
6733b39a JK |
1162 | { |
1163 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1164 | struct be_wrbq_create_req *req = embedded_payload(wrb); | |
1165 | struct be_wrbq_create_resp *resp = embedded_payload(wrb); | |
4eea99d5 | 1166 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
6733b39a JK |
1167 | int status; |
1168 | ||
c03a50f7 | 1169 | mutex_lock(&ctrl->mbox_lock); |
6733b39a JK |
1170 | memset(wrb, 0, sizeof(*wrb)); |
1171 | ||
1172 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1173 | ||
1174 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, | |
1175 | OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req)); | |
1176 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
4eea99d5 JK |
1177 | |
1178 | if (phba->fw_config.dual_ulp_aware) { | |
1179 | req->ulp_num = ulp_num; | |
1180 | req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT); | |
1181 | req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT); | |
1182 | } | |
1183 | ||
6733b39a JK |
1184 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); |
1185 | ||
1186 | status = be_mbox_notify(ctrl); | |
bfead3b2 | 1187 | if (!status) { |
6733b39a | 1188 | wrbq->id = le16_to_cpu(resp->cid); |
bfead3b2 | 1189 | wrbq->created = true; |
4eea99d5 JK |
1190 | |
1191 | pwrb_context->cid = wrbq->id; | |
1192 | if (!phba->fw_config.dual_ulp_aware) { | |
1193 | pwrb_context->doorbell_offset = DB_TXULP0_OFFSET; | |
1194 | pwrb_context->ulp_num = BEISCSI_ULP0; | |
1195 | } else { | |
1196 | pwrb_context->ulp_num = resp->ulp_num; | |
1197 | pwrb_context->doorbell_offset = resp->doorbell_offset; | |
1198 | } | |
bfead3b2 | 1199 | } |
c03a50f7 | 1200 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a JK |
1201 | return status; |
1202 | } | |
1203 | ||
15a90fe0 JK |
1204 | int be_cmd_iscsi_post_template_hdr(struct be_ctrl_info *ctrl, |
1205 | struct be_dma_mem *q_mem) | |
1206 | { | |
1207 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1208 | struct be_post_template_pages_req *req = embedded_payload(wrb); | |
1209 | int status; | |
1210 | ||
c03a50f7 | 1211 | mutex_lock(&ctrl->mbox_lock); |
15a90fe0 JK |
1212 | |
1213 | memset(wrb, 0, sizeof(*wrb)); | |
1214 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1215 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1216 | OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS, | |
1217 | sizeof(*req)); | |
1218 | ||
1219 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
1220 | req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI; | |
1221 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
1222 | ||
1223 | status = be_mbox_notify(ctrl); | |
c03a50f7 | 1224 | mutex_unlock(&ctrl->mbox_lock); |
15a90fe0 JK |
1225 | return status; |
1226 | } | |
1227 | ||
1228 | int be_cmd_iscsi_remove_template_hdr(struct be_ctrl_info *ctrl) | |
1229 | { | |
1230 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1231 | struct be_remove_template_pages_req *req = embedded_payload(wrb); | |
1232 | int status; | |
1233 | ||
c03a50f7 | 1234 | mutex_lock(&ctrl->mbox_lock); |
15a90fe0 JK |
1235 | |
1236 | memset(wrb, 0, sizeof(*wrb)); | |
1237 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1238 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1239 | OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS, | |
1240 | sizeof(*req)); | |
1241 | ||
1242 | req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI; | |
1243 | ||
1244 | status = be_mbox_notify(ctrl); | |
c03a50f7 | 1245 | mutex_unlock(&ctrl->mbox_lock); |
15a90fe0 JK |
1246 | return status; |
1247 | } | |
1248 | ||
6733b39a JK |
1249 | int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl, |
1250 | struct be_dma_mem *q_mem, | |
1251 | u32 page_offset, u32 num_pages) | |
1252 | { | |
1253 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1254 | struct be_post_sgl_pages_req *req = embedded_payload(wrb); | |
99bc5d55 | 1255 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
6733b39a JK |
1256 | int status; |
1257 | unsigned int curr_pages; | |
1258 | u32 internal_page_offset = 0; | |
1259 | u32 temp_num_pages = num_pages; | |
1260 | ||
1261 | if (num_pages == 0xff) | |
1262 | num_pages = 1; | |
1263 | ||
c03a50f7 | 1264 | mutex_lock(&ctrl->mbox_lock); |
6733b39a JK |
1265 | do { |
1266 | memset(wrb, 0, sizeof(*wrb)); | |
1267 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1268 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, | |
1269 | OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES, | |
1270 | sizeof(*req)); | |
1271 | curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req, | |
1272 | pages); | |
1273 | req->num_pages = min(num_pages, curr_pages); | |
1274 | req->page_offset = page_offset; | |
1275 | be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem); | |
1276 | q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE); | |
1277 | internal_page_offset += req->num_pages; | |
1278 | page_offset += req->num_pages; | |
1279 | num_pages -= req->num_pages; | |
1280 | ||
1281 | if (temp_num_pages == 0xff) | |
1282 | req->num_pages = temp_num_pages; | |
1283 | ||
1284 | status = be_mbox_notify(ctrl); | |
1285 | if (status) { | |
99bc5d55 JSJ |
1286 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
1287 | "BC_%d : FW CMD to map iscsi frags failed.\n"); | |
1288 | ||
6733b39a JK |
1289 | goto error; |
1290 | } | |
1291 | } while (num_pages > 0); | |
1292 | error: | |
c03a50f7 | 1293 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a JK |
1294 | if (status != 0) |
1295 | beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL); | |
1296 | return status; | |
1297 | } | |
e5285860 JK |
1298 | |
1299 | int beiscsi_cmd_reset_function(struct beiscsi_hba *phba) | |
1300 | { | |
1301 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
1302 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1303 | struct be_post_sgl_pages_req *req = embedded_payload(wrb); | |
1304 | int status; | |
1305 | ||
c03a50f7 | 1306 | mutex_lock(&ctrl->mbox_lock); |
e5285860 JK |
1307 | |
1308 | req = embedded_payload(wrb); | |
1309 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1310 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1311 | OPCODE_COMMON_FUNCTION_RESET, sizeof(*req)); | |
a264f5e8 | 1312 | status = be_mbox_notify(ctrl); |
e5285860 | 1313 | |
c03a50f7 | 1314 | mutex_unlock(&ctrl->mbox_lock); |
e5285860 JK |
1315 | return status; |
1316 | } | |
6f72238e JSJ |
1317 | |
1318 | /** | |
1319 | * be_cmd_set_vlan()- Configure VLAN paramters on the adapter | |
1320 | * @phba: device priv structure instance | |
1321 | * @vlan_tag: TAG to be set | |
1322 | * | |
1323 | * Set the VLAN_TAG for the adapter or Disable VLAN on adapter | |
1324 | * | |
1325 | * returns | |
1326 | * TAG for the MBX Cmd | |
1327 | * **/ | |
1328 | int be_cmd_set_vlan(struct beiscsi_hba *phba, | |
1329 | uint16_t vlan_tag) | |
1330 | { | |
1331 | unsigned int tag = 0; | |
1332 | struct be_mcc_wrb *wrb; | |
1333 | struct be_cmd_set_vlan_req *req; | |
1334 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
1335 | ||
c03a50f7 JB |
1336 | if (mutex_lock_interruptible(&ctrl->mbox_lock)) |
1337 | return 0; | |
6f72238e JSJ |
1338 | tag = alloc_mcc_tag(phba); |
1339 | if (!tag) { | |
c03a50f7 | 1340 | mutex_unlock(&ctrl->mbox_lock); |
6f72238e JSJ |
1341 | return tag; |
1342 | } | |
1343 | ||
1344 | wrb = wrb_from_mccq(phba); | |
1345 | req = embedded_payload(wrb); | |
1346 | wrb->tag0 |= tag; | |
1347 | be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0); | |
1348 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, | |
1349 | OPCODE_COMMON_ISCSI_NTWK_SET_VLAN, | |
1350 | sizeof(*req)); | |
1351 | ||
1352 | req->interface_hndl = phba->interface_handle; | |
1353 | req->vlan_priority = vlan_tag; | |
1354 | ||
cdde6682 | 1355 | be_mcc_notify(phba, tag); |
c03a50f7 | 1356 | mutex_unlock(&ctrl->mbox_lock); |
6f72238e JSJ |
1357 | |
1358 | return tag; | |
1359 | } |