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6733b39a | 1 | /** |
c4f39bda | 2 | * Copyright (C) 2005 - 2015 Emulex |
6733b39a JK |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
4627de93 | 11 | * linux-drivers@avagotech.com |
6733b39a | 12 | * |
c4f39bda | 13 | * Emulex |
255fa9a3 JK |
14 | * 3333 Susan Street |
15 | * Costa Mesa, CA 92626 | |
6733b39a JK |
16 | */ |
17 | ||
2177199d JSJ |
18 | #include <scsi/iscsi_proto.h> |
19 | ||
4eea99d5 | 20 | #include "be_main.h" |
6733b39a JK |
21 | #include "be.h" |
22 | #include "be_mgmt.h" | |
6733b39a | 23 | |
090e2184 JB |
24 | struct be_mcc_wrb *alloc_mcc_wrb(struct beiscsi_hba *phba, |
25 | unsigned int *ref_tag) | |
69fd6d7b | 26 | { |
090e2184 JB |
27 | struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; |
28 | struct be_mcc_wrb *wrb = NULL; | |
29 | unsigned int tag; | |
30 | ||
96eb8d4d | 31 | spin_lock(&phba->ctrl.mcc_lock); |
090e2184 JB |
32 | if (mccq->used == mccq->len) { |
33 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT | | |
34 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, | |
35 | "BC_%d : MCC queue full: WRB used %u tag avail %u\n", | |
36 | mccq->used, phba->ctrl.mcc_tag_available); | |
37 | goto alloc_failed; | |
38 | } | |
39 | ||
40 | if (!phba->ctrl.mcc_tag_available) | |
41 | goto alloc_failed; | |
42 | ||
43 | tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index]; | |
44 | if (!tag) { | |
45 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT | | |
46 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, | |
47 | "BC_%d : MCC tag 0 allocated: tag avail %u alloc index %u\n", | |
48 | phba->ctrl.mcc_tag_available, | |
49 | phba->ctrl.mcc_alloc_index); | |
50 | goto alloc_failed; | |
51 | } | |
52 | ||
53 | /* return this tag for further reference */ | |
54 | *ref_tag = tag; | |
55 | phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0; | |
56 | phba->ctrl.mcc_tag_status[tag] = 0; | |
57 | phba->ctrl.ptag_state[tag].tag_state = 0; | |
50a4b824 | 58 | phba->ctrl.ptag_state[tag].cbfn = NULL; |
090e2184 JB |
59 | phba->ctrl.mcc_tag_available--; |
60 | if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1)) | |
61 | phba->ctrl.mcc_alloc_index = 0; | |
62 | else | |
63 | phba->ctrl.mcc_alloc_index++; | |
64 | ||
65 | wrb = queue_head_node(mccq); | |
66 | memset(wrb, 0, sizeof(*wrb)); | |
67 | wrb->tag0 = tag; | |
68 | wrb->tag0 |= (mccq->head << MCC_Q_WRB_IDX_SHIFT) & MCC_Q_WRB_IDX_MASK; | |
69 | queue_head_inc(mccq); | |
70 | mccq->used++; | |
71 | ||
72 | alloc_failed: | |
96eb8d4d | 73 | spin_unlock(&phba->ctrl.mcc_lock); |
090e2184 JB |
74 | return wrb; |
75 | } | |
76 | ||
77 | void free_mcc_wrb(struct be_ctrl_info *ctrl, unsigned int tag) | |
78 | { | |
79 | struct be_queue_info *mccq = &ctrl->mcc_obj.q; | |
80 | ||
96eb8d4d | 81 | spin_lock(&ctrl->mcc_lock); |
69fd6d7b JB |
82 | tag = tag & MCC_Q_CMD_TAG_MASK; |
83 | ctrl->mcc_tag[ctrl->mcc_free_index] = tag; | |
84 | if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1)) | |
85 | ctrl->mcc_free_index = 0; | |
86 | else | |
87 | ctrl->mcc_free_index++; | |
88 | ctrl->mcc_tag_available++; | |
090e2184 | 89 | mccq->used--; |
96eb8d4d | 90 | spin_unlock(&ctrl->mcc_lock); |
69fd6d7b JB |
91 | } |
92 | ||
50a4b824 JB |
93 | /* |
94 | * beiscsi_mcc_compl_status - Return the status of MCC completion | |
95 | * @phba: Driver private structure | |
96 | * @tag: Tag for the MBX Command | |
97 | * @wrb: the WRB used for the MBX Command | |
98 | * @mbx_cmd_mem: ptr to memory allocated for MBX Cmd | |
99 | * | |
100 | * return | |
101 | * Success: 0 | |
102 | * Failure: Non-Zero | |
103 | */ | |
104 | int __beiscsi_mcc_compl_status(struct beiscsi_hba *phba, | |
105 | unsigned int tag, | |
106 | struct be_mcc_wrb **wrb, | |
107 | struct be_dma_mem *mbx_cmd_mem) | |
108 | { | |
109 | struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; | |
110 | uint16_t status = 0, addl_status = 0, wrb_num = 0; | |
111 | struct be_cmd_resp_hdr *mbx_resp_hdr; | |
112 | struct be_cmd_req_hdr *mbx_hdr; | |
113 | struct be_mcc_wrb *temp_wrb; | |
114 | uint32_t mcc_tag_status; | |
115 | int rc = 0; | |
116 | ||
117 | mcc_tag_status = phba->ctrl.mcc_tag_status[tag]; | |
118 | status = (mcc_tag_status & CQE_STATUS_MASK); | |
119 | addl_status = ((mcc_tag_status & CQE_STATUS_ADDL_MASK) >> | |
120 | CQE_STATUS_ADDL_SHIFT); | |
121 | ||
122 | if (mbx_cmd_mem) { | |
123 | mbx_hdr = (struct be_cmd_req_hdr *)mbx_cmd_mem->va; | |
124 | } else { | |
125 | wrb_num = (mcc_tag_status & CQE_STATUS_WRB_MASK) >> | |
126 | CQE_STATUS_WRB_SHIFT; | |
127 | temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num); | |
128 | mbx_hdr = embedded_payload(temp_wrb); | |
129 | ||
130 | if (wrb) | |
131 | *wrb = temp_wrb; | |
132 | } | |
133 | ||
134 | if (status || addl_status) { | |
135 | beiscsi_log(phba, KERN_WARNING, | |
136 | BEISCSI_LOG_INIT | BEISCSI_LOG_EH | | |
137 | BEISCSI_LOG_CONFIG, | |
138 | "BC_%d : MBX Cmd Failed for Subsys : %d Opcode : %d with Status : %d and Extd_Status : %d\n", | |
139 | mbx_hdr->subsystem, mbx_hdr->opcode, | |
140 | status, addl_status); | |
141 | rc = -EIO; | |
142 | if (status == MCC_STATUS_INSUFFICIENT_BUFFER) { | |
143 | mbx_resp_hdr = (struct be_cmd_resp_hdr *)mbx_hdr; | |
144 | beiscsi_log(phba, KERN_WARNING, | |
145 | BEISCSI_LOG_INIT | BEISCSI_LOG_EH | | |
146 | BEISCSI_LOG_CONFIG, | |
147 | "BC_%d : Insufficient Buffer Error Resp_Len : %d Actual_Resp_Len : %d\n", | |
148 | mbx_resp_hdr->response_length, | |
149 | mbx_resp_hdr->actual_resp_len); | |
150 | rc = -EAGAIN; | |
151 | } | |
152 | } | |
153 | ||
154 | return rc; | |
155 | } | |
156 | ||
e175defe | 157 | /* |
88840332 | 158 | * beiscsi_mccq_compl_wait()- Process completion in MCC CQ |
e175defe JSJ |
159 | * @phba: Driver private structure |
160 | * @tag: Tag for the MBX Command | |
161 | * @wrb: the WRB used for the MBX Command | |
1957aa7f | 162 | * @mbx_cmd_mem: ptr to memory allocated for MBX Cmd |
e175defe JSJ |
163 | * |
164 | * Waits for MBX completion with the passed TAG. | |
165 | * | |
166 | * return | |
167 | * Success: 0 | |
168 | * Failure: Non-Zero | |
169 | **/ | |
88840332 | 170 | int beiscsi_mccq_compl_wait(struct beiscsi_hba *phba, |
50a4b824 JB |
171 | unsigned int tag, |
172 | struct be_mcc_wrb **wrb, | |
88840332 | 173 | struct be_dma_mem *mbx_cmd_mem) |
e175defe JSJ |
174 | { |
175 | int rc = 0; | |
e175defe | 176 | |
9122e991 JB |
177 | if (beiscsi_hba_in_error(phba)) { |
178 | clear_bit(MCC_TAG_STATE_RUNNING, | |
179 | &phba->ctrl.ptag_state[tag].tag_state); | |
180 | return -EIO; | |
181 | } | |
7a158003 | 182 | |
e175defe | 183 | /* wait for the mccq completion */ |
50a4b824 JB |
184 | rc = wait_event_interruptible_timeout(phba->ctrl.mcc_wait[tag], |
185 | phba->ctrl.mcc_tag_status[tag], | |
186 | msecs_to_jiffies( | |
187 | BEISCSI_HOST_MBX_TIMEOUT)); | |
188 | ||
cdde6682 JB |
189 | /** |
190 | * If MBOX cmd timeout expired, tag and resource allocated | |
191 | * for cmd is not freed until FW returns completion. | |
192 | */ | |
e175defe | 193 | if (rc <= 0) { |
1957aa7f | 194 | struct be_dma_mem *tag_mem; |
1957aa7f | 195 | |
cdde6682 JB |
196 | /** |
197 | * PCI/DMA memory allocated and posted in non-embedded mode | |
198 | * will have mbx_cmd_mem != NULL. | |
199 | * Save virtual and bus addresses for the command so that it | |
200 | * can be freed later. | |
201 | **/ | |
1957aa7f JK |
202 | tag_mem = &phba->ctrl.ptag_state[tag].tag_mem_state; |
203 | if (mbx_cmd_mem) { | |
204 | tag_mem->size = mbx_cmd_mem->size; | |
205 | tag_mem->va = mbx_cmd_mem->va; | |
206 | tag_mem->dma = mbx_cmd_mem->dma; | |
207 | } else | |
208 | tag_mem->size = 0; | |
209 | ||
cdde6682 JB |
210 | /* first make tag_mem_state visible to all */ |
211 | wmb(); | |
212 | set_bit(MCC_TAG_STATE_TIMEOUT, | |
213 | &phba->ctrl.ptag_state[tag].tag_state); | |
214 | ||
e175defe JSJ |
215 | beiscsi_log(phba, KERN_ERR, |
216 | BEISCSI_LOG_INIT | BEISCSI_LOG_EH | | |
217 | BEISCSI_LOG_CONFIG, | |
218 | "BC_%d : MBX Cmd Completion timed out\n"); | |
1957aa7f | 219 | return -EBUSY; |
1957aa7f | 220 | } |
e175defe | 221 | |
50a4b824 | 222 | rc = __beiscsi_mcc_compl_status(phba, tag, wrb, mbx_cmd_mem); |
e175defe | 223 | |
090e2184 | 224 | free_mcc_wrb(&phba->ctrl, tag); |
e175defe JSJ |
225 | return rc; |
226 | } | |
227 | ||
e175defe | 228 | /* |
88840332 | 229 | * beiscsi_process_mbox_compl()- Check the MBX completion status |
e175defe JSJ |
230 | * @ctrl: Function specific MBX data structure |
231 | * @compl: Completion status of MBX Command | |
232 | * | |
233 | * Check for the MBX completion status when BMBX method used | |
234 | * | |
235 | * return | |
236 | * Success: Zero | |
237 | * Failure: Non-Zero | |
238 | **/ | |
88840332 JB |
239 | static int beiscsi_process_mbox_compl(struct be_ctrl_info *ctrl, |
240 | struct be_mcc_compl *compl) | |
6733b39a | 241 | { |
e175defe | 242 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); |
99bc5d55 | 243 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
e175defe | 244 | struct be_cmd_req_hdr *hdr = embedded_payload(wrb); |
6694095b | 245 | u16 compl_status, extd_status; |
6733b39a | 246 | |
c448427b JB |
247 | /** |
248 | * To check if valid bit is set, check the entire word as we don't know | |
249 | * the endianness of the data (old entry is host endian while a new | |
250 | * entry is little endian) | |
251 | */ | |
252 | if (!compl->flags) { | |
253 | beiscsi_log(phba, KERN_ERR, | |
254 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, | |
255 | "BC_%d : BMBX busy, no completion\n"); | |
256 | return -EBUSY; | |
257 | } | |
258 | compl->flags = le32_to_cpu(compl->flags); | |
259 | WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0); | |
6733b39a | 260 | |
c448427b JB |
261 | /** |
262 | * Just swap the status to host endian; | |
263 | * mcc tag is opaquely copied from mcc_wrb. | |
264 | */ | |
265 | be_dws_le_to_cpu(compl, 4); | |
6733b39a | 266 | compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & |
c448427b JB |
267 | CQE_STATUS_COMPL_MASK; |
268 | extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & | |
269 | CQE_STATUS_EXTD_MASK; | |
270 | /* Need to reset the entire word that houses the valid bit */ | |
271 | compl->flags = 0; | |
99bc5d55 | 272 | |
c448427b JB |
273 | if (compl_status == MCC_STATUS_SUCCESS) |
274 | return 0; | |
275 | ||
276 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, | |
277 | "BC_%d : error in cmd completion: Subsystem : %d Opcode : %d status(compl/extd)=%d/%d\n", | |
278 | hdr->subsystem, hdr->opcode, compl_status, extd_status); | |
6694095b | 279 | return compl_status; |
6733b39a JK |
280 | } |
281 | ||
9c4f8b01 JB |
282 | static void beiscsi_process_async_link(struct beiscsi_hba *phba, |
283 | struct be_mcc_compl *compl) | |
bfead3b2 | 284 | { |
9c4f8b01 | 285 | struct be_async_event_link_state *evt; |
6ea9b3b0 | 286 | |
9c4f8b01 | 287 | evt = (struct be_async_event_link_state *)compl; |
99bc5d55 | 288 | |
9c4f8b01 JB |
289 | phba->port_speed = evt->port_speed; |
290 | /** | |
291 | * Check logical link status in ASYNC event. | |
292 | * This has been newly introduced in SKH-R Firmware 10.0.338.45. | |
293 | **/ | |
294 | if (evt->port_link_status & BE_ASYNC_LINK_UP_MASK) { | |
50a4b824 JB |
295 | set_bit(BEISCSI_HBA_LINK_UP, &phba->state); |
296 | if (test_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state)) | |
297 | beiscsi_start_boot_work(phba, BE_BOOT_INVALID_SHANDLE); | |
9c4f8b01 JB |
298 | __beiscsi_log(phba, KERN_ERR, |
299 | "BC_%d : Link Up on Port %d tag 0x%x\n", | |
300 | evt->physical_port, evt->event_tag); | |
301 | } else { | |
9122e991 | 302 | clear_bit(BEISCSI_HBA_LINK_UP, &phba->state); |
9c4f8b01 JB |
303 | __beiscsi_log(phba, KERN_ERR, |
304 | "BC_%d : Link Down on Port %d tag 0x%x\n", | |
305 | evt->physical_port, evt->event_tag); | |
306 | iscsi_host_for_each_session(phba->shost, | |
480195c2 | 307 | beiscsi_session_fail); |
bfead3b2 | 308 | } |
6733b39a JK |
309 | } |
310 | ||
53aefe25 JB |
311 | static char *beiscsi_port_misconf_event_msg[] = { |
312 | "Physical Link is functional.", | |
313 | "Optics faulted/incorrectly installed/not installed - Reseat optics, if issue not resolved, replace.", | |
314 | "Optics of two types installed - Remove one optic or install matching pair of optics.", | |
315 | "Incompatible optics - Replace with compatible optics for card to function.", | |
316 | "Unqualified optics - Replace with Avago optics for Warranty and Technical Support.", | |
317 | "Uncertified optics - Replace with Avago Certified optics to enable link operation." | |
318 | }; | |
319 | ||
320 | static void beiscsi_process_async_sli(struct beiscsi_hba *phba, | |
321 | struct be_mcc_compl *compl) | |
322 | { | |
323 | struct be_async_event_sli *async_sli; | |
324 | u8 evt_type, state, old_state, le; | |
325 | char *sev = KERN_WARNING; | |
326 | char *msg = NULL; | |
327 | ||
328 | evt_type = compl->flags >> ASYNC_TRAILER_EVENT_TYPE_SHIFT; | |
329 | evt_type &= ASYNC_TRAILER_EVENT_TYPE_MASK; | |
330 | ||
331 | /* processing only MISCONFIGURED physical port event */ | |
332 | if (evt_type != ASYNC_SLI_EVENT_TYPE_MISCONFIGURED) | |
333 | return; | |
334 | ||
335 | async_sli = (struct be_async_event_sli *)compl; | |
336 | state = async_sli->event_data1 >> | |
337 | (phba->fw_config.phys_port * 8) & 0xff; | |
338 | le = async_sli->event_data2 >> | |
339 | (phba->fw_config.phys_port * 8) & 0xff; | |
340 | ||
341 | old_state = phba->optic_state; | |
342 | phba->optic_state = state; | |
343 | ||
344 | if (state >= ARRAY_SIZE(beiscsi_port_misconf_event_msg)) { | |
345 | /* fw is reporting a state we don't know, log and return */ | |
346 | __beiscsi_log(phba, KERN_ERR, | |
347 | "BC_%d : Port %c: Unrecognized optic state 0x%x\n", | |
348 | phba->port_name, async_sli->event_data1); | |
349 | return; | |
350 | } | |
351 | ||
352 | if (ASYNC_SLI_LINK_EFFECT_VALID(le)) { | |
353 | /* log link effect for unqualified-4, uncertified-5 optics */ | |
354 | if (state > 3) | |
355 | msg = (ASYNC_SLI_LINK_EFFECT_STATE(le)) ? | |
356 | " Link is non-operational." : | |
357 | " Link is operational."; | |
358 | /* 1 - info */ | |
359 | if (ASYNC_SLI_LINK_EFFECT_SEV(le) == 1) | |
360 | sev = KERN_INFO; | |
361 | /* 2 - error */ | |
362 | if (ASYNC_SLI_LINK_EFFECT_SEV(le) == 2) | |
363 | sev = KERN_ERR; | |
364 | } | |
365 | ||
366 | if (old_state != phba->optic_state) | |
367 | __beiscsi_log(phba, sev, "BC_%d : Port %c: %s%s\n", | |
368 | phba->port_name, | |
369 | beiscsi_port_misconf_event_msg[state], | |
370 | !msg ? "" : msg); | |
371 | } | |
372 | ||
373 | void beiscsi_process_async_event(struct beiscsi_hba *phba, | |
374 | struct be_mcc_compl *compl) | |
375 | { | |
376 | char *sev = KERN_INFO; | |
377 | u8 evt_code; | |
378 | ||
379 | /* interpret flags as an async trailer */ | |
380 | evt_code = compl->flags >> ASYNC_TRAILER_EVENT_CODE_SHIFT; | |
381 | evt_code &= ASYNC_TRAILER_EVENT_CODE_MASK; | |
382 | switch (evt_code) { | |
383 | case ASYNC_EVENT_CODE_LINK_STATE: | |
9c4f8b01 | 384 | beiscsi_process_async_link(phba, compl); |
53aefe25 JB |
385 | break; |
386 | case ASYNC_EVENT_CODE_ISCSI: | |
50a4b824 JB |
387 | if (test_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state)) |
388 | beiscsi_start_boot_work(phba, BE_BOOT_INVALID_SHANDLE); | |
53aefe25 JB |
389 | sev = KERN_ERR; |
390 | break; | |
391 | case ASYNC_EVENT_CODE_SLI: | |
392 | beiscsi_process_async_sli(phba, compl); | |
393 | break; | |
394 | default: | |
395 | /* event not registered */ | |
396 | sev = KERN_ERR; | |
397 | } | |
398 | ||
399 | beiscsi_log(phba, sev, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, | |
9c4f8b01 JB |
400 | "BC_%d : ASYNC Event %x: status 0x%08x flags 0x%08x\n", |
401 | evt_code, compl->status, compl->flags); | |
53aefe25 JB |
402 | } |
403 | ||
2e4e8f65 JB |
404 | int beiscsi_process_mcc_compl(struct be_ctrl_info *ctrl, |
405 | struct be_mcc_compl *compl) | |
bfead3b2 | 406 | { |
2e4e8f65 JB |
407 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
408 | u16 compl_status, extd_status; | |
409 | struct be_dma_mem *tag_mem; | |
410 | unsigned int tag, wrb_idx; | |
411 | ||
2e4e8f65 JB |
412 | be_dws_le_to_cpu(compl, 4); |
413 | tag = (compl->tag0 & MCC_Q_CMD_TAG_MASK); | |
414 | wrb_idx = (compl->tag0 & CQE_STATUS_WRB_MASK) >> CQE_STATUS_WRB_SHIFT; | |
415 | ||
416 | if (!test_bit(MCC_TAG_STATE_RUNNING, | |
417 | &ctrl->ptag_state[tag].tag_state)) { | |
418 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX | | |
419 | BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, | |
420 | "BC_%d : MBX cmd completed but not posted\n"); | |
421 | return 0; | |
422 | } | |
423 | ||
50a4b824 JB |
424 | /* end MCC with this tag */ |
425 | clear_bit(MCC_TAG_STATE_RUNNING, &ctrl->ptag_state[tag].tag_state); | |
426 | ||
2e4e8f65 JB |
427 | if (test_bit(MCC_TAG_STATE_TIMEOUT, &ctrl->ptag_state[tag].tag_state)) { |
428 | beiscsi_log(phba, KERN_WARNING, | |
429 | BEISCSI_LOG_MBOX | BEISCSI_LOG_INIT | | |
430 | BEISCSI_LOG_CONFIG, | |
431 | "BC_%d : MBX Completion for timeout Command from FW\n"); | |
432 | /** | |
433 | * Check for the size before freeing resource. | |
434 | * Only for non-embedded cmd, PCI resource is allocated. | |
435 | **/ | |
436 | tag_mem = &ctrl->ptag_state[tag].tag_mem_state; | |
50a4b824 | 437 | if (tag_mem->size) { |
2e4e8f65 JB |
438 | pci_free_consistent(ctrl->pdev, tag_mem->size, |
439 | tag_mem->va, tag_mem->dma); | |
50a4b824 JB |
440 | tag_mem->size = 0; |
441 | } | |
090e2184 | 442 | free_mcc_wrb(ctrl, tag); |
2e4e8f65 | 443 | return 0; |
bfead3b2 JK |
444 | } |
445 | ||
2e4e8f65 JB |
446 | compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & |
447 | CQE_STATUS_COMPL_MASK; | |
448 | extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & | |
449 | CQE_STATUS_EXTD_MASK; | |
450 | /* The ctrl.mcc_tag_status[tag] is filled with | |
451 | * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status, | |
452 | * [7:0] = compl_status | |
453 | */ | |
454 | ctrl->mcc_tag_status[tag] = CQE_VALID_MASK; | |
455 | ctrl->mcc_tag_status[tag] |= (wrb_idx << CQE_STATUS_WRB_SHIFT); | |
456 | ctrl->mcc_tag_status[tag] |= (extd_status << CQE_STATUS_ADDL_SHIFT) & | |
457 | CQE_STATUS_ADDL_MASK; | |
458 | ctrl->mcc_tag_status[tag] |= (compl_status & CQE_STATUS_MASK); | |
bfead3b2 | 459 | |
50a4b824 JB |
460 | if (test_bit(MCC_TAG_STATE_ASYNC, &ctrl->ptag_state[tag].tag_state)) { |
461 | if (ctrl->ptag_state[tag].cbfn) | |
462 | ctrl->ptag_state[tag].cbfn(phba, tag); | |
463 | else | |
6694095b JB |
464 | __beiscsi_log(phba, KERN_ERR, |
465 | "BC_%d : MBX ASYNC command with no callback\n"); | |
50a4b824 JB |
466 | free_mcc_wrb(ctrl, tag); |
467 | return 0; | |
468 | } | |
469 | ||
10bcd47d JB |
470 | if (test_bit(MCC_TAG_STATE_IGNORE, &ctrl->ptag_state[tag].tag_state)) { |
471 | /* just check completion status and free wrb */ | |
472 | __beiscsi_mcc_compl_status(phba, tag, NULL, NULL); | |
473 | free_mcc_wrb(ctrl, tag); | |
474 | return 0; | |
475 | } | |
476 | ||
2e4e8f65 JB |
477 | wake_up_interruptible(&ctrl->mcc_wait[tag]); |
478 | return 0; | |
bfead3b2 JK |
479 | } |
480 | ||
69fd6d7b JB |
481 | void be_mcc_notify(struct beiscsi_hba *phba, unsigned int tag) |
482 | { | |
483 | struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; | |
484 | u32 val = 0; | |
485 | ||
486 | set_bit(MCC_TAG_STATE_RUNNING, &phba->ctrl.ptag_state[tag].tag_state); | |
487 | val |= mccq->id & DB_MCCQ_RING_ID_MASK; | |
488 | val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; | |
489 | /* make request available for DMA */ | |
490 | wmb(); | |
491 | iowrite32(val, phba->db_va + DB_MCCQ_OFFSET); | |
bfead3b2 JK |
492 | } |
493 | ||
e175defe | 494 | /* |
88840332 | 495 | * be_mbox_db_ready_poll()- Check ready status |
e175defe JSJ |
496 | * @ctrl: Function specific MBX data structure |
497 | * | |
498 | * Check for the ready status of FW to send BMBX | |
499 | * commands to adapter. | |
500 | * | |
501 | * return | |
502 | * Success: 0 | |
503 | * Failure: Non-Zero | |
504 | **/ | |
88840332 | 505 | static int be_mbox_db_ready_poll(struct be_ctrl_info *ctrl) |
6733b39a | 506 | { |
9ec6f6b8 JB |
507 | /* wait 30s for generic non-flash MBOX operation */ |
508 | #define BEISCSI_MBX_RDY_BIT_TIMEOUT 30000 | |
6733b39a | 509 | void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET; |
e175defe | 510 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
92665a66 | 511 | unsigned long timeout; |
6733b39a JK |
512 | u32 ready; |
513 | ||
6ac999ef JB |
514 | /* |
515 | * This BMBX busy wait path is used during init only. | |
516 | * For the commands executed during init, 5s should suffice. | |
517 | */ | |
518 | timeout = jiffies + msecs_to_jiffies(BEISCSI_MBX_RDY_BIT_TIMEOUT); | |
519 | do { | |
9122e991 | 520 | if (beiscsi_hba_in_error(phba)) |
6ac999ef | 521 | return -EIO; |
7a158003 | 522 | |
6ac999ef JB |
523 | ready = ioread32(db); |
524 | if (ready == 0xffffffff) | |
525 | return -EIO; | |
e175defe | 526 | |
6ac999ef JB |
527 | ready &= MPU_MAILBOX_DB_RDY_MASK; |
528 | if (ready) | |
529 | return 0; | |
6733b39a | 530 | |
6ac999ef JB |
531 | if (time_after(jiffies, timeout)) |
532 | break; | |
3c9e36a9 JB |
533 | /* 1ms sleep is enough in most cases */ |
534 | schedule_timeout_uninterruptible(msecs_to_jiffies(1)); | |
6ac999ef | 535 | } while (!ready); |
92665a66 | 536 | |
6ac999ef JB |
537 | beiscsi_log(phba, KERN_ERR, |
538 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, | |
539 | "BC_%d : FW Timed Out\n"); | |
9122e991 | 540 | set_bit(BEISCSI_HBA_FW_TIMEOUT, &phba->state); |
6ac999ef | 541 | beiscsi_ue_detect(phba); |
6ac999ef | 542 | return -EBUSY; |
6733b39a JK |
543 | } |
544 | ||
e175defe JSJ |
545 | /* |
546 | * be_mbox_notify: Notify adapter of new BMBX command | |
547 | * @ctrl: Function specific MBX data structure | |
548 | * | |
549 | * Ring doorbell to inform adapter of a BMBX command | |
550 | * to process | |
551 | * | |
552 | * return | |
553 | * Success: 0 | |
554 | * Failure: Non-Zero | |
555 | **/ | |
480195c2 | 556 | static int be_mbox_notify(struct be_ctrl_info *ctrl) |
6733b39a JK |
557 | { |
558 | int status; | |
559 | u32 val = 0; | |
560 | void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET; | |
561 | struct be_dma_mem *mbox_mem = &ctrl->mbox_mem; | |
562 | struct be_mcc_mailbox *mbox = mbox_mem->va; | |
6733b39a | 563 | |
88840332 | 564 | status = be_mbox_db_ready_poll(ctrl); |
1e234bbb JK |
565 | if (status) |
566 | return status; | |
567 | ||
6733b39a JK |
568 | val &= ~MPU_MAILBOX_DB_RDY_MASK; |
569 | val |= MPU_MAILBOX_DB_HI_MASK; | |
570 | val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; | |
571 | iowrite32(val, db); | |
572 | ||
88840332 | 573 | status = be_mbox_db_ready_poll(ctrl); |
e175defe | 574 | if (status) |
6733b39a | 575 | return status; |
e175defe | 576 | |
6733b39a JK |
577 | val = 0; |
578 | val &= ~MPU_MAILBOX_DB_RDY_MASK; | |
579 | val &= ~MPU_MAILBOX_DB_HI_MASK; | |
580 | val |= (u32) (mbox_mem->dma >> 4) << 2; | |
581 | iowrite32(val, db); | |
582 | ||
88840332 | 583 | status = be_mbox_db_ready_poll(ctrl); |
e175defe | 584 | if (status) |
6733b39a | 585 | return status; |
e175defe | 586 | |
6ac999ef JB |
587 | /* RDY is set; small delay before CQE read. */ |
588 | udelay(1); | |
589 | ||
a264f5e8 JB |
590 | status = beiscsi_process_mbox_compl(ctrl, &mbox->compl); |
591 | return status; | |
bfead3b2 JK |
592 | } |
593 | ||
6733b39a JK |
594 | void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, |
595 | bool embedded, u8 sge_cnt) | |
596 | { | |
597 | if (embedded) | |
598 | wrb->embedded |= MCC_WRB_EMBEDDED_MASK; | |
599 | else | |
600 | wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) << | |
601 | MCC_WRB_SGE_CNT_SHIFT; | |
602 | wrb->payload_length = payload_len; | |
603 | be_dws_cpu_to_le(wrb, 8); | |
604 | } | |
605 | ||
606 | void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, | |
607 | u8 subsystem, u8 opcode, int cmd_len) | |
608 | { | |
609 | req_hdr->opcode = opcode; | |
610 | req_hdr->subsystem = subsystem; | |
611 | req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); | |
e175defe | 612 | req_hdr->timeout = BEISCSI_FW_MBX_TIMEOUT; |
6733b39a JK |
613 | } |
614 | ||
615 | static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, | |
616 | struct be_dma_mem *mem) | |
617 | { | |
618 | int i, buf_pages; | |
619 | u64 dma = (u64) mem->dma; | |
620 | ||
621 | buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); | |
622 | for (i = 0; i < buf_pages; i++) { | |
623 | pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); | |
624 | pages[i].hi = cpu_to_le32(upper_32_bits(dma)); | |
625 | dma += PAGE_SIZE_4K; | |
626 | } | |
627 | } | |
628 | ||
629 | static u32 eq_delay_to_mult(u32 usec_delay) | |
630 | { | |
631 | #define MAX_INTR_RATE 651042 | |
632 | const u32 round = 10; | |
633 | u32 multiplier; | |
634 | ||
635 | if (usec_delay == 0) | |
636 | multiplier = 0; | |
637 | else { | |
638 | u32 interrupt_rate = 1000000 / usec_delay; | |
639 | if (interrupt_rate == 0) | |
640 | multiplier = 1023; | |
641 | else { | |
642 | multiplier = (MAX_INTR_RATE - interrupt_rate) * round; | |
643 | multiplier /= interrupt_rate; | |
644 | multiplier = (multiplier + round / 2) / round; | |
645 | multiplier = min(multiplier, (u32) 1023); | |
646 | } | |
647 | } | |
648 | return multiplier; | |
649 | } | |
650 | ||
651 | struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem) | |
652 | { | |
653 | return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; | |
654 | } | |
655 | ||
656 | int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl, | |
657 | struct be_queue_info *eq, int eq_delay) | |
658 | { | |
659 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
660 | struct be_cmd_req_eq_create *req = embedded_payload(wrb); | |
661 | struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); | |
662 | struct be_dma_mem *q_mem = &eq->dma_mem; | |
663 | int status; | |
664 | ||
c03a50f7 | 665 | mutex_lock(&ctrl->mbox_lock); |
6733b39a JK |
666 | memset(wrb, 0, sizeof(*wrb)); |
667 | ||
668 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
669 | ||
670 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
671 | OPCODE_COMMON_EQ_CREATE, sizeof(*req)); | |
672 | ||
673 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
674 | ||
675 | AMAP_SET_BITS(struct amap_eq_context, func, req->context, | |
676 | PCI_FUNC(ctrl->pdev->devfn)); | |
677 | AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); | |
678 | AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); | |
679 | AMAP_SET_BITS(struct amap_eq_context, count, req->context, | |
680 | __ilog2_u32(eq->len / 256)); | |
681 | AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context, | |
682 | eq_delay_to_mult(eq_delay)); | |
683 | be_dws_cpu_to_le(req->context, sizeof(req->context)); | |
684 | ||
685 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
686 | ||
687 | status = be_mbox_notify(ctrl); | |
688 | if (!status) { | |
689 | eq->id = le16_to_cpu(resp->eq_id); | |
690 | eq->created = true; | |
691 | } | |
c03a50f7 | 692 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a JK |
693 | return status; |
694 | } | |
695 | ||
6733b39a JK |
696 | int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl, |
697 | struct be_queue_info *cq, struct be_queue_info *eq, | |
698 | bool sol_evts, bool no_delay, int coalesce_wm) | |
699 | { | |
700 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
701 | struct be_cmd_req_cq_create *req = embedded_payload(wrb); | |
702 | struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); | |
99bc5d55 | 703 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
6733b39a JK |
704 | struct be_dma_mem *q_mem = &cq->dma_mem; |
705 | void *ctxt = &req->context; | |
706 | int status; | |
707 | ||
c03a50f7 | 708 | mutex_lock(&ctrl->mbox_lock); |
6733b39a JK |
709 | memset(wrb, 0, sizeof(*wrb)); |
710 | ||
711 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
712 | ||
713 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
714 | OPCODE_COMMON_CQ_CREATE, sizeof(*req)); | |
6733b39a JK |
715 | |
716 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
2c9dfd36 | 717 | if (is_chip_be2_be3r(phba)) { |
eaae5267 JSJ |
718 | AMAP_SET_BITS(struct amap_cq_context, coalescwm, |
719 | ctxt, coalesce_wm); | |
720 | AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay); | |
721 | AMAP_SET_BITS(struct amap_cq_context, count, ctxt, | |
722 | __ilog2_u32(cq->len / 256)); | |
723 | AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1); | |
724 | AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts); | |
725 | AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); | |
726 | AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); | |
727 | AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1); | |
728 | AMAP_SET_BITS(struct amap_cq_context, func, ctxt, | |
729 | PCI_FUNC(ctrl->pdev->devfn)); | |
2c9dfd36 JK |
730 | } else { |
731 | req->hdr.version = MBX_CMD_VER2; | |
732 | req->page_size = 1; | |
733 | AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm, | |
734 | ctxt, coalesce_wm); | |
735 | AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, | |
736 | ctxt, no_delay); | |
737 | AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt, | |
738 | __ilog2_u32(cq->len / 256)); | |
739 | AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1); | |
740 | AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1); | |
741 | AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id); | |
742 | AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1); | |
eaae5267 | 743 | } |
6733b39a | 744 | |
6733b39a JK |
745 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); |
746 | ||
747 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
748 | ||
749 | status = be_mbox_notify(ctrl); | |
750 | if (!status) { | |
751 | cq->id = le16_to_cpu(resp->cq_id); | |
752 | cq->created = true; | |
753 | } else | |
99bc5d55 JSJ |
754 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
755 | "BC_%d : In be_cmd_cq_create, status=ox%08x\n", | |
756 | status); | |
757 | ||
c03a50f7 | 758 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a JK |
759 | |
760 | return status; | |
761 | } | |
762 | ||
763 | static u32 be_encoded_q_len(int q_len) | |
764 | { | |
765 | u32 len_encoded = fls(q_len); /* log2(len) + 1 */ | |
766 | if (len_encoded == 16) | |
767 | len_encoded = 0; | |
768 | return len_encoded; | |
769 | } | |
bfead3b2 | 770 | |
35e66019 | 771 | int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba, |
bfead3b2 JK |
772 | struct be_queue_info *mccq, |
773 | struct be_queue_info *cq) | |
774 | { | |
775 | struct be_mcc_wrb *wrb; | |
53aefe25 | 776 | struct be_cmd_req_mcc_create_ext *req; |
bfead3b2 JK |
777 | struct be_dma_mem *q_mem = &mccq->dma_mem; |
778 | struct be_ctrl_info *ctrl; | |
779 | void *ctxt; | |
780 | int status; | |
781 | ||
c03a50f7 | 782 | mutex_lock(&phba->ctrl.mbox_lock); |
bfead3b2 JK |
783 | ctrl = &phba->ctrl; |
784 | wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
37609766 | 785 | memset(wrb, 0, sizeof(*wrb)); |
bfead3b2 JK |
786 | req = embedded_payload(wrb); |
787 | ctxt = &req->context; | |
788 | ||
789 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
790 | ||
791 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
53aefe25 | 792 | OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req)); |
bfead3b2 JK |
793 | |
794 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
53aefe25 JB |
795 | req->async_evt_bitmap = 1 << ASYNC_EVENT_CODE_LINK_STATE; |
796 | req->async_evt_bitmap |= 1 << ASYNC_EVENT_CODE_ISCSI; | |
797 | req->async_evt_bitmap |= 1 << ASYNC_EVENT_CODE_SLI; | |
bfead3b2 JK |
798 | |
799 | AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, | |
800 | PCI_FUNC(phba->pcidev->devfn)); | |
801 | AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1); | |
802 | AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt, | |
803 | be_encoded_q_len(mccq->len)); | |
804 | AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id); | |
805 | ||
806 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
807 | ||
808 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
809 | ||
a264f5e8 | 810 | status = be_mbox_notify(ctrl); |
bfead3b2 JK |
811 | if (!status) { |
812 | struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); | |
813 | mccq->id = le16_to_cpu(resp->id); | |
814 | mccq->created = true; | |
815 | } | |
c03a50f7 | 816 | mutex_unlock(&phba->ctrl.mbox_lock); |
bfead3b2 JK |
817 | |
818 | return status; | |
819 | } | |
820 | ||
6733b39a JK |
821 | int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, |
822 | int queue_type) | |
823 | { | |
824 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
825 | struct be_cmd_req_q_destroy *req = embedded_payload(wrb); | |
99bc5d55 | 826 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
6733b39a JK |
827 | u8 subsys = 0, opcode = 0; |
828 | int status; | |
829 | ||
99bc5d55 JSJ |
830 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
831 | "BC_%d : In beiscsi_cmd_q_destroy " | |
832 | "queue_type : %d\n", queue_type); | |
833 | ||
c03a50f7 | 834 | mutex_lock(&ctrl->mbox_lock); |
6733b39a JK |
835 | memset(wrb, 0, sizeof(*wrb)); |
836 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
837 | ||
838 | switch (queue_type) { | |
839 | case QTYPE_EQ: | |
840 | subsys = CMD_SUBSYSTEM_COMMON; | |
841 | opcode = OPCODE_COMMON_EQ_DESTROY; | |
842 | break; | |
843 | case QTYPE_CQ: | |
844 | subsys = CMD_SUBSYSTEM_COMMON; | |
845 | opcode = OPCODE_COMMON_CQ_DESTROY; | |
846 | break; | |
bfead3b2 JK |
847 | case QTYPE_MCCQ: |
848 | subsys = CMD_SUBSYSTEM_COMMON; | |
849 | opcode = OPCODE_COMMON_MCC_DESTROY; | |
850 | break; | |
6733b39a JK |
851 | case QTYPE_WRBQ: |
852 | subsys = CMD_SUBSYSTEM_ISCSI; | |
853 | opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY; | |
854 | break; | |
855 | case QTYPE_DPDUQ: | |
856 | subsys = CMD_SUBSYSTEM_ISCSI; | |
857 | opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY; | |
858 | break; | |
859 | case QTYPE_SGL: | |
860 | subsys = CMD_SUBSYSTEM_ISCSI; | |
861 | opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES; | |
862 | break; | |
863 | default: | |
c03a50f7 | 864 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a | 865 | BUG(); |
d3ad2bb3 | 866 | return -ENXIO; |
6733b39a JK |
867 | } |
868 | be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); | |
869 | if (queue_type != QTYPE_SGL) | |
870 | req->id = cpu_to_le16(q->id); | |
871 | ||
872 | status = be_mbox_notify(ctrl); | |
873 | ||
c03a50f7 | 874 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a JK |
875 | return status; |
876 | } | |
877 | ||
8a86e833 JK |
878 | /** |
879 | * be_cmd_create_default_pdu_queue()- Create DEFQ for the adapter | |
880 | * @ctrl: ptr to ctrl_info | |
881 | * @cq: Completion Queue | |
882 | * @dq: Default Queue | |
883 | * @lenght: ring size | |
884 | * @entry_size: size of each entry in DEFQ | |
885 | * @is_header: Header or Data DEFQ | |
886 | * @ulp_num: Bind to which ULP | |
887 | * | |
888 | * Create HDR/Data DEFQ for the passed ULP. Unsol PDU are posted | |
889 | * on this queue by the FW | |
890 | * | |
891 | * return | |
892 | * Success: 0 | |
893 | * Failure: Non-Zero Value | |
894 | * | |
895 | **/ | |
6733b39a JK |
896 | int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl, |
897 | struct be_queue_info *cq, | |
898 | struct be_queue_info *dq, int length, | |
8a86e833 JK |
899 | int entry_size, uint8_t is_header, |
900 | uint8_t ulp_num) | |
6733b39a JK |
901 | { |
902 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
903 | struct be_defq_create_req *req = embedded_payload(wrb); | |
904 | struct be_dma_mem *q_mem = &dq->dma_mem; | |
ef9e1b9b | 905 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
6733b39a JK |
906 | void *ctxt = &req->context; |
907 | int status; | |
908 | ||
c03a50f7 | 909 | mutex_lock(&ctrl->mbox_lock); |
6733b39a JK |
910 | memset(wrb, 0, sizeof(*wrb)); |
911 | ||
912 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
913 | ||
914 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, | |
915 | OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req)); | |
916 | ||
917 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
8a86e833 JK |
918 | if (phba->fw_config.dual_ulp_aware) { |
919 | req->ulp_num = ulp_num; | |
920 | req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT); | |
921 | req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT); | |
922 | } | |
ef9e1b9b JK |
923 | |
924 | if (is_chip_be2_be3r(phba)) { | |
925 | AMAP_SET_BITS(struct amap_be_default_pdu_context, | |
926 | rx_pdid, ctxt, 0); | |
927 | AMAP_SET_BITS(struct amap_be_default_pdu_context, | |
928 | rx_pdid_valid, ctxt, 1); | |
929 | AMAP_SET_BITS(struct amap_be_default_pdu_context, | |
930 | pci_func_id, ctxt, PCI_FUNC(ctrl->pdev->devfn)); | |
931 | AMAP_SET_BITS(struct amap_be_default_pdu_context, | |
932 | ring_size, ctxt, | |
933 | be_encoded_q_len(length / | |
934 | sizeof(struct phys_addr))); | |
935 | AMAP_SET_BITS(struct amap_be_default_pdu_context, | |
936 | default_buffer_size, ctxt, entry_size); | |
937 | AMAP_SET_BITS(struct amap_be_default_pdu_context, | |
938 | cq_id_recv, ctxt, cq->id); | |
939 | } else { | |
940 | AMAP_SET_BITS(struct amap_default_pdu_context_ext, | |
941 | rx_pdid, ctxt, 0); | |
942 | AMAP_SET_BITS(struct amap_default_pdu_context_ext, | |
943 | rx_pdid_valid, ctxt, 1); | |
944 | AMAP_SET_BITS(struct amap_default_pdu_context_ext, | |
945 | ring_size, ctxt, | |
946 | be_encoded_q_len(length / | |
947 | sizeof(struct phys_addr))); | |
948 | AMAP_SET_BITS(struct amap_default_pdu_context_ext, | |
949 | default_buffer_size, ctxt, entry_size); | |
950 | AMAP_SET_BITS(struct amap_default_pdu_context_ext, | |
951 | cq_id_recv, ctxt, cq->id); | |
952 | } | |
6733b39a JK |
953 | |
954 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
955 | ||
956 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
957 | ||
958 | status = be_mbox_notify(ctrl); | |
959 | if (!status) { | |
8a86e833 | 960 | struct be_ring *defq_ring; |
6733b39a JK |
961 | struct be_defq_create_resp *resp = embedded_payload(wrb); |
962 | ||
963 | dq->id = le16_to_cpu(resp->id); | |
964 | dq->created = true; | |
8a86e833 JK |
965 | if (is_header) |
966 | defq_ring = &phba->phwi_ctrlr->default_pdu_hdr[ulp_num]; | |
967 | else | |
968 | defq_ring = &phba->phwi_ctrlr-> | |
969 | default_pdu_data[ulp_num]; | |
970 | ||
971 | defq_ring->id = dq->id; | |
972 | ||
973 | if (!phba->fw_config.dual_ulp_aware) { | |
974 | defq_ring->ulp_num = BEISCSI_ULP0; | |
975 | defq_ring->doorbell_offset = DB_RXULP0_OFFSET; | |
976 | } else { | |
977 | defq_ring->ulp_num = resp->ulp_num; | |
978 | defq_ring->doorbell_offset = resp->doorbell_offset; | |
979 | } | |
6733b39a | 980 | } |
c03a50f7 | 981 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a JK |
982 | |
983 | return status; | |
984 | } | |
985 | ||
4eea99d5 JK |
986 | /** |
987 | * be_cmd_wrbq_create()- Create WRBQ | |
988 | * @ctrl: ptr to ctrl_info | |
989 | * @q_mem: memory details for the queue | |
990 | * @wrbq: queue info | |
991 | * @pwrb_context: ptr to wrb_context | |
992 | * @ulp_num: ULP on which the WRBQ is to be created | |
993 | * | |
994 | * Create WRBQ on the passed ULP_NUM. | |
995 | * | |
996 | **/ | |
997 | int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, | |
998 | struct be_dma_mem *q_mem, | |
999 | struct be_queue_info *wrbq, | |
1000 | struct hwi_wrb_context *pwrb_context, | |
1001 | uint8_t ulp_num) | |
6733b39a JK |
1002 | { |
1003 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1004 | struct be_wrbq_create_req *req = embedded_payload(wrb); | |
1005 | struct be_wrbq_create_resp *resp = embedded_payload(wrb); | |
4eea99d5 | 1006 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
6733b39a JK |
1007 | int status; |
1008 | ||
c03a50f7 | 1009 | mutex_lock(&ctrl->mbox_lock); |
6733b39a JK |
1010 | memset(wrb, 0, sizeof(*wrb)); |
1011 | ||
1012 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1013 | ||
1014 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, | |
1015 | OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req)); | |
1016 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
4eea99d5 JK |
1017 | |
1018 | if (phba->fw_config.dual_ulp_aware) { | |
1019 | req->ulp_num = ulp_num; | |
1020 | req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT); | |
1021 | req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT); | |
1022 | } | |
1023 | ||
6733b39a JK |
1024 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); |
1025 | ||
1026 | status = be_mbox_notify(ctrl); | |
bfead3b2 | 1027 | if (!status) { |
6733b39a | 1028 | wrbq->id = le16_to_cpu(resp->cid); |
bfead3b2 | 1029 | wrbq->created = true; |
4eea99d5 JK |
1030 | |
1031 | pwrb_context->cid = wrbq->id; | |
1032 | if (!phba->fw_config.dual_ulp_aware) { | |
1033 | pwrb_context->doorbell_offset = DB_TXULP0_OFFSET; | |
1034 | pwrb_context->ulp_num = BEISCSI_ULP0; | |
1035 | } else { | |
1036 | pwrb_context->ulp_num = resp->ulp_num; | |
1037 | pwrb_context->doorbell_offset = resp->doorbell_offset; | |
1038 | } | |
bfead3b2 | 1039 | } |
c03a50f7 | 1040 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a JK |
1041 | return status; |
1042 | } | |
1043 | ||
15a90fe0 JK |
1044 | int be_cmd_iscsi_post_template_hdr(struct be_ctrl_info *ctrl, |
1045 | struct be_dma_mem *q_mem) | |
1046 | { | |
1047 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1048 | struct be_post_template_pages_req *req = embedded_payload(wrb); | |
1049 | int status; | |
1050 | ||
c03a50f7 | 1051 | mutex_lock(&ctrl->mbox_lock); |
15a90fe0 JK |
1052 | |
1053 | memset(wrb, 0, sizeof(*wrb)); | |
1054 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1055 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1056 | OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS, | |
1057 | sizeof(*req)); | |
1058 | ||
1059 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
1060 | req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI; | |
1061 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
1062 | ||
1063 | status = be_mbox_notify(ctrl); | |
c03a50f7 | 1064 | mutex_unlock(&ctrl->mbox_lock); |
15a90fe0 JK |
1065 | return status; |
1066 | } | |
1067 | ||
1068 | int be_cmd_iscsi_remove_template_hdr(struct be_ctrl_info *ctrl) | |
1069 | { | |
1070 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1071 | struct be_remove_template_pages_req *req = embedded_payload(wrb); | |
1072 | int status; | |
1073 | ||
c03a50f7 | 1074 | mutex_lock(&ctrl->mbox_lock); |
15a90fe0 JK |
1075 | |
1076 | memset(wrb, 0, sizeof(*wrb)); | |
1077 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1078 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1079 | OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS, | |
1080 | sizeof(*req)); | |
1081 | ||
1082 | req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI; | |
1083 | ||
1084 | status = be_mbox_notify(ctrl); | |
c03a50f7 | 1085 | mutex_unlock(&ctrl->mbox_lock); |
15a90fe0 JK |
1086 | return status; |
1087 | } | |
1088 | ||
6733b39a JK |
1089 | int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl, |
1090 | struct be_dma_mem *q_mem, | |
1091 | u32 page_offset, u32 num_pages) | |
1092 | { | |
1093 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1094 | struct be_post_sgl_pages_req *req = embedded_payload(wrb); | |
99bc5d55 | 1095 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); |
6733b39a JK |
1096 | int status; |
1097 | unsigned int curr_pages; | |
1098 | u32 internal_page_offset = 0; | |
1099 | u32 temp_num_pages = num_pages; | |
1100 | ||
1101 | if (num_pages == 0xff) | |
1102 | num_pages = 1; | |
1103 | ||
c03a50f7 | 1104 | mutex_lock(&ctrl->mbox_lock); |
6733b39a JK |
1105 | do { |
1106 | memset(wrb, 0, sizeof(*wrb)); | |
1107 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1108 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, | |
1109 | OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES, | |
1110 | sizeof(*req)); | |
1111 | curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req, | |
1112 | pages); | |
1113 | req->num_pages = min(num_pages, curr_pages); | |
1114 | req->page_offset = page_offset; | |
1115 | be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem); | |
1116 | q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE); | |
1117 | internal_page_offset += req->num_pages; | |
1118 | page_offset += req->num_pages; | |
1119 | num_pages -= req->num_pages; | |
1120 | ||
1121 | if (temp_num_pages == 0xff) | |
1122 | req->num_pages = temp_num_pages; | |
1123 | ||
1124 | status = be_mbox_notify(ctrl); | |
1125 | if (status) { | |
99bc5d55 JSJ |
1126 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
1127 | "BC_%d : FW CMD to map iscsi frags failed.\n"); | |
1128 | ||
6733b39a JK |
1129 | goto error; |
1130 | } | |
1131 | } while (num_pages > 0); | |
1132 | error: | |
c03a50f7 | 1133 | mutex_unlock(&ctrl->mbox_lock); |
6733b39a JK |
1134 | if (status != 0) |
1135 | beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL); | |
1136 | return status; | |
1137 | } | |
e5285860 | 1138 | |
6f72238e JSJ |
1139 | /** |
1140 | * be_cmd_set_vlan()- Configure VLAN paramters on the adapter | |
1141 | * @phba: device priv structure instance | |
1142 | * @vlan_tag: TAG to be set | |
1143 | * | |
1144 | * Set the VLAN_TAG for the adapter or Disable VLAN on adapter | |
1145 | * | |
1146 | * returns | |
1147 | * TAG for the MBX Cmd | |
1148 | * **/ | |
1149 | int be_cmd_set_vlan(struct beiscsi_hba *phba, | |
1150 | uint16_t vlan_tag) | |
1151 | { | |
090e2184 | 1152 | unsigned int tag; |
6f72238e JSJ |
1153 | struct be_mcc_wrb *wrb; |
1154 | struct be_cmd_set_vlan_req *req; | |
1155 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
1156 | ||
c03a50f7 JB |
1157 | if (mutex_lock_interruptible(&ctrl->mbox_lock)) |
1158 | return 0; | |
090e2184 JB |
1159 | wrb = alloc_mcc_wrb(phba, &tag); |
1160 | if (!wrb) { | |
c03a50f7 | 1161 | mutex_unlock(&ctrl->mbox_lock); |
090e2184 | 1162 | return 0; |
6f72238e JSJ |
1163 | } |
1164 | ||
6f72238e | 1165 | req = embedded_payload(wrb); |
6f72238e JSJ |
1166 | be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0); |
1167 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, | |
1168 | OPCODE_COMMON_ISCSI_NTWK_SET_VLAN, | |
1169 | sizeof(*req)); | |
1170 | ||
1171 | req->interface_hndl = phba->interface_handle; | |
1172 | req->vlan_priority = vlan_tag; | |
1173 | ||
cdde6682 | 1174 | be_mcc_notify(phba, tag); |
c03a50f7 | 1175 | mutex_unlock(&ctrl->mbox_lock); |
6f72238e JSJ |
1176 | |
1177 | return tag; | |
1178 | } | |
6694095b | 1179 | |
480195c2 JB |
1180 | int beiscsi_check_supported_fw(struct be_ctrl_info *ctrl, |
1181 | struct beiscsi_hba *phba) | |
1182 | { | |
1183 | struct be_dma_mem nonemb_cmd; | |
1184 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1185 | struct be_mgmt_controller_attributes *req; | |
1186 | struct be_sge *sge = nonembedded_sgl(wrb); | |
1187 | int status = 0; | |
1188 | ||
1189 | nonemb_cmd.va = pci_alloc_consistent(ctrl->pdev, | |
1190 | sizeof(struct be_mgmt_controller_attributes), | |
1191 | &nonemb_cmd.dma); | |
1192 | if (nonemb_cmd.va == NULL) { | |
1193 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
1194 | "BG_%d : pci_alloc_consistent failed in %s\n", | |
1195 | __func__); | |
1196 | return -ENOMEM; | |
1197 | } | |
1198 | nonemb_cmd.size = sizeof(struct be_mgmt_controller_attributes); | |
1199 | req = nonemb_cmd.va; | |
1200 | memset(req, 0, sizeof(*req)); | |
1201 | mutex_lock(&ctrl->mbox_lock); | |
1202 | memset(wrb, 0, sizeof(*wrb)); | |
1203 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1); | |
1204 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1205 | OPCODE_COMMON_GET_CNTL_ATTRIBUTES, sizeof(*req)); | |
1206 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd.dma)); | |
1207 | sge->pa_lo = cpu_to_le32(nonemb_cmd.dma & 0xFFFFFFFF); | |
1208 | sge->len = cpu_to_le32(nonemb_cmd.size); | |
1209 | status = be_mbox_notify(ctrl); | |
1210 | if (!status) { | |
1211 | struct be_mgmt_controller_attributes_resp *resp = nonemb_cmd.va; | |
1212 | ||
1213 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
1214 | "BG_%d : Firmware Version of CMD : %s\n" | |
1215 | "Firmware Version is : %s\n" | |
1216 | "Developer Build, not performing version check...\n", | |
1217 | resp->params.hba_attribs | |
1218 | .flashrom_version_string, | |
1219 | resp->params.hba_attribs. | |
1220 | firmware_version_string); | |
1221 | ||
1222 | phba->fw_config.iscsi_features = | |
1223 | resp->params.hba_attribs.iscsi_features; | |
1224 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
1225 | "BM_%d : phba->fw_config.iscsi_features = %d\n", | |
1226 | phba->fw_config.iscsi_features); | |
1227 | memcpy(phba->fw_ver_str, resp->params.hba_attribs. | |
1228 | firmware_version_string, BEISCSI_VER_STRLEN); | |
1229 | } else | |
1230 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
1231 | "BG_%d : Failed in beiscsi_check_supported_fw\n"); | |
1232 | mutex_unlock(&ctrl->mbox_lock); | |
1233 | if (nonemb_cmd.va) | |
1234 | pci_free_consistent(ctrl->pdev, nonemb_cmd.size, | |
1235 | nonemb_cmd.va, nonemb_cmd.dma); | |
1236 | ||
1237 | return status; | |
1238 | } | |
1239 | ||
1240 | /** | |
1241 | * beiscsi_get_fw_config()- Get the FW config for the function | |
1242 | * @ctrl: ptr to Ctrl Info | |
1243 | * @phba: ptr to the dev priv structure | |
1244 | * | |
1245 | * Get the FW config and resources available for the function. | |
1246 | * The resources are created based on the count received here. | |
1247 | * | |
1248 | * return | |
1249 | * Success: 0 | |
1250 | * Failure: Non-Zero Value | |
1251 | **/ | |
1252 | int beiscsi_get_fw_config(struct be_ctrl_info *ctrl, | |
1253 | struct beiscsi_hba *phba) | |
1254 | { | |
1255 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1256 | struct be_fw_cfg *pfw_cfg = embedded_payload(wrb); | |
1257 | uint32_t cid_count, icd_count; | |
1258 | int status = -EINVAL; | |
1259 | uint8_t ulp_num = 0; | |
1260 | ||
1261 | mutex_lock(&ctrl->mbox_lock); | |
1262 | memset(wrb, 0, sizeof(*wrb)); | |
1263 | be_wrb_hdr_prepare(wrb, sizeof(*pfw_cfg), true, 0); | |
1264 | ||
1265 | be_cmd_hdr_prepare(&pfw_cfg->hdr, CMD_SUBSYSTEM_COMMON, | |
1266 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, | |
1267 | EMBED_MBX_MAX_PAYLOAD_SIZE); | |
1268 | ||
1269 | if (be_mbox_notify(ctrl)) { | |
1270 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
1271 | "BG_%d : Failed in beiscsi_get_fw_config\n"); | |
1272 | goto fail_init; | |
1273 | } | |
1274 | ||
1275 | /* FW response formats depend on port id */ | |
1276 | phba->fw_config.phys_port = pfw_cfg->phys_port; | |
1277 | if (phba->fw_config.phys_port >= BEISCSI_PHYS_PORT_MAX) { | |
1278 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
1279 | "BG_%d : invalid physical port id %d\n", | |
1280 | phba->fw_config.phys_port); | |
1281 | goto fail_init; | |
1282 | } | |
1283 | ||
1284 | /* populate and check FW config against min and max values */ | |
1285 | if (!is_chip_be2_be3r(phba)) { | |
1286 | phba->fw_config.eqid_count = pfw_cfg->eqid_count; | |
1287 | phba->fw_config.cqid_count = pfw_cfg->cqid_count; | |
1288 | if (phba->fw_config.eqid_count == 0 || | |
1289 | phba->fw_config.eqid_count > 2048) { | |
1290 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
1291 | "BG_%d : invalid EQ count %d\n", | |
1292 | phba->fw_config.eqid_count); | |
1293 | goto fail_init; | |
1294 | } | |
1295 | if (phba->fw_config.cqid_count == 0 || | |
1296 | phba->fw_config.cqid_count > 4096) { | |
1297 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
1298 | "BG_%d : invalid CQ count %d\n", | |
1299 | phba->fw_config.cqid_count); | |
1300 | goto fail_init; | |
1301 | } | |
1302 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
1303 | "BG_%d : EQ_Count : %d CQ_Count : %d\n", | |
1304 | phba->fw_config.eqid_count, | |
1305 | phba->fw_config.cqid_count); | |
1306 | } | |
1307 | ||
1308 | /** | |
1309 | * Check on which all ULP iSCSI Protocol is loaded. | |
1310 | * Set the Bit for those ULP. This set flag is used | |
1311 | * at all places in the code to check on which ULP | |
1312 | * iSCSi Protocol is loaded | |
1313 | **/ | |
1314 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { | |
1315 | if (pfw_cfg->ulp[ulp_num].ulp_mode & | |
1316 | BEISCSI_ULP_ISCSI_INI_MODE) { | |
1317 | set_bit(ulp_num, &phba->fw_config.ulp_supported); | |
1318 | ||
1319 | /* Get the CID, ICD and Chain count for each ULP */ | |
1320 | phba->fw_config.iscsi_cid_start[ulp_num] = | |
1321 | pfw_cfg->ulp[ulp_num].sq_base; | |
1322 | phba->fw_config.iscsi_cid_count[ulp_num] = | |
1323 | pfw_cfg->ulp[ulp_num].sq_count; | |
1324 | ||
1325 | phba->fw_config.iscsi_icd_start[ulp_num] = | |
1326 | pfw_cfg->ulp[ulp_num].icd_base; | |
1327 | phba->fw_config.iscsi_icd_count[ulp_num] = | |
1328 | pfw_cfg->ulp[ulp_num].icd_count; | |
1329 | ||
1330 | phba->fw_config.iscsi_chain_start[ulp_num] = | |
1331 | pfw_cfg->chain_icd[ulp_num].chain_base; | |
1332 | phba->fw_config.iscsi_chain_count[ulp_num] = | |
1333 | pfw_cfg->chain_icd[ulp_num].chain_count; | |
1334 | ||
1335 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
1336 | "BG_%d : Function loaded on ULP : %d\n" | |
1337 | "\tiscsi_cid_count : %d\n" | |
1338 | "\tiscsi_cid_start : %d\n" | |
1339 | "\t iscsi_icd_count : %d\n" | |
1340 | "\t iscsi_icd_start : %d\n", | |
1341 | ulp_num, | |
1342 | phba->fw_config. | |
1343 | iscsi_cid_count[ulp_num], | |
1344 | phba->fw_config. | |
1345 | iscsi_cid_start[ulp_num], | |
1346 | phba->fw_config. | |
1347 | iscsi_icd_count[ulp_num], | |
1348 | phba->fw_config. | |
1349 | iscsi_icd_start[ulp_num]); | |
1350 | } | |
1351 | } | |
1352 | ||
1353 | if (phba->fw_config.ulp_supported == 0) { | |
1354 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
1355 | "BG_%d : iSCSI initiator mode not set: ULP0 %x ULP1 %x\n", | |
1356 | pfw_cfg->ulp[BEISCSI_ULP0].ulp_mode, | |
1357 | pfw_cfg->ulp[BEISCSI_ULP1].ulp_mode); | |
1358 | goto fail_init; | |
1359 | } | |
1360 | ||
1361 | /** | |
1362 | * ICD is shared among ULPs. Use icd_count of any one loaded ULP | |
1363 | **/ | |
1364 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) | |
1365 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) | |
1366 | break; | |
1367 | icd_count = phba->fw_config.iscsi_icd_count[ulp_num]; | |
1368 | if (icd_count == 0 || icd_count > 65536) { | |
1369 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
1370 | "BG_%d: invalid ICD count %d\n", icd_count); | |
1371 | goto fail_init; | |
1372 | } | |
1373 | ||
1374 | cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) + | |
1375 | BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1); | |
1376 | if (cid_count == 0 || cid_count > 4096) { | |
1377 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
1378 | "BG_%d: invalid CID count %d\n", cid_count); | |
1379 | goto fail_init; | |
1380 | } | |
1381 | ||
1382 | /** | |
1383 | * Check FW is dual ULP aware i.e. can handle either | |
1384 | * of the protocols. | |
1385 | */ | |
1386 | phba->fw_config.dual_ulp_aware = (pfw_cfg->function_mode & | |
1387 | BEISCSI_FUNC_DUA_MODE); | |
1388 | ||
1389 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
1390 | "BG_%d : DUA Mode : 0x%x\n", | |
1391 | phba->fw_config.dual_ulp_aware); | |
1392 | ||
1393 | /* all set, continue using this FW config */ | |
1394 | status = 0; | |
1395 | fail_init: | |
1396 | mutex_unlock(&ctrl->mbox_lock); | |
1397 | return status; | |
1398 | } | |
1399 | ||
1400 | /** | |
1401 | * beiscsi_get_port_name()- Get port name for the function | |
1402 | * @ctrl: ptr to Ctrl Info | |
1403 | * @phba: ptr to the dev priv structure | |
1404 | * | |
1405 | * Get the alphanumeric character for port | |
1406 | * | |
1407 | **/ | |
1408 | int beiscsi_get_port_name(struct be_ctrl_info *ctrl, struct beiscsi_hba *phba) | |
1409 | { | |
1410 | int ret = 0; | |
1411 | struct be_mcc_wrb *wrb; | |
1412 | struct be_cmd_get_port_name *ioctl; | |
1413 | ||
1414 | mutex_lock(&ctrl->mbox_lock); | |
1415 | wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1416 | memset(wrb, 0, sizeof(*wrb)); | |
1417 | ioctl = embedded_payload(wrb); | |
1418 | ||
1419 | be_wrb_hdr_prepare(wrb, sizeof(*ioctl), true, 0); | |
1420 | be_cmd_hdr_prepare(&ioctl->h.req_hdr, CMD_SUBSYSTEM_COMMON, | |
1421 | OPCODE_COMMON_GET_PORT_NAME, | |
1422 | EMBED_MBX_MAX_PAYLOAD_SIZE); | |
1423 | ret = be_mbox_notify(ctrl); | |
1424 | phba->port_name = 0; | |
1425 | if (!ret) { | |
1426 | phba->port_name = ioctl->p.resp.port_names >> | |
1427 | (phba->fw_config.phys_port * 8) & 0xff; | |
1428 | } else { | |
1429 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
1430 | "BG_%d : GET_PORT_NAME ret 0x%x status 0x%x\n", | |
1431 | ret, ioctl->h.resp_hdr.status); | |
1432 | } | |
1433 | ||
1434 | if (phba->port_name == 0) | |
1435 | phba->port_name = '?'; | |
1436 | ||
1437 | mutex_unlock(&ctrl->mbox_lock); | |
1438 | return ret; | |
1439 | } | |
1440 | ||
6694095b JB |
1441 | int beiscsi_set_uer_feature(struct beiscsi_hba *phba) |
1442 | { | |
1443 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
1444 | struct be_cmd_set_features *ioctl; | |
1445 | struct be_mcc_wrb *wrb; | |
1446 | int ret = 0; | |
1447 | ||
1448 | mutex_lock(&ctrl->mbox_lock); | |
1449 | wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1450 | memset(wrb, 0, sizeof(*wrb)); | |
1451 | ioctl = embedded_payload(wrb); | |
1452 | ||
1453 | be_wrb_hdr_prepare(wrb, sizeof(*ioctl), true, 0); | |
1454 | be_cmd_hdr_prepare(&ioctl->h.req_hdr, CMD_SUBSYSTEM_COMMON, | |
1455 | OPCODE_COMMON_SET_FEATURES, | |
1456 | EMBED_MBX_MAX_PAYLOAD_SIZE); | |
1457 | ioctl->feature = BE_CMD_SET_FEATURE_UER; | |
1458 | ioctl->param_len = sizeof(ioctl->param.req); | |
1459 | ioctl->param.req.uer = BE_CMD_UER_SUPP_BIT; | |
1460 | ret = be_mbox_notify(ctrl); | |
1461 | if (!ret) { | |
1462 | phba->ue2rp = ioctl->param.resp.ue2rp; | |
1463 | set_bit(BEISCSI_HBA_UER_SUPP, &phba->state); | |
1464 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
1465 | "BG_%d : HBA error recovery supported\n"); | |
1466 | } else { | |
1467 | /** | |
1468 | * Check "MCC_STATUS_INVALID_LENGTH" for SKH. | |
1469 | * Older FW versions return this error. | |
1470 | */ | |
1471 | if (ret == MCC_STATUS_ILLEGAL_REQUEST || | |
1472 | ret == MCC_STATUS_INVALID_LENGTH) | |
1473 | __beiscsi_log(phba, KERN_INFO, | |
1474 | "BG_%d : HBA error recovery not supported\n"); | |
1475 | } | |
1476 | ||
1477 | mutex_unlock(&ctrl->mbox_lock); | |
1478 | return ret; | |
1479 | } | |
4d2ee1e6 JB |
1480 | |
1481 | static u32 beiscsi_get_post_stage(struct beiscsi_hba *phba) | |
1482 | { | |
1483 | u32 sem; | |
1484 | ||
1485 | if (is_chip_be2_be3r(phba)) | |
1486 | sem = ioread32(phba->csr_va + SLIPORT_SEMAPHORE_OFFSET_BEx); | |
1487 | else | |
1488 | pci_read_config_dword(phba->pcidev, | |
1489 | SLIPORT_SEMAPHORE_OFFSET_SH, &sem); | |
1490 | return sem; | |
1491 | } | |
1492 | ||
1493 | int beiscsi_check_fw_rdy(struct beiscsi_hba *phba) | |
1494 | { | |
1495 | u32 loop, post, rdy = 0; | |
1496 | ||
1497 | loop = 1000; | |
1498 | while (loop--) { | |
1499 | post = beiscsi_get_post_stage(phba); | |
1500 | if (post & POST_ERROR_BIT) | |
1501 | break; | |
1502 | if ((post & POST_STAGE_MASK) == POST_STAGE_ARMFW_RDY) { | |
1503 | rdy = 1; | |
1504 | break; | |
1505 | } | |
1506 | msleep(60); | |
1507 | } | |
1508 | ||
1509 | if (!rdy) { | |
1510 | __beiscsi_log(phba, KERN_ERR, | |
1511 | "BC_%d : FW not ready 0x%x\n", post); | |
1512 | } | |
1513 | ||
1514 | return rdy; | |
1515 | } | |
1516 | ||
1517 | static int beiscsi_cmd_function_reset(struct beiscsi_hba *phba) | |
1518 | { | |
1519 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
1520 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1521 | struct be_post_sgl_pages_req *req = embedded_payload(wrb); | |
1522 | int status; | |
1523 | ||
1524 | mutex_lock(&ctrl->mbox_lock); | |
1525 | ||
1526 | req = embedded_payload(wrb); | |
1527 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1528 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1529 | OPCODE_COMMON_FUNCTION_RESET, sizeof(*req)); | |
1530 | status = be_mbox_notify(ctrl); | |
1531 | ||
1532 | mutex_unlock(&ctrl->mbox_lock); | |
1533 | return status; | |
1534 | } | |
1535 | ||
1536 | int beiscsi_cmd_special_wrb(struct be_ctrl_info *ctrl, u32 load) | |
1537 | { | |
1538 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1539 | struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); | |
1540 | u8 *endian_check; | |
1541 | int status; | |
1542 | ||
1543 | mutex_lock(&ctrl->mbox_lock); | |
1544 | memset(wrb, 0, sizeof(*wrb)); | |
1545 | ||
1546 | endian_check = (u8 *) wrb; | |
1547 | if (load) { | |
1548 | /* to start communicating */ | |
1549 | *endian_check++ = 0xFF; | |
1550 | *endian_check++ = 0x12; | |
1551 | *endian_check++ = 0x34; | |
1552 | *endian_check++ = 0xFF; | |
1553 | *endian_check++ = 0xFF; | |
1554 | *endian_check++ = 0x56; | |
1555 | *endian_check++ = 0x78; | |
1556 | *endian_check++ = 0xFF; | |
1557 | } else { | |
1558 | /* to stop communicating */ | |
1559 | *endian_check++ = 0xFF; | |
1560 | *endian_check++ = 0xAA; | |
1561 | *endian_check++ = 0xBB; | |
1562 | *endian_check++ = 0xFF; | |
1563 | *endian_check++ = 0xFF; | |
1564 | *endian_check++ = 0xCC; | |
1565 | *endian_check++ = 0xDD; | |
1566 | *endian_check = 0xFF; | |
1567 | } | |
1568 | be_dws_cpu_to_le(wrb, sizeof(*wrb)); | |
1569 | ||
1570 | status = be_mbox_notify(ctrl); | |
1571 | if (status) | |
1572 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
1573 | "BC_%d : special WRB message failed\n"); | |
1574 | mutex_unlock(&ctrl->mbox_lock); | |
1575 | return status; | |
1576 | } | |
1577 | ||
1578 | int beiscsi_init_sliport(struct beiscsi_hba *phba) | |
1579 | { | |
1580 | int status; | |
1581 | ||
1582 | /* check POST stage before talking to FW */ | |
1583 | status = beiscsi_check_fw_rdy(phba); | |
1584 | if (!status) | |
1585 | return -EIO; | |
1586 | ||
1587 | /* | |
1588 | * SLI COMMON_FUNCTION_RESET completion is indicated by BMBX RDY bit. | |
1589 | * It should clean up any stale info in FW for this fn. | |
1590 | */ | |
1591 | status = beiscsi_cmd_function_reset(phba); | |
1592 | if (status) { | |
1593 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
1594 | "BC_%d : SLI Function Reset failed\n"); | |
1595 | return status; | |
1596 | } | |
1597 | ||
1598 | /* indicate driver is loading */ | |
1599 | return beiscsi_cmd_special_wrb(&phba->ctrl, 1); | |
1600 | } | |
f79929de JB |
1601 | |
1602 | /** | |
1603 | * beiscsi_cmd_iscsi_cleanup()- Inform FW to cleanup EP data structures. | |
1604 | * @phba: pointer to dev priv structure | |
1605 | * @ulp: ULP number. | |
1606 | * | |
1607 | * return | |
1608 | * Success: 0 | |
1609 | * Failure: Non-Zero Value | |
1610 | **/ | |
1611 | int beiscsi_cmd_iscsi_cleanup(struct beiscsi_hba *phba, unsigned short ulp) | |
1612 | { | |
1613 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
1614 | struct iscsi_cleanup_req_v1 *req_v1; | |
1615 | struct iscsi_cleanup_req *req; | |
1616 | struct be_mcc_wrb *wrb; | |
1617 | int status; | |
1618 | ||
1619 | mutex_lock(&ctrl->mbox_lock); | |
1620 | wrb = wrb_from_mbox(&ctrl->mbox_mem); | |
1621 | req = embedded_payload(wrb); | |
1622 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1623 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, | |
1624 | OPCODE_COMMON_ISCSI_CLEANUP, sizeof(*req)); | |
1625 | ||
1626 | /** | |
1627 | * TODO: Check with FW folks the chute value to be set. | |
1628 | * For now, use the ULP_MASK as the chute value. | |
1629 | */ | |
1630 | if (is_chip_be2_be3r(phba)) { | |
1631 | req->chute = (1 << ulp); | |
1632 | req->hdr_ring_id = HWI_GET_DEF_HDRQ_ID(phba, ulp); | |
1633 | req->data_ring_id = HWI_GET_DEF_BUFQ_ID(phba, ulp); | |
1634 | } else { | |
1635 | req_v1 = (struct iscsi_cleanup_req_v1 *)req; | |
1636 | req_v1->hdr.version = 1; | |
1637 | req_v1->hdr_ring_id = cpu_to_le16(HWI_GET_DEF_HDRQ_ID(phba, | |
1638 | ulp)); | |
1639 | req_v1->data_ring_id = cpu_to_le16(HWI_GET_DEF_BUFQ_ID(phba, | |
1640 | ulp)); | |
1641 | } | |
1642 | ||
1643 | status = be_mbox_notify(ctrl); | |
1644 | if (status) | |
1645 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, | |
1646 | "BG_%d : %s failed %d\n", __func__, ulp); | |
1647 | mutex_unlock(&ctrl->mbox_lock); | |
1648 | return status; | |
1649 | } |