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scsi: be2iscsi: Fix queue and connection parameters
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / be2iscsi / be_main.c
CommitLineData
6733b39a 1/**
c4f39bda 2 * Copyright (C) 2005 - 2015 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
4627de93 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@avagotech.com)
6733b39a
JK		 11 *
12 * Contact Information:
4627de93 13 * linux-drivers@avagotech.com
6733b39a 14 *
c4f39bda 15 * Emulex
255fa9a3
JK		 16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a 18 */
255fa9a3 19
6733b39a
JK		 20#include <linux/reboot.h>
21#include <linux/delay.h>
5a0e3ad6 22#include <linux/slab.h>
6733b39a
JK		 23#include <linux/interrupt.h>
24#include <linux/blkdev.h>
25#include <linux/pci.h>
26#include <linux/string.h>
27#include <linux/kernel.h>
28#include <linux/semaphore.h>
c7acc5b8 29#include <linux/iscsi_boot_sysfs.h>
acf3368f 30#include <linux/module.h>
ffce3e2e 31#include <linux/bsg-lib.h>
1094cf68 32#include <linux/irq_poll.h>
6733b39a
JK		 33
34#include <scsi/libiscsi.h>
ffce3e2e
JK		 35#include <scsi/scsi_bsg_iscsi.h>
36#include <scsi/scsi_netlink.h>
6733b39a
JK		 37#include <scsi/scsi_transport_iscsi.h>
38#include <scsi/scsi_transport.h>
39#include <scsi/scsi_cmnd.h>
40#include <scsi/scsi_device.h>
41#include <scsi/scsi_host.h>
42#include <scsi/scsi.h>
43#include "be_main.h"
44#include "be_iscsi.h"
45#include "be_mgmt.h"
0a513dd8 46#include "be_cmds.h"
6733b39a
JK		 47
48static unsigned int be_iopoll_budget = 10;
49static unsigned int be_max_phys_size = 64;
bfead3b2 50static unsigned int enable_msix = 1;
6733b39a 51
6733b39a 52MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
76d15dbd 53MODULE_VERSION(BUILD_STR);
c4f39bda 54MODULE_AUTHOR("Emulex Corporation");
6733b39a
JK		 55MODULE_LICENSE("GPL");
56module_param(be_iopoll_budget, int, 0);
57module_param(enable_msix, int, 0);
58module_param(be_max_phys_size, uint, S_IRUGO);
99bc5d55
JSJ		 59MODULE_PARM_DESC(be_max_phys_size,
60 "Maximum Size (In Kilobytes) of physically contiguous "
61 "memory that can be allocated. Range is 16 - 128");
62
63#define beiscsi_disp_param(_name)\
64ssize_t \
65beiscsi_##_name##_disp(struct device *dev,\
66 struct device_attribute *attrib, char *buf) \
67{ \
68 struct Scsi_Host *shost = class_to_shost(dev);\
69 struct beiscsi_hba *phba = iscsi_host_priv(shost); \
70 uint32_t param_val = 0; \
71 param_val = phba->attr_##_name;\
72 return snprintf(buf, PAGE_SIZE, "%d\n",\
73 phba->attr_##_name);\
74}
75
76#define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
77int \
78beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
79{\
80 if (val >= _minval && val <= _maxval) {\
81 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
82 "BA_%d : beiscsi_"#_name" updated "\
83 "from 0x%x ==> 0x%x\n",\
84 phba->attr_##_name, val); \
85 phba->attr_##_name = val;\
86 return 0;\
87 } \
88 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
89 "BA_%d beiscsi_"#_name" attribute "\
90 "cannot be updated to 0x%x, "\
91 "range allowed is ["#_minval" - "#_maxval"]\n", val);\
92 return -EINVAL;\
93}
94
95#define beiscsi_store_param(_name) \
96ssize_t \
97beiscsi_##_name##_store(struct device *dev,\
98 struct device_attribute *attr, const char *buf,\
99 size_t count) \
100{ \
101 struct Scsi_Host *shost = class_to_shost(dev);\
102 struct beiscsi_hba *phba = iscsi_host_priv(shost);\
103 uint32_t param_val = 0;\
104 if (!isdigit(buf[0]))\
105 return -EINVAL;\
106 if (sscanf(buf, "%i", &param_val) != 1)\
107 return -EINVAL;\
108 if (beiscsi_##_name##_change(phba, param_val) == 0) \
109 return strlen(buf);\
110 else \
111 return -EINVAL;\
112}
113
114#define beiscsi_init_param(_name, _minval, _maxval, _defval) \
115int \
116beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
117{ \
118 if (val >= _minval && val <= _maxval) {\
119 phba->attr_##_name = val;\
120 return 0;\
121 } \
122 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
123 "BA_%d beiscsi_"#_name" attribute " \
124 "cannot be updated to 0x%x, "\
125 "range allowed is ["#_minval" - "#_maxval"]\n", val);\
126 phba->attr_##_name = _defval;\
127 return -EINVAL;\
128}
129
130#define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
131static uint beiscsi_##_name = _defval;\
132module_param(beiscsi_##_name, uint, S_IRUGO);\
133MODULE_PARM_DESC(beiscsi_##_name, _descp);\
134beiscsi_disp_param(_name)\
135beiscsi_change_param(_name, _minval, _maxval, _defval)\
136beiscsi_store_param(_name)\
137beiscsi_init_param(_name, _minval, _maxval, _defval)\
138DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
139 beiscsi_##_name##_disp, beiscsi_##_name##_store)
140
141/*
142 * When new log level added update the
143 * the MAX allowed value for log_enable
144 */
145BEISCSI_RW_ATTR(log_enable, 0x00,
146 0xFF, 0x00, "Enable logging Bit Mask\n"
147 "\t\t\t\tInitialization Events : 0x01\n"
148 "\t\t\t\tMailbox Events : 0x02\n"
149 "\t\t\t\tMiscellaneous Events : 0x04\n"
150 "\t\t\t\tError Handling : 0x08\n"
151 "\t\t\t\tIO Path Events : 0x10\n"
afb96058
JK		 152 "\t\t\t\tConfiguration Path : 0x20\n"
153 "\t\t\t\tiSCSI Protocol : 0x40\n");
99bc5d55 154
5cac7596 155DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
26000db7 156DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL);
22661e25 157DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL);
d3fea9af 158DEVICE_ATTR(beiscsi_phys_port, S_IRUGO, beiscsi_phys_port_disp, NULL);
6103c1f7
JK		 159DEVICE_ATTR(beiscsi_active_session_count, S_IRUGO,
160 beiscsi_active_session_disp, NULL);
161DEVICE_ATTR(beiscsi_free_session_count, S_IRUGO,
162 beiscsi_free_session_disp, NULL);
99bc5d55
JSJ		 163struct device_attribute *beiscsi_attrs[] = {
164 &dev_attr_beiscsi_log_enable,
5cac7596 165 &dev_attr_beiscsi_drvr_ver,
26000db7 166 &dev_attr_beiscsi_adapter_family,
22661e25 167 &dev_attr_beiscsi_fw_ver,
6103c1f7
JK		 168 &dev_attr_beiscsi_active_session_count,
169 &dev_attr_beiscsi_free_session_count,
d3fea9af 170 &dev_attr_beiscsi_phys_port,
99bc5d55
JSJ		 171 NULL,
172};
6733b39a 173
6763daae
JSJ		 174static char const *cqe_desc[] = {
175 "RESERVED_DESC",
176 "SOL_CMD_COMPLETE",
177 "SOL_CMD_KILLED_DATA_DIGEST_ERR",
178 "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
179 "CXN_KILLED_BURST_LEN_MISMATCH",
180 "CXN_KILLED_AHS_RCVD",
181 "CXN_KILLED_HDR_DIGEST_ERR",
182 "CXN_KILLED_UNKNOWN_HDR",
183 "CXN_KILLED_STALE_ITT_TTT_RCVD",
184 "CXN_KILLED_INVALID_ITT_TTT_RCVD",
185 "CXN_KILLED_RST_RCVD",
186 "CXN_KILLED_TIMED_OUT",
187 "CXN_KILLED_RST_SENT",
188 "CXN_KILLED_FIN_RCVD",
189 "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
190 "CXN_KILLED_BAD_WRB_INDEX_ERROR",
191 "CXN_KILLED_OVER_RUN_RESIDUAL",
192 "CXN_KILLED_UNDER_RUN_RESIDUAL",
193 "CMD_KILLED_INVALID_STATSN_RCVD",
194 "CMD_KILLED_INVALID_R2T_RCVD",
195 "CMD_CXN_KILLED_LUN_INVALID",
196 "CMD_CXN_KILLED_ICD_INVALID",
197 "CMD_CXN_KILLED_ITT_INVALID",
198 "CMD_CXN_KILLED_SEQ_OUTOFORDER",
199 "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
200 "CXN_INVALIDATE_NOTIFY",
201 "CXN_INVALIDATE_INDEX_NOTIFY",
202 "CMD_INVALIDATED_NOTIFY",
203 "UNSOL_HDR_NOTIFY",
204 "UNSOL_DATA_NOTIFY",
205 "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
206 "DRIVERMSG_NOTIFY",
207 "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
208 "SOL_CMD_KILLED_DIF_ERR",
209 "CXN_KILLED_SYN_RCVD",
210 "CXN_KILLED_IMM_DATA_RCVD"
211};
212
6733b39a
JK		 213static int beiscsi_slave_configure(struct scsi_device *sdev)
214{
215 blk_queue_max_segment_size(sdev->request_queue, 65536);
216 return 0;
217}
218
4183122d
JK		 219static int beiscsi_eh_abort(struct scsi_cmnd *sc)
220{
221 struct iscsi_cls_session *cls_session;
222 struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
223 struct beiscsi_io_task *aborted_io_task;
224 struct iscsi_conn *conn;
225 struct beiscsi_conn *beiscsi_conn;
226 struct beiscsi_hba *phba;
227 struct iscsi_session *session;
228 struct invalidate_command_table *inv_tbl;
3cbb7a74 229 struct be_dma_mem nonemb_cmd;
4183122d 230 unsigned int cid, tag, num_invalidate;
1957aa7f 231 int rc;
4183122d
JK		 232
233 cls_session = starget_to_session(scsi_target(sc->device));
234 session = cls_session->dd_data;
235
659743b0 236 spin_lock_bh(&session->frwd_lock);
4183122d
JK		 237 if (!aborted_task || !aborted_task->sc) {
238 /* we raced */
659743b0 239 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 240 return SUCCESS;
241 }
242
243 aborted_io_task = aborted_task->dd_data;
244 if (!aborted_io_task->scsi_cmnd) {
245 /* raced or invalid command */
659743b0 246 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 247 return SUCCESS;
248 }
659743b0 249 spin_unlock_bh(&session->frwd_lock);
7626c06b
JK		 250 /* Invalidate WRB Posted for this Task */
251 AMAP_SET_BITS(struct amap_iscsi_wrb, invld,
252 aborted_io_task->pwrb_handle->pwrb,
253 1);
254
4183122d
JK		 255 conn = aborted_task->conn;
256 beiscsi_conn = conn->dd_data;
257 phba = beiscsi_conn->phba;
258
259 /* invalidate iocb */
260 cid = beiscsi_conn->beiscsi_conn_cid;
261 inv_tbl = phba->inv_tbl;
262 memset(inv_tbl, 0x0, sizeof(*inv_tbl));
263 inv_tbl->cid = cid;
264 inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
265 num_invalidate = 1;
3cbb7a74
JK		 266 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
267 sizeof(struct invalidate_commands_params_in),
268 &nonemb_cmd.dma);
269 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 270 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
271 "BM_%d : Failed to allocate memory for"
272 "mgmt_invalidate_icds\n");
3cbb7a74
JK		 273 return FAILED;
274 }
275 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
276
277 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
278 cid, &nonemb_cmd);
4183122d 279 if (!tag) {
99bc5d55
JSJ		 280 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
281 "BM_%d : mgmt_invalidate_icds could not be"
282 "submitted\n");
3cbb7a74
JK		 283 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
284 nonemb_cmd.va, nonemb_cmd.dma);
285
4183122d 286 return FAILED;
4183122d 287 }
e175defe 288
88840332 289 rc = beiscsi_mccq_compl_wait(phba, tag, NULL, &nonemb_cmd);
1957aa7f
JK		 290 if (rc != -EBUSY)
291 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
292 nonemb_cmd.va, nonemb_cmd.dma);
293
4183122d
JK		 294 return iscsi_eh_abort(sc);
295}
296
297static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
298{
299 struct iscsi_task *abrt_task;
300 struct beiscsi_io_task *abrt_io_task;
301 struct iscsi_conn *conn;
302 struct beiscsi_conn *beiscsi_conn;
303 struct beiscsi_hba *phba;
304 struct iscsi_session *session;
305 struct iscsi_cls_session *cls_session;
306 struct invalidate_command_table *inv_tbl;
3cbb7a74 307 struct be_dma_mem nonemb_cmd;
4183122d 308 unsigned int cid, tag, i, num_invalidate;
1957aa7f 309 int rc;
4183122d
JK		 310
311 /* invalidate iocbs */
312 cls_session = starget_to_session(scsi_target(sc->device));
313 session = cls_session->dd_data;
659743b0 314 spin_lock_bh(&session->frwd_lock);
db7f7709 315 if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
659743b0 316 spin_unlock_bh(&session->frwd_lock);
db7f7709
JK		 317 return FAILED;
318 }
4183122d
JK		 319 conn = session->leadconn;
320 beiscsi_conn = conn->dd_data;
321 phba = beiscsi_conn->phba;
322 cid = beiscsi_conn->beiscsi_conn_cid;
323 inv_tbl = phba->inv_tbl;
324 memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
325 num_invalidate = 0;
326 for (i = 0; i < conn->session->cmds_max; i++) {
327 abrt_task = conn->session->cmds[i];
328 abrt_io_task = abrt_task->dd_data;
329 if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
330 continue;
331
126e964a 332 if (sc->device->lun != abrt_task->sc->device->lun)
4183122d
JK		 333 continue;
334
7626c06b
JK		 335 /* Invalidate WRB Posted for this Task */
336 AMAP_SET_BITS(struct amap_iscsi_wrb, invld,
337 abrt_io_task->pwrb_handle->pwrb,
338 1);
339
4183122d
JK		 340 inv_tbl->cid = cid;
341 inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
342 num_invalidate++;
343 inv_tbl++;
344 }
659743b0 345 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 346 inv_tbl = phba->inv_tbl;
347
3cbb7a74
JK		 348 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
349 sizeof(struct invalidate_commands_params_in),
350 &nonemb_cmd.dma);
351 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 352 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
353 "BM_%d : Failed to allocate memory for"
354 "mgmt_invalidate_icds\n");
3cbb7a74
JK		 355 return FAILED;
356 }
357 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
358 memset(nonemb_cmd.va, 0, nonemb_cmd.size);
359 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
360 cid, &nonemb_cmd);
4183122d 361 if (!tag) {
99bc5d55
JSJ		 362 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
363 "BM_%d : mgmt_invalidate_icds could not be"
364 " submitted\n");
3cbb7a74
JK		 365 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
366 nonemb_cmd.va, nonemb_cmd.dma);
4183122d 367 return FAILED;
4183122d 368 }
e175defe 369
88840332 370 rc = beiscsi_mccq_compl_wait(phba, tag, NULL, &nonemb_cmd);
1957aa7f
JK		 371 if (rc != -EBUSY)
372 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
373 nonemb_cmd.va, nonemb_cmd.dma);
4183122d 374 return iscsi_eh_device_reset(sc);
4183122d
JK		 375}
376
bfead3b2 377/*------------------- PCI Driver operations and data ----------------- */
9baa3c34 378static const struct pci_device_id beiscsi_pci_id_table[] = {
bfead3b2 379 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
f98c96b0 380 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
bfead3b2
JK		 381 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
382 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
383 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
139a1b1e 384 { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
bfead3b2
JK		 385 { 0 }
386};
387MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
388
99bc5d55 389
6733b39a
JK		 390static struct scsi_host_template beiscsi_sht = {
391 .module = THIS_MODULE,
c4f39bda 392 .name = "Emulex 10Gbe open-iscsi Initiator Driver",
6733b39a
JK		 393 .proc_name = DRV_NAME,
394 .queuecommand = iscsi_queuecommand,
db5ed4df 395 .change_queue_depth = scsi_change_queue_depth,
6733b39a
JK		 396 .slave_configure = beiscsi_slave_configure,
397 .target_alloc = iscsi_target_alloc,
4183122d
JK		 398 .eh_abort_handler = beiscsi_eh_abort,
399 .eh_device_reset_handler = beiscsi_eh_device_reset,
309ce156 400 .eh_target_reset_handler = iscsi_eh_session_reset,
99bc5d55 401 .shost_attrs = beiscsi_attrs,
6733b39a
JK		 402 .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
403 .can_queue = BE2_IO_DEPTH,
404 .this_id = -1,
405 .max_sectors = BEISCSI_MAX_SECTORS,
406 .cmd_per_lun = BEISCSI_CMD_PER_LUN,
407 .use_clustering = ENABLE_CLUSTERING,
ffce3e2e 408 .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
c40ecc12 409 .track_queue_depth = 1,
6733b39a 410};
6733b39a 411
bfead3b2 412static struct scsi_transport_template *beiscsi_scsi_transport;
6733b39a
JK		 413
414static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
415{
416 struct beiscsi_hba *phba;
417 struct Scsi_Host *shost;
418
419 shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
420 if (!shost) {
99bc5d55
JSJ		 421 dev_err(&pcidev->dev,
422 "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
6733b39a
JK		 423 return NULL;
424 }
6733b39a
JK		 425 shost->max_id = BE2_MAX_SESSIONS;
426 shost->max_channel = 0;
427 shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
428 shost->max_lun = BEISCSI_NUM_MAX_LUN;
429 shost->transportt = beiscsi_scsi_transport;
6733b39a
JK		 430 phba = iscsi_host_priv(shost);
431 memset(phba, 0, sizeof(*phba));
432 phba->shost = shost;
433 phba->pcidev = pci_dev_get(pcidev);
2807afb7 434 pci_set_drvdata(pcidev, phba);
0e43895e 435 phba->interface_handle = 0xFFFFFFFF;
6733b39a 436
6733b39a 437 return phba;
6733b39a
JK		 438}
439
440static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
441{
442 if (phba->csr_va) {
443 iounmap(phba->csr_va);
444 phba->csr_va = NULL;
445 }
446 if (phba->db_va) {
447 iounmap(phba->db_va);
448 phba->db_va = NULL;
449 }
450 if (phba->pci_va) {
451 iounmap(phba->pci_va);
452 phba->pci_va = NULL;
453 }
454}
455
456static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
457 struct pci_dev *pcidev)
458{
459 u8 __iomem *addr;
f98c96b0 460 int pcicfg_reg;
6733b39a
JK		 461
462 addr = ioremap_nocache(pci_resource_start(pcidev, 2),
463 pci_resource_len(pcidev, 2));
464 if (addr == NULL)
465 return -ENOMEM;
466 phba->ctrl.csr = addr;
467 phba->csr_va = addr;
468 phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
469
470 addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
471 if (addr == NULL)
472 goto pci_map_err;
473 phba->ctrl.db = addr;
474 phba->db_va = addr;
475 phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
476
f98c96b0
JK		 477 if (phba->generation == BE_GEN2)
478 pcicfg_reg = 1;
479 else
480 pcicfg_reg = 0;
481
482 addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
483 pci_resource_len(pcidev, pcicfg_reg));
484
6733b39a
JK		 485 if (addr == NULL)
486 goto pci_map_err;
487 phba->ctrl.pcicfg = addr;
488 phba->pci_va = addr;
f98c96b0 489 phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
6733b39a
JK		 490 return 0;
491
492pci_map_err:
493 beiscsi_unmap_pci_function(phba);
494 return -ENOMEM;
495}
496
497static int beiscsi_enable_pci(struct pci_dev *pcidev)
498{
499 int ret;
500
501 ret = pci_enable_device(pcidev);
502 if (ret) {
99bc5d55
JSJ		 503 dev_err(&pcidev->dev,
504 "beiscsi_enable_pci - enable device failed\n");
6733b39a
JK		 505 return ret;
506 }
507
e307f3ac
JSJ		 508 ret = pci_request_regions(pcidev, DRV_NAME);
509 if (ret) {
510 dev_err(&pcidev->dev,
511 "beiscsi_enable_pci - request region failed\n");
512 goto pci_dev_disable;
513 }
514
bfead3b2 515 pci_set_master(pcidev);
6c57625b
JK		 516 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64));
517 if (ret) {
518 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
519 if (ret) {
520 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
e307f3ac 521 goto pci_region_release;
6c57625b
JK		 522 } else {
523 ret = pci_set_consistent_dma_mask(pcidev,
524 DMA_BIT_MASK(32));
525 }
526 } else {
527 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
6733b39a
JK		 528 if (ret) {
529 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
e307f3ac 530 goto pci_region_release;
6733b39a
JK		 531 }
532 }
533 return 0;
e307f3ac
JSJ		 534
535pci_region_release:
536 pci_release_regions(pcidev);
537pci_dev_disable:
538 pci_disable_device(pcidev);
539
540 return ret;
6733b39a
JK		 541}
542
543static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
544{
545 struct be_ctrl_info *ctrl = &phba->ctrl;
546 struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
547 struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
548 int status = 0;
549
550 ctrl->pdev = pdev;
551 status = beiscsi_map_pci_bars(phba, pdev);
552 if (status)
553 return status;
6733b39a
JK		 554 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
555 mbox_mem_alloc->va = pci_alloc_consistent(pdev,
556 mbox_mem_alloc->size,
557 &mbox_mem_alloc->dma);
558 if (!mbox_mem_alloc->va) {
559 beiscsi_unmap_pci_function(phba);
a49e06d5 560 return -ENOMEM;
6733b39a
JK		 561 }
562
563 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
564 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
565 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
566 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
c03a50f7 567 mutex_init(&ctrl->mbox_lock);
bfead3b2 568 spin_lock_init(&phba->ctrl.mcc_lock);
bfead3b2 569
6733b39a
JK		 570 return status;
571}
572
843ae752
JK		 573/**
574 * beiscsi_get_params()- Set the config paramters
575 * @phba: ptr device priv structure
576 **/
6733b39a
JK		 577static void beiscsi_get_params(struct beiscsi_hba *phba)
578{
843ae752
JK		 579 uint32_t total_cid_count = 0;
580 uint32_t total_icd_count = 0;
581 uint8_t ulp_num = 0;
582
583 total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) +
584 BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1);
585
cf987b79
JK		 586 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
587 uint32_t align_mask = 0;
588 uint32_t icd_post_per_page = 0;
589 uint32_t icd_count_unavailable = 0;
590 uint32_t icd_start = 0, icd_count = 0;
591 uint32_t icd_start_align = 0, icd_count_align = 0;
592
843ae752 593 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
cf987b79
JK		 594 icd_start = phba->fw_config.iscsi_icd_start[ulp_num];
595 icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
596
597 /* Get ICD count that can be posted on each page */
598 icd_post_per_page = (PAGE_SIZE / (BE2_SGE *
599 sizeof(struct iscsi_sge)));
600 align_mask = (icd_post_per_page - 1);
601
602 /* Check if icd_start is aligned ICD per page posting */
603 if (icd_start % icd_post_per_page) {
604 icd_start_align = ((icd_start +
605 icd_post_per_page) &
606 ~(align_mask));
607 phba->fw_config.
608 iscsi_icd_start[ulp_num] =
609 icd_start_align;
610 }
611
612 icd_count_align = (icd_count & ~align_mask);
613
614 /* ICD discarded in the process of alignment */
615 if (icd_start_align)
616 icd_count_unavailable = ((icd_start_align -
617 icd_start) +
618 (icd_count -
619 icd_count_align));
620
621 /* Updated ICD count available */
622 phba->fw_config.iscsi_icd_count[ulp_num] = (icd_count -
623 icd_count_unavailable);
624
625 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
626 "BM_%d : Aligned ICD values\n"
627 "\t ICD Start : %d\n"
628 "\t ICD Count : %d\n"
629 "\t ICD Discarded : %d\n",
630 phba->fw_config.
631 iscsi_icd_start[ulp_num],
632 phba->fw_config.
633 iscsi_icd_count[ulp_num],
634 icd_count_unavailable);
843ae752
JK		 635 break;
636 }
cf987b79 637 }
843ae752 638
cf987b79 639 total_icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
843ae752
JK		 640 phba->params.ios_per_ctrl = (total_icd_count -
641 (total_cid_count +
642 BE2_TMFS + BE2_NOPOUT_REQ));
643 phba->params.cxns_per_ctrl = total_cid_count;
644 phba->params.asyncpdus_per_ctrl = total_cid_count;
645 phba->params.icds_per_ctrl = total_icd_count;
6733b39a
JK		 646 phba->params.num_sge_per_io = BE2_SGE;
647 phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
648 phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
649 phba->params.eq_timer = 64;
843ae752
JK		 650 phba->params.num_eq_entries = 1024;
651 phba->params.num_cq_entries = 1024;
6733b39a
JK		 652 phba->params.wrbs_per_cxn = 256;
653}
654
655static void hwi_ring_eq_db(struct beiscsi_hba *phba,
656 unsigned int id, unsigned int clr_interrupt,
657 unsigned int num_processed,
658 unsigned char rearm, unsigned char event)
659{
660 u32 val = 0;
e08b3c8b 661
6733b39a
JK		 662 if (rearm)
663 val |= 1 << DB_EQ_REARM_SHIFT;
664 if (clr_interrupt)
665 val |= 1 << DB_EQ_CLR_SHIFT;
666 if (event)
667 val |= 1 << DB_EQ_EVNT_SHIFT;
e08b3c8b 668
6733b39a 669 val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
e08b3c8b
JK		 670 /* Setting lower order EQ_ID Bits */
671 val |= (id & DB_EQ_RING_ID_LOW_MASK);
672
673 /* Setting Higher order EQ_ID Bits */
674 val |= (((id >> DB_EQ_HIGH_FEILD_SHIFT) &
675 DB_EQ_RING_ID_HIGH_MASK)
676 << DB_EQ_HIGH_SET_SHIFT);
677
6733b39a
JK		 678 iowrite32(val, phba->db_va + DB_EQ_OFFSET);
679}
680
bfead3b2
JK		 681/**
682 * be_isr_mcc - The isr routine of the driver.
683 * @irq: Not used
684 * @dev_id: Pointer to host adapter structure
685 */
686static irqreturn_t be_isr_mcc(int irq, void *dev_id)
687{
688 struct beiscsi_hba *phba;
a3095016 689 struct be_eq_entry *eqe;
bfead3b2
JK		 690 struct be_queue_info *eq;
691 struct be_queue_info *mcc;
a3095016 692 unsigned int mcc_events;
bfead3b2 693 struct be_eq_obj *pbe_eq;
bfead3b2
JK		 694
695 pbe_eq = dev_id;
696 eq = &pbe_eq->q;
697 phba = pbe_eq->phba;
698 mcc = &phba->ctrl.mcc_obj.cq;
699 eqe = queue_tail_node(eq);
bfead3b2 700
a3095016 701 mcc_events = 0;
bfead3b2
JK		 702 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
703 & EQE_VALID_MASK) {
704 if (((eqe->dw[offsetof(struct amap_eq_entry,
705 resource_id) / 32] &
706 EQE_RESID_MASK) >> 16) == mcc->id) {
a3095016 707 mcc_events++;
bfead3b2
JK		 708 }
709 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
710 queue_tail_inc(eq);
711 eqe = queue_tail_node(eq);
bfead3b2 712 }
bfead3b2 713
a3095016
JB		 714 if (mcc_events) {
715 queue_work(phba->wq, &pbe_eq->mcc_work);
716 hwi_ring_eq_db(phba, eq->id, 1, mcc_events, 1, 1);
717 }
bfead3b2
JK		 718 return IRQ_HANDLED;
719}
720
721/**
722 * be_isr_msix - The isr routine of the driver.
723 * @irq: Not used
724 * @dev_id: Pointer to host adapter structure
725 */
726static irqreturn_t be_isr_msix(int irq, void *dev_id)
727{
728 struct beiscsi_hba *phba;
bfead3b2 729 struct be_queue_info *eq;
bfead3b2 730 struct be_eq_obj *pbe_eq;
bfead3b2
JK		 731
732 pbe_eq = dev_id;
733 eq = &pbe_eq->q;
bfead3b2
JK		 734
735 phba = pbe_eq->phba;
1094cf68
JB		 736 /* disable interrupt till iopoll completes */
737 hwi_ring_eq_db(phba, eq->id, 1, 0, 0, 1);
738 irq_poll_sched(&pbe_eq->iopoll);
72fb46a9
JSJ		 739
740 return IRQ_HANDLED;
bfead3b2
JK		 741}
742
6733b39a
JK		 743/**
744 * be_isr - The isr routine of the driver.
745 * @irq: Not used
746 * @dev_id: Pointer to host adapter structure
747 */
748static irqreturn_t be_isr(int irq, void *dev_id)
749{
750 struct beiscsi_hba *phba;
751 struct hwi_controller *phwi_ctrlr;
752 struct hwi_context_memory *phwi_context;
a3095016 753 struct be_eq_entry *eqe;
6733b39a 754 struct be_queue_info *eq;
bfead3b2 755 struct be_queue_info *mcc;
a3095016 756 unsigned int mcc_events, io_events;
6733b39a 757 struct be_ctrl_info *ctrl;
bfead3b2 758 struct be_eq_obj *pbe_eq;
a3095016 759 int isr, rearm;
6733b39a
JK		 760
761 phba = dev_id;
6eab04a8 762 ctrl = &phba->ctrl;
bfead3b2
JK		 763 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
764 (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
765 if (!isr)
766 return IRQ_NONE;
6733b39a
JK		 767
768 phwi_ctrlr = phba->phwi_ctrlr;
769 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 770 pbe_eq = &phwi_context->be_eq[0];
771
772 eq = &phwi_context->be_eq[0].q;
773 mcc = &phba->ctrl.mcc_obj.cq;
6733b39a 774 eqe = queue_tail_node(eq);
6733b39a 775
a3095016
JB		 776 io_events = 0;
777 mcc_events = 0;
89f8b33c
JA		 778 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
779 & EQE_VALID_MASK) {
780 if (((eqe->dw[offsetof(struct amap_eq_entry,
a3095016
JB		 781 resource_id) / 32] & EQE_RESID_MASK) >> 16) == mcc->id)
782 mcc_events++;
783 else
784 io_events++;
89f8b33c
JA		 785 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
786 queue_tail_inc(eq);
787 eqe = queue_tail_node(eq);
788 }
a3095016 789 if (!io_events && !mcc_events)
89f8b33c 790 return IRQ_NONE;
a3095016
JB		 791
792 /* no need to rearm if interrupt is only for IOs */
793 rearm = 0;
794 if (mcc_events) {
795 queue_work(phba->wq, &pbe_eq->mcc_work);
796 /* rearm for MCCQ */
797 rearm = 1;
798 }
799 if (io_events)
800 irq_poll_sched(&pbe_eq->iopoll);
801 hwi_ring_eq_db(phba, eq->id, 0, (io_events + mcc_events), rearm, 1);
802 return IRQ_HANDLED;
6733b39a
JK		 803}
804
1094cf68 805
6733b39a
JK		 806static int beiscsi_init_irqs(struct beiscsi_hba *phba)
807{
808 struct pci_dev *pcidev = phba->pcidev;
bfead3b2
JK		 809 struct hwi_controller *phwi_ctrlr;
810 struct hwi_context_memory *phwi_context;
4f5af07e 811 int ret, msix_vec, i, j;
6733b39a 812
bfead3b2
JK		 813 phwi_ctrlr = phba->phwi_ctrlr;
814 phwi_context = phwi_ctrlr->phwi_ctxt;
815
816 if (phba->msix_enabled) {
817 for (i = 0; i < phba->num_cpus; i++) {
8fcfb210
JK		 818 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
819 GFP_KERNEL);
820 if (!phba->msi_name[i]) {
821 ret = -ENOMEM;
822 goto free_msix_irqs;
823 }
824
825 sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
826 phba->shost->host_no, i);
bfead3b2 827 msix_vec = phba->msix_entries[i].vector;
8fcfb210
JK		 828 ret = request_irq(msix_vec, be_isr_msix, 0,
829 phba->msi_name[i],
bfead3b2 830 &phwi_context->be_eq[i]);
4f5af07e 831 if (ret) {
99bc5d55
JSJ		 832 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
833 "BM_%d : beiscsi_init_irqs-Failed to"
834 "register msix for i = %d\n",
835 i);
8fcfb210 836 kfree(phba->msi_name[i]);
4f5af07e
JK		 837 goto free_msix_irqs;
838 }
bfead3b2 839 }
8fcfb210
JK		 840 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
841 if (!phba->msi_name[i]) {
842 ret = -ENOMEM;
843 goto free_msix_irqs;
844 }
845 sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
846 phba->shost->host_no);
bfead3b2 847 msix_vec = phba->msix_entries[i].vector;
8fcfb210 848 ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
bfead3b2 849 &phwi_context->be_eq[i]);
4f5af07e 850 if (ret) {
99bc5d55
JSJ		 851 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
852 "BM_%d : beiscsi_init_irqs-"
853 "Failed to register beiscsi_msix_mcc\n");
8fcfb210 854 kfree(phba->msi_name[i]);
4f5af07e
JK		 855 goto free_msix_irqs;
856 }
857
bfead3b2
JK		 858 } else {
859 ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
860 "beiscsi", phba);
861 if (ret) {
99bc5d55
JSJ		 862 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
863 "BM_%d : beiscsi_init_irqs-"
864 "Failed to register irq\\n");
bfead3b2
JK		 865 return ret;
866 }
6733b39a
JK		 867 }
868 return 0;
4f5af07e 869free_msix_irqs:
8fcfb210
JK		 870 for (j = i - 1; j >= 0; j--) {
871 kfree(phba->msi_name[j]);
872 msix_vec = phba->msix_entries[j].vector;
4f5af07e 873 free_irq(msix_vec, &phwi_context->be_eq[j]);
8fcfb210 874 }
4f5af07e 875 return ret;
6733b39a
JK		 876}
877
e08b3c8b 878void hwi_ring_cq_db(struct beiscsi_hba *phba,
6733b39a 879 unsigned int id, unsigned int num_processed,
1094cf68 880 unsigned char rearm)
6733b39a
JK		 881{
882 u32 val = 0;
e08b3c8b 883
6733b39a
JK		 884 if (rearm)
885 val |= 1 << DB_CQ_REARM_SHIFT;
e08b3c8b 886
6733b39a 887 val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
e08b3c8b
JK		 888
889 /* Setting lower order CQ_ID Bits */
890 val |= (id & DB_CQ_RING_ID_LOW_MASK);
891
892 /* Setting Higher order CQ_ID Bits */
893 val |= (((id >> DB_CQ_HIGH_FEILD_SHIFT) &
894 DB_CQ_RING_ID_HIGH_MASK)
895 << DB_CQ_HIGH_SET_SHIFT);
896
6733b39a
JK		 897 iowrite32(val, phba->db_va + DB_CQ_OFFSET);
898}
899
6733b39a
JK		 900static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
901{
902 struct sgl_handle *psgl_handle;
903
10139fe0 904 spin_lock_bh(&phba->io_sgl_lock);
6733b39a 905 if (phba->io_sgl_hndl_avbl) {
99bc5d55
JSJ		 906 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
907 "BM_%d : In alloc_io_sgl_handle,"
908 " io_sgl_alloc_index=%d\n",
909 phba->io_sgl_alloc_index);
910
6733b39a
JK		 911 psgl_handle = phba->io_sgl_hndl_base[phba->
912 io_sgl_alloc_index];
913 phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
914 phba->io_sgl_hndl_avbl--;
bfead3b2
JK		 915 if (phba->io_sgl_alloc_index == (phba->params.
916 ios_per_ctrl - 1))
6733b39a
JK		 917 phba->io_sgl_alloc_index = 0;
918 else
919 phba->io_sgl_alloc_index++;
920 } else
921 psgl_handle = NULL;
10139fe0 922 spin_unlock_bh(&phba->io_sgl_lock);
6733b39a
JK		 923 return psgl_handle;
924}
925
926static void
927free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
928{
10139fe0 929 spin_lock_bh(&phba->io_sgl_lock);
99bc5d55
JSJ		 930 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
931 "BM_%d : In free_,io_sgl_free_index=%d\n",
932 phba->io_sgl_free_index);
933
6733b39a
JK		 934 if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
935 /*
936 * this can happen if clean_task is called on a task that
937 * failed in xmit_task or alloc_pdu.
938 */
99bc5d55
JSJ		 939 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
940 "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
941 "value there=%p\n", phba->io_sgl_free_index,
942 phba->io_sgl_hndl_base
943 [phba->io_sgl_free_index]);
10139fe0 944 spin_unlock_bh(&phba->io_sgl_lock);
6733b39a
JK		 945 return;
946 }
947 phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
948 phba->io_sgl_hndl_avbl++;
949 if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
950 phba->io_sgl_free_index = 0;
951 else
952 phba->io_sgl_free_index++;
10139fe0 953 spin_unlock_bh(&phba->io_sgl_lock);
6733b39a
JK		 954}
955
cb564c6b
JB		 956static inline struct wrb_handle *
957beiscsi_get_wrb_handle(struct hwi_wrb_context *pwrb_context,
958 unsigned int wrbs_per_cxn)
959{
960 struct wrb_handle *pwrb_handle;
961
f64d92e6 962 spin_lock_bh(&pwrb_context->wrb_lock);
cb564c6b
JB		 963 pwrb_handle = pwrb_context->pwrb_handle_base[pwrb_context->alloc_index];
964 pwrb_context->wrb_handles_available--;
965 if (pwrb_context->alloc_index == (wrbs_per_cxn - 1))
966 pwrb_context->alloc_index = 0;
967 else
968 pwrb_context->alloc_index++;
f64d92e6 969 spin_unlock_bh(&pwrb_context->wrb_lock);
e1f9d31e 970 memset(pwrb_handle->pwrb, 0, sizeof(*pwrb_handle->pwrb));
cb564c6b
JB		 971
972 return pwrb_handle;
973}
974
6733b39a
JK		 975/**
976 * alloc_wrb_handle - To allocate a wrb handle
977 * @phba: The hba pointer
978 * @cid: The cid to use for allocation
340c99e9 979 * @pwrb_context: ptr to ptr to wrb context
6733b39a
JK		 980 *
981 * This happens under session_lock until submission to chip
982 */
340c99e9 983struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
cb564c6b 984 struct hwi_wrb_context **pcontext)
6733b39a
JK		 985{
986 struct hwi_wrb_context *pwrb_context;
987 struct hwi_controller *phwi_ctrlr;
a7909b39 988 uint16_t cri_index = BE_GET_CRI_FROM_CID(cid);
6733b39a
JK		 989
990 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 991 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
cb564c6b
JB		 992 /* return the context address */
993 *pcontext = pwrb_context;
994 return beiscsi_get_wrb_handle(pwrb_context, phba->params.wrbs_per_cxn);
995}
340c99e9 996
cb564c6b
JB		 997static inline void
998beiscsi_put_wrb_handle(struct hwi_wrb_context *pwrb_context,
999 struct wrb_handle *pwrb_handle,
1000 unsigned int wrbs_per_cxn)
1001{
f64d92e6 1002 spin_lock_bh(&pwrb_context->wrb_lock);
cb564c6b
JB		 1003 pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
1004 pwrb_context->wrb_handles_available++;
1005 if (pwrb_context->free_index == (wrbs_per_cxn - 1))
1006 pwrb_context->free_index = 0;
1007 else
1008 pwrb_context->free_index++;
f64d92e6 1009 spin_unlock_bh(&pwrb_context->wrb_lock);
6733b39a
JK		 1010}
1011
1012/**
1013 * free_wrb_handle - To free the wrb handle back to pool
1014 * @phba: The hba pointer
1015 * @pwrb_context: The context to free from
1016 * @pwrb_handle: The wrb_handle to free
1017 *
1018 * This happens under session_lock until submission to chip
1019 */
1020static void
1021free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
1022 struct wrb_handle *pwrb_handle)
1023{
cb564c6b
JB		 1024 beiscsi_put_wrb_handle(pwrb_context,
1025 pwrb_handle,
1026 phba->params.wrbs_per_cxn);
99bc5d55
JSJ		 1027 beiscsi_log(phba, KERN_INFO,
1028 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1029 "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
1030 "wrb_handles_available=%d\n",
1031 pwrb_handle, pwrb_context->free_index,
1032 pwrb_context->wrb_handles_available);
6733b39a
JK		 1033}
1034
1035static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
1036{
1037 struct sgl_handle *psgl_handle;
1038
10139fe0 1039 spin_lock_bh(&phba->mgmt_sgl_lock);
6733b39a
JK		 1040 if (phba->eh_sgl_hndl_avbl) {
1041 psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
1042 phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
99bc5d55
JSJ		 1043 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
1044 "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
1045 phba->eh_sgl_alloc_index,
1046 phba->eh_sgl_alloc_index);
1047
6733b39a
JK		 1048 phba->eh_sgl_hndl_avbl--;
1049 if (phba->eh_sgl_alloc_index ==
1050 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
1051 1))
1052 phba->eh_sgl_alloc_index = 0;
1053 else
1054 phba->eh_sgl_alloc_index++;
1055 } else
1056 psgl_handle = NULL;
10139fe0 1057 spin_unlock_bh(&phba->mgmt_sgl_lock);
6733b39a
JK		 1058 return psgl_handle;
1059}
1060
1061void
1062free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
1063{
10139fe0 1064 spin_lock_bh(&phba->mgmt_sgl_lock);
99bc5d55
JSJ		 1065 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
1066 "BM_%d : In free_mgmt_sgl_handle,"
1067 "eh_sgl_free_index=%d\n",
1068 phba->eh_sgl_free_index);
1069
6733b39a
JK		 1070 if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
1071 /*
1072 * this can happen if clean_task is called on a task that
1073 * failed in xmit_task or alloc_pdu.
1074 */
99bc5d55
JSJ		 1075 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
1076 "BM_%d : Double Free in eh SGL ,"
1077 "eh_sgl_free_index=%d\n",
1078 phba->eh_sgl_free_index);
10139fe0 1079 spin_unlock_bh(&phba->mgmt_sgl_lock);
6733b39a
JK		 1080 return;
1081 }
1082 phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
1083 phba->eh_sgl_hndl_avbl++;
1084 if (phba->eh_sgl_free_index ==
1085 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
1086 phba->eh_sgl_free_index = 0;
1087 else
1088 phba->eh_sgl_free_index++;
10139fe0 1089 spin_unlock_bh(&phba->mgmt_sgl_lock);
6733b39a
JK		 1090}
1091
1092static void
1093be_complete_io(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1094 struct iscsi_task *task,
1095 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1096{
1097 struct beiscsi_io_task *io_task = task->dd_data;
1098 struct be_status_bhs *sts_bhs =
1099 (struct be_status_bhs *)io_task->cmd_bhs;
1100 struct iscsi_conn *conn = beiscsi_conn->conn;
6733b39a
JK		 1101 unsigned char *sense;
1102 u32 resid = 0, exp_cmdsn, max_cmdsn;
1103 u8 rsp, status, flags;
1104
73133261
JSJ		 1105 exp_cmdsn = csol_cqe->exp_cmdsn;
1106 max_cmdsn = (csol_cqe->exp_cmdsn +
1107 csol_cqe->cmd_wnd - 1);
1108 rsp = csol_cqe->i_resp;
1109 status = csol_cqe->i_sts;
1110 flags = csol_cqe->i_flags;
1111 resid = csol_cqe->res_cnt;
1112
bd535451 1113 if (!task->sc) {
da334977 1114 if (io_task->scsi_cmnd) {
bd535451 1115 scsi_dma_unmap(io_task->scsi_cmnd);
da334977
JK		 1116 io_task->scsi_cmnd = NULL;
1117 }
6733b39a 1118
bd535451
JK		 1119 return;
1120 }
6733b39a
JK		 1121 task->sc->result = (DID_OK << 16) | status;
1122 if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
1123 task->sc->result = DID_ERROR << 16;
1124 goto unmap;
1125 }
1126
1127 /* bidi not initially supported */
1128 if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
6733b39a
JK		 1129 if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
1130 task->sc->result = DID_ERROR << 16;
1131
1132 if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
1133 scsi_set_resid(task->sc, resid);
1134 if (!status && (scsi_bufflen(task->sc) - resid <
1135 task->sc->underflow))
1136 task->sc->result = DID_ERROR << 16;
1137 }
1138 }
1139
1140 if (status == SAM_STAT_CHECK_CONDITION) {
4053a4be 1141 u16 sense_len;
bfead3b2 1142 unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
4053a4be 1143
6733b39a 1144 sense = sts_bhs->sense_info + sizeof(unsigned short);
4053a4be 1145 sense_len = be16_to_cpu(*slen);
6733b39a
JK		 1146 memcpy(task->sc->sense_buffer, sense,
1147 min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
1148 }
756d29c8 1149
73133261
JSJ		 1150 if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ)
1151 conn->rxdata_octets += resid;
6733b39a 1152unmap:
eb1c4692
JSJ		 1153 if (io_task->scsi_cmnd) {
1154 scsi_dma_unmap(io_task->scsi_cmnd);
1155 io_task->scsi_cmnd = NULL;
1156 }
6733b39a
JK		 1157 iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
1158}
1159
1160static void
1161be_complete_logout(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1162 struct iscsi_task *task,
1163 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1164{
1165 struct iscsi_logout_rsp *hdr;
bfead3b2 1166 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1167 struct iscsi_conn *conn = beiscsi_conn->conn;
1168
1169 hdr = (struct iscsi_logout_rsp *)task->hdr;
7bd6e25c 1170 hdr->opcode = ISCSI_OP_LOGOUT_RSP;
6733b39a
JK		 1171 hdr->t2wait = 5;
1172 hdr->t2retain = 0;
73133261
JSJ		 1173 hdr->flags = csol_cqe->i_flags;
1174 hdr->response = csol_cqe->i_resp;
702dc5e8
JK		 1175 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
1176 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1177 csol_cqe->cmd_wnd - 1);
73133261 1178
7bd6e25c
JK		 1179 hdr->dlength[0] = 0;
1180 hdr->dlength[1] = 0;
1181 hdr->dlength[2] = 0;
6733b39a 1182 hdr->hlength = 0;
bfead3b2 1183 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1184 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1185}
1186
1187static void
1188be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1189 struct iscsi_task *task,
1190 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1191{
1192 struct iscsi_tm_rsp *hdr;
1193 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1194 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1195
1196 hdr = (struct iscsi_tm_rsp *)task->hdr;
7bd6e25c 1197 hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
73133261
JSJ		 1198 hdr->flags = csol_cqe->i_flags;
1199 hdr->response = csol_cqe->i_resp;
702dc5e8
JK		 1200 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
1201 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1202 csol_cqe->cmd_wnd - 1);
73133261 1203
bfead3b2 1204 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1205 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1206}
1207
1208static void
1209hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
1210 struct beiscsi_hba *phba, struct sol_cqe *psol)
1211{
1212 struct hwi_wrb_context *pwrb_context;
e1f9d31e 1213 uint16_t wrb_index, cid, cri_index;
6733b39a 1214 struct hwi_controller *phwi_ctrlr;
e1f9d31e 1215 struct wrb_handle *pwrb_handle;
bfead3b2 1216 struct iscsi_task *task;
6733b39a
JK		 1217
1218 phwi_ctrlr = phba->phwi_ctrlr;
2c9dfd36
JK		 1219 if (is_chip_be2_be3r(phba)) {
1220 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
73133261 1221 wrb_idx, psol);
2c9dfd36 1222 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
73133261
JSJ		 1223 cid, psol);
1224 } else {
2c9dfd36 1225 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
73133261 1226 wrb_idx, psol);
2c9dfd36 1227 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
73133261
JSJ		 1228 cid, psol);
1229 }
1230
a7909b39
JK		 1231 cri_index = BE_GET_CRI_FROM_CID(cid);
1232 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
73133261 1233 pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index];
32951dd8 1234 task = pwrb_handle->pio_handle;
4a4a11b9 1235 iscsi_put_task(task);
6733b39a
JK		 1236}
1237
1238static void
1239be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1240 struct iscsi_task *task,
1241 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1242{
1243 struct iscsi_nopin *hdr;
1244 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1245 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1246
1247 hdr = (struct iscsi_nopin *)task->hdr;
73133261
JSJ		 1248 hdr->flags = csol_cqe->i_flags;
1249 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
702dc5e8
JK		 1250 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1251 csol_cqe->cmd_wnd - 1);
73133261 1252
6733b39a 1253 hdr->opcode = ISCSI_OP_NOOP_IN;
bfead3b2 1254 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1255 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1256}
1257
73133261
JSJ		 1258static void adapter_get_sol_cqe(struct beiscsi_hba *phba,
1259 struct sol_cqe *psol,
1260 struct common_sol_cqe *csol_cqe)
1261{
2c9dfd36
JK		 1262 if (is_chip_be2_be3r(phba)) {
1263 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe,
1264 i_exp_cmd_sn, psol);
1265 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe,
1266 i_res_cnt, psol);
1267 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
1268 i_cmd_wnd, psol);
1269 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe,
1270 wrb_index, psol);
1271 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe,
1272 cid, psol);
1273 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe,
1274 hw_sts, psol);
1275 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe,
1276 i_resp, psol);
1277 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe,
1278 i_sts, psol);
1279 csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe,
1280 i_flags, psol);
1281 } else {
73133261
JSJ		 1282 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1283 i_exp_cmd_sn, psol);
1284 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1285 i_res_cnt, psol);
1286 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1287 wrb_index, psol);
1288 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1289 cid, psol);
1290 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1291 hw_sts, psol);
702dc5e8 1292 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2,
73133261
JSJ		 1293 i_cmd_wnd, psol);
1294 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1295 cmd_cmpl, psol))
1296 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1297 i_sts, psol);
1298 else
1299 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1300 i_sts, psol);
1301 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1302 u, psol))
1303 csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW;
1304
1305 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1306 o, psol))
1307 csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW;
73133261
JSJ		 1308 }
1309}
1310
1311
6733b39a
JK		 1312static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
1313 struct beiscsi_hba *phba, struct sol_cqe *psol)
1314{
1315 struct hwi_wrb_context *pwrb_context;
1316 struct wrb_handle *pwrb_handle;
1317 struct iscsi_wrb *pwrb = NULL;
1318 struct hwi_controller *phwi_ctrlr;
1319 struct iscsi_task *task;
bfead3b2 1320 unsigned int type;
6733b39a
JK		 1321 struct iscsi_conn *conn = beiscsi_conn->conn;
1322 struct iscsi_session *session = conn->session;
73133261 1323 struct common_sol_cqe csol_cqe = {0};
a7909b39 1324 uint16_t cri_index = 0;
6733b39a
JK		 1325
1326 phwi_ctrlr = phba->phwi_ctrlr;
73133261
JSJ		 1327
1328 /* Copy the elements to a common structure */
1329 adapter_get_sol_cqe(phba, psol, &csol_cqe);
1330
a7909b39
JK		 1331 cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid);
1332 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
73133261
JSJ		 1333
1334 pwrb_handle = pwrb_context->pwrb_handle_basestd[
1335 csol_cqe.wrb_index];
1336
32951dd8
JK		 1337 task = pwrb_handle->pio_handle;
1338 pwrb = pwrb_handle->pwrb;
73133261 1339 type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type;
32951dd8 1340
659743b0 1341 spin_lock_bh(&session->back_lock);
bfead3b2 1342 switch (type) {
6733b39a
JK		 1343 case HWH_TYPE_IO:
1344 case HWH_TYPE_IO_RD:
1345 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
dafab8e0 1346 ISCSI_OP_NOOP_OUT)
73133261 1347 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
dafab8e0 1348 else
73133261 1349 be_complete_io(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1350 break;
1351
1352 case HWH_TYPE_LOGOUT:
dafab8e0 1353 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
73133261 1354 be_complete_logout(beiscsi_conn, task, &csol_cqe);
dafab8e0 1355 else
73133261 1356 be_complete_tmf(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1357 break;
1358
1359 case HWH_TYPE_LOGIN:
99bc5d55
JSJ		 1360 beiscsi_log(phba, KERN_ERR,
1361 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1362 "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
1363 " hwi_complete_cmd- Solicited path\n");
6733b39a
JK		 1364 break;
1365
6733b39a 1366 case HWH_TYPE_NOP:
73133261 1367 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1368 break;
1369
1370 default:
99bc5d55
JSJ		 1371 beiscsi_log(phba, KERN_WARNING,
1372 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1373 "BM_%d : In hwi_complete_cmd, unknown type = %d"
1374 "wrb_index 0x%x CID 0x%x\n", type,
73133261
JSJ		 1375 csol_cqe.wrb_index,
1376 csol_cqe.cid);
6733b39a
JK		 1377 break;
1378 }
35e66019 1379
659743b0 1380 spin_unlock_bh(&session->back_lock);
6733b39a
JK		 1381}
1382
938f372c
JB		 1383/**
1384 * ASYNC PDUs include
1385 * a. Unsolicited NOP-In (target initiated NOP-In)
1386 * b. ASYNC Messages
1387 * c. Reject PDU
1388 * d. Login response
1389 * These headers arrive unprocessed by the EP firmware.
1390 * iSCSI layer processes them.
1391 */
1392static unsigned int
1393beiscsi_complete_pdu(struct beiscsi_conn *beiscsi_conn,
1394 struct pdu_base *phdr, void *pdata, unsigned int dlen)
6733b39a 1395{
938f372c
JB		 1396 struct beiscsi_hba *phba = beiscsi_conn->phba;
1397 struct iscsi_conn *conn = beiscsi_conn->conn;
1398 struct beiscsi_io_task *io_task;
1399 struct iscsi_hdr *login_hdr;
1400 struct iscsi_task *task;
1401 u8 code;
1402
1403 code = AMAP_GET_BITS(struct amap_pdu_base, opcode, phdr);
1404 switch (code) {
1405 case ISCSI_OP_NOOP_IN:
1406 pdata = NULL;
1407 dlen = 0;
1408 break;
1409 case ISCSI_OP_ASYNC_EVENT:
1410 break;
1411 case ISCSI_OP_REJECT:
1412 WARN_ON(!pdata);
1413 WARN_ON(!(dlen == 48));
1414 beiscsi_log(phba, KERN_ERR,
1415 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1416 "BM_%d : In ISCSI_OP_REJECT\n");
1417 break;
1418 case ISCSI_OP_LOGIN_RSP:
1419 case ISCSI_OP_TEXT_RSP:
1420 task = conn->login_task;
1421 io_task = task->dd_data;
1422 login_hdr = (struct iscsi_hdr *)phdr;
1423 login_hdr->itt = io_task->libiscsi_itt;
1424 break;
1425 default:
1426 beiscsi_log(phba, KERN_WARNING,
1427 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1428 "BM_%d : unrecognized async PDU opcode 0x%x\n",
1429 code);
1430 return 1;
1431 }
1432 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)phdr, pdata, dlen);
1433 return 0;
1434}
1435
1436static inline void
1437beiscsi_hdl_put_handle(struct hd_async_context *pasync_ctx,
1438 struct hd_async_handle *pasync_handle)
1439{
1440 if (pasync_handle->is_header) {
1441 list_add_tail(&pasync_handle->link,
1442 &pasync_ctx->async_header.free_list);
1443 pasync_ctx->async_header.free_entries++;
1444 } else {
1445 list_add_tail(&pasync_handle->link,
1446 &pasync_ctx->async_data.free_list);
1447 pasync_ctx->async_data.free_entries++;
1448 }
6733b39a
JK		 1449}
1450
938f372c
JB		 1451static struct hd_async_handle *
1452beiscsi_hdl_get_handle(struct beiscsi_conn *beiscsi_conn,
1453 struct hd_async_context *pasync_ctx,
1454 struct i_t_dpdu_cqe *pdpdu_cqe)
6733b39a 1455{
938f372c
JB		 1456 struct beiscsi_hba *phba = beiscsi_conn->phba;
1457 struct hd_async_handle *pasync_handle;
6733b39a 1458 struct be_bus_address phys_addr;
938f372c
JB		 1459 u8 final, error = 0;
1460 u16 cid, code, ci;
1461 u32 dpl;
73133261 1462
938f372c
JB		 1463 cid = beiscsi_conn->beiscsi_conn_cid;
1464 /**
1465 * This function is invoked to get the right async_handle structure
1466 * from a given DEF PDU CQ entry.
1467 *
1468 * - index in CQ entry gives the vertical index
1469 * - address in CQ entry is the offset where the DMA last ended
1470 * - final - no more notifications for this PDU
1471 */
2c9dfd36
JK		 1472 if (is_chip_be2_be3r(phba)) {
1473 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
73133261 1474 dpl, pdpdu_cqe);
938f372c 1475 ci = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
73133261 1476 index, pdpdu_cqe);
938f372c
JB		 1477 final = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
1478 final, pdpdu_cqe);
73133261 1479 } else {
2c9dfd36 1480 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
73133261 1481 dpl, pdpdu_cqe);
938f372c 1482 ci = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
73133261 1483 index, pdpdu_cqe);
938f372c
JB		 1484 final = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
1485 final, pdpdu_cqe);
73133261 1486 }
6733b39a 1487
938f372c
JB		 1488 /**
1489 * DB addr Hi/Lo is same for BE and SKH.
1490 * Subtract the dataplacementlength to get to the base.
1491 */
1492 phys_addr.u.a32.address_lo = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
1493 db_addr_lo, pdpdu_cqe);
1494 phys_addr.u.a32.address_lo -= dpl;
1495 phys_addr.u.a32.address_hi = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
1496 db_addr_hi, pdpdu_cqe);
1497
1498 code = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, code, pdpdu_cqe);
1499 switch (code) {
6733b39a 1500 case UNSOL_HDR_NOTIFY:
938f372c 1501 pasync_handle = pasync_ctx->async_entry[ci].header;
6733b39a 1502 break;
938f372c
JB		 1503 case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
1504 error = 1;
6733b39a 1505 case UNSOL_DATA_NOTIFY:
938f372c 1506 pasync_handle = pasync_ctx->async_entry[ci].data;
6733b39a 1507 break;
938f372c 1508 /* called only for above codes */
6733b39a 1509 default:
938f372c
JB		 1510 pasync_handle = NULL;
1511 break;
6733b39a
JK		 1512 }
1513
938f372c
JB		 1514 if (!pasync_handle) {
1515 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI,
1516 "BM_%d : cid %d async PDU handle not found - code %d ci %d addr %llx\n",
1517 cid, code, ci, phys_addr.u.a64.address);
1518 return pasync_handle;
6733b39a
JK		 1519 }
1520
938f372c
JB		 1521 if (pasync_handle->pa.u.a64.address != phys_addr.u.a64.address ||
1522 pasync_handle->index != ci) {
1523 /* driver bug - if ci does not match async handle index */
1524 error = 1;
1525 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI,
1526 "BM_%d : cid %u async PDU handle mismatch - addr in %cQE %llx at %u:addr in CQE %llx ci %u\n",
1527 cid, pasync_handle->is_header ? 'H' : 'D',
1528 pasync_handle->pa.u.a64.address,
1529 pasync_handle->index,
1530 phys_addr.u.a64.address, ci);
1531 /* FW has stale address - attempt continuing by dropping */
1532 }
6733b39a 1533
938f372c
JB		 1534 /**
1535 * Each CID is associated with unique CRI.
1536 * ASYNC_CRI_FROM_CID mapping and CRI_FROM_CID are totaly different.
1537 **/
1538 pasync_handle->cri = BE_GET_ASYNC_CRI_FROM_CID(cid);
1539 pasync_handle->is_final = final;
73133261 1540 pasync_handle->buffer_len = dpl;
938f372c
JB		 1541 /* empty the slot */
1542 if (pasync_handle->is_header)
1543 pasync_ctx->async_entry[ci].header = NULL;
1544 else
1545 pasync_ctx->async_entry[ci].data = NULL;
6733b39a 1546
938f372c
JB		 1547 /**
1548 * DEF PDU header and data buffers with errors should be simply
1549 * dropped as there are no consumers for it.
1550 */
1551 if (error) {
1552 beiscsi_hdl_put_handle(pasync_ctx, pasync_handle);
1553 pasync_handle = NULL;
1554 }
6733b39a
JK		 1555 return pasync_handle;
1556}
1557
938f372c
JB		 1558static void
1559beiscsi_hdl_purge_handles(struct beiscsi_hba *phba,
1560 struct hd_async_context *pasync_ctx,
1561 u16 cri)
6733b39a 1562{
938f372c
JB		 1563 struct hd_async_handle *pasync_handle, *tmp_handle;
1564 struct list_head *plist;
6733b39a 1565
938f372c
JB		 1566 plist = &pasync_ctx->async_entry[cri].wq.list;
1567 list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
1568 list_del(&pasync_handle->link);
1569 beiscsi_hdl_put_handle(pasync_ctx, pasync_handle);
6733b39a
JK		 1570 }
1571
938f372c
JB		 1572 INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wq.list);
1573 pasync_ctx->async_entry[cri].wq.hdr_len = 0;
1574 pasync_ctx->async_entry[cri].wq.bytes_received = 0;
1575 pasync_ctx->async_entry[cri].wq.bytes_needed = 0;
6733b39a
JK		 1576}
1577
938f372c
JB		 1578static unsigned int
1579beiscsi_hdl_fwd_pdu(struct beiscsi_conn *beiscsi_conn,
1580 struct hd_async_context *pasync_ctx,
1581 u16 cri)
6733b39a 1582{
938f372c
JB		 1583 struct iscsi_session *session = beiscsi_conn->conn->session;
1584 struct hd_async_handle *pasync_handle, *plast_handle;
1585 struct beiscsi_hba *phba = beiscsi_conn->phba;
1586 void *phdr = NULL, *pdata = NULL;
1587 u32 dlen = 0, status = 0;
6733b39a 1588 struct list_head *plist;
6733b39a 1589
938f372c
JB		 1590 plist = &pasync_ctx->async_entry[cri].wq.list;
1591 plast_handle = NULL;
1592 list_for_each_entry(pasync_handle, plist, link) {
1593 plast_handle = pasync_handle;
1594 /* get the header, the first entry */
1595 if (!phdr) {
1596 phdr = pasync_handle->pbuffer;
1597 continue;
6733b39a 1598 }
938f372c
JB		 1599 /* use first buffer to collect all the data */
1600 if (!pdata) {
1601 pdata = pasync_handle->pbuffer;
1602 dlen = pasync_handle->buffer_len;
1603 continue;
1604 }
1605 memcpy(pdata + dlen, pasync_handle->pbuffer,
1606 pasync_handle->buffer_len);
1607 dlen += pasync_handle->buffer_len;
6733b39a
JK		 1608 }
1609
938f372c
JB		 1610 if (!plast_handle->is_final) {
1611 /* last handle should have final PDU notification from FW */
1612 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI,
1613 "BM_%d : cid %u %p fwd async PDU with last handle missing - HL%u:DN%u:DR%u\n",
1614 beiscsi_conn->beiscsi_conn_cid, plast_handle,
1615 pasync_ctx->async_entry[cri].wq.hdr_len,
1616 pasync_ctx->async_entry[cri].wq.bytes_needed,
1617 pasync_ctx->async_entry[cri].wq.bytes_received);
1618 }
1619 spin_lock_bh(&session->back_lock);
1620 status = beiscsi_complete_pdu(beiscsi_conn, phdr, pdata, dlen);
1621 spin_unlock_bh(&session->back_lock);
1622 beiscsi_hdl_purge_handles(phba, pasync_ctx, cri);
1623 return status;
6733b39a
JK		 1624}
1625
938f372c
JB		 1626static unsigned int
1627beiscsi_hdl_gather_pdu(struct beiscsi_conn *beiscsi_conn,
1628 struct hd_async_context *pasync_ctx,
1629 struct hd_async_handle *pasync_handle)
6733b39a 1630{
938f372c
JB		 1631 unsigned int bytes_needed = 0, status = 0;
1632 u16 cri = pasync_handle->cri;
1633 struct cri_wait_queue *wq;
1634 struct beiscsi_hba *phba;
1635 struct pdu_base *ppdu;
1636 char *err = "";
6733b39a 1637
938f372c
JB		 1638 phba = beiscsi_conn->phba;
1639 wq = &pasync_ctx->async_entry[cri].wq;
1640 if (pasync_handle->is_header) {
1641 /* check if PDU hdr is rcv'd when old hdr not completed */
1642 if (wq->hdr_len) {
1643 err = "incomplete";
1644 goto drop_pdu;
1645 }
1646 ppdu = pasync_handle->pbuffer;
1647 bytes_needed = AMAP_GET_BITS(struct amap_pdu_base,
1648 data_len_hi, ppdu);
1649 bytes_needed <<= 16;
1650 bytes_needed |= be16_to_cpu(AMAP_GET_BITS(struct amap_pdu_base,
1651 data_len_lo, ppdu));
1652 wq->hdr_len = pasync_handle->buffer_len;
1653 wq->bytes_received = 0;
1654 wq->bytes_needed = bytes_needed;
1655 list_add_tail(&pasync_handle->link, &wq->list);
1656 if (!bytes_needed)
1657 status = beiscsi_hdl_fwd_pdu(beiscsi_conn,
1658 pasync_ctx, cri);
1659 } else {
1660 /* check if data received has header and is needed */
1661 if (!wq->hdr_len || !wq->bytes_needed) {
1662 err = "header less";
1663 goto drop_pdu;
1664 }
1665 wq->bytes_received += pasync_handle->buffer_len;
1666 /* Something got overwritten? Better catch it here. */
1667 if (wq->bytes_received > wq->bytes_needed) {
1668 err = "overflow";
1669 goto drop_pdu;
1670 }
1671 list_add_tail(&pasync_handle->link, &wq->list);
1672 if (wq->bytes_received == wq->bytes_needed)
1673 status = beiscsi_hdl_fwd_pdu(beiscsi_conn,
1674 pasync_ctx, cri);
1675 }
1676 return status;
6733b39a 1677
938f372c
JB		 1678drop_pdu:
1679 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI,
1680 "BM_%d : cid %u async PDU %s - def-%c:HL%u:DN%u:DR%u\n",
1681 beiscsi_conn->beiscsi_conn_cid, err,
1682 pasync_handle->is_header ? 'H' : 'D',
1683 wq->hdr_len, wq->bytes_needed,
1684 pasync_handle->buffer_len);
1685 /* discard this handle */
1686 beiscsi_hdl_put_handle(pasync_ctx, pasync_handle);
1687 /* free all the other handles in cri_wait_queue */
1688 beiscsi_hdl_purge_handles(phba, pasync_ctx, cri);
1689 /* try continuing */
1690 return status;
6733b39a
JK		 1691}
1692
938f372c
JB		 1693static void
1694beiscsi_hdq_post_handles(struct beiscsi_hba *phba,
1695 u8 header, u8 ulp_num)
6733b39a 1696{
938f372c
JB		 1697 struct hd_async_handle *pasync_handle, *tmp, **slot;
1698 struct hd_async_context *pasync_ctx;
6733b39a 1699 struct hwi_controller *phwi_ctrlr;
938f372c 1700 struct list_head *hfree_list;
6733b39a 1701 struct phys_addr *pasync_sge;
938f372c
JB		 1702 u32 ring_id, doorbell = 0;
1703 u16 index, num_entries;
1704 u32 doorbell_offset;
1705 u16 prod = 0, cons;
6733b39a
JK		 1706
1707 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833 1708 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num);
dc63aac6 1709 num_entries = pasync_ctx->num_entries;
938f372c
JB		 1710 if (header) {
1711 cons = pasync_ctx->async_header.free_entries;
1712 hfree_list = &pasync_ctx->async_header.free_list;
8a86e833
JK		 1713 ring_id = phwi_ctrlr->default_pdu_hdr[ulp_num].id;
1714 doorbell_offset = phwi_ctrlr->default_pdu_hdr[ulp_num].
938f372c 1715 doorbell_offset;
6733b39a 1716 } else {
938f372c
JB		 1717 cons = pasync_ctx->async_data.free_entries;
1718 hfree_list = &pasync_ctx->async_data.free_list;
8a86e833
JK		 1719 ring_id = phwi_ctrlr->default_pdu_data[ulp_num].id;
1720 doorbell_offset = phwi_ctrlr->default_pdu_data[ulp_num].
938f372c 1721 doorbell_offset;
6733b39a 1722 }
938f372c
JB		 1723 /* number of entries posted must be in multiples of 8 */
1724 if (cons % 8)
1725 return;
6733b39a 1726
938f372c
JB		 1727 list_for_each_entry_safe(pasync_handle, tmp, hfree_list, link) {
1728 list_del_init(&pasync_handle->link);
1729 pasync_handle->is_final = 0;
1730 pasync_handle->buffer_len = 0;
6733b39a 1731
938f372c
JB		 1732 /* handles can be consumed out of order, use index in handle */
1733 index = pasync_handle->index;
1734 WARN_ON(pasync_handle->is_header != header);
1735 if (header)
1736 slot = &pasync_ctx->async_entry[index].header;
1737 else
1738 slot = &pasync_ctx->async_entry[index].data;
1739 /**
1740 * The slot just tracks handle's hold and release, so
1741 * overwriting at the same index won't do any harm but
1742 * needs to be caught.
1743 */
1744 if (*slot != NULL) {
1745 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI,
1746 "BM_%d : async PDU %s slot at %u not empty\n",
1747 header ? "header" : "data", index);
6733b39a 1748 }
938f372c
JB		 1749 /**
1750 * We use same freed index as in completion to post so this
1751 * operation is not required for refills. Its required only
1752 * for ring creation.
1753 */
1754 if (header)
1755 pasync_sge = pasync_ctx->async_header.ring_base;
1756 else
1757 pasync_sge = pasync_ctx->async_data.ring_base;
1758 pasync_sge += index;
1759 /* if its a refill then address is same; hi is lo */
1760 WARN_ON(pasync_sge->hi &&
1761 pasync_sge->hi != pasync_handle->pa.u.a32.address_lo);
1762 WARN_ON(pasync_sge->lo &&
1763 pasync_sge->lo != pasync_handle->pa.u.a32.address_hi);
1764 pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
1765 pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
1766
1767 *slot = pasync_handle;
1768 if (++prod == cons)
1769 break;
6733b39a 1770 }
938f372c
JB		 1771 if (header)
1772 pasync_ctx->async_header.free_entries -= prod;
1773 else
1774 pasync_ctx->async_data.free_entries -= prod;
6733b39a 1775
938f372c
JB		 1776 doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
1777 doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
1778 doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
1779 doorbell |= (prod & DB_DEF_PDU_CQPROC_MASK) << DB_DEF_PDU_CQPROC_SHIFT;
1780 iowrite32(doorbell, phba->db_va + doorbell_offset);
6733b39a
JK		 1781}
1782
938f372c
JB		 1783static void
1784beiscsi_hdq_process_compl(struct beiscsi_conn *beiscsi_conn,
1785 struct i_t_dpdu_cqe *pdpdu_cqe)
6733b39a 1786{
938f372c
JB		 1787 struct beiscsi_hba *phba = beiscsi_conn->phba;
1788 struct hd_async_handle *pasync_handle = NULL;
1789 struct hd_async_context *pasync_ctx;
6733b39a 1790 struct hwi_controller *phwi_ctrlr;
938f372c
JB		 1791 u16 cid_cri;
1792 u8 ulp_num;
6733b39a
JK		 1793
1794 phwi_ctrlr = phba->phwi_ctrlr;
938f372c
JB		 1795 cid_cri = BE_GET_CRI_FROM_CID(beiscsi_conn->beiscsi_conn_cid);
1796 ulp_num = BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cid_cri);
1797 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num);
1798 pasync_handle = beiscsi_hdl_get_handle(beiscsi_conn, pasync_ctx,
1799 pdpdu_cqe);
1800 if (!pasync_handle)
1801 return;
99bc5d55 1802
938f372c
JB		 1803 beiscsi_hdl_gather_pdu(beiscsi_conn, pasync_ctx, pasync_handle);
1804 beiscsi_hdq_post_handles(phba, pasync_handle->is_header, ulp_num);
6733b39a
JK		 1805}
1806
2e4e8f65 1807void beiscsi_process_mcc_cq(struct beiscsi_hba *phba)
756d29c8
JK		 1808{
1809 struct be_queue_info *mcc_cq;
1810 struct be_mcc_compl *mcc_compl;
1811 unsigned int num_processed = 0;
1812
1813 mcc_cq = &phba->ctrl.mcc_obj.cq;
1814 mcc_compl = queue_tail_node(mcc_cq);
1815 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
1816 while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
9122e991
JB		 1817 if (beiscsi_hba_in_error(phba))
1818 return;
1819
756d29c8
JK		 1820 if (num_processed >= 32) {
1821 hwi_ring_cq_db(phba, mcc_cq->id,
1094cf68 1822 num_processed, 0);
756d29c8
JK		 1823 num_processed = 0;
1824 }
1825 if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
53aefe25 1826 beiscsi_process_async_event(phba, mcc_compl);
756d29c8 1827 } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
2e4e8f65 1828 beiscsi_process_mcc_compl(&phba->ctrl, mcc_compl);
756d29c8
JK		 1829 }
1830
1831 mcc_compl->flags = 0;
1832 queue_tail_inc(mcc_cq);
1833 mcc_compl = queue_tail_node(mcc_cq);
1834 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
1835 num_processed++;
1836 }
1837
1838 if (num_processed > 0)
1094cf68 1839 hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1);
756d29c8 1840}
bfead3b2 1841
a3095016
JB		 1842static void beiscsi_mcc_work(struct work_struct *work)
1843{
1844 struct be_eq_obj *pbe_eq;
1845 struct beiscsi_hba *phba;
1846
1847 pbe_eq = container_of(work, struct be_eq_obj, mcc_work);
1848 phba = pbe_eq->phba;
1849 beiscsi_process_mcc_cq(phba);
1850 /* rearm EQ for further interrupts */
9122e991
JB		 1851 if (!beiscsi_hba_in_error(phba))
1852 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
a3095016
JB		 1853}
1854
6763daae
JSJ		 1855/**
1856 * beiscsi_process_cq()- Process the Completion Queue
1857 * @pbe_eq: Event Q on which the Completion has come
1094cf68 1858 * @budget: Max number of events to processed
6763daae
JSJ		 1859 *
1860 * return
1861 * Number of Completion Entries processed.
1862 **/
1094cf68 1863unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget)
6733b39a 1864{
6733b39a
JK		 1865 struct be_queue_info *cq;
1866 struct sol_cqe *sol;
1867 struct dmsg_cqe *dmsg;
1094cf68 1868 unsigned int total = 0;
6733b39a 1869 unsigned int num_processed = 0;
0a513dd8 1870 unsigned short code = 0, cid = 0;
a7909b39 1871 uint16_t cri_index = 0;
6733b39a 1872 struct beiscsi_conn *beiscsi_conn;
c2462288
JK		 1873 struct beiscsi_endpoint *beiscsi_ep;
1874 struct iscsi_endpoint *ep;
bfead3b2 1875 struct beiscsi_hba *phba;
6733b39a 1876
bfead3b2 1877 cq = pbe_eq->cq;
6733b39a 1878 sol = queue_tail_node(cq);
bfead3b2 1879 phba = pbe_eq->phba;
6733b39a
JK		 1880
1881 while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
1882 CQE_VALID_MASK) {
9122e991
JB		 1883 if (beiscsi_hba_in_error(phba))
1884 return 0;
1885
6733b39a
JK		 1886 be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
1887
73133261
JSJ		 1888 code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
1889 32] & CQE_CODE_MASK);
1890
1891 /* Get the CID */
2c9dfd36
JK		 1892 if (is_chip_be2_be3r(phba)) {
1893 cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol);
1894 } else {
73133261
JSJ		 1895 if ((code == DRIVERMSG_NOTIFY) ||
1896 (code == UNSOL_HDR_NOTIFY) ||
1897 (code == UNSOL_DATA_NOTIFY))
1898 cid = AMAP_GET_BITS(
1899 struct amap_i_t_dpdu_cqe_v2,
1900 cid, sol);
1901 else
1902 cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1903 cid, sol);
2c9dfd36 1904 }
32951dd8 1905
a7909b39
JK		 1906 cri_index = BE_GET_CRI_FROM_CID(cid);
1907 ep = phba->ep_array[cri_index];
b7ab35b1
JK		 1908
1909 if (ep == NULL) {
1910 /* connection has already been freed
1911 * just move on to next one
1912 */
1913 beiscsi_log(phba, KERN_WARNING,
1914 BEISCSI_LOG_INIT,
1915 "BM_%d : proc cqe of disconn ep: cid %d\n",
1916 cid);
1917 goto proc_next_cqe;
1918 }
1919
c2462288
JK		 1920 beiscsi_ep = ep->dd_data;
1921 beiscsi_conn = beiscsi_ep->conn;
756d29c8 1922
1094cf68
JB		 1923 /* replenish cq */
1924 if (num_processed == 32) {
1925 hwi_ring_cq_db(phba, cq->id, 32, 0);
6733b39a
JK		 1926 num_processed = 0;
1927 }
1094cf68 1928 total++;
6733b39a 1929
0a513dd8 1930 switch (code) {
6733b39a
JK		 1931 case SOL_CMD_COMPLETE:
1932 hwi_complete_cmd(beiscsi_conn, phba, sol);
1933 break;
1934 case DRIVERMSG_NOTIFY:
99bc5d55
JSJ		 1935 beiscsi_log(phba, KERN_INFO,
1936 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 1937 "BM_%d : Received %s[%d] on CID : %d\n",
1938 cqe_desc[code], code, cid);
99bc5d55 1939
6733b39a
JK		 1940 dmsg = (struct dmsg_cqe *)sol;
1941 hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
1942 break;
1943 case UNSOL_HDR_NOTIFY:
99bc5d55
JSJ		 1944 beiscsi_log(phba, KERN_INFO,
1945 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 1946 "BM_%d : Received %s[%d] on CID : %d\n",
1947 cqe_desc[code], code, cid);
99bc5d55 1948
8f09a3b9 1949 spin_lock_bh(&phba->async_pdu_lock);
938f372c
JB		 1950 beiscsi_hdq_process_compl(beiscsi_conn,
1951 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 1952 spin_unlock_bh(&phba->async_pdu_lock);
bfead3b2 1953 break;
6733b39a 1954 case UNSOL_DATA_NOTIFY:
99bc5d55
JSJ		 1955 beiscsi_log(phba, KERN_INFO,
1956 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
6763daae
JSJ		 1957 "BM_%d : Received %s[%d] on CID : %d\n",
1958 cqe_desc[code], code, cid);
99bc5d55 1959
8f09a3b9 1960 spin_lock_bh(&phba->async_pdu_lock);
938f372c
JB		 1961 beiscsi_hdq_process_compl(beiscsi_conn,
1962 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 1963 spin_unlock_bh(&phba->async_pdu_lock);
6733b39a
JK		 1964 break;
1965 case CXN_INVALIDATE_INDEX_NOTIFY:
1966 case CMD_INVALIDATED_NOTIFY:
1967 case CXN_INVALIDATE_NOTIFY:
99bc5d55
JSJ		 1968 beiscsi_log(phba, KERN_ERR,
1969 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 1970 "BM_%d : Ignoring %s[%d] on CID : %d\n",
1971 cqe_desc[code], code, cid);
6733b39a 1972 break;
1094cf68 1973 case CXN_KILLED_HDR_DIGEST_ERR:
6733b39a 1974 case SOL_CMD_KILLED_DATA_DIGEST_ERR:
1094cf68
JB		 1975 beiscsi_log(phba, KERN_ERR,
1976 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1977 "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
1978 cqe_desc[code], code, cid);
1979 break;
6733b39a
JK		 1980 case CMD_KILLED_INVALID_STATSN_RCVD:
1981 case CMD_KILLED_INVALID_R2T_RCVD:
1982 case CMD_CXN_KILLED_LUN_INVALID:
1983 case CMD_CXN_KILLED_ICD_INVALID:
1984 case CMD_CXN_KILLED_ITT_INVALID:
1985 case CMD_CXN_KILLED_SEQ_OUTOFORDER:
1986 case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
99bc5d55
JSJ		 1987 beiscsi_log(phba, KERN_ERR,
1988 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
6763daae
JSJ		 1989 "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
1990 cqe_desc[code], code, cid);
6733b39a
JK		 1991 break;
1992 case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
99bc5d55
JSJ		 1993 beiscsi_log(phba, KERN_ERR,
1994 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 1995 "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
1996 cqe_desc[code], code, cid);
8f09a3b9 1997 spin_lock_bh(&phba->async_pdu_lock);
938f372c
JB		 1998 /* driver consumes the entry and drops the contents */
1999 beiscsi_hdq_process_compl(beiscsi_conn,
2000 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 2001 spin_unlock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2002 break;
2003 case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
2004 case CXN_KILLED_BURST_LEN_MISMATCH:
2005 case CXN_KILLED_AHS_RCVD:
6733b39a
JK		 2006 case CXN_KILLED_UNKNOWN_HDR:
2007 case CXN_KILLED_STALE_ITT_TTT_RCVD:
2008 case CXN_KILLED_INVALID_ITT_TTT_RCVD:
2009 case CXN_KILLED_TIMED_OUT:
2010 case CXN_KILLED_FIN_RCVD:
6763daae
JSJ		 2011 case CXN_KILLED_RST_SENT:
2012 case CXN_KILLED_RST_RCVD:
6733b39a
JK		 2013 case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
2014 case CXN_KILLED_BAD_WRB_INDEX_ERROR:
2015 case CXN_KILLED_OVER_RUN_RESIDUAL:
2016 case CXN_KILLED_UNDER_RUN_RESIDUAL:
2017 case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
99bc5d55
JSJ		 2018 beiscsi_log(phba, KERN_ERR,
2019 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2020 "BM_%d : Event %s[%d] received on CID : %d\n",
2021 cqe_desc[code], code, cid);
0a513dd8
JSJ		 2022 if (beiscsi_conn)
2023 iscsi_conn_failure(beiscsi_conn->conn,
2024 ISCSI_ERR_CONN_FAILED);
6733b39a
JK		 2025 break;
2026 default:
99bc5d55
JSJ		 2027 beiscsi_log(phba, KERN_ERR,
2028 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2029 "BM_%d : Invalid CQE Event Received Code : %d"
2030 "CID 0x%x...\n",
0a513dd8 2031 code, cid);
6733b39a
JK		 2032 break;
2033 }
2034
b7ab35b1 2035proc_next_cqe:
6733b39a
JK		 2036 AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
2037 queue_tail_inc(cq);
2038 sol = queue_tail_node(cq);
2039 num_processed++;
1094cf68
JB		 2040 if (total == budget)
2041 break;
6733b39a
JK		 2042 }
2043
1094cf68
JB		 2044 hwi_ring_cq_db(phba, cq->id, num_processed, 1);
2045 return total;
6733b39a
JK		 2046}
2047
511cbce2 2048static int be_iopoll(struct irq_poll *iop, int budget)
6733b39a 2049{
a3095016 2050 unsigned int ret, io_events;
6733b39a 2051 struct beiscsi_hba *phba;
bfead3b2 2052 struct be_eq_obj *pbe_eq;
1094cf68
JB		 2053 struct be_eq_entry *eqe = NULL;
2054 struct be_queue_info *eq;
6733b39a 2055
bfead3b2 2056 pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
1094cf68 2057 phba = pbe_eq->phba;
9122e991
JB		 2058 if (beiscsi_hba_in_error(phba)) {
2059 irq_poll_complete(iop);
2060 return 0;
2061 }
2062
2063 io_events = 0;
1094cf68
JB		 2064 eq = &pbe_eq->q;
2065 eqe = queue_tail_node(eq);
1094cf68
JB		 2066 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] &
2067 EQE_VALID_MASK) {
2068 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
2069 queue_tail_inc(eq);
2070 eqe = queue_tail_node(eq);
a3095016 2071 io_events++;
1094cf68 2072 }
a3095016 2073 hwi_ring_eq_db(phba, eq->id, 1, io_events, 0, 1);
1094cf68
JB		 2074
2075 ret = beiscsi_process_cq(pbe_eq, budget);
73af08e1 2076 pbe_eq->cq_count += ret;
6733b39a 2077 if (ret < budget) {
511cbce2 2078 irq_poll_complete(iop);
99bc5d55
JSJ		 2079 beiscsi_log(phba, KERN_INFO,
2080 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1094cf68
JB		 2081 "BM_%d : rearm pbe_eq->q.id =%d ret %d\n",
2082 pbe_eq->q.id, ret);
9122e991
JB		 2083 if (!beiscsi_hba_in_error(phba))
2084 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
6733b39a
JK		 2085 }
2086 return ret;
2087}
2088
09a1093a
JSJ		 2089static void
2090hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg,
2091 unsigned int num_sg, struct beiscsi_io_task *io_task)
2092{
2093 struct iscsi_sge *psgl;
2094 unsigned int sg_len, index;
2095 unsigned int sge_len = 0;
2096 unsigned long long addr;
2097 struct scatterlist *l_sg;
2098 unsigned int offset;
2099
2100 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb,
2101 io_task->bhs_pa.u.a32.address_lo);
2102 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb,
2103 io_task->bhs_pa.u.a32.address_hi);
2104
2105 l_sg = sg;
2106 for (index = 0; (index < num_sg) && (index < 2); index++,
2107 sg = sg_next(sg)) {
2108 if (index == 0) {
2109 sg_len = sg_dma_len(sg);
2110 addr = (u64) sg_dma_address(sg);
2111 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2112 sge0_addr_lo, pwrb,
2113 lower_32_bits(addr));
2114 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2115 sge0_addr_hi, pwrb,
2116 upper_32_bits(addr));
2117 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2118 sge0_len, pwrb,
2119 sg_len);
2120 sge_len = sg_len;
2121 } else {
2122 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset,
2123 pwrb, sge_len);
2124 sg_len = sg_dma_len(sg);
2125 addr = (u64) sg_dma_address(sg);
2126 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2127 sge1_addr_lo, pwrb,
2128 lower_32_bits(addr));
2129 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2130 sge1_addr_hi, pwrb,
2131 upper_32_bits(addr));
2132 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2133 sge1_len, pwrb,
2134 sg_len);
2135 }
2136 }
2137 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2138 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2139
2140 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2141
2142 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2143 io_task->bhs_pa.u.a32.address_hi);
2144 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2145 io_task->bhs_pa.u.a32.address_lo);
2146
2147 if (num_sg == 1) {
2148 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2149 1);
2150 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2151 0);
2152 } else if (num_sg == 2) {
2153 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2154 0);
2155 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2156 1);
2157 } else {
2158 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2159 0);
2160 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2161 0);
2162 }
2163
2164 sg = l_sg;
2165 psgl++;
2166 psgl++;
2167 offset = 0;
2168 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
2169 sg_len = sg_dma_len(sg);
2170 addr = (u64) sg_dma_address(sg);
2171 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2172 lower_32_bits(addr));
2173 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2174 upper_32_bits(addr));
2175 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2176 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2177 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2178 offset += sg_len;
2179 }
2180 psgl--;
2181 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2182}
2183
6733b39a
JK		 2184static void
2185hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
2186 unsigned int num_sg, struct beiscsi_io_task *io_task)
2187{
2188 struct iscsi_sge *psgl;
58ff4bd0 2189 unsigned int sg_len, index;
6733b39a
JK		 2190 unsigned int sge_len = 0;
2191 unsigned long long addr;
2192 struct scatterlist *l_sg;
2193 unsigned int offset;
2194
2195 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2196 io_task->bhs_pa.u.a32.address_lo);
2197 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2198 io_task->bhs_pa.u.a32.address_hi);
2199
2200 l_sg = sg;
48bd86cf
JK		 2201 for (index = 0; (index < num_sg) && (index < 2); index++,
2202 sg = sg_next(sg)) {
6733b39a
JK		 2203 if (index == 0) {
2204 sg_len = sg_dma_len(sg);
2205 addr = (u64) sg_dma_address(sg);
2206 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
457ff3b7 2207 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2208 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
457ff3b7 2209 ((u32)(addr >> 32)));
6733b39a
JK		 2210 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2211 sg_len);
2212 sge_len = sg_len;
6733b39a 2213 } else {
6733b39a
JK		 2214 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
2215 pwrb, sge_len);
2216 sg_len = sg_dma_len(sg);
2217 addr = (u64) sg_dma_address(sg);
2218 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
457ff3b7 2219 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2220 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
457ff3b7 2221 ((u32)(addr >> 32)));
6733b39a
JK		 2222 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
2223 sg_len);
2224 }
2225 }
2226 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2227 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2228
2229 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2230
2231 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2232 io_task->bhs_pa.u.a32.address_hi);
2233 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2234 io_task->bhs_pa.u.a32.address_lo);
2235
caf818f1
JK		 2236 if (num_sg == 1) {
2237 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2238 1);
2239 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2240 0);
2241 } else if (num_sg == 2) {
2242 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2243 0);
2244 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2245 1);
2246 } else {
2247 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2248 0);
2249 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2250 0);
2251 }
6733b39a
JK		 2252 sg = l_sg;
2253 psgl++;
2254 psgl++;
2255 offset = 0;
48bd86cf 2256 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
6733b39a
JK		 2257 sg_len = sg_dma_len(sg);
2258 addr = (u64) sg_dma_address(sg);
2259 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2260 (addr & 0xFFFFFFFF));
2261 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2262 (addr >> 32));
2263 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2264 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2265 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2266 offset += sg_len;
2267 }
2268 psgl--;
2269 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2270}
2271
d629c471
JSJ		 2272/**
2273 * hwi_write_buffer()- Populate the WRB with task info
2274 * @pwrb: ptr to the WRB entry
2275 * @task: iscsi task which is to be executed
2276 **/
e0493627 2277static int hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
6733b39a
JK		 2278{
2279 struct iscsi_sge *psgl;
6733b39a
JK		 2280 struct beiscsi_io_task *io_task = task->dd_data;
2281 struct beiscsi_conn *beiscsi_conn = io_task->conn;
2282 struct beiscsi_hba *phba = beiscsi_conn->phba;
09a1093a 2283 uint8_t dsp_value = 0;
6733b39a
JK		 2284
2285 io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
2286 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2287 io_task->bhs_pa.u.a32.address_lo);
2288 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2289 io_task->bhs_pa.u.a32.address_hi);
2290
2291 if (task->data) {
09a1093a
JSJ		 2292
2293 /* Check for the data_count */
2294 dsp_value = (task->data_count) ? 1 : 0;
2295
2c9dfd36
JK		 2296 if (is_chip_be2_be3r(phba))
2297 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp,
09a1093a
JSJ		 2298 pwrb, dsp_value);
2299 else
2c9dfd36 2300 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp,
09a1093a
JSJ		 2301 pwrb, dsp_value);
2302
2303 /* Map addr only if there is data_count */
2304 if (dsp_value) {
d629c471
JSJ		 2305 io_task->mtask_addr = pci_map_single(phba->pcidev,
2306 task->data,
2307 task->data_count,
2308 PCI_DMA_TODEVICE);
e0493627
AK		 2309 if (pci_dma_mapping_error(phba->pcidev,
2310 io_task->mtask_addr))
2311 return -ENOMEM;
d629c471 2312 io_task->mtask_data_count = task->data_count;
09a1093a 2313 } else
d629c471 2314 io_task->mtask_addr = 0;
09a1093a 2315
6733b39a 2316 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
d629c471 2317 lower_32_bits(io_task->mtask_addr));
6733b39a 2318 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
d629c471 2319 upper_32_bits(io_task->mtask_addr));
6733b39a
JK		 2320 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2321 task->data_count);
2322
2323 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
2324 } else {
2325 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
d629c471 2326 io_task->mtask_addr = 0;
6733b39a
JK		 2327 }
2328
2329 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2330
2331 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
2332
2333 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2334 io_task->bhs_pa.u.a32.address_hi);
2335 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2336 io_task->bhs_pa.u.a32.address_lo);
2337 if (task->data) {
2338 psgl++;
2339 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
2340 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
2341 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
2342 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
2343 AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
2344 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2345
2346 psgl++;
2347 if (task->data) {
2348 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
d629c471 2349 lower_32_bits(io_task->mtask_addr));
6733b39a 2350 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
d629c471 2351 upper_32_bits(io_task->mtask_addr));
6733b39a
JK		 2352 }
2353 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
2354 }
2355 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
e0493627 2356 return 0;
6733b39a
JK		 2357}
2358
843ae752
JK		 2359/**
2360 * beiscsi_find_mem_req()- Find mem needed
2361 * @phba: ptr to HBA struct
2362 **/
6733b39a
JK		 2363static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
2364{
8a86e833 2365 uint8_t mem_descr_index, ulp_num;
bfead3b2 2366 unsigned int num_cq_pages, num_async_pdu_buf_pages;
6733b39a
JK		 2367 unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
2368 unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
2369
2370 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
2371 sizeof(struct sol_cqe));
6733b39a
JK		 2372
2373 phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
2374
2375 phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
2376 BE_ISCSI_PDU_HEADER_SIZE;
2377 phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
2378 sizeof(struct hwi_context_memory);
2379
6733b39a
JK		 2380
2381 phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
2382 * (phba->params.wrbs_per_cxn)
2383 * phba->params.cxns_per_ctrl;
2384 wrb_sz_per_cxn = sizeof(struct wrb_handle) *
2385 (phba->params.wrbs_per_cxn);
2386 phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
2387 phba->params.cxns_per_ctrl);
2388
2389 phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
2390 phba->params.icds_per_ctrl;
2391 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
2392 phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
8a86e833
JK		 2393 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
2394 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 2395
8a86e833
JK		 2396 num_async_pdu_buf_sgl_pages =
2397 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2398 phba, ulp_num) *
2399 sizeof(struct phys_addr));
2400
2401 num_async_pdu_buf_pages =
2402 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2403 phba, ulp_num) *
2404 phba->params.defpdu_hdr_sz);
2405
2406 num_async_pdu_data_pages =
2407 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2408 phba, ulp_num) *
2409 phba->params.defpdu_data_sz);
2410
2411 num_async_pdu_data_sgl_pages =
2412 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2413 phba, ulp_num) *
2414 sizeof(struct phys_addr));
2415
a129d92f
JK		 2416 mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 +
2417 (ulp_num * MEM_DESCR_OFFSET));
2418 phba->mem_req[mem_descr_index] =
2419 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2420 BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
2421
8a86e833
JK		 2422 mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
2423 (ulp_num * MEM_DESCR_OFFSET));
2424 phba->mem_req[mem_descr_index] =
2425 num_async_pdu_buf_pages *
2426 PAGE_SIZE;
2427
2428 mem_descr_index = (HWI_MEM_ASYNC_DATA_BUF_ULP0 +
2429 (ulp_num * MEM_DESCR_OFFSET));
2430 phba->mem_req[mem_descr_index] =
2431 num_async_pdu_data_pages *
2432 PAGE_SIZE;
2433
2434 mem_descr_index = (HWI_MEM_ASYNC_HEADER_RING_ULP0 +
2435 (ulp_num * MEM_DESCR_OFFSET));
2436 phba->mem_req[mem_descr_index] =
2437 num_async_pdu_buf_sgl_pages *
2438 PAGE_SIZE;
2439
2440 mem_descr_index = (HWI_MEM_ASYNC_DATA_RING_ULP0 +
2441 (ulp_num * MEM_DESCR_OFFSET));
2442 phba->mem_req[mem_descr_index] =
2443 num_async_pdu_data_sgl_pages *
2444 PAGE_SIZE;
2445
2446 mem_descr_index = (HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
2447 (ulp_num * MEM_DESCR_OFFSET));
2448 phba->mem_req[mem_descr_index] =
2449 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
938f372c 2450 sizeof(struct hd_async_handle);
8a86e833
JK		 2451
2452 mem_descr_index = (HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
2453 (ulp_num * MEM_DESCR_OFFSET));
2454 phba->mem_req[mem_descr_index] =
2455 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
938f372c 2456 sizeof(struct hd_async_handle);
8a86e833
JK		 2457
2458 mem_descr_index = (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
2459 (ulp_num * MEM_DESCR_OFFSET));
2460 phba->mem_req[mem_descr_index] =
938f372c 2461 sizeof(struct hd_async_context) +
8a86e833 2462 (BEISCSI_GET_CID_COUNT(phba, ulp_num) *
938f372c 2463 sizeof(struct hd_async_entry));
8a86e833
JK		 2464 }
2465 }
6733b39a
JK		 2466}
2467
2468static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
2469{
6733b39a 2470 dma_addr_t bus_add;
a7909b39
JK		 2471 struct hwi_controller *phwi_ctrlr;
2472 struct be_mem_descriptor *mem_descr;
6733b39a
JK		 2473 struct mem_array *mem_arr, *mem_arr_orig;
2474 unsigned int i, j, alloc_size, curr_alloc_size;
2475
3ec78271 2476 phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
6733b39a
JK		 2477 if (!phba->phwi_ctrlr)
2478 return -ENOMEM;
2479
a7909b39
JK		 2480 /* Allocate memory for wrb_context */
2481 phwi_ctrlr = phba->phwi_ctrlr;
2482 phwi_ctrlr->wrb_context = kzalloc(sizeof(struct hwi_wrb_context) *
2483 phba->params.cxns_per_ctrl,
2484 GFP_KERNEL);
0c88740d
ML		 2485 if (!phwi_ctrlr->wrb_context) {
2486 kfree(phba->phwi_ctrlr);
a7909b39 2487 return -ENOMEM;
0c88740d 2488 }
a7909b39 2489
6733b39a
JK		 2490 phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
2491 GFP_KERNEL);
2492 if (!phba->init_mem) {
a7909b39 2493 kfree(phwi_ctrlr->wrb_context);
6733b39a
JK		 2494 kfree(phba->phwi_ctrlr);
2495 return -ENOMEM;
2496 }
2497
2498 mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
2499 GFP_KERNEL);
2500 if (!mem_arr_orig) {
2501 kfree(phba->init_mem);
a7909b39 2502 kfree(phwi_ctrlr->wrb_context);
6733b39a
JK		 2503 kfree(phba->phwi_ctrlr);
2504 return -ENOMEM;
2505 }
2506
2507 mem_descr = phba->init_mem;
2508 for (i = 0; i < SE_MEM_MAX; i++) {
8a86e833
JK		 2509 if (!phba->mem_req[i]) {
2510 mem_descr->mem_array = NULL;
2511 mem_descr++;
2512 continue;
2513 }
2514
6733b39a
JK		 2515 j = 0;
2516 mem_arr = mem_arr_orig;
2517 alloc_size = phba->mem_req[i];
2518 memset(mem_arr, 0, sizeof(struct mem_array) *
2519 BEISCSI_MAX_FRAGS_INIT);
2520 curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
2521 do {
2522 mem_arr->virtual_address = pci_alloc_consistent(
2523 phba->pcidev,
2524 curr_alloc_size,
2525 &bus_add);
2526 if (!mem_arr->virtual_address) {
2527 if (curr_alloc_size <= BE_MIN_MEM_SIZE)
2528 goto free_mem;
2529 if (curr_alloc_size -
2530 rounddown_pow_of_two(curr_alloc_size))
2531 curr_alloc_size = rounddown_pow_of_two
2532 (curr_alloc_size);
2533 else
2534 curr_alloc_size = curr_alloc_size / 2;
2535 } else {
2536 mem_arr->bus_address.u.
2537 a64.address = (__u64) bus_add;
2538 mem_arr->size = curr_alloc_size;
2539 alloc_size -= curr_alloc_size;
2540 curr_alloc_size = min(be_max_phys_size *
2541 1024, alloc_size);
2542 j++;
2543 mem_arr++;
2544 }
2545 } while (alloc_size);
2546 mem_descr->num_elements = j;
2547 mem_descr->size_in_bytes = phba->mem_req[i];
2548 mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
2549 GFP_KERNEL);
2550 if (!mem_descr->mem_array)
2551 goto free_mem;
2552
2553 memcpy(mem_descr->mem_array, mem_arr_orig,
2554 sizeof(struct mem_array) * j);
2555 mem_descr++;
2556 }
2557 kfree(mem_arr_orig);
2558 return 0;
2559free_mem:
2560 mem_descr->num_elements = j;
2561 while ((i) || (j)) {
2562 for (j = mem_descr->num_elements; j > 0; j--) {
2563 pci_free_consistent(phba->pcidev,
2564 mem_descr->mem_array[j - 1].size,
2565 mem_descr->mem_array[j - 1].
2566 virtual_address,
457ff3b7
JK		 2567 (unsigned long)mem_descr->
2568 mem_array[j - 1].
6733b39a
JK		 2569 bus_address.u.a64.address);
2570 }
2571 if (i) {
2572 i--;
2573 kfree(mem_descr->mem_array);
2574 mem_descr--;
2575 }
2576 }
2577 kfree(mem_arr_orig);
2578 kfree(phba->init_mem);
a7909b39 2579 kfree(phba->phwi_ctrlr->wrb_context);
6733b39a
JK		 2580 kfree(phba->phwi_ctrlr);
2581 return -ENOMEM;
2582}
2583
2584static int beiscsi_get_memory(struct beiscsi_hba *phba)
2585{
2586 beiscsi_find_mem_req(phba);
2587 return beiscsi_alloc_mem(phba);
2588}
2589
2590static void iscsi_init_global_templates(struct beiscsi_hba *phba)
2591{
2592 struct pdu_data_out *pdata_out;
2593 struct pdu_nop_out *pnop_out;
2594 struct be_mem_descriptor *mem_descr;
2595
2596 mem_descr = phba->init_mem;
2597 mem_descr += ISCSI_MEM_GLOBAL_HEADER;
2598 pdata_out =
2599 (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
2600 memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2601
2602 AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
2603 IIOC_SCSI_DATA);
2604
2605 pnop_out =
2606 (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
2607 virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
2608
2609 memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2610 AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
2611 AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
2612 AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
2613}
2614
3ec78271 2615static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
6733b39a
JK		 2616{
2617 struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
a7909b39 2618 struct hwi_context_memory *phwi_ctxt;
3ec78271 2619 struct wrb_handle *pwrb_handle = NULL;
6733b39a
JK		 2620 struct hwi_controller *phwi_ctrlr;
2621 struct hwi_wrb_context *pwrb_context;
3ec78271
JK		 2622 struct iscsi_wrb *pwrb = NULL;
2623 unsigned int num_cxn_wrbh = 0;
2624 unsigned int num_cxn_wrb = 0, j, idx = 0, index;
6733b39a
JK		 2625
2626 mem_descr_wrbh = phba->init_mem;
2627 mem_descr_wrbh += HWI_MEM_WRBH;
2628
2629 mem_descr_wrb = phba->init_mem;
2630 mem_descr_wrb += HWI_MEM_WRB;
6733b39a
JK		 2631 phwi_ctrlr = phba->phwi_ctrlr;
2632
a7909b39
JK		 2633 /* Allocate memory for WRBQ */
2634 phwi_ctxt = phwi_ctrlr->phwi_ctxt;
2635 phwi_ctxt->be_wrbq = kzalloc(sizeof(struct be_queue_info) *
843ae752 2636 phba->params.cxns_per_ctrl,
a7909b39
JK		 2637 GFP_KERNEL);
2638 if (!phwi_ctxt->be_wrbq) {
2639 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2640 "BM_%d : WRBQ Mem Alloc Failed\n");
2641 return -ENOMEM;
2642 }
2643
2644 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a 2645 pwrb_context = &phwi_ctrlr->wrb_context[index];
6733b39a
JK		 2646 pwrb_context->pwrb_handle_base =
2647 kzalloc(sizeof(struct wrb_handle *) *
2648 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271 2649 if (!pwrb_context->pwrb_handle_base) {
99bc5d55
JSJ		 2650 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2651 "BM_%d : Mem Alloc Failed. Failing to load\n");
3ec78271
JK		 2652 goto init_wrb_hndl_failed;
2653 }
6733b39a
JK		 2654 pwrb_context->pwrb_handle_basestd =
2655 kzalloc(sizeof(struct wrb_handle *) *
2656 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271 2657 if (!pwrb_context->pwrb_handle_basestd) {
99bc5d55
JSJ		 2658 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2659 "BM_%d : Mem Alloc Failed. Failing to load\n");
3ec78271
JK		 2660 goto init_wrb_hndl_failed;
2661 }
2662 if (!num_cxn_wrbh) {
2663 pwrb_handle =
2664 mem_descr_wrbh->mem_array[idx].virtual_address;
2665 num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
2666 ((sizeof(struct wrb_handle)) *
2667 phba->params.wrbs_per_cxn));
2668 idx++;
2669 }
2670 pwrb_context->alloc_index = 0;
2671 pwrb_context->wrb_handles_available = 0;
2672 pwrb_context->free_index = 0;
2673
6733b39a 2674 if (num_cxn_wrbh) {
6733b39a
JK		 2675 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2676 pwrb_context->pwrb_handle_base[j] = pwrb_handle;
2677 pwrb_context->pwrb_handle_basestd[j] =
2678 pwrb_handle;
2679 pwrb_context->wrb_handles_available++;
bfead3b2 2680 pwrb_handle->wrb_index = j;
6733b39a
JK		 2681 pwrb_handle++;
2682 }
6733b39a
JK		 2683 num_cxn_wrbh--;
2684 }
f64d92e6 2685 spin_lock_init(&pwrb_context->wrb_lock);
6733b39a
JK		 2686 }
2687 idx = 0;
a7909b39 2688 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a 2689 pwrb_context = &phwi_ctrlr->wrb_context[index];
3ec78271 2690 if (!num_cxn_wrb) {
6733b39a 2691 pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
7c56533c 2692 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
3ec78271
JK		 2693 ((sizeof(struct iscsi_wrb) *
2694 phba->params.wrbs_per_cxn));
2695 idx++;
2696 }
2697
2698 if (num_cxn_wrb) {
6733b39a
JK		 2699 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2700 pwrb_handle = pwrb_context->pwrb_handle_base[j];
2701 pwrb_handle->pwrb = pwrb;
2702 pwrb++;
2703 }
2704 num_cxn_wrb--;
2705 }
2706 }
3ec78271
JK		 2707 return 0;
2708init_wrb_hndl_failed:
2709 for (j = index; j > 0; j--) {
2710 pwrb_context = &phwi_ctrlr->wrb_context[j];
2711 kfree(pwrb_context->pwrb_handle_base);
2712 kfree(pwrb_context->pwrb_handle_basestd);
2713 }
2714 return -ENOMEM;
6733b39a
JK		 2715}
2716
a7909b39 2717static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
6733b39a 2718{
8a86e833 2719 uint8_t ulp_num;
6733b39a
JK		 2720 struct hwi_controller *phwi_ctrlr;
2721 struct hba_parameters *p = &phba->params;
938f372c
JB		 2722 struct hd_async_context *pasync_ctx;
2723 struct hd_async_handle *pasync_header_h, *pasync_data_h;
dc63aac6 2724 unsigned int index, idx, num_per_mem, num_async_data;
6733b39a
JK		 2725 struct be_mem_descriptor *mem_descr;
2726
8a86e833
JK		 2727 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
2728 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
938f372c 2729 /* get async_ctx for each ULP */
8a86e833
JK		 2730 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2731 mem_descr += (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
2732 (ulp_num * MEM_DESCR_OFFSET));
2733
2734 phwi_ctrlr = phba->phwi_ctrlr;
2735 phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num] =
938f372c 2736 (struct hd_async_context *)
8a86e833
JK		 2737 mem_descr->mem_array[0].virtual_address;
2738
2739 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
2740 memset(pasync_ctx, 0, sizeof(*pasync_ctx));
2741
2742 pasync_ctx->async_entry =
938f372c 2743 (struct hd_async_entry *)
8a86e833 2744 ((long unsigned int)pasync_ctx +
938f372c 2745 sizeof(struct hd_async_context));
8a86e833
JK		 2746
2747 pasync_ctx->num_entries = BEISCSI_GET_CID_COUNT(phba,
2748 ulp_num);
938f372c 2749 /* setup header buffers */
8a86e833
JK		 2750 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2751 mem_descr += HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
2752 (ulp_num * MEM_DESCR_OFFSET);
2753 if (mem_descr->mem_array[0].virtual_address) {
2754 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2755 "BM_%d : hwi_init_async_pdu_ctx"
2756 " HWI_MEM_ASYNC_HEADER_BUF_ULP%d va=%p\n",
2757 ulp_num,
2758 mem_descr->mem_array[0].
2759 virtual_address);
2760 } else
2761 beiscsi_log(phba, KERN_WARNING,
2762 BEISCSI_LOG_INIT,
2763 "BM_%d : No Virtual address for ULP : %d\n",
2764 ulp_num);
2765
938f372c 2766 pasync_ctx->async_header.buffer_size = p->defpdu_hdr_sz;
8a86e833 2767 pasync_ctx->async_header.va_base =
6733b39a 2768 mem_descr->mem_array[0].virtual_address;
6733b39a 2769
8a86e833
JK		 2770 pasync_ctx->async_header.pa_base.u.a64.address =
2771 mem_descr->mem_array[0].
2772 bus_address.u.a64.address;
6733b39a 2773
938f372c 2774 /* setup header buffer sgls */
8a86e833
JK		 2775 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2776 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
2777 (ulp_num * MEM_DESCR_OFFSET);
2778 if (mem_descr->mem_array[0].virtual_address) {
2779 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2780 "BM_%d : hwi_init_async_pdu_ctx"
2781 " HWI_MEM_ASYNC_HEADER_RING_ULP%d va=%p\n",
2782 ulp_num,
2783 mem_descr->mem_array[0].
2784 virtual_address);
2785 } else
2786 beiscsi_log(phba, KERN_WARNING,
2787 BEISCSI_LOG_INIT,
2788 "BM_%d : No Virtual address for ULP : %d\n",
2789 ulp_num);
2790
2791 pasync_ctx->async_header.ring_base =
2792 mem_descr->mem_array[0].virtual_address;
6733b39a 2793
938f372c 2794 /* setup header buffer handles */
8a86e833
JK		 2795 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2796 mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
2797 (ulp_num * MEM_DESCR_OFFSET);
2798 if (mem_descr->mem_array[0].virtual_address) {
2799 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2800 "BM_%d : hwi_init_async_pdu_ctx"
2801 " HWI_MEM_ASYNC_HEADER_HANDLE_ULP%d va=%p\n",
2802 ulp_num,
2803 mem_descr->mem_array[0].
2804 virtual_address);
2805 } else
2806 beiscsi_log(phba, KERN_WARNING,
2807 BEISCSI_LOG_INIT,
2808 "BM_%d : No Virtual address for ULP : %d\n",
2809 ulp_num);
2810
2811 pasync_ctx->async_header.handle_base =
2812 mem_descr->mem_array[0].virtual_address;
8a86e833
JK		 2813 INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
2814
938f372c 2815 /* setup data buffer sgls */
8a86e833
JK		 2816 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2817 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
2818 (ulp_num * MEM_DESCR_OFFSET);
2819 if (mem_descr->mem_array[0].virtual_address) {
2820 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2821 "BM_%d : hwi_init_async_pdu_ctx"
2822 " HWI_MEM_ASYNC_DATA_RING_ULP%d va=%p\n",
2823 ulp_num,
2824 mem_descr->mem_array[0].
2825 virtual_address);
2826 } else
2827 beiscsi_log(phba, KERN_WARNING,
2828 BEISCSI_LOG_INIT,
2829 "BM_%d : No Virtual address for ULP : %d\n",
2830 ulp_num);
2831
2832 pasync_ctx->async_data.ring_base =
2833 mem_descr->mem_array[0].virtual_address;
6733b39a 2834
938f372c 2835 /* setup data buffer handles */
8a86e833
JK		 2836 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2837 mem_descr += HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
2838 (ulp_num * MEM_DESCR_OFFSET);
2839 if (!mem_descr->mem_array[0].virtual_address)
2840 beiscsi_log(phba, KERN_WARNING,
2841 BEISCSI_LOG_INIT,
2842 "BM_%d : No Virtual address for ULP : %d\n",
2843 ulp_num);
99bc5d55 2844
8a86e833
JK		 2845 pasync_ctx->async_data.handle_base =
2846 mem_descr->mem_array[0].virtual_address;
8a86e833
JK		 2847 INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
2848
2849 pasync_header_h =
938f372c 2850 (struct hd_async_handle *)
8a86e833
JK		 2851 pasync_ctx->async_header.handle_base;
2852 pasync_data_h =
938f372c 2853 (struct hd_async_handle *)
8a86e833
JK		 2854 pasync_ctx->async_data.handle_base;
2855
938f372c 2856 /* setup data buffers */
8a86e833
JK		 2857 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2858 mem_descr += HWI_MEM_ASYNC_DATA_BUF_ULP0 +
2859 (ulp_num * MEM_DESCR_OFFSET);
2860 if (mem_descr->mem_array[0].virtual_address) {
2861 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2862 "BM_%d : hwi_init_async_pdu_ctx"
2863 " HWI_MEM_ASYNC_DATA_BUF_ULP%d va=%p\n",
2864 ulp_num,
2865 mem_descr->mem_array[0].
2866 virtual_address);
2867 } else
2868 beiscsi_log(phba, KERN_WARNING,
2869 BEISCSI_LOG_INIT,
2870 "BM_%d : No Virtual address for ULP : %d\n",
2871 ulp_num);
2872
2873 idx = 0;
938f372c 2874 pasync_ctx->async_data.buffer_size = p->defpdu_data_sz;
dc63aac6
JK		 2875 pasync_ctx->async_data.va_base =
2876 mem_descr->mem_array[idx].virtual_address;
2877 pasync_ctx->async_data.pa_base.u.a64.address =
2878 mem_descr->mem_array[idx].
2879 bus_address.u.a64.address;
2880
2881 num_async_data = ((mem_descr->mem_array[idx].size) /
2882 phba->params.defpdu_data_sz);
8a86e833 2883 num_per_mem = 0;
6733b39a 2884
8a86e833
JK		 2885 for (index = 0; index < BEISCSI_GET_CID_COUNT
2886 (phba, ulp_num); index++) {
2887 pasync_header_h->cri = -1;
938f372c
JB		 2888 pasync_header_h->is_header = 1;
2889 pasync_header_h->index = index;
8a86e833
JK		 2890 INIT_LIST_HEAD(&pasync_header_h->link);
2891 pasync_header_h->pbuffer =
2892 (void *)((unsigned long)
2893 (pasync_ctx->
2894 async_header.va_base) +
2895 (p->defpdu_hdr_sz * index));
2896
2897 pasync_header_h->pa.u.a64.address =
2898 pasync_ctx->async_header.pa_base.u.a64.
2899 address + (p->defpdu_hdr_sz * index);
2900
2901 list_add_tail(&pasync_header_h->link,
2902 &pasync_ctx->async_header.
2903 free_list);
2904 pasync_header_h++;
2905 pasync_ctx->async_header.free_entries++;
8a86e833 2906 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
938f372c
JB		 2907 wq.list);
2908 pasync_ctx->async_entry[index].header = NULL;
2909
8a86e833 2910 pasync_data_h->cri = -1;
938f372c
JB		 2911 pasync_data_h->is_header = 0;
2912 pasync_data_h->index = index;
8a86e833
JK		 2913 INIT_LIST_HEAD(&pasync_data_h->link);
2914
2915 if (!num_async_data) {
2916 num_per_mem = 0;
2917 idx++;
2918 pasync_ctx->async_data.va_base =
2919 mem_descr->mem_array[idx].
2920 virtual_address;
2921 pasync_ctx->async_data.pa_base.u.
2922 a64.address =
2923 mem_descr->mem_array[idx].
2924 bus_address.u.a64.address;
2925 num_async_data =
2926 ((mem_descr->mem_array[idx].
2927 size) /
2928 phba->params.defpdu_data_sz);
2929 }
2930 pasync_data_h->pbuffer =
2931 (void *)((unsigned long)
2932 (pasync_ctx->async_data.va_base) +
2933 (p->defpdu_data_sz * num_per_mem));
2934
2935 pasync_data_h->pa.u.a64.address =
2936 pasync_ctx->async_data.pa_base.u.a64.
2937 address + (p->defpdu_data_sz *
2938 num_per_mem);
2939 num_per_mem++;
2940 num_async_data--;
2941
2942 list_add_tail(&pasync_data_h->link,
2943 &pasync_ctx->async_data.
2944 free_list);
2945 pasync_data_h++;
2946 pasync_ctx->async_data.free_entries++;
938f372c 2947 pasync_ctx->async_entry[index].data = NULL;
8a86e833 2948 }
8a86e833 2949 }
6733b39a
JK		 2950 }
2951
a7909b39 2952 return 0;
6733b39a
JK		 2953}
2954
2955static int
2956be_sgl_create_contiguous(void *virtual_address,
2957 u64 physical_address, u32 length,
2958 struct be_dma_mem *sgl)
2959{
2960 WARN_ON(!virtual_address);
2961 WARN_ON(!physical_address);
dd29dae0 2962 WARN_ON(!length);
6733b39a
JK		 2963 WARN_ON(!sgl);
2964
2965 sgl->va = virtual_address;
457ff3b7 2966 sgl->dma = (unsigned long)physical_address;
6733b39a
JK		 2967 sgl->size = length;
2968
2969 return 0;
2970}
2971
2972static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
2973{
2974 memset(sgl, 0, sizeof(*sgl));
2975}
2976
2977static void
2978hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
2979 struct mem_array *pmem, struct be_dma_mem *sgl)
2980{
2981 if (sgl->va)
2982 be_sgl_destroy_contiguous(sgl);
2983
2984 be_sgl_create_contiguous(pmem->virtual_address,
2985 pmem->bus_address.u.a64.address,
2986 pmem->size, sgl);
2987}
2988
2989static void
2990hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
2991 struct mem_array *pmem, struct be_dma_mem *sgl)
2992{
2993 if (sgl->va)
2994 be_sgl_destroy_contiguous(sgl);
2995
2996 be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
2997 pmem->bus_address.u.a64.address,
2998 pmem->size, sgl);
2999}
3000
3001static int be_fill_queue(struct be_queue_info *q,
3002 u16 len, u16 entry_size, void *vaddress)
3003{
3004 struct be_dma_mem *mem = &q->dma_mem;
3005
3006 memset(q, 0, sizeof(*q));
3007 q->len = len;
3008 q->entry_size = entry_size;
3009 mem->size = len * entry_size;
3010 mem->va = vaddress;
3011 if (!mem->va)
3012 return -ENOMEM;
3013 memset(mem->va, 0, mem->size);
3014 return 0;
3015}
3016
bfead3b2 3017static int beiscsi_create_eqs(struct beiscsi_hba *phba,
6733b39a
JK		 3018 struct hwi_context_memory *phwi_context)
3019{
bfead3b2 3020 unsigned int i, num_eq_pages;
99bc5d55 3021 int ret = 0, eq_for_mcc;
6733b39a
JK		 3022 struct be_queue_info *eq;
3023 struct be_dma_mem *mem;
6733b39a 3024 void *eq_vaddress;
bfead3b2 3025 dma_addr_t paddr;
6733b39a 3026
bfead3b2
JK		 3027 num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
3028 sizeof(struct be_eq_entry));
6733b39a 3029
bfead3b2
JK		 3030 if (phba->msix_enabled)
3031 eq_for_mcc = 1;
3032 else
3033 eq_for_mcc = 0;
3034 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
3035 eq = &phwi_context->be_eq[i].q;
3036 mem = &eq->dma_mem;
3037 phwi_context->be_eq[i].phba = phba;
3038 eq_vaddress = pci_alloc_consistent(phba->pcidev,
3039 num_eq_pages * PAGE_SIZE,
3040 &paddr);
3041 if (!eq_vaddress)
3042 goto create_eq_error;
3043
3044 mem->va = eq_vaddress;
3045 ret = be_fill_queue(eq, phba->params.num_eq_entries,
3046 sizeof(struct be_eq_entry), eq_vaddress);
3047 if (ret) {
99bc5d55
JSJ		 3048 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3049 "BM_%d : be_fill_queue Failed for EQ\n");
bfead3b2
JK		 3050 goto create_eq_error;
3051 }
6733b39a 3052
bfead3b2
JK		 3053 mem->dma = paddr;
3054 ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
3055 phwi_context->cur_eqd);
3056 if (ret) {
99bc5d55
JSJ		 3057 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3058 "BM_%d : beiscsi_cmd_eq_create"
3059 "Failed for EQ\n");
bfead3b2
JK		 3060 goto create_eq_error;
3061 }
99bc5d55
JSJ		 3062
3063 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3064 "BM_%d : eqid = %d\n",
3065 phwi_context->be_eq[i].q.id);
6733b39a 3066 }
6733b39a 3067 return 0;
bfead3b2 3068create_eq_error:
107dfcba 3069 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
bfead3b2
JK		 3070 eq = &phwi_context->be_eq[i].q;
3071 mem = &eq->dma_mem;
3072 if (mem->va)
3073 pci_free_consistent(phba->pcidev, num_eq_pages
3074 * PAGE_SIZE,
3075 mem->va, mem->dma);
3076 }
3077 return ret;
6733b39a
JK		 3078}
3079
bfead3b2 3080static int beiscsi_create_cqs(struct beiscsi_hba *phba,
6733b39a
JK		 3081 struct hwi_context_memory *phwi_context)
3082{
bfead3b2 3083 unsigned int i, num_cq_pages;
99bc5d55 3084 int ret = 0;
6733b39a
JK		 3085 struct be_queue_info *cq, *eq;
3086 struct be_dma_mem *mem;
bfead3b2 3087 struct be_eq_obj *pbe_eq;
6733b39a 3088 void *cq_vaddress;
bfead3b2 3089 dma_addr_t paddr;
6733b39a 3090
bfead3b2
JK		 3091 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
3092 sizeof(struct sol_cqe));
6733b39a 3093
bfead3b2
JK		 3094 for (i = 0; i < phba->num_cpus; i++) {
3095 cq = &phwi_context->be_cq[i];
3096 eq = &phwi_context->be_eq[i].q;
3097 pbe_eq = &phwi_context->be_eq[i];
3098 pbe_eq->cq = cq;
3099 pbe_eq->phba = phba;
3100 mem = &cq->dma_mem;
3101 cq_vaddress = pci_alloc_consistent(phba->pcidev,
3102 num_cq_pages * PAGE_SIZE,
3103 &paddr);
3104 if (!cq_vaddress)
3105 goto create_cq_error;
7da50879 3106 ret = be_fill_queue(cq, phba->params.num_cq_entries,
bfead3b2
JK		 3107 sizeof(struct sol_cqe), cq_vaddress);
3108 if (ret) {
99bc5d55
JSJ		 3109 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3110 "BM_%d : be_fill_queue Failed "
3111 "for ISCSI CQ\n");
bfead3b2
JK		 3112 goto create_cq_error;
3113 }
3114
3115 mem->dma = paddr;
3116 ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
3117 false, 0);
3118 if (ret) {
99bc5d55
JSJ		 3119 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3120 "BM_%d : beiscsi_cmd_eq_create"
3121 "Failed for ISCSI CQ\n");
bfead3b2
JK		 3122 goto create_cq_error;
3123 }
99bc5d55
JSJ		 3124 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3125 "BM_%d : iscsi cq_id is %d for eq_id %d\n"
3126 "iSCSI CQ CREATED\n", cq->id, eq->id);
6733b39a 3127 }
6733b39a 3128 return 0;
bfead3b2
JK		 3129
3130create_cq_error:
3131 for (i = 0; i < phba->num_cpus; i++) {
3132 cq = &phwi_context->be_cq[i];
3133 mem = &cq->dma_mem;
3134 if (mem->va)
3135 pci_free_consistent(phba->pcidev, num_cq_pages
3136 * PAGE_SIZE,
3137 mem->va, mem->dma);
3138 }
3139 return ret;
3140
6733b39a
JK		 3141}
3142
3143static int
3144beiscsi_create_def_hdr(struct beiscsi_hba *phba,
3145 struct hwi_context_memory *phwi_context,
3146 struct hwi_controller *phwi_ctrlr,
8a86e833 3147 unsigned int def_pdu_ring_sz, uint8_t ulp_num)
6733b39a
JK		 3148{
3149 unsigned int idx;
3150 int ret;
3151 struct be_queue_info *dq, *cq;
3152 struct be_dma_mem *mem;
3153 struct be_mem_descriptor *mem_descr;
3154 void *dq_vaddress;
3155
3156 idx = 0;
8a86e833 3157 dq = &phwi_context->be_def_hdrq[ulp_num];
bfead3b2 3158 cq = &phwi_context->be_cq[0];
6733b39a
JK		 3159 mem = &dq->dma_mem;
3160 mem_descr = phba->init_mem;
8a86e833
JK		 3161 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
3162 (ulp_num * MEM_DESCR_OFFSET);
6733b39a
JK		 3163 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
3164 ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
3165 sizeof(struct phys_addr),
3166 sizeof(struct phys_addr), dq_vaddress);
3167 if (ret) {
99bc5d55 3168 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3169 "BM_%d : be_fill_queue Failed for DEF PDU HDR on ULP : %d\n",
3170 ulp_num);
3171
6733b39a
JK		 3172 return ret;
3173 }
457ff3b7
JK		 3174 mem->dma = (unsigned long)mem_descr->mem_array[idx].
3175 bus_address.u.a64.address;
6733b39a
JK		 3176 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
3177 def_pdu_ring_sz,
8a86e833
JK		 3178 phba->params.defpdu_hdr_sz,
3179 BEISCSI_DEFQ_HDR, ulp_num);
6733b39a 3180 if (ret) {
99bc5d55 3181 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3182 "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR on ULP : %d\n",
3183 ulp_num);
3184
6733b39a
JK		 3185 return ret;
3186 }
99bc5d55 3187
8a86e833
JK		 3188 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3189 "BM_%d : iscsi hdr def pdu id for ULP : %d is %d\n",
3190 ulp_num,
3191 phwi_context->be_def_hdrq[ulp_num].id);
6733b39a
JK		 3192 return 0;
3193}
3194
3195static int
3196beiscsi_create_def_data(struct beiscsi_hba *phba,
3197 struct hwi_context_memory *phwi_context,
3198 struct hwi_controller *phwi_ctrlr,
8a86e833 3199 unsigned int def_pdu_ring_sz, uint8_t ulp_num)
6733b39a
JK		 3200{
3201 unsigned int idx;
3202 int ret;
3203 struct be_queue_info *dataq, *cq;
3204 struct be_dma_mem *mem;
3205 struct be_mem_descriptor *mem_descr;
3206 void *dq_vaddress;
3207
3208 idx = 0;
8a86e833 3209 dataq = &phwi_context->be_def_dataq[ulp_num];
bfead3b2 3210 cq = &phwi_context->be_cq[0];
6733b39a
JK		 3211 mem = &dataq->dma_mem;
3212 mem_descr = phba->init_mem;
8a86e833
JK		 3213 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
3214 (ulp_num * MEM_DESCR_OFFSET);
6733b39a
JK		 3215 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
3216 ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
3217 sizeof(struct phys_addr),
3218 sizeof(struct phys_addr), dq_vaddress);
3219 if (ret) {
99bc5d55 3220 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3221 "BM_%d : be_fill_queue Failed for DEF PDU "
3222 "DATA on ULP : %d\n",
3223 ulp_num);
3224
6733b39a
JK		 3225 return ret;
3226 }
457ff3b7
JK		 3227 mem->dma = (unsigned long)mem_descr->mem_array[idx].
3228 bus_address.u.a64.address;
6733b39a
JK		 3229 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
3230 def_pdu_ring_sz,
8a86e833
JK		 3231 phba->params.defpdu_data_sz,
3232 BEISCSI_DEFQ_DATA, ulp_num);
6733b39a 3233 if (ret) {
99bc5d55
JSJ		 3234 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3235 "BM_%d be_cmd_create_default_pdu_queue"
8a86e833
JK		 3236 " Failed for DEF PDU DATA on ULP : %d\n",
3237 ulp_num);
6733b39a
JK		 3238 return ret;
3239 }
8a86e833 3240
99bc5d55 3241 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
8a86e833
JK		 3242 "BM_%d : iscsi def data id on ULP : %d is %d\n",
3243 ulp_num,
3244 phwi_context->be_def_dataq[ulp_num].id);
99bc5d55 3245
99bc5d55 3246 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
8a86e833
JK		 3247 "BM_%d : DEFAULT PDU DATA RING CREATED"
3248 "on ULP : %d\n", ulp_num);
6733b39a
JK		 3249 return 0;
3250}
3251
15a90fe0
JK		 3252
3253static int
3254beiscsi_post_template_hdr(struct beiscsi_hba *phba)
3255{
3256 struct be_mem_descriptor *mem_descr;
3257 struct mem_array *pm_arr;
3258 struct be_dma_mem sgl;
a129d92f 3259 int status, ulp_num;
15a90fe0 3260
a129d92f
JK		 3261 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3262 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3263 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3264 mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 +
3265 (ulp_num * MEM_DESCR_OFFSET);
3266 pm_arr = mem_descr->mem_array;
15a90fe0 3267
a129d92f
JK		 3268 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
3269 status = be_cmd_iscsi_post_template_hdr(
3270 &phba->ctrl, &sgl);
15a90fe0 3271
a129d92f
JK		 3272 if (status != 0) {
3273 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3274 "BM_%d : Post Template HDR Failed for"
3275 "ULP_%d\n", ulp_num);
3276 return status;
3277 }
3278
3279 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3280 "BM_%d : Template HDR Pages Posted for"
3281 "ULP_%d\n", ulp_num);
15a90fe0
JK		 3282 }
3283 }
15a90fe0
JK		 3284 return 0;
3285}
3286
6733b39a
JK		 3287static int
3288beiscsi_post_pages(struct beiscsi_hba *phba)
3289{
3290 struct be_mem_descriptor *mem_descr;
3291 struct mem_array *pm_arr;
3292 unsigned int page_offset, i;
3293 struct be_dma_mem sgl;
843ae752 3294 int status, ulp_num = 0;
6733b39a
JK		 3295
3296 mem_descr = phba->init_mem;
3297 mem_descr += HWI_MEM_SGE;
3298 pm_arr = mem_descr->mem_array;
3299
90622db3
JK		 3300 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3301 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
3302 break;
3303
6733b39a 3304 page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
843ae752 3305 phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE;
6733b39a
JK		 3306 for (i = 0; i < mem_descr->num_elements; i++) {
3307 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
3308 status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
3309 page_offset,
3310 (pm_arr->size / PAGE_SIZE));
3311 page_offset += pm_arr->size / PAGE_SIZE;
3312 if (status != 0) {
99bc5d55
JSJ		 3313 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3314 "BM_%d : post sgl failed.\n");
6733b39a
JK		 3315 return status;
3316 }
3317 pm_arr++;
3318 }
99bc5d55
JSJ		 3319 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3320 "BM_%d : POSTED PAGES\n");
6733b39a
JK		 3321 return 0;
3322}
3323
bfead3b2
JK		 3324static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
3325{
3326 struct be_dma_mem *mem = &q->dma_mem;
c8b25598 3327 if (mem->va) {
bfead3b2
JK		 3328 pci_free_consistent(phba->pcidev, mem->size,
3329 mem->va, mem->dma);
c8b25598
JK		 3330 mem->va = NULL;
3331 }
bfead3b2
JK		 3332}
3333
3334static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
3335 u16 len, u16 entry_size)
3336{
3337 struct be_dma_mem *mem = &q->dma_mem;
3338
3339 memset(q, 0, sizeof(*q));
3340 q->len = len;
3341 q->entry_size = entry_size;
3342 mem->size = len * entry_size;
7c845eb5 3343 mem->va = pci_zalloc_consistent(phba->pcidev, mem->size, &mem->dma);
bfead3b2 3344 if (!mem->va)
d3ad2bb3 3345 return -ENOMEM;
bfead3b2
JK		 3346 return 0;
3347}
3348
6733b39a
JK		 3349static int
3350beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
3351 struct hwi_context_memory *phwi_context,
3352 struct hwi_controller *phwi_ctrlr)
3353{
3354 unsigned int wrb_mem_index, offset, size, num_wrb_rings;
3355 u64 pa_addr_lo;
4eea99d5 3356 unsigned int idx, num, i, ulp_num;
6733b39a
JK		 3357 struct mem_array *pwrb_arr;
3358 void *wrb_vaddr;
3359 struct be_dma_mem sgl;
3360 struct be_mem_descriptor *mem_descr;
a7909b39 3361 struct hwi_wrb_context *pwrb_context;
6733b39a 3362 int status;
4eea99d5
JK		 3363 uint8_t ulp_count = 0, ulp_base_num = 0;
3364 uint16_t cid_count_ulp[BEISCSI_ULP_COUNT] = { 0 };
6733b39a
JK		 3365
3366 idx = 0;
3367 mem_descr = phba->init_mem;
3368 mem_descr += HWI_MEM_WRB;
3369 pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
3370 GFP_KERNEL);
3371 if (!pwrb_arr) {
99bc5d55
JSJ		 3372 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3373 "BM_%d : Memory alloc failed in create wrb ring.\n");
6733b39a
JK		 3374 return -ENOMEM;
3375 }
3376 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
3377 pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
3378 num_wrb_rings = mem_descr->mem_array[idx].size /
3379 (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
3380
3381 for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
3382 if (num_wrb_rings) {
3383 pwrb_arr[num].virtual_address = wrb_vaddr;
3384 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
3385 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
3386 sizeof(struct iscsi_wrb);
3387 wrb_vaddr += pwrb_arr[num].size;
3388 pa_addr_lo += pwrb_arr[num].size;
3389 num_wrb_rings--;
3390 } else {
3391 idx++;
3392 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
3393 pa_addr_lo = mem_descr->mem_array[idx].\
3394 bus_address.u.a64.address;
3395 num_wrb_rings = mem_descr->mem_array[idx].size /
3396 (phba->params.wrbs_per_cxn *
3397 sizeof(struct iscsi_wrb));
3398 pwrb_arr[num].virtual_address = wrb_vaddr;
3399 pwrb_arr[num].bus_address.u.a64.address\
3400 = pa_addr_lo;
3401 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
3402 sizeof(struct iscsi_wrb);
3403 wrb_vaddr += pwrb_arr[num].size;
3404 pa_addr_lo += pwrb_arr[num].size;
3405 num_wrb_rings--;
3406 }
3407 }
4eea99d5
JK		 3408
3409 /* Get the ULP Count */
3410 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3411 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3412 ulp_count++;
3413 ulp_base_num = ulp_num;
3414 cid_count_ulp[ulp_num] =
3415 BEISCSI_GET_CID_COUNT(phba, ulp_num);
3416 }
3417
6733b39a
JK		 3418 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3419 wrb_mem_index = 0;
3420 offset = 0;
3421 size = 0;
3422
4eea99d5
JK		 3423 if (ulp_count > 1) {
3424 ulp_base_num = (ulp_base_num + 1) % BEISCSI_ULP_COUNT;
3425
3426 if (!cid_count_ulp[ulp_base_num])
3427 ulp_base_num = (ulp_base_num + 1) %
3428 BEISCSI_ULP_COUNT;
3429
3430 cid_count_ulp[ulp_base_num]--;
3431 }
3432
3433
6733b39a
JK		 3434 hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
3435 status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
4eea99d5
JK		 3436 &phwi_context->be_wrbq[i],
3437 &phwi_ctrlr->wrb_context[i],
3438 ulp_base_num);
6733b39a 3439 if (status != 0) {
99bc5d55
JSJ		 3440 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3441 "BM_%d : wrbq create failed.");
1462b8ff 3442 kfree(pwrb_arr);
6733b39a
JK		 3443 return status;
3444 }
a7909b39 3445 pwrb_context = &phwi_ctrlr->wrb_context[i];
a7909b39 3446 BE_SET_CID_TO_CRI(i, pwrb_context->cid);
6733b39a
JK		 3447 }
3448 kfree(pwrb_arr);
3449 return 0;
3450}
3451
3452static void free_wrb_handles(struct beiscsi_hba *phba)
3453{
3454 unsigned int index;
3455 struct hwi_controller *phwi_ctrlr;
3456 struct hwi_wrb_context *pwrb_context;
3457
3458 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 3459 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a
JK		 3460 pwrb_context = &phwi_ctrlr->wrb_context[index];
3461 kfree(pwrb_context->pwrb_handle_base);
3462 kfree(pwrb_context->pwrb_handle_basestd);
3463 }
3464}
3465
bfead3b2
JK		 3466static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
3467{
bfead3b2 3468 struct be_ctrl_info *ctrl = &phba->ctrl;
d1d5ca88
JB		 3469 struct be_dma_mem *ptag_mem;
3470 struct be_queue_info *q;
3471 int i, tag;
bfead3b2
JK		 3472
3473 q = &phba->ctrl.mcc_obj.q;
d1d5ca88
JB		 3474 for (i = 0; i < MAX_MCC_CMD; i++) {
3475 tag = i + 1;
3476 if (!test_bit(MCC_TAG_STATE_RUNNING,
3477 &ctrl->ptag_state[tag].tag_state))
3478 continue;
3479
3480 if (test_bit(MCC_TAG_STATE_TIMEOUT,
3481 &ctrl->ptag_state[tag].tag_state)) {
3482 ptag_mem = &ctrl->ptag_state[tag].tag_mem_state;
3483 if (ptag_mem->size) {
3484 pci_free_consistent(ctrl->pdev,
3485 ptag_mem->size,
3486 ptag_mem->va,
3487 ptag_mem->dma);
3488 ptag_mem->size = 0;
3489 }
3490 continue;
3491 }
3492 /**
3493 * If MCC is still active and waiting then wake up the process.
3494 * We are here only because port is going offline. The process
3495 * sees that (BEISCSI_HBA_ONLINE is cleared) and EIO error is
3496 * returned for the operation and allocated memory cleaned up.
3497 */
3498 if (waitqueue_active(&ctrl->mcc_wait[tag])) {
3499 ctrl->mcc_tag_status[tag] = MCC_STATUS_FAILED;
3500 ctrl->mcc_tag_status[tag] |= CQE_VALID_MASK;
3501 wake_up_interruptible(&ctrl->mcc_wait[tag]);
3502 /*
3503 * Control tag info gets reinitialized in enable
3504 * so wait for the process to clear running state.
3505 */
3506 while (test_bit(MCC_TAG_STATE_RUNNING,
3507 &ctrl->ptag_state[tag].tag_state))
3508 schedule_timeout_uninterruptible(HZ);
3509 }
3510 /**
3511 * For MCC with tag_states MCC_TAG_STATE_ASYNC and
3512 * MCC_TAG_STATE_IGNORE nothing needs to done.
3513 */
3514 }
4e2bdf7a 3515 if (q->created) {
bfead3b2 3516 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
4e2bdf7a
JSJ		 3517 be_queue_free(phba, q);
3518 }
bfead3b2
JK		 3519
3520 q = &phba->ctrl.mcc_obj.cq;
4e2bdf7a 3521 if (q->created) {
bfead3b2 3522 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
4e2bdf7a
JSJ		 3523 be_queue_free(phba, q);
3524 }
bfead3b2
JK		 3525}
3526
bfead3b2
JK		 3527static int be_mcc_queues_create(struct beiscsi_hba *phba,
3528 struct hwi_context_memory *phwi_context)
3529{
3530 struct be_queue_info *q, *cq;
3531 struct be_ctrl_info *ctrl = &phba->ctrl;
3532
3533 /* Alloc MCC compl queue */
3534 cq = &phba->ctrl.mcc_obj.cq;
3535 if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
3536 sizeof(struct be_mcc_compl)))
3537 goto err;
3538 /* Ask BE to create MCC compl queue; */
3539 if (phba->msix_enabled) {
3540 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
3541 [phba->num_cpus].q, false, true, 0))
3542 goto mcc_cq_free;
3543 } else {
3544 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
3545 false, true, 0))
3546 goto mcc_cq_free;
3547 }
3548
3549 /* Alloc MCC queue */
3550 q = &phba->ctrl.mcc_obj.q;
3551 if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
3552 goto mcc_cq_destroy;
3553
3554 /* Ask BE to create MCC queue */
35e66019 3555 if (beiscsi_cmd_mccq_create(phba, q, cq))
bfead3b2
JK		 3556 goto mcc_q_free;
3557
3558 return 0;
3559
3560mcc_q_free:
3561 be_queue_free(phba, q);
3562mcc_cq_destroy:
3563 beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
3564mcc_cq_free:
3565 be_queue_free(phba, cq);
3566err:
d3ad2bb3 3567 return -ENOMEM;
bfead3b2
JK		 3568}
3569
107dfcba
JSJ		 3570/**
3571 * find_num_cpus()- Get the CPU online count
3572 * @phba: ptr to priv structure
3573 *
3574 * CPU count is used for creating EQ.
3575 **/
3576static void find_num_cpus(struct beiscsi_hba *phba)
bfead3b2
JK		 3577{
3578 int num_cpus = 0;
3579
3580 num_cpus = num_online_cpus();
bfead3b2 3581
22abeef0
JSJ		 3582 switch (phba->generation) {
3583 case BE_GEN2:
3584 case BE_GEN3:
3585 phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
3586 BEISCSI_MAX_NUM_CPUS : num_cpus;
3587 break;
3588 case BE_GEN4:
68c26a3a
JK		 3589 /*
3590 * If eqid_count == 1 fall back to
3591 * INTX mechanism
3592 **/
3593 if (phba->fw_config.eqid_count == 1) {
3594 enable_msix = 0;
3595 phba->num_cpus = 1;
3596 return;
3597 }
3598
3599 phba->num_cpus =
3600 (num_cpus > (phba->fw_config.eqid_count - 1)) ?
3601 (phba->fw_config.eqid_count - 1) : num_cpus;
22abeef0
JSJ		 3602 break;
3603 default:
3604 phba->num_cpus = 1;
3605 }
6733b39a
JK		 3606}
3607
d1d5ca88
JB		 3608static void hwi_purge_eq(struct beiscsi_hba *phba)
3609{
3610 struct hwi_controller *phwi_ctrlr;
3611 struct hwi_context_memory *phwi_context;
3612 struct be_queue_info *eq;
3613 struct be_eq_entry *eqe = NULL;
3614 int i, eq_msix;
3615 unsigned int num_processed;
3616
3617 if (beiscsi_hba_in_error(phba))
3618 return;
3619
3620 phwi_ctrlr = phba->phwi_ctrlr;
3621 phwi_context = phwi_ctrlr->phwi_ctxt;
3622 if (phba->msix_enabled)
3623 eq_msix = 1;
3624 else
3625 eq_msix = 0;
3626
3627 for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
3628 eq = &phwi_context->be_eq[i].q;
3629 eqe = queue_tail_node(eq);
3630 num_processed = 0;
3631 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
3632 & EQE_VALID_MASK) {
3633 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
3634 queue_tail_inc(eq);
3635 eqe = queue_tail_node(eq);
3636 num_processed++;
3637 }
3638
3639 if (num_processed)
3640 hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
3641 }
3642}
3643
3644static void hwi_cleanup_port(struct beiscsi_hba *phba)
3645{
3646 struct be_queue_info *q;
3647 struct be_ctrl_info *ctrl = &phba->ctrl;
3648 struct hwi_controller *phwi_ctrlr;
3649 struct hwi_context_memory *phwi_context;
938f372c 3650 struct hd_async_context *pasync_ctx;
d1d5ca88
JB		 3651 int i, eq_for_mcc, ulp_num;
3652
3653 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3654 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
3655 beiscsi_cmd_iscsi_cleanup(phba, ulp_num);
3656
3657 /**
3658 * Purge all EQ entries that may have been left out. This is to
3659 * workaround a problem we've seen occasionally where driver gets an
3660 * interrupt with EQ entry bit set after stopping the controller.
3661 */
3662 hwi_purge_eq(phba);
3663
3664 phwi_ctrlr = phba->phwi_ctrlr;
3665 phwi_context = phwi_ctrlr->phwi_ctxt;
3666
3667 be_cmd_iscsi_remove_template_hdr(ctrl);
3668
3669 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3670 q = &phwi_context->be_wrbq[i];
3671 if (q->created)
3672 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
3673 }
3674 kfree(phwi_context->be_wrbq);
3675 free_wrb_handles(phba);
3676
3677 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3678 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3679
3680 q = &phwi_context->be_def_hdrq[ulp_num];
3681 if (q->created)
3682 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3683
3684 q = &phwi_context->be_def_dataq[ulp_num];
3685 if (q->created)
3686 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3687
3688 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
3689 }
3690 }
3691
3692 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
3693
3694 for (i = 0; i < (phba->num_cpus); i++) {
3695 q = &phwi_context->be_cq[i];
3696 if (q->created) {
3697 be_queue_free(phba, q);
3698 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
3699 }
3700 }
3701
3702 be_mcc_queues_destroy(phba);
3703 if (phba->msix_enabled)
3704 eq_for_mcc = 1;
3705 else
3706 eq_for_mcc = 0;
3707 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
3708 q = &phwi_context->be_eq[i].q;
3709 if (q->created) {
3710 be_queue_free(phba, q);
3711 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
3712 }
3713 }
4ee1ec42
JB		 3714 /* this ensures complete FW cleanup */
3715 beiscsi_cmd_function_reset(phba);
d1d5ca88
JB		 3716 /* last communication, indicate driver is unloading */
3717 beiscsi_cmd_special_wrb(&phba->ctrl, 0);
3718}
4ee1ec42 3719
6733b39a
JK		 3720static int hwi_init_port(struct beiscsi_hba *phba)
3721{
3722 struct hwi_controller *phwi_ctrlr;
3723 struct hwi_context_memory *phwi_context;
3724 unsigned int def_pdu_ring_sz;
3725 struct be_ctrl_info *ctrl = &phba->ctrl;
8a86e833 3726 int status, ulp_num;
6733b39a 3727
6733b39a 3728 phwi_ctrlr = phba->phwi_ctrlr;
6733b39a 3729 phwi_context = phwi_ctrlr->phwi_ctxt;
73af08e1 3730 phwi_context->max_eqd = 128;
bfead3b2 3731 phwi_context->min_eqd = 0;
1b7a7ddc 3732 phwi_context->cur_eqd = 32;
4d2ee1e6 3733 /* set port optic state to unknown */
53aefe25 3734 phba->optic_state = 0xff;
bfead3b2
JK		 3735
3736 status = beiscsi_create_eqs(phba, phwi_context);
6733b39a 3737 if (status != 0) {
99bc5d55
JSJ		 3738 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3739 "BM_%d : EQ not created\n");
6733b39a
JK		 3740 goto error;
3741 }
3742
bfead3b2
JK		 3743 status = be_mcc_queues_create(phba, phwi_context);
3744 if (status != 0)
3745 goto error;
3746
480195c2 3747 status = beiscsi_check_supported_fw(ctrl, phba);
6733b39a 3748 if (status != 0) {
99bc5d55
JSJ		 3749 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3750 "BM_%d : Unsupported fw version\n");
6733b39a
JK		 3751 goto error;
3752 }
3753
bfead3b2 3754 status = beiscsi_create_cqs(phba, phwi_context);
6733b39a 3755 if (status != 0) {
99bc5d55
JSJ		 3756 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3757 "BM_%d : CQ not created\n");
6733b39a
JK		 3758 goto error;
3759 }
3760
8a86e833
JK		 3761 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3762 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
8a86e833
JK		 3763 def_pdu_ring_sz =
3764 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
3765 sizeof(struct phys_addr);
3766
3767 status = beiscsi_create_def_hdr(phba, phwi_context,
3768 phwi_ctrlr,
3769 def_pdu_ring_sz,
3770 ulp_num);
3771 if (status != 0) {
3772 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3773 "BM_%d : Default Header not created for ULP : %d\n",
3774 ulp_num);
3775 goto error;
3776 }
3777
3778 status = beiscsi_create_def_data(phba, phwi_context,
3779 phwi_ctrlr,
3780 def_pdu_ring_sz,
3781 ulp_num);
3782 if (status != 0) {
3783 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3784 "BM_%d : Default Data not created for ULP : %d\n",
3785 ulp_num);
3786 goto error;
3787 }
f79929de
JB		 3788 /**
3789 * Now that the default PDU rings have been created,
3790 * let EP know about it.
3791 * Call beiscsi_cmd_iscsi_cleanup before posting?
3792 */
938f372c
JB		 3793 beiscsi_hdq_post_handles(phba, BEISCSI_DEFQ_HDR,
3794 ulp_num);
3795 beiscsi_hdq_post_handles(phba, BEISCSI_DEFQ_DATA,
3796 ulp_num);
8a86e833 3797 }
6733b39a
JK		 3798 }
3799
3800 status = beiscsi_post_pages(phba);
3801 if (status != 0) {
99bc5d55
JSJ		 3802 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3803 "BM_%d : Post SGL Pages Failed\n");
6733b39a
JK		 3804 goto error;
3805 }
3806
15a90fe0
JK		 3807 status = beiscsi_post_template_hdr(phba);
3808 if (status != 0) {
3809 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3810 "BM_%d : Template HDR Posting for CXN Failed\n");
3811 }
3812
6733b39a
JK		 3813 status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
3814 if (status != 0) {
99bc5d55
JSJ		 3815 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3816 "BM_%d : WRB Rings not created\n");
6733b39a
JK		 3817 goto error;
3818 }
3819
8a86e833
JK		 3820 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3821 uint16_t async_arr_idx = 0;
3822
3823 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3824 uint16_t cri = 0;
938f372c 3825 struct hd_async_context *pasync_ctx;
8a86e833
JK		 3826
3827 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(
3828 phwi_ctrlr, ulp_num);
3829 for (cri = 0; cri <
3830 phba->params.cxns_per_ctrl; cri++) {
3831 if (ulp_num == BEISCSI_GET_ULP_FROM_CRI
3832 (phwi_ctrlr, cri))
3833 pasync_ctx->cid_to_async_cri_map[
3834 phwi_ctrlr->wrb_context[cri].cid] =
3835 async_arr_idx++;
3836 }
938f372c
JB		 3837 /**
3838 * Now that the default PDU rings have been created,
3839 * let EP know about it.
3840 */
3841 beiscsi_hdq_post_handles(phba, BEISCSI_DEFQ_HDR,
3842 ulp_num);
3843 beiscsi_hdq_post_handles(phba, BEISCSI_DEFQ_DATA,
3844 ulp_num);
8a86e833
JK		 3845 }
3846 }
3847
99bc5d55
JSJ		 3848 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3849 "BM_%d : hwi_init_port success\n");
6733b39a
JK		 3850 return 0;
3851
3852error:
99bc5d55
JSJ		 3853 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3854 "BM_%d : hwi_init_port failed");
4d2ee1e6 3855 hwi_cleanup_port(phba);
a49e06d5 3856 return status;
6733b39a
JK		 3857}
3858
6733b39a
JK		 3859static int hwi_init_controller(struct beiscsi_hba *phba)
3860{
3861 struct hwi_controller *phwi_ctrlr;
3862
3863 phwi_ctrlr = phba->phwi_ctrlr;
3864 if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
3865 phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
3866 init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
99bc5d55
JSJ		 3867 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3868 "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
3869 phwi_ctrlr->phwi_ctxt);
6733b39a 3870 } else {
99bc5d55
JSJ		 3871 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3872 "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
3873 "than one element.Failing to load\n");
6733b39a
JK		 3874 return -ENOMEM;
3875 }
3876
3877 iscsi_init_global_templates(phba);
3ec78271
JK		 3878 if (beiscsi_init_wrb_handle(phba))
3879 return -ENOMEM;
3880
a7909b39
JK		 3881 if (hwi_init_async_pdu_ctx(phba)) {
3882 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3883 "BM_%d : hwi_init_async_pdu_ctx failed\n");
3884 return -ENOMEM;
3885 }
3886
6733b39a 3887 if (hwi_init_port(phba) != 0) {
99bc5d55
JSJ		 3888 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3889 "BM_%d : hwi_init_controller failed\n");
3890
6733b39a
JK		 3891 return -ENOMEM;
3892 }
3893 return 0;
3894}
3895
3896static void beiscsi_free_mem(struct beiscsi_hba *phba)
3897{
3898 struct be_mem_descriptor *mem_descr;
3899 int i, j;
3900
3901 mem_descr = phba->init_mem;
3902 i = 0;
3903 j = 0;
3904 for (i = 0; i < SE_MEM_MAX; i++) {
3905 for (j = mem_descr->num_elements; j > 0; j--) {
3906 pci_free_consistent(phba->pcidev,
3907 mem_descr->mem_array[j - 1].size,
3908 mem_descr->mem_array[j - 1].virtual_address,
457ff3b7
JK		 3909 (unsigned long)mem_descr->mem_array[j - 1].
3910 bus_address.u.a64.address);
6733b39a 3911 }
8a86e833 3912
6733b39a
JK		 3913 kfree(mem_descr->mem_array);
3914 mem_descr++;
3915 }
3916 kfree(phba->init_mem);
a7909b39 3917 kfree(phba->phwi_ctrlr->wrb_context);
6733b39a
JK		 3918 kfree(phba->phwi_ctrlr);
3919}
3920
3921static int beiscsi_init_controller(struct beiscsi_hba *phba)
3922{
3923 int ret = -ENOMEM;
3924
3925 ret = beiscsi_get_memory(phba);
3926 if (ret < 0) {
99bc5d55
JSJ		 3927 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3928 "BM_%d : beiscsi_dev_probe -"
3929 "Failed in beiscsi_alloc_memory\n");
6733b39a
JK		 3930 return ret;
3931 }
3932
3933 ret = hwi_init_controller(phba);
3934 if (ret)
3935 goto free_init;
99bc5d55
JSJ		 3936 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3937 "BM_%d : Return success from beiscsi_init_controller");
3938
6733b39a
JK		 3939 return 0;
3940
3941free_init:
3942 beiscsi_free_mem(phba);
a49e06d5 3943 return ret;
6733b39a
JK		 3944}
3945
3946static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
3947{
3948 struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
3949 struct sgl_handle *psgl_handle;
3950 struct iscsi_sge *pfrag;
90622db3
JK		 3951 unsigned int arr_index, i, idx;
3952 unsigned int ulp_icd_start, ulp_num = 0;
6733b39a
JK		 3953
3954 phba->io_sgl_hndl_avbl = 0;
3955 phba->eh_sgl_hndl_avbl = 0;
bfead3b2 3956
6733b39a
JK		 3957 mem_descr_sglh = phba->init_mem;
3958 mem_descr_sglh += HWI_MEM_SGLH;
3959 if (1 == mem_descr_sglh->num_elements) {
3960 phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
3961 phba->params.ios_per_ctrl,
3962 GFP_KERNEL);
3963 if (!phba->io_sgl_hndl_base) {
99bc5d55
JSJ		 3964 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3965 "BM_%d : Mem Alloc Failed. Failing to load\n");
6733b39a
JK		 3966 return -ENOMEM;
3967 }
3968 phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
3969 (phba->params.icds_per_ctrl -
3970 phba->params.ios_per_ctrl),
3971 GFP_KERNEL);
3972 if (!phba->eh_sgl_hndl_base) {
3973 kfree(phba->io_sgl_hndl_base);
99bc5d55
JSJ		 3974 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3975 "BM_%d : Mem Alloc Failed. Failing to load\n");
6733b39a
JK		 3976 return -ENOMEM;
3977 }
3978 } else {
99bc5d55
JSJ		 3979 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3980 "BM_%d : HWI_MEM_SGLH is more than one element."
3981 "Failing to load\n");
6733b39a
JK		 3982 return -ENOMEM;
3983 }
3984
3985 arr_index = 0;
3986 idx = 0;
3987 while (idx < mem_descr_sglh->num_elements) {
3988 psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
3989
3990 for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
3991 sizeof(struct sgl_handle)); i++) {
3992 if (arr_index < phba->params.ios_per_ctrl) {
3993 phba->io_sgl_hndl_base[arr_index] = psgl_handle;
3994 phba->io_sgl_hndl_avbl++;
3995 arr_index++;
3996 } else {
3997 phba->eh_sgl_hndl_base[arr_index -
3998 phba->params.ios_per_ctrl] =
3999 psgl_handle;
4000 arr_index++;
4001 phba->eh_sgl_hndl_avbl++;
4002 }
4003 psgl_handle++;
4004 }
4005 idx++;
4006 }
99bc5d55
JSJ		 4007 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4008 "BM_%d : phba->io_sgl_hndl_avbl=%d"
4009 "phba->eh_sgl_hndl_avbl=%d\n",
4010 phba->io_sgl_hndl_avbl,
4011 phba->eh_sgl_hndl_avbl);
4012
6733b39a
JK		 4013 mem_descr_sg = phba->init_mem;
4014 mem_descr_sg += HWI_MEM_SGE;
99bc5d55
JSJ		 4015 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4016 "\n BM_%d : mem_descr_sg->num_elements=%d\n",
4017 mem_descr_sg->num_elements);
4018
90622db3
JK		 4019 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
4020 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
4021 break;
4022
4023 ulp_icd_start = phba->fw_config.iscsi_icd_start[ulp_num];
4024
6733b39a
JK		 4025 arr_index = 0;
4026 idx = 0;
4027 while (idx < mem_descr_sg->num_elements) {
4028 pfrag = mem_descr_sg->mem_array[idx].virtual_address;
4029
4030 for (i = 0;
4031 i < (mem_descr_sg->mem_array[idx].size) /
4032 (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
4033 i++) {
4034 if (arr_index < phba->params.ios_per_ctrl)
4035 psgl_handle = phba->io_sgl_hndl_base[arr_index];
4036 else
4037 psgl_handle = phba->eh_sgl_hndl_base[arr_index -
4038 phba->params.ios_per_ctrl];
4039 psgl_handle->pfrag = pfrag;
4040 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
4041 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
4042 pfrag += phba->params.num_sge_per_io;
90622db3 4043 psgl_handle->sgl_index = ulp_icd_start + arr_index++;
6733b39a
JK		 4044 }
4045 idx++;
4046 }
4047 phba->io_sgl_free_index = 0;
4048 phba->io_sgl_alloc_index = 0;
4049 phba->eh_sgl_free_index = 0;
4050 phba->eh_sgl_alloc_index = 0;
4051 return 0;
4052}
4053
4054static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
4055{
0a3db7c0
JK		 4056 int ret;
4057 uint16_t i, ulp_num;
4058 struct ulp_cid_info *ptr_cid_info = NULL;
6733b39a 4059
0a3db7c0
JK		 4060 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4061 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4062 ptr_cid_info = kzalloc(sizeof(struct ulp_cid_info),
4063 GFP_KERNEL);
4064
4065 if (!ptr_cid_info) {
4066 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4067 "BM_%d : Failed to allocate memory"
4068 "for ULP_CID_INFO for ULP : %d\n",
4069 ulp_num);
4070 ret = -ENOMEM;
4071 goto free_memory;
4072
4073 }
4074
4075 /* Allocate memory for CID array */
4076 ptr_cid_info->cid_array = kzalloc(sizeof(void *) *
4077 BEISCSI_GET_CID_COUNT(phba,
4078 ulp_num), GFP_KERNEL);
4079 if (!ptr_cid_info->cid_array) {
4080 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4081 "BM_%d : Failed to allocate memory"
4082 "for CID_ARRAY for ULP : %d\n",
4083 ulp_num);
4084 kfree(ptr_cid_info);
4085 ptr_cid_info = NULL;
4086 ret = -ENOMEM;
4087
4088 goto free_memory;
4089 }
4090 ptr_cid_info->avlbl_cids = BEISCSI_GET_CID_COUNT(
4091 phba, ulp_num);
4092
4093 /* Save the cid_info_array ptr */
4094 phba->cid_array_info[ulp_num] = ptr_cid_info;
4095 }
6733b39a 4096 }
c2462288 4097 phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
a7909b39 4098 phba->params.cxns_per_ctrl, GFP_KERNEL);
6733b39a 4099 if (!phba->ep_array) {
99bc5d55
JSJ		 4100 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4101 "BM_%d : Failed to allocate memory in "
4102 "hba_setup_cid_tbls\n");
0a3db7c0
JK		 4103 ret = -ENOMEM;
4104
4105 goto free_memory;
6733b39a 4106 }
a7909b39
JK		 4107
4108 phba->conn_table = kzalloc(sizeof(struct beiscsi_conn *) *
4109 phba->params.cxns_per_ctrl, GFP_KERNEL);
4110 if (!phba->conn_table) {
4111 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4112 "BM_%d : Failed to allocate memory in"
4113 "hba_setup_cid_tbls\n");
4114
a7909b39 4115 kfree(phba->ep_array);
a7909b39 4116 phba->ep_array = NULL;
0a3db7c0 4117 ret = -ENOMEM;
5f2d25ef
TH		 4118
4119 goto free_memory;
6733b39a 4120 }
a7909b39 4121
0a3db7c0
JK		 4122 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
4123 ulp_num = phba->phwi_ctrlr->wrb_context[i].ulp_num;
4124
4125 ptr_cid_info = phba->cid_array_info[ulp_num];
4126 ptr_cid_info->cid_array[ptr_cid_info->cid_alloc++] =
4127 phba->phwi_ctrlr->wrb_context[i].cid;
4128
4129 }
4130
4131 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4132 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4133 ptr_cid_info = phba->cid_array_info[ulp_num];
a7909b39 4134
0a3db7c0
JK		 4135 ptr_cid_info->cid_alloc = 0;
4136 ptr_cid_info->cid_free = 0;
4137 }
4138 }
6733b39a 4139 return 0;
0a3db7c0
JK		 4140
4141free_memory:
4142 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4143 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4144 ptr_cid_info = phba->cid_array_info[ulp_num];
4145
4146 if (ptr_cid_info) {
4147 kfree(ptr_cid_info->cid_array);
4148 kfree(ptr_cid_info);
4149 phba->cid_array_info[ulp_num] = NULL;
4150 }
4151 }
4152 }
4153
4154 return ret;
6733b39a
JK		 4155}
4156
238f6b72 4157static void hwi_enable_intr(struct beiscsi_hba *phba)
6733b39a
JK		 4158{
4159 struct be_ctrl_info *ctrl = &phba->ctrl;
4160 struct hwi_controller *phwi_ctrlr;
4161 struct hwi_context_memory *phwi_context;
4162 struct be_queue_info *eq;
4163 u8 __iomem *addr;
bfead3b2 4164 u32 reg, i;
6733b39a
JK		 4165 u32 enabled;
4166
4167 phwi_ctrlr = phba->phwi_ctrlr;
4168 phwi_context = phwi_ctrlr->phwi_ctxt;
4169
6733b39a
JK		 4170 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
4171 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
4172 reg = ioread32(addr);
6733b39a
JK		 4173
4174 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4175 if (!enabled) {
4176 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
99bc5d55
JSJ		 4177 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4178 "BM_%d : reg =x%08x addr=%p\n", reg, addr);
6733b39a 4179 iowrite32(reg, addr);
665d6d94
JK		 4180 }
4181
4182 if (!phba->msix_enabled) {
4183 eq = &phwi_context->be_eq[0].q;
99bc5d55
JSJ		 4184 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4185 "BM_%d : eq->id=%d\n", eq->id);
4186
665d6d94
JK		 4187 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
4188 } else {
4189 for (i = 0; i <= phba->num_cpus; i++) {
4190 eq = &phwi_context->be_eq[i].q;
99bc5d55
JSJ		 4191 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4192 "BM_%d : eq->id=%d\n", eq->id);
bfead3b2
JK		 4193 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
4194 }
c03af1ae 4195 }
6733b39a
JK		 4196}
4197
4198static void hwi_disable_intr(struct beiscsi_hba *phba)
4199{
4200 struct be_ctrl_info *ctrl = &phba->ctrl;
4201
4202 u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
4203 u32 reg = ioread32(addr);
4204
4205 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4206 if (enabled) {
4207 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4208 iowrite32(reg, addr);
4209 } else
99bc5d55
JSJ		 4210 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
4211 "BM_%d : In hwi_disable_intr, Already Disabled\n");
6733b39a
JK		 4212}
4213
4214static int beiscsi_init_port(struct beiscsi_hba *phba)
4215{
4216 int ret;
4217
4218 ret = beiscsi_init_controller(phba);
4219 if (ret < 0) {
99bc5d55
JSJ		 4220 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4221 "BM_%d : beiscsi_dev_probe - Failed in"
4222 "beiscsi_init_controller\n");
6733b39a
JK		 4223 return ret;
4224 }
4225 ret = beiscsi_init_sgl_handle(phba);
4226 if (ret < 0) {
99bc5d55
JSJ		 4227 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4228 "BM_%d : beiscsi_dev_probe - Failed in"
4229 "beiscsi_init_sgl_handle\n");
6733b39a
JK		 4230 goto do_cleanup_ctrlr;
4231 }
4232
4233 if (hba_setup_cid_tbls(phba)) {
99bc5d55
JSJ		 4234 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4235 "BM_%d : Failed in hba_setup_cid_tbls\n");
6733b39a
JK		 4236 kfree(phba->io_sgl_hndl_base);
4237 kfree(phba->eh_sgl_hndl_base);
4238 goto do_cleanup_ctrlr;
4239 }
4240
4241 return ret;
4242
4243do_cleanup_ctrlr:
4d2ee1e6 4244 hwi_cleanup_port(phba);
6733b39a
JK		 4245 return ret;
4246}
4247
4d2ee1e6 4248static void beiscsi_cleanup_port(struct beiscsi_hba *phba)
6733b39a 4249{
0a3db7c0 4250 struct ulp_cid_info *ptr_cid_info = NULL;
f79929de 4251 int ulp_num;
6733b39a 4252
6733b39a
JK		 4253 kfree(phba->io_sgl_hndl_base);
4254 kfree(phba->eh_sgl_hndl_base);
6733b39a 4255 kfree(phba->ep_array);
a7909b39 4256 kfree(phba->conn_table);
0a3db7c0
JK		 4257
4258 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4259 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4260 ptr_cid_info = phba->cid_array_info[ulp_num];
4261
4262 if (ptr_cid_info) {
4263 kfree(ptr_cid_info->cid_array);
4264 kfree(ptr_cid_info);
4265 phba->cid_array_info[ulp_num] = NULL;
4266 }
4267 }
4268 }
6733b39a
JK		 4269}
4270
43f388b0
JK		 4271/**
4272 * beiscsi_free_mgmt_task_handles()- Free driver CXN resources
4273 * @beiscsi_conn: ptr to the conn to be cleaned up
4a4a11b9 4274 * @task: ptr to iscsi_task resource to be freed.
43f388b0
JK		 4275 *
4276 * Free driver mgmt resources binded to CXN.
4277 **/
4278void
4a4a11b9
JK		 4279beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
4280 struct iscsi_task *task)
43f388b0
JK		 4281{
4282 struct beiscsi_io_task *io_task;
4283 struct beiscsi_hba *phba = beiscsi_conn->phba;
4284 struct hwi_wrb_context *pwrb_context;
4285 struct hwi_controller *phwi_ctrlr;
a7909b39
JK		 4286 uint16_t cri_index = BE_GET_CRI_FROM_CID(
4287 beiscsi_conn->beiscsi_conn_cid);
43f388b0
JK		 4288
4289 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39
JK		 4290 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
4291
4a4a11b9 4292 io_task = task->dd_data;
43f388b0
JK		 4293
4294 if (io_task->pwrb_handle) {
e1f9d31e 4295 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
43f388b0
JK		 4296 io_task->pwrb_handle = NULL;
4297 }
4298
4299 if (io_task->psgl_handle) {
e1f9d31e 4300 free_mgmt_sgl_handle(phba, io_task->psgl_handle);
43f388b0
JK		 4301 io_task->psgl_handle = NULL;
4302 }
4303
eb1c4692 4304 if (io_task->mtask_addr) {
43f388b0
JK		 4305 pci_unmap_single(phba->pcidev,
4306 io_task->mtask_addr,
4307 io_task->mtask_data_count,
4308 PCI_DMA_TODEVICE);
eb1c4692
JSJ		 4309 io_task->mtask_addr = 0;
4310 }
43f388b0
JK		 4311}
4312
d629c471
JSJ		 4313/**
4314 * beiscsi_cleanup_task()- Free driver resources of the task
4315 * @task: ptr to the iscsi task
4316 *
4317 **/
1282ab76
MC		 4318static void beiscsi_cleanup_task(struct iscsi_task *task)
4319{
4320 struct beiscsi_io_task *io_task = task->dd_data;
4321 struct iscsi_conn *conn = task->conn;
4322 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4323 struct beiscsi_hba *phba = beiscsi_conn->phba;
4324 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
4325 struct hwi_wrb_context *pwrb_context;
4326 struct hwi_controller *phwi_ctrlr;
a7909b39
JK		 4327 uint16_t cri_index = BE_GET_CRI_FROM_CID(
4328 beiscsi_conn->beiscsi_conn_cid);
1282ab76
MC		 4329
4330 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 4331 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
1282ab76
MC		 4332
4333 if (io_task->cmd_bhs) {
4334 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
4335 io_task->bhs_pa.u.a64.address);
4336 io_task->cmd_bhs = NULL;
e1f9d31e 4337 task->hdr = NULL;
1282ab76
MC		 4338 }
4339
4340 if (task->sc) {
4341 if (io_task->pwrb_handle) {
4342 free_wrb_handle(phba, pwrb_context,
4343 io_task->pwrb_handle);
4344 io_task->pwrb_handle = NULL;
4345 }
4346
4347 if (io_task->psgl_handle) {
1282ab76 4348 free_io_sgl_handle(phba, io_task->psgl_handle);
1282ab76
MC		 4349 io_task->psgl_handle = NULL;
4350 }
da334977
JK		 4351
4352 if (io_task->scsi_cmnd) {
9122e991
JB		 4353 if (io_task->num_sg)
4354 scsi_dma_unmap(io_task->scsi_cmnd);
da334977
JK		 4355 io_task->scsi_cmnd = NULL;
4356 }
1282ab76 4357 } else {
43f388b0 4358 if (!beiscsi_conn->login_in_progress)
4a4a11b9 4359 beiscsi_free_mgmt_task_handles(beiscsi_conn, task);
1282ab76
MC		 4360 }
4361}
4362
6733b39a
JK		 4363void
4364beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
4365 struct beiscsi_offload_params *params)
4366{
4367 struct wrb_handle *pwrb_handle;
340c99e9 4368 struct hwi_wrb_context *pwrb_context = NULL;
6733b39a 4369 struct beiscsi_hba *phba = beiscsi_conn->phba;
1282ab76
MC		 4370 struct iscsi_task *task = beiscsi_conn->task;
4371 struct iscsi_session *session = task->conn->session;
6733b39a
JK		 4372 u32 doorbell = 0;
4373
4374 /*
4375 * We can always use 0 here because it is reserved by libiscsi for
4376 * login/startup related tasks.
4377 */
1282ab76 4378 beiscsi_conn->login_in_progress = 0;
659743b0 4379 spin_lock_bh(&session->back_lock);
1282ab76 4380 beiscsi_cleanup_task(task);
659743b0 4381 spin_unlock_bh(&session->back_lock);
1282ab76 4382
340c99e9
JSJ		 4383 pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid,
4384 &pwrb_context);
6733b39a 4385
acb9693c 4386 /* Check for the adapter family */
2c9dfd36 4387 if (is_chip_be2_be3r(phba))
acb9693c 4388 beiscsi_offload_cxn_v0(params, pwrb_handle,
340c99e9
JSJ		 4389 phba->init_mem,
4390 pwrb_context);
2c9dfd36 4391 else
340c99e9
JSJ		 4392 beiscsi_offload_cxn_v2(params, pwrb_handle,
4393 pwrb_context);
6733b39a 4394
acb9693c
JSJ		 4395 be_dws_le_to_cpu(pwrb_handle->pwrb,
4396 sizeof(struct iscsi_target_context_update_wrb));
6733b39a
JK		 4397
4398 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 4399 doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
bfead3b2 4400 << DB_DEF_PDU_WRB_INDEX_SHIFT;
6733b39a 4401 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4402 iowrite32(doorbell, phba->db_va +
4403 beiscsi_conn->doorbell_offset);
cb564c6b
JB		 4404
4405 /*
4406 * There is no completion for CONTEXT_UPDATE. The completion of next
4407 * WRB posted guarantees FW's processing and DMA'ing of it.
4408 * Use beiscsi_put_wrb_handle to put it back in the pool which makes
4409 * sure zero'ing or reuse of the WRB only after wrbs_per_cxn.
4410 */
4411 beiscsi_put_wrb_handle(pwrb_context, pwrb_handle,
4412 phba->params.wrbs_per_cxn);
4413 beiscsi_log(phba, KERN_INFO,
4414 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4415 "BM_%d : put CONTEXT_UPDATE pwrb_handle=%p free_index=0x%x wrb_handles_available=%d\n",
4416 pwrb_handle, pwrb_context->free_index,
4417 pwrb_context->wrb_handles_available);
6733b39a
JK		 4418}
4419
4420static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
4421 int *index, int *age)
4422{
bfead3b2 4423 *index = (int)itt;
6733b39a
JK		 4424 if (age)
4425 *age = conn->session->age;
4426}
4427
4428/**
4429 * beiscsi_alloc_pdu - allocates pdu and related resources
4430 * @task: libiscsi task
4431 * @opcode: opcode of pdu for task
4432 *
4433 * This is called with the session lock held. It will allocate
4434 * the wrb and sgl if needed for the command. And it will prep
4435 * the pdu's itt. beiscsi_parse_pdu will later translate
4436 * the pdu itt to the libiscsi task itt.
4437 */
4438static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
4439{
4440 struct beiscsi_io_task *io_task = task->dd_data;
4441 struct iscsi_conn *conn = task->conn;
4442 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4443 struct beiscsi_hba *phba = beiscsi_conn->phba;
4444 struct hwi_wrb_context *pwrb_context;
4445 struct hwi_controller *phwi_ctrlr;
4446 itt_t itt;
a7909b39 4447 uint16_t cri_index = 0;
2afc95bf
JK		 4448 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
4449 dma_addr_t paddr;
6733b39a 4450
2afc95bf 4451 io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
bc7accec 4452 GFP_ATOMIC, &paddr);
2afc95bf
JK		 4453 if (!io_task->cmd_bhs)
4454 return -ENOMEM;
2afc95bf 4455 io_task->bhs_pa.u.a64.address = paddr;
bfead3b2 4456 io_task->libiscsi_itt = (itt_t)task->itt;
6733b39a
JK		 4457 io_task->conn = beiscsi_conn;
4458
4459 task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
4460 task->hdr_max = sizeof(struct be_cmd_bhs);
d2cecf0d 4461 io_task->psgl_handle = NULL;
3ec78271 4462 io_task->pwrb_handle = NULL;
6733b39a
JK		 4463
4464 if (task->sc) {
6733b39a 4465 io_task->psgl_handle = alloc_io_sgl_handle(phba);
8359c79b
JSJ		 4466 if (!io_task->psgl_handle) {
4467 beiscsi_log(phba, KERN_ERR,
4468 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4469 "BM_%d : Alloc of IO_SGL_ICD Failed"
4470 "for the CID : %d\n",
4471 beiscsi_conn->beiscsi_conn_cid);
2afc95bf 4472 goto free_hndls;
8359c79b 4473 }
d2cecf0d 4474 io_task->pwrb_handle = alloc_wrb_handle(phba,
340c99e9
JSJ		 4475 beiscsi_conn->beiscsi_conn_cid,
4476 &io_task->pwrb_context);
8359c79b
JSJ		 4477 if (!io_task->pwrb_handle) {
4478 beiscsi_log(phba, KERN_ERR,
4479 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4480 "BM_%d : Alloc of WRB_HANDLE Failed"
4481 "for the CID : %d\n",
4482 beiscsi_conn->beiscsi_conn_cid);
d2cecf0d 4483 goto free_io_hndls;
8359c79b 4484 }
6733b39a
JK		 4485 } else {
4486 io_task->scsi_cmnd = NULL;
d7aea67b 4487 if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
43f388b0 4488 beiscsi_conn->task = task;
6733b39a 4489 if (!beiscsi_conn->login_in_progress) {
6733b39a
JK		 4490 io_task->psgl_handle = (struct sgl_handle *)
4491 alloc_mgmt_sgl_handle(phba);
8359c79b
JSJ		 4492 if (!io_task->psgl_handle) {
4493 beiscsi_log(phba, KERN_ERR,
4494 BEISCSI_LOG_IO |
4495 BEISCSI_LOG_CONFIG,
4496 "BM_%d : Alloc of MGMT_SGL_ICD Failed"
4497 "for the CID : %d\n",
4498 beiscsi_conn->
4499 beiscsi_conn_cid);
2afc95bf 4500 goto free_hndls;
8359c79b 4501 }
2afc95bf 4502
6733b39a
JK		 4503 beiscsi_conn->login_in_progress = 1;
4504 beiscsi_conn->plogin_sgl_handle =
4505 io_task->psgl_handle;
d2cecf0d
JK		 4506 io_task->pwrb_handle =
4507 alloc_wrb_handle(phba,
340c99e9
JSJ		 4508 beiscsi_conn->beiscsi_conn_cid,
4509 &io_task->pwrb_context);
8359c79b
JSJ		 4510 if (!io_task->pwrb_handle) {
4511 beiscsi_log(phba, KERN_ERR,
4512 BEISCSI_LOG_IO |
4513 BEISCSI_LOG_CONFIG,
4514 "BM_%d : Alloc of WRB_HANDLE Failed"
4515 "for the CID : %d\n",
4516 beiscsi_conn->
4517 beiscsi_conn_cid);
4518 goto free_mgmt_hndls;
4519 }
d2cecf0d
JK		 4520 beiscsi_conn->plogin_wrb_handle =
4521 io_task->pwrb_handle;
4522
6733b39a
JK		 4523 } else {
4524 io_task->psgl_handle =
4525 beiscsi_conn->plogin_sgl_handle;
d2cecf0d
JK		 4526 io_task->pwrb_handle =
4527 beiscsi_conn->plogin_wrb_handle;
6733b39a
JK		 4528 }
4529 } else {
6733b39a 4530 io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
8359c79b
JSJ		 4531 if (!io_task->psgl_handle) {
4532 beiscsi_log(phba, KERN_ERR,
4533 BEISCSI_LOG_IO |
4534 BEISCSI_LOG_CONFIG,
4535 "BM_%d : Alloc of MGMT_SGL_ICD Failed"
4536 "for the CID : %d\n",
4537 beiscsi_conn->
4538 beiscsi_conn_cid);
2afc95bf 4539 goto free_hndls;
8359c79b 4540 }
d2cecf0d
JK		 4541 io_task->pwrb_handle =
4542 alloc_wrb_handle(phba,
340c99e9
JSJ		 4543 beiscsi_conn->beiscsi_conn_cid,
4544 &io_task->pwrb_context);
8359c79b
JSJ		 4545 if (!io_task->pwrb_handle) {
4546 beiscsi_log(phba, KERN_ERR,
4547 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4548 "BM_%d : Alloc of WRB_HANDLE Failed"
4549 "for the CID : %d\n",
4550 beiscsi_conn->beiscsi_conn_cid);
d2cecf0d 4551 goto free_mgmt_hndls;
8359c79b 4552 }
d2cecf0d 4553
6733b39a
JK		 4554 }
4555 }
bfead3b2
JK		 4556 itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
4557 wrb_index << 16) | (unsigned int)
4558 (io_task->psgl_handle->sgl_index));
32951dd8 4559 io_task->pwrb_handle->pio_handle = task;
bfead3b2 4560
6733b39a
JK		 4561 io_task->cmd_bhs->iscsi_hdr.itt = itt;
4562 return 0;
2afc95bf 4563
d2cecf0d 4564free_io_hndls:
d2cecf0d 4565 free_io_sgl_handle(phba, io_task->psgl_handle);
d2cecf0d
JK		 4566 goto free_hndls;
4567free_mgmt_hndls:
d2cecf0d 4568 free_mgmt_sgl_handle(phba, io_task->psgl_handle);
a7909b39 4569 io_task->psgl_handle = NULL;
2afc95bf
JK		 4570free_hndls:
4571 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39
JK		 4572 cri_index = BE_GET_CRI_FROM_CID(
4573 beiscsi_conn->beiscsi_conn_cid);
4574 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
d2cecf0d
JK		 4575 if (io_task->pwrb_handle)
4576 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
2afc95bf
JK		 4577 io_task->pwrb_handle = NULL;
4578 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
4579 io_task->bhs_pa.u.a64.address);
1282ab76 4580 io_task->cmd_bhs = NULL;
2afc95bf 4581 return -ENOMEM;
6733b39a 4582}
09a1093a
JSJ		 4583int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg,
4584 unsigned int num_sg, unsigned int xferlen,
4585 unsigned int writedir)
4586{
4587
4588 struct beiscsi_io_task *io_task = task->dd_data;
4589 struct iscsi_conn *conn = task->conn;
4590 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4591 struct beiscsi_hba *phba = beiscsi_conn->phba;
4592 struct iscsi_wrb *pwrb = NULL;
4593 unsigned int doorbell = 0;
4594
4595 pwrb = io_task->pwrb_handle->pwrb;
09a1093a 4596
09a1093a
JSJ		 4597 io_task->bhs_len = sizeof(struct be_cmd_bhs);
4598
4599 if (writedir) {
4600 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
4601 INI_WR_CMD);
4602 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1);
4603 } else {
4604 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
4605 INI_RD_CMD);
4606 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0);
4607 }
4608
4609 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2,
4610 type, pwrb);
4611
4612 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb,
4613 cpu_to_be16(*(unsigned short *)
4614 &io_task->cmd_bhs->iscsi_hdr.lun));
4615 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen);
4616 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
4617 io_task->pwrb_handle->wrb_index);
4618 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
4619 be32_to_cpu(task->cmdsn));
4620 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
4621 io_task->psgl_handle->sgl_index);
4622
4623 hwi_write_sgl_v2(pwrb, sg, num_sg, io_task);
4624 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
340c99e9
JSJ		 4625 io_task->pwrb_handle->wrb_index);
4626 if (io_task->pwrb_context->plast_wrb)
4627 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb,
4628 io_task->pwrb_context->plast_wrb,
4629 io_task->pwrb_handle->wrb_index);
4630 io_task->pwrb_context->plast_wrb = pwrb;
09a1093a
JSJ		 4631
4632 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4633
4634 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
4635 doorbell |= (io_task->pwrb_handle->wrb_index &
4636 DB_DEF_PDU_WRB_INDEX_MASK) <<
4637 DB_DEF_PDU_WRB_INDEX_SHIFT;
4638 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4639 iowrite32(doorbell, phba->db_va +
4640 beiscsi_conn->doorbell_offset);
09a1093a
JSJ		 4641 return 0;
4642}
6733b39a 4643
6733b39a
JK		 4644static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
4645 unsigned int num_sg, unsigned int xferlen,
4646 unsigned int writedir)
4647{
4648
4649 struct beiscsi_io_task *io_task = task->dd_data;
4650 struct iscsi_conn *conn = task->conn;
4651 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4652 struct beiscsi_hba *phba = beiscsi_conn->phba;
4653 struct iscsi_wrb *pwrb = NULL;
4654 unsigned int doorbell = 0;
4655
4656 pwrb = io_task->pwrb_handle->pwrb;
6733b39a
JK		 4657 io_task->bhs_len = sizeof(struct be_cmd_bhs);
4658
4659 if (writedir) {
32951dd8
JK		 4660 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4661 INI_WR_CMD);
6733b39a 4662 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
6733b39a 4663 } else {
32951dd8
JK		 4664 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4665 INI_RD_CMD);
6733b39a
JK		 4666 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
4667 }
6733b39a 4668
09a1093a
JSJ		 4669 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb,
4670 type, pwrb);
4671
6733b39a 4672 AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
dc63aac6
JK		 4673 cpu_to_be16(*(unsigned short *)
4674 &io_task->cmd_bhs->iscsi_hdr.lun));
6733b39a
JK		 4675 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
4676 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
4677 io_task->pwrb_handle->wrb_index);
4678 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
4679 be32_to_cpu(task->cmdsn));
4680 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
4681 io_task->psgl_handle->sgl_index);
4682
4683 hwi_write_sgl(pwrb, sg, num_sg, io_task);
4684
4685 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
340c99e9
JSJ		 4686 io_task->pwrb_handle->wrb_index);
4687 if (io_task->pwrb_context->plast_wrb)
4688 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb,
4689 io_task->pwrb_context->plast_wrb,
4690 io_task->pwrb_handle->wrb_index);
4691 io_task->pwrb_context->plast_wrb = pwrb;
4692
6733b39a
JK		 4693 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4694
4695 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 4696 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 4697 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
4698 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
4699
1e4be6ff
JK		 4700 iowrite32(doorbell, phba->db_va +
4701 beiscsi_conn->doorbell_offset);
6733b39a
JK		 4702 return 0;
4703}
4704
4705static int beiscsi_mtask(struct iscsi_task *task)
4706{
dafab8e0 4707 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 4708 struct iscsi_conn *conn = task->conn;
4709 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4710 struct beiscsi_hba *phba = beiscsi_conn->phba;
4711 struct iscsi_wrb *pwrb = NULL;
4712 unsigned int doorbell = 0;
dafab8e0 4713 unsigned int cid;
09a1093a 4714 unsigned int pwrb_typeoffset = 0;
e0493627 4715 int ret = 0;
6733b39a 4716
bfead3b2 4717 cid = beiscsi_conn->beiscsi_conn_cid;
6733b39a 4718 pwrb = io_task->pwrb_handle->pwrb;
caf818f1 4719 memset(pwrb, 0, sizeof(*pwrb));
09a1093a 4720
2c9dfd36 4721 if (is_chip_be2_be3r(phba)) {
09a1093a
JSJ		 4722 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
4723 be32_to_cpu(task->cmdsn));
4724 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
4725 io_task->pwrb_handle->wrb_index);
4726 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
4727 io_task->psgl_handle->sgl_index);
4728 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
4729 task->data_count);
4730 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
340c99e9
JSJ		 4731 io_task->pwrb_handle->wrb_index);
4732 if (io_task->pwrb_context->plast_wrb)
4733 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb,
4734 io_task->pwrb_context->plast_wrb,
4735 io_task->pwrb_handle->wrb_index);
4736 io_task->pwrb_context->plast_wrb = pwrb;
4737
09a1093a 4738 pwrb_typeoffset = BE_WRB_TYPE_OFFSET;
2c9dfd36
JK		 4739 } else {
4740 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
4741 be32_to_cpu(task->cmdsn));
4742 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
4743 io_task->pwrb_handle->wrb_index);
4744 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
4745 io_task->psgl_handle->sgl_index);
4746 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb,
4747 task->data_count);
4748 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
340c99e9
JSJ		 4749 io_task->pwrb_handle->wrb_index);
4750 if (io_task->pwrb_context->plast_wrb)
4751 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb,
4752 io_task->pwrb_context->plast_wrb,
4753 io_task->pwrb_handle->wrb_index);
4754 io_task->pwrb_context->plast_wrb = pwrb;
4755
2c9dfd36 4756 pwrb_typeoffset = SKH_WRB_TYPE_OFFSET;
09a1093a
JSJ		 4757 }
4758
dafab8e0 4759
6733b39a
JK		 4760 switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
4761 case ISCSI_OP_LOGIN:
6733b39a 4762 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
09a1093a 4763 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
e0493627 4764 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 4765 break;
4766 case ISCSI_OP_NOOP_OUT:
1390b01b 4767 if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
09a1093a 4768 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
2c9dfd36
JK		 4769 if (is_chip_be2_be3r(phba))
4770 AMAP_SET_BITS(struct amap_iscsi_wrb,
09a1093a
JSJ		 4771 dmsg, pwrb, 1);
4772 else
2c9dfd36 4773 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
09a1093a 4774 dmsg, pwrb, 1);
1390b01b 4775 } else {
09a1093a 4776 ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset);
2c9dfd36
JK		 4777 if (is_chip_be2_be3r(phba))
4778 AMAP_SET_BITS(struct amap_iscsi_wrb,
09a1093a
JSJ		 4779 dmsg, pwrb, 0);
4780 else
2c9dfd36 4781 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
09a1093a 4782 dmsg, pwrb, 0);
1390b01b 4783 }
e0493627 4784 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 4785 break;
4786 case ISCSI_OP_TEXT:
09a1093a 4787 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
e0493627 4788 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 4789 break;
4790 case ISCSI_OP_SCSI_TMFUNC:
09a1093a 4791 ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset);
e0493627 4792 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 4793 break;
4794 case ISCSI_OP_LOGOUT:
09a1093a 4795 ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset);
e0493627 4796 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 4797 break;
4798
4799 default:
99bc5d55
JSJ		 4800 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
4801 "BM_%d : opcode =%d Not supported\n",
4802 task->hdr->opcode & ISCSI_OPCODE_MASK);
4803
6733b39a
JK		 4804 return -EINVAL;
4805 }
4806
e0493627
AK		 4807 if (ret)
4808 return ret;
4809
09a1093a 4810 /* Set the task type */
2c9dfd36
JK		 4811 io_task->wrb_type = (is_chip_be2_be3r(phba)) ?
4812 AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) :
4813 AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb);
6733b39a 4814
bfead3b2 4815 doorbell |= cid & DB_WRB_POST_CID_MASK;
32951dd8 4816 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 4817 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
4818 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4819 iowrite32(doorbell, phba->db_va +
4820 beiscsi_conn->doorbell_offset);
6733b39a
JK		 4821 return 0;
4822}
4823
4824static int beiscsi_task_xmit(struct iscsi_task *task)
4825{
6733b39a
JK		 4826 struct beiscsi_io_task *io_task = task->dd_data;
4827 struct scsi_cmnd *sc = task->sc;
1868379b 4828 struct beiscsi_hba *phba;
6733b39a
JK		 4829 struct scatterlist *sg;
4830 int num_sg;
4831 unsigned int writedir = 0, xferlen = 0;
4832
9122e991
JB		 4833 phba = io_task->conn->phba;
4834 /**
4835 * HBA in error includes BEISCSI_HBA_FW_TIMEOUT. IO path might be
4836 * operational if FW still gets heartbeat from EP FW. Is management
4837 * path really needed to continue further?
4838 */
d1d5ca88 4839 if (!beiscsi_hba_is_online(phba))
9122e991
JB		 4840 return -EIO;
4841
1868379b
JB		 4842 if (!io_task->conn->login_in_progress)
4843 task->hdr->exp_statsn = 0;
09a1093a 4844
6733b39a
JK		 4845 if (!sc)
4846 return beiscsi_mtask(task);
4847
4848 io_task->scsi_cmnd = sc;
9122e991 4849 io_task->num_sg = 0;
6733b39a
JK		 4850 num_sg = scsi_dma_map(sc);
4851 if (num_sg < 0) {
afb96058
JK		 4852 beiscsi_log(phba, KERN_ERR,
4853 BEISCSI_LOG_IO | BEISCSI_LOG_ISCSI,
4854 "BM_%d : scsi_dma_map Failed "
4855 "Driver_ITT : 0x%x ITT : 0x%x Xferlen : 0x%x\n",
4856 be32_to_cpu(io_task->cmd_bhs->iscsi_hdr.itt),
4857 io_task->libiscsi_itt, scsi_bufflen(sc));
99bc5d55 4858
6733b39a
JK		 4859 return num_sg;
4860 }
9122e991
JB		 4861 /**
4862 * For scsi cmd task, check num_sg before unmapping in cleanup_task.
4863 * For management task, cleanup_task checks mtask_addr before unmapping.
4864 */
4865 io_task->num_sg = num_sg;
6733b39a
JK		 4866 xferlen = scsi_bufflen(sc);
4867 sg = scsi_sglist(sc);
99bc5d55 4868 if (sc->sc_data_direction == DMA_TO_DEVICE)
6733b39a 4869 writedir = 1;
99bc5d55 4870 else
6733b39a 4871 writedir = 0;
99bc5d55 4872
09a1093a 4873 return phba->iotask_fn(task, sg, num_sg, xferlen, writedir);
6733b39a
JK		 4874}
4875
ffce3e2e
JK		 4876/**
4877 * beiscsi_bsg_request - handle bsg request from ISCSI transport
4878 * @job: job to handle
4879 */
4880static int beiscsi_bsg_request(struct bsg_job *job)
4881{
4882 struct Scsi_Host *shost;
4883 struct beiscsi_hba *phba;
4884 struct iscsi_bsg_request *bsg_req = job->request;
4885 int rc = -EINVAL;
4886 unsigned int tag;
4887 struct be_dma_mem nonemb_cmd;
4888 struct be_cmd_resp_hdr *resp;
4889 struct iscsi_bsg_reply *bsg_reply = job->reply;
4890 unsigned short status, extd_status;
4891
4892 shost = iscsi_job_to_shost(job);
4893 phba = iscsi_host_priv(shost);
4894
d1d5ca88 4895 if (!beiscsi_hba_is_online(phba)) {
9122e991
JB		 4896 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
4897 "BM_%d : HBA in error 0x%lx\n", phba->state);
4898 return -ENXIO;
4899 }
4900
ffce3e2e
JK		 4901 switch (bsg_req->msgcode) {
4902 case ISCSI_BSG_HST_VENDOR:
4903 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
4904 job->request_payload.payload_len,
4905 &nonemb_cmd.dma);
4906 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 4907 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
4908 "BM_%d : Failed to allocate memory for "
4909 "beiscsi_bsg_request\n");
8359c79b 4910 return -ENOMEM;
ffce3e2e
JK		 4911 }
4912 tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
4913 &nonemb_cmd);
4914 if (!tag) {
99bc5d55 4915 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
8359c79b 4916 "BM_%d : MBX Tag Allocation Failed\n");
99bc5d55 4917
ffce3e2e
JK		 4918 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
4919 nonemb_cmd.va, nonemb_cmd.dma);
4920 return -EAGAIN;
e175defe
JSJ		 4921 }
4922
4923 rc = wait_event_interruptible_timeout(
4924 phba->ctrl.mcc_wait[tag],
67296ad9 4925 phba->ctrl.mcc_tag_status[tag],
e175defe
JSJ		 4926 msecs_to_jiffies(
4927 BEISCSI_HOST_MBX_TIMEOUT));
d1d5ca88
JB		 4928
4929 if (!test_bit(BEISCSI_HBA_ONLINE, &phba->state)) {
4930 clear_bit(MCC_TAG_STATE_RUNNING,
4931 &phba->ctrl.ptag_state[tag].tag_state);
4932 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
4933 nonemb_cmd.va, nonemb_cmd.dma);
4934 return -EIO;
4935 }
67296ad9
JB		 4936 extd_status = (phba->ctrl.mcc_tag_status[tag] &
4937 CQE_STATUS_ADDL_MASK) >> CQE_STATUS_ADDL_SHIFT;
4938 status = phba->ctrl.mcc_tag_status[tag] & CQE_STATUS_MASK;
090e2184 4939 free_mcc_wrb(&phba->ctrl, tag);
ffce3e2e
JK		 4940 resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
4941 sg_copy_from_buffer(job->reply_payload.sg_list,
4942 job->reply_payload.sg_cnt,
4943 nonemb_cmd.va, (resp->response_length
4944 + sizeof(*resp)));
4945 bsg_reply->reply_payload_rcv_len = resp->response_length;
4946 bsg_reply->result = status;
4947 bsg_job_done(job, bsg_reply->result,
4948 bsg_reply->reply_payload_rcv_len);
4949 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
4950 nonemb_cmd.va, nonemb_cmd.dma);
4951 if (status || extd_status) {
99bc5d55 4952 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
8359c79b 4953 "BM_%d : MBX Cmd Failed"
99bc5d55
JSJ		 4954 " status = %d extd_status = %d\n",
4955 status, extd_status);
4956
ffce3e2e 4957 return -EIO;
8359c79b
JSJ		 4958 } else {
4959 rc = 0;
ffce3e2e
JK		 4960 }
4961 break;
4962
4963 default:
99bc5d55
JSJ		 4964 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
4965 "BM_%d : Unsupported bsg command: 0x%x\n",
4966 bsg_req->msgcode);
ffce3e2e
JK		 4967 break;
4968 }
4969
4970 return rc;
4971}
4972
99bc5d55
JSJ		 4973void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
4974{
4975 /* Set the logging parameter */
4976 beiscsi_log_enable_init(phba, beiscsi_log_enable);
4977}
4978
d1d5ca88 4979void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle)
6733b39a 4980{
d1d5ca88
JB		 4981 if (phba->boot_struct.boot_kset)
4982 return;
50a4b824
JB		 4983
4984 /* skip if boot work is already in progress */
4985 if (test_and_set_bit(BEISCSI_HBA_BOOT_WORK, &phba->state))
4986 return;
4987
4988 phba->boot_struct.retry = 3;
4989 phba->boot_struct.tag = 0;
4990 phba->boot_struct.s_handle = s_handle;
4991 phba->boot_struct.action = BEISCSI_BOOT_GET_SHANDLE;
4992 schedule_work(&phba->boot_work);
4993}
4994
4995static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
4996{
4997 struct beiscsi_hba *phba = data;
4998 struct mgmt_session_info *boot_sess = &phba->boot_struct.boot_sess;
4999 struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
5000 char *str = buf;
5001 int rc = -EPERM;
5002
5003 switch (type) {
5004 case ISCSI_BOOT_TGT_NAME:
5005 rc = sprintf(buf, "%.*s\n",
5006 (int)strlen(boot_sess->target_name),
5007 (char *)&boot_sess->target_name);
5008 break;
5009 case ISCSI_BOOT_TGT_IP_ADDR:
5010 if (boot_conn->dest_ipaddr.ip_type == BEISCSI_IP_TYPE_V4)
5011 rc = sprintf(buf, "%pI4\n",
5012 (char *)&boot_conn->dest_ipaddr.addr);
5013 else
5014 rc = sprintf(str, "%pI6\n",
5015 (char *)&boot_conn->dest_ipaddr.addr);
5016 break;
5017 case ISCSI_BOOT_TGT_PORT:
5018 rc = sprintf(str, "%d\n", boot_conn->dest_port);
5019 break;
5020
5021 case ISCSI_BOOT_TGT_CHAP_NAME:
5022 rc = sprintf(str, "%.*s\n",
5023 boot_conn->negotiated_login_options.auth_data.chap.
5024 target_chap_name_length,
5025 (char *)&boot_conn->negotiated_login_options.
5026 auth_data.chap.target_chap_name);
5027 break;
5028 case ISCSI_BOOT_TGT_CHAP_SECRET:
5029 rc = sprintf(str, "%.*s\n",
5030 boot_conn->negotiated_login_options.auth_data.chap.
5031 target_secret_length,
5032 (char *)&boot_conn->negotiated_login_options.
5033 auth_data.chap.target_secret);
5034 break;
5035 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
5036 rc = sprintf(str, "%.*s\n",
5037 boot_conn->negotiated_login_options.auth_data.chap.
5038 intr_chap_name_length,
5039 (char *)&boot_conn->negotiated_login_options.
5040 auth_data.chap.intr_chap_name);
5041 break;
5042 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
5043 rc = sprintf(str, "%.*s\n",
5044 boot_conn->negotiated_login_options.auth_data.chap.
5045 intr_secret_length,
5046 (char *)&boot_conn->negotiated_login_options.
5047 auth_data.chap.intr_secret);
5048 break;
5049 case ISCSI_BOOT_TGT_FLAGS:
5050 rc = sprintf(str, "2\n");
5051 break;
5052 case ISCSI_BOOT_TGT_NIC_ASSOC:
5053 rc = sprintf(str, "0\n");
5054 break;
5055 }
5056 return rc;
5057}
5058
5059static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
5060{
5061 struct beiscsi_hba *phba = data;
5062 char *str = buf;
5063 int rc = -EPERM;
5064
5065 switch (type) {
5066 case ISCSI_BOOT_INI_INITIATOR_NAME:
5067 rc = sprintf(str, "%s\n",
5068 phba->boot_struct.boot_sess.initiator_iscsiname);
5069 break;
5070 }
5071 return rc;
5072}
5073
5074static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
5075{
5076 struct beiscsi_hba *phba = data;
5077 char *str = buf;
5078 int rc = -EPERM;
5079
5080 switch (type) {
5081 case ISCSI_BOOT_ETH_FLAGS:
5082 rc = sprintf(str, "2\n");
5083 break;
5084 case ISCSI_BOOT_ETH_INDEX:
5085 rc = sprintf(str, "0\n");
5086 break;
5087 case ISCSI_BOOT_ETH_MAC:
5088 rc = beiscsi_get_macaddr(str, phba);
5089 break;
5090 }
5091 return rc;
5092}
5093
50a4b824
JB		 5094static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
5095{
5096 umode_t rc = 0;
5097
5098 switch (type) {
5099 case ISCSI_BOOT_TGT_NAME:
5100 case ISCSI_BOOT_TGT_IP_ADDR:
5101 case ISCSI_BOOT_TGT_PORT:
5102 case ISCSI_BOOT_TGT_CHAP_NAME:
5103 case ISCSI_BOOT_TGT_CHAP_SECRET:
5104 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
5105 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
5106 case ISCSI_BOOT_TGT_NIC_ASSOC:
5107 case ISCSI_BOOT_TGT_FLAGS:
5108 rc = S_IRUGO;
5109 break;
5110 }
5111 return rc;
5112}
5113
5114static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
5115{
5116 umode_t rc = 0;
5117
5118 switch (type) {
5119 case ISCSI_BOOT_INI_INITIATOR_NAME:
5120 rc = S_IRUGO;
5121 break;
5122 }
5123 return rc;
5124}
5125
50a4b824
JB		 5126static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
5127{
5128 umode_t rc = 0;
5129
5130 switch (type) {
5131 case ISCSI_BOOT_ETH_FLAGS:
5132 case ISCSI_BOOT_ETH_MAC:
5133 case ISCSI_BOOT_ETH_INDEX:
5134 rc = S_IRUGO;
5135 break;
5136 }
5137 return rc;
5138}
5139
5140static void beiscsi_boot_kobj_release(void *data)
5141{
5142 struct beiscsi_hba *phba = data;
5143
5144 scsi_host_put(phba->shost);
5145}
5146
5147static int beiscsi_boot_create_kset(struct beiscsi_hba *phba)
5148{
5149 struct boot_struct *bs = &phba->boot_struct;
5150 struct iscsi_boot_kobj *boot_kobj;
5151
5152 if (bs->boot_kset) {
5153 __beiscsi_log(phba, KERN_ERR,
5154 "BM_%d: boot_kset already created\n");
5155 return 0;
5156 }
5157
5158 bs->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
5159 if (!bs->boot_kset) {
5160 __beiscsi_log(phba, KERN_ERR,
5161 "BM_%d: boot_kset alloc failed\n");
5162 return -ENOMEM;
5163 }
5164
5165 /* get shost ref because the show function will refer phba */
5166 if (!scsi_host_get(phba->shost))
5167 goto free_kset;
5168
5169 boot_kobj = iscsi_boot_create_target(bs->boot_kset, 0, phba,
5170 beiscsi_show_boot_tgt_info,
5171 beiscsi_tgt_get_attr_visibility,
5172 beiscsi_boot_kobj_release);
5173 if (!boot_kobj)
5174 goto put_shost;
5175
5176 if (!scsi_host_get(phba->shost))
5177 goto free_kset;
5178
5179 boot_kobj = iscsi_boot_create_initiator(bs->boot_kset, 0, phba,
5180 beiscsi_show_boot_ini_info,
5181 beiscsi_ini_get_attr_visibility,
5182 beiscsi_boot_kobj_release);
5183 if (!boot_kobj)
5184 goto put_shost;
5185
5186 if (!scsi_host_get(phba->shost))
5187 goto free_kset;
5188
5189 boot_kobj = iscsi_boot_create_ethernet(bs->boot_kset, 0, phba,
5190 beiscsi_show_boot_eth_info,
5191 beiscsi_eth_get_attr_visibility,
5192 beiscsi_boot_kobj_release);
5193 if (!boot_kobj)
5194 goto put_shost;
5195
5196 return 0;
5197
5198put_shost:
5199 scsi_host_put(phba->shost);
5200free_kset:
5201 iscsi_boot_destroy_kset(bs->boot_kset);
5202 bs->boot_kset = NULL;
5203 return -ENOMEM;
5204}
5205
5206static void beiscsi_boot_work(struct work_struct *work)
5207{
5208 struct beiscsi_hba *phba =
5209 container_of(work, struct beiscsi_hba, boot_work);
5210 struct boot_struct *bs = &phba->boot_struct;
5211 unsigned int tag = 0;
5212
d1d5ca88 5213 if (!beiscsi_hba_is_online(phba))
50a4b824
JB		 5214 return;
5215
5216 beiscsi_log(phba, KERN_INFO,
5217 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
5218 "BM_%d : %s action %d\n",
5219 __func__, phba->boot_struct.action);
5220
5221 switch (phba->boot_struct.action) {
5222 case BEISCSI_BOOT_REOPEN_SESS:
5223 tag = beiscsi_boot_reopen_sess(phba);
5224 break;
5225 case BEISCSI_BOOT_GET_SHANDLE:
5226 tag = __beiscsi_boot_get_shandle(phba, 1);
5227 break;
5228 case BEISCSI_BOOT_GET_SINFO:
5229 tag = beiscsi_boot_get_sinfo(phba);
5230 break;
5231 case BEISCSI_BOOT_LOGOUT_SESS:
5232 tag = beiscsi_boot_logout_sess(phba);
5233 break;
5234 case BEISCSI_BOOT_CREATE_KSET:
5235 beiscsi_boot_create_kset(phba);
5236 /**
5237 * updated boot_kset is made visible to all before
5238 * ending the boot work.
5239 */
5240 mb();
5241 clear_bit(BEISCSI_HBA_BOOT_WORK, &phba->state);
5242 return;
5243 }
5244 if (!tag) {
5245 if (bs->retry--)
5246 schedule_work(&phba->boot_work);
5247 else
5248 clear_bit(BEISCSI_HBA_BOOT_WORK, &phba->state);
5249 }
5250}
5251
10bcd47d
JB		 5252static void beiscsi_eqd_update_work(struct work_struct *work)
5253{
5254 struct hwi_context_memory *phwi_context;
73af08e1 5255 struct be_set_eqd set_eqd[MAX_CPUS];
73af08e1 5256 struct hwi_controller *phwi_ctrlr;
10bcd47d
JB		 5257 struct be_eq_obj *pbe_eq;
5258 struct beiscsi_hba *phba;
5259 unsigned int pps, delta;
5260 struct be_aic_obj *aic;
73af08e1 5261 int eqd, i, num = 0;
10bcd47d 5262 unsigned long now;
73af08e1 5263
10bcd47d 5264 phba = container_of(work, struct beiscsi_hba, eqd_update.work);
d1d5ca88 5265 if (!beiscsi_hba_is_online(phba))
9122e991
JB		 5266 return;
5267
73af08e1
JK		 5268 phwi_ctrlr = phba->phwi_ctrlr;
5269 phwi_context = phwi_ctrlr->phwi_ctxt;
5270
5271 for (i = 0; i <= phba->num_cpus; i++) {
5272 aic = &phba->aic_obj[i];
5273 pbe_eq = &phwi_context->be_eq[i];
5274 now = jiffies;
10bcd47d 5275 if (!aic->jiffies || time_before(now, aic->jiffies) ||
73af08e1 5276 pbe_eq->cq_count < aic->eq_prev) {
10bcd47d 5277 aic->jiffies = now;
73af08e1
JK		 5278 aic->eq_prev = pbe_eq->cq_count;
5279 continue;
5280 }
10bcd47d 5281 delta = jiffies_to_msecs(now - aic->jiffies);
73af08e1
JK		 5282 pps = (((u32)(pbe_eq->cq_count - aic->eq_prev) * 1000) / delta);
5283 eqd = (pps / 1500) << 2;
5284
5285 if (eqd < 8)
5286 eqd = 0;
5287 eqd = min_t(u32, eqd, phwi_context->max_eqd);
5288 eqd = max_t(u32, eqd, phwi_context->min_eqd);
5289
10bcd47d 5290 aic->jiffies = now;
73af08e1
JK		 5291 aic->eq_prev = pbe_eq->cq_count;
5292
5293 if (eqd != aic->prev_eqd) {
5294 set_eqd[num].delay_multiplier = (eqd * 65)/100;
5295 set_eqd[num].eq_id = pbe_eq->q.id;
5296 aic->prev_eqd = eqd;
5297 num++;
5298 }
5299 }
10bcd47d
JB		 5300 if (num)
5301 /* completion of this is ignored */
5302 beiscsi_modify_eq_delay(phba, set_eqd, num);
73af08e1 5303
10bcd47d
JB		 5304 schedule_delayed_work(&phba->eqd_update,
5305 msecs_to_jiffies(BEISCSI_EQD_UPDATE_INTERVAL));
7a158003
JSJ		 5306}
5307
d1d5ca88
JB		 5308static void beiscsi_msix_enable(struct beiscsi_hba *phba)
5309{
5310 int i, status;
5311
5312 for (i = 0; i <= phba->num_cpus; i++)
5313 phba->msix_entries[i].entry = i;
5314
5315 status = pci_enable_msix_range(phba->pcidev, phba->msix_entries,
5316 phba->num_cpus + 1, phba->num_cpus + 1);
5317 if (status > 0)
5318 phba->msix_enabled = true;
5319}
5320
5321static void beiscsi_hw_tpe_check(unsigned long ptr)
5322{
5323 struct beiscsi_hba *phba;
5324 u32 wait;
5325
5326 phba = (struct beiscsi_hba *)ptr;
5327 /* if not TPE, do nothing */
5328 if (!beiscsi_detect_tpe(phba))
5329 return;
5330
5331 /* wait default 4000ms before recovering */
5332 wait = 4000;
5333 if (phba->ue2rp > BEISCSI_UE_DETECT_INTERVAL)
5334 wait = phba->ue2rp - BEISCSI_UE_DETECT_INTERVAL;
5335 queue_delayed_work(phba->wq, &phba->recover_port,
5336 msecs_to_jiffies(wait));
5337}
5338
5339static void beiscsi_hw_health_check(unsigned long ptr)
5340{
5341 struct beiscsi_hba *phba;
5342
5343 phba = (struct beiscsi_hba *)ptr;
5344 beiscsi_detect_ue(phba);
5345 if (beiscsi_detect_ue(phba)) {
5346 __beiscsi_log(phba, KERN_ERR,
5347 "BM_%d : port in error: %lx\n", phba->state);
10e1a44a
JB		 5348 /* sessions are no longer valid, so first fail the sessions */
5349 queue_work(phba->wq, &phba->sess_work);
5350
5351 /* detect UER supported */
d1d5ca88
JB		 5352 if (!test_bit(BEISCSI_HBA_UER_SUPP, &phba->state))
5353 return;
5354 /* modify this timer to check TPE */
5355 phba->hw_check.function = beiscsi_hw_tpe_check;
5356 }
5357
5358 mod_timer(&phba->hw_check,
5359 jiffies + msecs_to_jiffies(BEISCSI_UE_DETECT_INTERVAL));
5360}
5361
5362/*
5363 * beiscsi_enable_port()- Enables the disabled port.
5364 * Only port resources freed in disable function are reallocated.
5365 * This is called in HBA error handling path.
5366 *
5367 * @phba: Instance of driver private structure
5368 *
5369 **/
5370static int beiscsi_enable_port(struct beiscsi_hba *phba)
5371{
5372 struct hwi_context_memory *phwi_context;
5373 struct hwi_controller *phwi_ctrlr;
5374 struct be_eq_obj *pbe_eq;
5375 int ret, i;
5376
5377 if (test_bit(BEISCSI_HBA_ONLINE, &phba->state)) {
5378 __beiscsi_log(phba, KERN_ERR,
5379 "BM_%d : %s : port is online %lx\n",
5380 __func__, phba->state);
5381 return 0;
5382 }
5383
5384 ret = beiscsi_init_sliport(phba);
5385 if (ret)
5386 return ret;
5387
5388 if (enable_msix)
5389 find_num_cpus(phba);
5390 else
5391 phba->num_cpus = 1;
5392 if (enable_msix) {
5393 beiscsi_msix_enable(phba);
5394 if (!phba->msix_enabled)
5395 phba->num_cpus = 1;
5396 }
5397
5398 beiscsi_get_params(phba);
5399 /* Re-enable UER. If different TPE occurs then it is recoverable. */
5400 beiscsi_set_uer_feature(phba);
5401
5402 phba->shost->max_id = phba->params.cxns_per_ctrl;
5403 phba->shost->can_queue = phba->params.ios_per_ctrl;
5404 ret = hwi_init_controller(phba);
5405 if (ret) {
5406 __beiscsi_log(phba, KERN_ERR,
5407 "BM_%d : init controller failed %d\n", ret);
5408 goto disable_msix;
5409 }
5410
5411 for (i = 0; i < MAX_MCC_CMD; i++) {
5412 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5413 phba->ctrl.mcc_tag[i] = i + 1;
5414 phba->ctrl.mcc_tag_status[i + 1] = 0;
5415 phba->ctrl.mcc_tag_available++;
5416 }
5417
5418 phwi_ctrlr = phba->phwi_ctrlr;
5419 phwi_context = phwi_ctrlr->phwi_ctxt;
5420 for (i = 0; i < phba->num_cpus; i++) {
5421 pbe_eq = &phwi_context->be_eq[i];
5422 irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget, be_iopoll);
5423 }
5424
5425 i = (phba->msix_enabled) ? i : 0;
5426 /* Work item for MCC handling */
5427 pbe_eq = &phwi_context->be_eq[i];
5428 INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work);
5429
5430 ret = beiscsi_init_irqs(phba);
5431 if (ret < 0) {
5432 __beiscsi_log(phba, KERN_ERR,
5433 "BM_%d : setup IRQs failed %d\n", ret);
5434 goto cleanup_port;
5435 }
5436 hwi_enable_intr(phba);
5437 /* port operational: clear all error bits */
5438 set_bit(BEISCSI_HBA_ONLINE, &phba->state);
5439 __beiscsi_log(phba, KERN_INFO,
5440 "BM_%d : port online: 0x%lx\n", phba->state);
5441
5442 /* start hw_check timer and eqd_update work */
5443 schedule_delayed_work(&phba->eqd_update,
5444 msecs_to_jiffies(BEISCSI_EQD_UPDATE_INTERVAL));
5445
5446 /**
5447 * Timer function gets modified for TPE detection.
5448 * Always reinit to do health check first.
5449 */
5450 phba->hw_check.function = beiscsi_hw_health_check;
5451 mod_timer(&phba->hw_check,
5452 jiffies + msecs_to_jiffies(BEISCSI_UE_DETECT_INTERVAL));
5453 return 0;
5454
5455cleanup_port:
5456 for (i = 0; i < phba->num_cpus; i++) {
5457 pbe_eq = &phwi_context->be_eq[i];
5458 irq_poll_disable(&pbe_eq->iopoll);
5459 }
5460 hwi_cleanup_port(phba);
5461
5462disable_msix:
5463 if (phba->msix_enabled)
5464 pci_disable_msix(phba->pcidev);
5465
5466 return ret;
5467}
5468
5469/*
5470 * beiscsi_disable_port()- Disable port and cleanup driver resources.
5471 * This is called in HBA error handling and driver removal.
5472 * @phba: Instance Priv structure
5473 * @unload: indicate driver is unloading
5474 *
5475 * Free the OS and HW resources held by the driver
5476 **/
5477static void beiscsi_disable_port(struct beiscsi_hba *phba, int unload)
5478{
5479 struct hwi_context_memory *phwi_context;
5480 struct hwi_controller *phwi_ctrlr;
5481 struct be_eq_obj *pbe_eq;
5482 unsigned int i, msix_vec;
5483
5484 if (!test_and_clear_bit(BEISCSI_HBA_ONLINE, &phba->state))
5485 return;
5486
5487 phwi_ctrlr = phba->phwi_ctrlr;
5488 phwi_context = phwi_ctrlr->phwi_ctxt;
5489 hwi_disable_intr(phba);
5490 if (phba->msix_enabled) {
5491 for (i = 0; i <= phba->num_cpus; i++) {
5492 msix_vec = phba->msix_entries[i].vector;
5493 free_irq(msix_vec, &phwi_context->be_eq[i]);
5494 kfree(phba->msi_name[i]);
5495 }
5496 } else
5497 if (phba->pcidev->irq)
5498 free_irq(phba->pcidev->irq, phba);
5499 pci_disable_msix(phba->pcidev);
5500
5501 for (i = 0; i < phba->num_cpus; i++) {
5502 pbe_eq = &phwi_context->be_eq[i];
5503 irq_poll_disable(&pbe_eq->iopoll);
5504 }
5505 cancel_delayed_work_sync(&phba->eqd_update);
5506 cancel_work_sync(&phba->boot_work);
5507 /* WQ might be running cancel queued mcc_work if we are not exiting */
5508 if (!unload && beiscsi_hba_in_error(phba)) {
5509 pbe_eq = &phwi_context->be_eq[i];
5510 cancel_work_sync(&pbe_eq->mcc_work);
5511 }
5512 hwi_cleanup_port(phba);
5513}
5514
10e1a44a
JB		 5515static void beiscsi_sess_work(struct work_struct *work)
5516{
5517 struct beiscsi_hba *phba;
5518
5519 phba = container_of(work, struct beiscsi_hba, sess_work);
5520 /*
5521 * This work gets scheduled only in case of HBA error.
5522 * Old sessions are gone so need to be re-established.
5523 * iscsi_session_failure needs process context hence this work.
5524 */
5525 iscsi_host_for_each_session(phba->shost, beiscsi_session_fail);
5526}
5527
d1d5ca88
JB		 5528static void beiscsi_recover_port(struct work_struct *work)
5529{
5530 struct beiscsi_hba *phba;
5531
5532 phba = container_of(work, struct beiscsi_hba, recover_port.work);
d1d5ca88
JB		 5533 beiscsi_disable_port(phba, 0);
5534 beiscsi_enable_port(phba);
5535}
3567f36a
JK		 5536
5537static pci_ers_result_t beiscsi_eeh_err_detected(struct pci_dev *pdev,
5538 pci_channel_state_t state)
5539{
5540 struct beiscsi_hba *phba = NULL;
5541
5542 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
9122e991 5543 set_bit(BEISCSI_HBA_PCI_ERR, &phba->state);
3567f36a
JK		 5544
5545 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5546 "BM_%d : EEH error detected\n");
5547
d1d5ca88
JB		 5548 /* first stop UE detection when PCI error detected */
5549 del_timer_sync(&phba->hw_check);
5550 cancel_delayed_work_sync(&phba->recover_port);
5551
10e1a44a
JB		 5552 /* sessions are no longer valid, so first fail the sessions */
5553 iscsi_host_for_each_session(phba->shost, beiscsi_session_fail);
d1d5ca88 5554 beiscsi_disable_port(phba, 0);
3567f36a
JK		 5555
5556 if (state == pci_channel_io_perm_failure) {
5557 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5558 "BM_%d : EEH : State PERM Failure");
5559 return PCI_ERS_RESULT_DISCONNECT;
5560 }
5561
5562 pci_disable_device(pdev);
5563
5564 /* The error could cause the FW to trigger a flash debug dump.
5565 * Resetting the card while flash dump is in progress
5566 * can cause it not to recover; wait for it to finish.
5567 * Wait only for first function as it is needed only once per
5568 * adapter.
5569 **/
5570 if (pdev->devfn == 0)
5571 ssleep(30);
5572
5573 return PCI_ERS_RESULT_NEED_RESET;
5574}
5575
5576static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev)
5577{
5578 struct beiscsi_hba *phba = NULL;
5579 int status = 0;
5580
5581 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5582
5583 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5584 "BM_%d : EEH Reset\n");
5585
5586 status = pci_enable_device(pdev);
5587 if (status)
5588 return PCI_ERS_RESULT_DISCONNECT;
5589
5590 pci_set_master(pdev);
5591 pci_set_power_state(pdev, PCI_D0);
5592 pci_restore_state(pdev);
5593
4d2ee1e6
JB		 5594 status = beiscsi_check_fw_rdy(phba);
5595 if (status) {
3567f36a
JK		 5596 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5597 "BM_%d : EEH Reset Completed\n");
5598 } else {
5599 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5600 "BM_%d : EEH Reset Completion Failure\n");
5601 return PCI_ERS_RESULT_DISCONNECT;
5602 }
5603
5604 pci_cleanup_aer_uncorrect_error_status(pdev);
5605 return PCI_ERS_RESULT_RECOVERED;
5606}
5607
5608static void beiscsi_eeh_resume(struct pci_dev *pdev)
5609{
d1d5ca88
JB		 5610 struct beiscsi_hba *phba;
5611 int ret;
3567f36a
JK		 5612
5613 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5614 pci_save_state(pdev);
5615
d1d5ca88 5616 ret = beiscsi_enable_port(phba);
4d2ee1e6 5617 if (ret)
d1d5ca88
JB		 5618 __beiscsi_log(phba, KERN_ERR,
5619 "BM_%d : AER EEH resume failed\n");
3567f36a
JK		 5620}
5621
6f039790
GKH		 5622static int beiscsi_dev_probe(struct pci_dev *pcidev,
5623 const struct pci_device_id *id)
6733b39a
JK		 5624{
5625 struct beiscsi_hba *phba = NULL;
bfead3b2
JK		 5626 struct hwi_controller *phwi_ctrlr;
5627 struct hwi_context_memory *phwi_context;
5628 struct be_eq_obj *pbe_eq;
50a4b824 5629 unsigned int s_handle;
3567f36a 5630 int ret = 0, i;
6733b39a
JK		 5631
5632 ret = beiscsi_enable_pci(pcidev);
5633 if (ret < 0) {
99bc5d55
JSJ		 5634 dev_err(&pcidev->dev,
5635 "beiscsi_dev_probe - Failed to enable pci device\n");
6733b39a
JK		 5636 return ret;
5637 }
5638
5639 phba = beiscsi_hba_alloc(pcidev);
5640 if (!phba) {
99bc5d55
JSJ		 5641 dev_err(&pcidev->dev,
5642 "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
6733b39a
JK		 5643 goto disable_pci;
5644 }
5645
3567f36a
JK		 5646 /* Enable EEH reporting */
5647 ret = pci_enable_pcie_error_reporting(pcidev);
5648 if (ret)
5649 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5650 "BM_%d : PCIe Error Reporting "
5651 "Enabling Failed\n");
5652
5653 pci_save_state(pcidev);
5654
99bc5d55
JSJ		 5655 /* Initialize Driver configuration Paramters */
5656 beiscsi_hba_attrs_init(phba);
5657
6c83185a 5658 phba->mac_addr_set = false;
e175defe 5659
f98c96b0
JK		 5660 switch (pcidev->device) {
5661 case BE_DEVICE_ID1:
5662 case OC_DEVICE_ID1:
5663 case OC_DEVICE_ID2:
5664 phba->generation = BE_GEN2;
09a1093a 5665 phba->iotask_fn = beiscsi_iotask;
f98c96b0
JK		 5666 break;
5667 case BE_DEVICE_ID2:
5668 case OC_DEVICE_ID3:
5669 phba->generation = BE_GEN3;
09a1093a 5670 phba->iotask_fn = beiscsi_iotask;
f98c96b0 5671 break;
139a1b1e
JSJ		 5672 case OC_SKH_ID1:
5673 phba->generation = BE_GEN4;
09a1093a 5674 phba->iotask_fn = beiscsi_iotask_v2;
bf9131cb 5675 break;
f98c96b0
JK		 5676 default:
5677 phba->generation = 0;
5678 }
5679
6733b39a
JK		 5680 ret = be_ctrl_init(phba, pcidev);
5681 if (ret) {
99bc5d55 5682 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4d2ee1e6 5683 "BM_%d : be_ctrl_init failed\n");
6733b39a
JK		 5684 goto hba_free;
5685 }
5686
4d2ee1e6
JB		 5687 ret = beiscsi_init_sliport(phba);
5688 if (ret)
4d4d1ef8 5689 goto hba_free;
e9b91193 5690
6733b39a
JK		 5691 spin_lock_init(&phba->io_sgl_lock);
5692 spin_lock_init(&phba->mgmt_sgl_lock);
8f09a3b9 5693 spin_lock_init(&phba->async_pdu_lock);
480195c2 5694 ret = beiscsi_get_fw_config(&phba->ctrl, phba);
7da50879 5695 if (ret != 0) {
99bc5d55
JSJ		 5696 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5697 "BM_%d : Error getting fw config\n");
7da50879
JK		 5698 goto free_port;
5699 }
480195c2 5700 beiscsi_get_port_name(&phba->ctrl, phba);
4570f161 5701 beiscsi_get_params(phba);
6694095b 5702 beiscsi_set_uer_feature(phba);
68c26a3a
JK		 5703
5704 if (enable_msix)
5705 find_num_cpus(phba);
5706 else
5707 phba->num_cpus = 1;
5708
5709 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
5710 "BM_%d : num_cpus = %d\n",
5711 phba->num_cpus);
5712
5713 if (enable_msix) {
5714 beiscsi_msix_enable(phba);
5715 if (!phba->msix_enabled)
5716 phba->num_cpus = 1;
5717 }
5718
843ae752 5719 phba->shost->max_id = phba->params.cxns_per_ctrl;
aa874f07 5720 phba->shost->can_queue = phba->params.ios_per_ctrl;
6733b39a
JK		 5721 ret = beiscsi_init_port(phba);
5722 if (ret < 0) {
99bc5d55
JSJ		 5723 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5724 "BM_%d : beiscsi_dev_probe-"
5725 "Failed in beiscsi_init_port\n");
6733b39a
JK		 5726 goto free_port;
5727 }
5728
3567f36a 5729 for (i = 0; i < MAX_MCC_CMD; i++) {
756d29c8
JK		 5730 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5731 phba->ctrl.mcc_tag[i] = i + 1;
67296ad9 5732 phba->ctrl.mcc_tag_status[i + 1] = 0;
756d29c8 5733 phba->ctrl.mcc_tag_available++;
1957aa7f 5734 memset(&phba->ctrl.ptag_state[i].tag_mem_state, 0,
8fc01eaa 5735 sizeof(struct be_dma_mem));
756d29c8
JK		 5736 }
5737
5738 phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
5739
72fb46a9 5740 snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
6733b39a 5741 phba->shost->host_no);
d8537548 5742 phba->wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 1, phba->wq_name);
6733b39a 5743 if (!phba->wq) {
99bc5d55
JSJ		 5744 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5745 "BM_%d : beiscsi_dev_probe-"
5746 "Failed to allocate work queue\n");
6733b39a
JK		 5747 goto free_twq;
5748 }
5749
10bcd47d 5750 INIT_DELAYED_WORK(&phba->eqd_update, beiscsi_eqd_update_work);
6733b39a 5751
bfead3b2
JK		 5752 phwi_ctrlr = phba->phwi_ctrlr;
5753 phwi_context = phwi_ctrlr->phwi_ctxt;
72fb46a9 5754
89f8b33c 5755 for (i = 0; i < phba->num_cpus; i++) {
72fb46a9 5756 pbe_eq = &phwi_context->be_eq[i];
d1d5ca88 5757 irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget, be_iopoll);
6733b39a 5758 }
72fb46a9 5759
89f8b33c
JA		 5760 i = (phba->msix_enabled) ? i : 0;
5761 /* Work item for MCC handling */
5762 pbe_eq = &phwi_context->be_eq[i];
a3095016 5763 INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work);
89f8b33c 5764
6733b39a
JK		 5765 ret = beiscsi_init_irqs(phba);
5766 if (ret < 0) {
99bc5d55
JSJ		 5767 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5768 "BM_%d : beiscsi_dev_probe-"
5769 "Failed to beiscsi_init_irqs\n");
6733b39a
JK		 5770 goto free_blkenbld;
5771 }
238f6b72 5772 hwi_enable_intr(phba);
f457a46f 5773
d1d5ca88
JB		 5774 ret = iscsi_host_add(phba->shost, &phba->pcidev->dev);
5775 if (ret)
0598b8af
JK		 5776 goto free_blkenbld;
5777
d1d5ca88
JB		 5778 /* set online bit after port is operational */
5779 set_bit(BEISCSI_HBA_ONLINE, &phba->state);
5780 __beiscsi_log(phba, KERN_INFO,
5781 "BM_%d : port online: 0x%lx\n", phba->state);
5782
50a4b824
JB		 5783 INIT_WORK(&phba->boot_work, beiscsi_boot_work);
5784 ret = beiscsi_boot_get_shandle(phba, &s_handle);
5785 if (ret > 0) {
5786 beiscsi_start_boot_work(phba, s_handle);
5787 /**
5788 * Set this bit after starting the work to let
5789 * probe handle it first.
5790 * ASYNC event can too schedule this work.
f457a46f 5791 */
50a4b824
JB		 5792 set_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state);
5793 }
f457a46f 5794
96b48b92 5795 beiscsi_iface_create_default(phba);
10bcd47d
JB		 5796 schedule_delayed_work(&phba->eqd_update,
5797 msecs_to_jiffies(BEISCSI_EQD_UPDATE_INTERVAL));
d1d5ca88 5798
10e1a44a 5799 INIT_WORK(&phba->sess_work, beiscsi_sess_work);
d1d5ca88 5800 INIT_DELAYED_WORK(&phba->recover_port, beiscsi_recover_port);
10bcd47d
JB		 5801 /**
5802 * Start UE detection here. UE before this will cause stall in probe
5803 * and eventually fail the probe.
5804 */
5805 init_timer(&phba->hw_check);
5806 phba->hw_check.function = beiscsi_hw_health_check;
5807 phba->hw_check.data = (unsigned long)phba;
5808 mod_timer(&phba->hw_check,
5809 jiffies + msecs_to_jiffies(BEISCSI_UE_DETECT_INTERVAL));
99bc5d55
JSJ		 5810 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
5811 "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
6733b39a
JK		 5812 return 0;
5813
6733b39a
JK		 5814free_blkenbld:
5815 destroy_workqueue(phba->wq);
89f8b33c
JA		 5816 for (i = 0; i < phba->num_cpus; i++) {
5817 pbe_eq = &phwi_context->be_eq[i];
511cbce2 5818 irq_poll_disable(&pbe_eq->iopoll);
89f8b33c 5819 }
6733b39a 5820free_twq:
d1d5ca88 5821 hwi_cleanup_port(phba);
4d2ee1e6 5822 beiscsi_cleanup_port(phba);
6733b39a
JK		 5823 beiscsi_free_mem(phba);
5824free_port:
5825 pci_free_consistent(phba->pcidev,
5826 phba->ctrl.mbox_mem_alloced.size,
5827 phba->ctrl.mbox_mem_alloced.va,
5828 phba->ctrl.mbox_mem_alloced.dma);
5829 beiscsi_unmap_pci_function(phba);
5830hba_free:
238f6b72
JK		 5831 if (phba->msix_enabled)
5832 pci_disable_msix(phba->pcidev);
6733b39a
JK		 5833 pci_dev_put(phba->pcidev);
5834 iscsi_host_free(phba->shost);
2e7cee02 5835 pci_set_drvdata(pcidev, NULL);
6733b39a 5836disable_pci:
e307f3ac 5837 pci_release_regions(pcidev);
6733b39a
JK		 5838 pci_disable_device(pcidev);
5839 return ret;
5840}
5841
d1d5ca88
JB		 5842static void beiscsi_remove(struct pci_dev *pcidev)
5843{
5844 struct beiscsi_hba *phba = NULL;
5845
5846 phba = pci_get_drvdata(pcidev);
5847 if (!phba) {
5848 dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
5849 return;
5850 }
5851
5852 /* first stop UE detection before unloading */
5853 del_timer_sync(&phba->hw_check);
5854 cancel_delayed_work_sync(&phba->recover_port);
10e1a44a 5855 cancel_work_sync(&phba->sess_work);
d1d5ca88
JB		 5856
5857 beiscsi_iface_destroy_default(phba);
5858 iscsi_host_remove(phba->shost);
5859 beiscsi_disable_port(phba, 1);
5860
5861 /* after cancelling boot_work */
5862 iscsi_boot_destroy_kset(phba->boot_struct.boot_kset);
5863
5864 /* free all resources */
5865 destroy_workqueue(phba->wq);
5866 beiscsi_cleanup_port(phba);
5867 beiscsi_free_mem(phba);
5868
5869 /* ctrl uninit */
5870 beiscsi_unmap_pci_function(phba);
5871 pci_free_consistent(phba->pcidev,
5872 phba->ctrl.mbox_mem_alloced.size,
5873 phba->ctrl.mbox_mem_alloced.va,
5874 phba->ctrl.mbox_mem_alloced.dma);
5875
5876 pci_dev_put(phba->pcidev);
5877 iscsi_host_free(phba->shost);
5878 pci_disable_pcie_error_reporting(pcidev);
5879 pci_set_drvdata(pcidev, NULL);
5880 pci_release_regions(pcidev);
5881 pci_disable_device(pcidev);
5882}
5883
5884
3567f36a
JK		 5885static struct pci_error_handlers beiscsi_eeh_handlers = {
5886 .error_detected = beiscsi_eeh_err_detected,
5887 .slot_reset = beiscsi_eeh_reset,
5888 .resume = beiscsi_eeh_resume,
5889};
5890
6733b39a
JK		 5891struct iscsi_transport beiscsi_iscsi_transport = {
5892 .owner = THIS_MODULE,
5893 .name = DRV_NAME,
9db0fb3a 5894 .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
6733b39a 5895 CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
6733b39a
JK		 5896 .create_session = beiscsi_session_create,
5897 .destroy_session = beiscsi_session_destroy,
5898 .create_conn = beiscsi_conn_create,
5899 .bind_conn = beiscsi_conn_bind,
5900 .destroy_conn = iscsi_conn_teardown,
96b48b92
JB		 5901 .attr_is_visible = beiscsi_attr_is_visible,
5902 .set_iface_param = beiscsi_iface_set_param,
5903 .get_iface_param = beiscsi_iface_get_param,
6733b39a 5904 .set_param = beiscsi_set_param,
c7f7fd5b 5905 .get_conn_param = iscsi_conn_get_param,
6733b39a
JK		 5906 .get_session_param = iscsi_session_get_param,
5907 .get_host_param = beiscsi_get_host_param,
5908 .start_conn = beiscsi_conn_start,
fa95d206 5909 .stop_conn = iscsi_conn_stop,
6733b39a
JK		 5910 .send_pdu = iscsi_conn_send_pdu,
5911 .xmit_task = beiscsi_task_xmit,
5912 .cleanup_task = beiscsi_cleanup_task,
5913 .alloc_pdu = beiscsi_alloc_pdu,
5914 .parse_pdu_itt = beiscsi_parse_pdu,
5915 .get_stats = beiscsi_conn_get_stats,
c7f7fd5b 5916 .get_ep_param = beiscsi_ep_get_param,
6733b39a
JK		 5917 .ep_connect = beiscsi_ep_connect,
5918 .ep_poll = beiscsi_ep_poll,
5919 .ep_disconnect = beiscsi_ep_disconnect,
5920 .session_recovery_timedout = iscsi_session_recovery_timedout,
ffce3e2e 5921 .bsg_request = beiscsi_bsg_request,
6733b39a
JK		 5922};
5923
5924static struct pci_driver beiscsi_pci_driver = {
5925 .name = DRV_NAME,
5926 .probe = beiscsi_dev_probe,
5927 .remove = beiscsi_remove,
3567f36a
JK		 5928 .id_table = beiscsi_pci_id_table,
5929 .err_handler = &beiscsi_eeh_handlers
6733b39a
JK		 5930};
5931
5932static int __init beiscsi_module_init(void)
5933{
5934 int ret;
5935
5936 beiscsi_scsi_transport =
5937 iscsi_register_transport(&beiscsi_iscsi_transport);
5938 if (!beiscsi_scsi_transport) {
99bc5d55
JSJ		 5939 printk(KERN_ERR
5940 "beiscsi_module_init - Unable to register beiscsi transport.\n");
f55a24f2 5941 return -ENOMEM;
6733b39a 5942 }
99bc5d55
JSJ		 5943 printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
5944 &beiscsi_iscsi_transport);
6733b39a
JK		 5945
5946 ret = pci_register_driver(&beiscsi_pci_driver);
5947 if (ret) {
99bc5d55
JSJ		 5948 printk(KERN_ERR
5949 "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
6733b39a
JK		 5950 goto unregister_iscsi_transport;
5951 }
5952 return 0;
5953
5954unregister_iscsi_transport:
5955 iscsi_unregister_transport(&beiscsi_iscsi_transport);
5956 return ret;
5957}
5958
5959static void __exit beiscsi_module_exit(void)
5960{
5961 pci_unregister_driver(&beiscsi_pci_driver);
5962 iscsi_unregister_transport(&beiscsi_iscsi_transport);
5963}
5964
5965module_init(beiscsi_module_init);
5966module_exit(beiscsi_module_exit);
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