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scsi: libsas: remove sas_scsi_timed_out
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / be2iscsi / be_main.c
CommitLineData
6733b39a 1/**
60f36e04 2 * Copyright (C) 2005 - 2016 Broadcom
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
60f36e04 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@broadcom.com)
6733b39a
JK		 11 *
12 * Contact Information:
60f36e04 13 * linux-drivers@broadcom.com
6733b39a 14 *
c4f39bda 15 * Emulex
255fa9a3
JK		 16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a 18 */
255fa9a3 19
6733b39a
JK		 20#include <linux/reboot.h>
21#include <linux/delay.h>
5a0e3ad6 22#include <linux/slab.h>
6733b39a
JK		 23#include <linux/interrupt.h>
24#include <linux/blkdev.h>
25#include <linux/pci.h>
26#include <linux/string.h>
27#include <linux/kernel.h>
28#include <linux/semaphore.h>
c7acc5b8 29#include <linux/iscsi_boot_sysfs.h>
acf3368f 30#include <linux/module.h>
ffce3e2e 31#include <linux/bsg-lib.h>
1094cf68 32#include <linux/irq_poll.h>
6733b39a
JK		 33
34#include <scsi/libiscsi.h>
ffce3e2e
JK		 35#include <scsi/scsi_bsg_iscsi.h>
36#include <scsi/scsi_netlink.h>
6733b39a
JK		 37#include <scsi/scsi_transport_iscsi.h>
38#include <scsi/scsi_transport.h>
39#include <scsi/scsi_cmnd.h>
40#include <scsi/scsi_device.h>
41#include <scsi/scsi_host.h>
42#include <scsi/scsi.h>
43#include "be_main.h"
44#include "be_iscsi.h"
45#include "be_mgmt.h"
0a513dd8 46#include "be_cmds.h"
6733b39a
JK		 47
48static unsigned int be_iopoll_budget = 10;
49static unsigned int be_max_phys_size = 64;
bfead3b2 50static unsigned int enable_msix = 1;
6733b39a 51
6733b39a 52MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
76d15dbd 53MODULE_VERSION(BUILD_STR);
c4f39bda 54MODULE_AUTHOR("Emulex Corporation");
6733b39a
JK		 55MODULE_LICENSE("GPL");
56module_param(be_iopoll_budget, int, 0);
57module_param(enable_msix, int, 0);
58module_param(be_max_phys_size, uint, S_IRUGO);
99bc5d55
JSJ		 59MODULE_PARM_DESC(be_max_phys_size,
60 "Maximum Size (In Kilobytes) of physically contiguous "
61 "memory that can be allocated. Range is 16 - 128");
62
63#define beiscsi_disp_param(_name)\
0825b8ee 64static ssize_t \
99bc5d55
JSJ		 65beiscsi_##_name##_disp(struct device *dev,\
66 struct device_attribute *attrib, char *buf) \
67{ \
68 struct Scsi_Host *shost = class_to_shost(dev);\
69 struct beiscsi_hba *phba = iscsi_host_priv(shost); \
99bc5d55
JSJ		 70 return snprintf(buf, PAGE_SIZE, "%d\n",\
71 phba->attr_##_name);\
72}
73
74#define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
0825b8ee 75static int \
99bc5d55
JSJ		 76beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
77{\
78 if (val >= _minval && val <= _maxval) {\
79 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
80 "BA_%d : beiscsi_"#_name" updated "\
81 "from 0x%x ==> 0x%x\n",\
82 phba->attr_##_name, val); \
83 phba->attr_##_name = val;\
84 return 0;\
85 } \
86 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
87 "BA_%d beiscsi_"#_name" attribute "\
88 "cannot be updated to 0x%x, "\
89 "range allowed is ["#_minval" - "#_maxval"]\n", val);\
90 return -EINVAL;\
91}
92
93#define beiscsi_store_param(_name) \
0825b8ee 94static ssize_t \
99bc5d55
JSJ		 95beiscsi_##_name##_store(struct device *dev,\
96 struct device_attribute *attr, const char *buf,\
97 size_t count) \
98{ \
99 struct Scsi_Host *shost = class_to_shost(dev);\
100 struct beiscsi_hba *phba = iscsi_host_priv(shost);\
101 uint32_t param_val = 0;\
102 if (!isdigit(buf[0]))\
103 return -EINVAL;\
104 if (sscanf(buf, "%i", &param_val) != 1)\
105 return -EINVAL;\
106 if (beiscsi_##_name##_change(phba, param_val) == 0) \
107 return strlen(buf);\
108 else \
109 return -EINVAL;\
110}
111
112#define beiscsi_init_param(_name, _minval, _maxval, _defval) \
0825b8ee 113static int \
99bc5d55
JSJ		 114beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
115{ \
116 if (val >= _minval && val <= _maxval) {\
117 phba->attr_##_name = val;\
118 return 0;\
119 } \
120 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
121 "BA_%d beiscsi_"#_name" attribute " \
122 "cannot be updated to 0x%x, "\
123 "range allowed is ["#_minval" - "#_maxval"]\n", val);\
124 phba->attr_##_name = _defval;\
125 return -EINVAL;\
126}
127
128#define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
129static uint beiscsi_##_name = _defval;\
130module_param(beiscsi_##_name, uint, S_IRUGO);\
131MODULE_PARM_DESC(beiscsi_##_name, _descp);\
132beiscsi_disp_param(_name)\
133beiscsi_change_param(_name, _minval, _maxval, _defval)\
134beiscsi_store_param(_name)\
135beiscsi_init_param(_name, _minval, _maxval, _defval)\
136DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
137 beiscsi_##_name##_disp, beiscsi_##_name##_store)
138
139/*
140 * When new log level added update the
141 * the MAX allowed value for log_enable
142 */
143BEISCSI_RW_ATTR(log_enable, 0x00,
144 0xFF, 0x00, "Enable logging Bit Mask\n"
145 "\t\t\t\tInitialization Events : 0x01\n"
146 "\t\t\t\tMailbox Events : 0x02\n"
147 "\t\t\t\tMiscellaneous Events : 0x04\n"
148 "\t\t\t\tError Handling : 0x08\n"
149 "\t\t\t\tIO Path Events : 0x10\n"
afb96058
JK		 150 "\t\t\t\tConfiguration Path : 0x20\n"
151 "\t\t\t\tiSCSI Protocol : 0x40\n");
99bc5d55 152
5cac7596 153DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
26000db7 154DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL);
22661e25 155DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL);
d3fea9af 156DEVICE_ATTR(beiscsi_phys_port, S_IRUGO, beiscsi_phys_port_disp, NULL);
6103c1f7
JK		 157DEVICE_ATTR(beiscsi_active_session_count, S_IRUGO,
158 beiscsi_active_session_disp, NULL);
159DEVICE_ATTR(beiscsi_free_session_count, S_IRUGO,
160 beiscsi_free_session_disp, NULL);
99bc5d55
JSJ		 161struct device_attribute *beiscsi_attrs[] = {
162 &dev_attr_beiscsi_log_enable,
5cac7596 163 &dev_attr_beiscsi_drvr_ver,
26000db7 164 &dev_attr_beiscsi_adapter_family,
22661e25 165 &dev_attr_beiscsi_fw_ver,
6103c1f7
JK		 166 &dev_attr_beiscsi_active_session_count,
167 &dev_attr_beiscsi_free_session_count,
d3fea9af 168 &dev_attr_beiscsi_phys_port,
99bc5d55
JSJ		 169 NULL,
170};
6733b39a 171
6763daae
JSJ		 172static char const *cqe_desc[] = {
173 "RESERVED_DESC",
174 "SOL_CMD_COMPLETE",
175 "SOL_CMD_KILLED_DATA_DIGEST_ERR",
176 "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
177 "CXN_KILLED_BURST_LEN_MISMATCH",
178 "CXN_KILLED_AHS_RCVD",
179 "CXN_KILLED_HDR_DIGEST_ERR",
180 "CXN_KILLED_UNKNOWN_HDR",
181 "CXN_KILLED_STALE_ITT_TTT_RCVD",
182 "CXN_KILLED_INVALID_ITT_TTT_RCVD",
183 "CXN_KILLED_RST_RCVD",
184 "CXN_KILLED_TIMED_OUT",
185 "CXN_KILLED_RST_SENT",
186 "CXN_KILLED_FIN_RCVD",
187 "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
188 "CXN_KILLED_BAD_WRB_INDEX_ERROR",
189 "CXN_KILLED_OVER_RUN_RESIDUAL",
190 "CXN_KILLED_UNDER_RUN_RESIDUAL",
191 "CMD_KILLED_INVALID_STATSN_RCVD",
192 "CMD_KILLED_INVALID_R2T_RCVD",
193 "CMD_CXN_KILLED_LUN_INVALID",
194 "CMD_CXN_KILLED_ICD_INVALID",
195 "CMD_CXN_KILLED_ITT_INVALID",
196 "CMD_CXN_KILLED_SEQ_OUTOFORDER",
197 "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
198 "CXN_INVALIDATE_NOTIFY",
199 "CXN_INVALIDATE_INDEX_NOTIFY",
200 "CMD_INVALIDATED_NOTIFY",
201 "UNSOL_HDR_NOTIFY",
202 "UNSOL_DATA_NOTIFY",
203 "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
204 "DRIVERMSG_NOTIFY",
205 "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
206 "SOL_CMD_KILLED_DIF_ERR",
207 "CXN_KILLED_SYN_RCVD",
208 "CXN_KILLED_IMM_DATA_RCVD"
209};
210
6733b39a
JK		 211static int beiscsi_slave_configure(struct scsi_device *sdev)
212{
213 blk_queue_max_segment_size(sdev->request_queue, 65536);
214 return 0;
215}
216
4183122d
JK		 217static int beiscsi_eh_abort(struct scsi_cmnd *sc)
218{
faa0a22d 219 struct iscsi_task *abrt_task = (struct iscsi_task *)sc->SCp.ptr;
4183122d 220 struct iscsi_cls_session *cls_session;
faa0a22d 221 struct beiscsi_io_task *abrt_io_task;
4183122d 222 struct beiscsi_conn *beiscsi_conn;
4183122d 223 struct iscsi_session *session;
f3505013 224 struct invldt_cmd_tbl inv_tbl;
faa0a22d
JB		 225 struct beiscsi_hba *phba;
226 struct iscsi_conn *conn;
1957aa7f 227 int rc;
4183122d
JK		 228
229 cls_session = starget_to_session(scsi_target(sc->device));
230 session = cls_session->dd_data;
231
faa0a22d
JB		 232 /* check if we raced, task just got cleaned up under us */
233 spin_lock_bh(&session->back_lock);
234 if (!abrt_task || !abrt_task->sc) {
235 spin_unlock_bh(&session->back_lock);
4183122d
JK		 236 return SUCCESS;
237 }
faa0a22d
JB		 238 /* get a task ref till FW processes the req for the ICD used */
239 __iscsi_get_task(abrt_task);
240 abrt_io_task = abrt_task->dd_data;
241 conn = abrt_task->conn;
4183122d
JK		 242 beiscsi_conn = conn->dd_data;
243 phba = beiscsi_conn->phba;
faa0a22d 244 /* mark WRB invalid which have been not processed by FW yet */
392b7d2f
JB		 245 if (is_chip_be2_be3r(phba)) {
246 AMAP_SET_BITS(struct amap_iscsi_wrb, invld,
247 abrt_io_task->pwrb_handle->pwrb, 1);
248 } else {
249 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, invld,
250 abrt_io_task->pwrb_handle->pwrb, 1);
251 }
faa0a22d
JB		 252 inv_tbl.cid = beiscsi_conn->beiscsi_conn_cid;
253 inv_tbl.icd = abrt_io_task->psgl_handle->sgl_index;
254 spin_unlock_bh(&session->back_lock);
255
98713216 256 rc = beiscsi_mgmt_invalidate_icds(phba, &inv_tbl, 1);
faa0a22d 257 iscsi_put_task(abrt_task);
98713216 258 if (rc) {
99bc5d55 259 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
98713216
JB		 260 "BM_%d : sc %p invalidation failed %d\n",
261 sc, rc);
4183122d 262 return FAILED;
4183122d 263 }
e175defe 264
4183122d
JK		 265 return iscsi_eh_abort(sc);
266}
267
268static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
269{
98713216
JB		 270 struct beiscsi_invldt_cmd_tbl {
271 struct invldt_cmd_tbl tbl[BE_INVLDT_CMD_TBL_SZ];
272 struct iscsi_task *task[BE_INVLDT_CMD_TBL_SZ];
273 } *inv_tbl;
274 struct iscsi_cls_session *cls_session;
4183122d 275 struct beiscsi_conn *beiscsi_conn;
98713216 276 struct beiscsi_io_task *io_task;
4183122d 277 struct iscsi_session *session;
98713216
JB		 278 struct beiscsi_hba *phba;
279 struct iscsi_conn *conn;
280 struct iscsi_task *task;
281 unsigned int i, nents;
f3505013 282 int rc, more = 0;
4183122d 283
4183122d
JK		 284 cls_session = starget_to_session(scsi_target(sc->device));
285 session = cls_session->dd_data;
98713216 286
659743b0 287 spin_lock_bh(&session->frwd_lock);
db7f7709 288 if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
659743b0 289 spin_unlock_bh(&session->frwd_lock);
db7f7709
JK		 290 return FAILED;
291 }
98713216 292
4183122d
JK		 293 conn = session->leadconn;
294 beiscsi_conn = conn->dd_data;
295 phba = beiscsi_conn->phba;
f3505013 296
f2534736 297 inv_tbl = kzalloc(sizeof(*inv_tbl), GFP_ATOMIC);
f3505013
JB		 298 if (!inv_tbl) {
299 spin_unlock_bh(&session->frwd_lock);
300 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
301 "BM_%d : invldt_cmd_tbl alloc failed\n");
302 return FAILED;
303 }
304 nents = 0;
98713216
JB		 305 /* take back_lock to prevent task from getting cleaned up under us */
306 spin_lock(&session->back_lock);
4183122d 307 for (i = 0; i < conn->session->cmds_max; i++) {
98713216
JB		 308 task = conn->session->cmds[i];
309 if (!task->sc)
4183122d
JK		 310 continue;
311
98713216 312 if (sc->device->lun != task->sc->device->lun)
4183122d 313 continue;
f3505013
JB		 314 /**
315 * Can't fit in more cmds? Normally this won't happen b'coz
316 * BEISCSI_CMD_PER_LUN is same as BE_INVLDT_CMD_TBL_SZ.
317 */
318 if (nents == BE_INVLDT_CMD_TBL_SZ) {
319 more = 1;
320 break;
321 }
4183122d 322
98713216
JB		 323 /* get a task ref till FW processes the req for the ICD used */
324 __iscsi_get_task(task);
325 io_task = task->dd_data;
326 /* mark WRB invalid which have been not processed by FW yet */
392b7d2f
JB		 327 if (is_chip_be2_be3r(phba)) {
328 AMAP_SET_BITS(struct amap_iscsi_wrb, invld,
329 io_task->pwrb_handle->pwrb, 1);
330 } else {
331 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, invld,
332 io_task->pwrb_handle->pwrb, 1);
333 }
7626c06b 334
98713216
JB		 335 inv_tbl->tbl[nents].cid = beiscsi_conn->beiscsi_conn_cid;
336 inv_tbl->tbl[nents].icd = io_task->psgl_handle->sgl_index;
337 inv_tbl->task[nents] = task;
f3505013 338 nents++;
4183122d 339 }
98713216 340 spin_unlock_bh(&session->back_lock);
659743b0 341 spin_unlock_bh(&session->frwd_lock);
4183122d 342
98713216
JB		 343 rc = SUCCESS;
344 if (!nents)
345 goto end_reset;
346
f3505013
JB		 347 if (more) {
348 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
349 "BM_%d : number of cmds exceeds size of invalidation table\n");
98713216
JB		 350 rc = FAILED;
351 goto end_reset;
f3505013
JB		 352 }
353
98713216 354 if (beiscsi_mgmt_invalidate_icds(phba, &inv_tbl->tbl[0], nents)) {
99bc5d55 355 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
98713216
JB		 356 "BM_%d : cid %u scmds invalidation failed\n",
357 beiscsi_conn->beiscsi_conn_cid);
358 rc = FAILED;
4183122d 359 }
e175defe 360
98713216
JB		 361end_reset:
362 for (i = 0; i < nents; i++)
363 iscsi_put_task(inv_tbl->task[i]);
364 kfree(inv_tbl);
365
366 if (rc == SUCCESS)
367 rc = iscsi_eh_device_reset(sc);
368 return rc;
4183122d
JK		 369}
370
bfead3b2 371/*------------------- PCI Driver operations and data ----------------- */
9baa3c34 372static const struct pci_device_id beiscsi_pci_id_table[] = {
bfead3b2 373 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
f98c96b0 374 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
bfead3b2
JK		 375 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
376 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
377 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
139a1b1e 378 { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
bfead3b2
JK		 379 { 0 }
380};
381MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
382
99bc5d55 383
6733b39a
JK		 384static struct scsi_host_template beiscsi_sht = {
385 .module = THIS_MODULE,
c4f39bda 386 .name = "Emulex 10Gbe open-iscsi Initiator Driver",
6733b39a
JK		 387 .proc_name = DRV_NAME,
388 .queuecommand = iscsi_queuecommand,
db5ed4df 389 .change_queue_depth = scsi_change_queue_depth,
6733b39a
JK		 390 .slave_configure = beiscsi_slave_configure,
391 .target_alloc = iscsi_target_alloc,
4183122d
JK		 392 .eh_abort_handler = beiscsi_eh_abort,
393 .eh_device_reset_handler = beiscsi_eh_device_reset,
309ce156 394 .eh_target_reset_handler = iscsi_eh_session_reset,
99bc5d55 395 .shost_attrs = beiscsi_attrs,
6733b39a
JK		 396 .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
397 .can_queue = BE2_IO_DEPTH,
398 .this_id = -1,
399 .max_sectors = BEISCSI_MAX_SECTORS,
400 .cmd_per_lun = BEISCSI_CMD_PER_LUN,
401 .use_clustering = ENABLE_CLUSTERING,
ffce3e2e 402 .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
c40ecc12 403 .track_queue_depth = 1,
6733b39a 404};
6733b39a 405
bfead3b2 406static struct scsi_transport_template *beiscsi_scsi_transport;
6733b39a
JK		 407
408static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
409{
410 struct beiscsi_hba *phba;
411 struct Scsi_Host *shost;
412
413 shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
414 if (!shost) {
99bc5d55
JSJ		 415 dev_err(&pcidev->dev,
416 "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
6733b39a
JK		 417 return NULL;
418 }
6733b39a
JK		 419 shost->max_id = BE2_MAX_SESSIONS;
420 shost->max_channel = 0;
421 shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
422 shost->max_lun = BEISCSI_NUM_MAX_LUN;
423 shost->transportt = beiscsi_scsi_transport;
6733b39a
JK		 424 phba = iscsi_host_priv(shost);
425 memset(phba, 0, sizeof(*phba));
426 phba->shost = shost;
427 phba->pcidev = pci_dev_get(pcidev);
2807afb7 428 pci_set_drvdata(pcidev, phba);
0e43895e 429 phba->interface_handle = 0xFFFFFFFF;
6733b39a 430
6733b39a 431 return phba;
6733b39a
JK		 432}
433
434static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
435{
436 if (phba->csr_va) {
437 iounmap(phba->csr_va);
438 phba->csr_va = NULL;
439 }
440 if (phba->db_va) {
441 iounmap(phba->db_va);
442 phba->db_va = NULL;
443 }
444 if (phba->pci_va) {
445 iounmap(phba->pci_va);
446 phba->pci_va = NULL;
447 }
448}
449
450static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
451 struct pci_dev *pcidev)
452{
453 u8 __iomem *addr;
f98c96b0 454 int pcicfg_reg;
6733b39a
JK		 455
456 addr = ioremap_nocache(pci_resource_start(pcidev, 2),
457 pci_resource_len(pcidev, 2));
458 if (addr == NULL)
459 return -ENOMEM;
460 phba->ctrl.csr = addr;
461 phba->csr_va = addr;
462 phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
463
464 addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
465 if (addr == NULL)
466 goto pci_map_err;
467 phba->ctrl.db = addr;
468 phba->db_va = addr;
469 phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
470
f98c96b0
JK		 471 if (phba->generation == BE_GEN2)
472 pcicfg_reg = 1;
473 else
474 pcicfg_reg = 0;
475
476 addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
477 pci_resource_len(pcidev, pcicfg_reg));
478
6733b39a
JK		 479 if (addr == NULL)
480 goto pci_map_err;
481 phba->ctrl.pcicfg = addr;
482 phba->pci_va = addr;
f98c96b0 483 phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
6733b39a
JK		 484 return 0;
485
486pci_map_err:
487 beiscsi_unmap_pci_function(phba);
488 return -ENOMEM;
489}
490
491static int beiscsi_enable_pci(struct pci_dev *pcidev)
492{
493 int ret;
494
495 ret = pci_enable_device(pcidev);
496 if (ret) {
99bc5d55
JSJ		 497 dev_err(&pcidev->dev,
498 "beiscsi_enable_pci - enable device failed\n");
6733b39a
JK		 499 return ret;
500 }
501
e307f3ac
JSJ		 502 ret = pci_request_regions(pcidev, DRV_NAME);
503 if (ret) {
504 dev_err(&pcidev->dev,
505 "beiscsi_enable_pci - request region failed\n");
506 goto pci_dev_disable;
507 }
508
bfead3b2 509 pci_set_master(pcidev);
6c57625b
JK		 510 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64));
511 if (ret) {
512 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
513 if (ret) {
514 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
e307f3ac 515 goto pci_region_release;
6c57625b
JK		 516 } else {
517 ret = pci_set_consistent_dma_mask(pcidev,
518 DMA_BIT_MASK(32));
519 }
520 } else {
521 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
6733b39a
JK		 522 if (ret) {
523 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
e307f3ac 524 goto pci_region_release;
6733b39a
JK		 525 }
526 }
527 return 0;
e307f3ac
JSJ		 528
529pci_region_release:
530 pci_release_regions(pcidev);
531pci_dev_disable:
532 pci_disable_device(pcidev);
533
534 return ret;
6733b39a
JK		 535}
536
537static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
538{
539 struct be_ctrl_info *ctrl = &phba->ctrl;
540 struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
541 struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
542 int status = 0;
543
544 ctrl->pdev = pdev;
545 status = beiscsi_map_pci_bars(phba, pdev);
546 if (status)
547 return status;
6733b39a
JK		 548 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
549 mbox_mem_alloc->va = pci_alloc_consistent(pdev,
550 mbox_mem_alloc->size,
551 &mbox_mem_alloc->dma);
552 if (!mbox_mem_alloc->va) {
553 beiscsi_unmap_pci_function(phba);
a49e06d5 554 return -ENOMEM;
6733b39a
JK		 555 }
556
557 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
558 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
559 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
560 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
c03a50f7 561 mutex_init(&ctrl->mbox_lock);
bfead3b2 562 spin_lock_init(&phba->ctrl.mcc_lock);
bfead3b2 563
6733b39a
JK		 564 return status;
565}
566
843ae752
JK		 567/**
568 * beiscsi_get_params()- Set the config paramters
569 * @phba: ptr device priv structure
570 **/
6733b39a
JK		 571static void beiscsi_get_params(struct beiscsi_hba *phba)
572{
843ae752
JK		 573 uint32_t total_cid_count = 0;
574 uint32_t total_icd_count = 0;
575 uint8_t ulp_num = 0;
576
577 total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) +
578 BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1);
579
cf987b79
JK		 580 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
581 uint32_t align_mask = 0;
582 uint32_t icd_post_per_page = 0;
583 uint32_t icd_count_unavailable = 0;
584 uint32_t icd_start = 0, icd_count = 0;
585 uint32_t icd_start_align = 0, icd_count_align = 0;
586
843ae752 587 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
cf987b79
JK		 588 icd_start = phba->fw_config.iscsi_icd_start[ulp_num];
589 icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
590
591 /* Get ICD count that can be posted on each page */
592 icd_post_per_page = (PAGE_SIZE / (BE2_SGE *
593 sizeof(struct iscsi_sge)));
594 align_mask = (icd_post_per_page - 1);
595
596 /* Check if icd_start is aligned ICD per page posting */
597 if (icd_start % icd_post_per_page) {
598 icd_start_align = ((icd_start +
599 icd_post_per_page) &
600 ~(align_mask));
601 phba->fw_config.
602 iscsi_icd_start[ulp_num] =
603 icd_start_align;
604 }
605
606 icd_count_align = (icd_count & ~align_mask);
607
608 /* ICD discarded in the process of alignment */
609 if (icd_start_align)
610 icd_count_unavailable = ((icd_start_align -
611 icd_start) +
612 (icd_count -
613 icd_count_align));
614
615 /* Updated ICD count available */
616 phba->fw_config.iscsi_icd_count[ulp_num] = (icd_count -
617 icd_count_unavailable);
618
619 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
620 "BM_%d : Aligned ICD values\n"
621 "\t ICD Start : %d\n"
622 "\t ICD Count : %d\n"
623 "\t ICD Discarded : %d\n",
624 phba->fw_config.
625 iscsi_icd_start[ulp_num],
626 phba->fw_config.
627 iscsi_icd_count[ulp_num],
628 icd_count_unavailable);
843ae752
JK		 629 break;
630 }
cf987b79 631 }
843ae752 632
cf987b79 633 total_icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
843ae752
JK		 634 phba->params.ios_per_ctrl = (total_icd_count -
635 (total_cid_count +
636 BE2_TMFS + BE2_NOPOUT_REQ));
637 phba->params.cxns_per_ctrl = total_cid_count;
638 phba->params.asyncpdus_per_ctrl = total_cid_count;
639 phba->params.icds_per_ctrl = total_icd_count;
6733b39a
JK		 640 phba->params.num_sge_per_io = BE2_SGE;
641 phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
642 phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
843ae752
JK		 643 phba->params.num_eq_entries = 1024;
644 phba->params.num_cq_entries = 1024;
6733b39a
JK		 645 phba->params.wrbs_per_cxn = 256;
646}
647
648static void hwi_ring_eq_db(struct beiscsi_hba *phba,
649 unsigned int id, unsigned int clr_interrupt,
650 unsigned int num_processed,
651 unsigned char rearm, unsigned char event)
652{
653 u32 val = 0;
e08b3c8b 654
6733b39a
JK		 655 if (rearm)
656 val |= 1 << DB_EQ_REARM_SHIFT;
657 if (clr_interrupt)
658 val |= 1 << DB_EQ_CLR_SHIFT;
659 if (event)
660 val |= 1 << DB_EQ_EVNT_SHIFT;
e08b3c8b 661
6733b39a 662 val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
e08b3c8b
JK		 663 /* Setting lower order EQ_ID Bits */
664 val |= (id & DB_EQ_RING_ID_LOW_MASK);
665
666 /* Setting Higher order EQ_ID Bits */
667 val |= (((id >> DB_EQ_HIGH_FEILD_SHIFT) &
668 DB_EQ_RING_ID_HIGH_MASK)
669 << DB_EQ_HIGH_SET_SHIFT);
670
6733b39a
JK		 671 iowrite32(val, phba->db_va + DB_EQ_OFFSET);
672}
673
bfead3b2
JK		 674/**
675 * be_isr_mcc - The isr routine of the driver.
676 * @irq: Not used
677 * @dev_id: Pointer to host adapter structure
678 */
679static irqreturn_t be_isr_mcc(int irq, void *dev_id)
680{
681 struct beiscsi_hba *phba;
a3095016 682 struct be_eq_entry *eqe;
bfead3b2
JK		 683 struct be_queue_info *eq;
684 struct be_queue_info *mcc;
a3095016 685 unsigned int mcc_events;
bfead3b2 686 struct be_eq_obj *pbe_eq;
bfead3b2
JK		 687
688 pbe_eq = dev_id;
689 eq = &pbe_eq->q;
690 phba = pbe_eq->phba;
691 mcc = &phba->ctrl.mcc_obj.cq;
692 eqe = queue_tail_node(eq);
bfead3b2 693
a3095016 694 mcc_events = 0;
bfead3b2
JK		 695 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
696 & EQE_VALID_MASK) {
697 if (((eqe->dw[offsetof(struct amap_eq_entry,
698 resource_id) / 32] &
699 EQE_RESID_MASK) >> 16) == mcc->id) {
a3095016 700 mcc_events++;
bfead3b2
JK		 701 }
702 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
703 queue_tail_inc(eq);
704 eqe = queue_tail_node(eq);
bfead3b2 705 }
bfead3b2 706
a3095016
JB		 707 if (mcc_events) {
708 queue_work(phba->wq, &pbe_eq->mcc_work);
709 hwi_ring_eq_db(phba, eq->id, 1, mcc_events, 1, 1);
710 }
bfead3b2
JK		 711 return IRQ_HANDLED;
712}
713
714/**
715 * be_isr_msix - The isr routine of the driver.
716 * @irq: Not used
717 * @dev_id: Pointer to host adapter structure
718 */
719static irqreturn_t be_isr_msix(int irq, void *dev_id)
720{
721 struct beiscsi_hba *phba;
bfead3b2 722 struct be_queue_info *eq;
bfead3b2 723 struct be_eq_obj *pbe_eq;
bfead3b2
JK		 724
725 pbe_eq = dev_id;
726 eq = &pbe_eq->q;
bfead3b2
JK		 727
728 phba = pbe_eq->phba;
1094cf68
JB		 729 /* disable interrupt till iopoll completes */
730 hwi_ring_eq_db(phba, eq->id, 1, 0, 0, 1);
731 irq_poll_sched(&pbe_eq->iopoll);
72fb46a9
JSJ		 732
733 return IRQ_HANDLED;
bfead3b2
JK		 734}
735
6733b39a
JK		 736/**
737 * be_isr - The isr routine of the driver.
738 * @irq: Not used
739 * @dev_id: Pointer to host adapter structure
740 */
741static irqreturn_t be_isr(int irq, void *dev_id)
742{
743 struct beiscsi_hba *phba;
744 struct hwi_controller *phwi_ctrlr;
745 struct hwi_context_memory *phwi_context;
a3095016 746 struct be_eq_entry *eqe;
6733b39a 747 struct be_queue_info *eq;
bfead3b2 748 struct be_queue_info *mcc;
a3095016 749 unsigned int mcc_events, io_events;
6733b39a 750 struct be_ctrl_info *ctrl;
bfead3b2 751 struct be_eq_obj *pbe_eq;
a3095016 752 int isr, rearm;
6733b39a
JK		 753
754 phba = dev_id;
6eab04a8 755 ctrl = &phba->ctrl;
bfead3b2
JK		 756 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
757 (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
758 if (!isr)
759 return IRQ_NONE;
6733b39a
JK		 760
761 phwi_ctrlr = phba->phwi_ctrlr;
762 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 763 pbe_eq = &phwi_context->be_eq[0];
764
765 eq = &phwi_context->be_eq[0].q;
766 mcc = &phba->ctrl.mcc_obj.cq;
6733b39a 767 eqe = queue_tail_node(eq);
6733b39a 768
a3095016
JB		 769 io_events = 0;
770 mcc_events = 0;
89f8b33c
JA		 771 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
772 & EQE_VALID_MASK) {
773 if (((eqe->dw[offsetof(struct amap_eq_entry,
a3095016
JB		 774 resource_id) / 32] & EQE_RESID_MASK) >> 16) == mcc->id)
775 mcc_events++;
776 else
777 io_events++;
89f8b33c
JA		 778 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
779 queue_tail_inc(eq);
780 eqe = queue_tail_node(eq);
781 }
a3095016 782 if (!io_events && !mcc_events)
89f8b33c 783 return IRQ_NONE;
a3095016
JB		 784
785 /* no need to rearm if interrupt is only for IOs */
786 rearm = 0;
787 if (mcc_events) {
788 queue_work(phba->wq, &pbe_eq->mcc_work);
789 /* rearm for MCCQ */
790 rearm = 1;
791 }
792 if (io_events)
793 irq_poll_sched(&pbe_eq->iopoll);
794 hwi_ring_eq_db(phba, eq->id, 0, (io_events + mcc_events), rearm, 1);
795 return IRQ_HANDLED;
6733b39a
JK		 796}
797
1094cf68 798
6733b39a
JK		 799static int beiscsi_init_irqs(struct beiscsi_hba *phba)
800{
801 struct pci_dev *pcidev = phba->pcidev;
bfead3b2
JK		 802 struct hwi_controller *phwi_ctrlr;
803 struct hwi_context_memory *phwi_context;
4f5af07e 804 int ret, msix_vec, i, j;
6733b39a 805
bfead3b2
JK		 806 phwi_ctrlr = phba->phwi_ctrlr;
807 phwi_context = phwi_ctrlr->phwi_ctxt;
808
809 if (phba->msix_enabled) {
810 for (i = 0; i < phba->num_cpus; i++) {
8fcfb210
JK		 811 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
812 GFP_KERNEL);
813 if (!phba->msi_name[i]) {
814 ret = -ENOMEM;
815 goto free_msix_irqs;
816 }
817
818 sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
819 phba->shost->host_no, i);
bfead3b2 820 msix_vec = phba->msix_entries[i].vector;
8fcfb210
JK		 821 ret = request_irq(msix_vec, be_isr_msix, 0,
822 phba->msi_name[i],
bfead3b2 823 &phwi_context->be_eq[i]);
4f5af07e 824 if (ret) {
99bc5d55
JSJ		 825 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
826 "BM_%d : beiscsi_init_irqs-Failed to"
827 "register msix for i = %d\n",
828 i);
8fcfb210 829 kfree(phba->msi_name[i]);
4f5af07e
JK		 830 goto free_msix_irqs;
831 }
bfead3b2 832 }
8fcfb210
JK		 833 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
834 if (!phba->msi_name[i]) {
835 ret = -ENOMEM;
836 goto free_msix_irqs;
837 }
838 sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
839 phba->shost->host_no);
bfead3b2 840 msix_vec = phba->msix_entries[i].vector;
8fcfb210 841 ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
bfead3b2 842 &phwi_context->be_eq[i]);
4f5af07e 843 if (ret) {
99bc5d55
JSJ		 844 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
845 "BM_%d : beiscsi_init_irqs-"
846 "Failed to register beiscsi_msix_mcc\n");
8fcfb210 847 kfree(phba->msi_name[i]);
4f5af07e
JK		 848 goto free_msix_irqs;
849 }
850
bfead3b2
JK		 851 } else {
852 ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
853 "beiscsi", phba);
854 if (ret) {
99bc5d55
JSJ		 855 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
856 "BM_%d : beiscsi_init_irqs-"
857 "Failed to register irq\\n");
bfead3b2
JK		 858 return ret;
859 }
6733b39a
JK		 860 }
861 return 0;
4f5af07e 862free_msix_irqs:
8fcfb210
JK		 863 for (j = i - 1; j >= 0; j--) {
864 kfree(phba->msi_name[j]);
865 msix_vec = phba->msix_entries[j].vector;
4f5af07e 866 free_irq(msix_vec, &phwi_context->be_eq[j]);
8fcfb210 867 }
4f5af07e 868 return ret;
6733b39a
JK		 869}
870
e08b3c8b 871void hwi_ring_cq_db(struct beiscsi_hba *phba,
6733b39a 872 unsigned int id, unsigned int num_processed,
1094cf68 873 unsigned char rearm)
6733b39a
JK		 874{
875 u32 val = 0;
e08b3c8b 876
6733b39a
JK		 877 if (rearm)
878 val |= 1 << DB_CQ_REARM_SHIFT;
e08b3c8b 879
6733b39a 880 val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
e08b3c8b
JK		 881
882 /* Setting lower order CQ_ID Bits */
883 val |= (id & DB_CQ_RING_ID_LOW_MASK);
884
885 /* Setting Higher order CQ_ID Bits */
886 val |= (((id >> DB_CQ_HIGH_FEILD_SHIFT) &
887 DB_CQ_RING_ID_HIGH_MASK)
888 << DB_CQ_HIGH_SET_SHIFT);
889
6733b39a
JK		 890 iowrite32(val, phba->db_va + DB_CQ_OFFSET);
891}
892
6733b39a
JK		 893static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
894{
895 struct sgl_handle *psgl_handle;
7d2c0d64 896 unsigned long flags;
6733b39a 897
7d2c0d64 898 spin_lock_irqsave(&phba->io_sgl_lock, flags);
6733b39a 899 if (phba->io_sgl_hndl_avbl) {
99bc5d55
JSJ		 900 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
901 "BM_%d : In alloc_io_sgl_handle,"
902 " io_sgl_alloc_index=%d\n",
903 phba->io_sgl_alloc_index);
904
6733b39a
JK		 905 psgl_handle = phba->io_sgl_hndl_base[phba->
906 io_sgl_alloc_index];
907 phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
908 phba->io_sgl_hndl_avbl--;
bfead3b2
JK		 909 if (phba->io_sgl_alloc_index == (phba->params.
910 ios_per_ctrl - 1))
6733b39a
JK		 911 phba->io_sgl_alloc_index = 0;
912 else
913 phba->io_sgl_alloc_index++;
914 } else
915 psgl_handle = NULL;
7d2c0d64 916 spin_unlock_irqrestore(&phba->io_sgl_lock, flags);
6733b39a
JK		 917 return psgl_handle;
918}
919
920static void
921free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
922{
7d2c0d64
JB		 923 unsigned long flags;
924
925 spin_lock_irqsave(&phba->io_sgl_lock, flags);
99bc5d55
JSJ		 926 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
927 "BM_%d : In free_,io_sgl_free_index=%d\n",
928 phba->io_sgl_free_index);
929
6733b39a
JK		 930 if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
931 /*
932 * this can happen if clean_task is called on a task that
933 * failed in xmit_task or alloc_pdu.
934 */
99bc5d55
JSJ		 935 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
936 "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
937 "value there=%p\n", phba->io_sgl_free_index,
938 phba->io_sgl_hndl_base
939 [phba->io_sgl_free_index]);
7d2c0d64 940 spin_unlock_irqrestore(&phba->io_sgl_lock, flags);
6733b39a
JK		 941 return;
942 }
943 phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
944 phba->io_sgl_hndl_avbl++;
945 if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
946 phba->io_sgl_free_index = 0;
947 else
948 phba->io_sgl_free_index++;
7d2c0d64 949 spin_unlock_irqrestore(&phba->io_sgl_lock, flags);
6733b39a
JK		 950}
951
cb564c6b
JB		 952static inline struct wrb_handle *
953beiscsi_get_wrb_handle(struct hwi_wrb_context *pwrb_context,
954 unsigned int wrbs_per_cxn)
955{
956 struct wrb_handle *pwrb_handle;
7d2c0d64 957 unsigned long flags;
cb564c6b 958
7d2c0d64 959 spin_lock_irqsave(&pwrb_context->wrb_lock, flags);
3f7f62ee
JB		 960 if (!pwrb_context->wrb_handles_available) {
961 spin_unlock_irqrestore(&pwrb_context->wrb_lock, flags);
962 return NULL;
963 }
cb564c6b
JB		 964 pwrb_handle = pwrb_context->pwrb_handle_base[pwrb_context->alloc_index];
965 pwrb_context->wrb_handles_available--;
966 if (pwrb_context->alloc_index == (wrbs_per_cxn - 1))
967 pwrb_context->alloc_index = 0;
968 else
969 pwrb_context->alloc_index++;
7d2c0d64 970 spin_unlock_irqrestore(&pwrb_context->wrb_lock, flags);
bf9b7554
JB		 971
972 if (pwrb_handle)
973 memset(pwrb_handle->pwrb, 0, sizeof(*pwrb_handle->pwrb));
cb564c6b
JB		 974
975 return pwrb_handle;
976}
977
6733b39a
JK		 978/**
979 * alloc_wrb_handle - To allocate a wrb handle
980 * @phba: The hba pointer
981 * @cid: The cid to use for allocation
340c99e9 982 * @pwrb_context: ptr to ptr to wrb context
6733b39a
JK		 983 *
984 * This happens under session_lock until submission to chip
985 */
340c99e9 986struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
cb564c6b 987 struct hwi_wrb_context **pcontext)
6733b39a
JK		 988{
989 struct hwi_wrb_context *pwrb_context;
990 struct hwi_controller *phwi_ctrlr;
a7909b39 991 uint16_t cri_index = BE_GET_CRI_FROM_CID(cid);
6733b39a
JK		 992
993 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 994 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
cb564c6b
JB		 995 /* return the context address */
996 *pcontext = pwrb_context;
997 return beiscsi_get_wrb_handle(pwrb_context, phba->params.wrbs_per_cxn);
998}
340c99e9 999
cb564c6b
JB		 1000static inline void
1001beiscsi_put_wrb_handle(struct hwi_wrb_context *pwrb_context,
1002 struct wrb_handle *pwrb_handle,
1003 unsigned int wrbs_per_cxn)
1004{
7d2c0d64
JB		 1005 unsigned long flags;
1006
1007 spin_lock_irqsave(&pwrb_context->wrb_lock, flags);
cb564c6b
JB		 1008 pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
1009 pwrb_context->wrb_handles_available++;
1010 if (pwrb_context->free_index == (wrbs_per_cxn - 1))
1011 pwrb_context->free_index = 0;
1012 else
1013 pwrb_context->free_index++;
3f7f62ee 1014 pwrb_handle->pio_handle = NULL;
7d2c0d64 1015 spin_unlock_irqrestore(&pwrb_context->wrb_lock, flags);
6733b39a
JK		 1016}
1017
1018/**
1019 * free_wrb_handle - To free the wrb handle back to pool
1020 * @phba: The hba pointer
1021 * @pwrb_context: The context to free from
1022 * @pwrb_handle: The wrb_handle to free
1023 *
1024 * This happens under session_lock until submission to chip
1025 */
1026static void
1027free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
1028 struct wrb_handle *pwrb_handle)
1029{
cb564c6b
JB		 1030 beiscsi_put_wrb_handle(pwrb_context,
1031 pwrb_handle,
1032 phba->params.wrbs_per_cxn);
99bc5d55
JSJ		 1033 beiscsi_log(phba, KERN_INFO,
1034 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1035 "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
1036 "wrb_handles_available=%d\n",
1037 pwrb_handle, pwrb_context->free_index,
1038 pwrb_context->wrb_handles_available);
6733b39a
JK		 1039}
1040
1041static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
1042{
1043 struct sgl_handle *psgl_handle;
7d2c0d64 1044 unsigned long flags;
6733b39a 1045
7d2c0d64 1046 spin_lock_irqsave(&phba->mgmt_sgl_lock, flags);
6733b39a
JK		 1047 if (phba->eh_sgl_hndl_avbl) {
1048 psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
1049 phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
99bc5d55
JSJ		 1050 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
1051 "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
1052 phba->eh_sgl_alloc_index,
1053 phba->eh_sgl_alloc_index);
1054
6733b39a
JK		 1055 phba->eh_sgl_hndl_avbl--;
1056 if (phba->eh_sgl_alloc_index ==
1057 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
1058 1))
1059 phba->eh_sgl_alloc_index = 0;
1060 else
1061 phba->eh_sgl_alloc_index++;
1062 } else
1063 psgl_handle = NULL;
7d2c0d64 1064 spin_unlock_irqrestore(&phba->mgmt_sgl_lock, flags);
6733b39a
JK		 1065 return psgl_handle;
1066}
1067
1068void
1069free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
1070{
7d2c0d64
JB		 1071 unsigned long flags;
1072
1073 spin_lock_irqsave(&phba->mgmt_sgl_lock, flags);
99bc5d55
JSJ		 1074 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
1075 "BM_%d : In free_mgmt_sgl_handle,"
1076 "eh_sgl_free_index=%d\n",
1077 phba->eh_sgl_free_index);
1078
6733b39a
JK		 1079 if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
1080 /*
1081 * this can happen if clean_task is called on a task that
1082 * failed in xmit_task or alloc_pdu.
1083 */
99bc5d55
JSJ		 1084 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
1085 "BM_%d : Double Free in eh SGL ,"
1086 "eh_sgl_free_index=%d\n",
1087 phba->eh_sgl_free_index);
7d2c0d64 1088 spin_unlock_irqrestore(&phba->mgmt_sgl_lock, flags);
6733b39a
JK		 1089 return;
1090 }
1091 phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
1092 phba->eh_sgl_hndl_avbl++;
1093 if (phba->eh_sgl_free_index ==
1094 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
1095 phba->eh_sgl_free_index = 0;
1096 else
1097 phba->eh_sgl_free_index++;
7d2c0d64 1098 spin_unlock_irqrestore(&phba->mgmt_sgl_lock, flags);
6733b39a
JK		 1099}
1100
1101static void
1102be_complete_io(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1103 struct iscsi_task *task,
1104 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1105{
1106 struct beiscsi_io_task *io_task = task->dd_data;
1107 struct be_status_bhs *sts_bhs =
1108 (struct be_status_bhs *)io_task->cmd_bhs;
1109 struct iscsi_conn *conn = beiscsi_conn->conn;
6733b39a
JK		 1110 unsigned char *sense;
1111 u32 resid = 0, exp_cmdsn, max_cmdsn;
1112 u8 rsp, status, flags;
1113
73133261
JSJ		 1114 exp_cmdsn = csol_cqe->exp_cmdsn;
1115 max_cmdsn = (csol_cqe->exp_cmdsn +
1116 csol_cqe->cmd_wnd - 1);
1117 rsp = csol_cqe->i_resp;
1118 status = csol_cqe->i_sts;
1119 flags = csol_cqe->i_flags;
1120 resid = csol_cqe->res_cnt;
1121
bd535451 1122 if (!task->sc) {
da334977 1123 if (io_task->scsi_cmnd) {
bd535451 1124 scsi_dma_unmap(io_task->scsi_cmnd);
da334977
JK		 1125 io_task->scsi_cmnd = NULL;
1126 }
6733b39a 1127
bd535451
JK		 1128 return;
1129 }
6733b39a
JK		 1130 task->sc->result = (DID_OK << 16) | status;
1131 if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
1132 task->sc->result = DID_ERROR << 16;
1133 goto unmap;
1134 }
1135
1136 /* bidi not initially supported */
1137 if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
6733b39a
JK		 1138 if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
1139 task->sc->result = DID_ERROR << 16;
1140
1141 if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
1142 scsi_set_resid(task->sc, resid);
1143 if (!status && (scsi_bufflen(task->sc) - resid <
1144 task->sc->underflow))
1145 task->sc->result = DID_ERROR << 16;
1146 }
1147 }
1148
1149 if (status == SAM_STAT_CHECK_CONDITION) {
4053a4be 1150 u16 sense_len;
bfead3b2 1151 unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
4053a4be 1152
6733b39a 1153 sense = sts_bhs->sense_info + sizeof(unsigned short);
4053a4be 1154 sense_len = be16_to_cpu(*slen);
6733b39a
JK		 1155 memcpy(task->sc->sense_buffer, sense,
1156 min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
1157 }
756d29c8 1158
73133261
JSJ		 1159 if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ)
1160 conn->rxdata_octets += resid;
6733b39a 1161unmap:
eb1c4692
JSJ		 1162 if (io_task->scsi_cmnd) {
1163 scsi_dma_unmap(io_task->scsi_cmnd);
1164 io_task->scsi_cmnd = NULL;
1165 }
6733b39a
JK		 1166 iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
1167}
1168
1169static void
1170be_complete_logout(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1171 struct iscsi_task *task,
1172 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1173{
1174 struct iscsi_logout_rsp *hdr;
bfead3b2 1175 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1176 struct iscsi_conn *conn = beiscsi_conn->conn;
1177
1178 hdr = (struct iscsi_logout_rsp *)task->hdr;
7bd6e25c 1179 hdr->opcode = ISCSI_OP_LOGOUT_RSP;
6733b39a
JK		 1180 hdr->t2wait = 5;
1181 hdr->t2retain = 0;
73133261
JSJ		 1182 hdr->flags = csol_cqe->i_flags;
1183 hdr->response = csol_cqe->i_resp;
702dc5e8
JK		 1184 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
1185 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1186 csol_cqe->cmd_wnd - 1);
73133261 1187
7bd6e25c
JK		 1188 hdr->dlength[0] = 0;
1189 hdr->dlength[1] = 0;
1190 hdr->dlength[2] = 0;
6733b39a 1191 hdr->hlength = 0;
bfead3b2 1192 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1193 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1194}
1195
1196static void
1197be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1198 struct iscsi_task *task,
1199 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1200{
1201 struct iscsi_tm_rsp *hdr;
1202 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1203 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1204
1205 hdr = (struct iscsi_tm_rsp *)task->hdr;
7bd6e25c 1206 hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
73133261
JSJ		 1207 hdr->flags = csol_cqe->i_flags;
1208 hdr->response = csol_cqe->i_resp;
702dc5e8
JK		 1209 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
1210 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1211 csol_cqe->cmd_wnd - 1);
73133261 1212
bfead3b2 1213 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1214 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1215}
1216
1217static void
1218hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
1219 struct beiscsi_hba *phba, struct sol_cqe *psol)
1220{
1221 struct hwi_wrb_context *pwrb_context;
e1f9d31e 1222 uint16_t wrb_index, cid, cri_index;
6733b39a 1223 struct hwi_controller *phwi_ctrlr;
e1f9d31e 1224 struct wrb_handle *pwrb_handle;
3f7f62ee 1225 struct iscsi_session *session;
bfead3b2 1226 struct iscsi_task *task;
6733b39a
JK		 1227
1228 phwi_ctrlr = phba->phwi_ctrlr;
2c9dfd36
JK		 1229 if (is_chip_be2_be3r(phba)) {
1230 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
73133261 1231 wrb_idx, psol);
2c9dfd36 1232 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
73133261
JSJ		 1233 cid, psol);
1234 } else {
2c9dfd36 1235 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
73133261 1236 wrb_idx, psol);
2c9dfd36 1237 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
73133261
JSJ		 1238 cid, psol);
1239 }
1240
a7909b39
JK		 1241 cri_index = BE_GET_CRI_FROM_CID(cid);
1242 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
73133261 1243 pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index];
3f7f62ee
JB		 1244 session = beiscsi_conn->conn->session;
1245 spin_lock_bh(&session->back_lock);
32951dd8 1246 task = pwrb_handle->pio_handle;
3f7f62ee
JB		 1247 if (task)
1248 __iscsi_put_task(task);
1249 spin_unlock_bh(&session->back_lock);
6733b39a
JK		 1250}
1251
1252static void
1253be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1254 struct iscsi_task *task,
1255 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1256{
1257 struct iscsi_nopin *hdr;
1258 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1259 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1260
1261 hdr = (struct iscsi_nopin *)task->hdr;
73133261
JSJ		 1262 hdr->flags = csol_cqe->i_flags;
1263 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
702dc5e8
JK		 1264 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1265 csol_cqe->cmd_wnd - 1);
73133261 1266
6733b39a 1267 hdr->opcode = ISCSI_OP_NOOP_IN;
bfead3b2 1268 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1269 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1270}
1271
73133261
JSJ		 1272static void adapter_get_sol_cqe(struct beiscsi_hba *phba,
1273 struct sol_cqe *psol,
1274 struct common_sol_cqe *csol_cqe)
1275{
2c9dfd36
JK		 1276 if (is_chip_be2_be3r(phba)) {
1277 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe,
1278 i_exp_cmd_sn, psol);
1279 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe,
1280 i_res_cnt, psol);
1281 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
1282 i_cmd_wnd, psol);
1283 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe,
1284 wrb_index, psol);
1285 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe,
1286 cid, psol);
1287 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe,
1288 hw_sts, psol);
1289 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe,
1290 i_resp, psol);
1291 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe,
1292 i_sts, psol);
1293 csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe,
1294 i_flags, psol);
1295 } else {
73133261
JSJ		 1296 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1297 i_exp_cmd_sn, psol);
1298 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1299 i_res_cnt, psol);
1300 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1301 wrb_index, psol);
1302 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1303 cid, psol);
1304 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1305 hw_sts, psol);
702dc5e8 1306 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2,
73133261
JSJ		 1307 i_cmd_wnd, psol);
1308 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1309 cmd_cmpl, psol))
1310 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1311 i_sts, psol);
1312 else
1313 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1314 i_sts, psol);
1315 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1316 u, psol))
1317 csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW;
1318
1319 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1320 o, psol))
1321 csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW;
73133261
JSJ		 1322 }
1323}
1324
1325
6733b39a
JK		 1326static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
1327 struct beiscsi_hba *phba, struct sol_cqe *psol)
1328{
3f7f62ee
JB		 1329 struct iscsi_conn *conn = beiscsi_conn->conn;
1330 struct iscsi_session *session = conn->session;
1331 struct common_sol_cqe csol_cqe = {0};
6733b39a 1332 struct hwi_wrb_context *pwrb_context;
3f7f62ee 1333 struct hwi_controller *phwi_ctrlr;
6733b39a 1334 struct wrb_handle *pwrb_handle;
6733b39a 1335 struct iscsi_task *task;
a7909b39 1336 uint16_t cri_index = 0;
3f7f62ee 1337 uint8_t type;
6733b39a
JK		 1338
1339 phwi_ctrlr = phba->phwi_ctrlr;
73133261
JSJ		 1340
1341 /* Copy the elements to a common structure */
1342 adapter_get_sol_cqe(phba, psol, &csol_cqe);
1343
a7909b39
JK		 1344 cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid);
1345 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
73133261
JSJ		 1346
1347 pwrb_handle = pwrb_context->pwrb_handle_basestd[
1348 csol_cqe.wrb_index];
1349
3f7f62ee 1350 spin_lock_bh(&session->back_lock);
32951dd8 1351 task = pwrb_handle->pio_handle;
3f7f62ee
JB		 1352 if (!task) {
1353 spin_unlock_bh(&session->back_lock);
1354 return;
1355 }
73133261 1356 type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type;
32951dd8 1357
bfead3b2 1358 switch (type) {
6733b39a
JK		 1359 case HWH_TYPE_IO:
1360 case HWH_TYPE_IO_RD:
1361 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
dafab8e0 1362 ISCSI_OP_NOOP_OUT)
73133261 1363 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
dafab8e0 1364 else
73133261 1365 be_complete_io(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1366 break;
1367
1368 case HWH_TYPE_LOGOUT:
dafab8e0 1369 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
73133261 1370 be_complete_logout(beiscsi_conn, task, &csol_cqe);
dafab8e0 1371 else
73133261 1372 be_complete_tmf(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1373 break;
1374
1375 case HWH_TYPE_LOGIN:
99bc5d55
JSJ		 1376 beiscsi_log(phba, KERN_ERR,
1377 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1378 "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
1379 " hwi_complete_cmd- Solicited path\n");
6733b39a
JK		 1380 break;
1381
6733b39a 1382 case HWH_TYPE_NOP:
73133261 1383 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1384 break;
1385
1386 default:
99bc5d55
JSJ		 1387 beiscsi_log(phba, KERN_WARNING,
1388 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1389 "BM_%d : In hwi_complete_cmd, unknown type = %d"
1390 "wrb_index 0x%x CID 0x%x\n", type,
73133261
JSJ		 1391 csol_cqe.wrb_index,
1392 csol_cqe.cid);
6733b39a
JK		 1393 break;
1394 }
35e66019 1395
659743b0 1396 spin_unlock_bh(&session->back_lock);
6733b39a
JK		 1397}
1398
938f372c
JB		 1399/**
1400 * ASYNC PDUs include
1401 * a. Unsolicited NOP-In (target initiated NOP-In)
1402 * b. ASYNC Messages
1403 * c. Reject PDU
1404 * d. Login response
1405 * These headers arrive unprocessed by the EP firmware.
1406 * iSCSI layer processes them.
1407 */
1408static unsigned int
1409beiscsi_complete_pdu(struct beiscsi_conn *beiscsi_conn,
1410 struct pdu_base *phdr, void *pdata, unsigned int dlen)
6733b39a 1411{
938f372c
JB		 1412 struct beiscsi_hba *phba = beiscsi_conn->phba;
1413 struct iscsi_conn *conn = beiscsi_conn->conn;
1414 struct beiscsi_io_task *io_task;
1415 struct iscsi_hdr *login_hdr;
1416 struct iscsi_task *task;
1417 u8 code;
1418
1419 code = AMAP_GET_BITS(struct amap_pdu_base, opcode, phdr);
1420 switch (code) {
1421 case ISCSI_OP_NOOP_IN:
1422 pdata = NULL;
1423 dlen = 0;
1424 break;
1425 case ISCSI_OP_ASYNC_EVENT:
1426 break;
1427 case ISCSI_OP_REJECT:
1428 WARN_ON(!pdata);
1429 WARN_ON(!(dlen == 48));
1430 beiscsi_log(phba, KERN_ERR,
1431 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1432 "BM_%d : In ISCSI_OP_REJECT\n");
1433 break;
1434 case ISCSI_OP_LOGIN_RSP:
1435 case ISCSI_OP_TEXT_RSP:
1436 task = conn->login_task;
1437 io_task = task->dd_data;
1438 login_hdr = (struct iscsi_hdr *)phdr;
1439 login_hdr->itt = io_task->libiscsi_itt;
1440 break;
1441 default:
1442 beiscsi_log(phba, KERN_WARNING,
1443 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1444 "BM_%d : unrecognized async PDU opcode 0x%x\n",
1445 code);
1446 return 1;
1447 }
1448 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)phdr, pdata, dlen);
1449 return 0;
1450}
1451
1452static inline void
1453beiscsi_hdl_put_handle(struct hd_async_context *pasync_ctx,
1454 struct hd_async_handle *pasync_handle)
1455{
1456 if (pasync_handle->is_header) {
1457 list_add_tail(&pasync_handle->link,
1458 &pasync_ctx->async_header.free_list);
1459 pasync_ctx->async_header.free_entries++;
1460 } else {
1461 list_add_tail(&pasync_handle->link,
1462 &pasync_ctx->async_data.free_list);
1463 pasync_ctx->async_data.free_entries++;
1464 }
6733b39a
JK		 1465}
1466
938f372c
JB		 1467static struct hd_async_handle *
1468beiscsi_hdl_get_handle(struct beiscsi_conn *beiscsi_conn,
1469 struct hd_async_context *pasync_ctx,
1470 struct i_t_dpdu_cqe *pdpdu_cqe)
6733b39a 1471{
938f372c
JB		 1472 struct beiscsi_hba *phba = beiscsi_conn->phba;
1473 struct hd_async_handle *pasync_handle;
6733b39a 1474 struct be_bus_address phys_addr;
938f372c
JB		 1475 u8 final, error = 0;
1476 u16 cid, code, ci;
1477 u32 dpl;
73133261 1478
938f372c
JB		 1479 cid = beiscsi_conn->beiscsi_conn_cid;
1480 /**
1481 * This function is invoked to get the right async_handle structure
1482 * from a given DEF PDU CQ entry.
1483 *
1484 * - index in CQ entry gives the vertical index
1485 * - address in CQ entry is the offset where the DMA last ended
1486 * - final - no more notifications for this PDU
1487 */
2c9dfd36
JK		 1488 if (is_chip_be2_be3r(phba)) {
1489 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
73133261 1490 dpl, pdpdu_cqe);
938f372c 1491 ci = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
73133261 1492 index, pdpdu_cqe);
938f372c
JB		 1493 final = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
1494 final, pdpdu_cqe);
73133261 1495 } else {
2c9dfd36 1496 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
73133261 1497 dpl, pdpdu_cqe);
938f372c 1498 ci = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
73133261 1499 index, pdpdu_cqe);
938f372c
JB		 1500 final = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
1501 final, pdpdu_cqe);
73133261 1502 }
6733b39a 1503
938f372c
JB		 1504 /**
1505 * DB addr Hi/Lo is same for BE and SKH.
1506 * Subtract the dataplacementlength to get to the base.
1507 */
1508 phys_addr.u.a32.address_lo = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
1509 db_addr_lo, pdpdu_cqe);
1510 phys_addr.u.a32.address_lo -= dpl;
1511 phys_addr.u.a32.address_hi = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
1512 db_addr_hi, pdpdu_cqe);
1513
1514 code = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, code, pdpdu_cqe);
1515 switch (code) {
6733b39a 1516 case UNSOL_HDR_NOTIFY:
938f372c 1517 pasync_handle = pasync_ctx->async_entry[ci].header;
6733b39a 1518 break;
938f372c
JB		 1519 case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
1520 error = 1;
6733b39a 1521 case UNSOL_DATA_NOTIFY:
938f372c 1522 pasync_handle = pasync_ctx->async_entry[ci].data;
6733b39a 1523 break;
938f372c 1524 /* called only for above codes */
6733b39a 1525 default:
938f372c
JB		 1526 pasync_handle = NULL;
1527 break;
6733b39a
JK		 1528 }
1529
938f372c
JB		 1530 if (!pasync_handle) {
1531 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI,
1532 "BM_%d : cid %d async PDU handle not found - code %d ci %d addr %llx\n",
1533 cid, code, ci, phys_addr.u.a64.address);
1534 return pasync_handle;
6733b39a
JK		 1535 }
1536
938f372c
JB		 1537 if (pasync_handle->pa.u.a64.address != phys_addr.u.a64.address ||
1538 pasync_handle->index != ci) {
1539 /* driver bug - if ci does not match async handle index */
1540 error = 1;
1541 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI,
1542 "BM_%d : cid %u async PDU handle mismatch - addr in %cQE %llx at %u:addr in CQE %llx ci %u\n",
1543 cid, pasync_handle->is_header ? 'H' : 'D',
1544 pasync_handle->pa.u.a64.address,
1545 pasync_handle->index,
1546 phys_addr.u.a64.address, ci);
1547 /* FW has stale address - attempt continuing by dropping */
1548 }
6733b39a 1549
938f372c
JB		 1550 /**
1551 * Each CID is associated with unique CRI.
1552 * ASYNC_CRI_FROM_CID mapping and CRI_FROM_CID are totaly different.
1553 **/
1554 pasync_handle->cri = BE_GET_ASYNC_CRI_FROM_CID(cid);
1555 pasync_handle->is_final = final;
73133261 1556 pasync_handle->buffer_len = dpl;
938f372c
JB		 1557 /* empty the slot */
1558 if (pasync_handle->is_header)
1559 pasync_ctx->async_entry[ci].header = NULL;
1560 else
1561 pasync_ctx->async_entry[ci].data = NULL;
6733b39a 1562
938f372c
JB		 1563 /**
1564 * DEF PDU header and data buffers with errors should be simply
1565 * dropped as there are no consumers for it.
1566 */
1567 if (error) {
1568 beiscsi_hdl_put_handle(pasync_ctx, pasync_handle);
1569 pasync_handle = NULL;
1570 }
6733b39a
JK		 1571 return pasync_handle;
1572}
1573
938f372c
JB		 1574static void
1575beiscsi_hdl_purge_handles(struct beiscsi_hba *phba,
1576 struct hd_async_context *pasync_ctx,
1577 u16 cri)
6733b39a 1578{
938f372c
JB		 1579 struct hd_async_handle *pasync_handle, *tmp_handle;
1580 struct list_head *plist;
6733b39a 1581
938f372c
JB		 1582 plist = &pasync_ctx->async_entry[cri].wq.list;
1583 list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
1584 list_del(&pasync_handle->link);
1585 beiscsi_hdl_put_handle(pasync_ctx, pasync_handle);
6733b39a
JK		 1586 }
1587
938f372c
JB		 1588 INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wq.list);
1589 pasync_ctx->async_entry[cri].wq.hdr_len = 0;
1590 pasync_ctx->async_entry[cri].wq.bytes_received = 0;
1591 pasync_ctx->async_entry[cri].wq.bytes_needed = 0;
6733b39a
JK		 1592}
1593
938f372c
JB		 1594static unsigned int
1595beiscsi_hdl_fwd_pdu(struct beiscsi_conn *beiscsi_conn,
1596 struct hd_async_context *pasync_ctx,
1597 u16 cri)
6733b39a 1598{
938f372c
JB		 1599 struct iscsi_session *session = beiscsi_conn->conn->session;
1600 struct hd_async_handle *pasync_handle, *plast_handle;
1601 struct beiscsi_hba *phba = beiscsi_conn->phba;
1602 void *phdr = NULL, *pdata = NULL;
1603 u32 dlen = 0, status = 0;
6733b39a 1604 struct list_head *plist;
6733b39a 1605
938f372c
JB		 1606 plist = &pasync_ctx->async_entry[cri].wq.list;
1607 plast_handle = NULL;
1608 list_for_each_entry(pasync_handle, plist, link) {
1609 plast_handle = pasync_handle;
1610 /* get the header, the first entry */
1611 if (!phdr) {
1612 phdr = pasync_handle->pbuffer;
1613 continue;
6733b39a 1614 }
938f372c
JB		 1615 /* use first buffer to collect all the data */
1616 if (!pdata) {
1617 pdata = pasync_handle->pbuffer;
1618 dlen = pasync_handle->buffer_len;
1619 continue;
1620 }
1621 memcpy(pdata + dlen, pasync_handle->pbuffer,
1622 pasync_handle->buffer_len);
1623 dlen += pasync_handle->buffer_len;
6733b39a
JK		 1624 }
1625
938f372c
JB		 1626 if (!plast_handle->is_final) {
1627 /* last handle should have final PDU notification from FW */
1628 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI,
1629 "BM_%d : cid %u %p fwd async PDU with last handle missing - HL%u:DN%u:DR%u\n",
1630 beiscsi_conn->beiscsi_conn_cid, plast_handle,
1631 pasync_ctx->async_entry[cri].wq.hdr_len,
1632 pasync_ctx->async_entry[cri].wq.bytes_needed,
1633 pasync_ctx->async_entry[cri].wq.bytes_received);
1634 }
1635 spin_lock_bh(&session->back_lock);
1636 status = beiscsi_complete_pdu(beiscsi_conn, phdr, pdata, dlen);
1637 spin_unlock_bh(&session->back_lock);
1638 beiscsi_hdl_purge_handles(phba, pasync_ctx, cri);
1639 return status;
6733b39a
JK		 1640}
1641
938f372c
JB		 1642static unsigned int
1643beiscsi_hdl_gather_pdu(struct beiscsi_conn *beiscsi_conn,
1644 struct hd_async_context *pasync_ctx,
1645 struct hd_async_handle *pasync_handle)
6733b39a 1646{
938f372c
JB		 1647 unsigned int bytes_needed = 0, status = 0;
1648 u16 cri = pasync_handle->cri;
1649 struct cri_wait_queue *wq;
1650 struct beiscsi_hba *phba;
1651 struct pdu_base *ppdu;
1652 char *err = "";
6733b39a 1653
938f372c
JB		 1654 phba = beiscsi_conn->phba;
1655 wq = &pasync_ctx->async_entry[cri].wq;
1656 if (pasync_handle->is_header) {
1657 /* check if PDU hdr is rcv'd when old hdr not completed */
1658 if (wq->hdr_len) {
1659 err = "incomplete";
1660 goto drop_pdu;
1661 }
1662 ppdu = pasync_handle->pbuffer;
1663 bytes_needed = AMAP_GET_BITS(struct amap_pdu_base,
1664 data_len_hi, ppdu);
1665 bytes_needed <<= 16;
1666 bytes_needed |= be16_to_cpu(AMAP_GET_BITS(struct amap_pdu_base,
1667 data_len_lo, ppdu));
1668 wq->hdr_len = pasync_handle->buffer_len;
1669 wq->bytes_received = 0;
1670 wq->bytes_needed = bytes_needed;
1671 list_add_tail(&pasync_handle->link, &wq->list);
1672 if (!bytes_needed)
1673 status = beiscsi_hdl_fwd_pdu(beiscsi_conn,
1674 pasync_ctx, cri);
1675 } else {
1676 /* check if data received has header and is needed */
1677 if (!wq->hdr_len || !wq->bytes_needed) {
1678 err = "header less";
1679 goto drop_pdu;
1680 }
1681 wq->bytes_received += pasync_handle->buffer_len;
1682 /* Something got overwritten? Better catch it here. */
1683 if (wq->bytes_received > wq->bytes_needed) {
1684 err = "overflow";
1685 goto drop_pdu;
1686 }
1687 list_add_tail(&pasync_handle->link, &wq->list);
1688 if (wq->bytes_received == wq->bytes_needed)
1689 status = beiscsi_hdl_fwd_pdu(beiscsi_conn,
1690 pasync_ctx, cri);
1691 }
1692 return status;
6733b39a 1693
938f372c
JB		 1694drop_pdu:
1695 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI,
1696 "BM_%d : cid %u async PDU %s - def-%c:HL%u:DN%u:DR%u\n",
1697 beiscsi_conn->beiscsi_conn_cid, err,
1698 pasync_handle->is_header ? 'H' : 'D',
1699 wq->hdr_len, wq->bytes_needed,
1700 pasync_handle->buffer_len);
1701 /* discard this handle */
1702 beiscsi_hdl_put_handle(pasync_ctx, pasync_handle);
1703 /* free all the other handles in cri_wait_queue */
1704 beiscsi_hdl_purge_handles(phba, pasync_ctx, cri);
1705 /* try continuing */
1706 return status;
6733b39a
JK		 1707}
1708
938f372c
JB		 1709static void
1710beiscsi_hdq_post_handles(struct beiscsi_hba *phba,
1711 u8 header, u8 ulp_num)
6733b39a 1712{
938f372c
JB		 1713 struct hd_async_handle *pasync_handle, *tmp, **slot;
1714 struct hd_async_context *pasync_ctx;
6733b39a 1715 struct hwi_controller *phwi_ctrlr;
938f372c 1716 struct list_head *hfree_list;
6733b39a 1717 struct phys_addr *pasync_sge;
938f372c 1718 u32 ring_id, doorbell = 0;
938f372c
JB		 1719 u32 doorbell_offset;
1720 u16 prod = 0, cons;
fa1261c4 1721 u16 index;
6733b39a
JK		 1722
1723 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833 1724 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num);
938f372c
JB		 1725 if (header) {
1726 cons = pasync_ctx->async_header.free_entries;
1727 hfree_list = &pasync_ctx->async_header.free_list;
8a86e833
JK		 1728 ring_id = phwi_ctrlr->default_pdu_hdr[ulp_num].id;
1729 doorbell_offset = phwi_ctrlr->default_pdu_hdr[ulp_num].
938f372c 1730 doorbell_offset;
6733b39a 1731 } else {
938f372c
JB		 1732 cons = pasync_ctx->async_data.free_entries;
1733 hfree_list = &pasync_ctx->async_data.free_list;
8a86e833
JK		 1734 ring_id = phwi_ctrlr->default_pdu_data[ulp_num].id;
1735 doorbell_offset = phwi_ctrlr->default_pdu_data[ulp_num].
938f372c 1736 doorbell_offset;
6733b39a 1737 }
938f372c
JB		 1738 /* number of entries posted must be in multiples of 8 */
1739 if (cons % 8)
1740 return;
6733b39a 1741
938f372c
JB		 1742 list_for_each_entry_safe(pasync_handle, tmp, hfree_list, link) {
1743 list_del_init(&pasync_handle->link);
1744 pasync_handle->is_final = 0;
1745 pasync_handle->buffer_len = 0;
6733b39a 1746
938f372c
JB		 1747 /* handles can be consumed out of order, use index in handle */
1748 index = pasync_handle->index;
1749 WARN_ON(pasync_handle->is_header != header);
1750 if (header)
1751 slot = &pasync_ctx->async_entry[index].header;
1752 else
1753 slot = &pasync_ctx->async_entry[index].data;
1754 /**
1755 * The slot just tracks handle's hold and release, so
1756 * overwriting at the same index won't do any harm but
1757 * needs to be caught.
1758 */
1759 if (*slot != NULL) {
1760 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI,
1761 "BM_%d : async PDU %s slot at %u not empty\n",
1762 header ? "header" : "data", index);
6733b39a 1763 }
938f372c
JB		 1764 /**
1765 * We use same freed index as in completion to post so this
1766 * operation is not required for refills. Its required only
1767 * for ring creation.
1768 */
1769 if (header)
1770 pasync_sge = pasync_ctx->async_header.ring_base;
1771 else
1772 pasync_sge = pasync_ctx->async_data.ring_base;
1773 pasync_sge += index;
1774 /* if its a refill then address is same; hi is lo */
1775 WARN_ON(pasync_sge->hi &&
1776 pasync_sge->hi != pasync_handle->pa.u.a32.address_lo);
1777 WARN_ON(pasync_sge->lo &&
1778 pasync_sge->lo != pasync_handle->pa.u.a32.address_hi);
1779 pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
1780 pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
1781
1782 *slot = pasync_handle;
1783 if (++prod == cons)
1784 break;
6733b39a 1785 }
938f372c
JB		 1786 if (header)
1787 pasync_ctx->async_header.free_entries -= prod;
1788 else
1789 pasync_ctx->async_data.free_entries -= prod;
6733b39a 1790
938f372c
JB		 1791 doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
1792 doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
1793 doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
1794 doorbell |= (prod & DB_DEF_PDU_CQPROC_MASK) << DB_DEF_PDU_CQPROC_SHIFT;
1795 iowrite32(doorbell, phba->db_va + doorbell_offset);
6733b39a
JK		 1796}
1797
938f372c
JB		 1798static void
1799beiscsi_hdq_process_compl(struct beiscsi_conn *beiscsi_conn,
1800 struct i_t_dpdu_cqe *pdpdu_cqe)
6733b39a 1801{
938f372c
JB		 1802 struct beiscsi_hba *phba = beiscsi_conn->phba;
1803 struct hd_async_handle *pasync_handle = NULL;
1804 struct hd_async_context *pasync_ctx;
6733b39a 1805 struct hwi_controller *phwi_ctrlr;
938f372c
JB		 1806 u16 cid_cri;
1807 u8 ulp_num;
6733b39a
JK		 1808
1809 phwi_ctrlr = phba->phwi_ctrlr;
938f372c
JB		 1810 cid_cri = BE_GET_CRI_FROM_CID(beiscsi_conn->beiscsi_conn_cid);
1811 ulp_num = BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cid_cri);
1812 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num);
1813 pasync_handle = beiscsi_hdl_get_handle(beiscsi_conn, pasync_ctx,
1814 pdpdu_cqe);
1815 if (!pasync_handle)
1816 return;
99bc5d55 1817
938f372c
JB		 1818 beiscsi_hdl_gather_pdu(beiscsi_conn, pasync_ctx, pasync_handle);
1819 beiscsi_hdq_post_handles(phba, pasync_handle->is_header, ulp_num);
6733b39a
JK		 1820}
1821
2e4e8f65 1822void beiscsi_process_mcc_cq(struct beiscsi_hba *phba)
756d29c8
JK		 1823{
1824 struct be_queue_info *mcc_cq;
1825 struct be_mcc_compl *mcc_compl;
1826 unsigned int num_processed = 0;
1827
1828 mcc_cq = &phba->ctrl.mcc_obj.cq;
1829 mcc_compl = queue_tail_node(mcc_cq);
1830 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
1831 while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
9122e991
JB		 1832 if (beiscsi_hba_in_error(phba))
1833 return;
1834
756d29c8
JK		 1835 if (num_processed >= 32) {
1836 hwi_ring_cq_db(phba, mcc_cq->id,
1094cf68 1837 num_processed, 0);
756d29c8
JK		 1838 num_processed = 0;
1839 }
1840 if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
53aefe25 1841 beiscsi_process_async_event(phba, mcc_compl);
756d29c8 1842 } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
2e4e8f65 1843 beiscsi_process_mcc_compl(&phba->ctrl, mcc_compl);
756d29c8
JK		 1844 }
1845
1846 mcc_compl->flags = 0;
1847 queue_tail_inc(mcc_cq);
1848 mcc_compl = queue_tail_node(mcc_cq);
1849 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
1850 num_processed++;
1851 }
1852
1853 if (num_processed > 0)
1094cf68 1854 hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1);
756d29c8 1855}
bfead3b2 1856
a3095016
JB		 1857static void beiscsi_mcc_work(struct work_struct *work)
1858{
1859 struct be_eq_obj *pbe_eq;
1860 struct beiscsi_hba *phba;
1861
1862 pbe_eq = container_of(work, struct be_eq_obj, mcc_work);
1863 phba = pbe_eq->phba;
1864 beiscsi_process_mcc_cq(phba);
1865 /* rearm EQ for further interrupts */
9122e991
JB		 1866 if (!beiscsi_hba_in_error(phba))
1867 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
a3095016
JB		 1868}
1869
6763daae
JSJ		 1870/**
1871 * beiscsi_process_cq()- Process the Completion Queue
1872 * @pbe_eq: Event Q on which the Completion has come
1094cf68 1873 * @budget: Max number of events to processed
6763daae
JSJ		 1874 *
1875 * return
1876 * Number of Completion Entries processed.
1877 **/
1094cf68 1878unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget)
6733b39a 1879{
6733b39a
JK		 1880 struct be_queue_info *cq;
1881 struct sol_cqe *sol;
1882 struct dmsg_cqe *dmsg;
1094cf68 1883 unsigned int total = 0;
6733b39a 1884 unsigned int num_processed = 0;
0a513dd8 1885 unsigned short code = 0, cid = 0;
a7909b39 1886 uint16_t cri_index = 0;
6733b39a 1887 struct beiscsi_conn *beiscsi_conn;
c2462288
JK		 1888 struct beiscsi_endpoint *beiscsi_ep;
1889 struct iscsi_endpoint *ep;
bfead3b2 1890 struct beiscsi_hba *phba;
6733b39a 1891
bfead3b2 1892 cq = pbe_eq->cq;
6733b39a 1893 sol = queue_tail_node(cq);
bfead3b2 1894 phba = pbe_eq->phba;
6733b39a
JK		 1895
1896 while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
1897 CQE_VALID_MASK) {
9122e991
JB		 1898 if (beiscsi_hba_in_error(phba))
1899 return 0;
1900
6733b39a
JK		 1901 be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
1902
73133261
JSJ		 1903 code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
1904 32] & CQE_CODE_MASK);
1905
1906 /* Get the CID */
2c9dfd36
JK		 1907 if (is_chip_be2_be3r(phba)) {
1908 cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol);
1909 } else {
73133261
JSJ		 1910 if ((code == DRIVERMSG_NOTIFY) ||
1911 (code == UNSOL_HDR_NOTIFY) ||
1912 (code == UNSOL_DATA_NOTIFY))
1913 cid = AMAP_GET_BITS(
1914 struct amap_i_t_dpdu_cqe_v2,
1915 cid, sol);
1916 else
1917 cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1918 cid, sol);
2c9dfd36 1919 }
32951dd8 1920
a7909b39
JK		 1921 cri_index = BE_GET_CRI_FROM_CID(cid);
1922 ep = phba->ep_array[cri_index];
b7ab35b1
JK		 1923
1924 if (ep == NULL) {
1925 /* connection has already been freed
1926 * just move on to next one
1927 */
1928 beiscsi_log(phba, KERN_WARNING,
1929 BEISCSI_LOG_INIT,
1930 "BM_%d : proc cqe of disconn ep: cid %d\n",
1931 cid);
1932 goto proc_next_cqe;
1933 }
1934
c2462288
JK		 1935 beiscsi_ep = ep->dd_data;
1936 beiscsi_conn = beiscsi_ep->conn;
756d29c8 1937
1094cf68
JB		 1938 /* replenish cq */
1939 if (num_processed == 32) {
1940 hwi_ring_cq_db(phba, cq->id, 32, 0);
6733b39a
JK		 1941 num_processed = 0;
1942 }
1094cf68 1943 total++;
6733b39a 1944
0a513dd8 1945 switch (code) {
6733b39a
JK		 1946 case SOL_CMD_COMPLETE:
1947 hwi_complete_cmd(beiscsi_conn, phba, sol);
1948 break;
1949 case DRIVERMSG_NOTIFY:
99bc5d55
JSJ		 1950 beiscsi_log(phba, KERN_INFO,
1951 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 1952 "BM_%d : Received %s[%d] on CID : %d\n",
1953 cqe_desc[code], code, cid);
99bc5d55 1954
6733b39a
JK		 1955 dmsg = (struct dmsg_cqe *)sol;
1956 hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
1957 break;
1958 case UNSOL_HDR_NOTIFY:
99bc5d55
JSJ		 1959 beiscsi_log(phba, KERN_INFO,
1960 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 1961 "BM_%d : Received %s[%d] on CID : %d\n",
1962 cqe_desc[code], code, cid);
99bc5d55 1963
8f09a3b9 1964 spin_lock_bh(&phba->async_pdu_lock);
938f372c
JB		 1965 beiscsi_hdq_process_compl(beiscsi_conn,
1966 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 1967 spin_unlock_bh(&phba->async_pdu_lock);
bfead3b2 1968 break;
6733b39a 1969 case UNSOL_DATA_NOTIFY:
99bc5d55
JSJ		 1970 beiscsi_log(phba, KERN_INFO,
1971 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
6763daae
JSJ		 1972 "BM_%d : Received %s[%d] on CID : %d\n",
1973 cqe_desc[code], code, cid);
99bc5d55 1974
8f09a3b9 1975 spin_lock_bh(&phba->async_pdu_lock);
938f372c
JB		 1976 beiscsi_hdq_process_compl(beiscsi_conn,
1977 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 1978 spin_unlock_bh(&phba->async_pdu_lock);
6733b39a
JK		 1979 break;
1980 case CXN_INVALIDATE_INDEX_NOTIFY:
1981 case CMD_INVALIDATED_NOTIFY:
1982 case CXN_INVALIDATE_NOTIFY:
99bc5d55
JSJ		 1983 beiscsi_log(phba, KERN_ERR,
1984 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 1985 "BM_%d : Ignoring %s[%d] on CID : %d\n",
1986 cqe_desc[code], code, cid);
6733b39a 1987 break;
1094cf68 1988 case CXN_KILLED_HDR_DIGEST_ERR:
6733b39a 1989 case SOL_CMD_KILLED_DATA_DIGEST_ERR:
1094cf68
JB		 1990 beiscsi_log(phba, KERN_ERR,
1991 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1992 "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
1993 cqe_desc[code], code, cid);
1994 break;
6733b39a
JK		 1995 case CMD_KILLED_INVALID_STATSN_RCVD:
1996 case CMD_KILLED_INVALID_R2T_RCVD:
1997 case CMD_CXN_KILLED_LUN_INVALID:
1998 case CMD_CXN_KILLED_ICD_INVALID:
1999 case CMD_CXN_KILLED_ITT_INVALID:
2000 case CMD_CXN_KILLED_SEQ_OUTOFORDER:
2001 case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
99bc5d55
JSJ		 2002 beiscsi_log(phba, KERN_ERR,
2003 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
6763daae
JSJ		 2004 "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
2005 cqe_desc[code], code, cid);
6733b39a
JK		 2006 break;
2007 case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
99bc5d55
JSJ		 2008 beiscsi_log(phba, KERN_ERR,
2009 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2010 "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
2011 cqe_desc[code], code, cid);
8f09a3b9 2012 spin_lock_bh(&phba->async_pdu_lock);
938f372c
JB		 2013 /* driver consumes the entry and drops the contents */
2014 beiscsi_hdq_process_compl(beiscsi_conn,
2015 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 2016 spin_unlock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2017 break;
2018 case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
2019 case CXN_KILLED_BURST_LEN_MISMATCH:
2020 case CXN_KILLED_AHS_RCVD:
6733b39a
JK		 2021 case CXN_KILLED_UNKNOWN_HDR:
2022 case CXN_KILLED_STALE_ITT_TTT_RCVD:
2023 case CXN_KILLED_INVALID_ITT_TTT_RCVD:
2024 case CXN_KILLED_TIMED_OUT:
2025 case CXN_KILLED_FIN_RCVD:
6763daae
JSJ		 2026 case CXN_KILLED_RST_SENT:
2027 case CXN_KILLED_RST_RCVD:
6733b39a
JK		 2028 case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
2029 case CXN_KILLED_BAD_WRB_INDEX_ERROR:
2030 case CXN_KILLED_OVER_RUN_RESIDUAL:
2031 case CXN_KILLED_UNDER_RUN_RESIDUAL:
2032 case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
99bc5d55
JSJ		 2033 beiscsi_log(phba, KERN_ERR,
2034 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2035 "BM_%d : Event %s[%d] received on CID : %d\n",
2036 cqe_desc[code], code, cid);
0a513dd8
JSJ		 2037 if (beiscsi_conn)
2038 iscsi_conn_failure(beiscsi_conn->conn,
2039 ISCSI_ERR_CONN_FAILED);
6733b39a
JK		 2040 break;
2041 default:
99bc5d55
JSJ		 2042 beiscsi_log(phba, KERN_ERR,
2043 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2044 "BM_%d : Invalid CQE Event Received Code : %d"
2045 "CID 0x%x...\n",
0a513dd8 2046 code, cid);
6733b39a
JK		 2047 break;
2048 }
2049
b7ab35b1 2050proc_next_cqe:
6733b39a
JK		 2051 AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
2052 queue_tail_inc(cq);
2053 sol = queue_tail_node(cq);
2054 num_processed++;
1094cf68
JB		 2055 if (total == budget)
2056 break;
6733b39a
JK		 2057 }
2058
1094cf68
JB		 2059 hwi_ring_cq_db(phba, cq->id, num_processed, 1);
2060 return total;
6733b39a
JK		 2061}
2062
511cbce2 2063static int be_iopoll(struct irq_poll *iop, int budget)
6733b39a 2064{
a3095016 2065 unsigned int ret, io_events;
6733b39a 2066 struct beiscsi_hba *phba;
bfead3b2 2067 struct be_eq_obj *pbe_eq;
1094cf68
JB		 2068 struct be_eq_entry *eqe = NULL;
2069 struct be_queue_info *eq;
6733b39a 2070
bfead3b2 2071 pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
1094cf68 2072 phba = pbe_eq->phba;
9122e991
JB		 2073 if (beiscsi_hba_in_error(phba)) {
2074 irq_poll_complete(iop);
2075 return 0;
2076 }
2077
2078 io_events = 0;
1094cf68
JB		 2079 eq = &pbe_eq->q;
2080 eqe = queue_tail_node(eq);
1094cf68
JB		 2081 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] &
2082 EQE_VALID_MASK) {
2083 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
2084 queue_tail_inc(eq);
2085 eqe = queue_tail_node(eq);
a3095016 2086 io_events++;
1094cf68 2087 }
a3095016 2088 hwi_ring_eq_db(phba, eq->id, 1, io_events, 0, 1);
1094cf68
JB		 2089
2090 ret = beiscsi_process_cq(pbe_eq, budget);
73af08e1 2091 pbe_eq->cq_count += ret;
6733b39a 2092 if (ret < budget) {
511cbce2 2093 irq_poll_complete(iop);
99bc5d55
JSJ		 2094 beiscsi_log(phba, KERN_INFO,
2095 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1094cf68
JB		 2096 "BM_%d : rearm pbe_eq->q.id =%d ret %d\n",
2097 pbe_eq->q.id, ret);
9122e991
JB		 2098 if (!beiscsi_hba_in_error(phba))
2099 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
6733b39a
JK		 2100 }
2101 return ret;
2102}
2103
09a1093a
JSJ		 2104static void
2105hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg,
2106 unsigned int num_sg, struct beiscsi_io_task *io_task)
2107{
2108 struct iscsi_sge *psgl;
2109 unsigned int sg_len, index;
2110 unsigned int sge_len = 0;
2111 unsigned long long addr;
2112 struct scatterlist *l_sg;
2113 unsigned int offset;
2114
2115 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb,
2116 io_task->bhs_pa.u.a32.address_lo);
2117 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb,
2118 io_task->bhs_pa.u.a32.address_hi);
2119
2120 l_sg = sg;
2121 for (index = 0; (index < num_sg) && (index < 2); index++,
2122 sg = sg_next(sg)) {
2123 if (index == 0) {
2124 sg_len = sg_dma_len(sg);
2125 addr = (u64) sg_dma_address(sg);
2126 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2127 sge0_addr_lo, pwrb,
2128 lower_32_bits(addr));
2129 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2130 sge0_addr_hi, pwrb,
2131 upper_32_bits(addr));
2132 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2133 sge0_len, pwrb,
2134 sg_len);
2135 sge_len = sg_len;
2136 } else {
2137 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset,
2138 pwrb, sge_len);
2139 sg_len = sg_dma_len(sg);
2140 addr = (u64) sg_dma_address(sg);
2141 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2142 sge1_addr_lo, pwrb,
2143 lower_32_bits(addr));
2144 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2145 sge1_addr_hi, pwrb,
2146 upper_32_bits(addr));
2147 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2148 sge1_len, pwrb,
2149 sg_len);
2150 }
2151 }
2152 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2153 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2154
2155 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2156
2157 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2158 io_task->bhs_pa.u.a32.address_hi);
2159 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2160 io_task->bhs_pa.u.a32.address_lo);
2161
2162 if (num_sg == 1) {
2163 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2164 1);
2165 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2166 0);
2167 } else if (num_sg == 2) {
2168 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2169 0);
2170 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2171 1);
2172 } else {
2173 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2174 0);
2175 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2176 0);
2177 }
2178
2179 sg = l_sg;
2180 psgl++;
2181 psgl++;
2182 offset = 0;
2183 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
2184 sg_len = sg_dma_len(sg);
2185 addr = (u64) sg_dma_address(sg);
2186 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2187 lower_32_bits(addr));
2188 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2189 upper_32_bits(addr));
2190 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2191 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2192 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2193 offset += sg_len;
2194 }
2195 psgl--;
2196 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2197}
2198
6733b39a
JK		 2199static void
2200hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
2201 unsigned int num_sg, struct beiscsi_io_task *io_task)
2202{
2203 struct iscsi_sge *psgl;
58ff4bd0 2204 unsigned int sg_len, index;
6733b39a
JK		 2205 unsigned int sge_len = 0;
2206 unsigned long long addr;
2207 struct scatterlist *l_sg;
2208 unsigned int offset;
2209
2210 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2211 io_task->bhs_pa.u.a32.address_lo);
2212 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2213 io_task->bhs_pa.u.a32.address_hi);
2214
2215 l_sg = sg;
48bd86cf
JK		 2216 for (index = 0; (index < num_sg) && (index < 2); index++,
2217 sg = sg_next(sg)) {
6733b39a
JK		 2218 if (index == 0) {
2219 sg_len = sg_dma_len(sg);
2220 addr = (u64) sg_dma_address(sg);
2221 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
457ff3b7 2222 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2223 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
457ff3b7 2224 ((u32)(addr >> 32)));
6733b39a
JK		 2225 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2226 sg_len);
2227 sge_len = sg_len;
6733b39a 2228 } else {
6733b39a
JK		 2229 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
2230 pwrb, sge_len);
2231 sg_len = sg_dma_len(sg);
2232 addr = (u64) sg_dma_address(sg);
2233 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
457ff3b7 2234 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2235 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
457ff3b7 2236 ((u32)(addr >> 32)));
6733b39a
JK		 2237 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
2238 sg_len);
2239 }
2240 }
2241 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2242 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2243
2244 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2245
2246 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2247 io_task->bhs_pa.u.a32.address_hi);
2248 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2249 io_task->bhs_pa.u.a32.address_lo);
2250
caf818f1
JK		 2251 if (num_sg == 1) {
2252 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2253 1);
2254 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2255 0);
2256 } else if (num_sg == 2) {
2257 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2258 0);
2259 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2260 1);
2261 } else {
2262 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2263 0);
2264 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2265 0);
2266 }
6733b39a
JK		 2267 sg = l_sg;
2268 psgl++;
2269 psgl++;
2270 offset = 0;
48bd86cf 2271 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
6733b39a
JK		 2272 sg_len = sg_dma_len(sg);
2273 addr = (u64) sg_dma_address(sg);
2274 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2275 (addr & 0xFFFFFFFF));
2276 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2277 (addr >> 32));
2278 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2279 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2280 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2281 offset += sg_len;
2282 }
2283 psgl--;
2284 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2285}
2286
d629c471
JSJ		 2287/**
2288 * hwi_write_buffer()- Populate the WRB with task info
2289 * @pwrb: ptr to the WRB entry
2290 * @task: iscsi task which is to be executed
2291 **/
e0493627 2292static int hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
6733b39a
JK		 2293{
2294 struct iscsi_sge *psgl;
6733b39a
JK		 2295 struct beiscsi_io_task *io_task = task->dd_data;
2296 struct beiscsi_conn *beiscsi_conn = io_task->conn;
2297 struct beiscsi_hba *phba = beiscsi_conn->phba;
09a1093a 2298 uint8_t dsp_value = 0;
6733b39a
JK		 2299
2300 io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
2301 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2302 io_task->bhs_pa.u.a32.address_lo);
2303 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2304 io_task->bhs_pa.u.a32.address_hi);
2305
2306 if (task->data) {
09a1093a
JSJ		 2307
2308 /* Check for the data_count */
2309 dsp_value = (task->data_count) ? 1 : 0;
2310
2c9dfd36
JK		 2311 if (is_chip_be2_be3r(phba))
2312 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp,
09a1093a
JSJ		 2313 pwrb, dsp_value);
2314 else
2c9dfd36 2315 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp,
09a1093a
JSJ		 2316 pwrb, dsp_value);
2317
2318 /* Map addr only if there is data_count */
2319 if (dsp_value) {
d629c471
JSJ		 2320 io_task->mtask_addr = pci_map_single(phba->pcidev,
2321 task->data,
2322 task->data_count,
2323 PCI_DMA_TODEVICE);
e0493627
AK		 2324 if (pci_dma_mapping_error(phba->pcidev,
2325 io_task->mtask_addr))
2326 return -ENOMEM;
d629c471 2327 io_task->mtask_data_count = task->data_count;
09a1093a 2328 } else
d629c471 2329 io_task->mtask_addr = 0;
09a1093a 2330
6733b39a 2331 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
d629c471 2332 lower_32_bits(io_task->mtask_addr));
6733b39a 2333 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
d629c471 2334 upper_32_bits(io_task->mtask_addr));
6733b39a
JK		 2335 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2336 task->data_count);
2337
2338 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
2339 } else {
2340 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
d629c471 2341 io_task->mtask_addr = 0;
6733b39a
JK		 2342 }
2343
2344 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2345
2346 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
2347
2348 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2349 io_task->bhs_pa.u.a32.address_hi);
2350 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2351 io_task->bhs_pa.u.a32.address_lo);
2352 if (task->data) {
2353 psgl++;
2354 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
2355 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
2356 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
2357 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
2358 AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
2359 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2360
2361 psgl++;
2362 if (task->data) {
2363 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
d629c471 2364 lower_32_bits(io_task->mtask_addr));
6733b39a 2365 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
d629c471 2366 upper_32_bits(io_task->mtask_addr));
6733b39a
JK		 2367 }
2368 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
2369 }
2370 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
e0493627 2371 return 0;
6733b39a
JK		 2372}
2373
843ae752
JK		 2374/**
2375 * beiscsi_find_mem_req()- Find mem needed
2376 * @phba: ptr to HBA struct
2377 **/
6733b39a
JK		 2378static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
2379{
8a86e833 2380 uint8_t mem_descr_index, ulp_num;
fa1261c4 2381 unsigned int num_async_pdu_buf_pages;
6733b39a
JK		 2382 unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
2383 unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
2384
6733b39a
JK		 2385 phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
2386
2387 phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
2388 BE_ISCSI_PDU_HEADER_SIZE;
2389 phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
2390 sizeof(struct hwi_context_memory);
2391
6733b39a
JK		 2392
2393 phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
2394 * (phba->params.wrbs_per_cxn)
2395 * phba->params.cxns_per_ctrl;
2396 wrb_sz_per_cxn = sizeof(struct wrb_handle) *
2397 (phba->params.wrbs_per_cxn);
2398 phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
2399 phba->params.cxns_per_ctrl);
2400
2401 phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
2402 phba->params.icds_per_ctrl;
2403 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
2404 phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
8a86e833
JK		 2405 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
2406 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 2407
8a86e833
JK		 2408 num_async_pdu_buf_sgl_pages =
2409 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2410 phba, ulp_num) *
2411 sizeof(struct phys_addr));
2412
2413 num_async_pdu_buf_pages =
2414 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2415 phba, ulp_num) *
2416 phba->params.defpdu_hdr_sz);
2417
2418 num_async_pdu_data_pages =
2419 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2420 phba, ulp_num) *
2421 phba->params.defpdu_data_sz);
2422
2423 num_async_pdu_data_sgl_pages =
2424 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2425 phba, ulp_num) *
2426 sizeof(struct phys_addr));
2427
a129d92f
JK		 2428 mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 +
2429 (ulp_num * MEM_DESCR_OFFSET));
2430 phba->mem_req[mem_descr_index] =
2431 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2432 BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
2433
8a86e833
JK		 2434 mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
2435 (ulp_num * MEM_DESCR_OFFSET));
2436 phba->mem_req[mem_descr_index] =
2437 num_async_pdu_buf_pages *
2438 PAGE_SIZE;
2439
2440 mem_descr_index = (HWI_MEM_ASYNC_DATA_BUF_ULP0 +
2441 (ulp_num * MEM_DESCR_OFFSET));
2442 phba->mem_req[mem_descr_index] =
2443 num_async_pdu_data_pages *
2444 PAGE_SIZE;
2445
2446 mem_descr_index = (HWI_MEM_ASYNC_HEADER_RING_ULP0 +
2447 (ulp_num * MEM_DESCR_OFFSET));
2448 phba->mem_req[mem_descr_index] =
2449 num_async_pdu_buf_sgl_pages *
2450 PAGE_SIZE;
2451
2452 mem_descr_index = (HWI_MEM_ASYNC_DATA_RING_ULP0 +
2453 (ulp_num * MEM_DESCR_OFFSET));
2454 phba->mem_req[mem_descr_index] =
2455 num_async_pdu_data_sgl_pages *
2456 PAGE_SIZE;
2457
2458 mem_descr_index = (HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
2459 (ulp_num * MEM_DESCR_OFFSET));
2460 phba->mem_req[mem_descr_index] =
2461 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
938f372c 2462 sizeof(struct hd_async_handle);
8a86e833
JK		 2463
2464 mem_descr_index = (HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
2465 (ulp_num * MEM_DESCR_OFFSET));
2466 phba->mem_req[mem_descr_index] =
2467 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
938f372c 2468 sizeof(struct hd_async_handle);
8a86e833
JK		 2469
2470 mem_descr_index = (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
2471 (ulp_num * MEM_DESCR_OFFSET));
2472 phba->mem_req[mem_descr_index] =
938f372c 2473 sizeof(struct hd_async_context) +
8a86e833 2474 (BEISCSI_GET_CID_COUNT(phba, ulp_num) *
938f372c 2475 sizeof(struct hd_async_entry));
8a86e833
JK		 2476 }
2477 }
6733b39a
JK		 2478}
2479
2480static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
2481{
6733b39a 2482 dma_addr_t bus_add;
a7909b39
JK		 2483 struct hwi_controller *phwi_ctrlr;
2484 struct be_mem_descriptor *mem_descr;
6733b39a
JK		 2485 struct mem_array *mem_arr, *mem_arr_orig;
2486 unsigned int i, j, alloc_size, curr_alloc_size;
2487
3ec78271 2488 phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
6733b39a
JK		 2489 if (!phba->phwi_ctrlr)
2490 return -ENOMEM;
2491
a7909b39
JK		 2492 /* Allocate memory for wrb_context */
2493 phwi_ctrlr = phba->phwi_ctrlr;
2494 phwi_ctrlr->wrb_context = kzalloc(sizeof(struct hwi_wrb_context) *
2495 phba->params.cxns_per_ctrl,
2496 GFP_KERNEL);
0c88740d
ML		 2497 if (!phwi_ctrlr->wrb_context) {
2498 kfree(phba->phwi_ctrlr);
a7909b39 2499 return -ENOMEM;
0c88740d 2500 }
a7909b39 2501
6733b39a
JK		 2502 phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
2503 GFP_KERNEL);
2504 if (!phba->init_mem) {
a7909b39 2505 kfree(phwi_ctrlr->wrb_context);
6733b39a
JK		 2506 kfree(phba->phwi_ctrlr);
2507 return -ENOMEM;
2508 }
2509
2510 mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
2511 GFP_KERNEL);
2512 if (!mem_arr_orig) {
2513 kfree(phba->init_mem);
a7909b39 2514 kfree(phwi_ctrlr->wrb_context);
6733b39a
JK		 2515 kfree(phba->phwi_ctrlr);
2516 return -ENOMEM;
2517 }
2518
2519 mem_descr = phba->init_mem;
2520 for (i = 0; i < SE_MEM_MAX; i++) {
8a86e833
JK		 2521 if (!phba->mem_req[i]) {
2522 mem_descr->mem_array = NULL;
2523 mem_descr++;
2524 continue;
2525 }
2526
6733b39a
JK		 2527 j = 0;
2528 mem_arr = mem_arr_orig;
2529 alloc_size = phba->mem_req[i];
2530 memset(mem_arr, 0, sizeof(struct mem_array) *
2531 BEISCSI_MAX_FRAGS_INIT);
2532 curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
2533 do {
2534 mem_arr->virtual_address = pci_alloc_consistent(
2535 phba->pcidev,
2536 curr_alloc_size,
2537 &bus_add);
2538 if (!mem_arr->virtual_address) {
2539 if (curr_alloc_size <= BE_MIN_MEM_SIZE)
2540 goto free_mem;
2541 if (curr_alloc_size -
2542 rounddown_pow_of_two(curr_alloc_size))
2543 curr_alloc_size = rounddown_pow_of_two
2544 (curr_alloc_size);
2545 else
2546 curr_alloc_size = curr_alloc_size / 2;
2547 } else {
2548 mem_arr->bus_address.u.
2549 a64.address = (__u64) bus_add;
2550 mem_arr->size = curr_alloc_size;
2551 alloc_size -= curr_alloc_size;
2552 curr_alloc_size = min(be_max_phys_size *
2553 1024, alloc_size);
2554 j++;
2555 mem_arr++;
2556 }
2557 } while (alloc_size);
2558 mem_descr->num_elements = j;
2559 mem_descr->size_in_bytes = phba->mem_req[i];
2560 mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
2561 GFP_KERNEL);
2562 if (!mem_descr->mem_array)
2563 goto free_mem;
2564
2565 memcpy(mem_descr->mem_array, mem_arr_orig,
2566 sizeof(struct mem_array) * j);
2567 mem_descr++;
2568 }
2569 kfree(mem_arr_orig);
2570 return 0;
2571free_mem:
2572 mem_descr->num_elements = j;
2573 while ((i) || (j)) {
2574 for (j = mem_descr->num_elements; j > 0; j--) {
2575 pci_free_consistent(phba->pcidev,
2576 mem_descr->mem_array[j - 1].size,
2577 mem_descr->mem_array[j - 1].
2578 virtual_address,
457ff3b7
JK		 2579 (unsigned long)mem_descr->
2580 mem_array[j - 1].
6733b39a
JK		 2581 bus_address.u.a64.address);
2582 }
2583 if (i) {
2584 i--;
2585 kfree(mem_descr->mem_array);
2586 mem_descr--;
2587 }
2588 }
2589 kfree(mem_arr_orig);
2590 kfree(phba->init_mem);
a7909b39 2591 kfree(phba->phwi_ctrlr->wrb_context);
6733b39a
JK		 2592 kfree(phba->phwi_ctrlr);
2593 return -ENOMEM;
2594}
2595
2596static int beiscsi_get_memory(struct beiscsi_hba *phba)
2597{
2598 beiscsi_find_mem_req(phba);
2599 return beiscsi_alloc_mem(phba);
2600}
2601
2602static void iscsi_init_global_templates(struct beiscsi_hba *phba)
2603{
2604 struct pdu_data_out *pdata_out;
2605 struct pdu_nop_out *pnop_out;
2606 struct be_mem_descriptor *mem_descr;
2607
2608 mem_descr = phba->init_mem;
2609 mem_descr += ISCSI_MEM_GLOBAL_HEADER;
2610 pdata_out =
2611 (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
2612 memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2613
2614 AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
2615 IIOC_SCSI_DATA);
2616
2617 pnop_out =
2618 (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
2619 virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
2620
2621 memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2622 AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
2623 AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
2624 AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
2625}
2626
3ec78271 2627static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
6733b39a
JK		 2628{
2629 struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
a7909b39 2630 struct hwi_context_memory *phwi_ctxt;
3ec78271 2631 struct wrb_handle *pwrb_handle = NULL;
6733b39a
JK		 2632 struct hwi_controller *phwi_ctrlr;
2633 struct hwi_wrb_context *pwrb_context;
3ec78271
JK		 2634 struct iscsi_wrb *pwrb = NULL;
2635 unsigned int num_cxn_wrbh = 0;
2636 unsigned int num_cxn_wrb = 0, j, idx = 0, index;
6733b39a
JK		 2637
2638 mem_descr_wrbh = phba->init_mem;
2639 mem_descr_wrbh += HWI_MEM_WRBH;
2640
2641 mem_descr_wrb = phba->init_mem;
2642 mem_descr_wrb += HWI_MEM_WRB;
6733b39a
JK		 2643 phwi_ctrlr = phba->phwi_ctrlr;
2644
a7909b39
JK		 2645 /* Allocate memory for WRBQ */
2646 phwi_ctxt = phwi_ctrlr->phwi_ctxt;
2647 phwi_ctxt->be_wrbq = kzalloc(sizeof(struct be_queue_info) *
843ae752 2648 phba->params.cxns_per_ctrl,
a7909b39
JK		 2649 GFP_KERNEL);
2650 if (!phwi_ctxt->be_wrbq) {
2651 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2652 "BM_%d : WRBQ Mem Alloc Failed\n");
2653 return -ENOMEM;
2654 }
2655
2656 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a 2657 pwrb_context = &phwi_ctrlr->wrb_context[index];
6733b39a
JK		 2658 pwrb_context->pwrb_handle_base =
2659 kzalloc(sizeof(struct wrb_handle *) *
2660 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271 2661 if (!pwrb_context->pwrb_handle_base) {
99bc5d55
JSJ		 2662 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2663 "BM_%d : Mem Alloc Failed. Failing to load\n");
3ec78271
JK		 2664 goto init_wrb_hndl_failed;
2665 }
6733b39a
JK		 2666 pwrb_context->pwrb_handle_basestd =
2667 kzalloc(sizeof(struct wrb_handle *) *
2668 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271 2669 if (!pwrb_context->pwrb_handle_basestd) {
99bc5d55
JSJ		 2670 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2671 "BM_%d : Mem Alloc Failed. Failing to load\n");
3ec78271
JK		 2672 goto init_wrb_hndl_failed;
2673 }
2674 if (!num_cxn_wrbh) {
2675 pwrb_handle =
2676 mem_descr_wrbh->mem_array[idx].virtual_address;
2677 num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
2678 ((sizeof(struct wrb_handle)) *
2679 phba->params.wrbs_per_cxn));
2680 idx++;
2681 }
2682 pwrb_context->alloc_index = 0;
2683 pwrb_context->wrb_handles_available = 0;
2684 pwrb_context->free_index = 0;
2685
6733b39a 2686 if (num_cxn_wrbh) {
6733b39a
JK		 2687 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2688 pwrb_context->pwrb_handle_base[j] = pwrb_handle;
2689 pwrb_context->pwrb_handle_basestd[j] =
2690 pwrb_handle;
2691 pwrb_context->wrb_handles_available++;
bfead3b2 2692 pwrb_handle->wrb_index = j;
6733b39a
JK		 2693 pwrb_handle++;
2694 }
6733b39a
JK		 2695 num_cxn_wrbh--;
2696 }
f64d92e6 2697 spin_lock_init(&pwrb_context->wrb_lock);
6733b39a
JK		 2698 }
2699 idx = 0;
a7909b39 2700 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a 2701 pwrb_context = &phwi_ctrlr->wrb_context[index];
3ec78271 2702 if (!num_cxn_wrb) {
6733b39a 2703 pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
7c56533c 2704 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
3ec78271
JK		 2705 ((sizeof(struct iscsi_wrb) *
2706 phba->params.wrbs_per_cxn));
2707 idx++;
2708 }
2709
2710 if (num_cxn_wrb) {
6733b39a
JK		 2711 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2712 pwrb_handle = pwrb_context->pwrb_handle_base[j];
2713 pwrb_handle->pwrb = pwrb;
2714 pwrb++;
2715 }
2716 num_cxn_wrb--;
2717 }
2718 }
3ec78271
JK		 2719 return 0;
2720init_wrb_hndl_failed:
2721 for (j = index; j > 0; j--) {
2722 pwrb_context = &phwi_ctrlr->wrb_context[j];
2723 kfree(pwrb_context->pwrb_handle_base);
2724 kfree(pwrb_context->pwrb_handle_basestd);
2725 }
2726 return -ENOMEM;
6733b39a
JK		 2727}
2728
a7909b39 2729static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
6733b39a 2730{
8a86e833 2731 uint8_t ulp_num;
6733b39a
JK		 2732 struct hwi_controller *phwi_ctrlr;
2733 struct hba_parameters *p = &phba->params;
938f372c
JB		 2734 struct hd_async_context *pasync_ctx;
2735 struct hd_async_handle *pasync_header_h, *pasync_data_h;
dc63aac6 2736 unsigned int index, idx, num_per_mem, num_async_data;
6733b39a
JK		 2737 struct be_mem_descriptor *mem_descr;
2738
8a86e833
JK		 2739 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
2740 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
d7401055 2741 /* get async_ctx for each ULP */
8a86e833
JK		 2742 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2743 mem_descr += (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
2744 (ulp_num * MEM_DESCR_OFFSET));
2745
2746 phwi_ctrlr = phba->phwi_ctrlr;
2747 phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num] =
938f372c 2748 (struct hd_async_context *)
8a86e833
JK		 2749 mem_descr->mem_array[0].virtual_address;
2750
2751 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
2752 memset(pasync_ctx, 0, sizeof(*pasync_ctx));
2753
2754 pasync_ctx->async_entry =
938f372c 2755 (struct hd_async_entry *)
8a86e833 2756 ((long unsigned int)pasync_ctx +
938f372c 2757 sizeof(struct hd_async_context));
8a86e833
JK		 2758
2759 pasync_ctx->num_entries = BEISCSI_GET_CID_COUNT(phba,
2760 ulp_num);
938f372c 2761 /* setup header buffers */
8a86e833
JK		 2762 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2763 mem_descr += HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
2764 (ulp_num * MEM_DESCR_OFFSET);
2765 if (mem_descr->mem_array[0].virtual_address) {
2766 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2767 "BM_%d : hwi_init_async_pdu_ctx"
2768 " HWI_MEM_ASYNC_HEADER_BUF_ULP%d va=%p\n",
2769 ulp_num,
2770 mem_descr->mem_array[0].
2771 virtual_address);
2772 } else
2773 beiscsi_log(phba, KERN_WARNING,
2774 BEISCSI_LOG_INIT,
2775 "BM_%d : No Virtual address for ULP : %d\n",
2776 ulp_num);
2777
938f372c 2778 pasync_ctx->async_header.buffer_size = p->defpdu_hdr_sz;
8a86e833 2779 pasync_ctx->async_header.va_base =
6733b39a 2780 mem_descr->mem_array[0].virtual_address;
6733b39a 2781
8a86e833
JK		 2782 pasync_ctx->async_header.pa_base.u.a64.address =
2783 mem_descr->mem_array[0].
2784 bus_address.u.a64.address;
6733b39a 2785
938f372c 2786 /* setup header buffer sgls */
8a86e833
JK		 2787 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2788 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
2789 (ulp_num * MEM_DESCR_OFFSET);
2790 if (mem_descr->mem_array[0].virtual_address) {
2791 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2792 "BM_%d : hwi_init_async_pdu_ctx"
2793 " HWI_MEM_ASYNC_HEADER_RING_ULP%d va=%p\n",
2794 ulp_num,
2795 mem_descr->mem_array[0].
2796 virtual_address);
2797 } else
2798 beiscsi_log(phba, KERN_WARNING,
2799 BEISCSI_LOG_INIT,
2800 "BM_%d : No Virtual address for ULP : %d\n",
2801 ulp_num);
2802
2803 pasync_ctx->async_header.ring_base =
2804 mem_descr->mem_array[0].virtual_address;
6733b39a 2805
938f372c 2806 /* setup header buffer handles */
8a86e833
JK		 2807 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2808 mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
2809 (ulp_num * MEM_DESCR_OFFSET);
2810 if (mem_descr->mem_array[0].virtual_address) {
2811 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2812 "BM_%d : hwi_init_async_pdu_ctx"
2813 " HWI_MEM_ASYNC_HEADER_HANDLE_ULP%d va=%p\n",
2814 ulp_num,
2815 mem_descr->mem_array[0].
2816 virtual_address);
2817 } else
2818 beiscsi_log(phba, KERN_WARNING,
2819 BEISCSI_LOG_INIT,
2820 "BM_%d : No Virtual address for ULP : %d\n",
2821 ulp_num);
2822
2823 pasync_ctx->async_header.handle_base =
2824 mem_descr->mem_array[0].virtual_address;
8a86e833
JK		 2825 INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
2826
938f372c 2827 /* setup data buffer sgls */
8a86e833
JK		 2828 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2829 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
2830 (ulp_num * MEM_DESCR_OFFSET);
2831 if (mem_descr->mem_array[0].virtual_address) {
2832 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2833 "BM_%d : hwi_init_async_pdu_ctx"
2834 " HWI_MEM_ASYNC_DATA_RING_ULP%d va=%p\n",
2835 ulp_num,
2836 mem_descr->mem_array[0].
2837 virtual_address);
2838 } else
2839 beiscsi_log(phba, KERN_WARNING,
2840 BEISCSI_LOG_INIT,
2841 "BM_%d : No Virtual address for ULP : %d\n",
2842 ulp_num);
2843
2844 pasync_ctx->async_data.ring_base =
2845 mem_descr->mem_array[0].virtual_address;
6733b39a 2846
938f372c 2847 /* setup data buffer handles */
8a86e833
JK		 2848 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2849 mem_descr += HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
2850 (ulp_num * MEM_DESCR_OFFSET);
2851 if (!mem_descr->mem_array[0].virtual_address)
2852 beiscsi_log(phba, KERN_WARNING,
2853 BEISCSI_LOG_INIT,
2854 "BM_%d : No Virtual address for ULP : %d\n",
2855 ulp_num);
99bc5d55 2856
8a86e833
JK		 2857 pasync_ctx->async_data.handle_base =
2858 mem_descr->mem_array[0].virtual_address;
8a86e833
JK		 2859 INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
2860
2861 pasync_header_h =
938f372c 2862 (struct hd_async_handle *)
8a86e833
JK		 2863 pasync_ctx->async_header.handle_base;
2864 pasync_data_h =
938f372c 2865 (struct hd_async_handle *)
8a86e833
JK		 2866 pasync_ctx->async_data.handle_base;
2867
938f372c 2868 /* setup data buffers */
8a86e833
JK		 2869 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2870 mem_descr += HWI_MEM_ASYNC_DATA_BUF_ULP0 +
2871 (ulp_num * MEM_DESCR_OFFSET);
2872 if (mem_descr->mem_array[0].virtual_address) {
2873 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2874 "BM_%d : hwi_init_async_pdu_ctx"
2875 " HWI_MEM_ASYNC_DATA_BUF_ULP%d va=%p\n",
2876 ulp_num,
2877 mem_descr->mem_array[0].
2878 virtual_address);
2879 } else
2880 beiscsi_log(phba, KERN_WARNING,
2881 BEISCSI_LOG_INIT,
2882 "BM_%d : No Virtual address for ULP : %d\n",
2883 ulp_num);
2884
2885 idx = 0;
938f372c 2886 pasync_ctx->async_data.buffer_size = p->defpdu_data_sz;
dc63aac6
JK		 2887 pasync_ctx->async_data.va_base =
2888 mem_descr->mem_array[idx].virtual_address;
2889 pasync_ctx->async_data.pa_base.u.a64.address =
2890 mem_descr->mem_array[idx].
2891 bus_address.u.a64.address;
2892
2893 num_async_data = ((mem_descr->mem_array[idx].size) /
2894 phba->params.defpdu_data_sz);
8a86e833 2895 num_per_mem = 0;
6733b39a 2896
8a86e833
JK		 2897 for (index = 0; index < BEISCSI_GET_CID_COUNT
2898 (phba, ulp_num); index++) {
2899 pasync_header_h->cri = -1;
938f372c
JB		 2900 pasync_header_h->is_header = 1;
2901 pasync_header_h->index = index;
8a86e833
JK		 2902 INIT_LIST_HEAD(&pasync_header_h->link);
2903 pasync_header_h->pbuffer =
2904 (void *)((unsigned long)
2905 (pasync_ctx->
2906 async_header.va_base) +
2907 (p->defpdu_hdr_sz * index));
2908
2909 pasync_header_h->pa.u.a64.address =
2910 pasync_ctx->async_header.pa_base.u.a64.
2911 address + (p->defpdu_hdr_sz * index);
2912
2913 list_add_tail(&pasync_header_h->link,
2914 &pasync_ctx->async_header.
2915 free_list);
2916 pasync_header_h++;
2917 pasync_ctx->async_header.free_entries++;
8a86e833 2918 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
938f372c
JB		 2919 wq.list);
2920 pasync_ctx->async_entry[index].header = NULL;
2921
8a86e833 2922 pasync_data_h->cri = -1;
938f372c
JB		 2923 pasync_data_h->is_header = 0;
2924 pasync_data_h->index = index;
8a86e833
JK		 2925 INIT_LIST_HEAD(&pasync_data_h->link);
2926
2927 if (!num_async_data) {
2928 num_per_mem = 0;
2929 idx++;
2930 pasync_ctx->async_data.va_base =
2931 mem_descr->mem_array[idx].
2932 virtual_address;
2933 pasync_ctx->async_data.pa_base.u.
2934 a64.address =
2935 mem_descr->mem_array[idx].
2936 bus_address.u.a64.address;
2937 num_async_data =
2938 ((mem_descr->mem_array[idx].
2939 size) /
2940 phba->params.defpdu_data_sz);
2941 }
2942 pasync_data_h->pbuffer =
2943 (void *)((unsigned long)
2944 (pasync_ctx->async_data.va_base) +
2945 (p->defpdu_data_sz * num_per_mem));
2946
2947 pasync_data_h->pa.u.a64.address =
2948 pasync_ctx->async_data.pa_base.u.a64.
2949 address + (p->defpdu_data_sz *
2950 num_per_mem);
2951 num_per_mem++;
2952 num_async_data--;
2953
2954 list_add_tail(&pasync_data_h->link,
2955 &pasync_ctx->async_data.
2956 free_list);
2957 pasync_data_h++;
2958 pasync_ctx->async_data.free_entries++;
938f372c 2959 pasync_ctx->async_entry[index].data = NULL;
8a86e833 2960 }
8a86e833 2961 }
6733b39a
JK		 2962 }
2963
a7909b39 2964 return 0;
6733b39a
JK		 2965}
2966
2967static int
2968be_sgl_create_contiguous(void *virtual_address,
2969 u64 physical_address, u32 length,
2970 struct be_dma_mem *sgl)
2971{
2972 WARN_ON(!virtual_address);
2973 WARN_ON(!physical_address);
dd29dae0 2974 WARN_ON(!length);
6733b39a
JK		 2975 WARN_ON(!sgl);
2976
2977 sgl->va = virtual_address;
457ff3b7 2978 sgl->dma = (unsigned long)physical_address;
6733b39a
JK		 2979 sgl->size = length;
2980
2981 return 0;
2982}
2983
2984static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
2985{
2986 memset(sgl, 0, sizeof(*sgl));
2987}
2988
2989static void
2990hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
2991 struct mem_array *pmem, struct be_dma_mem *sgl)
2992{
2993 if (sgl->va)
2994 be_sgl_destroy_contiguous(sgl);
2995
2996 be_sgl_create_contiguous(pmem->virtual_address,
2997 pmem->bus_address.u.a64.address,
2998 pmem->size, sgl);
2999}
3000
3001static void
3002hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
3003 struct mem_array *pmem, struct be_dma_mem *sgl)
3004{
3005 if (sgl->va)
3006 be_sgl_destroy_contiguous(sgl);
3007
3008 be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
3009 pmem->bus_address.u.a64.address,
3010 pmem->size, sgl);
3011}
3012
3013static int be_fill_queue(struct be_queue_info *q,
3014 u16 len, u16 entry_size, void *vaddress)
3015{
3016 struct be_dma_mem *mem = &q->dma_mem;
3017
3018 memset(q, 0, sizeof(*q));
3019 q->len = len;
3020 q->entry_size = entry_size;
3021 mem->size = len * entry_size;
3022 mem->va = vaddress;
3023 if (!mem->va)
3024 return -ENOMEM;
3025 memset(mem->va, 0, mem->size);
3026 return 0;
3027}
3028
bfead3b2 3029static int beiscsi_create_eqs(struct beiscsi_hba *phba,
6733b39a
JK		 3030 struct hwi_context_memory *phwi_context)
3031{
deeea8ed 3032 int ret = -ENOMEM, eq_for_mcc;
bfead3b2 3033 unsigned int i, num_eq_pages;
6733b39a
JK		 3034 struct be_queue_info *eq;
3035 struct be_dma_mem *mem;
6733b39a 3036 void *eq_vaddress;
bfead3b2 3037 dma_addr_t paddr;
6733b39a 3038
bfead3b2
JK		 3039 num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
3040 sizeof(struct be_eq_entry));
6733b39a 3041
bfead3b2
JK		 3042 if (phba->msix_enabled)
3043 eq_for_mcc = 1;
3044 else
3045 eq_for_mcc = 0;
3046 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
3047 eq = &phwi_context->be_eq[i].q;
3048 mem = &eq->dma_mem;
3049 phwi_context->be_eq[i].phba = phba;
3050 eq_vaddress = pci_alloc_consistent(phba->pcidev,
deeea8ed
CJ		 3051 num_eq_pages * PAGE_SIZE,
3052 &paddr);
84a261ff
PB		 3053 if (!eq_vaddress) {
3054 ret = -ENOMEM;
bfead3b2 3055 goto create_eq_error;
84a261ff 3056 }
bfead3b2
JK		 3057
3058 mem->va = eq_vaddress;
3059 ret = be_fill_queue(eq, phba->params.num_eq_entries,
3060 sizeof(struct be_eq_entry), eq_vaddress);
3061 if (ret) {
99bc5d55
JSJ		 3062 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3063 "BM_%d : be_fill_queue Failed for EQ\n");
bfead3b2
JK		 3064 goto create_eq_error;
3065 }
6733b39a 3066
bfead3b2
JK		 3067 mem->dma = paddr;
3068 ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
3069 phwi_context->cur_eqd);
3070 if (ret) {
99bc5d55
JSJ		 3071 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3072 "BM_%d : beiscsi_cmd_eq_create"
3073 "Failed for EQ\n");
bfead3b2
JK		 3074 goto create_eq_error;
3075 }
99bc5d55
JSJ		 3076
3077 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3078 "BM_%d : eqid = %d\n",
3079 phwi_context->be_eq[i].q.id);
6733b39a 3080 }
6733b39a 3081 return 0;
deeea8ed 3082
bfead3b2 3083create_eq_error:
107dfcba 3084 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
bfead3b2
JK		 3085 eq = &phwi_context->be_eq[i].q;
3086 mem = &eq->dma_mem;
3087 if (mem->va)
3088 pci_free_consistent(phba->pcidev, num_eq_pages
3089 * PAGE_SIZE,
3090 mem->va, mem->dma);
3091 }
3092 return ret;
6733b39a
JK		 3093}
3094
bfead3b2 3095static int beiscsi_create_cqs(struct beiscsi_hba *phba,
6733b39a
JK		 3096 struct hwi_context_memory *phwi_context)
3097{
bfead3b2 3098 unsigned int i, num_cq_pages;
6733b39a
JK		 3099 struct be_queue_info *cq, *eq;
3100 struct be_dma_mem *mem;
bfead3b2 3101 struct be_eq_obj *pbe_eq;
6733b39a 3102 void *cq_vaddress;
deeea8ed 3103 int ret = -ENOMEM;
bfead3b2 3104 dma_addr_t paddr;
6733b39a 3105
bfead3b2
JK		 3106 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
3107 sizeof(struct sol_cqe));
6733b39a 3108
bfead3b2
JK		 3109 for (i = 0; i < phba->num_cpus; i++) {
3110 cq = &phwi_context->be_cq[i];
3111 eq = &phwi_context->be_eq[i].q;
3112 pbe_eq = &phwi_context->be_eq[i];
3113 pbe_eq->cq = cq;
3114 pbe_eq->phba = phba;
3115 mem = &cq->dma_mem;
3116 cq_vaddress = pci_alloc_consistent(phba->pcidev,
deeea8ed
CJ		 3117 num_cq_pages * PAGE_SIZE,
3118 &paddr);
29b33252
PB		 3119 if (!cq_vaddress) {
3120 ret = -ENOMEM;
bfead3b2 3121 goto create_cq_error;
29b33252 3122 }
deeea8ed 3123
7da50879 3124 ret = be_fill_queue(cq, phba->params.num_cq_entries,
bfead3b2
JK		 3125 sizeof(struct sol_cqe), cq_vaddress);
3126 if (ret) {
99bc5d55
JSJ		 3127 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3128 "BM_%d : be_fill_queue Failed "
3129 "for ISCSI CQ\n");
bfead3b2
JK		 3130 goto create_cq_error;
3131 }
3132
3133 mem->dma = paddr;
3134 ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
3135 false, 0);
3136 if (ret) {
99bc5d55
JSJ		 3137 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3138 "BM_%d : beiscsi_cmd_eq_create"
3139 "Failed for ISCSI CQ\n");
bfead3b2
JK		 3140 goto create_cq_error;
3141 }
99bc5d55
JSJ		 3142 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3143 "BM_%d : iscsi cq_id is %d for eq_id %d\n"
3144 "iSCSI CQ CREATED\n", cq->id, eq->id);
6733b39a 3145 }
6733b39a 3146 return 0;
bfead3b2
JK		 3147
3148create_cq_error:
3149 for (i = 0; i < phba->num_cpus; i++) {
3150 cq = &phwi_context->be_cq[i];
3151 mem = &cq->dma_mem;
3152 if (mem->va)
3153 pci_free_consistent(phba->pcidev, num_cq_pages
3154 * PAGE_SIZE,
3155 mem->va, mem->dma);
3156 }
3157 return ret;
6733b39a
JK		 3158}
3159
3160static int
3161beiscsi_create_def_hdr(struct beiscsi_hba *phba,
3162 struct hwi_context_memory *phwi_context,
3163 struct hwi_controller *phwi_ctrlr,
8a86e833 3164 unsigned int def_pdu_ring_sz, uint8_t ulp_num)
6733b39a
JK		 3165{
3166 unsigned int idx;
3167 int ret;
3168 struct be_queue_info *dq, *cq;
3169 struct be_dma_mem *mem;
3170 struct be_mem_descriptor *mem_descr;
3171 void *dq_vaddress;
3172
3173 idx = 0;
8a86e833 3174 dq = &phwi_context->be_def_hdrq[ulp_num];
bfead3b2 3175 cq = &phwi_context->be_cq[0];
6733b39a
JK		 3176 mem = &dq->dma_mem;
3177 mem_descr = phba->init_mem;
8a86e833
JK		 3178 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
3179 (ulp_num * MEM_DESCR_OFFSET);
6733b39a
JK		 3180 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
3181 ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
3182 sizeof(struct phys_addr),
3183 sizeof(struct phys_addr), dq_vaddress);
3184 if (ret) {
99bc5d55 3185 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3186 "BM_%d : be_fill_queue Failed for DEF PDU HDR on ULP : %d\n",
3187 ulp_num);
3188
6733b39a
JK		 3189 return ret;
3190 }
457ff3b7
JK		 3191 mem->dma = (unsigned long)mem_descr->mem_array[idx].
3192 bus_address.u.a64.address;
6733b39a
JK		 3193 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
3194 def_pdu_ring_sz,
8a86e833
JK		 3195 phba->params.defpdu_hdr_sz,
3196 BEISCSI_DEFQ_HDR, ulp_num);
6733b39a 3197 if (ret) {
99bc5d55 3198 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3199 "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR on ULP : %d\n",
3200 ulp_num);
3201
6733b39a
JK		 3202 return ret;
3203 }
99bc5d55 3204
8a86e833
JK		 3205 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3206 "BM_%d : iscsi hdr def pdu id for ULP : %d is %d\n",
3207 ulp_num,
3208 phwi_context->be_def_hdrq[ulp_num].id);
6733b39a
JK		 3209 return 0;
3210}
3211
3212static int
3213beiscsi_create_def_data(struct beiscsi_hba *phba,
3214 struct hwi_context_memory *phwi_context,
3215 struct hwi_controller *phwi_ctrlr,
8a86e833 3216 unsigned int def_pdu_ring_sz, uint8_t ulp_num)
6733b39a
JK		 3217{
3218 unsigned int idx;
3219 int ret;
3220 struct be_queue_info *dataq, *cq;
3221 struct be_dma_mem *mem;
3222 struct be_mem_descriptor *mem_descr;
3223 void *dq_vaddress;
3224
3225 idx = 0;
8a86e833 3226 dataq = &phwi_context->be_def_dataq[ulp_num];
bfead3b2 3227 cq = &phwi_context->be_cq[0];
6733b39a
JK		 3228 mem = &dataq->dma_mem;
3229 mem_descr = phba->init_mem;
8a86e833
JK		 3230 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
3231 (ulp_num * MEM_DESCR_OFFSET);
6733b39a
JK		 3232 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
3233 ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
3234 sizeof(struct phys_addr),
3235 sizeof(struct phys_addr), dq_vaddress);
3236 if (ret) {
99bc5d55 3237 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3238 "BM_%d : be_fill_queue Failed for DEF PDU "
3239 "DATA on ULP : %d\n",
3240 ulp_num);
3241
6733b39a
JK		 3242 return ret;
3243 }
457ff3b7
JK		 3244 mem->dma = (unsigned long)mem_descr->mem_array[idx].
3245 bus_address.u.a64.address;
6733b39a
JK		 3246 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
3247 def_pdu_ring_sz,
8a86e833
JK		 3248 phba->params.defpdu_data_sz,
3249 BEISCSI_DEFQ_DATA, ulp_num);
6733b39a 3250 if (ret) {
99bc5d55
JSJ		 3251 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3252 "BM_%d be_cmd_create_default_pdu_queue"
8a86e833
JK		 3253 " Failed for DEF PDU DATA on ULP : %d\n",
3254 ulp_num);
6733b39a
JK		 3255 return ret;
3256 }
8a86e833 3257
99bc5d55 3258 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
8a86e833
JK		 3259 "BM_%d : iscsi def data id on ULP : %d is %d\n",
3260 ulp_num,
3261 phwi_context->be_def_dataq[ulp_num].id);
99bc5d55 3262
99bc5d55 3263 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
8a86e833
JK		 3264 "BM_%d : DEFAULT PDU DATA RING CREATED"
3265 "on ULP : %d\n", ulp_num);
6733b39a
JK		 3266 return 0;
3267}
3268
15a90fe0
JK		 3269
3270static int
3271beiscsi_post_template_hdr(struct beiscsi_hba *phba)
3272{
3273 struct be_mem_descriptor *mem_descr;
3274 struct mem_array *pm_arr;
3275 struct be_dma_mem sgl;
a129d92f 3276 int status, ulp_num;
15a90fe0 3277
a129d92f
JK		 3278 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3279 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3280 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3281 mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 +
3282 (ulp_num * MEM_DESCR_OFFSET);
3283 pm_arr = mem_descr->mem_array;
15a90fe0 3284
a129d92f
JK		 3285 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
3286 status = be_cmd_iscsi_post_template_hdr(
3287 &phba->ctrl, &sgl);
15a90fe0 3288
a129d92f
JK		 3289 if (status != 0) {
3290 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3291 "BM_%d : Post Template HDR Failed for"
3292 "ULP_%d\n", ulp_num);
3293 return status;
3294 }
3295
3296 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3297 "BM_%d : Template HDR Pages Posted for"
3298 "ULP_%d\n", ulp_num);
15a90fe0
JK		 3299 }
3300 }
15a90fe0
JK		 3301 return 0;
3302}
3303
6733b39a
JK		 3304static int
3305beiscsi_post_pages(struct beiscsi_hba *phba)
3306{
3307 struct be_mem_descriptor *mem_descr;
3308 struct mem_array *pm_arr;
3309 unsigned int page_offset, i;
3310 struct be_dma_mem sgl;
843ae752 3311 int status, ulp_num = 0;
6733b39a
JK		 3312
3313 mem_descr = phba->init_mem;
3314 mem_descr += HWI_MEM_SGE;
3315 pm_arr = mem_descr->mem_array;
3316
90622db3
JK		 3317 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3318 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
3319 break;
3320
6733b39a 3321 page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
843ae752 3322 phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE;
6733b39a
JK		 3323 for (i = 0; i < mem_descr->num_elements; i++) {
3324 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
3325 status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
3326 page_offset,
3327 (pm_arr->size / PAGE_SIZE));
3328 page_offset += pm_arr->size / PAGE_SIZE;
3329 if (status != 0) {
99bc5d55
JSJ		 3330 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3331 "BM_%d : post sgl failed.\n");
6733b39a
JK		 3332 return status;
3333 }
3334 pm_arr++;
3335 }
99bc5d55
JSJ		 3336 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3337 "BM_%d : POSTED PAGES\n");
6733b39a
JK		 3338 return 0;
3339}
3340
bfead3b2
JK		 3341static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
3342{
3343 struct be_dma_mem *mem = &q->dma_mem;
c8b25598 3344 if (mem->va) {
bfead3b2
JK		 3345 pci_free_consistent(phba->pcidev, mem->size,
3346 mem->va, mem->dma);
c8b25598
JK		 3347 mem->va = NULL;
3348 }
bfead3b2
JK		 3349}
3350
3351static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
3352 u16 len, u16 entry_size)
3353{
3354 struct be_dma_mem *mem = &q->dma_mem;
3355
3356 memset(q, 0, sizeof(*q));
3357 q->len = len;
3358 q->entry_size = entry_size;
3359 mem->size = len * entry_size;
7c845eb5 3360 mem->va = pci_zalloc_consistent(phba->pcidev, mem->size, &mem->dma);
bfead3b2 3361 if (!mem->va)
d3ad2bb3 3362 return -ENOMEM;
bfead3b2
JK		 3363 return 0;
3364}
3365
6733b39a
JK		 3366static int
3367beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
3368 struct hwi_context_memory *phwi_context,
3369 struct hwi_controller *phwi_ctrlr)
3370{
fa1261c4 3371 unsigned int num_wrb_rings;
6733b39a 3372 u64 pa_addr_lo;
4eea99d5 3373 unsigned int idx, num, i, ulp_num;
6733b39a
JK		 3374 struct mem_array *pwrb_arr;
3375 void *wrb_vaddr;
3376 struct be_dma_mem sgl;
3377 struct be_mem_descriptor *mem_descr;
a7909b39 3378 struct hwi_wrb_context *pwrb_context;
6733b39a 3379 int status;
4eea99d5
JK		 3380 uint8_t ulp_count = 0, ulp_base_num = 0;
3381 uint16_t cid_count_ulp[BEISCSI_ULP_COUNT] = { 0 };
6733b39a
JK		 3382
3383 idx = 0;
3384 mem_descr = phba->init_mem;
3385 mem_descr += HWI_MEM_WRB;
3386 pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
3387 GFP_KERNEL);
3388 if (!pwrb_arr) {
99bc5d55
JSJ		 3389 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3390 "BM_%d : Memory alloc failed in create wrb ring.\n");
6733b39a
JK		 3391 return -ENOMEM;
3392 }
3393 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
3394 pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
3395 num_wrb_rings = mem_descr->mem_array[idx].size /
3396 (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
3397
3398 for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
3399 if (num_wrb_rings) {
3400 pwrb_arr[num].virtual_address = wrb_vaddr;
3401 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
3402 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
3403 sizeof(struct iscsi_wrb);
3404 wrb_vaddr += pwrb_arr[num].size;
3405 pa_addr_lo += pwrb_arr[num].size;
3406 num_wrb_rings--;
3407 } else {
3408 idx++;
3409 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
3410 pa_addr_lo = mem_descr->mem_array[idx].\
3411 bus_address.u.a64.address;
3412 num_wrb_rings = mem_descr->mem_array[idx].size /
3413 (phba->params.wrbs_per_cxn *
3414 sizeof(struct iscsi_wrb));
3415 pwrb_arr[num].virtual_address = wrb_vaddr;
3416 pwrb_arr[num].bus_address.u.a64.address\
3417 = pa_addr_lo;
3418 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
3419 sizeof(struct iscsi_wrb);
3420 wrb_vaddr += pwrb_arr[num].size;
3421 pa_addr_lo += pwrb_arr[num].size;
3422 num_wrb_rings--;
3423 }
3424 }
4eea99d5
JK		 3425
3426 /* Get the ULP Count */
3427 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3428 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3429 ulp_count++;
3430 ulp_base_num = ulp_num;
3431 cid_count_ulp[ulp_num] =
3432 BEISCSI_GET_CID_COUNT(phba, ulp_num);
3433 }
3434
6733b39a 3435 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
4eea99d5
JK		 3436 if (ulp_count > 1) {
3437 ulp_base_num = (ulp_base_num + 1) % BEISCSI_ULP_COUNT;
3438
3439 if (!cid_count_ulp[ulp_base_num])
3440 ulp_base_num = (ulp_base_num + 1) %
3441 BEISCSI_ULP_COUNT;
3442
3443 cid_count_ulp[ulp_base_num]--;
3444 }
3445
3446
6733b39a
JK		 3447 hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
3448 status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
4eea99d5
JK		 3449 &phwi_context->be_wrbq[i],
3450 &phwi_ctrlr->wrb_context[i],
3451 ulp_base_num);
6733b39a 3452 if (status != 0) {
99bc5d55
JSJ		 3453 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3454 "BM_%d : wrbq create failed.");
1462b8ff 3455 kfree(pwrb_arr);
6733b39a
JK		 3456 return status;
3457 }
a7909b39 3458 pwrb_context = &phwi_ctrlr->wrb_context[i];
a7909b39 3459 BE_SET_CID_TO_CRI(i, pwrb_context->cid);
6733b39a
JK		 3460 }
3461 kfree(pwrb_arr);
3462 return 0;
3463}
3464
3465static void free_wrb_handles(struct beiscsi_hba *phba)
3466{
3467 unsigned int index;
3468 struct hwi_controller *phwi_ctrlr;
3469 struct hwi_wrb_context *pwrb_context;
3470
3471 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 3472 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a
JK		 3473 pwrb_context = &phwi_ctrlr->wrb_context[index];
3474 kfree(pwrb_context->pwrb_handle_base);
3475 kfree(pwrb_context->pwrb_handle_basestd);
3476 }
3477}
3478
bfead3b2
JK		 3479static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
3480{
bfead3b2 3481 struct be_ctrl_info *ctrl = &phba->ctrl;
d1d5ca88
JB		 3482 struct be_dma_mem *ptag_mem;
3483 struct be_queue_info *q;
3484 int i, tag;
bfead3b2
JK		 3485
3486 q = &phba->ctrl.mcc_obj.q;
d1d5ca88
JB		 3487 for (i = 0; i < MAX_MCC_CMD; i++) {
3488 tag = i + 1;
3489 if (!test_bit(MCC_TAG_STATE_RUNNING,
3490 &ctrl->ptag_state[tag].tag_state))
3491 continue;
3492
3493 if (test_bit(MCC_TAG_STATE_TIMEOUT,
3494 &ctrl->ptag_state[tag].tag_state)) {
3495 ptag_mem = &ctrl->ptag_state[tag].tag_mem_state;
3496 if (ptag_mem->size) {
3497 pci_free_consistent(ctrl->pdev,
3498 ptag_mem->size,
3499 ptag_mem->va,
3500 ptag_mem->dma);
3501 ptag_mem->size = 0;
3502 }
3503 continue;
3504 }
3505 /**
3506 * If MCC is still active and waiting then wake up the process.
3507 * We are here only because port is going offline. The process
3508 * sees that (BEISCSI_HBA_ONLINE is cleared) and EIO error is
3509 * returned for the operation and allocated memory cleaned up.
3510 */
3511 if (waitqueue_active(&ctrl->mcc_wait[tag])) {
3512 ctrl->mcc_tag_status[tag] = MCC_STATUS_FAILED;
3513 ctrl->mcc_tag_status[tag] |= CQE_VALID_MASK;
3514 wake_up_interruptible(&ctrl->mcc_wait[tag]);
3515 /*
3516 * Control tag info gets reinitialized in enable
3517 * so wait for the process to clear running state.
3518 */
3519 while (test_bit(MCC_TAG_STATE_RUNNING,
3520 &ctrl->ptag_state[tag].tag_state))
3521 schedule_timeout_uninterruptible(HZ);
3522 }
3523 /**
3524 * For MCC with tag_states MCC_TAG_STATE_ASYNC and
3525 * MCC_TAG_STATE_IGNORE nothing needs to done.
3526 */
3527 }
4e2bdf7a 3528 if (q->created) {
bfead3b2 3529 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
4e2bdf7a
JSJ		 3530 be_queue_free(phba, q);
3531 }
bfead3b2
JK		 3532
3533 q = &phba->ctrl.mcc_obj.cq;
4e2bdf7a 3534 if (q->created) {
bfead3b2 3535 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
4e2bdf7a
JSJ		 3536 be_queue_free(phba, q);
3537 }
bfead3b2
JK		 3538}
3539
bfead3b2
JK		 3540static int be_mcc_queues_create(struct beiscsi_hba *phba,
3541 struct hwi_context_memory *phwi_context)
3542{
3543 struct be_queue_info *q, *cq;
3544 struct be_ctrl_info *ctrl = &phba->ctrl;
3545
3546 /* Alloc MCC compl queue */
3547 cq = &phba->ctrl.mcc_obj.cq;
3548 if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
3549 sizeof(struct be_mcc_compl)))
3550 goto err;
3551 /* Ask BE to create MCC compl queue; */
3552 if (phba->msix_enabled) {
3553 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
3554 [phba->num_cpus].q, false, true, 0))
3555 goto mcc_cq_free;
3556 } else {
3557 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
3558 false, true, 0))
3559 goto mcc_cq_free;
3560 }
3561
3562 /* Alloc MCC queue */
3563 q = &phba->ctrl.mcc_obj.q;
3564 if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
3565 goto mcc_cq_destroy;
3566
3567 /* Ask BE to create MCC queue */
35e66019 3568 if (beiscsi_cmd_mccq_create(phba, q, cq))
bfead3b2
JK		 3569 goto mcc_q_free;
3570
3571 return 0;
3572
3573mcc_q_free:
3574 be_queue_free(phba, q);
3575mcc_cq_destroy:
3576 beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
3577mcc_cq_free:
3578 be_queue_free(phba, cq);
3579err:
d3ad2bb3 3580 return -ENOMEM;
bfead3b2
JK		 3581}
3582
107dfcba
JSJ		 3583/**
3584 * find_num_cpus()- Get the CPU online count
3585 * @phba: ptr to priv structure
3586 *
3587 * CPU count is used for creating EQ.
3588 **/
3589static void find_num_cpus(struct beiscsi_hba *phba)
bfead3b2
JK		 3590{
3591 int num_cpus = 0;
3592
3593 num_cpus = num_online_cpus();
bfead3b2 3594
22abeef0
JSJ		 3595 switch (phba->generation) {
3596 case BE_GEN2:
3597 case BE_GEN3:
3598 phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
3599 BEISCSI_MAX_NUM_CPUS : num_cpus;
3600 break;
3601 case BE_GEN4:
68c26a3a
JK		 3602 /*
3603 * If eqid_count == 1 fall back to
3604 * INTX mechanism
3605 **/
3606 if (phba->fw_config.eqid_count == 1) {
3607 enable_msix = 0;
3608 phba->num_cpus = 1;
3609 return;
3610 }
3611
3612 phba->num_cpus =
3613 (num_cpus > (phba->fw_config.eqid_count - 1)) ?
3614 (phba->fw_config.eqid_count - 1) : num_cpus;
22abeef0
JSJ		 3615 break;
3616 default:
3617 phba->num_cpus = 1;
3618 }
6733b39a
JK		 3619}
3620
d1d5ca88
JB		 3621static void hwi_purge_eq(struct beiscsi_hba *phba)
3622{
3623 struct hwi_controller *phwi_ctrlr;
3624 struct hwi_context_memory *phwi_context;
3625 struct be_queue_info *eq;
3626 struct be_eq_entry *eqe = NULL;
3627 int i, eq_msix;
3628 unsigned int num_processed;
3629
3630 if (beiscsi_hba_in_error(phba))
3631 return;
3632
3633 phwi_ctrlr = phba->phwi_ctrlr;
3634 phwi_context = phwi_ctrlr->phwi_ctxt;
3635 if (phba->msix_enabled)
3636 eq_msix = 1;
3637 else
3638 eq_msix = 0;
3639
3640 for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
3641 eq = &phwi_context->be_eq[i].q;
3642 eqe = queue_tail_node(eq);
3643 num_processed = 0;
3644 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
3645 & EQE_VALID_MASK) {
3646 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
3647 queue_tail_inc(eq);
3648 eqe = queue_tail_node(eq);
3649 num_processed++;
3650 }
3651
3652 if (num_processed)
3653 hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
3654 }
3655}
3656
3657static void hwi_cleanup_port(struct beiscsi_hba *phba)
3658{
3659 struct be_queue_info *q;
3660 struct be_ctrl_info *ctrl = &phba->ctrl;
3661 struct hwi_controller *phwi_ctrlr;
3662 struct hwi_context_memory *phwi_context;
d1d5ca88
JB		 3663 int i, eq_for_mcc, ulp_num;
3664
3665 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3666 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
3667 beiscsi_cmd_iscsi_cleanup(phba, ulp_num);
3668
3669 /**
3670 * Purge all EQ entries that may have been left out. This is to
3671 * workaround a problem we've seen occasionally where driver gets an
3672 * interrupt with EQ entry bit set after stopping the controller.
3673 */
3674 hwi_purge_eq(phba);
3675
3676 phwi_ctrlr = phba->phwi_ctrlr;
3677 phwi_context = phwi_ctrlr->phwi_ctxt;
3678
3679 be_cmd_iscsi_remove_template_hdr(ctrl);
3680
3681 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3682 q = &phwi_context->be_wrbq[i];
3683 if (q->created)
3684 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
3685 }
3686 kfree(phwi_context->be_wrbq);
3687 free_wrb_handles(phba);
3688
3689 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3690 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3691
3692 q = &phwi_context->be_def_hdrq[ulp_num];
3693 if (q->created)
3694 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3695
3696 q = &phwi_context->be_def_dataq[ulp_num];
3697 if (q->created)
3698 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
d1d5ca88
JB		 3699 }
3700 }
3701
3702 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
3703
3704 for (i = 0; i < (phba->num_cpus); i++) {
3705 q = &phwi_context->be_cq[i];
3706 if (q->created) {
3707 be_queue_free(phba, q);
3708 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
3709 }
3710 }
3711
3712 be_mcc_queues_destroy(phba);
3713 if (phba->msix_enabled)
3714 eq_for_mcc = 1;
3715 else
3716 eq_for_mcc = 0;
3717 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
3718 q = &phwi_context->be_eq[i].q;
3719 if (q->created) {
3720 be_queue_free(phba, q);
3721 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
3722 }
3723 }
4ee1ec42
JB		 3724 /* this ensures complete FW cleanup */
3725 beiscsi_cmd_function_reset(phba);
d1d5ca88
JB		 3726 /* last communication, indicate driver is unloading */
3727 beiscsi_cmd_special_wrb(&phba->ctrl, 0);
3728}
4ee1ec42 3729
6733b39a
JK		 3730static int hwi_init_port(struct beiscsi_hba *phba)
3731{
3732 struct hwi_controller *phwi_ctrlr;
3733 struct hwi_context_memory *phwi_context;
3734 unsigned int def_pdu_ring_sz;
3735 struct be_ctrl_info *ctrl = &phba->ctrl;
8a86e833 3736 int status, ulp_num;
6733b39a 3737
6733b39a 3738 phwi_ctrlr = phba->phwi_ctrlr;
6733b39a 3739 phwi_context = phwi_ctrlr->phwi_ctxt;
73af08e1 3740 phwi_context->max_eqd = 128;
bfead3b2 3741 phwi_context->min_eqd = 0;
1b7a7ddc 3742 phwi_context->cur_eqd = 32;
4d2ee1e6 3743 /* set port optic state to unknown */
53aefe25 3744 phba->optic_state = 0xff;
bfead3b2
JK		 3745
3746 status = beiscsi_create_eqs(phba, phwi_context);
6733b39a 3747 if (status != 0) {
99bc5d55
JSJ		 3748 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3749 "BM_%d : EQ not created\n");
6733b39a
JK		 3750 goto error;
3751 }
3752
bfead3b2
JK		 3753 status = be_mcc_queues_create(phba, phwi_context);
3754 if (status != 0)
3755 goto error;
3756
480195c2 3757 status = beiscsi_check_supported_fw(ctrl, phba);
6733b39a 3758 if (status != 0) {
99bc5d55
JSJ		 3759 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3760 "BM_%d : Unsupported fw version\n");
6733b39a
JK		 3761 goto error;
3762 }
3763
bfead3b2 3764 status = beiscsi_create_cqs(phba, phwi_context);
6733b39a 3765 if (status != 0) {
99bc5d55
JSJ		 3766 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3767 "BM_%d : CQ not created\n");
6733b39a
JK		 3768 goto error;
3769 }
3770
8a86e833
JK		 3771 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3772 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
8a86e833
JK		 3773 def_pdu_ring_sz =
3774 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
3775 sizeof(struct phys_addr);
3776
3777 status = beiscsi_create_def_hdr(phba, phwi_context,
3778 phwi_ctrlr,
3779 def_pdu_ring_sz,
3780 ulp_num);
3781 if (status != 0) {
3782 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3783 "BM_%d : Default Header not created for ULP : %d\n",
3784 ulp_num);
3785 goto error;
3786 }
3787
3788 status = beiscsi_create_def_data(phba, phwi_context,
3789 phwi_ctrlr,
3790 def_pdu_ring_sz,
3791 ulp_num);
3792 if (status != 0) {
3793 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3794 "BM_%d : Default Data not created for ULP : %d\n",
3795 ulp_num);
3796 goto error;
3797 }
f79929de
JB		 3798 /**
3799 * Now that the default PDU rings have been created,
3800 * let EP know about it.
f79929de 3801 */
938f372c
JB		 3802 beiscsi_hdq_post_handles(phba, BEISCSI_DEFQ_HDR,
3803 ulp_num);
3804 beiscsi_hdq_post_handles(phba, BEISCSI_DEFQ_DATA,
3805 ulp_num);
8a86e833 3806 }
6733b39a
JK		 3807 }
3808
3809 status = beiscsi_post_pages(phba);
3810 if (status != 0) {
99bc5d55
JSJ		 3811 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3812 "BM_%d : Post SGL Pages Failed\n");
6733b39a
JK		 3813 goto error;
3814 }
3815
15a90fe0
JK		 3816 status = beiscsi_post_template_hdr(phba);
3817 if (status != 0) {
3818 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3819 "BM_%d : Template HDR Posting for CXN Failed\n");
3820 }
3821
6733b39a
JK		 3822 status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
3823 if (status != 0) {
99bc5d55
JSJ		 3824 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3825 "BM_%d : WRB Rings not created\n");
6733b39a
JK		 3826 goto error;
3827 }
3828
8a86e833
JK		 3829 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3830 uint16_t async_arr_idx = 0;
3831
3832 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3833 uint16_t cri = 0;
938f372c 3834 struct hd_async_context *pasync_ctx;
8a86e833
JK		 3835
3836 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(
3837 phwi_ctrlr, ulp_num);
3838 for (cri = 0; cri <
3839 phba->params.cxns_per_ctrl; cri++) {
3840 if (ulp_num == BEISCSI_GET_ULP_FROM_CRI
3841 (phwi_ctrlr, cri))
3842 pasync_ctx->cid_to_async_cri_map[
3843 phwi_ctrlr->wrb_context[cri].cid] =
3844 async_arr_idx++;
3845 }
3846 }
3847 }
3848
99bc5d55
JSJ		 3849 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3850 "BM_%d : hwi_init_port success\n");
6733b39a
JK		 3851 return 0;
3852
3853error:
99bc5d55
JSJ		 3854 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3855 "BM_%d : hwi_init_port failed");
4d2ee1e6 3856 hwi_cleanup_port(phba);
a49e06d5 3857 return status;
6733b39a
JK		 3858}
3859
6733b39a
JK		 3860static int hwi_init_controller(struct beiscsi_hba *phba)
3861{
3862 struct hwi_controller *phwi_ctrlr;
3863
3864 phwi_ctrlr = phba->phwi_ctrlr;
3865 if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
3866 phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
3867 init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
99bc5d55
JSJ		 3868 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3869 "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
3870 phwi_ctrlr->phwi_ctxt);
6733b39a 3871 } else {
99bc5d55
JSJ		 3872 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3873 "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
3874 "than one element.Failing to load\n");
6733b39a
JK		 3875 return -ENOMEM;
3876 }
3877
3878 iscsi_init_global_templates(phba);
3ec78271
JK		 3879 if (beiscsi_init_wrb_handle(phba))
3880 return -ENOMEM;
3881
a7909b39
JK		 3882 if (hwi_init_async_pdu_ctx(phba)) {
3883 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3884 "BM_%d : hwi_init_async_pdu_ctx failed\n");
3885 return -ENOMEM;
3886 }
3887
6733b39a 3888 if (hwi_init_port(phba) != 0) {
99bc5d55
JSJ		 3889 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3890 "BM_%d : hwi_init_controller failed\n");
3891
6733b39a
JK		 3892 return -ENOMEM;
3893 }
3894 return 0;
3895}
3896
3897static void beiscsi_free_mem(struct beiscsi_hba *phba)
3898{
3899 struct be_mem_descriptor *mem_descr;
3900 int i, j;
3901
3902 mem_descr = phba->init_mem;
3903 i = 0;
3904 j = 0;
3905 for (i = 0; i < SE_MEM_MAX; i++) {
3906 for (j = mem_descr->num_elements; j > 0; j--) {
3907 pci_free_consistent(phba->pcidev,
3908 mem_descr->mem_array[j - 1].size,
3909 mem_descr->mem_array[j - 1].virtual_address,
457ff3b7
JK		 3910 (unsigned long)mem_descr->mem_array[j - 1].
3911 bus_address.u.a64.address);
6733b39a 3912 }
8a86e833 3913
6733b39a
JK		 3914 kfree(mem_descr->mem_array);
3915 mem_descr++;
3916 }
3917 kfree(phba->init_mem);
a7909b39 3918 kfree(phba->phwi_ctrlr->wrb_context);
6733b39a
JK		 3919 kfree(phba->phwi_ctrlr);
3920}
3921
6733b39a
JK		 3922static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
3923{
3924 struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
3925 struct sgl_handle *psgl_handle;
3926 struct iscsi_sge *pfrag;
90622db3
JK		 3927 unsigned int arr_index, i, idx;
3928 unsigned int ulp_icd_start, ulp_num = 0;
6733b39a
JK		 3929
3930 phba->io_sgl_hndl_avbl = 0;
3931 phba->eh_sgl_hndl_avbl = 0;
bfead3b2 3932
6733b39a
JK		 3933 mem_descr_sglh = phba->init_mem;
3934 mem_descr_sglh += HWI_MEM_SGLH;
3935 if (1 == mem_descr_sglh->num_elements) {
3936 phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
3937 phba->params.ios_per_ctrl,
3938 GFP_KERNEL);
3939 if (!phba->io_sgl_hndl_base) {
99bc5d55
JSJ		 3940 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3941 "BM_%d : Mem Alloc Failed. Failing to load\n");
6733b39a
JK		 3942 return -ENOMEM;
3943 }
3944 phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
3945 (phba->params.icds_per_ctrl -
3946 phba->params.ios_per_ctrl),
3947 GFP_KERNEL);
3948 if (!phba->eh_sgl_hndl_base) {
3949 kfree(phba->io_sgl_hndl_base);
99bc5d55
JSJ		 3950 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3951 "BM_%d : Mem Alloc Failed. Failing to load\n");
6733b39a
JK		 3952 return -ENOMEM;
3953 }
3954 } else {
99bc5d55
JSJ		 3955 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3956 "BM_%d : HWI_MEM_SGLH is more than one element."
3957 "Failing to load\n");
6733b39a
JK		 3958 return -ENOMEM;
3959 }
3960
3961 arr_index = 0;
3962 idx = 0;
3963 while (idx < mem_descr_sglh->num_elements) {
3964 psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
3965
3966 for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
3967 sizeof(struct sgl_handle)); i++) {
3968 if (arr_index < phba->params.ios_per_ctrl) {
3969 phba->io_sgl_hndl_base[arr_index] = psgl_handle;
3970 phba->io_sgl_hndl_avbl++;
3971 arr_index++;
3972 } else {
3973 phba->eh_sgl_hndl_base[arr_index -
3974 phba->params.ios_per_ctrl] =
3975 psgl_handle;
3976 arr_index++;
3977 phba->eh_sgl_hndl_avbl++;
3978 }
3979 psgl_handle++;
3980 }
3981 idx++;
3982 }
99bc5d55
JSJ		 3983 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3984 "BM_%d : phba->io_sgl_hndl_avbl=%d"
3985 "phba->eh_sgl_hndl_avbl=%d\n",
3986 phba->io_sgl_hndl_avbl,
3987 phba->eh_sgl_hndl_avbl);
3988
6733b39a
JK		 3989 mem_descr_sg = phba->init_mem;
3990 mem_descr_sg += HWI_MEM_SGE;
99bc5d55
JSJ		 3991 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3992 "\n BM_%d : mem_descr_sg->num_elements=%d\n",
3993 mem_descr_sg->num_elements);
3994
90622db3
JK		 3995 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3996 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
3997 break;
3998
3999 ulp_icd_start = phba->fw_config.iscsi_icd_start[ulp_num];
4000
6733b39a
JK		 4001 arr_index = 0;
4002 idx = 0;
4003 while (idx < mem_descr_sg->num_elements) {
4004 pfrag = mem_descr_sg->mem_array[idx].virtual_address;
4005
4006 for (i = 0;
4007 i < (mem_descr_sg->mem_array[idx].size) /
4008 (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
4009 i++) {
4010 if (arr_index < phba->params.ios_per_ctrl)
4011 psgl_handle = phba->io_sgl_hndl_base[arr_index];
4012 else
4013 psgl_handle = phba->eh_sgl_hndl_base[arr_index -
4014 phba->params.ios_per_ctrl];
4015 psgl_handle->pfrag = pfrag;
4016 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
4017 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
4018 pfrag += phba->params.num_sge_per_io;
90622db3 4019 psgl_handle->sgl_index = ulp_icd_start + arr_index++;
6733b39a
JK		 4020 }
4021 idx++;
4022 }
4023 phba->io_sgl_free_index = 0;
4024 phba->io_sgl_alloc_index = 0;
4025 phba->eh_sgl_free_index = 0;
4026 phba->eh_sgl_alloc_index = 0;
4027 return 0;
4028}
4029
4030static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
4031{
0a3db7c0
JK		 4032 int ret;
4033 uint16_t i, ulp_num;
4034 struct ulp_cid_info *ptr_cid_info = NULL;
6733b39a 4035
0a3db7c0
JK		 4036 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4037 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4038 ptr_cid_info = kzalloc(sizeof(struct ulp_cid_info),
4039 GFP_KERNEL);
4040
4041 if (!ptr_cid_info) {
4042 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4043 "BM_%d : Failed to allocate memory"
4044 "for ULP_CID_INFO for ULP : %d\n",
4045 ulp_num);
4046 ret = -ENOMEM;
4047 goto free_memory;
4048
4049 }
4050
4051 /* Allocate memory for CID array */
413f3656
JB		 4052 ptr_cid_info->cid_array =
4053 kcalloc(BEISCSI_GET_CID_COUNT(phba, ulp_num),
4054 sizeof(*ptr_cid_info->cid_array),
4055 GFP_KERNEL);
0a3db7c0
JK		 4056 if (!ptr_cid_info->cid_array) {
4057 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4058 "BM_%d : Failed to allocate memory"
4059 "for CID_ARRAY for ULP : %d\n",
4060 ulp_num);
4061 kfree(ptr_cid_info);
4062 ptr_cid_info = NULL;
4063 ret = -ENOMEM;
4064
4065 goto free_memory;
4066 }
4067 ptr_cid_info->avlbl_cids = BEISCSI_GET_CID_COUNT(
4068 phba, ulp_num);
4069
4070 /* Save the cid_info_array ptr */
4071 phba->cid_array_info[ulp_num] = ptr_cid_info;
4072 }
6733b39a 4073 }
c2462288 4074 phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
a7909b39 4075 phba->params.cxns_per_ctrl, GFP_KERNEL);
6733b39a 4076 if (!phba->ep_array) {
99bc5d55
JSJ		 4077 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4078 "BM_%d : Failed to allocate memory in "
4079 "hba_setup_cid_tbls\n");
0a3db7c0
JK		 4080 ret = -ENOMEM;
4081
4082 goto free_memory;
6733b39a 4083 }
a7909b39
JK		 4084
4085 phba->conn_table = kzalloc(sizeof(struct beiscsi_conn *) *
4086 phba->params.cxns_per_ctrl, GFP_KERNEL);
4087 if (!phba->conn_table) {
4088 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4089 "BM_%d : Failed to allocate memory in"
4090 "hba_setup_cid_tbls\n");
4091
a7909b39 4092 kfree(phba->ep_array);
a7909b39 4093 phba->ep_array = NULL;
0a3db7c0 4094 ret = -ENOMEM;
5f2d25ef
TH		 4095
4096 goto free_memory;
6733b39a 4097 }
a7909b39 4098
0a3db7c0
JK		 4099 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
4100 ulp_num = phba->phwi_ctrlr->wrb_context[i].ulp_num;
4101
4102 ptr_cid_info = phba->cid_array_info[ulp_num];
4103 ptr_cid_info->cid_array[ptr_cid_info->cid_alloc++] =
4104 phba->phwi_ctrlr->wrb_context[i].cid;
4105
4106 }
4107
4108 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4109 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4110 ptr_cid_info = phba->cid_array_info[ulp_num];
a7909b39 4111
0a3db7c0
JK		 4112 ptr_cid_info->cid_alloc = 0;
4113 ptr_cid_info->cid_free = 0;
4114 }
4115 }
6733b39a 4116 return 0;
0a3db7c0
JK		 4117
4118free_memory:
4119 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4120 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4121 ptr_cid_info = phba->cid_array_info[ulp_num];
4122
4123 if (ptr_cid_info) {
4124 kfree(ptr_cid_info->cid_array);
4125 kfree(ptr_cid_info);
4126 phba->cid_array_info[ulp_num] = NULL;
4127 }
4128 }
4129 }
4130
4131 return ret;
6733b39a
JK		 4132}
4133
238f6b72 4134static void hwi_enable_intr(struct beiscsi_hba *phba)
6733b39a
JK		 4135{
4136 struct be_ctrl_info *ctrl = &phba->ctrl;
4137 struct hwi_controller *phwi_ctrlr;
4138 struct hwi_context_memory *phwi_context;
4139 struct be_queue_info *eq;
4140 u8 __iomem *addr;
bfead3b2 4141 u32 reg, i;
6733b39a
JK		 4142 u32 enabled;
4143
4144 phwi_ctrlr = phba->phwi_ctrlr;
4145 phwi_context = phwi_ctrlr->phwi_ctxt;
4146
6733b39a
JK		 4147 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
4148 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
4149 reg = ioread32(addr);
6733b39a
JK		 4150
4151 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4152 if (!enabled) {
4153 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
99bc5d55
JSJ		 4154 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4155 "BM_%d : reg =x%08x addr=%p\n", reg, addr);
6733b39a 4156 iowrite32(reg, addr);
665d6d94
JK		 4157 }
4158
4159 if (!phba->msix_enabled) {
4160 eq = &phwi_context->be_eq[0].q;
99bc5d55
JSJ		 4161 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4162 "BM_%d : eq->id=%d\n", eq->id);
4163
665d6d94
JK		 4164 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
4165 } else {
4166 for (i = 0; i <= phba->num_cpus; i++) {
4167 eq = &phwi_context->be_eq[i].q;
99bc5d55
JSJ		 4168 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4169 "BM_%d : eq->id=%d\n", eq->id);
bfead3b2
JK		 4170 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
4171 }
c03af1ae 4172 }
6733b39a
JK		 4173}
4174
4175static void hwi_disable_intr(struct beiscsi_hba *phba)
4176{
4177 struct be_ctrl_info *ctrl = &phba->ctrl;
4178
4179 u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
4180 u32 reg = ioread32(addr);
4181
4182 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4183 if (enabled) {
4184 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4185 iowrite32(reg, addr);
4186 } else
99bc5d55
JSJ		 4187 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
4188 "BM_%d : In hwi_disable_intr, Already Disabled\n");
6733b39a
JK		 4189}
4190
4191static int beiscsi_init_port(struct beiscsi_hba *phba)
4192{
4193 int ret;
4194
dd940972 4195 ret = hwi_init_controller(phba);
6733b39a 4196 if (ret < 0) {
99bc5d55 4197 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
dd940972 4198 "BM_%d : init controller failed\n");
6733b39a
JK		 4199 return ret;
4200 }
4201 ret = beiscsi_init_sgl_handle(phba);
4202 if (ret < 0) {
99bc5d55 4203 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
dd940972
JB		 4204 "BM_%d : init sgl handles failed\n");
4205 goto cleanup_port;
6733b39a
JK		 4206 }
4207
deeea8ed
CJ		 4208 ret = hba_setup_cid_tbls(phba);
4209 if (ret < 0) {
99bc5d55 4210 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
dd940972 4211 "BM_%d : setup CID table failed\n");
6733b39a
JK		 4212 kfree(phba->io_sgl_hndl_base);
4213 kfree(phba->eh_sgl_hndl_base);
dd940972 4214 goto cleanup_port;
6733b39a 4215 }
6733b39a
JK		 4216 return ret;
4217
dd940972 4218cleanup_port:
4d2ee1e6 4219 hwi_cleanup_port(phba);
6733b39a
JK		 4220 return ret;
4221}
4222
4d2ee1e6 4223static void beiscsi_cleanup_port(struct beiscsi_hba *phba)
6733b39a 4224{
0a3db7c0 4225 struct ulp_cid_info *ptr_cid_info = NULL;
f79929de 4226 int ulp_num;
6733b39a 4227
6733b39a
JK		 4228 kfree(phba->io_sgl_hndl_base);
4229 kfree(phba->eh_sgl_hndl_base);
6733b39a 4230 kfree(phba->ep_array);
a7909b39 4231 kfree(phba->conn_table);
0a3db7c0
JK		 4232
4233 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4234 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4235 ptr_cid_info = phba->cid_array_info[ulp_num];
4236
4237 if (ptr_cid_info) {
4238 kfree(ptr_cid_info->cid_array);
4239 kfree(ptr_cid_info);
4240 phba->cid_array_info[ulp_num] = NULL;
4241 }
4242 }
4243 }
6733b39a
JK		 4244}
4245
43f388b0
JK		 4246/**
4247 * beiscsi_free_mgmt_task_handles()- Free driver CXN resources
4248 * @beiscsi_conn: ptr to the conn to be cleaned up
4a4a11b9 4249 * @task: ptr to iscsi_task resource to be freed.
43f388b0
JK		 4250 *
4251 * Free driver mgmt resources binded to CXN.
4252 **/
4253void
4a4a11b9
JK		 4254beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
4255 struct iscsi_task *task)
43f388b0
JK		 4256{
4257 struct beiscsi_io_task *io_task;
4258 struct beiscsi_hba *phba = beiscsi_conn->phba;
4259 struct hwi_wrb_context *pwrb_context;
4260 struct hwi_controller *phwi_ctrlr;
a7909b39
JK		 4261 uint16_t cri_index = BE_GET_CRI_FROM_CID(
4262 beiscsi_conn->beiscsi_conn_cid);
43f388b0
JK		 4263
4264 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39
JK		 4265 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
4266
4a4a11b9 4267 io_task = task->dd_data;
43f388b0
JK		 4268
4269 if (io_task->pwrb_handle) {
e1f9d31e 4270 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
43f388b0
JK		 4271 io_task->pwrb_handle = NULL;
4272 }
4273
4274 if (io_task->psgl_handle) {
e1f9d31e 4275 free_mgmt_sgl_handle(phba, io_task->psgl_handle);
43f388b0
JK		 4276 io_task->psgl_handle = NULL;
4277 }
4278
eb1c4692 4279 if (io_task->mtask_addr) {
43f388b0
JK		 4280 pci_unmap_single(phba->pcidev,
4281 io_task->mtask_addr,
4282 io_task->mtask_data_count,
4283 PCI_DMA_TODEVICE);
eb1c4692
JSJ		 4284 io_task->mtask_addr = 0;
4285 }
43f388b0
JK		 4286}
4287
d629c471
JSJ		 4288/**
4289 * beiscsi_cleanup_task()- Free driver resources of the task
4290 * @task: ptr to the iscsi task
4291 *
4292 **/
1282ab76
MC		 4293static void beiscsi_cleanup_task(struct iscsi_task *task)
4294{
4295 struct beiscsi_io_task *io_task = task->dd_data;
4296 struct iscsi_conn *conn = task->conn;
4297 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4298 struct beiscsi_hba *phba = beiscsi_conn->phba;
4299 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
4300 struct hwi_wrb_context *pwrb_context;
4301 struct hwi_controller *phwi_ctrlr;
a7909b39
JK		 4302 uint16_t cri_index = BE_GET_CRI_FROM_CID(
4303 beiscsi_conn->beiscsi_conn_cid);
1282ab76
MC		 4304
4305 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 4306 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
1282ab76
MC		 4307
4308 if (io_task->cmd_bhs) {
4309 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
4310 io_task->bhs_pa.u.a64.address);
4311 io_task->cmd_bhs = NULL;
e1f9d31e 4312 task->hdr = NULL;
1282ab76
MC		 4313 }
4314
4315 if (task->sc) {
4316 if (io_task->pwrb_handle) {
4317 free_wrb_handle(phba, pwrb_context,
4318 io_task->pwrb_handle);
4319 io_task->pwrb_handle = NULL;
4320 }
4321
4322 if (io_task->psgl_handle) {
1282ab76 4323 free_io_sgl_handle(phba, io_task->psgl_handle);
1282ab76
MC		 4324 io_task->psgl_handle = NULL;
4325 }
da334977
JK		 4326
4327 if (io_task->scsi_cmnd) {
9122e991
JB		 4328 if (io_task->num_sg)
4329 scsi_dma_unmap(io_task->scsi_cmnd);
da334977
JK		 4330 io_task->scsi_cmnd = NULL;
4331 }
1282ab76 4332 } else {
43f388b0 4333 if (!beiscsi_conn->login_in_progress)
4a4a11b9 4334 beiscsi_free_mgmt_task_handles(beiscsi_conn, task);
1282ab76
MC		 4335 }
4336}
4337
6733b39a
JK		 4338void
4339beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
4340 struct beiscsi_offload_params *params)
4341{
4342 struct wrb_handle *pwrb_handle;
340c99e9 4343 struct hwi_wrb_context *pwrb_context = NULL;
6733b39a 4344 struct beiscsi_hba *phba = beiscsi_conn->phba;
1282ab76
MC		 4345 struct iscsi_task *task = beiscsi_conn->task;
4346 struct iscsi_session *session = task->conn->session;
6733b39a
JK		 4347 u32 doorbell = 0;
4348
4349 /*
4350 * We can always use 0 here because it is reserved by libiscsi for
4351 * login/startup related tasks.
4352 */
1282ab76 4353 beiscsi_conn->login_in_progress = 0;
659743b0 4354 spin_lock_bh(&session->back_lock);
1282ab76 4355 beiscsi_cleanup_task(task);
659743b0 4356 spin_unlock_bh(&session->back_lock);
1282ab76 4357
340c99e9
JSJ		 4358 pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid,
4359 &pwrb_context);
6733b39a 4360
acb9693c 4361 /* Check for the adapter family */
2c9dfd36 4362 if (is_chip_be2_be3r(phba))
acb9693c 4363 beiscsi_offload_cxn_v0(params, pwrb_handle,
340c99e9
JSJ		 4364 phba->init_mem,
4365 pwrb_context);
2c9dfd36 4366 else
340c99e9
JSJ		 4367 beiscsi_offload_cxn_v2(params, pwrb_handle,
4368 pwrb_context);
6733b39a 4369
acb9693c
JSJ		 4370 be_dws_le_to_cpu(pwrb_handle->pwrb,
4371 sizeof(struct iscsi_target_context_update_wrb));
6733b39a
JK		 4372
4373 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 4374 doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
bfead3b2 4375 << DB_DEF_PDU_WRB_INDEX_SHIFT;
6733b39a 4376 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4377 iowrite32(doorbell, phba->db_va +
4378 beiscsi_conn->doorbell_offset);
cb564c6b
JB		 4379
4380 /*
4381 * There is no completion for CONTEXT_UPDATE. The completion of next
4382 * WRB posted guarantees FW's processing and DMA'ing of it.
4383 * Use beiscsi_put_wrb_handle to put it back in the pool which makes
4384 * sure zero'ing or reuse of the WRB only after wrbs_per_cxn.
4385 */
4386 beiscsi_put_wrb_handle(pwrb_context, pwrb_handle,
4387 phba->params.wrbs_per_cxn);
4388 beiscsi_log(phba, KERN_INFO,
4389 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4390 "BM_%d : put CONTEXT_UPDATE pwrb_handle=%p free_index=0x%x wrb_handles_available=%d\n",
4391 pwrb_handle, pwrb_context->free_index,
4392 pwrb_context->wrb_handles_available);
6733b39a
JK		 4393}
4394
4395static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
4396 int *index, int *age)
4397{
bfead3b2 4398 *index = (int)itt;
6733b39a
JK		 4399 if (age)
4400 *age = conn->session->age;
4401}
4402
4403/**
4404 * beiscsi_alloc_pdu - allocates pdu and related resources
4405 * @task: libiscsi task
4406 * @opcode: opcode of pdu for task
4407 *
4408 * This is called with the session lock held. It will allocate
4409 * the wrb and sgl if needed for the command. And it will prep
4410 * the pdu's itt. beiscsi_parse_pdu will later translate
4411 * the pdu itt to the libiscsi task itt.
4412 */
4413static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
4414{
4415 struct beiscsi_io_task *io_task = task->dd_data;
4416 struct iscsi_conn *conn = task->conn;
4417 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4418 struct beiscsi_hba *phba = beiscsi_conn->phba;
4419 struct hwi_wrb_context *pwrb_context;
4420 struct hwi_controller *phwi_ctrlr;
4421 itt_t itt;
a7909b39 4422 uint16_t cri_index = 0;
2afc95bf
JK		 4423 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
4424 dma_addr_t paddr;
6733b39a 4425
2afc95bf 4426 io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
bc7accec 4427 GFP_ATOMIC, &paddr);
2afc95bf
JK		 4428 if (!io_task->cmd_bhs)
4429 return -ENOMEM;
2afc95bf 4430 io_task->bhs_pa.u.a64.address = paddr;
bfead3b2 4431 io_task->libiscsi_itt = (itt_t)task->itt;
6733b39a
JK		 4432 io_task->conn = beiscsi_conn;
4433
4434 task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
4435 task->hdr_max = sizeof(struct be_cmd_bhs);
d2cecf0d 4436 io_task->psgl_handle = NULL;
3ec78271 4437 io_task->pwrb_handle = NULL;
6733b39a
JK		 4438
4439 if (task->sc) {
6733b39a 4440 io_task->psgl_handle = alloc_io_sgl_handle(phba);
8359c79b
JSJ		 4441 if (!io_task->psgl_handle) {
4442 beiscsi_log(phba, KERN_ERR,
4443 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4444 "BM_%d : Alloc of IO_SGL_ICD Failed"
4445 "for the CID : %d\n",
4446 beiscsi_conn->beiscsi_conn_cid);
2afc95bf 4447 goto free_hndls;
8359c79b 4448 }
d2cecf0d 4449 io_task->pwrb_handle = alloc_wrb_handle(phba,
340c99e9
JSJ		 4450 beiscsi_conn->beiscsi_conn_cid,
4451 &io_task->pwrb_context);
8359c79b
JSJ		 4452 if (!io_task->pwrb_handle) {
4453 beiscsi_log(phba, KERN_ERR,
4454 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4455 "BM_%d : Alloc of WRB_HANDLE Failed"
4456 "for the CID : %d\n",
4457 beiscsi_conn->beiscsi_conn_cid);
d2cecf0d 4458 goto free_io_hndls;
8359c79b 4459 }
6733b39a
JK		 4460 } else {
4461 io_task->scsi_cmnd = NULL;
d7aea67b 4462 if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
43f388b0 4463 beiscsi_conn->task = task;
6733b39a 4464 if (!beiscsi_conn->login_in_progress) {
6733b39a
JK		 4465 io_task->psgl_handle = (struct sgl_handle *)
4466 alloc_mgmt_sgl_handle(phba);
8359c79b
JSJ		 4467 if (!io_task->psgl_handle) {
4468 beiscsi_log(phba, KERN_ERR,
4469 BEISCSI_LOG_IO |
4470 BEISCSI_LOG_CONFIG,
4471 "BM_%d : Alloc of MGMT_SGL_ICD Failed"
4472 "for the CID : %d\n",
4473 beiscsi_conn->
4474 beiscsi_conn_cid);
2afc95bf 4475 goto free_hndls;
8359c79b 4476 }
2afc95bf 4477
6733b39a
JK		 4478 beiscsi_conn->login_in_progress = 1;
4479 beiscsi_conn->plogin_sgl_handle =
4480 io_task->psgl_handle;
d2cecf0d
JK		 4481 io_task->pwrb_handle =
4482 alloc_wrb_handle(phba,
340c99e9
JSJ		 4483 beiscsi_conn->beiscsi_conn_cid,
4484 &io_task->pwrb_context);
8359c79b
JSJ		 4485 if (!io_task->pwrb_handle) {
4486 beiscsi_log(phba, KERN_ERR,
4487 BEISCSI_LOG_IO |
4488 BEISCSI_LOG_CONFIG,
4489 "BM_%d : Alloc of WRB_HANDLE Failed"
4490 "for the CID : %d\n",
4491 beiscsi_conn->
4492 beiscsi_conn_cid);
4493 goto free_mgmt_hndls;
4494 }
d2cecf0d
JK		 4495 beiscsi_conn->plogin_wrb_handle =
4496 io_task->pwrb_handle;
4497
6733b39a
JK		 4498 } else {
4499 io_task->psgl_handle =
4500 beiscsi_conn->plogin_sgl_handle;
d2cecf0d
JK		 4501 io_task->pwrb_handle =
4502 beiscsi_conn->plogin_wrb_handle;
6733b39a
JK		 4503 }
4504 } else {
6733b39a 4505 io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
8359c79b
JSJ		 4506 if (!io_task->psgl_handle) {
4507 beiscsi_log(phba, KERN_ERR,
4508 BEISCSI_LOG_IO |
4509 BEISCSI_LOG_CONFIG,
4510 "BM_%d : Alloc of MGMT_SGL_ICD Failed"
4511 "for the CID : %d\n",
4512 beiscsi_conn->
4513 beiscsi_conn_cid);
2afc95bf 4514 goto free_hndls;
8359c79b 4515 }
d2cecf0d
JK		 4516 io_task->pwrb_handle =
4517 alloc_wrb_handle(phba,
340c99e9
JSJ		 4518 beiscsi_conn->beiscsi_conn_cid,
4519 &io_task->pwrb_context);
8359c79b
JSJ		 4520 if (!io_task->pwrb_handle) {
4521 beiscsi_log(phba, KERN_ERR,
4522 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4523 "BM_%d : Alloc of WRB_HANDLE Failed"
4524 "for the CID : %d\n",
4525 beiscsi_conn->beiscsi_conn_cid);
d2cecf0d 4526 goto free_mgmt_hndls;
8359c79b 4527 }
d2cecf0d 4528
6733b39a
JK		 4529 }
4530 }
bfead3b2
JK		 4531 itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
4532 wrb_index << 16) | (unsigned int)
4533 (io_task->psgl_handle->sgl_index));
32951dd8 4534 io_task->pwrb_handle->pio_handle = task;
bfead3b2 4535
6733b39a
JK		 4536 io_task->cmd_bhs->iscsi_hdr.itt = itt;
4537 return 0;
2afc95bf 4538
d2cecf0d 4539free_io_hndls:
d2cecf0d 4540 free_io_sgl_handle(phba, io_task->psgl_handle);
d2cecf0d
JK		 4541 goto free_hndls;
4542free_mgmt_hndls:
d2cecf0d 4543 free_mgmt_sgl_handle(phba, io_task->psgl_handle);
a7909b39 4544 io_task->psgl_handle = NULL;
2afc95bf
JK		 4545free_hndls:
4546 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39
JK		 4547 cri_index = BE_GET_CRI_FROM_CID(
4548 beiscsi_conn->beiscsi_conn_cid);
4549 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
d2cecf0d
JK		 4550 if (io_task->pwrb_handle)
4551 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
2afc95bf
JK		 4552 io_task->pwrb_handle = NULL;
4553 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
4554 io_task->bhs_pa.u.a64.address);
1282ab76 4555 io_task->cmd_bhs = NULL;
2afc95bf 4556 return -ENOMEM;
6733b39a 4557}
0825b8ee 4558static int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg,
09a1093a
JSJ		 4559 unsigned int num_sg, unsigned int xferlen,
4560 unsigned int writedir)
4561{
4562
4563 struct beiscsi_io_task *io_task = task->dd_data;
4564 struct iscsi_conn *conn = task->conn;
4565 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4566 struct beiscsi_hba *phba = beiscsi_conn->phba;
4567 struct iscsi_wrb *pwrb = NULL;
4568 unsigned int doorbell = 0;
4569
4570 pwrb = io_task->pwrb_handle->pwrb;
09a1093a 4571
09a1093a
JSJ		 4572 io_task->bhs_len = sizeof(struct be_cmd_bhs);
4573
4574 if (writedir) {
4575 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
4576 INI_WR_CMD);
4577 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1);
4578 } else {
4579 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
4580 INI_RD_CMD);
4581 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0);
4582 }
4583
4584 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2,
4585 type, pwrb);
4586
4587 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb,
4588 cpu_to_be16(*(unsigned short *)
4589 &io_task->cmd_bhs->iscsi_hdr.lun));
4590 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen);
4591 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
4592 io_task->pwrb_handle->wrb_index);
4593 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
4594 be32_to_cpu(task->cmdsn));
4595 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
4596 io_task->psgl_handle->sgl_index);
4597
4598 hwi_write_sgl_v2(pwrb, sg, num_sg, io_task);
4599 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
340c99e9
JSJ		 4600 io_task->pwrb_handle->wrb_index);
4601 if (io_task->pwrb_context->plast_wrb)
4602 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb,
4603 io_task->pwrb_context->plast_wrb,
4604 io_task->pwrb_handle->wrb_index);
4605 io_task->pwrb_context->plast_wrb = pwrb;
09a1093a
JSJ		 4606
4607 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4608
4609 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
4610 doorbell |= (io_task->pwrb_handle->wrb_index &
4611 DB_DEF_PDU_WRB_INDEX_MASK) <<
4612 DB_DEF_PDU_WRB_INDEX_SHIFT;
4613 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4614 iowrite32(doorbell, phba->db_va +
4615 beiscsi_conn->doorbell_offset);
09a1093a
JSJ		 4616 return 0;
4617}
6733b39a 4618
6733b39a
JK		 4619static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
4620 unsigned int num_sg, unsigned int xferlen,
4621 unsigned int writedir)
4622{
4623
4624 struct beiscsi_io_task *io_task = task->dd_data;
4625 struct iscsi_conn *conn = task->conn;
4626 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4627 struct beiscsi_hba *phba = beiscsi_conn->phba;
4628 struct iscsi_wrb *pwrb = NULL;
4629 unsigned int doorbell = 0;
4630
4631 pwrb = io_task->pwrb_handle->pwrb;
6733b39a
JK		 4632 io_task->bhs_len = sizeof(struct be_cmd_bhs);
4633
4634 if (writedir) {
32951dd8
JK		 4635 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4636 INI_WR_CMD);
6733b39a 4637 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
6733b39a 4638 } else {
32951dd8
JK		 4639 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4640 INI_RD_CMD);
6733b39a
JK		 4641 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
4642 }
6733b39a 4643
09a1093a
JSJ		 4644 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb,
4645 type, pwrb);
4646
6733b39a 4647 AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
dc63aac6
JK		 4648 cpu_to_be16(*(unsigned short *)
4649 &io_task->cmd_bhs->iscsi_hdr.lun));
6733b39a
JK		 4650 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
4651 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
4652 io_task->pwrb_handle->wrb_index);
4653 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
4654 be32_to_cpu(task->cmdsn));
4655 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
4656 io_task->psgl_handle->sgl_index);
4657
4658 hwi_write_sgl(pwrb, sg, num_sg, io_task);
4659
4660 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
340c99e9
JSJ		 4661 io_task->pwrb_handle->wrb_index);
4662 if (io_task->pwrb_context->plast_wrb)
4663 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb,
4664 io_task->pwrb_context->plast_wrb,
4665 io_task->pwrb_handle->wrb_index);
4666 io_task->pwrb_context->plast_wrb = pwrb;
4667
6733b39a
JK		 4668 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4669
4670 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 4671 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 4672 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
4673 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
4674
1e4be6ff
JK		 4675 iowrite32(doorbell, phba->db_va +
4676 beiscsi_conn->doorbell_offset);
6733b39a
JK		 4677 return 0;
4678}
4679
4680static int beiscsi_mtask(struct iscsi_task *task)
4681{
dafab8e0 4682 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 4683 struct iscsi_conn *conn = task->conn;
4684 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4685 struct beiscsi_hba *phba = beiscsi_conn->phba;
4686 struct iscsi_wrb *pwrb = NULL;
4687 unsigned int doorbell = 0;
dafab8e0 4688 unsigned int cid;
09a1093a 4689 unsigned int pwrb_typeoffset = 0;
e0493627 4690 int ret = 0;
6733b39a 4691
bfead3b2 4692 cid = beiscsi_conn->beiscsi_conn_cid;
6733b39a 4693 pwrb = io_task->pwrb_handle->pwrb;
09a1093a 4694
2c9dfd36 4695 if (is_chip_be2_be3r(phba)) {
09a1093a
JSJ		 4696 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
4697 be32_to_cpu(task->cmdsn));
4698 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
4699 io_task->pwrb_handle->wrb_index);
4700 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
4701 io_task->psgl_handle->sgl_index);
4702 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
4703 task->data_count);
4704 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
340c99e9
JSJ		 4705 io_task->pwrb_handle->wrb_index);
4706 if (io_task->pwrb_context->plast_wrb)
4707 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb,
4708 io_task->pwrb_context->plast_wrb,
4709 io_task->pwrb_handle->wrb_index);
4710 io_task->pwrb_context->plast_wrb = pwrb;
4711
09a1093a 4712 pwrb_typeoffset = BE_WRB_TYPE_OFFSET;
2c9dfd36
JK		 4713 } else {
4714 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
4715 be32_to_cpu(task->cmdsn));
4716 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
4717 io_task->pwrb_handle->wrb_index);
4718 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
4719 io_task->psgl_handle->sgl_index);
4720 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb,
4721 task->data_count);
4722 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
340c99e9
JSJ		 4723 io_task->pwrb_handle->wrb_index);
4724 if (io_task->pwrb_context->plast_wrb)
4725 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb,
4726 io_task->pwrb_context->plast_wrb,
4727 io_task->pwrb_handle->wrb_index);
4728 io_task->pwrb_context->plast_wrb = pwrb;
4729
2c9dfd36 4730 pwrb_typeoffset = SKH_WRB_TYPE_OFFSET;
09a1093a
JSJ		 4731 }
4732
dafab8e0 4733
6733b39a
JK		 4734 switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
4735 case ISCSI_OP_LOGIN:
6733b39a 4736 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
09a1093a 4737 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
e0493627 4738 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 4739 break;
4740 case ISCSI_OP_NOOP_OUT:
1390b01b 4741 if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
09a1093a 4742 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
2c9dfd36
JK		 4743 if (is_chip_be2_be3r(phba))
4744 AMAP_SET_BITS(struct amap_iscsi_wrb,
09a1093a
JSJ		 4745 dmsg, pwrb, 1);
4746 else
2c9dfd36 4747 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
09a1093a 4748 dmsg, pwrb, 1);
1390b01b 4749 } else {
09a1093a 4750 ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset);
2c9dfd36
JK		 4751 if (is_chip_be2_be3r(phba))
4752 AMAP_SET_BITS(struct amap_iscsi_wrb,
09a1093a
JSJ		 4753 dmsg, pwrb, 0);
4754 else
2c9dfd36 4755 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
09a1093a 4756 dmsg, pwrb, 0);
1390b01b 4757 }
e0493627 4758 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 4759 break;
4760 case ISCSI_OP_TEXT:
09a1093a 4761 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
e0493627 4762 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 4763 break;
4764 case ISCSI_OP_SCSI_TMFUNC:
09a1093a 4765 ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset);
e0493627 4766 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 4767 break;
4768 case ISCSI_OP_LOGOUT:
09a1093a 4769 ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset);
e0493627 4770 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 4771 break;
4772
4773 default:
99bc5d55
JSJ		 4774 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
4775 "BM_%d : opcode =%d Not supported\n",
4776 task->hdr->opcode & ISCSI_OPCODE_MASK);
4777
6733b39a
JK		 4778 return -EINVAL;
4779 }
4780
e0493627
AK		 4781 if (ret)
4782 return ret;
4783
09a1093a 4784 /* Set the task type */
2c9dfd36
JK		 4785 io_task->wrb_type = (is_chip_be2_be3r(phba)) ?
4786 AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) :
4787 AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb);
6733b39a 4788
bfead3b2 4789 doorbell |= cid & DB_WRB_POST_CID_MASK;
32951dd8 4790 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 4791 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
4792 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4793 iowrite32(doorbell, phba->db_va +
4794 beiscsi_conn->doorbell_offset);
6733b39a
JK		 4795 return 0;
4796}
4797
4798static int beiscsi_task_xmit(struct iscsi_task *task)
4799{
6733b39a
JK		 4800 struct beiscsi_io_task *io_task = task->dd_data;
4801 struct scsi_cmnd *sc = task->sc;
1868379b 4802 struct beiscsi_hba *phba;
6733b39a
JK		 4803 struct scatterlist *sg;
4804 int num_sg;
4805 unsigned int writedir = 0, xferlen = 0;
4806
9122e991
JB		 4807 phba = io_task->conn->phba;
4808 /**
4809 * HBA in error includes BEISCSI_HBA_FW_TIMEOUT. IO path might be
4810 * operational if FW still gets heartbeat from EP FW. Is management
4811 * path really needed to continue further?
4812 */
d1d5ca88 4813 if (!beiscsi_hba_is_online(phba))
9122e991
JB		 4814 return -EIO;
4815
1868379b
JB		 4816 if (!io_task->conn->login_in_progress)
4817 task->hdr->exp_statsn = 0;
09a1093a 4818
6733b39a
JK		 4819 if (!sc)
4820 return beiscsi_mtask(task);
4821
4822 io_task->scsi_cmnd = sc;
9122e991 4823 io_task->num_sg = 0;
6733b39a
JK		 4824 num_sg = scsi_dma_map(sc);
4825 if (num_sg < 0) {
afb96058
JK		 4826 beiscsi_log(phba, KERN_ERR,
4827 BEISCSI_LOG_IO | BEISCSI_LOG_ISCSI,
4828 "BM_%d : scsi_dma_map Failed "
4829 "Driver_ITT : 0x%x ITT : 0x%x Xferlen : 0x%x\n",
4830 be32_to_cpu(io_task->cmd_bhs->iscsi_hdr.itt),
4831 io_task->libiscsi_itt, scsi_bufflen(sc));
99bc5d55 4832
6733b39a
JK		 4833 return num_sg;
4834 }
9122e991
JB		 4835 /**
4836 * For scsi cmd task, check num_sg before unmapping in cleanup_task.
4837 * For management task, cleanup_task checks mtask_addr before unmapping.
4838 */
4839 io_task->num_sg = num_sg;
6733b39a
JK		 4840 xferlen = scsi_bufflen(sc);
4841 sg = scsi_sglist(sc);
99bc5d55 4842 if (sc->sc_data_direction == DMA_TO_DEVICE)
6733b39a 4843 writedir = 1;
99bc5d55 4844 else
6733b39a 4845 writedir = 0;
99bc5d55 4846
09a1093a 4847 return phba->iotask_fn(task, sg, num_sg, xferlen, writedir);
6733b39a
JK		 4848}
4849
ffce3e2e
JK		 4850/**
4851 * beiscsi_bsg_request - handle bsg request from ISCSI transport
4852 * @job: job to handle
4853 */
4854static int beiscsi_bsg_request(struct bsg_job *job)
4855{
4856 struct Scsi_Host *shost;
4857 struct beiscsi_hba *phba;
4858 struct iscsi_bsg_request *bsg_req = job->request;
4859 int rc = -EINVAL;
4860 unsigned int tag;
4861 struct be_dma_mem nonemb_cmd;
4862 struct be_cmd_resp_hdr *resp;
4863 struct iscsi_bsg_reply *bsg_reply = job->reply;
4864 unsigned short status, extd_status;
4865
4866 shost = iscsi_job_to_shost(job);
4867 phba = iscsi_host_priv(shost);
4868
d1d5ca88 4869 if (!beiscsi_hba_is_online(phba)) {
9122e991
JB		 4870 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
4871 "BM_%d : HBA in error 0x%lx\n", phba->state);
4872 return -ENXIO;
4873 }
4874
ffce3e2e
JK		 4875 switch (bsg_req->msgcode) {
4876 case ISCSI_BSG_HST_VENDOR:
4877 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
4878 job->request_payload.payload_len,
4879 &nonemb_cmd.dma);
4880 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 4881 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
4882 "BM_%d : Failed to allocate memory for "
4883 "beiscsi_bsg_request\n");
8359c79b 4884 return -ENOMEM;
ffce3e2e
JK		 4885 }
4886 tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
4887 &nonemb_cmd);
4888 if (!tag) {
99bc5d55 4889 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
8359c79b 4890 "BM_%d : MBX Tag Allocation Failed\n");
99bc5d55 4891
ffce3e2e
JK		 4892 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
4893 nonemb_cmd.va, nonemb_cmd.dma);
4894 return -EAGAIN;
e175defe
JSJ		 4895 }
4896
4897 rc = wait_event_interruptible_timeout(
4898 phba->ctrl.mcc_wait[tag],
67296ad9 4899 phba->ctrl.mcc_tag_status[tag],
e175defe
JSJ		 4900 msecs_to_jiffies(
4901 BEISCSI_HOST_MBX_TIMEOUT));
d1d5ca88
JB		 4902
4903 if (!test_bit(BEISCSI_HBA_ONLINE, &phba->state)) {
4904 clear_bit(MCC_TAG_STATE_RUNNING,
4905 &phba->ctrl.ptag_state[tag].tag_state);
4906 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
4907 nonemb_cmd.va, nonemb_cmd.dma);
4908 return -EIO;
4909 }
67296ad9
JB		 4910 extd_status = (phba->ctrl.mcc_tag_status[tag] &
4911 CQE_STATUS_ADDL_MASK) >> CQE_STATUS_ADDL_SHIFT;
4912 status = phba->ctrl.mcc_tag_status[tag] & CQE_STATUS_MASK;
090e2184 4913 free_mcc_wrb(&phba->ctrl, tag);
ffce3e2e
JK		 4914 resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
4915 sg_copy_from_buffer(job->reply_payload.sg_list,
4916 job->reply_payload.sg_cnt,
4917 nonemb_cmd.va, (resp->response_length
4918 + sizeof(*resp)));
4919 bsg_reply->reply_payload_rcv_len = resp->response_length;
4920 bsg_reply->result = status;
4921 bsg_job_done(job, bsg_reply->result,
4922 bsg_reply->reply_payload_rcv_len);
4923 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
4924 nonemb_cmd.va, nonemb_cmd.dma);
4925 if (status || extd_status) {
99bc5d55 4926 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
8359c79b 4927 "BM_%d : MBX Cmd Failed"
99bc5d55
JSJ		 4928 " status = %d extd_status = %d\n",
4929 status, extd_status);
4930
ffce3e2e 4931 return -EIO;
8359c79b
JSJ		 4932 } else {
4933 rc = 0;
ffce3e2e
JK		 4934 }
4935 break;
4936
4937 default:
99bc5d55
JSJ		 4938 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
4939 "BM_%d : Unsupported bsg command: 0x%x\n",
4940 bsg_req->msgcode);
ffce3e2e
JK		 4941 break;
4942 }
4943
4944 return rc;
4945}
4946
0825b8ee 4947static void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
99bc5d55
JSJ		 4948{
4949 /* Set the logging parameter */
4950 beiscsi_log_enable_init(phba, beiscsi_log_enable);
4951}
4952
d1d5ca88 4953void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle)
6733b39a 4954{
d1d5ca88
JB		 4955 if (phba->boot_struct.boot_kset)
4956 return;
50a4b824
JB		 4957
4958 /* skip if boot work is already in progress */
4959 if (test_and_set_bit(BEISCSI_HBA_BOOT_WORK, &phba->state))
4960 return;
4961
4962 phba->boot_struct.retry = 3;
4963 phba->boot_struct.tag = 0;
4964 phba->boot_struct.s_handle = s_handle;
4965 phba->boot_struct.action = BEISCSI_BOOT_GET_SHANDLE;
4966 schedule_work(&phba->boot_work);
4967}
4968
4969static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
4970{
4971 struct beiscsi_hba *phba = data;
4972 struct mgmt_session_info *boot_sess = &phba->boot_struct.boot_sess;
4973 struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
4974 char *str = buf;
4975 int rc = -EPERM;
4976
4977 switch (type) {
4978 case ISCSI_BOOT_TGT_NAME:
4979 rc = sprintf(buf, "%.*s\n",
4980 (int)strlen(boot_sess->target_name),
4981 (char *)&boot_sess->target_name);
4982 break;
4983 case ISCSI_BOOT_TGT_IP_ADDR:
4984 if (boot_conn->dest_ipaddr.ip_type == BEISCSI_IP_TYPE_V4)
4985 rc = sprintf(buf, "%pI4\n",
4986 (char *)&boot_conn->dest_ipaddr.addr);
4987 else
4988 rc = sprintf(str, "%pI6\n",
4989 (char *)&boot_conn->dest_ipaddr.addr);
4990 break;
4991 case ISCSI_BOOT_TGT_PORT:
4992 rc = sprintf(str, "%d\n", boot_conn->dest_port);
4993 break;
4994
4995 case ISCSI_BOOT_TGT_CHAP_NAME:
4996 rc = sprintf(str, "%.*s\n",
4997 boot_conn->negotiated_login_options.auth_data.chap.
4998 target_chap_name_length,
4999 (char *)&boot_conn->negotiated_login_options.
5000 auth_data.chap.target_chap_name);
5001 break;
5002 case ISCSI_BOOT_TGT_CHAP_SECRET:
5003 rc = sprintf(str, "%.*s\n",
5004 boot_conn->negotiated_login_options.auth_data.chap.
5005 target_secret_length,
5006 (char *)&boot_conn->negotiated_login_options.
5007 auth_data.chap.target_secret);
5008 break;
5009 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
5010 rc = sprintf(str, "%.*s\n",
5011 boot_conn->negotiated_login_options.auth_data.chap.
5012 intr_chap_name_length,
5013 (char *)&boot_conn->negotiated_login_options.
5014 auth_data.chap.intr_chap_name);
5015 break;
5016 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
5017 rc = sprintf(str, "%.*s\n",
5018 boot_conn->negotiated_login_options.auth_data.chap.
5019 intr_secret_length,
5020 (char *)&boot_conn->negotiated_login_options.
5021 auth_data.chap.intr_secret);
5022 break;
5023 case ISCSI_BOOT_TGT_FLAGS:
5024 rc = sprintf(str, "2\n");
5025 break;
5026 case ISCSI_BOOT_TGT_NIC_ASSOC:
5027 rc = sprintf(str, "0\n");
5028 break;
5029 }
5030 return rc;
5031}
5032
5033static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
5034{
5035 struct beiscsi_hba *phba = data;
5036 char *str = buf;
5037 int rc = -EPERM;
5038
5039 switch (type) {
5040 case ISCSI_BOOT_INI_INITIATOR_NAME:
5041 rc = sprintf(str, "%s\n",
5042 phba->boot_struct.boot_sess.initiator_iscsiname);
5043 break;
5044 }
5045 return rc;
5046}
5047
5048static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
5049{
5050 struct beiscsi_hba *phba = data;
5051 char *str = buf;
5052 int rc = -EPERM;
5053
5054 switch (type) {
5055 case ISCSI_BOOT_ETH_FLAGS:
5056 rc = sprintf(str, "2\n");
5057 break;
5058 case ISCSI_BOOT_ETH_INDEX:
5059 rc = sprintf(str, "0\n");
5060 break;
5061 case ISCSI_BOOT_ETH_MAC:
5062 rc = beiscsi_get_macaddr(str, phba);
5063 break;
5064 }
5065 return rc;
5066}
5067
50a4b824
JB		 5068static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
5069{
5070 umode_t rc = 0;
5071
5072 switch (type) {
5073 case ISCSI_BOOT_TGT_NAME:
5074 case ISCSI_BOOT_TGT_IP_ADDR:
5075 case ISCSI_BOOT_TGT_PORT:
5076 case ISCSI_BOOT_TGT_CHAP_NAME:
5077 case ISCSI_BOOT_TGT_CHAP_SECRET:
5078 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
5079 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
5080 case ISCSI_BOOT_TGT_NIC_ASSOC:
5081 case ISCSI_BOOT_TGT_FLAGS:
5082 rc = S_IRUGO;
5083 break;
5084 }
5085 return rc;
5086}
5087
5088static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
5089{
5090 umode_t rc = 0;
5091
5092 switch (type) {
5093 case ISCSI_BOOT_INI_INITIATOR_NAME:
5094 rc = S_IRUGO;
5095 break;
5096 }
5097 return rc;
5098}
5099
50a4b824
JB		 5100static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
5101{
5102 umode_t rc = 0;
5103
5104 switch (type) {
5105 case ISCSI_BOOT_ETH_FLAGS:
5106 case ISCSI_BOOT_ETH_MAC:
5107 case ISCSI_BOOT_ETH_INDEX:
5108 rc = S_IRUGO;
5109 break;
5110 }
5111 return rc;
5112}
5113
5114static void beiscsi_boot_kobj_release(void *data)
5115{
5116 struct beiscsi_hba *phba = data;
5117
5118 scsi_host_put(phba->shost);
5119}
5120
5121static int beiscsi_boot_create_kset(struct beiscsi_hba *phba)
5122{
5123 struct boot_struct *bs = &phba->boot_struct;
5124 struct iscsi_boot_kobj *boot_kobj;
5125
5126 if (bs->boot_kset) {
5127 __beiscsi_log(phba, KERN_ERR,
5128 "BM_%d: boot_kset already created\n");
5129 return 0;
5130 }
5131
5132 bs->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
5133 if (!bs->boot_kset) {
5134 __beiscsi_log(phba, KERN_ERR,
5135 "BM_%d: boot_kset alloc failed\n");
5136 return -ENOMEM;
5137 }
5138
5139 /* get shost ref because the show function will refer phba */
5140 if (!scsi_host_get(phba->shost))
5141 goto free_kset;
5142
5143 boot_kobj = iscsi_boot_create_target(bs->boot_kset, 0, phba,
5144 beiscsi_show_boot_tgt_info,
5145 beiscsi_tgt_get_attr_visibility,
5146 beiscsi_boot_kobj_release);
5147 if (!boot_kobj)
5148 goto put_shost;
5149
5150 if (!scsi_host_get(phba->shost))
5151 goto free_kset;
5152
5153 boot_kobj = iscsi_boot_create_initiator(bs->boot_kset, 0, phba,
5154 beiscsi_show_boot_ini_info,
5155 beiscsi_ini_get_attr_visibility,
5156 beiscsi_boot_kobj_release);
5157 if (!boot_kobj)
5158 goto put_shost;
5159
5160 if (!scsi_host_get(phba->shost))
5161 goto free_kset;
5162
5163 boot_kobj = iscsi_boot_create_ethernet(bs->boot_kset, 0, phba,
5164 beiscsi_show_boot_eth_info,
5165 beiscsi_eth_get_attr_visibility,
5166 beiscsi_boot_kobj_release);
5167 if (!boot_kobj)
5168 goto put_shost;
5169
5170 return 0;
5171
5172put_shost:
5173 scsi_host_put(phba->shost);
5174free_kset:
5175 iscsi_boot_destroy_kset(bs->boot_kset);
5176 bs->boot_kset = NULL;
5177 return -ENOMEM;
5178}
5179
5180static void beiscsi_boot_work(struct work_struct *work)
5181{
5182 struct beiscsi_hba *phba =
5183 container_of(work, struct beiscsi_hba, boot_work);
5184 struct boot_struct *bs = &phba->boot_struct;
5185 unsigned int tag = 0;
5186
d1d5ca88 5187 if (!beiscsi_hba_is_online(phba))
50a4b824
JB		 5188 return;
5189
5190 beiscsi_log(phba, KERN_INFO,
5191 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
5192 "BM_%d : %s action %d\n",
5193 __func__, phba->boot_struct.action);
5194
5195 switch (phba->boot_struct.action) {
5196 case BEISCSI_BOOT_REOPEN_SESS:
5197 tag = beiscsi_boot_reopen_sess(phba);
5198 break;
5199 case BEISCSI_BOOT_GET_SHANDLE:
5200 tag = __beiscsi_boot_get_shandle(phba, 1);
5201 break;
5202 case BEISCSI_BOOT_GET_SINFO:
5203 tag = beiscsi_boot_get_sinfo(phba);
5204 break;
5205 case BEISCSI_BOOT_LOGOUT_SESS:
5206 tag = beiscsi_boot_logout_sess(phba);
5207 break;
5208 case BEISCSI_BOOT_CREATE_KSET:
5209 beiscsi_boot_create_kset(phba);
5210 /**
5211 * updated boot_kset is made visible to all before
5212 * ending the boot work.
5213 */
5214 mb();
5215 clear_bit(BEISCSI_HBA_BOOT_WORK, &phba->state);
5216 return;
5217 }
5218 if (!tag) {
5219 if (bs->retry--)
5220 schedule_work(&phba->boot_work);
5221 else
5222 clear_bit(BEISCSI_HBA_BOOT_WORK, &phba->state);
5223 }
5224}
5225
10bcd47d
JB		 5226static void beiscsi_eqd_update_work(struct work_struct *work)
5227{
5228 struct hwi_context_memory *phwi_context;
73af08e1 5229 struct be_set_eqd set_eqd[MAX_CPUS];
73af08e1 5230 struct hwi_controller *phwi_ctrlr;
10bcd47d
JB		 5231 struct be_eq_obj *pbe_eq;
5232 struct beiscsi_hba *phba;
5233 unsigned int pps, delta;
5234 struct be_aic_obj *aic;
73af08e1 5235 int eqd, i, num = 0;
10bcd47d 5236 unsigned long now;
73af08e1 5237
10bcd47d 5238 phba = container_of(work, struct beiscsi_hba, eqd_update.work);
d1d5ca88 5239 if (!beiscsi_hba_is_online(phba))
9122e991
JB		 5240 return;
5241
73af08e1
JK		 5242 phwi_ctrlr = phba->phwi_ctrlr;
5243 phwi_context = phwi_ctrlr->phwi_ctxt;
5244
5245 for (i = 0; i <= phba->num_cpus; i++) {
5246 aic = &phba->aic_obj[i];
5247 pbe_eq = &phwi_context->be_eq[i];
5248 now = jiffies;
10bcd47d 5249 if (!aic->jiffies || time_before(now, aic->jiffies) ||
73af08e1 5250 pbe_eq->cq_count < aic->eq_prev) {
10bcd47d 5251 aic->jiffies = now;
73af08e1
JK		 5252 aic->eq_prev = pbe_eq->cq_count;
5253 continue;
5254 }
10bcd47d 5255 delta = jiffies_to_msecs(now - aic->jiffies);
73af08e1
JK		 5256 pps = (((u32)(pbe_eq->cq_count - aic->eq_prev) * 1000) / delta);
5257 eqd = (pps / 1500) << 2;
5258
5259 if (eqd < 8)
5260 eqd = 0;
5261 eqd = min_t(u32, eqd, phwi_context->max_eqd);
5262 eqd = max_t(u32, eqd, phwi_context->min_eqd);
5263
10bcd47d 5264 aic->jiffies = now;
73af08e1
JK		 5265 aic->eq_prev = pbe_eq->cq_count;
5266
5267 if (eqd != aic->prev_eqd) {
5268 set_eqd[num].delay_multiplier = (eqd * 65)/100;
5269 set_eqd[num].eq_id = pbe_eq->q.id;
5270 aic->prev_eqd = eqd;
5271 num++;
5272 }
5273 }
10bcd47d
JB		 5274 if (num)
5275 /* completion of this is ignored */
5276 beiscsi_modify_eq_delay(phba, set_eqd, num);
73af08e1 5277
10bcd47d
JB		 5278 schedule_delayed_work(&phba->eqd_update,
5279 msecs_to_jiffies(BEISCSI_EQD_UPDATE_INTERVAL));
7a158003
JSJ		 5280}
5281
d1d5ca88
JB		 5282static void beiscsi_msix_enable(struct beiscsi_hba *phba)
5283{
5284 int i, status;
5285
5286 for (i = 0; i <= phba->num_cpus; i++)
5287 phba->msix_entries[i].entry = i;
5288
5289 status = pci_enable_msix_range(phba->pcidev, phba->msix_entries,
5290 phba->num_cpus + 1, phba->num_cpus + 1);
5291 if (status > 0)
5292 phba->msix_enabled = true;
5293}
5294
5295static void beiscsi_hw_tpe_check(unsigned long ptr)
5296{
5297 struct beiscsi_hba *phba;
5298 u32 wait;
5299
5300 phba = (struct beiscsi_hba *)ptr;
5301 /* if not TPE, do nothing */
5302 if (!beiscsi_detect_tpe(phba))
5303 return;
5304
5305 /* wait default 4000ms before recovering */
5306 wait = 4000;
5307 if (phba->ue2rp > BEISCSI_UE_DETECT_INTERVAL)
5308 wait = phba->ue2rp - BEISCSI_UE_DETECT_INTERVAL;
5309 queue_delayed_work(phba->wq, &phba->recover_port,
5310 msecs_to_jiffies(wait));
5311}
5312
5313static void beiscsi_hw_health_check(unsigned long ptr)
5314{
5315 struct beiscsi_hba *phba;
5316
5317 phba = (struct beiscsi_hba *)ptr;
5318 beiscsi_detect_ue(phba);
5319 if (beiscsi_detect_ue(phba)) {
5320 __beiscsi_log(phba, KERN_ERR,
5321 "BM_%d : port in error: %lx\n", phba->state);
10e1a44a
JB		 5322 /* sessions are no longer valid, so first fail the sessions */
5323 queue_work(phba->wq, &phba->sess_work);
5324
5325 /* detect UER supported */
d1d5ca88
JB		 5326 if (!test_bit(BEISCSI_HBA_UER_SUPP, &phba->state))
5327 return;
5328 /* modify this timer to check TPE */
5329 phba->hw_check.function = beiscsi_hw_tpe_check;
5330 }
5331
5332 mod_timer(&phba->hw_check,
5333 jiffies + msecs_to_jiffies(BEISCSI_UE_DETECT_INTERVAL));
5334}
5335
5336/*
5337 * beiscsi_enable_port()- Enables the disabled port.
5338 * Only port resources freed in disable function are reallocated.
5339 * This is called in HBA error handling path.
5340 *
5341 * @phba: Instance of driver private structure
5342 *
5343 **/
5344static int beiscsi_enable_port(struct beiscsi_hba *phba)
5345{
5346 struct hwi_context_memory *phwi_context;
5347 struct hwi_controller *phwi_ctrlr;
5348 struct be_eq_obj *pbe_eq;
5349 int ret, i;
5350
5351 if (test_bit(BEISCSI_HBA_ONLINE, &phba->state)) {
5352 __beiscsi_log(phba, KERN_ERR,
5353 "BM_%d : %s : port is online %lx\n",
5354 __func__, phba->state);
5355 return 0;
5356 }
5357
5358 ret = beiscsi_init_sliport(phba);
5359 if (ret)
5360 return ret;
5361
5362 if (enable_msix)
5363 find_num_cpus(phba);
5364 else
5365 phba->num_cpus = 1;
5366 if (enable_msix) {
5367 beiscsi_msix_enable(phba);
5368 if (!phba->msix_enabled)
5369 phba->num_cpus = 1;
5370 }
5371
5372 beiscsi_get_params(phba);
5373 /* Re-enable UER. If different TPE occurs then it is recoverable. */
5374 beiscsi_set_uer_feature(phba);
5375
5376 phba->shost->max_id = phba->params.cxns_per_ctrl;
5377 phba->shost->can_queue = phba->params.ios_per_ctrl;
dd940972
JB		 5378 ret = beiscsi_init_port(phba);
5379 if (ret < 0) {
d1d5ca88 5380 __beiscsi_log(phba, KERN_ERR,
dd940972 5381 "BM_%d : init port failed\n");
d1d5ca88
JB		 5382 goto disable_msix;
5383 }
5384
5385 for (i = 0; i < MAX_MCC_CMD; i++) {
5386 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5387 phba->ctrl.mcc_tag[i] = i + 1;
5388 phba->ctrl.mcc_tag_status[i + 1] = 0;
5389 phba->ctrl.mcc_tag_available++;
5390 }
5391
5392 phwi_ctrlr = phba->phwi_ctrlr;
5393 phwi_context = phwi_ctrlr->phwi_ctxt;
5394 for (i = 0; i < phba->num_cpus; i++) {
5395 pbe_eq = &phwi_context->be_eq[i];
5396 irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget, be_iopoll);
5397 }
5398
5399 i = (phba->msix_enabled) ? i : 0;
5400 /* Work item for MCC handling */
5401 pbe_eq = &phwi_context->be_eq[i];
5402 INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work);
5403
5404 ret = beiscsi_init_irqs(phba);
5405 if (ret < 0) {
5406 __beiscsi_log(phba, KERN_ERR,
5407 "BM_%d : setup IRQs failed %d\n", ret);
5408 goto cleanup_port;
5409 }
5410 hwi_enable_intr(phba);
5411 /* port operational: clear all error bits */
5412 set_bit(BEISCSI_HBA_ONLINE, &phba->state);
5413 __beiscsi_log(phba, KERN_INFO,
5414 "BM_%d : port online: 0x%lx\n", phba->state);
5415
5416 /* start hw_check timer and eqd_update work */
5417 schedule_delayed_work(&phba->eqd_update,
5418 msecs_to_jiffies(BEISCSI_EQD_UPDATE_INTERVAL));
5419
5420 /**
5421 * Timer function gets modified for TPE detection.
5422 * Always reinit to do health check first.
5423 */
5424 phba->hw_check.function = beiscsi_hw_health_check;
5425 mod_timer(&phba->hw_check,
5426 jiffies + msecs_to_jiffies(BEISCSI_UE_DETECT_INTERVAL));
5427 return 0;
5428
5429cleanup_port:
5430 for (i = 0; i < phba->num_cpus; i++) {
5431 pbe_eq = &phwi_context->be_eq[i];
5432 irq_poll_disable(&pbe_eq->iopoll);
5433 }
5434 hwi_cleanup_port(phba);
5435
5436disable_msix:
5437 if (phba->msix_enabled)
5438 pci_disable_msix(phba->pcidev);
5439
5440 return ret;
5441}
5442
5443/*
5444 * beiscsi_disable_port()- Disable port and cleanup driver resources.
5445 * This is called in HBA error handling and driver removal.
5446 * @phba: Instance Priv structure
5447 * @unload: indicate driver is unloading
5448 *
5449 * Free the OS and HW resources held by the driver
5450 **/
5451static void beiscsi_disable_port(struct beiscsi_hba *phba, int unload)
5452{
5453 struct hwi_context_memory *phwi_context;
5454 struct hwi_controller *phwi_ctrlr;
5455 struct be_eq_obj *pbe_eq;
5456 unsigned int i, msix_vec;
5457
5458 if (!test_and_clear_bit(BEISCSI_HBA_ONLINE, &phba->state))
5459 return;
5460
5461 phwi_ctrlr = phba->phwi_ctrlr;
5462 phwi_context = phwi_ctrlr->phwi_ctxt;
5463 hwi_disable_intr(phba);
5464 if (phba->msix_enabled) {
5465 for (i = 0; i <= phba->num_cpus; i++) {
5466 msix_vec = phba->msix_entries[i].vector;
5467 free_irq(msix_vec, &phwi_context->be_eq[i]);
5468 kfree(phba->msi_name[i]);
5469 }
5470 } else
5471 if (phba->pcidev->irq)
5472 free_irq(phba->pcidev->irq, phba);
5473 pci_disable_msix(phba->pcidev);
5474
5475 for (i = 0; i < phba->num_cpus; i++) {
5476 pbe_eq = &phwi_context->be_eq[i];
5477 irq_poll_disable(&pbe_eq->iopoll);
5478 }
5479 cancel_delayed_work_sync(&phba->eqd_update);
5480 cancel_work_sync(&phba->boot_work);
5481 /* WQ might be running cancel queued mcc_work if we are not exiting */
5482 if (!unload && beiscsi_hba_in_error(phba)) {
5483 pbe_eq = &phwi_context->be_eq[i];
5484 cancel_work_sync(&pbe_eq->mcc_work);
5485 }
5486 hwi_cleanup_port(phba);
dd940972 5487 beiscsi_cleanup_port(phba);
d1d5ca88
JB		 5488}
5489
10e1a44a
JB		 5490static void beiscsi_sess_work(struct work_struct *work)
5491{
5492 struct beiscsi_hba *phba;
5493
5494 phba = container_of(work, struct beiscsi_hba, sess_work);
5495 /*
5496 * This work gets scheduled only in case of HBA error.
5497 * Old sessions are gone so need to be re-established.
5498 * iscsi_session_failure needs process context hence this work.
5499 */
5500 iscsi_host_for_each_session(phba->shost, beiscsi_session_fail);
5501}
5502
d1d5ca88
JB		 5503static void beiscsi_recover_port(struct work_struct *work)
5504{
5505 struct beiscsi_hba *phba;
5506
5507 phba = container_of(work, struct beiscsi_hba, recover_port.work);
d1d5ca88
JB		 5508 beiscsi_disable_port(phba, 0);
5509 beiscsi_enable_port(phba);
5510}
3567f36a
JK		 5511
5512static pci_ers_result_t beiscsi_eeh_err_detected(struct pci_dev *pdev,
5513 pci_channel_state_t state)
5514{
5515 struct beiscsi_hba *phba = NULL;
5516
5517 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
9122e991 5518 set_bit(BEISCSI_HBA_PCI_ERR, &phba->state);
3567f36a
JK		 5519
5520 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5521 "BM_%d : EEH error detected\n");
5522
d1d5ca88
JB		 5523 /* first stop UE detection when PCI error detected */
5524 del_timer_sync(&phba->hw_check);
5525 cancel_delayed_work_sync(&phba->recover_port);
5526
10e1a44a
JB		 5527 /* sessions are no longer valid, so first fail the sessions */
5528 iscsi_host_for_each_session(phba->shost, beiscsi_session_fail);
d1d5ca88 5529 beiscsi_disable_port(phba, 0);
3567f36a
JK		 5530
5531 if (state == pci_channel_io_perm_failure) {
5532 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5533 "BM_%d : EEH : State PERM Failure");
5534 return PCI_ERS_RESULT_DISCONNECT;
5535 }
5536
5537 pci_disable_device(pdev);
5538
5539 /* The error could cause the FW to trigger a flash debug dump.
5540 * Resetting the card while flash dump is in progress
5541 * can cause it not to recover; wait for it to finish.
5542 * Wait only for first function as it is needed only once per
5543 * adapter.
5544 **/
5545 if (pdev->devfn == 0)
5546 ssleep(30);
5547
5548 return PCI_ERS_RESULT_NEED_RESET;
5549}
5550
5551static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev)
5552{
5553 struct beiscsi_hba *phba = NULL;
5554 int status = 0;
5555
5556 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5557
5558 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5559 "BM_%d : EEH Reset\n");
5560
5561 status = pci_enable_device(pdev);
5562 if (status)
5563 return PCI_ERS_RESULT_DISCONNECT;
5564
5565 pci_set_master(pdev);
5566 pci_set_power_state(pdev, PCI_D0);
5567 pci_restore_state(pdev);
5568
4d2ee1e6
JB		 5569 status = beiscsi_check_fw_rdy(phba);
5570 if (status) {
3567f36a
JK		 5571 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5572 "BM_%d : EEH Reset Completed\n");
5573 } else {
5574 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5575 "BM_%d : EEH Reset Completion Failure\n");
5576 return PCI_ERS_RESULT_DISCONNECT;
5577 }
5578
5579 pci_cleanup_aer_uncorrect_error_status(pdev);
5580 return PCI_ERS_RESULT_RECOVERED;
5581}
5582
5583static void beiscsi_eeh_resume(struct pci_dev *pdev)
5584{
d1d5ca88
JB		 5585 struct beiscsi_hba *phba;
5586 int ret;
3567f36a
JK		 5587
5588 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5589 pci_save_state(pdev);
5590
d1d5ca88 5591 ret = beiscsi_enable_port(phba);
4d2ee1e6 5592 if (ret)
d1d5ca88
JB		 5593 __beiscsi_log(phba, KERN_ERR,
5594 "BM_%d : AER EEH resume failed\n");
3567f36a
JK		 5595}
5596
6f039790
GKH		 5597static int beiscsi_dev_probe(struct pci_dev *pcidev,
5598 const struct pci_device_id *id)
6733b39a 5599{
bfead3b2 5600 struct hwi_context_memory *phwi_context;
29e80b7c
JB		 5601 struct hwi_controller *phwi_ctrlr;
5602 struct beiscsi_hba *phba = NULL;
bfead3b2 5603 struct be_eq_obj *pbe_eq;
50a4b824 5604 unsigned int s_handle;
29e80b7c 5605 char wq_name[20];
deeea8ed 5606 int ret, i;
6733b39a
JK		 5607
5608 ret = beiscsi_enable_pci(pcidev);
5609 if (ret < 0) {
99bc5d55
JSJ		 5610 dev_err(&pcidev->dev,
5611 "beiscsi_dev_probe - Failed to enable pci device\n");
6733b39a
JK		 5612 return ret;
5613 }
5614
5615 phba = beiscsi_hba_alloc(pcidev);
5616 if (!phba) {
99bc5d55
JSJ		 5617 dev_err(&pcidev->dev,
5618 "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
deeea8ed 5619 ret = -ENOMEM;
6733b39a
JK		 5620 goto disable_pci;
5621 }
5622
3567f36a
JK		 5623 /* Enable EEH reporting */
5624 ret = pci_enable_pcie_error_reporting(pcidev);
5625 if (ret)
5626 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5627 "BM_%d : PCIe Error Reporting "
5628 "Enabling Failed\n");
5629
5630 pci_save_state(pcidev);
5631
99bc5d55
JSJ		 5632 /* Initialize Driver configuration Paramters */
5633 beiscsi_hba_attrs_init(phba);
5634
6c83185a 5635 phba->mac_addr_set = false;
e175defe 5636
f98c96b0
JK		 5637 switch (pcidev->device) {
5638 case BE_DEVICE_ID1:
5639 case OC_DEVICE_ID1:
5640 case OC_DEVICE_ID2:
5641 phba->generation = BE_GEN2;
09a1093a 5642 phba->iotask_fn = beiscsi_iotask;
5fa7db21
KM		 5643 dev_warn(&pcidev->dev,
5644 "Obsolete/Unsupported BE2 Adapter Family\n");
f98c96b0
JK		 5645 break;
5646 case BE_DEVICE_ID2:
5647 case OC_DEVICE_ID3:
5648 phba->generation = BE_GEN3;
09a1093a 5649 phba->iotask_fn = beiscsi_iotask;
f98c96b0 5650 break;
139a1b1e
JSJ		 5651 case OC_SKH_ID1:
5652 phba->generation = BE_GEN4;
09a1093a 5653 phba->iotask_fn = beiscsi_iotask_v2;
bf9131cb 5654 break;
f98c96b0
JK		 5655 default:
5656 phba->generation = 0;
5657 }
5658
6733b39a
JK		 5659 ret = be_ctrl_init(phba, pcidev);
5660 if (ret) {
99bc5d55 5661 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4d2ee1e6 5662 "BM_%d : be_ctrl_init failed\n");
6733b39a
JK		 5663 goto hba_free;
5664 }
5665
4d2ee1e6
JB		 5666 ret = beiscsi_init_sliport(phba);
5667 if (ret)
4d4d1ef8 5668 goto hba_free;
e9b91193 5669
6733b39a
JK		 5670 spin_lock_init(&phba->io_sgl_lock);
5671 spin_lock_init(&phba->mgmt_sgl_lock);
8f09a3b9 5672 spin_lock_init(&phba->async_pdu_lock);
480195c2 5673 ret = beiscsi_get_fw_config(&phba->ctrl, phba);
7da50879 5674 if (ret != 0) {
99bc5d55
JSJ		 5675 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5676 "BM_%d : Error getting fw config\n");
7da50879
JK		 5677 goto free_port;
5678 }
480195c2 5679 beiscsi_get_port_name(&phba->ctrl, phba);
4570f161 5680 beiscsi_get_params(phba);
6694095b 5681 beiscsi_set_uer_feature(phba);
68c26a3a
JK		 5682
5683 if (enable_msix)
5684 find_num_cpus(phba);
5685 else
5686 phba->num_cpus = 1;
5687
5688 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
5689 "BM_%d : num_cpus = %d\n",
5690 phba->num_cpus);
5691
5692 if (enable_msix) {
5693 beiscsi_msix_enable(phba);
5694 if (!phba->msix_enabled)
5695 phba->num_cpus = 1;
5696 }
5697
843ae752 5698 phba->shost->max_id = phba->params.cxns_per_ctrl;
aa874f07 5699 phba->shost->can_queue = phba->params.ios_per_ctrl;
dd940972
JB		 5700 ret = beiscsi_get_memory(phba);
5701 if (ret < 0) {
5702 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5703 "BM_%d : alloc host mem failed\n");
5704 goto free_port;
5705 }
5706
6733b39a
JK		 5707 ret = beiscsi_init_port(phba);
5708 if (ret < 0) {
99bc5d55 5709 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
dd940972
JB		 5710 "BM_%d : init port failed\n");
5711 beiscsi_free_mem(phba);
6733b39a
JK		 5712 goto free_port;
5713 }
5714
3567f36a 5715 for (i = 0; i < MAX_MCC_CMD; i++) {
756d29c8
JK		 5716 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5717 phba->ctrl.mcc_tag[i] = i + 1;
67296ad9 5718 phba->ctrl.mcc_tag_status[i + 1] = 0;
756d29c8 5719 phba->ctrl.mcc_tag_available++;
1957aa7f 5720 memset(&phba->ctrl.ptag_state[i].tag_mem_state, 0,
8fc01eaa 5721 sizeof(struct be_dma_mem));
756d29c8
JK		 5722 }
5723
5724 phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
5725
29e80b7c 5726 snprintf(wq_name, sizeof(wq_name), "beiscsi_%02x_wq",
6733b39a 5727 phba->shost->host_no);
29e80b7c 5728 phba->wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 1, wq_name);
6733b39a 5729 if (!phba->wq) {
99bc5d55
JSJ		 5730 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5731 "BM_%d : beiscsi_dev_probe-"
5732 "Failed to allocate work queue\n");
deeea8ed 5733 ret = -ENOMEM;
6733b39a
JK		 5734 goto free_twq;
5735 }
5736
10bcd47d 5737 INIT_DELAYED_WORK(&phba->eqd_update, beiscsi_eqd_update_work);
6733b39a 5738
bfead3b2
JK		 5739 phwi_ctrlr = phba->phwi_ctrlr;
5740 phwi_context = phwi_ctrlr->phwi_ctxt;
72fb46a9 5741
89f8b33c 5742 for (i = 0; i < phba->num_cpus; i++) {
72fb46a9 5743 pbe_eq = &phwi_context->be_eq[i];
d1d5ca88 5744 irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget, be_iopoll);
6733b39a 5745 }
72fb46a9 5746
89f8b33c
JA		 5747 i = (phba->msix_enabled) ? i : 0;
5748 /* Work item for MCC handling */
5749 pbe_eq = &phwi_context->be_eq[i];
a3095016 5750 INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work);
89f8b33c 5751
6733b39a
JK		 5752 ret = beiscsi_init_irqs(phba);
5753 if (ret < 0) {
99bc5d55
JSJ		 5754 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5755 "BM_%d : beiscsi_dev_probe-"
5756 "Failed to beiscsi_init_irqs\n");
6733b39a
JK		 5757 goto free_blkenbld;
5758 }
238f6b72 5759 hwi_enable_intr(phba);
f457a46f 5760
d1d5ca88
JB		 5761 ret = iscsi_host_add(phba->shost, &phba->pcidev->dev);
5762 if (ret)
0598b8af
JK		 5763 goto free_blkenbld;
5764
d1d5ca88
JB		 5765 /* set online bit after port is operational */
5766 set_bit(BEISCSI_HBA_ONLINE, &phba->state);
5767 __beiscsi_log(phba, KERN_INFO,
5768 "BM_%d : port online: 0x%lx\n", phba->state);
5769
50a4b824
JB		 5770 INIT_WORK(&phba->boot_work, beiscsi_boot_work);
5771 ret = beiscsi_boot_get_shandle(phba, &s_handle);
5772 if (ret > 0) {
5773 beiscsi_start_boot_work(phba, s_handle);
5774 /**
5775 * Set this bit after starting the work to let
5776 * probe handle it first.
5777 * ASYNC event can too schedule this work.
f457a46f 5778 */
50a4b824
JB		 5779 set_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state);
5780 }
f457a46f 5781
96b48b92 5782 beiscsi_iface_create_default(phba);
10bcd47d
JB		 5783 schedule_delayed_work(&phba->eqd_update,
5784 msecs_to_jiffies(BEISCSI_EQD_UPDATE_INTERVAL));
d1d5ca88 5785
10e1a44a 5786 INIT_WORK(&phba->sess_work, beiscsi_sess_work);
d1d5ca88 5787 INIT_DELAYED_WORK(&phba->recover_port, beiscsi_recover_port);
10bcd47d
JB		 5788 /**
5789 * Start UE detection here. UE before this will cause stall in probe
5790 * and eventually fail the probe.
5791 */
5792 init_timer(&phba->hw_check);
5793 phba->hw_check.function = beiscsi_hw_health_check;
5794 phba->hw_check.data = (unsigned long)phba;
5795 mod_timer(&phba->hw_check,
5796 jiffies + msecs_to_jiffies(BEISCSI_UE_DETECT_INTERVAL));
99bc5d55
JSJ		 5797 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
5798 "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
6733b39a
JK		 5799 return 0;
5800
6733b39a
JK		 5801free_blkenbld:
5802 destroy_workqueue(phba->wq);
89f8b33c
JA		 5803 for (i = 0; i < phba->num_cpus; i++) {
5804 pbe_eq = &phwi_context->be_eq[i];
511cbce2 5805 irq_poll_disable(&pbe_eq->iopoll);
89f8b33c 5806 }
6733b39a 5807free_twq:
d1d5ca88 5808 hwi_cleanup_port(phba);
4d2ee1e6 5809 beiscsi_cleanup_port(phba);
6733b39a
JK		 5810 beiscsi_free_mem(phba);
5811free_port:
5812 pci_free_consistent(phba->pcidev,
5813 phba->ctrl.mbox_mem_alloced.size,
5814 phba->ctrl.mbox_mem_alloced.va,
5815 phba->ctrl.mbox_mem_alloced.dma);
5816 beiscsi_unmap_pci_function(phba);
5817hba_free:
238f6b72
JK		 5818 if (phba->msix_enabled)
5819 pci_disable_msix(phba->pcidev);
6733b39a
JK		 5820 pci_dev_put(phba->pcidev);
5821 iscsi_host_free(phba->shost);
2e7cee02 5822 pci_set_drvdata(pcidev, NULL);
6733b39a 5823disable_pci:
e307f3ac 5824 pci_release_regions(pcidev);
6733b39a
JK		 5825 pci_disable_device(pcidev);
5826 return ret;
5827}
5828
d1d5ca88
JB		 5829static void beiscsi_remove(struct pci_dev *pcidev)
5830{
5831 struct beiscsi_hba *phba = NULL;
5832
5833 phba = pci_get_drvdata(pcidev);
5834 if (!phba) {
5835 dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
5836 return;
5837 }
5838
5839 /* first stop UE detection before unloading */
5840 del_timer_sync(&phba->hw_check);
5841 cancel_delayed_work_sync(&phba->recover_port);
10e1a44a 5842 cancel_work_sync(&phba->sess_work);
d1d5ca88
JB		 5843
5844 beiscsi_iface_destroy_default(phba);
5845 iscsi_host_remove(phba->shost);
5846 beiscsi_disable_port(phba, 1);
5847
5848 /* after cancelling boot_work */
5849 iscsi_boot_destroy_kset(phba->boot_struct.boot_kset);
5850
5851 /* free all resources */
5852 destroy_workqueue(phba->wq);
d1d5ca88
JB		 5853 beiscsi_free_mem(phba);
5854
5855 /* ctrl uninit */
5856 beiscsi_unmap_pci_function(phba);
5857 pci_free_consistent(phba->pcidev,
5858 phba->ctrl.mbox_mem_alloced.size,
5859 phba->ctrl.mbox_mem_alloced.va,
5860 phba->ctrl.mbox_mem_alloced.dma);
5861
5862 pci_dev_put(phba->pcidev);
5863 iscsi_host_free(phba->shost);
5864 pci_disable_pcie_error_reporting(pcidev);
5865 pci_set_drvdata(pcidev, NULL);
5866 pci_release_regions(pcidev);
5867 pci_disable_device(pcidev);
5868}
5869
5870
3567f36a
JK		 5871static struct pci_error_handlers beiscsi_eeh_handlers = {
5872 .error_detected = beiscsi_eeh_err_detected,
5873 .slot_reset = beiscsi_eeh_reset,
5874 .resume = beiscsi_eeh_resume,
5875};
5876
6733b39a
JK		 5877struct iscsi_transport beiscsi_iscsi_transport = {
5878 .owner = THIS_MODULE,
5879 .name = DRV_NAME,
9db0fb3a 5880 .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
6733b39a 5881 CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
6733b39a
JK		 5882 .create_session = beiscsi_session_create,
5883 .destroy_session = beiscsi_session_destroy,
5884 .create_conn = beiscsi_conn_create,
5885 .bind_conn = beiscsi_conn_bind,
5886 .destroy_conn = iscsi_conn_teardown,
96b48b92
JB		 5887 .attr_is_visible = beiscsi_attr_is_visible,
5888 .set_iface_param = beiscsi_iface_set_param,
5889 .get_iface_param = beiscsi_iface_get_param,
6733b39a 5890 .set_param = beiscsi_set_param,
c7f7fd5b 5891 .get_conn_param = iscsi_conn_get_param,
6733b39a
JK		 5892 .get_session_param = iscsi_session_get_param,
5893 .get_host_param = beiscsi_get_host_param,
5894 .start_conn = beiscsi_conn_start,
fa95d206 5895 .stop_conn = iscsi_conn_stop,
6733b39a
JK		 5896 .send_pdu = iscsi_conn_send_pdu,
5897 .xmit_task = beiscsi_task_xmit,
5898 .cleanup_task = beiscsi_cleanup_task,
5899 .alloc_pdu = beiscsi_alloc_pdu,
5900 .parse_pdu_itt = beiscsi_parse_pdu,
5901 .get_stats = beiscsi_conn_get_stats,
c7f7fd5b 5902 .get_ep_param = beiscsi_ep_get_param,
6733b39a
JK		 5903 .ep_connect = beiscsi_ep_connect,
5904 .ep_poll = beiscsi_ep_poll,
5905 .ep_disconnect = beiscsi_ep_disconnect,
5906 .session_recovery_timedout = iscsi_session_recovery_timedout,
ffce3e2e 5907 .bsg_request = beiscsi_bsg_request,
6733b39a
JK		 5908};
5909
5910static struct pci_driver beiscsi_pci_driver = {
5911 .name = DRV_NAME,
5912 .probe = beiscsi_dev_probe,
5913 .remove = beiscsi_remove,
3567f36a
JK		 5914 .id_table = beiscsi_pci_id_table,
5915 .err_handler = &beiscsi_eeh_handlers
6733b39a
JK		 5916};
5917
5918static int __init beiscsi_module_init(void)
5919{
5920 int ret;
5921
5922 beiscsi_scsi_transport =
5923 iscsi_register_transport(&beiscsi_iscsi_transport);
5924 if (!beiscsi_scsi_transport) {
99bc5d55
JSJ		 5925 printk(KERN_ERR
5926 "beiscsi_module_init - Unable to register beiscsi transport.\n");
f55a24f2 5927 return -ENOMEM;
6733b39a 5928 }
99bc5d55
JSJ		 5929 printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
5930 &beiscsi_iscsi_transport);
6733b39a
JK		 5931
5932 ret = pci_register_driver(&beiscsi_pci_driver);
5933 if (ret) {
99bc5d55
JSJ		 5934 printk(KERN_ERR
5935 "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
6733b39a
JK		 5936 goto unregister_iscsi_transport;
5937 }
5938 return 0;
5939
5940unregister_iscsi_transport:
5941 iscsi_unregister_transport(&beiscsi_iscsi_transport);
5942 return ret;
5943}
5944
5945static void __exit beiscsi_module_exit(void)
5946{
5947 pci_unregister_driver(&beiscsi_pci_driver);
5948 iscsi_unregister_transport(&beiscsi_iscsi_transport);
5949}
5950
5951module_init(beiscsi_module_init);
5952module_exit(beiscsi_module_exit);
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