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scsi: be2iscsi: Remove isr_lock and dead code
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / be2iscsi / be_main.c
CommitLineData
6733b39a 1/**
c4f39bda 2 * Copyright (C) 2005 - 2015 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
4627de93 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@avagotech.com)
6733b39a
JK		 11 *
12 * Contact Information:
4627de93 13 * linux-drivers@avagotech.com
6733b39a 14 *
c4f39bda 15 * Emulex
255fa9a3
JK		 16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a 18 */
255fa9a3 19
6733b39a
JK		 20#include <linux/reboot.h>
21#include <linux/delay.h>
5a0e3ad6 22#include <linux/slab.h>
6733b39a
JK		 23#include <linux/interrupt.h>
24#include <linux/blkdev.h>
25#include <linux/pci.h>
26#include <linux/string.h>
27#include <linux/kernel.h>
28#include <linux/semaphore.h>
c7acc5b8 29#include <linux/iscsi_boot_sysfs.h>
acf3368f 30#include <linux/module.h>
ffce3e2e 31#include <linux/bsg-lib.h>
1094cf68 32#include <linux/irq_poll.h>
6733b39a
JK		 33
34#include <scsi/libiscsi.h>
ffce3e2e
JK		 35#include <scsi/scsi_bsg_iscsi.h>
36#include <scsi/scsi_netlink.h>
6733b39a
JK		 37#include <scsi/scsi_transport_iscsi.h>
38#include <scsi/scsi_transport.h>
39#include <scsi/scsi_cmnd.h>
40#include <scsi/scsi_device.h>
41#include <scsi/scsi_host.h>
42#include <scsi/scsi.h>
43#include "be_main.h"
44#include "be_iscsi.h"
45#include "be_mgmt.h"
0a513dd8 46#include "be_cmds.h"
6733b39a
JK		 47
48static unsigned int be_iopoll_budget = 10;
49static unsigned int be_max_phys_size = 64;
bfead3b2 50static unsigned int enable_msix = 1;
6733b39a 51
6733b39a 52MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
76d15dbd 53MODULE_VERSION(BUILD_STR);
c4f39bda 54MODULE_AUTHOR("Emulex Corporation");
6733b39a
JK		 55MODULE_LICENSE("GPL");
56module_param(be_iopoll_budget, int, 0);
57module_param(enable_msix, int, 0);
58module_param(be_max_phys_size, uint, S_IRUGO);
99bc5d55
JSJ		 59MODULE_PARM_DESC(be_max_phys_size,
60 "Maximum Size (In Kilobytes) of physically contiguous "
61 "memory that can be allocated. Range is 16 - 128");
62
63#define beiscsi_disp_param(_name)\
64ssize_t \
65beiscsi_##_name##_disp(struct device *dev,\
66 struct device_attribute *attrib, char *buf) \
67{ \
68 struct Scsi_Host *shost = class_to_shost(dev);\
69 struct beiscsi_hba *phba = iscsi_host_priv(shost); \
70 uint32_t param_val = 0; \
71 param_val = phba->attr_##_name;\
72 return snprintf(buf, PAGE_SIZE, "%d\n",\
73 phba->attr_##_name);\
74}
75
76#define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
77int \
78beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
79{\
80 if (val >= _minval && val <= _maxval) {\
81 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
82 "BA_%d : beiscsi_"#_name" updated "\
83 "from 0x%x ==> 0x%x\n",\
84 phba->attr_##_name, val); \
85 phba->attr_##_name = val;\
86 return 0;\
87 } \
88 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
89 "BA_%d beiscsi_"#_name" attribute "\
90 "cannot be updated to 0x%x, "\
91 "range allowed is ["#_minval" - "#_maxval"]\n", val);\
92 return -EINVAL;\
93}
94
95#define beiscsi_store_param(_name) \
96ssize_t \
97beiscsi_##_name##_store(struct device *dev,\
98 struct device_attribute *attr, const char *buf,\
99 size_t count) \
100{ \
101 struct Scsi_Host *shost = class_to_shost(dev);\
102 struct beiscsi_hba *phba = iscsi_host_priv(shost);\
103 uint32_t param_val = 0;\
104 if (!isdigit(buf[0]))\
105 return -EINVAL;\
106 if (sscanf(buf, "%i", &param_val) != 1)\
107 return -EINVAL;\
108 if (beiscsi_##_name##_change(phba, param_val) == 0) \
109 return strlen(buf);\
110 else \
111 return -EINVAL;\
112}
113
114#define beiscsi_init_param(_name, _minval, _maxval, _defval) \
115int \
116beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
117{ \
118 if (val >= _minval && val <= _maxval) {\
119 phba->attr_##_name = val;\
120 return 0;\
121 } \
122 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
123 "BA_%d beiscsi_"#_name" attribute " \
124 "cannot be updated to 0x%x, "\
125 "range allowed is ["#_minval" - "#_maxval"]\n", val);\
126 phba->attr_##_name = _defval;\
127 return -EINVAL;\
128}
129
130#define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
131static uint beiscsi_##_name = _defval;\
132module_param(beiscsi_##_name, uint, S_IRUGO);\
133MODULE_PARM_DESC(beiscsi_##_name, _descp);\
134beiscsi_disp_param(_name)\
135beiscsi_change_param(_name, _minval, _maxval, _defval)\
136beiscsi_store_param(_name)\
137beiscsi_init_param(_name, _minval, _maxval, _defval)\
138DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
139 beiscsi_##_name##_disp, beiscsi_##_name##_store)
140
141/*
142 * When new log level added update the
143 * the MAX allowed value for log_enable
144 */
145BEISCSI_RW_ATTR(log_enable, 0x00,
146 0xFF, 0x00, "Enable logging Bit Mask\n"
147 "\t\t\t\tInitialization Events : 0x01\n"
148 "\t\t\t\tMailbox Events : 0x02\n"
149 "\t\t\t\tMiscellaneous Events : 0x04\n"
150 "\t\t\t\tError Handling : 0x08\n"
151 "\t\t\t\tIO Path Events : 0x10\n"
afb96058
JK		 152 "\t\t\t\tConfiguration Path : 0x20\n"
153 "\t\t\t\tiSCSI Protocol : 0x40\n");
99bc5d55 154
5cac7596 155DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
26000db7 156DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL);
22661e25 157DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL);
d3fea9af 158DEVICE_ATTR(beiscsi_phys_port, S_IRUGO, beiscsi_phys_port_disp, NULL);
6103c1f7
JK		 159DEVICE_ATTR(beiscsi_active_session_count, S_IRUGO,
160 beiscsi_active_session_disp, NULL);
161DEVICE_ATTR(beiscsi_free_session_count, S_IRUGO,
162 beiscsi_free_session_disp, NULL);
99bc5d55
JSJ		 163struct device_attribute *beiscsi_attrs[] = {
164 &dev_attr_beiscsi_log_enable,
5cac7596 165 &dev_attr_beiscsi_drvr_ver,
26000db7 166 &dev_attr_beiscsi_adapter_family,
22661e25 167 &dev_attr_beiscsi_fw_ver,
6103c1f7
JK		 168 &dev_attr_beiscsi_active_session_count,
169 &dev_attr_beiscsi_free_session_count,
d3fea9af 170 &dev_attr_beiscsi_phys_port,
99bc5d55
JSJ		 171 NULL,
172};
6733b39a 173
6763daae
JSJ		 174static char const *cqe_desc[] = {
175 "RESERVED_DESC",
176 "SOL_CMD_COMPLETE",
177 "SOL_CMD_KILLED_DATA_DIGEST_ERR",
178 "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
179 "CXN_KILLED_BURST_LEN_MISMATCH",
180 "CXN_KILLED_AHS_RCVD",
181 "CXN_KILLED_HDR_DIGEST_ERR",
182 "CXN_KILLED_UNKNOWN_HDR",
183 "CXN_KILLED_STALE_ITT_TTT_RCVD",
184 "CXN_KILLED_INVALID_ITT_TTT_RCVD",
185 "CXN_KILLED_RST_RCVD",
186 "CXN_KILLED_TIMED_OUT",
187 "CXN_KILLED_RST_SENT",
188 "CXN_KILLED_FIN_RCVD",
189 "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
190 "CXN_KILLED_BAD_WRB_INDEX_ERROR",
191 "CXN_KILLED_OVER_RUN_RESIDUAL",
192 "CXN_KILLED_UNDER_RUN_RESIDUAL",
193 "CMD_KILLED_INVALID_STATSN_RCVD",
194 "CMD_KILLED_INVALID_R2T_RCVD",
195 "CMD_CXN_KILLED_LUN_INVALID",
196 "CMD_CXN_KILLED_ICD_INVALID",
197 "CMD_CXN_KILLED_ITT_INVALID",
198 "CMD_CXN_KILLED_SEQ_OUTOFORDER",
199 "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
200 "CXN_INVALIDATE_NOTIFY",
201 "CXN_INVALIDATE_INDEX_NOTIFY",
202 "CMD_INVALIDATED_NOTIFY",
203 "UNSOL_HDR_NOTIFY",
204 "UNSOL_DATA_NOTIFY",
205 "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
206 "DRIVERMSG_NOTIFY",
207 "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
208 "SOL_CMD_KILLED_DIF_ERR",
209 "CXN_KILLED_SYN_RCVD",
210 "CXN_KILLED_IMM_DATA_RCVD"
211};
212
6733b39a
JK		 213static int beiscsi_slave_configure(struct scsi_device *sdev)
214{
215 blk_queue_max_segment_size(sdev->request_queue, 65536);
216 return 0;
217}
218
4183122d
JK		 219static int beiscsi_eh_abort(struct scsi_cmnd *sc)
220{
221 struct iscsi_cls_session *cls_session;
222 struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
223 struct beiscsi_io_task *aborted_io_task;
224 struct iscsi_conn *conn;
225 struct beiscsi_conn *beiscsi_conn;
226 struct beiscsi_hba *phba;
227 struct iscsi_session *session;
228 struct invalidate_command_table *inv_tbl;
3cbb7a74 229 struct be_dma_mem nonemb_cmd;
4183122d 230 unsigned int cid, tag, num_invalidate;
1957aa7f 231 int rc;
4183122d
JK		 232
233 cls_session = starget_to_session(scsi_target(sc->device));
234 session = cls_session->dd_data;
235
659743b0 236 spin_lock_bh(&session->frwd_lock);
4183122d
JK		 237 if (!aborted_task || !aborted_task->sc) {
238 /* we raced */
659743b0 239 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 240 return SUCCESS;
241 }
242
243 aborted_io_task = aborted_task->dd_data;
244 if (!aborted_io_task->scsi_cmnd) {
245 /* raced or invalid command */
659743b0 246 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 247 return SUCCESS;
248 }
659743b0 249 spin_unlock_bh(&session->frwd_lock);
7626c06b
JK		 250 /* Invalidate WRB Posted for this Task */
251 AMAP_SET_BITS(struct amap_iscsi_wrb, invld,
252 aborted_io_task->pwrb_handle->pwrb,
253 1);
254
4183122d
JK		 255 conn = aborted_task->conn;
256 beiscsi_conn = conn->dd_data;
257 phba = beiscsi_conn->phba;
258
259 /* invalidate iocb */
260 cid = beiscsi_conn->beiscsi_conn_cid;
261 inv_tbl = phba->inv_tbl;
262 memset(inv_tbl, 0x0, sizeof(*inv_tbl));
263 inv_tbl->cid = cid;
264 inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
265 num_invalidate = 1;
3cbb7a74
JK		 266 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
267 sizeof(struct invalidate_commands_params_in),
268 &nonemb_cmd.dma);
269 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 270 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
271 "BM_%d : Failed to allocate memory for"
272 "mgmt_invalidate_icds\n");
3cbb7a74
JK		 273 return FAILED;
274 }
275 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
276
277 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
278 cid, &nonemb_cmd);
4183122d 279 if (!tag) {
99bc5d55
JSJ		 280 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
281 "BM_%d : mgmt_invalidate_icds could not be"
282 "submitted\n");
3cbb7a74
JK		 283 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
284 nonemb_cmd.va, nonemb_cmd.dma);
285
4183122d 286 return FAILED;
4183122d 287 }
e175defe 288
88840332 289 rc = beiscsi_mccq_compl_wait(phba, tag, NULL, &nonemb_cmd);
1957aa7f
JK		 290 if (rc != -EBUSY)
291 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
292 nonemb_cmd.va, nonemb_cmd.dma);
293
4183122d
JK		 294 return iscsi_eh_abort(sc);
295}
296
297static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
298{
299 struct iscsi_task *abrt_task;
300 struct beiscsi_io_task *abrt_io_task;
301 struct iscsi_conn *conn;
302 struct beiscsi_conn *beiscsi_conn;
303 struct beiscsi_hba *phba;
304 struct iscsi_session *session;
305 struct iscsi_cls_session *cls_session;
306 struct invalidate_command_table *inv_tbl;
3cbb7a74 307 struct be_dma_mem nonemb_cmd;
4183122d 308 unsigned int cid, tag, i, num_invalidate;
1957aa7f 309 int rc;
4183122d
JK		 310
311 /* invalidate iocbs */
312 cls_session = starget_to_session(scsi_target(sc->device));
313 session = cls_session->dd_data;
659743b0 314 spin_lock_bh(&session->frwd_lock);
db7f7709 315 if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
659743b0 316 spin_unlock_bh(&session->frwd_lock);
db7f7709
JK		 317 return FAILED;
318 }
4183122d
JK		 319 conn = session->leadconn;
320 beiscsi_conn = conn->dd_data;
321 phba = beiscsi_conn->phba;
322 cid = beiscsi_conn->beiscsi_conn_cid;
323 inv_tbl = phba->inv_tbl;
324 memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
325 num_invalidate = 0;
326 for (i = 0; i < conn->session->cmds_max; i++) {
327 abrt_task = conn->session->cmds[i];
328 abrt_io_task = abrt_task->dd_data;
329 if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
330 continue;
331
126e964a 332 if (sc->device->lun != abrt_task->sc->device->lun)
4183122d
JK		 333 continue;
334
7626c06b
JK		 335 /* Invalidate WRB Posted for this Task */
336 AMAP_SET_BITS(struct amap_iscsi_wrb, invld,
337 abrt_io_task->pwrb_handle->pwrb,
338 1);
339
4183122d
JK		 340 inv_tbl->cid = cid;
341 inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
342 num_invalidate++;
343 inv_tbl++;
344 }
659743b0 345 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 346 inv_tbl = phba->inv_tbl;
347
3cbb7a74
JK		 348 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
349 sizeof(struct invalidate_commands_params_in),
350 &nonemb_cmd.dma);
351 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 352 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
353 "BM_%d : Failed to allocate memory for"
354 "mgmt_invalidate_icds\n");
3cbb7a74
JK		 355 return FAILED;
356 }
357 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
358 memset(nonemb_cmd.va, 0, nonemb_cmd.size);
359 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
360 cid, &nonemb_cmd);
4183122d 361 if (!tag) {
99bc5d55
JSJ		 362 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
363 "BM_%d : mgmt_invalidate_icds could not be"
364 " submitted\n");
3cbb7a74
JK		 365 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
366 nonemb_cmd.va, nonemb_cmd.dma);
4183122d 367 return FAILED;
4183122d 368 }
e175defe 369
88840332 370 rc = beiscsi_mccq_compl_wait(phba, tag, NULL, &nonemb_cmd);
1957aa7f
JK		 371 if (rc != -EBUSY)
372 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
373 nonemb_cmd.va, nonemb_cmd.dma);
4183122d 374 return iscsi_eh_device_reset(sc);
4183122d
JK		 375}
376
c7acc5b8
JK		 377static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
378{
379 struct beiscsi_hba *phba = data;
f457a46f
MC		 380 struct mgmt_session_info *boot_sess = &phba->boot_sess;
381 struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
c7acc5b8 382 char *str = buf;
c5bf8889 383 int rc = -EPERM;
c7acc5b8
JK		 384
385 switch (type) {
386 case ISCSI_BOOT_TGT_NAME:
387 rc = sprintf(buf, "%.*s\n",
f457a46f
MC		 388 (int)strlen(boot_sess->target_name),
389 (char *)&boot_sess->target_name);
c7acc5b8
JK		 390 break;
391 case ISCSI_BOOT_TGT_IP_ADDR:
290aa376 392 if (boot_conn->dest_ipaddr.ip_type == BEISCSI_IP_TYPE_V4)
c7acc5b8 393 rc = sprintf(buf, "%pI4\n",
0e43895e 394 (char *)&boot_conn->dest_ipaddr.addr);
c7acc5b8
JK		 395 else
396 rc = sprintf(str, "%pI6\n",
0e43895e 397 (char *)&boot_conn->dest_ipaddr.addr);
c7acc5b8
JK		 398 break;
399 case ISCSI_BOOT_TGT_PORT:
f457a46f 400 rc = sprintf(str, "%d\n", boot_conn->dest_port);
c7acc5b8
JK		 401 break;
402
403 case ISCSI_BOOT_TGT_CHAP_NAME:
404 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 405 boot_conn->negotiated_login_options.auth_data.chap.
406 target_chap_name_length,
407 (char *)&boot_conn->negotiated_login_options.
408 auth_data.chap.target_chap_name);
c7acc5b8
JK		 409 break;
410 case ISCSI_BOOT_TGT_CHAP_SECRET:
411 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 412 boot_conn->negotiated_login_options.auth_data.chap.
413 target_secret_length,
414 (char *)&boot_conn->negotiated_login_options.
415 auth_data.chap.target_secret);
c7acc5b8
JK		 416 break;
417 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
418 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 419 boot_conn->negotiated_login_options.auth_data.chap.
420 intr_chap_name_length,
421 (char *)&boot_conn->negotiated_login_options.
422 auth_data.chap.intr_chap_name);
c7acc5b8
JK		 423 break;
424 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
f457a46f
MC		 425 rc = sprintf(str, "%.*s\n",
426 boot_conn->negotiated_login_options.auth_data.chap.
427 intr_secret_length,
428 (char *)&boot_conn->negotiated_login_options.
429 auth_data.chap.intr_secret);
c7acc5b8
JK		 430 break;
431 case ISCSI_BOOT_TGT_FLAGS:
f457a46f 432 rc = sprintf(str, "2\n");
c7acc5b8
JK		 433 break;
434 case ISCSI_BOOT_TGT_NIC_ASSOC:
f457a46f 435 rc = sprintf(str, "0\n");
c7acc5b8 436 break;
c7acc5b8
JK		 437 }
438 return rc;
439}
440
441static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
442{
443 struct beiscsi_hba *phba = data;
444 char *str = buf;
c5bf8889 445 int rc = -EPERM;
c7acc5b8
JK		 446
447 switch (type) {
448 case ISCSI_BOOT_INI_INITIATOR_NAME:
449 rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
450 break;
c7acc5b8
JK		 451 }
452 return rc;
453}
454
455static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
456{
457 struct beiscsi_hba *phba = data;
458 char *str = buf;
c5bf8889 459 int rc = -EPERM;
c7acc5b8
JK		 460
461 switch (type) {
462 case ISCSI_BOOT_ETH_FLAGS:
f457a46f 463 rc = sprintf(str, "2\n");
c7acc5b8
JK		 464 break;
465 case ISCSI_BOOT_ETH_INDEX:
f457a46f 466 rc = sprintf(str, "0\n");
c7acc5b8
JK		 467 break;
468 case ISCSI_BOOT_ETH_MAC:
0e43895e
MC		 469 rc = beiscsi_get_macaddr(str, phba);
470 break;
c7acc5b8
JK		 471 }
472 return rc;
473}
474
475
587a1f16 476static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
c7acc5b8 477{
c5bf8889 478 umode_t rc = 0;
c7acc5b8
JK		 479
480 switch (type) {
481 case ISCSI_BOOT_TGT_NAME:
482 case ISCSI_BOOT_TGT_IP_ADDR:
483 case ISCSI_BOOT_TGT_PORT:
484 case ISCSI_BOOT_TGT_CHAP_NAME:
485 case ISCSI_BOOT_TGT_CHAP_SECRET:
486 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
487 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
488 case ISCSI_BOOT_TGT_NIC_ASSOC:
489 case ISCSI_BOOT_TGT_FLAGS:
490 rc = S_IRUGO;
491 break;
c7acc5b8
JK		 492 }
493 return rc;
494}
495
587a1f16 496static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
c7acc5b8 497{
c5bf8889 498 umode_t rc = 0;
c7acc5b8
JK		 499
500 switch (type) {
501 case ISCSI_BOOT_INI_INITIATOR_NAME:
502 rc = S_IRUGO;
503 break;
c7acc5b8
JK		 504 }
505 return rc;
506}
507
508
587a1f16 509static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
c7acc5b8 510{
c5bf8889 511 umode_t rc = 0;
c7acc5b8
JK		 512
513 switch (type) {
514 case ISCSI_BOOT_ETH_FLAGS:
515 case ISCSI_BOOT_ETH_MAC:
516 case ISCSI_BOOT_ETH_INDEX:
517 rc = S_IRUGO;
518 break;
c7acc5b8
JK		 519 }
520 return rc;
521}
522
bfead3b2 523/*------------------- PCI Driver operations and data ----------------- */
9baa3c34 524static const struct pci_device_id beiscsi_pci_id_table[] = {
bfead3b2 525 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
f98c96b0 526 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
bfead3b2
JK		 527 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
528 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
529 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
139a1b1e 530 { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
bfead3b2
JK		 531 { 0 }
532};
533MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
534
99bc5d55 535
6733b39a
JK		 536static struct scsi_host_template beiscsi_sht = {
537 .module = THIS_MODULE,
c4f39bda 538 .name = "Emulex 10Gbe open-iscsi Initiator Driver",
6733b39a
JK		 539 .proc_name = DRV_NAME,
540 .queuecommand = iscsi_queuecommand,
db5ed4df 541 .change_queue_depth = scsi_change_queue_depth,
6733b39a
JK		 542 .slave_configure = beiscsi_slave_configure,
543 .target_alloc = iscsi_target_alloc,
4183122d
JK		 544 .eh_abort_handler = beiscsi_eh_abort,
545 .eh_device_reset_handler = beiscsi_eh_device_reset,
309ce156 546 .eh_target_reset_handler = iscsi_eh_session_reset,
99bc5d55 547 .shost_attrs = beiscsi_attrs,
6733b39a
JK		 548 .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
549 .can_queue = BE2_IO_DEPTH,
550 .this_id = -1,
551 .max_sectors = BEISCSI_MAX_SECTORS,
552 .cmd_per_lun = BEISCSI_CMD_PER_LUN,
553 .use_clustering = ENABLE_CLUSTERING,
ffce3e2e 554 .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
c40ecc12 555 .track_queue_depth = 1,
6733b39a 556};
6733b39a 557
bfead3b2 558static struct scsi_transport_template *beiscsi_scsi_transport;
6733b39a
JK		 559
560static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
561{
562 struct beiscsi_hba *phba;
563 struct Scsi_Host *shost;
564
565 shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
566 if (!shost) {
99bc5d55
JSJ		 567 dev_err(&pcidev->dev,
568 "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
6733b39a
JK		 569 return NULL;
570 }
6733b39a
JK		 571 shost->max_id = BE2_MAX_SESSIONS;
572 shost->max_channel = 0;
573 shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
574 shost->max_lun = BEISCSI_NUM_MAX_LUN;
575 shost->transportt = beiscsi_scsi_transport;
6733b39a
JK		 576 phba = iscsi_host_priv(shost);
577 memset(phba, 0, sizeof(*phba));
578 phba->shost = shost;
579 phba->pcidev = pci_dev_get(pcidev);
2807afb7 580 pci_set_drvdata(pcidev, phba);
0e43895e 581 phba->interface_handle = 0xFFFFFFFF;
6733b39a 582
6733b39a 583 return phba;
6733b39a
JK		 584}
585
586static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
587{
588 if (phba->csr_va) {
589 iounmap(phba->csr_va);
590 phba->csr_va = NULL;
591 }
592 if (phba->db_va) {
593 iounmap(phba->db_va);
594 phba->db_va = NULL;
595 }
596 if (phba->pci_va) {
597 iounmap(phba->pci_va);
598 phba->pci_va = NULL;
599 }
600}
601
602static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
603 struct pci_dev *pcidev)
604{
605 u8 __iomem *addr;
f98c96b0 606 int pcicfg_reg;
6733b39a
JK		 607
608 addr = ioremap_nocache(pci_resource_start(pcidev, 2),
609 pci_resource_len(pcidev, 2));
610 if (addr == NULL)
611 return -ENOMEM;
612 phba->ctrl.csr = addr;
613 phba->csr_va = addr;
614 phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
615
616 addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
617 if (addr == NULL)
618 goto pci_map_err;
619 phba->ctrl.db = addr;
620 phba->db_va = addr;
621 phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
622
f98c96b0
JK		 623 if (phba->generation == BE_GEN2)
624 pcicfg_reg = 1;
625 else
626 pcicfg_reg = 0;
627
628 addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
629 pci_resource_len(pcidev, pcicfg_reg));
630
6733b39a
JK		 631 if (addr == NULL)
632 goto pci_map_err;
633 phba->ctrl.pcicfg = addr;
634 phba->pci_va = addr;
f98c96b0 635 phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
6733b39a
JK		 636 return 0;
637
638pci_map_err:
639 beiscsi_unmap_pci_function(phba);
640 return -ENOMEM;
641}
642
643static int beiscsi_enable_pci(struct pci_dev *pcidev)
644{
645 int ret;
646
647 ret = pci_enable_device(pcidev);
648 if (ret) {
99bc5d55
JSJ		 649 dev_err(&pcidev->dev,
650 "beiscsi_enable_pci - enable device failed\n");
6733b39a
JK		 651 return ret;
652 }
653
e307f3ac
JSJ		 654 ret = pci_request_regions(pcidev, DRV_NAME);
655 if (ret) {
656 dev_err(&pcidev->dev,
657 "beiscsi_enable_pci - request region failed\n");
658 goto pci_dev_disable;
659 }
660
bfead3b2 661 pci_set_master(pcidev);
6c57625b
JK		 662 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64));
663 if (ret) {
664 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
665 if (ret) {
666 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
e307f3ac 667 goto pci_region_release;
6c57625b
JK		 668 } else {
669 ret = pci_set_consistent_dma_mask(pcidev,
670 DMA_BIT_MASK(32));
671 }
672 } else {
673 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
6733b39a
JK		 674 if (ret) {
675 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
e307f3ac 676 goto pci_region_release;
6733b39a
JK		 677 }
678 }
679 return 0;
e307f3ac
JSJ		 680
681pci_region_release:
682 pci_release_regions(pcidev);
683pci_dev_disable:
684 pci_disable_device(pcidev);
685
686 return ret;
6733b39a
JK		 687}
688
689static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
690{
691 struct be_ctrl_info *ctrl = &phba->ctrl;
692 struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
693 struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
694 int status = 0;
695
696 ctrl->pdev = pdev;
697 status = beiscsi_map_pci_bars(phba, pdev);
698 if (status)
699 return status;
6733b39a
JK		 700 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
701 mbox_mem_alloc->va = pci_alloc_consistent(pdev,
702 mbox_mem_alloc->size,
703 &mbox_mem_alloc->dma);
704 if (!mbox_mem_alloc->va) {
705 beiscsi_unmap_pci_function(phba);
a49e06d5 706 return -ENOMEM;
6733b39a
JK		 707 }
708
709 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
710 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
711 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
712 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
c03a50f7 713 mutex_init(&ctrl->mbox_lock);
bfead3b2 714 spin_lock_init(&phba->ctrl.mcc_lock);
bfead3b2 715
6733b39a
JK		 716 return status;
717}
718
843ae752
JK		 719/**
720 * beiscsi_get_params()- Set the config paramters
721 * @phba: ptr device priv structure
722 **/
6733b39a
JK		 723static void beiscsi_get_params(struct beiscsi_hba *phba)
724{
843ae752
JK		 725 uint32_t total_cid_count = 0;
726 uint32_t total_icd_count = 0;
727 uint8_t ulp_num = 0;
728
729 total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) +
730 BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1);
731
cf987b79
JK		 732 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
733 uint32_t align_mask = 0;
734 uint32_t icd_post_per_page = 0;
735 uint32_t icd_count_unavailable = 0;
736 uint32_t icd_start = 0, icd_count = 0;
737 uint32_t icd_start_align = 0, icd_count_align = 0;
738
843ae752 739 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
cf987b79
JK		 740 icd_start = phba->fw_config.iscsi_icd_start[ulp_num];
741 icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
742
743 /* Get ICD count that can be posted on each page */
744 icd_post_per_page = (PAGE_SIZE / (BE2_SGE *
745 sizeof(struct iscsi_sge)));
746 align_mask = (icd_post_per_page - 1);
747
748 /* Check if icd_start is aligned ICD per page posting */
749 if (icd_start % icd_post_per_page) {
750 icd_start_align = ((icd_start +
751 icd_post_per_page) &
752 ~(align_mask));
753 phba->fw_config.
754 iscsi_icd_start[ulp_num] =
755 icd_start_align;
756 }
757
758 icd_count_align = (icd_count & ~align_mask);
759
760 /* ICD discarded in the process of alignment */
761 if (icd_start_align)
762 icd_count_unavailable = ((icd_start_align -
763 icd_start) +
764 (icd_count -
765 icd_count_align));
766
767 /* Updated ICD count available */
768 phba->fw_config.iscsi_icd_count[ulp_num] = (icd_count -
769 icd_count_unavailable);
770
771 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
772 "BM_%d : Aligned ICD values\n"
773 "\t ICD Start : %d\n"
774 "\t ICD Count : %d\n"
775 "\t ICD Discarded : %d\n",
776 phba->fw_config.
777 iscsi_icd_start[ulp_num],
778 phba->fw_config.
779 iscsi_icd_count[ulp_num],
780 icd_count_unavailable);
843ae752
JK		 781 break;
782 }
cf987b79 783 }
843ae752 784
cf987b79 785 total_icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
843ae752
JK		 786 phba->params.ios_per_ctrl = (total_icd_count -
787 (total_cid_count +
788 BE2_TMFS + BE2_NOPOUT_REQ));
789 phba->params.cxns_per_ctrl = total_cid_count;
790 phba->params.asyncpdus_per_ctrl = total_cid_count;
791 phba->params.icds_per_ctrl = total_icd_count;
6733b39a
JK		 792 phba->params.num_sge_per_io = BE2_SGE;
793 phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
794 phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
795 phba->params.eq_timer = 64;
843ae752
JK		 796 phba->params.num_eq_entries = 1024;
797 phba->params.num_cq_entries = 1024;
6733b39a
JK		 798 phba->params.wrbs_per_cxn = 256;
799}
800
801static void hwi_ring_eq_db(struct beiscsi_hba *phba,
802 unsigned int id, unsigned int clr_interrupt,
803 unsigned int num_processed,
804 unsigned char rearm, unsigned char event)
805{
806 u32 val = 0;
e08b3c8b 807
6733b39a
JK		 808 if (rearm)
809 val |= 1 << DB_EQ_REARM_SHIFT;
810 if (clr_interrupt)
811 val |= 1 << DB_EQ_CLR_SHIFT;
812 if (event)
813 val |= 1 << DB_EQ_EVNT_SHIFT;
e08b3c8b 814
6733b39a 815 val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
e08b3c8b
JK		 816 /* Setting lower order EQ_ID Bits */
817 val |= (id & DB_EQ_RING_ID_LOW_MASK);
818
819 /* Setting Higher order EQ_ID Bits */
820 val |= (((id >> DB_EQ_HIGH_FEILD_SHIFT) &
821 DB_EQ_RING_ID_HIGH_MASK)
822 << DB_EQ_HIGH_SET_SHIFT);
823
6733b39a
JK		 824 iowrite32(val, phba->db_va + DB_EQ_OFFSET);
825}
826
bfead3b2
JK		 827/**
828 * be_isr_mcc - The isr routine of the driver.
829 * @irq: Not used
830 * @dev_id: Pointer to host adapter structure
831 */
832static irqreturn_t be_isr_mcc(int irq, void *dev_id)
833{
834 struct beiscsi_hba *phba;
a3095016 835 struct be_eq_entry *eqe;
bfead3b2
JK		 836 struct be_queue_info *eq;
837 struct be_queue_info *mcc;
a3095016 838 unsigned int mcc_events;
bfead3b2 839 struct be_eq_obj *pbe_eq;
bfead3b2
JK		 840
841 pbe_eq = dev_id;
842 eq = &pbe_eq->q;
843 phba = pbe_eq->phba;
844 mcc = &phba->ctrl.mcc_obj.cq;
845 eqe = queue_tail_node(eq);
bfead3b2 846
a3095016 847 mcc_events = 0;
bfead3b2
JK		 848 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
849 & EQE_VALID_MASK) {
850 if (((eqe->dw[offsetof(struct amap_eq_entry,
851 resource_id) / 32] &
852 EQE_RESID_MASK) >> 16) == mcc->id) {
a3095016 853 mcc_events++;
bfead3b2
JK		 854 }
855 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
856 queue_tail_inc(eq);
857 eqe = queue_tail_node(eq);
bfead3b2 858 }
bfead3b2 859
a3095016
JB		 860 if (mcc_events) {
861 queue_work(phba->wq, &pbe_eq->mcc_work);
862 hwi_ring_eq_db(phba, eq->id, 1, mcc_events, 1, 1);
863 }
bfead3b2
JK		 864 return IRQ_HANDLED;
865}
866
867/**
868 * be_isr_msix - The isr routine of the driver.
869 * @irq: Not used
870 * @dev_id: Pointer to host adapter structure
871 */
872static irqreturn_t be_isr_msix(int irq, void *dev_id)
873{
874 struct beiscsi_hba *phba;
bfead3b2 875 struct be_queue_info *eq;
bfead3b2 876 struct be_eq_obj *pbe_eq;
bfead3b2
JK		 877
878 pbe_eq = dev_id;
879 eq = &pbe_eq->q;
bfead3b2
JK		 880
881 phba = pbe_eq->phba;
1094cf68
JB		 882 /* disable interrupt till iopoll completes */
883 hwi_ring_eq_db(phba, eq->id, 1, 0, 0, 1);
884 irq_poll_sched(&pbe_eq->iopoll);
72fb46a9
JSJ		 885
886 return IRQ_HANDLED;
bfead3b2
JK		 887}
888
6733b39a
JK		 889/**
890 * be_isr - The isr routine of the driver.
891 * @irq: Not used
892 * @dev_id: Pointer to host adapter structure
893 */
894static irqreturn_t be_isr(int irq, void *dev_id)
895{
896 struct beiscsi_hba *phba;
897 struct hwi_controller *phwi_ctrlr;
898 struct hwi_context_memory *phwi_context;
a3095016 899 struct be_eq_entry *eqe;
6733b39a 900 struct be_queue_info *eq;
bfead3b2 901 struct be_queue_info *mcc;
a3095016 902 unsigned int mcc_events, io_events;
6733b39a 903 struct be_ctrl_info *ctrl;
bfead3b2 904 struct be_eq_obj *pbe_eq;
a3095016 905 int isr, rearm;
6733b39a
JK		 906
907 phba = dev_id;
6eab04a8 908 ctrl = &phba->ctrl;
bfead3b2
JK		 909 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
910 (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
911 if (!isr)
912 return IRQ_NONE;
6733b39a
JK		 913
914 phwi_ctrlr = phba->phwi_ctrlr;
915 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 916 pbe_eq = &phwi_context->be_eq[0];
917
918 eq = &phwi_context->be_eq[0].q;
919 mcc = &phba->ctrl.mcc_obj.cq;
6733b39a 920 eqe = queue_tail_node(eq);
6733b39a 921
a3095016
JB		 922 io_events = 0;
923 mcc_events = 0;
89f8b33c
JA		 924 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
925 & EQE_VALID_MASK) {
926 if (((eqe->dw[offsetof(struct amap_eq_entry,
a3095016
JB		 927 resource_id) / 32] & EQE_RESID_MASK) >> 16) == mcc->id)
928 mcc_events++;
929 else
930 io_events++;
89f8b33c
JA		 931 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
932 queue_tail_inc(eq);
933 eqe = queue_tail_node(eq);
934 }
a3095016 935 if (!io_events && !mcc_events)
89f8b33c 936 return IRQ_NONE;
a3095016
JB		 937
938 /* no need to rearm if interrupt is only for IOs */
939 rearm = 0;
940 if (mcc_events) {
941 queue_work(phba->wq, &pbe_eq->mcc_work);
942 /* rearm for MCCQ */
943 rearm = 1;
944 }
945 if (io_events)
946 irq_poll_sched(&pbe_eq->iopoll);
947 hwi_ring_eq_db(phba, eq->id, 0, (io_events + mcc_events), rearm, 1);
948 return IRQ_HANDLED;
6733b39a
JK		 949}
950
1094cf68 951
6733b39a
JK		 952static int beiscsi_init_irqs(struct beiscsi_hba *phba)
953{
954 struct pci_dev *pcidev = phba->pcidev;
bfead3b2
JK		 955 struct hwi_controller *phwi_ctrlr;
956 struct hwi_context_memory *phwi_context;
4f5af07e 957 int ret, msix_vec, i, j;
6733b39a 958
bfead3b2
JK		 959 phwi_ctrlr = phba->phwi_ctrlr;
960 phwi_context = phwi_ctrlr->phwi_ctxt;
961
962 if (phba->msix_enabled) {
963 for (i = 0; i < phba->num_cpus; i++) {
8fcfb210
JK		 964 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
965 GFP_KERNEL);
966 if (!phba->msi_name[i]) {
967 ret = -ENOMEM;
968 goto free_msix_irqs;
969 }
970
971 sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
972 phba->shost->host_no, i);
bfead3b2 973 msix_vec = phba->msix_entries[i].vector;
8fcfb210
JK		 974 ret = request_irq(msix_vec, be_isr_msix, 0,
975 phba->msi_name[i],
bfead3b2 976 &phwi_context->be_eq[i]);
4f5af07e 977 if (ret) {
99bc5d55
JSJ		 978 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
979 "BM_%d : beiscsi_init_irqs-Failed to"
980 "register msix for i = %d\n",
981 i);
8fcfb210 982 kfree(phba->msi_name[i]);
4f5af07e
JK		 983 goto free_msix_irqs;
984 }
bfead3b2 985 }
8fcfb210
JK		 986 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
987 if (!phba->msi_name[i]) {
988 ret = -ENOMEM;
989 goto free_msix_irqs;
990 }
991 sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
992 phba->shost->host_no);
bfead3b2 993 msix_vec = phba->msix_entries[i].vector;
8fcfb210 994 ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
bfead3b2 995 &phwi_context->be_eq[i]);
4f5af07e 996 if (ret) {
99bc5d55
JSJ		 997 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
998 "BM_%d : beiscsi_init_irqs-"
999 "Failed to register beiscsi_msix_mcc\n");
8fcfb210 1000 kfree(phba->msi_name[i]);
4f5af07e
JK		 1001 goto free_msix_irqs;
1002 }
1003
bfead3b2
JK		 1004 } else {
1005 ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
1006 "beiscsi", phba);
1007 if (ret) {
99bc5d55
JSJ		 1008 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1009 "BM_%d : beiscsi_init_irqs-"
1010 "Failed to register irq\\n");
bfead3b2
JK		 1011 return ret;
1012 }
6733b39a
JK		 1013 }
1014 return 0;
4f5af07e 1015free_msix_irqs:
8fcfb210
JK		 1016 for (j = i - 1; j >= 0; j--) {
1017 kfree(phba->msi_name[j]);
1018 msix_vec = phba->msix_entries[j].vector;
4f5af07e 1019 free_irq(msix_vec, &phwi_context->be_eq[j]);
8fcfb210 1020 }
4f5af07e 1021 return ret;
6733b39a
JK		 1022}
1023
e08b3c8b 1024void hwi_ring_cq_db(struct beiscsi_hba *phba,
6733b39a 1025 unsigned int id, unsigned int num_processed,
1094cf68 1026 unsigned char rearm)
6733b39a
JK		 1027{
1028 u32 val = 0;
e08b3c8b 1029
6733b39a
JK		 1030 if (rearm)
1031 val |= 1 << DB_CQ_REARM_SHIFT;
e08b3c8b 1032
6733b39a 1033 val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
e08b3c8b
JK		 1034
1035 /* Setting lower order CQ_ID Bits */
1036 val |= (id & DB_CQ_RING_ID_LOW_MASK);
1037
1038 /* Setting Higher order CQ_ID Bits */
1039 val |= (((id >> DB_CQ_HIGH_FEILD_SHIFT) &
1040 DB_CQ_RING_ID_HIGH_MASK)
1041 << DB_CQ_HIGH_SET_SHIFT);
1042
6733b39a
JK		 1043 iowrite32(val, phba->db_va + DB_CQ_OFFSET);
1044}
1045
6733b39a
JK		 1046static unsigned int
1047beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
1048 struct beiscsi_hba *phba,
6733b39a
JK		 1049 struct pdu_base *ppdu,
1050 unsigned long pdu_len,
1051 void *pbuffer, unsigned long buf_len)
1052{
1053 struct iscsi_conn *conn = beiscsi_conn->conn;
1054 struct iscsi_session *session = conn->session;
bfead3b2
JK		 1055 struct iscsi_task *task;
1056 struct beiscsi_io_task *io_task;
1057 struct iscsi_hdr *login_hdr;
6733b39a
JK		 1058
1059 switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
1060 PDUBASE_OPCODE_MASK) {
1061 case ISCSI_OP_NOOP_IN:
1062 pbuffer = NULL;
1063 buf_len = 0;
1064 break;
1065 case ISCSI_OP_ASYNC_EVENT:
1066 break;
1067 case ISCSI_OP_REJECT:
1068 WARN_ON(!pbuffer);
1069 WARN_ON(!(buf_len == 48));
99bc5d55
JSJ		 1070 beiscsi_log(phba, KERN_ERR,
1071 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1072 "BM_%d : In ISCSI_OP_REJECT\n");
6733b39a
JK		 1073 break;
1074 case ISCSI_OP_LOGIN_RSP:
7bd6e25c 1075 case ISCSI_OP_TEXT_RSP:
bfead3b2
JK		 1076 task = conn->login_task;
1077 io_task = task->dd_data;
1078 login_hdr = (struct iscsi_hdr *)ppdu;
1079 login_hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1080 break;
1081 default:
99bc5d55
JSJ		 1082 beiscsi_log(phba, KERN_WARNING,
1083 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1084 "BM_%d : Unrecognized opcode 0x%x in async msg\n",
1085 (ppdu->
6733b39a 1086 dw[offsetof(struct amap_pdu_base, opcode) / 32]
99bc5d55 1087 & PDUBASE_OPCODE_MASK));
6733b39a
JK		 1088 return 1;
1089 }
1090
659743b0 1091 spin_lock_bh(&session->back_lock);
6733b39a 1092 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
659743b0 1093 spin_unlock_bh(&session->back_lock);
6733b39a
JK		 1094 return 0;
1095}
1096
1097static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
1098{
1099 struct sgl_handle *psgl_handle;
1100
10139fe0 1101 spin_lock_bh(&phba->io_sgl_lock);
6733b39a 1102 if (phba->io_sgl_hndl_avbl) {
99bc5d55
JSJ		 1103 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
1104 "BM_%d : In alloc_io_sgl_handle,"
1105 " io_sgl_alloc_index=%d\n",
1106 phba->io_sgl_alloc_index);
1107
6733b39a
JK		 1108 psgl_handle = phba->io_sgl_hndl_base[phba->
1109 io_sgl_alloc_index];
1110 phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
1111 phba->io_sgl_hndl_avbl--;
bfead3b2
JK		 1112 if (phba->io_sgl_alloc_index == (phba->params.
1113 ios_per_ctrl - 1))
6733b39a
JK		 1114 phba->io_sgl_alloc_index = 0;
1115 else
1116 phba->io_sgl_alloc_index++;
1117 } else
1118 psgl_handle = NULL;
10139fe0 1119 spin_unlock_bh(&phba->io_sgl_lock);
6733b39a
JK		 1120 return psgl_handle;
1121}
1122
1123static void
1124free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
1125{
10139fe0 1126 spin_lock_bh(&phba->io_sgl_lock);
99bc5d55
JSJ		 1127 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
1128 "BM_%d : In free_,io_sgl_free_index=%d\n",
1129 phba->io_sgl_free_index);
1130
6733b39a
JK		 1131 if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
1132 /*
1133 * this can happen if clean_task is called on a task that
1134 * failed in xmit_task or alloc_pdu.
1135 */
99bc5d55
JSJ		 1136 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
1137 "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
1138 "value there=%p\n", phba->io_sgl_free_index,
1139 phba->io_sgl_hndl_base
1140 [phba->io_sgl_free_index]);
10139fe0 1141 spin_unlock_bh(&phba->io_sgl_lock);
6733b39a
JK		 1142 return;
1143 }
1144 phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
1145 phba->io_sgl_hndl_avbl++;
1146 if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
1147 phba->io_sgl_free_index = 0;
1148 else
1149 phba->io_sgl_free_index++;
10139fe0 1150 spin_unlock_bh(&phba->io_sgl_lock);
6733b39a
JK		 1151}
1152
cb564c6b
JB		 1153static inline struct wrb_handle *
1154beiscsi_get_wrb_handle(struct hwi_wrb_context *pwrb_context,
1155 unsigned int wrbs_per_cxn)
1156{
1157 struct wrb_handle *pwrb_handle;
1158
f64d92e6 1159 spin_lock_bh(&pwrb_context->wrb_lock);
cb564c6b
JB		 1160 pwrb_handle = pwrb_context->pwrb_handle_base[pwrb_context->alloc_index];
1161 pwrb_context->wrb_handles_available--;
1162 if (pwrb_context->alloc_index == (wrbs_per_cxn - 1))
1163 pwrb_context->alloc_index = 0;
1164 else
1165 pwrb_context->alloc_index++;
f64d92e6 1166 spin_unlock_bh(&pwrb_context->wrb_lock);
cb564c6b
JB		 1167
1168 return pwrb_handle;
1169}
1170
6733b39a
JK		 1171/**
1172 * alloc_wrb_handle - To allocate a wrb handle
1173 * @phba: The hba pointer
1174 * @cid: The cid to use for allocation
340c99e9 1175 * @pwrb_context: ptr to ptr to wrb context
6733b39a
JK		 1176 *
1177 * This happens under session_lock until submission to chip
1178 */
340c99e9 1179struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
cb564c6b 1180 struct hwi_wrb_context **pcontext)
6733b39a
JK		 1181{
1182 struct hwi_wrb_context *pwrb_context;
1183 struct hwi_controller *phwi_ctrlr;
a7909b39 1184 uint16_t cri_index = BE_GET_CRI_FROM_CID(cid);
6733b39a
JK		 1185
1186 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 1187 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
cb564c6b
JB		 1188 /* return the context address */
1189 *pcontext = pwrb_context;
1190 return beiscsi_get_wrb_handle(pwrb_context, phba->params.wrbs_per_cxn);
1191}
340c99e9 1192
cb564c6b
JB		 1193static inline void
1194beiscsi_put_wrb_handle(struct hwi_wrb_context *pwrb_context,
1195 struct wrb_handle *pwrb_handle,
1196 unsigned int wrbs_per_cxn)
1197{
f64d92e6 1198 spin_lock_bh(&pwrb_context->wrb_lock);
cb564c6b
JB		 1199 pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
1200 pwrb_context->wrb_handles_available++;
1201 if (pwrb_context->free_index == (wrbs_per_cxn - 1))
1202 pwrb_context->free_index = 0;
1203 else
1204 pwrb_context->free_index++;
f64d92e6 1205 spin_unlock_bh(&pwrb_context->wrb_lock);
6733b39a
JK		 1206}
1207
1208/**
1209 * free_wrb_handle - To free the wrb handle back to pool
1210 * @phba: The hba pointer
1211 * @pwrb_context: The context to free from
1212 * @pwrb_handle: The wrb_handle to free
1213 *
1214 * This happens under session_lock until submission to chip
1215 */
1216static void
1217free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
1218 struct wrb_handle *pwrb_handle)
1219{
cb564c6b
JB		 1220 beiscsi_put_wrb_handle(pwrb_context,
1221 pwrb_handle,
1222 phba->params.wrbs_per_cxn);
99bc5d55
JSJ		 1223 beiscsi_log(phba, KERN_INFO,
1224 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1225 "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
1226 "wrb_handles_available=%d\n",
1227 pwrb_handle, pwrb_context->free_index,
1228 pwrb_context->wrb_handles_available);
6733b39a
JK		 1229}
1230
1231static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
1232{
1233 struct sgl_handle *psgl_handle;
1234
10139fe0 1235 spin_lock_bh(&phba->mgmt_sgl_lock);
6733b39a
JK		 1236 if (phba->eh_sgl_hndl_avbl) {
1237 psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
1238 phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
99bc5d55
JSJ		 1239 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
1240 "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
1241 phba->eh_sgl_alloc_index,
1242 phba->eh_sgl_alloc_index);
1243
6733b39a
JK		 1244 phba->eh_sgl_hndl_avbl--;
1245 if (phba->eh_sgl_alloc_index ==
1246 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
1247 1))
1248 phba->eh_sgl_alloc_index = 0;
1249 else
1250 phba->eh_sgl_alloc_index++;
1251 } else
1252 psgl_handle = NULL;
10139fe0 1253 spin_unlock_bh(&phba->mgmt_sgl_lock);
6733b39a
JK		 1254 return psgl_handle;
1255}
1256
1257void
1258free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
1259{
10139fe0 1260 spin_lock_bh(&phba->mgmt_sgl_lock);
99bc5d55
JSJ		 1261 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
1262 "BM_%d : In free_mgmt_sgl_handle,"
1263 "eh_sgl_free_index=%d\n",
1264 phba->eh_sgl_free_index);
1265
6733b39a
JK		 1266 if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
1267 /*
1268 * this can happen if clean_task is called on a task that
1269 * failed in xmit_task or alloc_pdu.
1270 */
99bc5d55
JSJ		 1271 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
1272 "BM_%d : Double Free in eh SGL ,"
1273 "eh_sgl_free_index=%d\n",
1274 phba->eh_sgl_free_index);
10139fe0 1275 spin_unlock_bh(&phba->mgmt_sgl_lock);
6733b39a
JK		 1276 return;
1277 }
1278 phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
1279 phba->eh_sgl_hndl_avbl++;
1280 if (phba->eh_sgl_free_index ==
1281 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
1282 phba->eh_sgl_free_index = 0;
1283 else
1284 phba->eh_sgl_free_index++;
10139fe0 1285 spin_unlock_bh(&phba->mgmt_sgl_lock);
6733b39a
JK		 1286}
1287
1288static void
1289be_complete_io(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1290 struct iscsi_task *task,
1291 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1292{
1293 struct beiscsi_io_task *io_task = task->dd_data;
1294 struct be_status_bhs *sts_bhs =
1295 (struct be_status_bhs *)io_task->cmd_bhs;
1296 struct iscsi_conn *conn = beiscsi_conn->conn;
6733b39a
JK		 1297 unsigned char *sense;
1298 u32 resid = 0, exp_cmdsn, max_cmdsn;
1299 u8 rsp, status, flags;
1300
73133261
JSJ		 1301 exp_cmdsn = csol_cqe->exp_cmdsn;
1302 max_cmdsn = (csol_cqe->exp_cmdsn +
1303 csol_cqe->cmd_wnd - 1);
1304 rsp = csol_cqe->i_resp;
1305 status = csol_cqe->i_sts;
1306 flags = csol_cqe->i_flags;
1307 resid = csol_cqe->res_cnt;
1308
bd535451 1309 if (!task->sc) {
da334977 1310 if (io_task->scsi_cmnd) {
bd535451 1311 scsi_dma_unmap(io_task->scsi_cmnd);
da334977
JK		 1312 io_task->scsi_cmnd = NULL;
1313 }
6733b39a 1314
bd535451
JK		 1315 return;
1316 }
6733b39a
JK		 1317 task->sc->result = (DID_OK << 16) | status;
1318 if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
1319 task->sc->result = DID_ERROR << 16;
1320 goto unmap;
1321 }
1322
1323 /* bidi not initially supported */
1324 if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
6733b39a
JK		 1325 if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
1326 task->sc->result = DID_ERROR << 16;
1327
1328 if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
1329 scsi_set_resid(task->sc, resid);
1330 if (!status && (scsi_bufflen(task->sc) - resid <
1331 task->sc->underflow))
1332 task->sc->result = DID_ERROR << 16;
1333 }
1334 }
1335
1336 if (status == SAM_STAT_CHECK_CONDITION) {
4053a4be 1337 u16 sense_len;
bfead3b2 1338 unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
4053a4be 1339
6733b39a 1340 sense = sts_bhs->sense_info + sizeof(unsigned short);
4053a4be 1341 sense_len = be16_to_cpu(*slen);
6733b39a
JK		 1342 memcpy(task->sc->sense_buffer, sense,
1343 min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
1344 }
756d29c8 1345
73133261
JSJ		 1346 if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ)
1347 conn->rxdata_octets += resid;
6733b39a 1348unmap:
eb1c4692
JSJ		 1349 if (io_task->scsi_cmnd) {
1350 scsi_dma_unmap(io_task->scsi_cmnd);
1351 io_task->scsi_cmnd = NULL;
1352 }
6733b39a
JK		 1353 iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
1354}
1355
1356static void
1357be_complete_logout(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1358 struct iscsi_task *task,
1359 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1360{
1361 struct iscsi_logout_rsp *hdr;
bfead3b2 1362 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1363 struct iscsi_conn *conn = beiscsi_conn->conn;
1364
1365 hdr = (struct iscsi_logout_rsp *)task->hdr;
7bd6e25c 1366 hdr->opcode = ISCSI_OP_LOGOUT_RSP;
6733b39a
JK		 1367 hdr->t2wait = 5;
1368 hdr->t2retain = 0;
73133261
JSJ		 1369 hdr->flags = csol_cqe->i_flags;
1370 hdr->response = csol_cqe->i_resp;
702dc5e8
JK		 1371 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
1372 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1373 csol_cqe->cmd_wnd - 1);
73133261 1374
7bd6e25c
JK		 1375 hdr->dlength[0] = 0;
1376 hdr->dlength[1] = 0;
1377 hdr->dlength[2] = 0;
6733b39a 1378 hdr->hlength = 0;
bfead3b2 1379 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1380 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1381}
1382
1383static void
1384be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1385 struct iscsi_task *task,
1386 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1387{
1388 struct iscsi_tm_rsp *hdr;
1389 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1390 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1391
1392 hdr = (struct iscsi_tm_rsp *)task->hdr;
7bd6e25c 1393 hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
73133261
JSJ		 1394 hdr->flags = csol_cqe->i_flags;
1395 hdr->response = csol_cqe->i_resp;
702dc5e8
JK		 1396 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
1397 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1398 csol_cqe->cmd_wnd - 1);
73133261 1399
bfead3b2 1400 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1401 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1402}
1403
1404static void
1405hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
1406 struct beiscsi_hba *phba, struct sol_cqe *psol)
1407{
1408 struct hwi_wrb_context *pwrb_context;
bfead3b2 1409 struct wrb_handle *pwrb_handle = NULL;
6733b39a 1410 struct hwi_controller *phwi_ctrlr;
bfead3b2
JK		 1411 struct iscsi_task *task;
1412 struct beiscsi_io_task *io_task;
a7909b39 1413 uint16_t wrb_index, cid, cri_index;
6733b39a
JK		 1414
1415 phwi_ctrlr = phba->phwi_ctrlr;
2c9dfd36
JK		 1416 if (is_chip_be2_be3r(phba)) {
1417 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
73133261 1418 wrb_idx, psol);
2c9dfd36 1419 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
73133261
JSJ		 1420 cid, psol);
1421 } else {
2c9dfd36 1422 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
73133261 1423 wrb_idx, psol);
2c9dfd36 1424 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
73133261
JSJ		 1425 cid, psol);
1426 }
1427
a7909b39
JK		 1428 cri_index = BE_GET_CRI_FROM_CID(cid);
1429 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
73133261 1430 pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index];
32951dd8 1431 task = pwrb_handle->pio_handle;
35e66019 1432
bfead3b2 1433 io_task = task->dd_data;
4a4a11b9
JK		 1434 memset(io_task->pwrb_handle->pwrb, 0, sizeof(struct iscsi_wrb));
1435 iscsi_put_task(task);
6733b39a
JK		 1436}
1437
1438static void
1439be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1440 struct iscsi_task *task,
1441 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1442{
1443 struct iscsi_nopin *hdr;
1444 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1445 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1446
1447 hdr = (struct iscsi_nopin *)task->hdr;
73133261
JSJ		 1448 hdr->flags = csol_cqe->i_flags;
1449 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
702dc5e8
JK		 1450 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1451 csol_cqe->cmd_wnd - 1);
73133261 1452
6733b39a 1453 hdr->opcode = ISCSI_OP_NOOP_IN;
bfead3b2 1454 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1455 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1456}
1457
73133261
JSJ		 1458static void adapter_get_sol_cqe(struct beiscsi_hba *phba,
1459 struct sol_cqe *psol,
1460 struct common_sol_cqe *csol_cqe)
1461{
2c9dfd36
JK		 1462 if (is_chip_be2_be3r(phba)) {
1463 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe,
1464 i_exp_cmd_sn, psol);
1465 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe,
1466 i_res_cnt, psol);
1467 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
1468 i_cmd_wnd, psol);
1469 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe,
1470 wrb_index, psol);
1471 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe,
1472 cid, psol);
1473 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe,
1474 hw_sts, psol);
1475 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe,
1476 i_resp, psol);
1477 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe,
1478 i_sts, psol);
1479 csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe,
1480 i_flags, psol);
1481 } else {
73133261
JSJ		 1482 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1483 i_exp_cmd_sn, psol);
1484 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1485 i_res_cnt, psol);
1486 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1487 wrb_index, psol);
1488 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1489 cid, psol);
1490 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1491 hw_sts, psol);
702dc5e8 1492 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2,
73133261
JSJ		 1493 i_cmd_wnd, psol);
1494 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1495 cmd_cmpl, psol))
1496 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1497 i_sts, psol);
1498 else
1499 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1500 i_sts, psol);
1501 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1502 u, psol))
1503 csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW;
1504
1505 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1506 o, psol))
1507 csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW;
73133261
JSJ		 1508 }
1509}
1510
1511
6733b39a
JK		 1512static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
1513 struct beiscsi_hba *phba, struct sol_cqe *psol)
1514{
1515 struct hwi_wrb_context *pwrb_context;
1516 struct wrb_handle *pwrb_handle;
1517 struct iscsi_wrb *pwrb = NULL;
1518 struct hwi_controller *phwi_ctrlr;
1519 struct iscsi_task *task;
bfead3b2 1520 unsigned int type;
6733b39a
JK		 1521 struct iscsi_conn *conn = beiscsi_conn->conn;
1522 struct iscsi_session *session = conn->session;
73133261 1523 struct common_sol_cqe csol_cqe = {0};
a7909b39 1524 uint16_t cri_index = 0;
6733b39a
JK		 1525
1526 phwi_ctrlr = phba->phwi_ctrlr;
73133261
JSJ		 1527
1528 /* Copy the elements to a common structure */
1529 adapter_get_sol_cqe(phba, psol, &csol_cqe);
1530
a7909b39
JK		 1531 cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid);
1532 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
73133261
JSJ		 1533
1534 pwrb_handle = pwrb_context->pwrb_handle_basestd[
1535 csol_cqe.wrb_index];
1536
32951dd8
JK		 1537 task = pwrb_handle->pio_handle;
1538 pwrb = pwrb_handle->pwrb;
73133261 1539 type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type;
32951dd8 1540
659743b0 1541 spin_lock_bh(&session->back_lock);
bfead3b2 1542 switch (type) {
6733b39a
JK		 1543 case HWH_TYPE_IO:
1544 case HWH_TYPE_IO_RD:
1545 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
dafab8e0 1546 ISCSI_OP_NOOP_OUT)
73133261 1547 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
dafab8e0 1548 else
73133261 1549 be_complete_io(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1550 break;
1551
1552 case HWH_TYPE_LOGOUT:
dafab8e0 1553 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
73133261 1554 be_complete_logout(beiscsi_conn, task, &csol_cqe);
dafab8e0 1555 else
73133261 1556 be_complete_tmf(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1557 break;
1558
1559 case HWH_TYPE_LOGIN:
99bc5d55
JSJ		 1560 beiscsi_log(phba, KERN_ERR,
1561 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1562 "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
1563 " hwi_complete_cmd- Solicited path\n");
6733b39a
JK		 1564 break;
1565
6733b39a 1566 case HWH_TYPE_NOP:
73133261 1567 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1568 break;
1569
1570 default:
99bc5d55
JSJ		 1571 beiscsi_log(phba, KERN_WARNING,
1572 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1573 "BM_%d : In hwi_complete_cmd, unknown type = %d"
1574 "wrb_index 0x%x CID 0x%x\n", type,
73133261
JSJ		 1575 csol_cqe.wrb_index,
1576 csol_cqe.cid);
6733b39a
JK		 1577 break;
1578 }
35e66019 1579
659743b0 1580 spin_unlock_bh(&session->back_lock);
6733b39a
JK		 1581}
1582
1583static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
1584 *pasync_ctx, unsigned int is_header,
1585 unsigned int host_write_ptr)
1586{
1587 if (is_header)
1588 return &pasync_ctx->async_entry[host_write_ptr].
1589 header_busy_list;
1590 else
1591 return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
1592}
1593
1594static struct async_pdu_handle *
1595hwi_get_async_handle(struct beiscsi_hba *phba,
1596 struct beiscsi_conn *beiscsi_conn,
1597 struct hwi_async_pdu_context *pasync_ctx,
1598 struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
1599{
1600 struct be_bus_address phys_addr;
1601 struct list_head *pbusy_list;
1602 struct async_pdu_handle *pasync_handle = NULL;
6733b39a 1603 unsigned char is_header = 0;
73133261
JSJ		 1604 unsigned int index, dpl;
1605
2c9dfd36
JK		 1606 if (is_chip_be2_be3r(phba)) {
1607 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
73133261 1608 dpl, pdpdu_cqe);
2c9dfd36 1609 index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
73133261
JSJ		 1610 index, pdpdu_cqe);
1611 } else {
2c9dfd36 1612 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
73133261 1613 dpl, pdpdu_cqe);
2c9dfd36 1614 index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
73133261
JSJ		 1615 index, pdpdu_cqe);
1616 }
6733b39a
JK		 1617
1618 phys_addr.u.a32.address_lo =
73133261
JSJ		 1619 (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1620 db_addr_lo) / 32] - dpl);
6733b39a 1621 phys_addr.u.a32.address_hi =
73133261
JSJ		 1622 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1623 db_addr_hi) / 32];
6733b39a
JK		 1624
1625 phys_addr.u.a64.address =
1626 *((unsigned long long *)(&phys_addr.u.a64.address));
1627
1628 switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
1629 & PDUCQE_CODE_MASK) {
1630 case UNSOL_HDR_NOTIFY:
1631 is_header = 1;
1632
73133261
JSJ		 1633 pbusy_list = hwi_get_async_busy_list(pasync_ctx,
1634 is_header, index);
6733b39a
JK		 1635 break;
1636 case UNSOL_DATA_NOTIFY:
73133261
JSJ		 1637 pbusy_list = hwi_get_async_busy_list(pasync_ctx,
1638 is_header, index);
6733b39a
JK		 1639 break;
1640 default:
1641 pbusy_list = NULL;
99bc5d55
JSJ		 1642 beiscsi_log(phba, KERN_WARNING,
1643 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1644 "BM_%d : Unexpected code=%d\n",
1645 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1646 code) / 32] & PDUCQE_CODE_MASK);
6733b39a
JK		 1647 return NULL;
1648 }
1649
6733b39a
JK		 1650 WARN_ON(list_empty(pbusy_list));
1651 list_for_each_entry(pasync_handle, pbusy_list, link) {
dc63aac6 1652 if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
6733b39a
JK		 1653 break;
1654 }
1655
1656 WARN_ON(!pasync_handle);
1657
8a86e833
JK		 1658 pasync_handle->cri = BE_GET_ASYNC_CRI_FROM_CID(
1659 beiscsi_conn->beiscsi_conn_cid);
6733b39a 1660 pasync_handle->is_header = is_header;
73133261
JSJ		 1661 pasync_handle->buffer_len = dpl;
1662 *pcq_index = index;
6733b39a 1663
6733b39a
JK		 1664 return pasync_handle;
1665}
1666
1667static unsigned int
99bc5d55
JSJ		 1668hwi_update_async_writables(struct beiscsi_hba *phba,
1669 struct hwi_async_pdu_context *pasync_ctx,
1670 unsigned int is_header, unsigned int cq_index)
6733b39a
JK		 1671{
1672 struct list_head *pbusy_list;
1673 struct async_pdu_handle *pasync_handle;
1674 unsigned int num_entries, writables = 0;
1675 unsigned int *pep_read_ptr, *pwritables;
1676
dc63aac6 1677 num_entries = pasync_ctx->num_entries;
6733b39a
JK		 1678 if (is_header) {
1679 pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
1680 pwritables = &pasync_ctx->async_header.writables;
6733b39a
JK		 1681 } else {
1682 pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
1683 pwritables = &pasync_ctx->async_data.writables;
6733b39a
JK		 1684 }
1685
1686 while ((*pep_read_ptr) != cq_index) {
1687 (*pep_read_ptr)++;
1688 *pep_read_ptr = (*pep_read_ptr) % num_entries;
1689
1690 pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
1691 *pep_read_ptr);
1692 if (writables == 0)
1693 WARN_ON(list_empty(pbusy_list));
1694
1695 if (!list_empty(pbusy_list)) {
1696 pasync_handle = list_entry(pbusy_list->next,
1697 struct async_pdu_handle,
1698 link);
1699 WARN_ON(!pasync_handle);
1700 pasync_handle->consumed = 1;
1701 }
1702
1703 writables++;
1704 }
1705
1706 if (!writables) {
99bc5d55
JSJ		 1707 beiscsi_log(phba, KERN_ERR,
1708 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1709 "BM_%d : Duplicate notification received - index 0x%x!!\n",
1710 cq_index);
6733b39a
JK		 1711 WARN_ON(1);
1712 }
1713
1714 *pwritables = *pwritables + writables;
1715 return 0;
1716}
1717
9728d8d0 1718static void hwi_free_async_msg(struct beiscsi_hba *phba,
8a86e833
JK		 1719 struct hwi_async_pdu_context *pasync_ctx,
1720 unsigned int cri)
6733b39a 1721{
6733b39a
JK		 1722 struct async_pdu_handle *pasync_handle, *tmp_handle;
1723 struct list_head *plist;
6733b39a 1724
6733b39a 1725 plist = &pasync_ctx->async_entry[cri].wait_queue.list;
6733b39a
JK		 1726 list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
1727 list_del(&pasync_handle->link);
1728
9728d8d0 1729 if (pasync_handle->is_header) {
6733b39a
JK		 1730 list_add_tail(&pasync_handle->link,
1731 &pasync_ctx->async_header.free_list);
1732 pasync_ctx->async_header.free_entries++;
6733b39a
JK		 1733 } else {
1734 list_add_tail(&pasync_handle->link,
1735 &pasync_ctx->async_data.free_list);
1736 pasync_ctx->async_data.free_entries++;
6733b39a
JK		 1737 }
1738 }
1739
1740 INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
1741 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
1742 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
6733b39a
JK		 1743}
1744
1745static struct phys_addr *
1746hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
1747 unsigned int is_header, unsigned int host_write_ptr)
1748{
1749 struct phys_addr *pasync_sge = NULL;
1750
1751 if (is_header)
1752 pasync_sge = pasync_ctx->async_header.ring_base;
1753 else
1754 pasync_sge = pasync_ctx->async_data.ring_base;
1755
1756 return pasync_sge + host_write_ptr;
1757}
1758
1759static void hwi_post_async_buffers(struct beiscsi_hba *phba,
8a86e833 1760 unsigned int is_header, uint8_t ulp_num)
6733b39a
JK		 1761{
1762 struct hwi_controller *phwi_ctrlr;
1763 struct hwi_async_pdu_context *pasync_ctx;
1764 struct async_pdu_handle *pasync_handle;
1765 struct list_head *pfree_link, *pbusy_list;
1766 struct phys_addr *pasync_sge;
1767 unsigned int ring_id, num_entries;
8a86e833 1768 unsigned int host_write_num, doorbell_offset;
6733b39a
JK		 1769 unsigned int writables;
1770 unsigned int i = 0;
1771 u32 doorbell = 0;
1772
1773 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833 1774 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num);
dc63aac6 1775 num_entries = pasync_ctx->num_entries;
6733b39a
JK		 1776
1777 if (is_header) {
6733b39a
JK		 1778 writables = min(pasync_ctx->async_header.writables,
1779 pasync_ctx->async_header.free_entries);
1780 pfree_link = pasync_ctx->async_header.free_list.next;
1781 host_write_num = pasync_ctx->async_header.host_write_ptr;
8a86e833
JK		 1782 ring_id = phwi_ctrlr->default_pdu_hdr[ulp_num].id;
1783 doorbell_offset = phwi_ctrlr->default_pdu_hdr[ulp_num].
1784 doorbell_offset;
6733b39a 1785 } else {
6733b39a
JK		 1786 writables = min(pasync_ctx->async_data.writables,
1787 pasync_ctx->async_data.free_entries);
1788 pfree_link = pasync_ctx->async_data.free_list.next;
1789 host_write_num = pasync_ctx->async_data.host_write_ptr;
8a86e833
JK		 1790 ring_id = phwi_ctrlr->default_pdu_data[ulp_num].id;
1791 doorbell_offset = phwi_ctrlr->default_pdu_data[ulp_num].
1792 doorbell_offset;
6733b39a
JK		 1793 }
1794
1795 writables = (writables / 8) * 8;
1796 if (writables) {
1797 for (i = 0; i < writables; i++) {
1798 pbusy_list =
1799 hwi_get_async_busy_list(pasync_ctx, is_header,
1800 host_write_num);
1801 pasync_handle =
1802 list_entry(pfree_link, struct async_pdu_handle,
1803 link);
1804 WARN_ON(!pasync_handle);
1805 pasync_handle->consumed = 0;
1806
1807 pfree_link = pfree_link->next;
1808
1809 pasync_sge = hwi_get_ring_address(pasync_ctx,
1810 is_header, host_write_num);
1811
1812 pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
1813 pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
1814
1815 list_move(&pasync_handle->link, pbusy_list);
1816
1817 host_write_num++;
1818 host_write_num = host_write_num % num_entries;
1819 }
1820
1821 if (is_header) {
1822 pasync_ctx->async_header.host_write_ptr =
1823 host_write_num;
1824 pasync_ctx->async_header.free_entries -= writables;
1825 pasync_ctx->async_header.writables -= writables;
1826 pasync_ctx->async_header.busy_entries += writables;
1827 } else {
1828 pasync_ctx->async_data.host_write_ptr = host_write_num;
1829 pasync_ctx->async_data.free_entries -= writables;
1830 pasync_ctx->async_data.writables -= writables;
1831 pasync_ctx->async_data.busy_entries += writables;
1832 }
1833
1834 doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
1835 doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
1836 doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
1837 doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
1838 << DB_DEF_PDU_CQPROC_SHIFT;
1839
8a86e833 1840 iowrite32(doorbell, phba->db_va + doorbell_offset);
6733b39a
JK		 1841 }
1842}
1843
1844static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
1845 struct beiscsi_conn *beiscsi_conn,
1846 struct i_t_dpdu_cqe *pdpdu_cqe)
1847{
1848 struct hwi_controller *phwi_ctrlr;
1849 struct hwi_async_pdu_context *pasync_ctx;
1850 struct async_pdu_handle *pasync_handle = NULL;
1851 unsigned int cq_index = -1;
8a86e833
JK		 1852 uint16_t cri_index = BE_GET_CRI_FROM_CID(
1853 beiscsi_conn->beiscsi_conn_cid);
6733b39a
JK		 1854
1855 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833
JK		 1856 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
1857 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
1858 cri_index));
6733b39a
JK		 1859
1860 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
1861 pdpdu_cqe, &cq_index);
1862 BUG_ON(pasync_handle->is_header != 0);
1863 if (pasync_handle->consumed == 0)
99bc5d55
JSJ		 1864 hwi_update_async_writables(phba, pasync_ctx,
1865 pasync_handle->is_header, cq_index);
6733b39a 1866
8a86e833
JK		 1867 hwi_free_async_msg(phba, pasync_ctx, pasync_handle->cri);
1868 hwi_post_async_buffers(phba, pasync_handle->is_header,
1869 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
1870 cri_index));
6733b39a
JK		 1871}
1872
1873static unsigned int
1874hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
1875 struct beiscsi_hba *phba,
1876 struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
1877{
1878 struct list_head *plist;
1879 struct async_pdu_handle *pasync_handle;
1880 void *phdr = NULL;
1881 unsigned int hdr_len = 0, buf_len = 0;
1882 unsigned int status, index = 0, offset = 0;
1883 void *pfirst_buffer = NULL;
1884 unsigned int num_buf = 0;
1885
1886 plist = &pasync_ctx->async_entry[cri].wait_queue.list;
1887
1888 list_for_each_entry(pasync_handle, plist, link) {
1889 if (index == 0) {
1890 phdr = pasync_handle->pbuffer;
1891 hdr_len = pasync_handle->buffer_len;
1892 } else {
1893 buf_len = pasync_handle->buffer_len;
1894 if (!num_buf) {
1895 pfirst_buffer = pasync_handle->pbuffer;
1896 num_buf++;
1897 }
1898 memcpy(pfirst_buffer + offset,
1899 pasync_handle->pbuffer, buf_len);
f2ba02b8 1900 offset += buf_len;
6733b39a
JK		 1901 }
1902 index++;
1903 }
1904
1905 status = beiscsi_process_async_pdu(beiscsi_conn, phba,
7da50879 1906 phdr, hdr_len, pfirst_buffer,
f2ba02b8 1907 offset);
6733b39a 1908
8a86e833 1909 hwi_free_async_msg(phba, pasync_ctx, cri);
6733b39a
JK		 1910 return 0;
1911}
1912
1913static unsigned int
1914hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
1915 struct beiscsi_hba *phba,
1916 struct async_pdu_handle *pasync_handle)
1917{
1918 struct hwi_async_pdu_context *pasync_ctx;
1919 struct hwi_controller *phwi_ctrlr;
1920 unsigned int bytes_needed = 0, status = 0;
1921 unsigned short cri = pasync_handle->cri;
1922 struct pdu_base *ppdu;
1923
1924 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833
JK		 1925 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
1926 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
1927 BE_GET_CRI_FROM_CID(beiscsi_conn->
1928 beiscsi_conn_cid)));
6733b39a
JK		 1929
1930 list_del(&pasync_handle->link);
1931 if (pasync_handle->is_header) {
1932 pasync_ctx->async_header.busy_entries--;
1933 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
8a86e833 1934 hwi_free_async_msg(phba, pasync_ctx, cri);
6733b39a
JK		 1935 BUG();
1936 }
1937
1938 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
1939 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
1940 pasync_ctx->async_entry[cri].wait_queue.hdr_len =
1941 (unsigned short)pasync_handle->buffer_len;
1942 list_add_tail(&pasync_handle->link,
1943 &pasync_ctx->async_entry[cri].wait_queue.list);
1944
1945 ppdu = pasync_handle->pbuffer;
1946 bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
1947 data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
1948 0xFFFF0000) | ((be16_to_cpu((ppdu->
1949 dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
1950 & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
1951
1952 if (status == 0) {
1953 pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
1954 bytes_needed;
1955
1956 if (bytes_needed == 0)
1957 status = hwi_fwd_async_msg(beiscsi_conn, phba,
1958 pasync_ctx, cri);
1959 }
1960 } else {
1961 pasync_ctx->async_data.busy_entries--;
1962 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
1963 list_add_tail(&pasync_handle->link,
1964 &pasync_ctx->async_entry[cri].wait_queue.
1965 list);
1966 pasync_ctx->async_entry[cri].wait_queue.
1967 bytes_received +=
1968 (unsigned short)pasync_handle->buffer_len;
1969
1970 if (pasync_ctx->async_entry[cri].wait_queue.
1971 bytes_received >=
1972 pasync_ctx->async_entry[cri].wait_queue.
1973 bytes_needed)
1974 status = hwi_fwd_async_msg(beiscsi_conn, phba,
1975 pasync_ctx, cri);
1976 }
1977 }
1978 return status;
1979}
1980
1981static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
1982 struct beiscsi_hba *phba,
1983 struct i_t_dpdu_cqe *pdpdu_cqe)
1984{
1985 struct hwi_controller *phwi_ctrlr;
1986 struct hwi_async_pdu_context *pasync_ctx;
1987 struct async_pdu_handle *pasync_handle = NULL;
1988 unsigned int cq_index = -1;
8a86e833
JK		 1989 uint16_t cri_index = BE_GET_CRI_FROM_CID(
1990 beiscsi_conn->beiscsi_conn_cid);
6733b39a
JK		 1991
1992 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833
JK		 1993 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
1994 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
1995 cri_index));
1996
6733b39a
JK		 1997 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
1998 pdpdu_cqe, &cq_index);
1999
2000 if (pasync_handle->consumed == 0)
99bc5d55
JSJ		 2001 hwi_update_async_writables(phba, pasync_ctx,
2002 pasync_handle->is_header, cq_index);
2003
6733b39a 2004 hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
8a86e833
JK		 2005 hwi_post_async_buffers(phba, pasync_handle->is_header,
2006 BEISCSI_GET_ULP_FROM_CRI(
2007 phwi_ctrlr, cri_index));
6733b39a
JK		 2008}
2009
2e4e8f65 2010void beiscsi_process_mcc_cq(struct beiscsi_hba *phba)
756d29c8
JK		 2011{
2012 struct be_queue_info *mcc_cq;
2013 struct be_mcc_compl *mcc_compl;
2014 unsigned int num_processed = 0;
2015
2016 mcc_cq = &phba->ctrl.mcc_obj.cq;
2017 mcc_compl = queue_tail_node(mcc_cq);
2018 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
2019 while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
756d29c8
JK		 2020 if (num_processed >= 32) {
2021 hwi_ring_cq_db(phba, mcc_cq->id,
1094cf68 2022 num_processed, 0);
756d29c8
JK		 2023 num_processed = 0;
2024 }
2025 if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
53aefe25 2026 beiscsi_process_async_event(phba, mcc_compl);
756d29c8 2027 } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
2e4e8f65 2028 beiscsi_process_mcc_compl(&phba->ctrl, mcc_compl);
756d29c8
JK		 2029 }
2030
2031 mcc_compl->flags = 0;
2032 queue_tail_inc(mcc_cq);
2033 mcc_compl = queue_tail_node(mcc_cq);
2034 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
2035 num_processed++;
2036 }
2037
2038 if (num_processed > 0)
1094cf68 2039 hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1);
756d29c8 2040}
bfead3b2 2041
a3095016
JB		 2042static void beiscsi_mcc_work(struct work_struct *work)
2043{
2044 struct be_eq_obj *pbe_eq;
2045 struct beiscsi_hba *phba;
2046
2047 pbe_eq = container_of(work, struct be_eq_obj, mcc_work);
2048 phba = pbe_eq->phba;
2049 beiscsi_process_mcc_cq(phba);
2050 /* rearm EQ for further interrupts */
2051 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
2052}
2053
6763daae
JSJ		 2054/**
2055 * beiscsi_process_cq()- Process the Completion Queue
2056 * @pbe_eq: Event Q on which the Completion has come
1094cf68 2057 * @budget: Max number of events to processed
6763daae
JSJ		 2058 *
2059 * return
2060 * Number of Completion Entries processed.
2061 **/
1094cf68 2062unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget)
6733b39a 2063{
6733b39a
JK		 2064 struct be_queue_info *cq;
2065 struct sol_cqe *sol;
2066 struct dmsg_cqe *dmsg;
1094cf68 2067 unsigned int total = 0;
6733b39a 2068 unsigned int num_processed = 0;
0a513dd8 2069 unsigned short code = 0, cid = 0;
a7909b39 2070 uint16_t cri_index = 0;
6733b39a 2071 struct beiscsi_conn *beiscsi_conn;
c2462288
JK		 2072 struct beiscsi_endpoint *beiscsi_ep;
2073 struct iscsi_endpoint *ep;
bfead3b2 2074 struct beiscsi_hba *phba;
6733b39a 2075
bfead3b2 2076 cq = pbe_eq->cq;
6733b39a 2077 sol = queue_tail_node(cq);
bfead3b2 2078 phba = pbe_eq->phba;
6733b39a
JK		 2079
2080 while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
2081 CQE_VALID_MASK) {
2082 be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
2083
73133261
JSJ		 2084 code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
2085 32] & CQE_CODE_MASK);
2086
2087 /* Get the CID */
2c9dfd36
JK		 2088 if (is_chip_be2_be3r(phba)) {
2089 cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol);
2090 } else {
73133261
JSJ		 2091 if ((code == DRIVERMSG_NOTIFY) ||
2092 (code == UNSOL_HDR_NOTIFY) ||
2093 (code == UNSOL_DATA_NOTIFY))
2094 cid = AMAP_GET_BITS(
2095 struct amap_i_t_dpdu_cqe_v2,
2096 cid, sol);
2097 else
2098 cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
2099 cid, sol);
2c9dfd36 2100 }
32951dd8 2101
a7909b39
JK		 2102 cri_index = BE_GET_CRI_FROM_CID(cid);
2103 ep = phba->ep_array[cri_index];
b7ab35b1
JK		 2104
2105 if (ep == NULL) {
2106 /* connection has already been freed
2107 * just move on to next one
2108 */
2109 beiscsi_log(phba, KERN_WARNING,
2110 BEISCSI_LOG_INIT,
2111 "BM_%d : proc cqe of disconn ep: cid %d\n",
2112 cid);
2113 goto proc_next_cqe;
2114 }
2115
c2462288
JK		 2116 beiscsi_ep = ep->dd_data;
2117 beiscsi_conn = beiscsi_ep->conn;
756d29c8 2118
1094cf68
JB		 2119 /* replenish cq */
2120 if (num_processed == 32) {
2121 hwi_ring_cq_db(phba, cq->id, 32, 0);
6733b39a
JK		 2122 num_processed = 0;
2123 }
1094cf68 2124 total++;
6733b39a 2125
0a513dd8 2126 switch (code) {
6733b39a
JK		 2127 case SOL_CMD_COMPLETE:
2128 hwi_complete_cmd(beiscsi_conn, phba, sol);
2129 break;
2130 case DRIVERMSG_NOTIFY:
99bc5d55
JSJ		 2131 beiscsi_log(phba, KERN_INFO,
2132 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2133 "BM_%d : Received %s[%d] on CID : %d\n",
2134 cqe_desc[code], code, cid);
99bc5d55 2135
6733b39a
JK		 2136 dmsg = (struct dmsg_cqe *)sol;
2137 hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
2138 break;
2139 case UNSOL_HDR_NOTIFY:
99bc5d55
JSJ		 2140 beiscsi_log(phba, KERN_INFO,
2141 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2142 "BM_%d : Received %s[%d] on CID : %d\n",
2143 cqe_desc[code], code, cid);
99bc5d55 2144
8f09a3b9 2145 spin_lock_bh(&phba->async_pdu_lock);
bfead3b2
JK		 2146 hwi_process_default_pdu_ring(beiscsi_conn, phba,
2147 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 2148 spin_unlock_bh(&phba->async_pdu_lock);
bfead3b2 2149 break;
6733b39a 2150 case UNSOL_DATA_NOTIFY:
99bc5d55
JSJ		 2151 beiscsi_log(phba, KERN_INFO,
2152 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
6763daae
JSJ		 2153 "BM_%d : Received %s[%d] on CID : %d\n",
2154 cqe_desc[code], code, cid);
99bc5d55 2155
8f09a3b9 2156 spin_lock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2157 hwi_process_default_pdu_ring(beiscsi_conn, phba,
2158 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 2159 spin_unlock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2160 break;
2161 case CXN_INVALIDATE_INDEX_NOTIFY:
2162 case CMD_INVALIDATED_NOTIFY:
2163 case CXN_INVALIDATE_NOTIFY:
99bc5d55
JSJ		 2164 beiscsi_log(phba, KERN_ERR,
2165 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2166 "BM_%d : Ignoring %s[%d] on CID : %d\n",
2167 cqe_desc[code], code, cid);
6733b39a 2168 break;
1094cf68 2169 case CXN_KILLED_HDR_DIGEST_ERR:
6733b39a 2170 case SOL_CMD_KILLED_DATA_DIGEST_ERR:
1094cf68
JB		 2171 beiscsi_log(phba, KERN_ERR,
2172 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
2173 "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
2174 cqe_desc[code], code, cid);
2175 break;
6733b39a
JK		 2176 case CMD_KILLED_INVALID_STATSN_RCVD:
2177 case CMD_KILLED_INVALID_R2T_RCVD:
2178 case CMD_CXN_KILLED_LUN_INVALID:
2179 case CMD_CXN_KILLED_ICD_INVALID:
2180 case CMD_CXN_KILLED_ITT_INVALID:
2181 case CMD_CXN_KILLED_SEQ_OUTOFORDER:
2182 case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
99bc5d55
JSJ		 2183 beiscsi_log(phba, KERN_ERR,
2184 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
6763daae
JSJ		 2185 "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
2186 cqe_desc[code], code, cid);
6733b39a
JK		 2187 break;
2188 case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
99bc5d55
JSJ		 2189 beiscsi_log(phba, KERN_ERR,
2190 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2191 "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
2192 cqe_desc[code], code, cid);
8f09a3b9 2193 spin_lock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2194 hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
2195 (struct i_t_dpdu_cqe *) sol);
8f09a3b9 2196 spin_unlock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2197 break;
2198 case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
2199 case CXN_KILLED_BURST_LEN_MISMATCH:
2200 case CXN_KILLED_AHS_RCVD:
6733b39a
JK		 2201 case CXN_KILLED_UNKNOWN_HDR:
2202 case CXN_KILLED_STALE_ITT_TTT_RCVD:
2203 case CXN_KILLED_INVALID_ITT_TTT_RCVD:
2204 case CXN_KILLED_TIMED_OUT:
2205 case CXN_KILLED_FIN_RCVD:
6763daae
JSJ		 2206 case CXN_KILLED_RST_SENT:
2207 case CXN_KILLED_RST_RCVD:
6733b39a
JK		 2208 case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
2209 case CXN_KILLED_BAD_WRB_INDEX_ERROR:
2210 case CXN_KILLED_OVER_RUN_RESIDUAL:
2211 case CXN_KILLED_UNDER_RUN_RESIDUAL:
2212 case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
99bc5d55
JSJ		 2213 beiscsi_log(phba, KERN_ERR,
2214 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2215 "BM_%d : Event %s[%d] received on CID : %d\n",
2216 cqe_desc[code], code, cid);
0a513dd8
JSJ		 2217 if (beiscsi_conn)
2218 iscsi_conn_failure(beiscsi_conn->conn,
2219 ISCSI_ERR_CONN_FAILED);
6733b39a
JK		 2220 break;
2221 default:
99bc5d55
JSJ		 2222 beiscsi_log(phba, KERN_ERR,
2223 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2224 "BM_%d : Invalid CQE Event Received Code : %d"
2225 "CID 0x%x...\n",
0a513dd8 2226 code, cid);
6733b39a
JK		 2227 break;
2228 }
2229
b7ab35b1 2230proc_next_cqe:
6733b39a
JK		 2231 AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
2232 queue_tail_inc(cq);
2233 sol = queue_tail_node(cq);
2234 num_processed++;
1094cf68
JB		 2235 if (total == budget)
2236 break;
6733b39a
JK		 2237 }
2238
1094cf68
JB		 2239 hwi_ring_cq_db(phba, cq->id, num_processed, 1);
2240 return total;
6733b39a
JK		 2241}
2242
511cbce2 2243static int be_iopoll(struct irq_poll *iop, int budget)
6733b39a 2244{
a3095016 2245 unsigned int ret, io_events;
6733b39a 2246 struct beiscsi_hba *phba;
bfead3b2 2247 struct be_eq_obj *pbe_eq;
1094cf68
JB		 2248 struct be_eq_entry *eqe = NULL;
2249 struct be_queue_info *eq;
6733b39a 2250
a3095016 2251 io_events = 0;
bfead3b2 2252 pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
1094cf68
JB		 2253 phba = pbe_eq->phba;
2254 eq = &pbe_eq->q;
2255 eqe = queue_tail_node(eq);
2256
2257 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] &
2258 EQE_VALID_MASK) {
2259 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
2260 queue_tail_inc(eq);
2261 eqe = queue_tail_node(eq);
a3095016 2262 io_events++;
1094cf68
JB		 2263 }
2264
a3095016 2265 hwi_ring_eq_db(phba, eq->id, 1, io_events, 0, 1);
1094cf68
JB		 2266
2267 ret = beiscsi_process_cq(pbe_eq, budget);
73af08e1 2268 pbe_eq->cq_count += ret;
6733b39a 2269 if (ret < budget) {
511cbce2 2270 irq_poll_complete(iop);
99bc5d55
JSJ		 2271 beiscsi_log(phba, KERN_INFO,
2272 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1094cf68
JB		 2273 "BM_%d : rearm pbe_eq->q.id =%d ret %d\n",
2274 pbe_eq->q.id, ret);
bfead3b2 2275 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
6733b39a
JK		 2276 }
2277 return ret;
2278}
2279
09a1093a
JSJ		 2280static void
2281hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg,
2282 unsigned int num_sg, struct beiscsi_io_task *io_task)
2283{
2284 struct iscsi_sge *psgl;
2285 unsigned int sg_len, index;
2286 unsigned int sge_len = 0;
2287 unsigned long long addr;
2288 struct scatterlist *l_sg;
2289 unsigned int offset;
2290
2291 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb,
2292 io_task->bhs_pa.u.a32.address_lo);
2293 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb,
2294 io_task->bhs_pa.u.a32.address_hi);
2295
2296 l_sg = sg;
2297 for (index = 0; (index < num_sg) && (index < 2); index++,
2298 sg = sg_next(sg)) {
2299 if (index == 0) {
2300 sg_len = sg_dma_len(sg);
2301 addr = (u64) sg_dma_address(sg);
2302 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2303 sge0_addr_lo, pwrb,
2304 lower_32_bits(addr));
2305 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2306 sge0_addr_hi, pwrb,
2307 upper_32_bits(addr));
2308 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2309 sge0_len, pwrb,
2310 sg_len);
2311 sge_len = sg_len;
2312 } else {
2313 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset,
2314 pwrb, sge_len);
2315 sg_len = sg_dma_len(sg);
2316 addr = (u64) sg_dma_address(sg);
2317 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2318 sge1_addr_lo, pwrb,
2319 lower_32_bits(addr));
2320 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2321 sge1_addr_hi, pwrb,
2322 upper_32_bits(addr));
2323 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2324 sge1_len, pwrb,
2325 sg_len);
2326 }
2327 }
2328 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2329 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2330
2331 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2332
2333 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2334 io_task->bhs_pa.u.a32.address_hi);
2335 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2336 io_task->bhs_pa.u.a32.address_lo);
2337
2338 if (num_sg == 1) {
2339 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2340 1);
2341 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2342 0);
2343 } else if (num_sg == 2) {
2344 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2345 0);
2346 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2347 1);
2348 } else {
2349 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2350 0);
2351 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2352 0);
2353 }
2354
2355 sg = l_sg;
2356 psgl++;
2357 psgl++;
2358 offset = 0;
2359 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
2360 sg_len = sg_dma_len(sg);
2361 addr = (u64) sg_dma_address(sg);
2362 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2363 lower_32_bits(addr));
2364 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2365 upper_32_bits(addr));
2366 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2367 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2368 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2369 offset += sg_len;
2370 }
2371 psgl--;
2372 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2373}
2374
6733b39a
JK		 2375static void
2376hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
2377 unsigned int num_sg, struct beiscsi_io_task *io_task)
2378{
2379 struct iscsi_sge *psgl;
58ff4bd0 2380 unsigned int sg_len, index;
6733b39a
JK		 2381 unsigned int sge_len = 0;
2382 unsigned long long addr;
2383 struct scatterlist *l_sg;
2384 unsigned int offset;
2385
2386 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2387 io_task->bhs_pa.u.a32.address_lo);
2388 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2389 io_task->bhs_pa.u.a32.address_hi);
2390
2391 l_sg = sg;
48bd86cf
JK		 2392 for (index = 0; (index < num_sg) && (index < 2); index++,
2393 sg = sg_next(sg)) {
6733b39a
JK		 2394 if (index == 0) {
2395 sg_len = sg_dma_len(sg);
2396 addr = (u64) sg_dma_address(sg);
2397 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
457ff3b7 2398 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2399 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
457ff3b7 2400 ((u32)(addr >> 32)));
6733b39a
JK		 2401 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2402 sg_len);
2403 sge_len = sg_len;
6733b39a 2404 } else {
6733b39a
JK		 2405 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
2406 pwrb, sge_len);
2407 sg_len = sg_dma_len(sg);
2408 addr = (u64) sg_dma_address(sg);
2409 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
457ff3b7 2410 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2411 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
457ff3b7 2412 ((u32)(addr >> 32)));
6733b39a
JK		 2413 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
2414 sg_len);
2415 }
2416 }
2417 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2418 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2419
2420 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2421
2422 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2423 io_task->bhs_pa.u.a32.address_hi);
2424 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2425 io_task->bhs_pa.u.a32.address_lo);
2426
caf818f1
JK		 2427 if (num_sg == 1) {
2428 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2429 1);
2430 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2431 0);
2432 } else if (num_sg == 2) {
2433 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2434 0);
2435 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2436 1);
2437 } else {
2438 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2439 0);
2440 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2441 0);
2442 }
6733b39a
JK		 2443 sg = l_sg;
2444 psgl++;
2445 psgl++;
2446 offset = 0;
48bd86cf 2447 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
6733b39a
JK		 2448 sg_len = sg_dma_len(sg);
2449 addr = (u64) sg_dma_address(sg);
2450 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2451 (addr & 0xFFFFFFFF));
2452 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2453 (addr >> 32));
2454 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2455 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2456 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2457 offset += sg_len;
2458 }
2459 psgl--;
2460 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2461}
2462
d629c471
JSJ		 2463/**
2464 * hwi_write_buffer()- Populate the WRB with task info
2465 * @pwrb: ptr to the WRB entry
2466 * @task: iscsi task which is to be executed
2467 **/
e0493627 2468static int hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
6733b39a
JK		 2469{
2470 struct iscsi_sge *psgl;
6733b39a
JK		 2471 struct beiscsi_io_task *io_task = task->dd_data;
2472 struct beiscsi_conn *beiscsi_conn = io_task->conn;
2473 struct beiscsi_hba *phba = beiscsi_conn->phba;
09a1093a 2474 uint8_t dsp_value = 0;
6733b39a
JK		 2475
2476 io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
2477 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2478 io_task->bhs_pa.u.a32.address_lo);
2479 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2480 io_task->bhs_pa.u.a32.address_hi);
2481
2482 if (task->data) {
09a1093a
JSJ		 2483
2484 /* Check for the data_count */
2485 dsp_value = (task->data_count) ? 1 : 0;
2486
2c9dfd36
JK		 2487 if (is_chip_be2_be3r(phba))
2488 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp,
09a1093a
JSJ		 2489 pwrb, dsp_value);
2490 else
2c9dfd36 2491 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp,
09a1093a
JSJ		 2492 pwrb, dsp_value);
2493
2494 /* Map addr only if there is data_count */
2495 if (dsp_value) {
d629c471
JSJ		 2496 io_task->mtask_addr = pci_map_single(phba->pcidev,
2497 task->data,
2498 task->data_count,
2499 PCI_DMA_TODEVICE);
e0493627
AK		 2500 if (pci_dma_mapping_error(phba->pcidev,
2501 io_task->mtask_addr))
2502 return -ENOMEM;
d629c471 2503 io_task->mtask_data_count = task->data_count;
09a1093a 2504 } else
d629c471 2505 io_task->mtask_addr = 0;
09a1093a 2506
6733b39a 2507 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
d629c471 2508 lower_32_bits(io_task->mtask_addr));
6733b39a 2509 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
d629c471 2510 upper_32_bits(io_task->mtask_addr));
6733b39a
JK		 2511 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2512 task->data_count);
2513
2514 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
2515 } else {
2516 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
d629c471 2517 io_task->mtask_addr = 0;
6733b39a
JK		 2518 }
2519
2520 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2521
2522 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
2523
2524 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2525 io_task->bhs_pa.u.a32.address_hi);
2526 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2527 io_task->bhs_pa.u.a32.address_lo);
2528 if (task->data) {
2529 psgl++;
2530 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
2531 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
2532 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
2533 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
2534 AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
2535 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2536
2537 psgl++;
2538 if (task->data) {
2539 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
d629c471 2540 lower_32_bits(io_task->mtask_addr));
6733b39a 2541 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
d629c471 2542 upper_32_bits(io_task->mtask_addr));
6733b39a
JK		 2543 }
2544 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
2545 }
2546 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
e0493627 2547 return 0;
6733b39a
JK		 2548}
2549
843ae752
JK		 2550/**
2551 * beiscsi_find_mem_req()- Find mem needed
2552 * @phba: ptr to HBA struct
2553 **/
6733b39a
JK		 2554static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
2555{
8a86e833 2556 uint8_t mem_descr_index, ulp_num;
bfead3b2 2557 unsigned int num_cq_pages, num_async_pdu_buf_pages;
6733b39a
JK		 2558 unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
2559 unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
2560
2561 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
2562 sizeof(struct sol_cqe));
6733b39a
JK		 2563
2564 phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
2565
2566 phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
2567 BE_ISCSI_PDU_HEADER_SIZE;
2568 phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
2569 sizeof(struct hwi_context_memory);
2570
6733b39a
JK		 2571
2572 phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
2573 * (phba->params.wrbs_per_cxn)
2574 * phba->params.cxns_per_ctrl;
2575 wrb_sz_per_cxn = sizeof(struct wrb_handle) *
2576 (phba->params.wrbs_per_cxn);
2577 phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
2578 phba->params.cxns_per_ctrl);
2579
2580 phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
2581 phba->params.icds_per_ctrl;
2582 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
2583 phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
8a86e833
JK		 2584 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
2585 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 2586
8a86e833
JK		 2587 num_async_pdu_buf_sgl_pages =
2588 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2589 phba, ulp_num) *
2590 sizeof(struct phys_addr));
2591
2592 num_async_pdu_buf_pages =
2593 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2594 phba, ulp_num) *
2595 phba->params.defpdu_hdr_sz);
2596
2597 num_async_pdu_data_pages =
2598 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2599 phba, ulp_num) *
2600 phba->params.defpdu_data_sz);
2601
2602 num_async_pdu_data_sgl_pages =
2603 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2604 phba, ulp_num) *
2605 sizeof(struct phys_addr));
2606
a129d92f
JK		 2607 mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 +
2608 (ulp_num * MEM_DESCR_OFFSET));
2609 phba->mem_req[mem_descr_index] =
2610 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2611 BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
2612
8a86e833
JK		 2613 mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
2614 (ulp_num * MEM_DESCR_OFFSET));
2615 phba->mem_req[mem_descr_index] =
2616 num_async_pdu_buf_pages *
2617 PAGE_SIZE;
2618
2619 mem_descr_index = (HWI_MEM_ASYNC_DATA_BUF_ULP0 +
2620 (ulp_num * MEM_DESCR_OFFSET));
2621 phba->mem_req[mem_descr_index] =
2622 num_async_pdu_data_pages *
2623 PAGE_SIZE;
2624
2625 mem_descr_index = (HWI_MEM_ASYNC_HEADER_RING_ULP0 +
2626 (ulp_num * MEM_DESCR_OFFSET));
2627 phba->mem_req[mem_descr_index] =
2628 num_async_pdu_buf_sgl_pages *
2629 PAGE_SIZE;
2630
2631 mem_descr_index = (HWI_MEM_ASYNC_DATA_RING_ULP0 +
2632 (ulp_num * MEM_DESCR_OFFSET));
2633 phba->mem_req[mem_descr_index] =
2634 num_async_pdu_data_sgl_pages *
2635 PAGE_SIZE;
2636
2637 mem_descr_index = (HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
2638 (ulp_num * MEM_DESCR_OFFSET));
2639 phba->mem_req[mem_descr_index] =
2640 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2641 sizeof(struct async_pdu_handle);
2642
2643 mem_descr_index = (HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
2644 (ulp_num * MEM_DESCR_OFFSET));
2645 phba->mem_req[mem_descr_index] =
2646 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2647 sizeof(struct async_pdu_handle);
2648
2649 mem_descr_index = (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
2650 (ulp_num * MEM_DESCR_OFFSET));
2651 phba->mem_req[mem_descr_index] =
2652 sizeof(struct hwi_async_pdu_context) +
2653 (BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2654 sizeof(struct hwi_async_entry));
2655 }
2656 }
6733b39a
JK		 2657}
2658
2659static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
2660{
6733b39a 2661 dma_addr_t bus_add;
a7909b39
JK		 2662 struct hwi_controller *phwi_ctrlr;
2663 struct be_mem_descriptor *mem_descr;
6733b39a
JK		 2664 struct mem_array *mem_arr, *mem_arr_orig;
2665 unsigned int i, j, alloc_size, curr_alloc_size;
2666
3ec78271 2667 phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
6733b39a
JK		 2668 if (!phba->phwi_ctrlr)
2669 return -ENOMEM;
2670
a7909b39
JK		 2671 /* Allocate memory for wrb_context */
2672 phwi_ctrlr = phba->phwi_ctrlr;
2673 phwi_ctrlr->wrb_context = kzalloc(sizeof(struct hwi_wrb_context) *
2674 phba->params.cxns_per_ctrl,
2675 GFP_KERNEL);
0c88740d
ML		 2676 if (!phwi_ctrlr->wrb_context) {
2677 kfree(phba->phwi_ctrlr);
a7909b39 2678 return -ENOMEM;
0c88740d 2679 }
a7909b39 2680
6733b39a
JK		 2681 phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
2682 GFP_KERNEL);
2683 if (!phba->init_mem) {
a7909b39 2684 kfree(phwi_ctrlr->wrb_context);
6733b39a
JK		 2685 kfree(phba->phwi_ctrlr);
2686 return -ENOMEM;
2687 }
2688
2689 mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
2690 GFP_KERNEL);
2691 if (!mem_arr_orig) {
2692 kfree(phba->init_mem);
a7909b39 2693 kfree(phwi_ctrlr->wrb_context);
6733b39a
JK		 2694 kfree(phba->phwi_ctrlr);
2695 return -ENOMEM;
2696 }
2697
2698 mem_descr = phba->init_mem;
2699 for (i = 0; i < SE_MEM_MAX; i++) {
8a86e833
JK		 2700 if (!phba->mem_req[i]) {
2701 mem_descr->mem_array = NULL;
2702 mem_descr++;
2703 continue;
2704 }
2705
6733b39a
JK		 2706 j = 0;
2707 mem_arr = mem_arr_orig;
2708 alloc_size = phba->mem_req[i];
2709 memset(mem_arr, 0, sizeof(struct mem_array) *
2710 BEISCSI_MAX_FRAGS_INIT);
2711 curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
2712 do {
2713 mem_arr->virtual_address = pci_alloc_consistent(
2714 phba->pcidev,
2715 curr_alloc_size,
2716 &bus_add);
2717 if (!mem_arr->virtual_address) {
2718 if (curr_alloc_size <= BE_MIN_MEM_SIZE)
2719 goto free_mem;
2720 if (curr_alloc_size -
2721 rounddown_pow_of_two(curr_alloc_size))
2722 curr_alloc_size = rounddown_pow_of_two
2723 (curr_alloc_size);
2724 else
2725 curr_alloc_size = curr_alloc_size / 2;
2726 } else {
2727 mem_arr->bus_address.u.
2728 a64.address = (__u64) bus_add;
2729 mem_arr->size = curr_alloc_size;
2730 alloc_size -= curr_alloc_size;
2731 curr_alloc_size = min(be_max_phys_size *
2732 1024, alloc_size);
2733 j++;
2734 mem_arr++;
2735 }
2736 } while (alloc_size);
2737 mem_descr->num_elements = j;
2738 mem_descr->size_in_bytes = phba->mem_req[i];
2739 mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
2740 GFP_KERNEL);
2741 if (!mem_descr->mem_array)
2742 goto free_mem;
2743
2744 memcpy(mem_descr->mem_array, mem_arr_orig,
2745 sizeof(struct mem_array) * j);
2746 mem_descr++;
2747 }
2748 kfree(mem_arr_orig);
2749 return 0;
2750free_mem:
2751 mem_descr->num_elements = j;
2752 while ((i) || (j)) {
2753 for (j = mem_descr->num_elements; j > 0; j--) {
2754 pci_free_consistent(phba->pcidev,
2755 mem_descr->mem_array[j - 1].size,
2756 mem_descr->mem_array[j - 1].
2757 virtual_address,
457ff3b7
JK		 2758 (unsigned long)mem_descr->
2759 mem_array[j - 1].
6733b39a
JK		 2760 bus_address.u.a64.address);
2761 }
2762 if (i) {
2763 i--;
2764 kfree(mem_descr->mem_array);
2765 mem_descr--;
2766 }
2767 }
2768 kfree(mem_arr_orig);
2769 kfree(phba->init_mem);
a7909b39 2770 kfree(phba->phwi_ctrlr->wrb_context);
6733b39a
JK		 2771 kfree(phba->phwi_ctrlr);
2772 return -ENOMEM;
2773}
2774
2775static int beiscsi_get_memory(struct beiscsi_hba *phba)
2776{
2777 beiscsi_find_mem_req(phba);
2778 return beiscsi_alloc_mem(phba);
2779}
2780
2781static void iscsi_init_global_templates(struct beiscsi_hba *phba)
2782{
2783 struct pdu_data_out *pdata_out;
2784 struct pdu_nop_out *pnop_out;
2785 struct be_mem_descriptor *mem_descr;
2786
2787 mem_descr = phba->init_mem;
2788 mem_descr += ISCSI_MEM_GLOBAL_HEADER;
2789 pdata_out =
2790 (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
2791 memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2792
2793 AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
2794 IIOC_SCSI_DATA);
2795
2796 pnop_out =
2797 (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
2798 virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
2799
2800 memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2801 AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
2802 AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
2803 AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
2804}
2805
3ec78271 2806static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
6733b39a
JK		 2807{
2808 struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
a7909b39 2809 struct hwi_context_memory *phwi_ctxt;
3ec78271 2810 struct wrb_handle *pwrb_handle = NULL;
6733b39a
JK		 2811 struct hwi_controller *phwi_ctrlr;
2812 struct hwi_wrb_context *pwrb_context;
3ec78271
JK		 2813 struct iscsi_wrb *pwrb = NULL;
2814 unsigned int num_cxn_wrbh = 0;
2815 unsigned int num_cxn_wrb = 0, j, idx = 0, index;
6733b39a
JK		 2816
2817 mem_descr_wrbh = phba->init_mem;
2818 mem_descr_wrbh += HWI_MEM_WRBH;
2819
2820 mem_descr_wrb = phba->init_mem;
2821 mem_descr_wrb += HWI_MEM_WRB;
6733b39a
JK		 2822 phwi_ctrlr = phba->phwi_ctrlr;
2823
a7909b39
JK		 2824 /* Allocate memory for WRBQ */
2825 phwi_ctxt = phwi_ctrlr->phwi_ctxt;
2826 phwi_ctxt->be_wrbq = kzalloc(sizeof(struct be_queue_info) *
843ae752 2827 phba->params.cxns_per_ctrl,
a7909b39
JK		 2828 GFP_KERNEL);
2829 if (!phwi_ctxt->be_wrbq) {
2830 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2831 "BM_%d : WRBQ Mem Alloc Failed\n");
2832 return -ENOMEM;
2833 }
2834
2835 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a 2836 pwrb_context = &phwi_ctrlr->wrb_context[index];
6733b39a
JK		 2837 pwrb_context->pwrb_handle_base =
2838 kzalloc(sizeof(struct wrb_handle *) *
2839 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271 2840 if (!pwrb_context->pwrb_handle_base) {
99bc5d55
JSJ		 2841 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2842 "BM_%d : Mem Alloc Failed. Failing to load\n");
3ec78271
JK		 2843 goto init_wrb_hndl_failed;
2844 }
6733b39a
JK		 2845 pwrb_context->pwrb_handle_basestd =
2846 kzalloc(sizeof(struct wrb_handle *) *
2847 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271 2848 if (!pwrb_context->pwrb_handle_basestd) {
99bc5d55
JSJ		 2849 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2850 "BM_%d : Mem Alloc Failed. Failing to load\n");
3ec78271
JK		 2851 goto init_wrb_hndl_failed;
2852 }
2853 if (!num_cxn_wrbh) {
2854 pwrb_handle =
2855 mem_descr_wrbh->mem_array[idx].virtual_address;
2856 num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
2857 ((sizeof(struct wrb_handle)) *
2858 phba->params.wrbs_per_cxn));
2859 idx++;
2860 }
2861 pwrb_context->alloc_index = 0;
2862 pwrb_context->wrb_handles_available = 0;
2863 pwrb_context->free_index = 0;
2864
6733b39a 2865 if (num_cxn_wrbh) {
6733b39a
JK		 2866 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2867 pwrb_context->pwrb_handle_base[j] = pwrb_handle;
2868 pwrb_context->pwrb_handle_basestd[j] =
2869 pwrb_handle;
2870 pwrb_context->wrb_handles_available++;
bfead3b2 2871 pwrb_handle->wrb_index = j;
6733b39a
JK		 2872 pwrb_handle++;
2873 }
6733b39a
JK		 2874 num_cxn_wrbh--;
2875 }
f64d92e6 2876 spin_lock_init(&pwrb_context->wrb_lock);
6733b39a
JK		 2877 }
2878 idx = 0;
a7909b39 2879 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a 2880 pwrb_context = &phwi_ctrlr->wrb_context[index];
3ec78271 2881 if (!num_cxn_wrb) {
6733b39a 2882 pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
7c56533c 2883 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
3ec78271
JK		 2884 ((sizeof(struct iscsi_wrb) *
2885 phba->params.wrbs_per_cxn));
2886 idx++;
2887 }
2888
2889 if (num_cxn_wrb) {
6733b39a
JK		 2890 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2891 pwrb_handle = pwrb_context->pwrb_handle_base[j];
2892 pwrb_handle->pwrb = pwrb;
2893 pwrb++;
2894 }
2895 num_cxn_wrb--;
2896 }
2897 }
3ec78271
JK		 2898 return 0;
2899init_wrb_hndl_failed:
2900 for (j = index; j > 0; j--) {
2901 pwrb_context = &phwi_ctrlr->wrb_context[j];
2902 kfree(pwrb_context->pwrb_handle_base);
2903 kfree(pwrb_context->pwrb_handle_basestd);
2904 }
2905 return -ENOMEM;
6733b39a
JK		 2906}
2907
a7909b39 2908static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
6733b39a 2909{
8a86e833 2910 uint8_t ulp_num;
6733b39a
JK		 2911 struct hwi_controller *phwi_ctrlr;
2912 struct hba_parameters *p = &phba->params;
2913 struct hwi_async_pdu_context *pasync_ctx;
2914 struct async_pdu_handle *pasync_header_h, *pasync_data_h;
dc63aac6 2915 unsigned int index, idx, num_per_mem, num_async_data;
6733b39a
JK		 2916 struct be_mem_descriptor *mem_descr;
2917
8a86e833
JK		 2918 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
2919 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 2920
8a86e833
JK		 2921 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2922 mem_descr += (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
2923 (ulp_num * MEM_DESCR_OFFSET));
2924
2925 phwi_ctrlr = phba->phwi_ctrlr;
2926 phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num] =
2927 (struct hwi_async_pdu_context *)
2928 mem_descr->mem_array[0].virtual_address;
2929
2930 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
2931 memset(pasync_ctx, 0, sizeof(*pasync_ctx));
2932
2933 pasync_ctx->async_entry =
2934 (struct hwi_async_entry *)
2935 ((long unsigned int)pasync_ctx +
2936 sizeof(struct hwi_async_pdu_context));
2937
2938 pasync_ctx->num_entries = BEISCSI_GET_CID_COUNT(phba,
2939 ulp_num);
2940 pasync_ctx->buffer_size = p->defpdu_hdr_sz;
2941
2942 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2943 mem_descr += HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
2944 (ulp_num * MEM_DESCR_OFFSET);
2945 if (mem_descr->mem_array[0].virtual_address) {
2946 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2947 "BM_%d : hwi_init_async_pdu_ctx"
2948 " HWI_MEM_ASYNC_HEADER_BUF_ULP%d va=%p\n",
2949 ulp_num,
2950 mem_descr->mem_array[0].
2951 virtual_address);
2952 } else
2953 beiscsi_log(phba, KERN_WARNING,
2954 BEISCSI_LOG_INIT,
2955 "BM_%d : No Virtual address for ULP : %d\n",
2956 ulp_num);
2957
2958 pasync_ctx->async_header.va_base =
6733b39a 2959 mem_descr->mem_array[0].virtual_address;
6733b39a 2960
8a86e833
JK		 2961 pasync_ctx->async_header.pa_base.u.a64.address =
2962 mem_descr->mem_array[0].
2963 bus_address.u.a64.address;
6733b39a 2964
8a86e833
JK		 2965 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2966 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
2967 (ulp_num * MEM_DESCR_OFFSET);
2968 if (mem_descr->mem_array[0].virtual_address) {
2969 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2970 "BM_%d : hwi_init_async_pdu_ctx"
2971 " HWI_MEM_ASYNC_HEADER_RING_ULP%d va=%p\n",
2972 ulp_num,
2973 mem_descr->mem_array[0].
2974 virtual_address);
2975 } else
2976 beiscsi_log(phba, KERN_WARNING,
2977 BEISCSI_LOG_INIT,
2978 "BM_%d : No Virtual address for ULP : %d\n",
2979 ulp_num);
2980
2981 pasync_ctx->async_header.ring_base =
2982 mem_descr->mem_array[0].virtual_address;
6733b39a 2983
8a86e833
JK		 2984 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2985 mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
2986 (ulp_num * MEM_DESCR_OFFSET);
2987 if (mem_descr->mem_array[0].virtual_address) {
2988 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2989 "BM_%d : hwi_init_async_pdu_ctx"
2990 " HWI_MEM_ASYNC_HEADER_HANDLE_ULP%d va=%p\n",
2991 ulp_num,
2992 mem_descr->mem_array[0].
2993 virtual_address);
2994 } else
2995 beiscsi_log(phba, KERN_WARNING,
2996 BEISCSI_LOG_INIT,
2997 "BM_%d : No Virtual address for ULP : %d\n",
2998 ulp_num);
2999
3000 pasync_ctx->async_header.handle_base =
3001 mem_descr->mem_array[0].virtual_address;
3002 pasync_ctx->async_header.writables = 0;
3003 INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
3004
3005 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3006 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
3007 (ulp_num * MEM_DESCR_OFFSET);
3008 if (mem_descr->mem_array[0].virtual_address) {
3009 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3010 "BM_%d : hwi_init_async_pdu_ctx"
3011 " HWI_MEM_ASYNC_DATA_RING_ULP%d va=%p\n",
3012 ulp_num,
3013 mem_descr->mem_array[0].
3014 virtual_address);
3015 } else
3016 beiscsi_log(phba, KERN_WARNING,
3017 BEISCSI_LOG_INIT,
3018 "BM_%d : No Virtual address for ULP : %d\n",
3019 ulp_num);
3020
3021 pasync_ctx->async_data.ring_base =
3022 mem_descr->mem_array[0].virtual_address;
6733b39a 3023
8a86e833
JK		 3024 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3025 mem_descr += HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
3026 (ulp_num * MEM_DESCR_OFFSET);
3027 if (!mem_descr->mem_array[0].virtual_address)
3028 beiscsi_log(phba, KERN_WARNING,
3029 BEISCSI_LOG_INIT,
3030 "BM_%d : No Virtual address for ULP : %d\n",
3031 ulp_num);
99bc5d55 3032
8a86e833
JK		 3033 pasync_ctx->async_data.handle_base =
3034 mem_descr->mem_array[0].virtual_address;
3035 pasync_ctx->async_data.writables = 0;
3036 INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
3037
3038 pasync_header_h =
3039 (struct async_pdu_handle *)
3040 pasync_ctx->async_header.handle_base;
3041 pasync_data_h =
3042 (struct async_pdu_handle *)
3043 pasync_ctx->async_data.handle_base;
3044
3045 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3046 mem_descr += HWI_MEM_ASYNC_DATA_BUF_ULP0 +
3047 (ulp_num * MEM_DESCR_OFFSET);
3048 if (mem_descr->mem_array[0].virtual_address) {
3049 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3050 "BM_%d : hwi_init_async_pdu_ctx"
3051 " HWI_MEM_ASYNC_DATA_BUF_ULP%d va=%p\n",
3052 ulp_num,
3053 mem_descr->mem_array[0].
3054 virtual_address);
3055 } else
3056 beiscsi_log(phba, KERN_WARNING,
3057 BEISCSI_LOG_INIT,
3058 "BM_%d : No Virtual address for ULP : %d\n",
3059 ulp_num);
3060
3061 idx = 0;
dc63aac6
JK		 3062 pasync_ctx->async_data.va_base =
3063 mem_descr->mem_array[idx].virtual_address;
3064 pasync_ctx->async_data.pa_base.u.a64.address =
3065 mem_descr->mem_array[idx].
3066 bus_address.u.a64.address;
3067
3068 num_async_data = ((mem_descr->mem_array[idx].size) /
3069 phba->params.defpdu_data_sz);
8a86e833 3070 num_per_mem = 0;
6733b39a 3071
8a86e833
JK		 3072 for (index = 0; index < BEISCSI_GET_CID_COUNT
3073 (phba, ulp_num); index++) {
3074 pasync_header_h->cri = -1;
3075 pasync_header_h->index = (char)index;
3076 INIT_LIST_HEAD(&pasync_header_h->link);
3077 pasync_header_h->pbuffer =
3078 (void *)((unsigned long)
3079 (pasync_ctx->
3080 async_header.va_base) +
3081 (p->defpdu_hdr_sz * index));
3082
3083 pasync_header_h->pa.u.a64.address =
3084 pasync_ctx->async_header.pa_base.u.a64.
3085 address + (p->defpdu_hdr_sz * index);
3086
3087 list_add_tail(&pasync_header_h->link,
3088 &pasync_ctx->async_header.
3089 free_list);
3090 pasync_header_h++;
3091 pasync_ctx->async_header.free_entries++;
3092 pasync_ctx->async_header.writables++;
3093
3094 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
3095 wait_queue.list);
3096 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
3097 header_busy_list);
3098 pasync_data_h->cri = -1;
3099 pasync_data_h->index = (char)index;
3100 INIT_LIST_HEAD(&pasync_data_h->link);
3101
3102 if (!num_async_data) {
3103 num_per_mem = 0;
3104 idx++;
3105 pasync_ctx->async_data.va_base =
3106 mem_descr->mem_array[idx].
3107 virtual_address;
3108 pasync_ctx->async_data.pa_base.u.
3109 a64.address =
3110 mem_descr->mem_array[idx].
3111 bus_address.u.a64.address;
3112 num_async_data =
3113 ((mem_descr->mem_array[idx].
3114 size) /
3115 phba->params.defpdu_data_sz);
3116 }
3117 pasync_data_h->pbuffer =
3118 (void *)((unsigned long)
3119 (pasync_ctx->async_data.va_base) +
3120 (p->defpdu_data_sz * num_per_mem));
3121
3122 pasync_data_h->pa.u.a64.address =
3123 pasync_ctx->async_data.pa_base.u.a64.
3124 address + (p->defpdu_data_sz *
3125 num_per_mem);
3126 num_per_mem++;
3127 num_async_data--;
3128
3129 list_add_tail(&pasync_data_h->link,
3130 &pasync_ctx->async_data.
3131 free_list);
3132 pasync_data_h++;
3133 pasync_ctx->async_data.free_entries++;
3134 pasync_ctx->async_data.writables++;
3135
3136 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
3137 data_busy_list);
3138 }
6733b39a 3139
8a86e833
JK		 3140 pasync_ctx->async_header.host_write_ptr = 0;
3141 pasync_ctx->async_header.ep_read_ptr = -1;
3142 pasync_ctx->async_data.host_write_ptr = 0;
3143 pasync_ctx->async_data.ep_read_ptr = -1;
3144 }
6733b39a
JK		 3145 }
3146
a7909b39 3147 return 0;
6733b39a
JK		 3148}
3149
3150static int
3151be_sgl_create_contiguous(void *virtual_address,
3152 u64 physical_address, u32 length,
3153 struct be_dma_mem *sgl)
3154{
3155 WARN_ON(!virtual_address);
3156 WARN_ON(!physical_address);
dd29dae0 3157 WARN_ON(!length);
6733b39a
JK		 3158 WARN_ON(!sgl);
3159
3160 sgl->va = virtual_address;
457ff3b7 3161 sgl->dma = (unsigned long)physical_address;
6733b39a
JK		 3162 sgl->size = length;
3163
3164 return 0;
3165}
3166
3167static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
3168{
3169 memset(sgl, 0, sizeof(*sgl));
3170}
3171
3172static void
3173hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
3174 struct mem_array *pmem, struct be_dma_mem *sgl)
3175{
3176 if (sgl->va)
3177 be_sgl_destroy_contiguous(sgl);
3178
3179 be_sgl_create_contiguous(pmem->virtual_address,
3180 pmem->bus_address.u.a64.address,
3181 pmem->size, sgl);
3182}
3183
3184static void
3185hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
3186 struct mem_array *pmem, struct be_dma_mem *sgl)
3187{
3188 if (sgl->va)
3189 be_sgl_destroy_contiguous(sgl);
3190
3191 be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
3192 pmem->bus_address.u.a64.address,
3193 pmem->size, sgl);
3194}
3195
3196static int be_fill_queue(struct be_queue_info *q,
3197 u16 len, u16 entry_size, void *vaddress)
3198{
3199 struct be_dma_mem *mem = &q->dma_mem;
3200
3201 memset(q, 0, sizeof(*q));
3202 q->len = len;
3203 q->entry_size = entry_size;
3204 mem->size = len * entry_size;
3205 mem->va = vaddress;
3206 if (!mem->va)
3207 return -ENOMEM;
3208 memset(mem->va, 0, mem->size);
3209 return 0;
3210}
3211
bfead3b2 3212static int beiscsi_create_eqs(struct beiscsi_hba *phba,
6733b39a
JK		 3213 struct hwi_context_memory *phwi_context)
3214{
bfead3b2 3215 unsigned int i, num_eq_pages;
99bc5d55 3216 int ret = 0, eq_for_mcc;
6733b39a
JK		 3217 struct be_queue_info *eq;
3218 struct be_dma_mem *mem;
6733b39a 3219 void *eq_vaddress;
bfead3b2 3220 dma_addr_t paddr;
6733b39a 3221
bfead3b2
JK		 3222 num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
3223 sizeof(struct be_eq_entry));
6733b39a 3224
bfead3b2
JK		 3225 if (phba->msix_enabled)
3226 eq_for_mcc = 1;
3227 else
3228 eq_for_mcc = 0;
3229 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
3230 eq = &phwi_context->be_eq[i].q;
3231 mem = &eq->dma_mem;
3232 phwi_context->be_eq[i].phba = phba;
3233 eq_vaddress = pci_alloc_consistent(phba->pcidev,
3234 num_eq_pages * PAGE_SIZE,
3235 &paddr);
3236 if (!eq_vaddress)
3237 goto create_eq_error;
3238
3239 mem->va = eq_vaddress;
3240 ret = be_fill_queue(eq, phba->params.num_eq_entries,
3241 sizeof(struct be_eq_entry), eq_vaddress);
3242 if (ret) {
99bc5d55
JSJ		 3243 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3244 "BM_%d : be_fill_queue Failed for EQ\n");
bfead3b2
JK		 3245 goto create_eq_error;
3246 }
6733b39a 3247
bfead3b2
JK		 3248 mem->dma = paddr;
3249 ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
3250 phwi_context->cur_eqd);
3251 if (ret) {
99bc5d55
JSJ		 3252 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3253 "BM_%d : beiscsi_cmd_eq_create"
3254 "Failed for EQ\n");
bfead3b2
JK		 3255 goto create_eq_error;
3256 }
99bc5d55
JSJ		 3257
3258 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3259 "BM_%d : eqid = %d\n",
3260 phwi_context->be_eq[i].q.id);
6733b39a 3261 }
6733b39a 3262 return 0;
bfead3b2 3263create_eq_error:
107dfcba 3264 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
bfead3b2
JK		 3265 eq = &phwi_context->be_eq[i].q;
3266 mem = &eq->dma_mem;
3267 if (mem->va)
3268 pci_free_consistent(phba->pcidev, num_eq_pages
3269 * PAGE_SIZE,
3270 mem->va, mem->dma);
3271 }
3272 return ret;
6733b39a
JK		 3273}
3274
bfead3b2 3275static int beiscsi_create_cqs(struct beiscsi_hba *phba,
6733b39a
JK		 3276 struct hwi_context_memory *phwi_context)
3277{
bfead3b2 3278 unsigned int i, num_cq_pages;
99bc5d55 3279 int ret = 0;
6733b39a
JK		 3280 struct be_queue_info *cq, *eq;
3281 struct be_dma_mem *mem;
bfead3b2 3282 struct be_eq_obj *pbe_eq;
6733b39a 3283 void *cq_vaddress;
bfead3b2 3284 dma_addr_t paddr;
6733b39a 3285
bfead3b2
JK		 3286 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
3287 sizeof(struct sol_cqe));
6733b39a 3288
bfead3b2
JK		 3289 for (i = 0; i < phba->num_cpus; i++) {
3290 cq = &phwi_context->be_cq[i];
3291 eq = &phwi_context->be_eq[i].q;
3292 pbe_eq = &phwi_context->be_eq[i];
3293 pbe_eq->cq = cq;
3294 pbe_eq->phba = phba;
3295 mem = &cq->dma_mem;
3296 cq_vaddress = pci_alloc_consistent(phba->pcidev,
3297 num_cq_pages * PAGE_SIZE,
3298 &paddr);
3299 if (!cq_vaddress)
3300 goto create_cq_error;
7da50879 3301 ret = be_fill_queue(cq, phba->params.num_cq_entries,
bfead3b2
JK		 3302 sizeof(struct sol_cqe), cq_vaddress);
3303 if (ret) {
99bc5d55
JSJ		 3304 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3305 "BM_%d : be_fill_queue Failed "
3306 "for ISCSI CQ\n");
bfead3b2
JK		 3307 goto create_cq_error;
3308 }
3309
3310 mem->dma = paddr;
3311 ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
3312 false, 0);
3313 if (ret) {
99bc5d55
JSJ		 3314 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3315 "BM_%d : beiscsi_cmd_eq_create"
3316 "Failed for ISCSI CQ\n");
bfead3b2
JK		 3317 goto create_cq_error;
3318 }
99bc5d55
JSJ		 3319 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3320 "BM_%d : iscsi cq_id is %d for eq_id %d\n"
3321 "iSCSI CQ CREATED\n", cq->id, eq->id);
6733b39a 3322 }
6733b39a 3323 return 0;
bfead3b2
JK		 3324
3325create_cq_error:
3326 for (i = 0; i < phba->num_cpus; i++) {
3327 cq = &phwi_context->be_cq[i];
3328 mem = &cq->dma_mem;
3329 if (mem->va)
3330 pci_free_consistent(phba->pcidev, num_cq_pages
3331 * PAGE_SIZE,
3332 mem->va, mem->dma);
3333 }
3334 return ret;
3335
6733b39a
JK		 3336}
3337
3338static int
3339beiscsi_create_def_hdr(struct beiscsi_hba *phba,
3340 struct hwi_context_memory *phwi_context,
3341 struct hwi_controller *phwi_ctrlr,
8a86e833 3342 unsigned int def_pdu_ring_sz, uint8_t ulp_num)
6733b39a
JK		 3343{
3344 unsigned int idx;
3345 int ret;
3346 struct be_queue_info *dq, *cq;
3347 struct be_dma_mem *mem;
3348 struct be_mem_descriptor *mem_descr;
3349 void *dq_vaddress;
3350
3351 idx = 0;
8a86e833 3352 dq = &phwi_context->be_def_hdrq[ulp_num];
bfead3b2 3353 cq = &phwi_context->be_cq[0];
6733b39a
JK		 3354 mem = &dq->dma_mem;
3355 mem_descr = phba->init_mem;
8a86e833
JK		 3356 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
3357 (ulp_num * MEM_DESCR_OFFSET);
6733b39a
JK		 3358 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
3359 ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
3360 sizeof(struct phys_addr),
3361 sizeof(struct phys_addr), dq_vaddress);
3362 if (ret) {
99bc5d55 3363 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3364 "BM_%d : be_fill_queue Failed for DEF PDU HDR on ULP : %d\n",
3365 ulp_num);
3366
6733b39a
JK		 3367 return ret;
3368 }
457ff3b7
JK		 3369 mem->dma = (unsigned long)mem_descr->mem_array[idx].
3370 bus_address.u.a64.address;
6733b39a
JK		 3371 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
3372 def_pdu_ring_sz,
8a86e833
JK		 3373 phba->params.defpdu_hdr_sz,
3374 BEISCSI_DEFQ_HDR, ulp_num);
6733b39a 3375 if (ret) {
99bc5d55 3376 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3377 "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR on ULP : %d\n",
3378 ulp_num);
3379
6733b39a
JK		 3380 return ret;
3381 }
99bc5d55 3382
8a86e833
JK		 3383 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3384 "BM_%d : iscsi hdr def pdu id for ULP : %d is %d\n",
3385 ulp_num,
3386 phwi_context->be_def_hdrq[ulp_num].id);
3387 hwi_post_async_buffers(phba, BEISCSI_DEFQ_HDR, ulp_num);
6733b39a
JK		 3388 return 0;
3389}
3390
3391static int
3392beiscsi_create_def_data(struct beiscsi_hba *phba,
3393 struct hwi_context_memory *phwi_context,
3394 struct hwi_controller *phwi_ctrlr,
8a86e833 3395 unsigned int def_pdu_ring_sz, uint8_t ulp_num)
6733b39a
JK		 3396{
3397 unsigned int idx;
3398 int ret;
3399 struct be_queue_info *dataq, *cq;
3400 struct be_dma_mem *mem;
3401 struct be_mem_descriptor *mem_descr;
3402 void *dq_vaddress;
3403
3404 idx = 0;
8a86e833 3405 dataq = &phwi_context->be_def_dataq[ulp_num];
bfead3b2 3406 cq = &phwi_context->be_cq[0];
6733b39a
JK		 3407 mem = &dataq->dma_mem;
3408 mem_descr = phba->init_mem;
8a86e833
JK		 3409 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
3410 (ulp_num * MEM_DESCR_OFFSET);
6733b39a
JK		 3411 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
3412 ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
3413 sizeof(struct phys_addr),
3414 sizeof(struct phys_addr), dq_vaddress);
3415 if (ret) {
99bc5d55 3416 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3417 "BM_%d : be_fill_queue Failed for DEF PDU "
3418 "DATA on ULP : %d\n",
3419 ulp_num);
3420
6733b39a
JK		 3421 return ret;
3422 }
457ff3b7
JK		 3423 mem->dma = (unsigned long)mem_descr->mem_array[idx].
3424 bus_address.u.a64.address;
6733b39a
JK		 3425 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
3426 def_pdu_ring_sz,
8a86e833
JK		 3427 phba->params.defpdu_data_sz,
3428 BEISCSI_DEFQ_DATA, ulp_num);
6733b39a 3429 if (ret) {
99bc5d55
JSJ		 3430 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3431 "BM_%d be_cmd_create_default_pdu_queue"
8a86e833
JK		 3432 " Failed for DEF PDU DATA on ULP : %d\n",
3433 ulp_num);
6733b39a
JK		 3434 return ret;
3435 }
8a86e833 3436
99bc5d55 3437 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
8a86e833
JK		 3438 "BM_%d : iscsi def data id on ULP : %d is %d\n",
3439 ulp_num,
3440 phwi_context->be_def_dataq[ulp_num].id);
99bc5d55 3441
8a86e833 3442 hwi_post_async_buffers(phba, BEISCSI_DEFQ_DATA, ulp_num);
99bc5d55 3443 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
8a86e833
JK		 3444 "BM_%d : DEFAULT PDU DATA RING CREATED"
3445 "on ULP : %d\n", ulp_num);
99bc5d55 3446
6733b39a
JK		 3447 return 0;
3448}
3449
15a90fe0
JK		 3450
3451static int
3452beiscsi_post_template_hdr(struct beiscsi_hba *phba)
3453{
3454 struct be_mem_descriptor *mem_descr;
3455 struct mem_array *pm_arr;
3456 struct be_dma_mem sgl;
a129d92f 3457 int status, ulp_num;
15a90fe0 3458
a129d92f
JK		 3459 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3460 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3461 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3462 mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 +
3463 (ulp_num * MEM_DESCR_OFFSET);
3464 pm_arr = mem_descr->mem_array;
15a90fe0 3465
a129d92f
JK		 3466 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
3467 status = be_cmd_iscsi_post_template_hdr(
3468 &phba->ctrl, &sgl);
15a90fe0 3469
a129d92f
JK		 3470 if (status != 0) {
3471 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3472 "BM_%d : Post Template HDR Failed for"
3473 "ULP_%d\n", ulp_num);
3474 return status;
3475 }
3476
3477 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3478 "BM_%d : Template HDR Pages Posted for"
3479 "ULP_%d\n", ulp_num);
15a90fe0
JK		 3480 }
3481 }
15a90fe0
JK		 3482 return 0;
3483}
3484
6733b39a
JK		 3485static int
3486beiscsi_post_pages(struct beiscsi_hba *phba)
3487{
3488 struct be_mem_descriptor *mem_descr;
3489 struct mem_array *pm_arr;
3490 unsigned int page_offset, i;
3491 struct be_dma_mem sgl;
843ae752 3492 int status, ulp_num = 0;
6733b39a
JK		 3493
3494 mem_descr = phba->init_mem;
3495 mem_descr += HWI_MEM_SGE;
3496 pm_arr = mem_descr->mem_array;
3497
90622db3
JK		 3498 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3499 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
3500 break;
3501
6733b39a 3502 page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
843ae752 3503 phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE;
6733b39a
JK		 3504 for (i = 0; i < mem_descr->num_elements; i++) {
3505 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
3506 status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
3507 page_offset,
3508 (pm_arr->size / PAGE_SIZE));
3509 page_offset += pm_arr->size / PAGE_SIZE;
3510 if (status != 0) {
99bc5d55
JSJ		 3511 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3512 "BM_%d : post sgl failed.\n");
6733b39a
JK		 3513 return status;
3514 }
3515 pm_arr++;
3516 }
99bc5d55
JSJ		 3517 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3518 "BM_%d : POSTED PAGES\n");
6733b39a
JK		 3519 return 0;
3520}
3521
bfead3b2
JK		 3522static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
3523{
3524 struct be_dma_mem *mem = &q->dma_mem;
c8b25598 3525 if (mem->va) {
bfead3b2
JK		 3526 pci_free_consistent(phba->pcidev, mem->size,
3527 mem->va, mem->dma);
c8b25598
JK		 3528 mem->va = NULL;
3529 }
bfead3b2
JK		 3530}
3531
3532static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
3533 u16 len, u16 entry_size)
3534{
3535 struct be_dma_mem *mem = &q->dma_mem;
3536
3537 memset(q, 0, sizeof(*q));
3538 q->len = len;
3539 q->entry_size = entry_size;
3540 mem->size = len * entry_size;
7c845eb5 3541 mem->va = pci_zalloc_consistent(phba->pcidev, mem->size, &mem->dma);
bfead3b2 3542 if (!mem->va)
d3ad2bb3 3543 return -ENOMEM;
bfead3b2
JK		 3544 return 0;
3545}
3546
6733b39a
JK		 3547static int
3548beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
3549 struct hwi_context_memory *phwi_context,
3550 struct hwi_controller *phwi_ctrlr)
3551{
3552 unsigned int wrb_mem_index, offset, size, num_wrb_rings;
3553 u64 pa_addr_lo;
4eea99d5 3554 unsigned int idx, num, i, ulp_num;
6733b39a
JK		 3555 struct mem_array *pwrb_arr;
3556 void *wrb_vaddr;
3557 struct be_dma_mem sgl;
3558 struct be_mem_descriptor *mem_descr;
a7909b39 3559 struct hwi_wrb_context *pwrb_context;
6733b39a 3560 int status;
4eea99d5
JK		 3561 uint8_t ulp_count = 0, ulp_base_num = 0;
3562 uint16_t cid_count_ulp[BEISCSI_ULP_COUNT] = { 0 };
6733b39a
JK		 3563
3564 idx = 0;
3565 mem_descr = phba->init_mem;
3566 mem_descr += HWI_MEM_WRB;
3567 pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
3568 GFP_KERNEL);
3569 if (!pwrb_arr) {
99bc5d55
JSJ		 3570 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3571 "BM_%d : Memory alloc failed in create wrb ring.\n");
6733b39a
JK		 3572 return -ENOMEM;
3573 }
3574 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
3575 pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
3576 num_wrb_rings = mem_descr->mem_array[idx].size /
3577 (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
3578
3579 for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
3580 if (num_wrb_rings) {
3581 pwrb_arr[num].virtual_address = wrb_vaddr;
3582 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
3583 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
3584 sizeof(struct iscsi_wrb);
3585 wrb_vaddr += pwrb_arr[num].size;
3586 pa_addr_lo += pwrb_arr[num].size;
3587 num_wrb_rings--;
3588 } else {
3589 idx++;
3590 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
3591 pa_addr_lo = mem_descr->mem_array[idx].\
3592 bus_address.u.a64.address;
3593 num_wrb_rings = mem_descr->mem_array[idx].size /
3594 (phba->params.wrbs_per_cxn *
3595 sizeof(struct iscsi_wrb));
3596 pwrb_arr[num].virtual_address = wrb_vaddr;
3597 pwrb_arr[num].bus_address.u.a64.address\
3598 = pa_addr_lo;
3599 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
3600 sizeof(struct iscsi_wrb);
3601 wrb_vaddr += pwrb_arr[num].size;
3602 pa_addr_lo += pwrb_arr[num].size;
3603 num_wrb_rings--;
3604 }
3605 }
4eea99d5
JK		 3606
3607 /* Get the ULP Count */
3608 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3609 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3610 ulp_count++;
3611 ulp_base_num = ulp_num;
3612 cid_count_ulp[ulp_num] =
3613 BEISCSI_GET_CID_COUNT(phba, ulp_num);
3614 }
3615
6733b39a
JK		 3616 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3617 wrb_mem_index = 0;
3618 offset = 0;
3619 size = 0;
3620
4eea99d5
JK		 3621 if (ulp_count > 1) {
3622 ulp_base_num = (ulp_base_num + 1) % BEISCSI_ULP_COUNT;
3623
3624 if (!cid_count_ulp[ulp_base_num])
3625 ulp_base_num = (ulp_base_num + 1) %
3626 BEISCSI_ULP_COUNT;
3627
3628 cid_count_ulp[ulp_base_num]--;
3629 }
3630
3631
6733b39a
JK		 3632 hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
3633 status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
4eea99d5
JK		 3634 &phwi_context->be_wrbq[i],
3635 &phwi_ctrlr->wrb_context[i],
3636 ulp_base_num);
6733b39a 3637 if (status != 0) {
99bc5d55
JSJ		 3638 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3639 "BM_%d : wrbq create failed.");
1462b8ff 3640 kfree(pwrb_arr);
6733b39a
JK		 3641 return status;
3642 }
a7909b39 3643 pwrb_context = &phwi_ctrlr->wrb_context[i];
a7909b39 3644 BE_SET_CID_TO_CRI(i, pwrb_context->cid);
6733b39a
JK		 3645 }
3646 kfree(pwrb_arr);
3647 return 0;
3648}
3649
3650static void free_wrb_handles(struct beiscsi_hba *phba)
3651{
3652 unsigned int index;
3653 struct hwi_controller *phwi_ctrlr;
3654 struct hwi_wrb_context *pwrb_context;
3655
3656 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 3657 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a
JK		 3658 pwrb_context = &phwi_ctrlr->wrb_context[index];
3659 kfree(pwrb_context->pwrb_handle_base);
3660 kfree(pwrb_context->pwrb_handle_basestd);
3661 }
3662}
3663
bfead3b2
JK		 3664static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
3665{
3666 struct be_queue_info *q;
3667 struct be_ctrl_info *ctrl = &phba->ctrl;
3668
3669 q = &phba->ctrl.mcc_obj.q;
4e2bdf7a 3670 if (q->created) {
bfead3b2 3671 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
4e2bdf7a
JSJ		 3672 be_queue_free(phba, q);
3673 }
bfead3b2
JK		 3674
3675 q = &phba->ctrl.mcc_obj.cq;
4e2bdf7a 3676 if (q->created) {
bfead3b2 3677 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
4e2bdf7a
JSJ		 3678 be_queue_free(phba, q);
3679 }
bfead3b2
JK		 3680}
3681
6733b39a
JK		 3682static void hwi_cleanup(struct beiscsi_hba *phba)
3683{
3684 struct be_queue_info *q;
3685 struct be_ctrl_info *ctrl = &phba->ctrl;
3686 struct hwi_controller *phwi_ctrlr;
3687 struct hwi_context_memory *phwi_context;
a7909b39 3688 struct hwi_async_pdu_context *pasync_ctx;
23188167 3689 int i, eq_for_mcc, ulp_num;
6733b39a
JK		 3690
3691 phwi_ctrlr = phba->phwi_ctrlr;
3692 phwi_context = phwi_ctrlr->phwi_ctxt;
15a90fe0
JK		 3693
3694 be_cmd_iscsi_remove_template_hdr(ctrl);
3695
6733b39a
JK		 3696 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3697 q = &phwi_context->be_wrbq[i];
3698 if (q->created)
3699 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
3700 }
a7909b39 3701 kfree(phwi_context->be_wrbq);
6733b39a
JK		 3702 free_wrb_handles(phba);
3703
8a86e833
JK		 3704 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3705 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 3706
8a86e833
JK		 3707 q = &phwi_context->be_def_hdrq[ulp_num];
3708 if (q->created)
3709 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3710
3711 q = &phwi_context->be_def_dataq[ulp_num];
3712 if (q->created)
3713 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3714
3715 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
3716 }
3717 }
6733b39a
JK		 3718
3719 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
3720
bfead3b2
JK		 3721 for (i = 0; i < (phba->num_cpus); i++) {
3722 q = &phwi_context->be_cq[i];
4e2bdf7a
JSJ		 3723 if (q->created) {
3724 be_queue_free(phba, q);
bfead3b2 3725 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
4e2bdf7a 3726 }
bfead3b2 3727 }
23188167
JK		 3728
3729 be_mcc_queues_destroy(phba);
bfead3b2 3730 if (phba->msix_enabled)
23188167 3731 eq_for_mcc = 1;
bfead3b2 3732 else
23188167
JK		 3733 eq_for_mcc = 0;
3734 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
bfead3b2 3735 q = &phwi_context->be_eq[i].q;
4e2bdf7a
JSJ		 3736 if (q->created) {
3737 be_queue_free(phba, q);
bfead3b2 3738 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
4e2bdf7a 3739 }
bfead3b2 3740 }
0283fbb1 3741 be_cmd_fw_uninit(ctrl);
bfead3b2 3742}
6733b39a 3743
bfead3b2
JK		 3744static int be_mcc_queues_create(struct beiscsi_hba *phba,
3745 struct hwi_context_memory *phwi_context)
3746{
3747 struct be_queue_info *q, *cq;
3748 struct be_ctrl_info *ctrl = &phba->ctrl;
3749
3750 /* Alloc MCC compl queue */
3751 cq = &phba->ctrl.mcc_obj.cq;
3752 if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
3753 sizeof(struct be_mcc_compl)))
3754 goto err;
3755 /* Ask BE to create MCC compl queue; */
3756 if (phba->msix_enabled) {
3757 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
3758 [phba->num_cpus].q, false, true, 0))
3759 goto mcc_cq_free;
3760 } else {
3761 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
3762 false, true, 0))
3763 goto mcc_cq_free;
3764 }
3765
3766 /* Alloc MCC queue */
3767 q = &phba->ctrl.mcc_obj.q;
3768 if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
3769 goto mcc_cq_destroy;
3770
3771 /* Ask BE to create MCC queue */
35e66019 3772 if (beiscsi_cmd_mccq_create(phba, q, cq))
bfead3b2
JK		 3773 goto mcc_q_free;
3774
3775 return 0;
3776
3777mcc_q_free:
3778 be_queue_free(phba, q);
3779mcc_cq_destroy:
3780 beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
3781mcc_cq_free:
3782 be_queue_free(phba, cq);
3783err:
d3ad2bb3 3784 return -ENOMEM;
bfead3b2
JK		 3785}
3786
107dfcba
JSJ		 3787/**
3788 * find_num_cpus()- Get the CPU online count
3789 * @phba: ptr to priv structure
3790 *
3791 * CPU count is used for creating EQ.
3792 **/
3793static void find_num_cpus(struct beiscsi_hba *phba)
bfead3b2
JK		 3794{
3795 int num_cpus = 0;
3796
3797 num_cpus = num_online_cpus();
bfead3b2 3798
22abeef0
JSJ		 3799 switch (phba->generation) {
3800 case BE_GEN2:
3801 case BE_GEN3:
3802 phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
3803 BEISCSI_MAX_NUM_CPUS : num_cpus;
3804 break;
3805 case BE_GEN4:
68c26a3a
JK		 3806 /*
3807 * If eqid_count == 1 fall back to
3808 * INTX mechanism
3809 **/
3810 if (phba->fw_config.eqid_count == 1) {
3811 enable_msix = 0;
3812 phba->num_cpus = 1;
3813 return;
3814 }
3815
3816 phba->num_cpus =
3817 (num_cpus > (phba->fw_config.eqid_count - 1)) ?
3818 (phba->fw_config.eqid_count - 1) : num_cpus;
22abeef0
JSJ		 3819 break;
3820 default:
3821 phba->num_cpus = 1;
3822 }
6733b39a
JK		 3823}
3824
3825static int hwi_init_port(struct beiscsi_hba *phba)
3826{
3827 struct hwi_controller *phwi_ctrlr;
3828 struct hwi_context_memory *phwi_context;
3829 unsigned int def_pdu_ring_sz;
3830 struct be_ctrl_info *ctrl = &phba->ctrl;
8a86e833 3831 int status, ulp_num;
6733b39a 3832
6733b39a 3833 phwi_ctrlr = phba->phwi_ctrlr;
6733b39a 3834 phwi_context = phwi_ctrlr->phwi_ctxt;
73af08e1 3835 phwi_context->max_eqd = 128;
bfead3b2 3836 phwi_context->min_eqd = 0;
73af08e1 3837 phwi_context->cur_eqd = 0;
6733b39a 3838 be_cmd_fw_initialize(&phba->ctrl);
53aefe25
JB		 3839 /* set optic state to unknown */
3840 phba->optic_state = 0xff;
bfead3b2
JK		 3841
3842 status = beiscsi_create_eqs(phba, phwi_context);
6733b39a 3843 if (status != 0) {
99bc5d55
JSJ		 3844 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3845 "BM_%d : EQ not created\n");
6733b39a
JK		 3846 goto error;
3847 }
3848
bfead3b2
JK		 3849 status = be_mcc_queues_create(phba, phwi_context);
3850 if (status != 0)
3851 goto error;
3852
3853 status = mgmt_check_supported_fw(ctrl, phba);
6733b39a 3854 if (status != 0) {
99bc5d55
JSJ		 3855 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3856 "BM_%d : Unsupported fw version\n");
6733b39a
JK		 3857 goto error;
3858 }
3859
bfead3b2 3860 status = beiscsi_create_cqs(phba, phwi_context);
6733b39a 3861 if (status != 0) {
99bc5d55
JSJ		 3862 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3863 "BM_%d : CQ not created\n");
6733b39a
JK		 3864 goto error;
3865 }
3866
8a86e833
JK		 3867 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3868 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 3869
8a86e833
JK		 3870 def_pdu_ring_sz =
3871 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
3872 sizeof(struct phys_addr);
3873
3874 status = beiscsi_create_def_hdr(phba, phwi_context,
3875 phwi_ctrlr,
3876 def_pdu_ring_sz,
3877 ulp_num);
3878 if (status != 0) {
3879 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3880 "BM_%d : Default Header not created for ULP : %d\n",
3881 ulp_num);
3882 goto error;
3883 }
3884
3885 status = beiscsi_create_def_data(phba, phwi_context,
3886 phwi_ctrlr,
3887 def_pdu_ring_sz,
3888 ulp_num);
3889 if (status != 0) {
3890 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3891 "BM_%d : Default Data not created for ULP : %d\n",
3892 ulp_num);
3893 goto error;
3894 }
3895 }
6733b39a
JK		 3896 }
3897
3898 status = beiscsi_post_pages(phba);
3899 if (status != 0) {
99bc5d55
JSJ		 3900 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3901 "BM_%d : Post SGL Pages Failed\n");
6733b39a
JK		 3902 goto error;
3903 }
3904
15a90fe0
JK		 3905 status = beiscsi_post_template_hdr(phba);
3906 if (status != 0) {
3907 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3908 "BM_%d : Template HDR Posting for CXN Failed\n");
3909 }
3910
6733b39a
JK		 3911 status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
3912 if (status != 0) {
99bc5d55
JSJ		 3913 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3914 "BM_%d : WRB Rings not created\n");
6733b39a
JK		 3915 goto error;
3916 }
3917
8a86e833
JK		 3918 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3919 uint16_t async_arr_idx = 0;
3920
3921 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3922 uint16_t cri = 0;
3923 struct hwi_async_pdu_context *pasync_ctx;
3924
3925 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(
3926 phwi_ctrlr, ulp_num);
3927 for (cri = 0; cri <
3928 phba->params.cxns_per_ctrl; cri++) {
3929 if (ulp_num == BEISCSI_GET_ULP_FROM_CRI
3930 (phwi_ctrlr, cri))
3931 pasync_ctx->cid_to_async_cri_map[
3932 phwi_ctrlr->wrb_context[cri].cid] =
3933 async_arr_idx++;
3934 }
3935 }
3936 }
3937
99bc5d55
JSJ		 3938 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3939 "BM_%d : hwi_init_port success\n");
6733b39a
JK		 3940 return 0;
3941
3942error:
99bc5d55
JSJ		 3943 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3944 "BM_%d : hwi_init_port failed");
6733b39a 3945 hwi_cleanup(phba);
a49e06d5 3946 return status;
6733b39a
JK		 3947}
3948
6733b39a
JK		 3949static int hwi_init_controller(struct beiscsi_hba *phba)
3950{
3951 struct hwi_controller *phwi_ctrlr;
3952
3953 phwi_ctrlr = phba->phwi_ctrlr;
3954 if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
3955 phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
3956 init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
99bc5d55
JSJ		 3957 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3958 "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
3959 phwi_ctrlr->phwi_ctxt);
6733b39a 3960 } else {
99bc5d55
JSJ		 3961 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3962 "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
3963 "than one element.Failing to load\n");
6733b39a
JK		 3964 return -ENOMEM;
3965 }
3966
3967 iscsi_init_global_templates(phba);
3ec78271
JK		 3968 if (beiscsi_init_wrb_handle(phba))
3969 return -ENOMEM;
3970
a7909b39
JK		 3971 if (hwi_init_async_pdu_ctx(phba)) {
3972 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3973 "BM_%d : hwi_init_async_pdu_ctx failed\n");
3974 return -ENOMEM;
3975 }
3976
6733b39a 3977 if (hwi_init_port(phba) != 0) {
99bc5d55
JSJ		 3978 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3979 "BM_%d : hwi_init_controller failed\n");
3980
6733b39a
JK		 3981 return -ENOMEM;
3982 }
3983 return 0;
3984}
3985
3986static void beiscsi_free_mem(struct beiscsi_hba *phba)
3987{
3988 struct be_mem_descriptor *mem_descr;
3989 int i, j;
3990
3991 mem_descr = phba->init_mem;
3992 i = 0;
3993 j = 0;
3994 for (i = 0; i < SE_MEM_MAX; i++) {
3995 for (j = mem_descr->num_elements; j > 0; j--) {
3996 pci_free_consistent(phba->pcidev,
3997 mem_descr->mem_array[j - 1].size,
3998 mem_descr->mem_array[j - 1].virtual_address,
457ff3b7
JK		 3999 (unsigned long)mem_descr->mem_array[j - 1].
4000 bus_address.u.a64.address);
6733b39a 4001 }
8a86e833 4002
6733b39a
JK		 4003 kfree(mem_descr->mem_array);
4004 mem_descr++;
4005 }
4006 kfree(phba->init_mem);
a7909b39 4007 kfree(phba->phwi_ctrlr->wrb_context);
6733b39a
JK		 4008 kfree(phba->phwi_ctrlr);
4009}
4010
4011static int beiscsi_init_controller(struct beiscsi_hba *phba)
4012{
4013 int ret = -ENOMEM;
4014
4015 ret = beiscsi_get_memory(phba);
4016 if (ret < 0) {
99bc5d55
JSJ		 4017 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4018 "BM_%d : beiscsi_dev_probe -"
4019 "Failed in beiscsi_alloc_memory\n");
6733b39a
JK		 4020 return ret;
4021 }
4022
4023 ret = hwi_init_controller(phba);
4024 if (ret)
4025 goto free_init;
99bc5d55
JSJ		 4026 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4027 "BM_%d : Return success from beiscsi_init_controller");
4028
6733b39a
JK		 4029 return 0;
4030
4031free_init:
4032 beiscsi_free_mem(phba);
a49e06d5 4033 return ret;
6733b39a
JK		 4034}
4035
4036static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
4037{
4038 struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
4039 struct sgl_handle *psgl_handle;
4040 struct iscsi_sge *pfrag;
90622db3
JK		 4041 unsigned int arr_index, i, idx;
4042 unsigned int ulp_icd_start, ulp_num = 0;
6733b39a
JK		 4043
4044 phba->io_sgl_hndl_avbl = 0;
4045 phba->eh_sgl_hndl_avbl = 0;
bfead3b2 4046
6733b39a
JK		 4047 mem_descr_sglh = phba->init_mem;
4048 mem_descr_sglh += HWI_MEM_SGLH;
4049 if (1 == mem_descr_sglh->num_elements) {
4050 phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
4051 phba->params.ios_per_ctrl,
4052 GFP_KERNEL);
4053 if (!phba->io_sgl_hndl_base) {
99bc5d55
JSJ		 4054 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4055 "BM_%d : Mem Alloc Failed. Failing to load\n");
6733b39a
JK		 4056 return -ENOMEM;
4057 }
4058 phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
4059 (phba->params.icds_per_ctrl -
4060 phba->params.ios_per_ctrl),
4061 GFP_KERNEL);
4062 if (!phba->eh_sgl_hndl_base) {
4063 kfree(phba->io_sgl_hndl_base);
99bc5d55
JSJ		 4064 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4065 "BM_%d : Mem Alloc Failed. Failing to load\n");
6733b39a
JK		 4066 return -ENOMEM;
4067 }
4068 } else {
99bc5d55
JSJ		 4069 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4070 "BM_%d : HWI_MEM_SGLH is more than one element."
4071 "Failing to load\n");
6733b39a
JK		 4072 return -ENOMEM;
4073 }
4074
4075 arr_index = 0;
4076 idx = 0;
4077 while (idx < mem_descr_sglh->num_elements) {
4078 psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
4079
4080 for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
4081 sizeof(struct sgl_handle)); i++) {
4082 if (arr_index < phba->params.ios_per_ctrl) {
4083 phba->io_sgl_hndl_base[arr_index] = psgl_handle;
4084 phba->io_sgl_hndl_avbl++;
4085 arr_index++;
4086 } else {
4087 phba->eh_sgl_hndl_base[arr_index -
4088 phba->params.ios_per_ctrl] =
4089 psgl_handle;
4090 arr_index++;
4091 phba->eh_sgl_hndl_avbl++;
4092 }
4093 psgl_handle++;
4094 }
4095 idx++;
4096 }
99bc5d55
JSJ		 4097 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4098 "BM_%d : phba->io_sgl_hndl_avbl=%d"
4099 "phba->eh_sgl_hndl_avbl=%d\n",
4100 phba->io_sgl_hndl_avbl,
4101 phba->eh_sgl_hndl_avbl);
4102
6733b39a
JK		 4103 mem_descr_sg = phba->init_mem;
4104 mem_descr_sg += HWI_MEM_SGE;
99bc5d55
JSJ		 4105 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4106 "\n BM_%d : mem_descr_sg->num_elements=%d\n",
4107 mem_descr_sg->num_elements);
4108
90622db3
JK		 4109 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
4110 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
4111 break;
4112
4113 ulp_icd_start = phba->fw_config.iscsi_icd_start[ulp_num];
4114
6733b39a
JK		 4115 arr_index = 0;
4116 idx = 0;
4117 while (idx < mem_descr_sg->num_elements) {
4118 pfrag = mem_descr_sg->mem_array[idx].virtual_address;
4119
4120 for (i = 0;
4121 i < (mem_descr_sg->mem_array[idx].size) /
4122 (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
4123 i++) {
4124 if (arr_index < phba->params.ios_per_ctrl)
4125 psgl_handle = phba->io_sgl_hndl_base[arr_index];
4126 else
4127 psgl_handle = phba->eh_sgl_hndl_base[arr_index -
4128 phba->params.ios_per_ctrl];
4129 psgl_handle->pfrag = pfrag;
4130 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
4131 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
4132 pfrag += phba->params.num_sge_per_io;
90622db3 4133 psgl_handle->sgl_index = ulp_icd_start + arr_index++;
6733b39a
JK		 4134 }
4135 idx++;
4136 }
4137 phba->io_sgl_free_index = 0;
4138 phba->io_sgl_alloc_index = 0;
4139 phba->eh_sgl_free_index = 0;
4140 phba->eh_sgl_alloc_index = 0;
4141 return 0;
4142}
4143
4144static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
4145{
0a3db7c0
JK		 4146 int ret;
4147 uint16_t i, ulp_num;
4148 struct ulp_cid_info *ptr_cid_info = NULL;
6733b39a 4149
0a3db7c0
JK		 4150 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4151 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4152 ptr_cid_info = kzalloc(sizeof(struct ulp_cid_info),
4153 GFP_KERNEL);
4154
4155 if (!ptr_cid_info) {
4156 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4157 "BM_%d : Failed to allocate memory"
4158 "for ULP_CID_INFO for ULP : %d\n",
4159 ulp_num);
4160 ret = -ENOMEM;
4161 goto free_memory;
4162
4163 }
4164
4165 /* Allocate memory for CID array */
4166 ptr_cid_info->cid_array = kzalloc(sizeof(void *) *
4167 BEISCSI_GET_CID_COUNT(phba,
4168 ulp_num), GFP_KERNEL);
4169 if (!ptr_cid_info->cid_array) {
4170 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4171 "BM_%d : Failed to allocate memory"
4172 "for CID_ARRAY for ULP : %d\n",
4173 ulp_num);
4174 kfree(ptr_cid_info);
4175 ptr_cid_info = NULL;
4176 ret = -ENOMEM;
4177
4178 goto free_memory;
4179 }
4180 ptr_cid_info->avlbl_cids = BEISCSI_GET_CID_COUNT(
4181 phba, ulp_num);
4182
4183 /* Save the cid_info_array ptr */
4184 phba->cid_array_info[ulp_num] = ptr_cid_info;
4185 }
6733b39a 4186 }
c2462288 4187 phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
a7909b39 4188 phba->params.cxns_per_ctrl, GFP_KERNEL);
6733b39a 4189 if (!phba->ep_array) {
99bc5d55
JSJ		 4190 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4191 "BM_%d : Failed to allocate memory in "
4192 "hba_setup_cid_tbls\n");
0a3db7c0
JK		 4193 ret = -ENOMEM;
4194
4195 goto free_memory;
6733b39a 4196 }
a7909b39
JK		 4197
4198 phba->conn_table = kzalloc(sizeof(struct beiscsi_conn *) *
4199 phba->params.cxns_per_ctrl, GFP_KERNEL);
4200 if (!phba->conn_table) {
4201 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4202 "BM_%d : Failed to allocate memory in"
4203 "hba_setup_cid_tbls\n");
4204
a7909b39 4205 kfree(phba->ep_array);
a7909b39 4206 phba->ep_array = NULL;
0a3db7c0 4207 ret = -ENOMEM;
5f2d25ef
TH		 4208
4209 goto free_memory;
6733b39a 4210 }
a7909b39 4211
0a3db7c0
JK		 4212 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
4213 ulp_num = phba->phwi_ctrlr->wrb_context[i].ulp_num;
4214
4215 ptr_cid_info = phba->cid_array_info[ulp_num];
4216 ptr_cid_info->cid_array[ptr_cid_info->cid_alloc++] =
4217 phba->phwi_ctrlr->wrb_context[i].cid;
4218
4219 }
4220
4221 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4222 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4223 ptr_cid_info = phba->cid_array_info[ulp_num];
a7909b39 4224
0a3db7c0
JK		 4225 ptr_cid_info->cid_alloc = 0;
4226 ptr_cid_info->cid_free = 0;
4227 }
4228 }
6733b39a 4229 return 0;
0a3db7c0
JK		 4230
4231free_memory:
4232 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4233 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4234 ptr_cid_info = phba->cid_array_info[ulp_num];
4235
4236 if (ptr_cid_info) {
4237 kfree(ptr_cid_info->cid_array);
4238 kfree(ptr_cid_info);
4239 phba->cid_array_info[ulp_num] = NULL;
4240 }
4241 }
4242 }
4243
4244 return ret;
6733b39a
JK		 4245}
4246
238f6b72 4247static void hwi_enable_intr(struct beiscsi_hba *phba)
6733b39a
JK		 4248{
4249 struct be_ctrl_info *ctrl = &phba->ctrl;
4250 struct hwi_controller *phwi_ctrlr;
4251 struct hwi_context_memory *phwi_context;
4252 struct be_queue_info *eq;
4253 u8 __iomem *addr;
bfead3b2 4254 u32 reg, i;
6733b39a
JK		 4255 u32 enabled;
4256
4257 phwi_ctrlr = phba->phwi_ctrlr;
4258 phwi_context = phwi_ctrlr->phwi_ctxt;
4259
6733b39a
JK		 4260 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
4261 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
4262 reg = ioread32(addr);
6733b39a
JK		 4263
4264 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4265 if (!enabled) {
4266 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
99bc5d55
JSJ		 4267 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4268 "BM_%d : reg =x%08x addr=%p\n", reg, addr);
6733b39a 4269 iowrite32(reg, addr);
665d6d94
JK		 4270 }
4271
4272 if (!phba->msix_enabled) {
4273 eq = &phwi_context->be_eq[0].q;
99bc5d55
JSJ		 4274 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4275 "BM_%d : eq->id=%d\n", eq->id);
4276
665d6d94
JK		 4277 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
4278 } else {
4279 for (i = 0; i <= phba->num_cpus; i++) {
4280 eq = &phwi_context->be_eq[i].q;
99bc5d55
JSJ		 4281 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4282 "BM_%d : eq->id=%d\n", eq->id);
bfead3b2
JK		 4283 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
4284 }
c03af1ae 4285 }
6733b39a
JK		 4286}
4287
4288static void hwi_disable_intr(struct beiscsi_hba *phba)
4289{
4290 struct be_ctrl_info *ctrl = &phba->ctrl;
4291
4292 u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
4293 u32 reg = ioread32(addr);
4294
4295 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4296 if (enabled) {
4297 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4298 iowrite32(reg, addr);
4299 } else
99bc5d55
JSJ		 4300 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
4301 "BM_%d : In hwi_disable_intr, Already Disabled\n");
6733b39a
JK		 4302}
4303
9aef4200
JSJ		 4304/**
4305 * beiscsi_get_boot_info()- Get the boot session info
4306 * @phba: The device priv structure instance
4307 *
4308 * Get the boot target info and store in driver priv structure
4309 *
4310 * return values
4311 * Success: 0
4312 * Failure: Non-Zero Value
4313 **/
c7acc5b8
JK		 4314static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
4315{
0e43895e 4316 struct be_cmd_get_session_resp *session_resp;
c7acc5b8 4317 struct be_dma_mem nonemb_cmd;
e175defe 4318 unsigned int tag;
9aef4200 4319 unsigned int s_handle;
f457a46f 4320 int ret = -ENOMEM;
c7acc5b8 4321
9aef4200
JSJ		 4322 /* Get the session handle of the boot target */
4323 ret = be_mgmt_get_boot_shandle(phba, &s_handle);
4324 if (ret) {
99bc5d55
JSJ		 4325 beiscsi_log(phba, KERN_ERR,
4326 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
4327 "BM_%d : No boot session\n");
3efde862
JSJ		 4328
4329 if (ret == -ENXIO)
4330 phba->get_boot = 0;
4331
4332
9aef4200 4333 return ret;
c7acc5b8 4334 }
3efde862 4335 phba->get_boot = 0;
7c845eb5
JP		 4336 nonemb_cmd.va = pci_zalloc_consistent(phba->ctrl.pdev,
4337 sizeof(*session_resp),
4338 &nonemb_cmd.dma);
c7acc5b8 4339 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 4340 beiscsi_log(phba, KERN_ERR,
4341 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
4342 "BM_%d : Failed to allocate memory for"
4343 "beiscsi_get_session_info\n");
4344
c7acc5b8
JK		 4345 return -ENOMEM;
4346 }
4347
9aef4200 4348 tag = mgmt_get_session_info(phba, s_handle,
0e43895e 4349 &nonemb_cmd);
c7acc5b8 4350 if (!tag) {
99bc5d55
JSJ		 4351 beiscsi_log(phba, KERN_ERR,
4352 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
4353 "BM_%d : beiscsi_get_session_info"
4354 " Failed\n");
4355
c7acc5b8 4356 goto boot_freemem;
e175defe 4357 }
c7acc5b8 4358
88840332 4359 ret = beiscsi_mccq_compl_wait(phba, tag, NULL, &nonemb_cmd);
e175defe 4360 if (ret) {
99bc5d55
JSJ		 4361 beiscsi_log(phba, KERN_ERR,
4362 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
e175defe 4363 "BM_%d : beiscsi_get_session_info Failed");
1957aa7f
JK		 4364
4365 if (ret != -EBUSY)
4366 goto boot_freemem;
4367 else
4368 return ret;
c7acc5b8 4369 }
e175defe 4370
c7acc5b8 4371 session_resp = nonemb_cmd.va ;
f457a46f 4372
c7acc5b8
JK		 4373 memcpy(&phba->boot_sess, &session_resp->session_info,
4374 sizeof(struct mgmt_session_info));
3f4134c1
JSJ		 4375
4376 beiscsi_logout_fw_sess(phba,
4377 phba->boot_sess.session_handle);
f457a46f
MC		 4378 ret = 0;
4379
c7acc5b8
JK		 4380boot_freemem:
4381 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
4382 nonemb_cmd.va, nonemb_cmd.dma);
f457a46f
MC		 4383 return ret;
4384}
4385
4386static void beiscsi_boot_release(void *data)
4387{
4388 struct beiscsi_hba *phba = data;
4389
4390 scsi_host_put(phba->shost);
4391}
4392
4393static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
4394{
4395 struct iscsi_boot_kobj *boot_kobj;
4396
a3d313ea
JK		 4397 /* it has been created previously */
4398 if (phba->boot_kset)
4399 return 0;
4400
f457a46f
MC		 4401 /* get boot info using mgmt cmd */
4402 if (beiscsi_get_boot_info(phba))
4403 /* Try to see if we can carry on without this */
4404 return 0;
4405
4406 phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
4407 if (!phba->boot_kset)
4408 return -ENOMEM;
4409
4410 /* get a ref because the show function will ref the phba */
4411 if (!scsi_host_get(phba->shost))
4412 goto free_kset;
4413 boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
4414 beiscsi_show_boot_tgt_info,
4415 beiscsi_tgt_get_attr_visibility,
4416 beiscsi_boot_release);
4417 if (!boot_kobj)
4418 goto put_shost;
4419
4420 if (!scsi_host_get(phba->shost))
4421 goto free_kset;
4422 boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
4423 beiscsi_show_boot_ini_info,
4424 beiscsi_ini_get_attr_visibility,
4425 beiscsi_boot_release);
4426 if (!boot_kobj)
4427 goto put_shost;
4428
4429 if (!scsi_host_get(phba->shost))
4430 goto free_kset;
4431 boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
4432 beiscsi_show_boot_eth_info,
4433 beiscsi_eth_get_attr_visibility,
4434 beiscsi_boot_release);
4435 if (!boot_kobj)
4436 goto put_shost;
4437 return 0;
4438
4439put_shost:
4440 scsi_host_put(phba->shost);
4441free_kset:
4442 iscsi_boot_destroy_kset(phba->boot_kset);
84bd6499 4443 phba->boot_kset = NULL;
c7acc5b8
JK		 4444 return -ENOMEM;
4445}
4446
6733b39a
JK		 4447static int beiscsi_init_port(struct beiscsi_hba *phba)
4448{
4449 int ret;
4450
4451 ret = beiscsi_init_controller(phba);
4452 if (ret < 0) {
99bc5d55
JSJ		 4453 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4454 "BM_%d : beiscsi_dev_probe - Failed in"
4455 "beiscsi_init_controller\n");
6733b39a
JK		 4456 return ret;
4457 }
4458 ret = beiscsi_init_sgl_handle(phba);
4459 if (ret < 0) {
99bc5d55
JSJ		 4460 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4461 "BM_%d : beiscsi_dev_probe - Failed in"
4462 "beiscsi_init_sgl_handle\n");
6733b39a
JK		 4463 goto do_cleanup_ctrlr;
4464 }
4465
4466 if (hba_setup_cid_tbls(phba)) {
99bc5d55
JSJ		 4467 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4468 "BM_%d : Failed in hba_setup_cid_tbls\n");
6733b39a
JK		 4469 kfree(phba->io_sgl_hndl_base);
4470 kfree(phba->eh_sgl_hndl_base);
4471 goto do_cleanup_ctrlr;
4472 }
4473
4474 return ret;
4475
4476do_cleanup_ctrlr:
4477 hwi_cleanup(phba);
4478 return ret;
4479}
4480
4481static void hwi_purge_eq(struct beiscsi_hba *phba)
4482{
4483 struct hwi_controller *phwi_ctrlr;
4484 struct hwi_context_memory *phwi_context;
4485 struct be_queue_info *eq;
4486 struct be_eq_entry *eqe = NULL;
bfead3b2 4487 int i, eq_msix;
756d29c8 4488 unsigned int num_processed;
6733b39a
JK		 4489
4490 phwi_ctrlr = phba->phwi_ctrlr;
4491 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 4492 if (phba->msix_enabled)
4493 eq_msix = 1;
4494 else
4495 eq_msix = 0;
6733b39a 4496
bfead3b2
JK		 4497 for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
4498 eq = &phwi_context->be_eq[i].q;
6733b39a 4499 eqe = queue_tail_node(eq);
756d29c8 4500 num_processed = 0;
bfead3b2
JK		 4501 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
4502 & EQE_VALID_MASK) {
4503 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
4504 queue_tail_inc(eq);
4505 eqe = queue_tail_node(eq);
756d29c8 4506 num_processed++;
bfead3b2 4507 }
756d29c8
JK		 4508
4509 if (num_processed)
4510 hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
6733b39a
JK		 4511 }
4512}
4513
4514static void beiscsi_clean_port(struct beiscsi_hba *phba)
4515{
0a3db7c0
JK		 4516 int mgmt_status, ulp_num;
4517 struct ulp_cid_info *ptr_cid_info = NULL;
6733b39a 4518
bd41c2bd
JK		 4519 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4520 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4521 mgmt_status = mgmt_epfw_cleanup(phba, ulp_num);
4522 if (mgmt_status)
4523 beiscsi_log(phba, KERN_WARNING,
4524 BEISCSI_LOG_INIT,
4525 "BM_%d : mgmt_epfw_cleanup FAILED"
4526 " for ULP_%d\n", ulp_num);
4527 }
4528 }
756d29c8 4529
6733b39a 4530 hwi_purge_eq(phba);
756d29c8 4531 hwi_cleanup(phba);
6733b39a
JK		 4532 kfree(phba->io_sgl_hndl_base);
4533 kfree(phba->eh_sgl_hndl_base);
6733b39a 4534 kfree(phba->ep_array);
a7909b39 4535 kfree(phba->conn_table);
0a3db7c0
JK		 4536
4537 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4538 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4539 ptr_cid_info = phba->cid_array_info[ulp_num];
4540
4541 if (ptr_cid_info) {
4542 kfree(ptr_cid_info->cid_array);
4543 kfree(ptr_cid_info);
4544 phba->cid_array_info[ulp_num] = NULL;
4545 }
4546 }
4547 }
4548
6733b39a
JK		 4549}
4550
43f388b0
JK		 4551/**
4552 * beiscsi_free_mgmt_task_handles()- Free driver CXN resources
4553 * @beiscsi_conn: ptr to the conn to be cleaned up
4a4a11b9 4554 * @task: ptr to iscsi_task resource to be freed.
43f388b0
JK		 4555 *
4556 * Free driver mgmt resources binded to CXN.
4557 **/
4558void
4a4a11b9
JK		 4559beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
4560 struct iscsi_task *task)
43f388b0
JK		 4561{
4562 struct beiscsi_io_task *io_task;
4563 struct beiscsi_hba *phba = beiscsi_conn->phba;
4564 struct hwi_wrb_context *pwrb_context;
4565 struct hwi_controller *phwi_ctrlr;
a7909b39
JK		 4566 uint16_t cri_index = BE_GET_CRI_FROM_CID(
4567 beiscsi_conn->beiscsi_conn_cid);
43f388b0
JK		 4568
4569 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39
JK		 4570 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
4571
4a4a11b9 4572 io_task = task->dd_data;
43f388b0
JK		 4573
4574 if (io_task->pwrb_handle) {
4575 memset(io_task->pwrb_handle->pwrb, 0,
4576 sizeof(struct iscsi_wrb));
4577 free_wrb_handle(phba, pwrb_context,
4578 io_task->pwrb_handle);
4579 io_task->pwrb_handle = NULL;
4580 }
4581
4582 if (io_task->psgl_handle) {
43f388b0
JK		 4583 free_mgmt_sgl_handle(phba,
4584 io_task->psgl_handle);
43f388b0
JK		 4585 io_task->psgl_handle = NULL;
4586 }
4587
eb1c4692 4588 if (io_task->mtask_addr) {
43f388b0
JK		 4589 pci_unmap_single(phba->pcidev,
4590 io_task->mtask_addr,
4591 io_task->mtask_data_count,
4592 PCI_DMA_TODEVICE);
eb1c4692
JSJ		 4593 io_task->mtask_addr = 0;
4594 }
43f388b0
JK		 4595}
4596
d629c471
JSJ		 4597/**
4598 * beiscsi_cleanup_task()- Free driver resources of the task
4599 * @task: ptr to the iscsi task
4600 *
4601 **/
1282ab76
MC		 4602static void beiscsi_cleanup_task(struct iscsi_task *task)
4603{
4604 struct beiscsi_io_task *io_task = task->dd_data;
4605 struct iscsi_conn *conn = task->conn;
4606 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4607 struct beiscsi_hba *phba = beiscsi_conn->phba;
4608 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
4609 struct hwi_wrb_context *pwrb_context;
4610 struct hwi_controller *phwi_ctrlr;
a7909b39
JK		 4611 uint16_t cri_index = BE_GET_CRI_FROM_CID(
4612 beiscsi_conn->beiscsi_conn_cid);
1282ab76
MC		 4613
4614 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 4615 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
1282ab76
MC		 4616
4617 if (io_task->cmd_bhs) {
4618 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
4619 io_task->bhs_pa.u.a64.address);
4620 io_task->cmd_bhs = NULL;
4621 }
4622
4623 if (task->sc) {
4624 if (io_task->pwrb_handle) {
4625 free_wrb_handle(phba, pwrb_context,
4626 io_task->pwrb_handle);
4627 io_task->pwrb_handle = NULL;
4628 }
4629
4630 if (io_task->psgl_handle) {
1282ab76 4631 free_io_sgl_handle(phba, io_task->psgl_handle);
1282ab76
MC		 4632 io_task->psgl_handle = NULL;
4633 }
da334977
JK		 4634
4635 if (io_task->scsi_cmnd) {
4636 scsi_dma_unmap(io_task->scsi_cmnd);
4637 io_task->scsi_cmnd = NULL;
4638 }
1282ab76 4639 } else {
43f388b0 4640 if (!beiscsi_conn->login_in_progress)
4a4a11b9 4641 beiscsi_free_mgmt_task_handles(beiscsi_conn, task);
1282ab76
MC		 4642 }
4643}
4644
6733b39a
JK		 4645void
4646beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
4647 struct beiscsi_offload_params *params)
4648{
4649 struct wrb_handle *pwrb_handle;
340c99e9 4650 struct hwi_wrb_context *pwrb_context = NULL;
6733b39a 4651 struct beiscsi_hba *phba = beiscsi_conn->phba;
1282ab76
MC		 4652 struct iscsi_task *task = beiscsi_conn->task;
4653 struct iscsi_session *session = task->conn->session;
6733b39a
JK		 4654 u32 doorbell = 0;
4655
4656 /*
4657 * We can always use 0 here because it is reserved by libiscsi for
4658 * login/startup related tasks.
4659 */
1282ab76 4660 beiscsi_conn->login_in_progress = 0;
659743b0 4661 spin_lock_bh(&session->back_lock);
1282ab76 4662 beiscsi_cleanup_task(task);
659743b0 4663 spin_unlock_bh(&session->back_lock);
1282ab76 4664
340c99e9
JSJ		 4665 pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid,
4666 &pwrb_context);
6733b39a 4667
acb9693c 4668 /* Check for the adapter family */
2c9dfd36 4669 if (is_chip_be2_be3r(phba))
acb9693c 4670 beiscsi_offload_cxn_v0(params, pwrb_handle,
340c99e9
JSJ		 4671 phba->init_mem,
4672 pwrb_context);
2c9dfd36 4673 else
340c99e9
JSJ		 4674 beiscsi_offload_cxn_v2(params, pwrb_handle,
4675 pwrb_context);
6733b39a 4676
acb9693c
JSJ		 4677 be_dws_le_to_cpu(pwrb_handle->pwrb,
4678 sizeof(struct iscsi_target_context_update_wrb));
6733b39a
JK		 4679
4680 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 4681 doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
bfead3b2 4682 << DB_DEF_PDU_WRB_INDEX_SHIFT;
6733b39a 4683 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4684 iowrite32(doorbell, phba->db_va +
4685 beiscsi_conn->doorbell_offset);
cb564c6b
JB		 4686
4687 /*
4688 * There is no completion for CONTEXT_UPDATE. The completion of next
4689 * WRB posted guarantees FW's processing and DMA'ing of it.
4690 * Use beiscsi_put_wrb_handle to put it back in the pool which makes
4691 * sure zero'ing or reuse of the WRB only after wrbs_per_cxn.
4692 */
4693 beiscsi_put_wrb_handle(pwrb_context, pwrb_handle,
4694 phba->params.wrbs_per_cxn);
4695 beiscsi_log(phba, KERN_INFO,
4696 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4697 "BM_%d : put CONTEXT_UPDATE pwrb_handle=%p free_index=0x%x wrb_handles_available=%d\n",
4698 pwrb_handle, pwrb_context->free_index,
4699 pwrb_context->wrb_handles_available);
6733b39a
JK		 4700}
4701
4702static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
4703 int *index, int *age)
4704{
bfead3b2 4705 *index = (int)itt;
6733b39a
JK		 4706 if (age)
4707 *age = conn->session->age;
4708}
4709
4710/**
4711 * beiscsi_alloc_pdu - allocates pdu and related resources
4712 * @task: libiscsi task
4713 * @opcode: opcode of pdu for task
4714 *
4715 * This is called with the session lock held. It will allocate
4716 * the wrb and sgl if needed for the command. And it will prep
4717 * the pdu's itt. beiscsi_parse_pdu will later translate
4718 * the pdu itt to the libiscsi task itt.
4719 */
4720static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
4721{
4722 struct beiscsi_io_task *io_task = task->dd_data;
4723 struct iscsi_conn *conn = task->conn;
4724 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4725 struct beiscsi_hba *phba = beiscsi_conn->phba;
4726 struct hwi_wrb_context *pwrb_context;
4727 struct hwi_controller *phwi_ctrlr;
4728 itt_t itt;
a7909b39 4729 uint16_t cri_index = 0;
2afc95bf
JK		 4730 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
4731 dma_addr_t paddr;
6733b39a 4732
2afc95bf 4733 io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
bc7accec 4734 GFP_ATOMIC, &paddr);
2afc95bf
JK		 4735 if (!io_task->cmd_bhs)
4736 return -ENOMEM;
2afc95bf 4737 io_task->bhs_pa.u.a64.address = paddr;
bfead3b2 4738 io_task->libiscsi_itt = (itt_t)task->itt;
6733b39a
JK		 4739 io_task->conn = beiscsi_conn;
4740
4741 task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
4742 task->hdr_max = sizeof(struct be_cmd_bhs);
d2cecf0d 4743 io_task->psgl_handle = NULL;
3ec78271 4744 io_task->pwrb_handle = NULL;
6733b39a
JK		 4745
4746 if (task->sc) {
6733b39a 4747 io_task->psgl_handle = alloc_io_sgl_handle(phba);
8359c79b
JSJ		 4748 if (!io_task->psgl_handle) {
4749 beiscsi_log(phba, KERN_ERR,
4750 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4751 "BM_%d : Alloc of IO_SGL_ICD Failed"
4752 "for the CID : %d\n",
4753 beiscsi_conn->beiscsi_conn_cid);
2afc95bf 4754 goto free_hndls;
8359c79b 4755 }
d2cecf0d 4756 io_task->pwrb_handle = alloc_wrb_handle(phba,
340c99e9
JSJ		 4757 beiscsi_conn->beiscsi_conn_cid,
4758 &io_task->pwrb_context);
8359c79b
JSJ		 4759 if (!io_task->pwrb_handle) {
4760 beiscsi_log(phba, KERN_ERR,
4761 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4762 "BM_%d : Alloc of WRB_HANDLE Failed"
4763 "for the CID : %d\n",
4764 beiscsi_conn->beiscsi_conn_cid);
d2cecf0d 4765 goto free_io_hndls;
8359c79b 4766 }
6733b39a
JK		 4767 } else {
4768 io_task->scsi_cmnd = NULL;
d7aea67b 4769 if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
43f388b0 4770 beiscsi_conn->task = task;
6733b39a 4771 if (!beiscsi_conn->login_in_progress) {
6733b39a
JK		 4772 io_task->psgl_handle = (struct sgl_handle *)
4773 alloc_mgmt_sgl_handle(phba);
8359c79b
JSJ		 4774 if (!io_task->psgl_handle) {
4775 beiscsi_log(phba, KERN_ERR,
4776 BEISCSI_LOG_IO |
4777 BEISCSI_LOG_CONFIG,
4778 "BM_%d : Alloc of MGMT_SGL_ICD Failed"
4779 "for the CID : %d\n",
4780 beiscsi_conn->
4781 beiscsi_conn_cid);
2afc95bf 4782 goto free_hndls;
8359c79b 4783 }
2afc95bf 4784
6733b39a
JK		 4785 beiscsi_conn->login_in_progress = 1;
4786 beiscsi_conn->plogin_sgl_handle =
4787 io_task->psgl_handle;
d2cecf0d
JK		 4788 io_task->pwrb_handle =
4789 alloc_wrb_handle(phba,
340c99e9
JSJ		 4790 beiscsi_conn->beiscsi_conn_cid,
4791 &io_task->pwrb_context);
8359c79b
JSJ		 4792 if (!io_task->pwrb_handle) {
4793 beiscsi_log(phba, KERN_ERR,
4794 BEISCSI_LOG_IO |
4795 BEISCSI_LOG_CONFIG,
4796 "BM_%d : Alloc of WRB_HANDLE Failed"
4797 "for the CID : %d\n",
4798 beiscsi_conn->
4799 beiscsi_conn_cid);
4800 goto free_mgmt_hndls;
4801 }
d2cecf0d
JK		 4802 beiscsi_conn->plogin_wrb_handle =
4803 io_task->pwrb_handle;
4804
6733b39a
JK		 4805 } else {
4806 io_task->psgl_handle =
4807 beiscsi_conn->plogin_sgl_handle;
d2cecf0d
JK		 4808 io_task->pwrb_handle =
4809 beiscsi_conn->plogin_wrb_handle;
6733b39a
JK		 4810 }
4811 } else {
6733b39a 4812 io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
8359c79b
JSJ		 4813 if (!io_task->psgl_handle) {
4814 beiscsi_log(phba, KERN_ERR,
4815 BEISCSI_LOG_IO |
4816 BEISCSI_LOG_CONFIG,
4817 "BM_%d : Alloc of MGMT_SGL_ICD Failed"
4818 "for the CID : %d\n",
4819 beiscsi_conn->
4820 beiscsi_conn_cid);
2afc95bf 4821 goto free_hndls;
8359c79b 4822 }
d2cecf0d
JK		 4823 io_task->pwrb_handle =
4824 alloc_wrb_handle(phba,
340c99e9
JSJ		 4825 beiscsi_conn->beiscsi_conn_cid,
4826 &io_task->pwrb_context);
8359c79b
JSJ		 4827 if (!io_task->pwrb_handle) {
4828 beiscsi_log(phba, KERN_ERR,
4829 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4830 "BM_%d : Alloc of WRB_HANDLE Failed"
4831 "for the CID : %d\n",
4832 beiscsi_conn->beiscsi_conn_cid);
d2cecf0d 4833 goto free_mgmt_hndls;
8359c79b 4834 }
d2cecf0d 4835
6733b39a
JK		 4836 }
4837 }
bfead3b2
JK		 4838 itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
4839 wrb_index << 16) | (unsigned int)
4840 (io_task->psgl_handle->sgl_index));
32951dd8 4841 io_task->pwrb_handle->pio_handle = task;
bfead3b2 4842
6733b39a
JK		 4843 io_task->cmd_bhs->iscsi_hdr.itt = itt;
4844 return 0;
2afc95bf 4845
d2cecf0d 4846free_io_hndls:
d2cecf0d 4847 free_io_sgl_handle(phba, io_task->psgl_handle);
d2cecf0d
JK		 4848 goto free_hndls;
4849free_mgmt_hndls:
d2cecf0d 4850 free_mgmt_sgl_handle(phba, io_task->psgl_handle);
a7909b39 4851 io_task->psgl_handle = NULL;
2afc95bf
JK		 4852free_hndls:
4853 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39
JK		 4854 cri_index = BE_GET_CRI_FROM_CID(
4855 beiscsi_conn->beiscsi_conn_cid);
4856 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
d2cecf0d
JK		 4857 if (io_task->pwrb_handle)
4858 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
2afc95bf
JK		 4859 io_task->pwrb_handle = NULL;
4860 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
4861 io_task->bhs_pa.u.a64.address);
1282ab76 4862 io_task->cmd_bhs = NULL;
2afc95bf 4863 return -ENOMEM;
6733b39a 4864}
09a1093a
JSJ		 4865int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg,
4866 unsigned int num_sg, unsigned int xferlen,
4867 unsigned int writedir)
4868{
4869
4870 struct beiscsi_io_task *io_task = task->dd_data;
4871 struct iscsi_conn *conn = task->conn;
4872 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4873 struct beiscsi_hba *phba = beiscsi_conn->phba;
4874 struct iscsi_wrb *pwrb = NULL;
4875 unsigned int doorbell = 0;
4876
4877 pwrb = io_task->pwrb_handle->pwrb;
09a1093a 4878
09a1093a
JSJ		 4879 io_task->bhs_len = sizeof(struct be_cmd_bhs);
4880
4881 if (writedir) {
4882 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
4883 INI_WR_CMD);
4884 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1);
4885 } else {
4886 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
4887 INI_RD_CMD);
4888 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0);
4889 }
4890
4891 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2,
4892 type, pwrb);
4893
4894 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb,
4895 cpu_to_be16(*(unsigned short *)
4896 &io_task->cmd_bhs->iscsi_hdr.lun));
4897 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen);
4898 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
4899 io_task->pwrb_handle->wrb_index);
4900 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
4901 be32_to_cpu(task->cmdsn));
4902 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
4903 io_task->psgl_handle->sgl_index);
4904
4905 hwi_write_sgl_v2(pwrb, sg, num_sg, io_task);
4906 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
340c99e9
JSJ		 4907 io_task->pwrb_handle->wrb_index);
4908 if (io_task->pwrb_context->plast_wrb)
4909 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb,
4910 io_task->pwrb_context->plast_wrb,
4911 io_task->pwrb_handle->wrb_index);
4912 io_task->pwrb_context->plast_wrb = pwrb;
09a1093a
JSJ		 4913
4914 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4915
4916 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
4917 doorbell |= (io_task->pwrb_handle->wrb_index &
4918 DB_DEF_PDU_WRB_INDEX_MASK) <<
4919 DB_DEF_PDU_WRB_INDEX_SHIFT;
4920 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4921 iowrite32(doorbell, phba->db_va +
4922 beiscsi_conn->doorbell_offset);
09a1093a
JSJ		 4923 return 0;
4924}
6733b39a 4925
6733b39a
JK		 4926static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
4927 unsigned int num_sg, unsigned int xferlen,
4928 unsigned int writedir)
4929{
4930
4931 struct beiscsi_io_task *io_task = task->dd_data;
4932 struct iscsi_conn *conn = task->conn;
4933 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4934 struct beiscsi_hba *phba = beiscsi_conn->phba;
4935 struct iscsi_wrb *pwrb = NULL;
4936 unsigned int doorbell = 0;
4937
4938 pwrb = io_task->pwrb_handle->pwrb;
6733b39a
JK		 4939 io_task->bhs_len = sizeof(struct be_cmd_bhs);
4940
4941 if (writedir) {
32951dd8
JK		 4942 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4943 INI_WR_CMD);
6733b39a 4944 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
6733b39a 4945 } else {
32951dd8
JK		 4946 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4947 INI_RD_CMD);
6733b39a
JK		 4948 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
4949 }
6733b39a 4950
09a1093a
JSJ		 4951 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb,
4952 type, pwrb);
4953
6733b39a 4954 AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
dc63aac6
JK		 4955 cpu_to_be16(*(unsigned short *)
4956 &io_task->cmd_bhs->iscsi_hdr.lun));
6733b39a
JK		 4957 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
4958 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
4959 io_task->pwrb_handle->wrb_index);
4960 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
4961 be32_to_cpu(task->cmdsn));
4962 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
4963 io_task->psgl_handle->sgl_index);
4964
4965 hwi_write_sgl(pwrb, sg, num_sg, io_task);
4966
4967 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
340c99e9
JSJ		 4968 io_task->pwrb_handle->wrb_index);
4969 if (io_task->pwrb_context->plast_wrb)
4970 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb,
4971 io_task->pwrb_context->plast_wrb,
4972 io_task->pwrb_handle->wrb_index);
4973 io_task->pwrb_context->plast_wrb = pwrb;
4974
6733b39a
JK		 4975 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4976
4977 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 4978 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 4979 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
4980 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
4981
1e4be6ff
JK		 4982 iowrite32(doorbell, phba->db_va +
4983 beiscsi_conn->doorbell_offset);
6733b39a
JK		 4984 return 0;
4985}
4986
4987static int beiscsi_mtask(struct iscsi_task *task)
4988{
dafab8e0 4989 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 4990 struct iscsi_conn *conn = task->conn;
4991 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4992 struct beiscsi_hba *phba = beiscsi_conn->phba;
4993 struct iscsi_wrb *pwrb = NULL;
4994 unsigned int doorbell = 0;
dafab8e0 4995 unsigned int cid;
09a1093a 4996 unsigned int pwrb_typeoffset = 0;
e0493627 4997 int ret = 0;
6733b39a 4998
bfead3b2 4999 cid = beiscsi_conn->beiscsi_conn_cid;
6733b39a 5000 pwrb = io_task->pwrb_handle->pwrb;
caf818f1 5001 memset(pwrb, 0, sizeof(*pwrb));
09a1093a 5002
2c9dfd36 5003 if (is_chip_be2_be3r(phba)) {
09a1093a
JSJ		 5004 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
5005 be32_to_cpu(task->cmdsn));
5006 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
5007 io_task->pwrb_handle->wrb_index);
5008 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
5009 io_task->psgl_handle->sgl_index);
5010 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
5011 task->data_count);
5012 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
340c99e9
JSJ		 5013 io_task->pwrb_handle->wrb_index);
5014 if (io_task->pwrb_context->plast_wrb)
5015 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb,
5016 io_task->pwrb_context->plast_wrb,
5017 io_task->pwrb_handle->wrb_index);
5018 io_task->pwrb_context->plast_wrb = pwrb;
5019
09a1093a 5020 pwrb_typeoffset = BE_WRB_TYPE_OFFSET;
2c9dfd36
JK		 5021 } else {
5022 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
5023 be32_to_cpu(task->cmdsn));
5024 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
5025 io_task->pwrb_handle->wrb_index);
5026 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
5027 io_task->psgl_handle->sgl_index);
5028 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb,
5029 task->data_count);
5030 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
340c99e9
JSJ		 5031 io_task->pwrb_handle->wrb_index);
5032 if (io_task->pwrb_context->plast_wrb)
5033 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb,
5034 io_task->pwrb_context->plast_wrb,
5035 io_task->pwrb_handle->wrb_index);
5036 io_task->pwrb_context->plast_wrb = pwrb;
5037
2c9dfd36 5038 pwrb_typeoffset = SKH_WRB_TYPE_OFFSET;
09a1093a
JSJ		 5039 }
5040
dafab8e0 5041
6733b39a
JK		 5042 switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
5043 case ISCSI_OP_LOGIN:
6733b39a 5044 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
09a1093a 5045 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
e0493627 5046 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 5047 break;
5048 case ISCSI_OP_NOOP_OUT:
1390b01b 5049 if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
09a1093a 5050 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
2c9dfd36
JK		 5051 if (is_chip_be2_be3r(phba))
5052 AMAP_SET_BITS(struct amap_iscsi_wrb,
09a1093a
JSJ		 5053 dmsg, pwrb, 1);
5054 else
2c9dfd36 5055 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
09a1093a 5056 dmsg, pwrb, 1);
1390b01b 5057 } else {
09a1093a 5058 ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset);
2c9dfd36
JK		 5059 if (is_chip_be2_be3r(phba))
5060 AMAP_SET_BITS(struct amap_iscsi_wrb,
09a1093a
JSJ		 5061 dmsg, pwrb, 0);
5062 else
2c9dfd36 5063 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
09a1093a 5064 dmsg, pwrb, 0);
1390b01b 5065 }
e0493627 5066 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 5067 break;
5068 case ISCSI_OP_TEXT:
09a1093a 5069 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
e0493627 5070 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 5071 break;
5072 case ISCSI_OP_SCSI_TMFUNC:
09a1093a 5073 ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset);
e0493627 5074 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 5075 break;
5076 case ISCSI_OP_LOGOUT:
09a1093a 5077 ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset);
e0493627 5078 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 5079 break;
5080
5081 default:
99bc5d55
JSJ		 5082 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
5083 "BM_%d : opcode =%d Not supported\n",
5084 task->hdr->opcode & ISCSI_OPCODE_MASK);
5085
6733b39a
JK		 5086 return -EINVAL;
5087 }
5088
e0493627
AK		 5089 if (ret)
5090 return ret;
5091
09a1093a 5092 /* Set the task type */
2c9dfd36
JK		 5093 io_task->wrb_type = (is_chip_be2_be3r(phba)) ?
5094 AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) :
5095 AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb);
6733b39a 5096
bfead3b2 5097 doorbell |= cid & DB_WRB_POST_CID_MASK;
32951dd8 5098 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 5099 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
5100 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 5101 iowrite32(doorbell, phba->db_va +
5102 beiscsi_conn->doorbell_offset);
6733b39a
JK		 5103 return 0;
5104}
5105
5106static int beiscsi_task_xmit(struct iscsi_task *task)
5107{
6733b39a
JK		 5108 struct beiscsi_io_task *io_task = task->dd_data;
5109 struct scsi_cmnd *sc = task->sc;
1868379b 5110 struct beiscsi_hba *phba;
6733b39a
JK		 5111 struct scatterlist *sg;
5112 int num_sg;
5113 unsigned int writedir = 0, xferlen = 0;
5114
1868379b
JB		 5115 if (!io_task->conn->login_in_progress)
5116 task->hdr->exp_statsn = 0;
09a1093a 5117
6733b39a
JK		 5118 if (!sc)
5119 return beiscsi_mtask(task);
5120
5121 io_task->scsi_cmnd = sc;
5122 num_sg = scsi_dma_map(sc);
1868379b 5123 phba = io_task->conn->phba;
6733b39a 5124 if (num_sg < 0) {
afb96058
JK		 5125 beiscsi_log(phba, KERN_ERR,
5126 BEISCSI_LOG_IO | BEISCSI_LOG_ISCSI,
5127 "BM_%d : scsi_dma_map Failed "
5128 "Driver_ITT : 0x%x ITT : 0x%x Xferlen : 0x%x\n",
5129 be32_to_cpu(io_task->cmd_bhs->iscsi_hdr.itt),
5130 io_task->libiscsi_itt, scsi_bufflen(sc));
99bc5d55 5131
6733b39a
JK		 5132 return num_sg;
5133 }
6733b39a
JK		 5134 xferlen = scsi_bufflen(sc);
5135 sg = scsi_sglist(sc);
99bc5d55 5136 if (sc->sc_data_direction == DMA_TO_DEVICE)
6733b39a 5137 writedir = 1;
99bc5d55 5138 else
6733b39a 5139 writedir = 0;
99bc5d55 5140
09a1093a 5141 return phba->iotask_fn(task, sg, num_sg, xferlen, writedir);
6733b39a
JK		 5142}
5143
ffce3e2e
JK		 5144/**
5145 * beiscsi_bsg_request - handle bsg request from ISCSI transport
5146 * @job: job to handle
5147 */
5148static int beiscsi_bsg_request(struct bsg_job *job)
5149{
5150 struct Scsi_Host *shost;
5151 struct beiscsi_hba *phba;
5152 struct iscsi_bsg_request *bsg_req = job->request;
5153 int rc = -EINVAL;
5154 unsigned int tag;
5155 struct be_dma_mem nonemb_cmd;
5156 struct be_cmd_resp_hdr *resp;
5157 struct iscsi_bsg_reply *bsg_reply = job->reply;
5158 unsigned short status, extd_status;
5159
5160 shost = iscsi_job_to_shost(job);
5161 phba = iscsi_host_priv(shost);
5162
5163 switch (bsg_req->msgcode) {
5164 case ISCSI_BSG_HST_VENDOR:
5165 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
5166 job->request_payload.payload_len,
5167 &nonemb_cmd.dma);
5168 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 5169 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
5170 "BM_%d : Failed to allocate memory for "
5171 "beiscsi_bsg_request\n");
8359c79b 5172 return -ENOMEM;
ffce3e2e
JK		 5173 }
5174 tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
5175 &nonemb_cmd);
5176 if (!tag) {
99bc5d55 5177 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
8359c79b 5178 "BM_%d : MBX Tag Allocation Failed\n");
99bc5d55 5179
ffce3e2e
JK		 5180 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
5181 nonemb_cmd.va, nonemb_cmd.dma);
5182 return -EAGAIN;
e175defe
JSJ		 5183 }
5184
5185 rc = wait_event_interruptible_timeout(
5186 phba->ctrl.mcc_wait[tag],
67296ad9 5187 phba->ctrl.mcc_tag_status[tag],
e175defe
JSJ		 5188 msecs_to_jiffies(
5189 BEISCSI_HOST_MBX_TIMEOUT));
67296ad9
JB		 5190 extd_status = (phba->ctrl.mcc_tag_status[tag] &
5191 CQE_STATUS_ADDL_MASK) >> CQE_STATUS_ADDL_SHIFT;
5192 status = phba->ctrl.mcc_tag_status[tag] & CQE_STATUS_MASK;
090e2184 5193 free_mcc_wrb(&phba->ctrl, tag);
ffce3e2e
JK		 5194 resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
5195 sg_copy_from_buffer(job->reply_payload.sg_list,
5196 job->reply_payload.sg_cnt,
5197 nonemb_cmd.va, (resp->response_length
5198 + sizeof(*resp)));
5199 bsg_reply->reply_payload_rcv_len = resp->response_length;
5200 bsg_reply->result = status;
5201 bsg_job_done(job, bsg_reply->result,
5202 bsg_reply->reply_payload_rcv_len);
5203 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
5204 nonemb_cmd.va, nonemb_cmd.dma);
5205 if (status || extd_status) {
99bc5d55 5206 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
8359c79b 5207 "BM_%d : MBX Cmd Failed"
99bc5d55
JSJ		 5208 " status = %d extd_status = %d\n",
5209 status, extd_status);
5210
ffce3e2e 5211 return -EIO;
8359c79b
JSJ		 5212 } else {
5213 rc = 0;
ffce3e2e
JK		 5214 }
5215 break;
5216
5217 default:
99bc5d55
JSJ		 5218 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
5219 "BM_%d : Unsupported bsg command: 0x%x\n",
5220 bsg_req->msgcode);
ffce3e2e
JK		 5221 break;
5222 }
5223
5224 return rc;
5225}
5226
99bc5d55
JSJ		 5227void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
5228{
5229 /* Set the logging parameter */
5230 beiscsi_log_enable_init(phba, beiscsi_log_enable);
5231}
5232
4d4d1ef8
JSJ		 5233/*
5234 * beiscsi_quiesce()- Cleanup Driver resources
5235 * @phba: Instance Priv structure
3567f36a 5236 * @unload_state:i Clean or EEH unload state
4d4d1ef8
JSJ		 5237 *
5238 * Free the OS and HW resources held by the driver
5239 **/
3567f36a
JK		 5240static void beiscsi_quiesce(struct beiscsi_hba *phba,
5241 uint32_t unload_state)
6733b39a 5242{
bfead3b2
JK		 5243 struct hwi_controller *phwi_ctrlr;
5244 struct hwi_context_memory *phwi_context;
5245 struct be_eq_obj *pbe_eq;
5246 unsigned int i, msix_vec;
6733b39a 5247
bfead3b2
JK		 5248 phwi_ctrlr = phba->phwi_ctrlr;
5249 phwi_context = phwi_ctrlr->phwi_ctxt;
6733b39a 5250 hwi_disable_intr(phba);
bfead3b2
JK		 5251 if (phba->msix_enabled) {
5252 for (i = 0; i <= phba->num_cpus; i++) {
5253 msix_vec = phba->msix_entries[i].vector;
5254 free_irq(msix_vec, &phwi_context->be_eq[i]);
8fcfb210 5255 kfree(phba->msi_name[i]);
bfead3b2
JK		 5256 }
5257 } else
e729b503 5258 if (phba->pcidev->irq)
bfead3b2
JK		 5259 free_irq(phba->pcidev->irq, phba);
5260 pci_disable_msix(phba->pcidev);
53281edb 5261 cancel_delayed_work_sync(&phba->beiscsi_hw_check_task);
3567f36a 5262
89f8b33c
JA		 5263 for (i = 0; i < phba->num_cpus; i++) {
5264 pbe_eq = &phwi_context->be_eq[i];
511cbce2 5265 irq_poll_disable(&pbe_eq->iopoll);
89f8b33c 5266 }
6733b39a 5267
3567f36a
JK		 5268 if (unload_state == BEISCSI_CLEAN_UNLOAD) {
5269 destroy_workqueue(phba->wq);
5270 beiscsi_clean_port(phba);
5271 beiscsi_free_mem(phba);
e9b91193 5272
3567f36a
JK		 5273 beiscsi_unmap_pci_function(phba);
5274 pci_free_consistent(phba->pcidev,
5275 phba->ctrl.mbox_mem_alloced.size,
5276 phba->ctrl.mbox_mem_alloced.va,
5277 phba->ctrl.mbox_mem_alloced.dma);
5278 } else {
5279 hwi_purge_eq(phba);
5280 hwi_cleanup(phba);
5281 }
7a158003 5282
25602c97
JK		 5283}
5284
5285static void beiscsi_remove(struct pci_dev *pcidev)
5286{
25602c97
JK		 5287 struct beiscsi_hba *phba = NULL;
5288
5289 phba = pci_get_drvdata(pcidev);
5290 if (!phba) {
5291 dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
5292 return;
5293 }
5294
96b48b92 5295 beiscsi_iface_destroy_default(phba);
9d045163 5296 iscsi_boot_destroy_kset(phba->boot_kset);
6733b39a 5297 iscsi_host_remove(phba->shost);
cdaa4ded 5298 beiscsi_quiesce(phba, BEISCSI_CLEAN_UNLOAD);
6733b39a
JK		 5299 pci_dev_put(phba->pcidev);
5300 iscsi_host_free(phba->shost);
3567f36a
JK		 5301 pci_disable_pcie_error_reporting(pcidev);
5302 pci_set_drvdata(pcidev, NULL);
e307f3ac 5303 pci_release_regions(pcidev);
8dce69ff 5304 pci_disable_device(pcidev);
6733b39a
JK		 5305}
5306
bfead3b2
JK		 5307static void beiscsi_msix_enable(struct beiscsi_hba *phba)
5308{
5309 int i, status;
5310
5311 for (i = 0; i <= phba->num_cpus; i++)
5312 phba->msix_entries[i].entry = i;
5313
e149fc13
AG		 5314 status = pci_enable_msix_range(phba->pcidev, phba->msix_entries,
5315 phba->num_cpus + 1, phba->num_cpus + 1);
5316 if (status > 0)
bfead3b2
JK		 5317 phba->msix_enabled = true;
5318
5319 return;
5320}
5321
73af08e1
JK		 5322static void be_eqd_update(struct beiscsi_hba *phba)
5323{
5324 struct be_set_eqd set_eqd[MAX_CPUS];
5325 struct be_aic_obj *aic;
5326 struct be_eq_obj *pbe_eq;
5327 struct hwi_controller *phwi_ctrlr;
5328 struct hwi_context_memory *phwi_context;
5329 int eqd, i, num = 0;
5330 ulong now;
5331 u32 pps, delta;
5332 unsigned int tag;
5333
5334 phwi_ctrlr = phba->phwi_ctrlr;
5335 phwi_context = phwi_ctrlr->phwi_ctxt;
5336
5337 for (i = 0; i <= phba->num_cpus; i++) {
5338 aic = &phba->aic_obj[i];
5339 pbe_eq = &phwi_context->be_eq[i];
5340 now = jiffies;
5341 if (!aic->jiffs || time_before(now, aic->jiffs) ||
5342 pbe_eq->cq_count < aic->eq_prev) {
5343 aic->jiffs = now;
5344 aic->eq_prev = pbe_eq->cq_count;
5345 continue;
5346 }
5347 delta = jiffies_to_msecs(now - aic->jiffs);
5348 pps = (((u32)(pbe_eq->cq_count - aic->eq_prev) * 1000) / delta);
5349 eqd = (pps / 1500) << 2;
5350
5351 if (eqd < 8)
5352 eqd = 0;
5353 eqd = min_t(u32, eqd, phwi_context->max_eqd);
5354 eqd = max_t(u32, eqd, phwi_context->min_eqd);
5355
5356 aic->jiffs = now;
5357 aic->eq_prev = pbe_eq->cq_count;
5358
5359 if (eqd != aic->prev_eqd) {
5360 set_eqd[num].delay_multiplier = (eqd * 65)/100;
5361 set_eqd[num].eq_id = pbe_eq->q.id;
5362 aic->prev_eqd = eqd;
5363 num++;
5364 }
5365 }
5366 if (num) {
5367 tag = be_cmd_modify_eq_delay(phba, set_eqd, num);
5368 if (tag)
88840332 5369 beiscsi_mccq_compl_wait(phba, tag, NULL, NULL);
73af08e1
JK		 5370 }
5371}
5372
a3d313ea
JK		 5373static void be_check_boot_session(struct beiscsi_hba *phba)
5374{
5375 if (beiscsi_setup_boot_info(phba))
5376 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5377 "BM_%d : Could not set up "
5378 "iSCSI boot info on async event.\n");
5379}
5380
7a158003
JSJ		 5381/*
5382 * beiscsi_hw_health_check()- Check adapter health
5383 * @work: work item to check HW health
5384 *
5385 * Check if adapter in an unrecoverable state or not.
5386 **/
5387static void
5388beiscsi_hw_health_check(struct work_struct *work)
5389{
5390 struct beiscsi_hba *phba =
5391 container_of(work, struct beiscsi_hba,
5392 beiscsi_hw_check_task.work);
5393
73af08e1
JK		 5394 be_eqd_update(phba);
5395
a3d313ea 5396 if (phba->state & BE_ADAPTER_CHECK_BOOT) {
3efde862
JSJ		 5397 if ((phba->get_boot > 0) && (!phba->boot_kset)) {
5398 phba->get_boot--;
5399 if (!(phba->get_boot % BE_GET_BOOT_TO))
5400 be_check_boot_session(phba);
5401 } else {
5402 phba->state &= ~BE_ADAPTER_CHECK_BOOT;
5403 phba->get_boot = 0;
5404 }
a3d313ea
JK		 5405 }
5406
7a158003
JSJ		 5407 beiscsi_ue_detect(phba);
5408
5409 schedule_delayed_work(&phba->beiscsi_hw_check_task,
5410 msecs_to_jiffies(1000));
5411}
5412
3567f36a
JK		 5413
5414static pci_ers_result_t beiscsi_eeh_err_detected(struct pci_dev *pdev,
5415 pci_channel_state_t state)
5416{
5417 struct beiscsi_hba *phba = NULL;
5418
5419 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5420 phba->state |= BE_ADAPTER_PCI_ERR;
5421
5422 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5423 "BM_%d : EEH error detected\n");
5424
5425 beiscsi_quiesce(phba, BEISCSI_EEH_UNLOAD);
5426
5427 if (state == pci_channel_io_perm_failure) {
5428 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5429 "BM_%d : EEH : State PERM Failure");
5430 return PCI_ERS_RESULT_DISCONNECT;
5431 }
5432
5433 pci_disable_device(pdev);
5434
5435 /* The error could cause the FW to trigger a flash debug dump.
5436 * Resetting the card while flash dump is in progress
5437 * can cause it not to recover; wait for it to finish.
5438 * Wait only for first function as it is needed only once per
5439 * adapter.
5440 **/
5441 if (pdev->devfn == 0)
5442 ssleep(30);
5443
5444 return PCI_ERS_RESULT_NEED_RESET;
5445}
5446
5447static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev)
5448{
5449 struct beiscsi_hba *phba = NULL;
5450 int status = 0;
5451
5452 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5453
5454 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5455 "BM_%d : EEH Reset\n");
5456
5457 status = pci_enable_device(pdev);
5458 if (status)
5459 return PCI_ERS_RESULT_DISCONNECT;
5460
5461 pci_set_master(pdev);
5462 pci_set_power_state(pdev, PCI_D0);
5463 pci_restore_state(pdev);
5464
5465 /* Wait for the CHIP Reset to complete */
5466 status = be_chk_reset_complete(phba);
5467 if (!status) {
5468 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5469 "BM_%d : EEH Reset Completed\n");
5470 } else {
5471 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5472 "BM_%d : EEH Reset Completion Failure\n");
5473 return PCI_ERS_RESULT_DISCONNECT;
5474 }
5475
5476 pci_cleanup_aer_uncorrect_error_status(pdev);
5477 return PCI_ERS_RESULT_RECOVERED;
5478}
5479
5480static void beiscsi_eeh_resume(struct pci_dev *pdev)
5481{
5482 int ret = 0, i;
5483 struct be_eq_obj *pbe_eq;
5484 struct beiscsi_hba *phba = NULL;
5485 struct hwi_controller *phwi_ctrlr;
5486 struct hwi_context_memory *phwi_context;
5487
5488 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5489 pci_save_state(pdev);
5490
5491 if (enable_msix)
5492 find_num_cpus(phba);
5493 else
5494 phba->num_cpus = 1;
5495
5496 if (enable_msix) {
5497 beiscsi_msix_enable(phba);
5498 if (!phba->msix_enabled)
5499 phba->num_cpus = 1;
5500 }
5501
5502 ret = beiscsi_cmd_reset_function(phba);
5503 if (ret) {
5504 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5505 "BM_%d : Reset Failed\n");
5506 goto ret_err;
5507 }
5508
5509 ret = be_chk_reset_complete(phba);
5510 if (ret) {
5511 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5512 "BM_%d : Failed to get out of reset.\n");
5513 goto ret_err;
5514 }
5515
5516 beiscsi_get_params(phba);
5517 phba->shost->max_id = phba->params.cxns_per_ctrl;
5518 phba->shost->can_queue = phba->params.ios_per_ctrl;
5519 ret = hwi_init_controller(phba);
c6fff322
NK		 5520 if (ret) {
5521 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5522 "BM_%d : beiscsi_eeh_resume -"
5523 "Failed to initialize beiscsi_hba.\n");
5524 goto ret_err;
5525 }
3567f36a
JK		 5526
5527 for (i = 0; i < MAX_MCC_CMD; i++) {
5528 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5529 phba->ctrl.mcc_tag[i] = i + 1;
67296ad9 5530 phba->ctrl.mcc_tag_status[i + 1] = 0;
3567f36a
JK		 5531 phba->ctrl.mcc_tag_available++;
5532 }
5533
5534 phwi_ctrlr = phba->phwi_ctrlr;
5535 phwi_context = phwi_ctrlr->phwi_ctxt;
5536
89f8b33c 5537 for (i = 0; i < phba->num_cpus; i++) {
3567f36a 5538 pbe_eq = &phwi_context->be_eq[i];
511cbce2 5539 irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget,
89f8b33c 5540 be_iopoll);
3567f36a
JK		 5541 }
5542
89f8b33c
JA		 5543 i = (phba->msix_enabled) ? i : 0;
5544 /* Work item for MCC handling */
5545 pbe_eq = &phwi_context->be_eq[i];
a3095016 5546 INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work);
89f8b33c 5547
3567f36a
JK		 5548 ret = beiscsi_init_irqs(phba);
5549 if (ret < 0) {
5550 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5551 "BM_%d : beiscsi_eeh_resume - "
5552 "Failed to beiscsi_init_irqs\n");
5553 goto ret_err;
5554 }
5555
5556 hwi_enable_intr(phba);
5557 phba->state &= ~BE_ADAPTER_PCI_ERR;
5558
5559 return;
5560ret_err:
5561 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5562 "BM_%d : AER EEH Resume Failed\n");
5563}
5564
6f039790
GKH		 5565static int beiscsi_dev_probe(struct pci_dev *pcidev,
5566 const struct pci_device_id *id)
6733b39a
JK		 5567{
5568 struct beiscsi_hba *phba = NULL;
bfead3b2
JK		 5569 struct hwi_controller *phwi_ctrlr;
5570 struct hwi_context_memory *phwi_context;
5571 struct be_eq_obj *pbe_eq;
3567f36a 5572 int ret = 0, i;
6733b39a
JK		 5573
5574 ret = beiscsi_enable_pci(pcidev);
5575 if (ret < 0) {
99bc5d55
JSJ		 5576 dev_err(&pcidev->dev,
5577 "beiscsi_dev_probe - Failed to enable pci device\n");
6733b39a
JK		 5578 return ret;
5579 }
5580
5581 phba = beiscsi_hba_alloc(pcidev);
5582 if (!phba) {
99bc5d55
JSJ		 5583 dev_err(&pcidev->dev,
5584 "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
6733b39a
JK		 5585 goto disable_pci;
5586 }
5587
3567f36a
JK		 5588 /* Enable EEH reporting */
5589 ret = pci_enable_pcie_error_reporting(pcidev);
5590 if (ret)
5591 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5592 "BM_%d : PCIe Error Reporting "
5593 "Enabling Failed\n");
5594
5595 pci_save_state(pcidev);
5596
99bc5d55
JSJ		 5597 /* Initialize Driver configuration Paramters */
5598 beiscsi_hba_attrs_init(phba);
5599
e175defe 5600 phba->fw_timeout = false;
6c83185a 5601 phba->mac_addr_set = false;
e175defe
JSJ		 5602
5603
f98c96b0
JK		 5604 switch (pcidev->device) {
5605 case BE_DEVICE_ID1:
5606 case OC_DEVICE_ID1:
5607 case OC_DEVICE_ID2:
5608 phba->generation = BE_GEN2;
09a1093a 5609 phba->iotask_fn = beiscsi_iotask;
f98c96b0
JK		 5610 break;
5611 case BE_DEVICE_ID2:
5612 case OC_DEVICE_ID3:
5613 phba->generation = BE_GEN3;
09a1093a 5614 phba->iotask_fn = beiscsi_iotask;
f98c96b0 5615 break;
139a1b1e
JSJ		 5616 case OC_SKH_ID1:
5617 phba->generation = BE_GEN4;
09a1093a 5618 phba->iotask_fn = beiscsi_iotask_v2;
bf9131cb 5619 break;
f98c96b0
JK		 5620 default:
5621 phba->generation = 0;
5622 }
5623
6733b39a
JK		 5624 ret = be_ctrl_init(phba, pcidev);
5625 if (ret) {
99bc5d55
JSJ		 5626 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5627 "BM_%d : beiscsi_dev_probe-"
5628 "Failed in be_ctrl_init\n");
6733b39a
JK		 5629 goto hba_free;
5630 }
5631
cdaa4ded
JB		 5632 /*
5633 * FUNCTION_RESET should clean up any stale info in FW for this fn
5634 */
4d4d1ef8
JSJ		 5635 ret = beiscsi_cmd_reset_function(phba);
5636 if (ret) {
5637 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
92665a66 5638 "BM_%d : Reset Failed\n");
4d4d1ef8
JSJ		 5639 goto hba_free;
5640 }
5641 ret = be_chk_reset_complete(phba);
5642 if (ret) {
5643 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
92665a66 5644 "BM_%d : Failed to get out of reset.\n");
4d4d1ef8 5645 goto hba_free;
e9b91193
JK		 5646 }
5647
6733b39a
JK		 5648 spin_lock_init(&phba->io_sgl_lock);
5649 spin_lock_init(&phba->mgmt_sgl_lock);
8f09a3b9 5650 spin_lock_init(&phba->async_pdu_lock);
7da50879
JK		 5651 ret = mgmt_get_fw_config(&phba->ctrl, phba);
5652 if (ret != 0) {
99bc5d55
JSJ		 5653 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5654 "BM_%d : Error getting fw config\n");
7da50879
JK		 5655 goto free_port;
5656 }
53aefe25 5657 mgmt_get_port_name(&phba->ctrl, phba);
4570f161 5658 beiscsi_get_params(phba);
68c26a3a
JK		 5659
5660 if (enable_msix)
5661 find_num_cpus(phba);
5662 else
5663 phba->num_cpus = 1;
5664
5665 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
5666 "BM_%d : num_cpus = %d\n",
5667 phba->num_cpus);
5668
5669 if (enable_msix) {
5670 beiscsi_msix_enable(phba);
5671 if (!phba->msix_enabled)
5672 phba->num_cpus = 1;
5673 }
5674
843ae752 5675 phba->shost->max_id = phba->params.cxns_per_ctrl;
aa874f07 5676 phba->shost->can_queue = phba->params.ios_per_ctrl;
6733b39a
JK		 5677 ret = beiscsi_init_port(phba);
5678 if (ret < 0) {
99bc5d55
JSJ		 5679 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5680 "BM_%d : beiscsi_dev_probe-"
5681 "Failed in beiscsi_init_port\n");
6733b39a
JK		 5682 goto free_port;
5683 }
5684
3567f36a 5685 for (i = 0; i < MAX_MCC_CMD; i++) {
756d29c8
JK		 5686 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5687 phba->ctrl.mcc_tag[i] = i + 1;
67296ad9 5688 phba->ctrl.mcc_tag_status[i + 1] = 0;
756d29c8 5689 phba->ctrl.mcc_tag_available++;
1957aa7f 5690 memset(&phba->ctrl.ptag_state[i].tag_mem_state, 0,
8fc01eaa 5691 sizeof(struct be_dma_mem));
756d29c8
JK		 5692 }
5693
5694 phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
5695
72fb46a9 5696 snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
6733b39a 5697 phba->shost->host_no);
d8537548 5698 phba->wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 1, phba->wq_name);
6733b39a 5699 if (!phba->wq) {
99bc5d55
JSJ		 5700 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5701 "BM_%d : beiscsi_dev_probe-"
5702 "Failed to allocate work queue\n");
6733b39a
JK		 5703 goto free_twq;
5704 }
5705
7a158003
JSJ		 5706 INIT_DELAYED_WORK(&phba->beiscsi_hw_check_task,
5707 beiscsi_hw_health_check);
6733b39a 5708
bfead3b2
JK		 5709 phwi_ctrlr = phba->phwi_ctrlr;
5710 phwi_context = phwi_ctrlr->phwi_ctxt;
72fb46a9 5711
89f8b33c 5712 for (i = 0; i < phba->num_cpus; i++) {
72fb46a9 5713 pbe_eq = &phwi_context->be_eq[i];
511cbce2 5714 irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget,
89f8b33c 5715 be_iopoll);
6733b39a 5716 }
72fb46a9 5717
89f8b33c
JA		 5718 i = (phba->msix_enabled) ? i : 0;
5719 /* Work item for MCC handling */
5720 pbe_eq = &phwi_context->be_eq[i];
a3095016 5721 INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work);
89f8b33c 5722
6733b39a
JK		 5723 ret = beiscsi_init_irqs(phba);
5724 if (ret < 0) {
99bc5d55
JSJ		 5725 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5726 "BM_%d : beiscsi_dev_probe-"
5727 "Failed to beiscsi_init_irqs\n");
6733b39a
JK		 5728 goto free_blkenbld;
5729 }
238f6b72 5730 hwi_enable_intr(phba);
f457a46f 5731
0598b8af
JK		 5732 if (iscsi_host_add(phba->shost, &phba->pcidev->dev))
5733 goto free_blkenbld;
5734
f457a46f
MC		 5735 if (beiscsi_setup_boot_info(phba))
5736 /*
5737 * log error but continue, because we may not be using
5738 * iscsi boot.
5739 */
99bc5d55
JSJ		 5740 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5741 "BM_%d : Could not set up "
5742 "iSCSI boot info.\n");
f457a46f 5743
96b48b92 5744 beiscsi_iface_create_default(phba);
7a158003
JSJ		 5745 schedule_delayed_work(&phba->beiscsi_hw_check_task,
5746 msecs_to_jiffies(1000));
5747
99bc5d55
JSJ		 5748 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
5749 "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
6733b39a
JK		 5750 return 0;
5751
6733b39a
JK		 5752free_blkenbld:
5753 destroy_workqueue(phba->wq);
89f8b33c
JA		 5754 for (i = 0; i < phba->num_cpus; i++) {
5755 pbe_eq = &phwi_context->be_eq[i];
511cbce2 5756 irq_poll_disable(&pbe_eq->iopoll);
89f8b33c 5757 }
6733b39a
JK		 5758free_twq:
5759 beiscsi_clean_port(phba);
5760 beiscsi_free_mem(phba);
5761free_port:
5762 pci_free_consistent(phba->pcidev,
5763 phba->ctrl.mbox_mem_alloced.size,
5764 phba->ctrl.mbox_mem_alloced.va,
5765 phba->ctrl.mbox_mem_alloced.dma);
5766 beiscsi_unmap_pci_function(phba);
5767hba_free:
238f6b72
JK		 5768 if (phba->msix_enabled)
5769 pci_disable_msix(phba->pcidev);
6733b39a
JK		 5770 pci_dev_put(phba->pcidev);
5771 iscsi_host_free(phba->shost);
2e7cee02 5772 pci_set_drvdata(pcidev, NULL);
6733b39a 5773disable_pci:
e307f3ac 5774 pci_release_regions(pcidev);
6733b39a
JK		 5775 pci_disable_device(pcidev);
5776 return ret;
5777}
5778
3567f36a
JK		 5779static struct pci_error_handlers beiscsi_eeh_handlers = {
5780 .error_detected = beiscsi_eeh_err_detected,
5781 .slot_reset = beiscsi_eeh_reset,
5782 .resume = beiscsi_eeh_resume,
5783};
5784
6733b39a
JK		 5785struct iscsi_transport beiscsi_iscsi_transport = {
5786 .owner = THIS_MODULE,
5787 .name = DRV_NAME,
9db0fb3a 5788 .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
6733b39a 5789 CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
6733b39a
JK		 5790 .create_session = beiscsi_session_create,
5791 .destroy_session = beiscsi_session_destroy,
5792 .create_conn = beiscsi_conn_create,
5793 .bind_conn = beiscsi_conn_bind,
5794 .destroy_conn = iscsi_conn_teardown,
96b48b92
JB		 5795 .attr_is_visible = beiscsi_attr_is_visible,
5796 .set_iface_param = beiscsi_iface_set_param,
5797 .get_iface_param = beiscsi_iface_get_param,
6733b39a 5798 .set_param = beiscsi_set_param,
c7f7fd5b 5799 .get_conn_param = iscsi_conn_get_param,
6733b39a
JK		 5800 .get_session_param = iscsi_session_get_param,
5801 .get_host_param = beiscsi_get_host_param,
5802 .start_conn = beiscsi_conn_start,
fa95d206 5803 .stop_conn = iscsi_conn_stop,
6733b39a
JK		 5804 .send_pdu = iscsi_conn_send_pdu,
5805 .xmit_task = beiscsi_task_xmit,
5806 .cleanup_task = beiscsi_cleanup_task,
5807 .alloc_pdu = beiscsi_alloc_pdu,
5808 .parse_pdu_itt = beiscsi_parse_pdu,
5809 .get_stats = beiscsi_conn_get_stats,
c7f7fd5b 5810 .get_ep_param = beiscsi_ep_get_param,
6733b39a
JK		 5811 .ep_connect = beiscsi_ep_connect,
5812 .ep_poll = beiscsi_ep_poll,
5813 .ep_disconnect = beiscsi_ep_disconnect,
5814 .session_recovery_timedout = iscsi_session_recovery_timedout,
ffce3e2e 5815 .bsg_request = beiscsi_bsg_request,
6733b39a
JK		 5816};
5817
5818static struct pci_driver beiscsi_pci_driver = {
5819 .name = DRV_NAME,
5820 .probe = beiscsi_dev_probe,
5821 .remove = beiscsi_remove,
3567f36a
JK		 5822 .id_table = beiscsi_pci_id_table,
5823 .err_handler = &beiscsi_eeh_handlers
6733b39a
JK		 5824};
5825
bfead3b2 5826
6733b39a
JK		 5827static int __init beiscsi_module_init(void)
5828{
5829 int ret;
5830
5831 beiscsi_scsi_transport =
5832 iscsi_register_transport(&beiscsi_iscsi_transport);
5833 if (!beiscsi_scsi_transport) {
99bc5d55
JSJ		 5834 printk(KERN_ERR
5835 "beiscsi_module_init - Unable to register beiscsi transport.\n");
f55a24f2 5836 return -ENOMEM;
6733b39a 5837 }
99bc5d55
JSJ		 5838 printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
5839 &beiscsi_iscsi_transport);
6733b39a
JK		 5840
5841 ret = pci_register_driver(&beiscsi_pci_driver);
5842 if (ret) {
99bc5d55
JSJ		 5843 printk(KERN_ERR
5844 "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
6733b39a
JK		 5845 goto unregister_iscsi_transport;
5846 }
5847 return 0;
5848
5849unregister_iscsi_transport:
5850 iscsi_unregister_transport(&beiscsi_iscsi_transport);
5851 return ret;
5852}
5853
5854static void __exit beiscsi_module_exit(void)
5855{
5856 pci_unregister_driver(&beiscsi_pci_driver);
5857 iscsi_unregister_transport(&beiscsi_iscsi_transport);
5858}
5859
5860module_init(beiscsi_module_init);
5861module_exit(beiscsi_module_exit);
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