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be2iscsi: Fix TCP parameters while connection offloading.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / be2iscsi / be_main.c
CommitLineData
6733b39a 1/**
533c165f 2 * Copyright (C) 2005 - 2013 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
255fa9a3 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
6733b39a
JK		 11 *
12 * Contact Information:
255fa9a3 13 * linux-drivers@emulex.com
6733b39a 14 *
255fa9a3
JK		 15 * Emulex
16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a 18 */
255fa9a3 19
6733b39a
JK		 20#include <linux/reboot.h>
21#include <linux/delay.h>
5a0e3ad6 22#include <linux/slab.h>
6733b39a
JK		 23#include <linux/interrupt.h>
24#include <linux/blkdev.h>
25#include <linux/pci.h>
26#include <linux/string.h>
27#include <linux/kernel.h>
28#include <linux/semaphore.h>
c7acc5b8 29#include <linux/iscsi_boot_sysfs.h>
acf3368f 30#include <linux/module.h>
ffce3e2e 31#include <linux/bsg-lib.h>
6733b39a
JK		 32
33#include <scsi/libiscsi.h>
ffce3e2e
JK		 34#include <scsi/scsi_bsg_iscsi.h>
35#include <scsi/scsi_netlink.h>
6733b39a
JK		 36#include <scsi/scsi_transport_iscsi.h>
37#include <scsi/scsi_transport.h>
38#include <scsi/scsi_cmnd.h>
39#include <scsi/scsi_device.h>
40#include <scsi/scsi_host.h>
41#include <scsi/scsi.h>
42#include "be_main.h"
43#include "be_iscsi.h"
44#include "be_mgmt.h"
0a513dd8 45#include "be_cmds.h"
6733b39a
JK		 46
47static unsigned int be_iopoll_budget = 10;
48static unsigned int be_max_phys_size = 64;
bfead3b2 49static unsigned int enable_msix = 1;
6733b39a
JK		 50
51MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
52MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
76d15dbd 53MODULE_VERSION(BUILD_STR);
2f635883 54MODULE_AUTHOR("Emulex Corporation");
6733b39a
JK		 55MODULE_LICENSE("GPL");
56module_param(be_iopoll_budget, int, 0);
57module_param(enable_msix, int, 0);
58module_param(be_max_phys_size, uint, S_IRUGO);
99bc5d55
JSJ		 59MODULE_PARM_DESC(be_max_phys_size,
60 "Maximum Size (In Kilobytes) of physically contiguous "
61 "memory that can be allocated. Range is 16 - 128");
62
63#define beiscsi_disp_param(_name)\
64ssize_t \
65beiscsi_##_name##_disp(struct device *dev,\
66 struct device_attribute *attrib, char *buf) \
67{ \
68 struct Scsi_Host *shost = class_to_shost(dev);\
69 struct beiscsi_hba *phba = iscsi_host_priv(shost); \
70 uint32_t param_val = 0; \
71 param_val = phba->attr_##_name;\
72 return snprintf(buf, PAGE_SIZE, "%d\n",\
73 phba->attr_##_name);\
74}
75
76#define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
77int \
78beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
79{\
80 if (val >= _minval && val <= _maxval) {\
81 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
82 "BA_%d : beiscsi_"#_name" updated "\
83 "from 0x%x ==> 0x%x\n",\
84 phba->attr_##_name, val); \
85 phba->attr_##_name = val;\
86 return 0;\
87 } \
88 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
89 "BA_%d beiscsi_"#_name" attribute "\
90 "cannot be updated to 0x%x, "\
91 "range allowed is ["#_minval" - "#_maxval"]\n", val);\
92 return -EINVAL;\
93}
94
95#define beiscsi_store_param(_name) \
96ssize_t \
97beiscsi_##_name##_store(struct device *dev,\
98 struct device_attribute *attr, const char *buf,\
99 size_t count) \
100{ \
101 struct Scsi_Host *shost = class_to_shost(dev);\
102 struct beiscsi_hba *phba = iscsi_host_priv(shost);\
103 uint32_t param_val = 0;\
104 if (!isdigit(buf[0]))\
105 return -EINVAL;\
106 if (sscanf(buf, "%i", &param_val) != 1)\
107 return -EINVAL;\
108 if (beiscsi_##_name##_change(phba, param_val) == 0) \
109 return strlen(buf);\
110 else \
111 return -EINVAL;\
112}
113
114#define beiscsi_init_param(_name, _minval, _maxval, _defval) \
115int \
116beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
117{ \
118 if (val >= _minval && val <= _maxval) {\
119 phba->attr_##_name = val;\
120 return 0;\
121 } \
122 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
123 "BA_%d beiscsi_"#_name" attribute " \
124 "cannot be updated to 0x%x, "\
125 "range allowed is ["#_minval" - "#_maxval"]\n", val);\
126 phba->attr_##_name = _defval;\
127 return -EINVAL;\
128}
129
130#define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
131static uint beiscsi_##_name = _defval;\
132module_param(beiscsi_##_name, uint, S_IRUGO);\
133MODULE_PARM_DESC(beiscsi_##_name, _descp);\
134beiscsi_disp_param(_name)\
135beiscsi_change_param(_name, _minval, _maxval, _defval)\
136beiscsi_store_param(_name)\
137beiscsi_init_param(_name, _minval, _maxval, _defval)\
138DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
139 beiscsi_##_name##_disp, beiscsi_##_name##_store)
140
141/*
142 * When new log level added update the
143 * the MAX allowed value for log_enable
144 */
145BEISCSI_RW_ATTR(log_enable, 0x00,
146 0xFF, 0x00, "Enable logging Bit Mask\n"
147 "\t\t\t\tInitialization Events : 0x01\n"
148 "\t\t\t\tMailbox Events : 0x02\n"
149 "\t\t\t\tMiscellaneous Events : 0x04\n"
150 "\t\t\t\tError Handling : 0x08\n"
151 "\t\t\t\tIO Path Events : 0x10\n"
afb96058
JK		 152 "\t\t\t\tConfiguration Path : 0x20\n"
153 "\t\t\t\tiSCSI Protocol : 0x40\n");
99bc5d55 154
5cac7596 155DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
26000db7 156DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL);
22661e25 157DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL);
d3fea9af 158DEVICE_ATTR(beiscsi_phys_port, S_IRUGO, beiscsi_phys_port_disp, NULL);
6103c1f7
JK		 159DEVICE_ATTR(beiscsi_active_session_count, S_IRUGO,
160 beiscsi_active_session_disp, NULL);
161DEVICE_ATTR(beiscsi_free_session_count, S_IRUGO,
162 beiscsi_free_session_disp, NULL);
99bc5d55
JSJ		 163struct device_attribute *beiscsi_attrs[] = {
164 &dev_attr_beiscsi_log_enable,
5cac7596 165 &dev_attr_beiscsi_drvr_ver,
26000db7 166 &dev_attr_beiscsi_adapter_family,
22661e25 167 &dev_attr_beiscsi_fw_ver,
6103c1f7
JK		 168 &dev_attr_beiscsi_active_session_count,
169 &dev_attr_beiscsi_free_session_count,
d3fea9af 170 &dev_attr_beiscsi_phys_port,
99bc5d55
JSJ		 171 NULL,
172};
6733b39a 173
6763daae
JSJ		 174static char const *cqe_desc[] = {
175 "RESERVED_DESC",
176 "SOL_CMD_COMPLETE",
177 "SOL_CMD_KILLED_DATA_DIGEST_ERR",
178 "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
179 "CXN_KILLED_BURST_LEN_MISMATCH",
180 "CXN_KILLED_AHS_RCVD",
181 "CXN_KILLED_HDR_DIGEST_ERR",
182 "CXN_KILLED_UNKNOWN_HDR",
183 "CXN_KILLED_STALE_ITT_TTT_RCVD",
184 "CXN_KILLED_INVALID_ITT_TTT_RCVD",
185 "CXN_KILLED_RST_RCVD",
186 "CXN_KILLED_TIMED_OUT",
187 "CXN_KILLED_RST_SENT",
188 "CXN_KILLED_FIN_RCVD",
189 "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
190 "CXN_KILLED_BAD_WRB_INDEX_ERROR",
191 "CXN_KILLED_OVER_RUN_RESIDUAL",
192 "CXN_KILLED_UNDER_RUN_RESIDUAL",
193 "CMD_KILLED_INVALID_STATSN_RCVD",
194 "CMD_KILLED_INVALID_R2T_RCVD",
195 "CMD_CXN_KILLED_LUN_INVALID",
196 "CMD_CXN_KILLED_ICD_INVALID",
197 "CMD_CXN_KILLED_ITT_INVALID",
198 "CMD_CXN_KILLED_SEQ_OUTOFORDER",
199 "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
200 "CXN_INVALIDATE_NOTIFY",
201 "CXN_INVALIDATE_INDEX_NOTIFY",
202 "CMD_INVALIDATED_NOTIFY",
203 "UNSOL_HDR_NOTIFY",
204 "UNSOL_DATA_NOTIFY",
205 "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
206 "DRIVERMSG_NOTIFY",
207 "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
208 "SOL_CMD_KILLED_DIF_ERR",
209 "CXN_KILLED_SYN_RCVD",
210 "CXN_KILLED_IMM_DATA_RCVD"
211};
212
6733b39a
JK		 213static int beiscsi_slave_configure(struct scsi_device *sdev)
214{
215 blk_queue_max_segment_size(sdev->request_queue, 65536);
216 return 0;
217}
218
4183122d
JK		 219static int beiscsi_eh_abort(struct scsi_cmnd *sc)
220{
221 struct iscsi_cls_session *cls_session;
222 struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
223 struct beiscsi_io_task *aborted_io_task;
224 struct iscsi_conn *conn;
225 struct beiscsi_conn *beiscsi_conn;
226 struct beiscsi_hba *phba;
227 struct iscsi_session *session;
228 struct invalidate_command_table *inv_tbl;
3cbb7a74 229 struct be_dma_mem nonemb_cmd;
4183122d 230 unsigned int cid, tag, num_invalidate;
1957aa7f 231 int rc;
4183122d
JK		 232
233 cls_session = starget_to_session(scsi_target(sc->device));
234 session = cls_session->dd_data;
235
659743b0 236 spin_lock_bh(&session->frwd_lock);
4183122d
JK		 237 if (!aborted_task || !aborted_task->sc) {
238 /* we raced */
659743b0 239 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 240 return SUCCESS;
241 }
242
243 aborted_io_task = aborted_task->dd_data;
244 if (!aborted_io_task->scsi_cmnd) {
245 /* raced or invalid command */
659743b0 246 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 247 return SUCCESS;
248 }
659743b0 249 spin_unlock_bh(&session->frwd_lock);
7626c06b
JK		 250 /* Invalidate WRB Posted for this Task */
251 AMAP_SET_BITS(struct amap_iscsi_wrb, invld,
252 aborted_io_task->pwrb_handle->pwrb,
253 1);
254
4183122d
JK		 255 conn = aborted_task->conn;
256 beiscsi_conn = conn->dd_data;
257 phba = beiscsi_conn->phba;
258
259 /* invalidate iocb */
260 cid = beiscsi_conn->beiscsi_conn_cid;
261 inv_tbl = phba->inv_tbl;
262 memset(inv_tbl, 0x0, sizeof(*inv_tbl));
263 inv_tbl->cid = cid;
264 inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
265 num_invalidate = 1;
3cbb7a74
JK		 266 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
267 sizeof(struct invalidate_commands_params_in),
268 &nonemb_cmd.dma);
269 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 270 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
271 "BM_%d : Failed to allocate memory for"
272 "mgmt_invalidate_icds\n");
3cbb7a74
JK		 273 return FAILED;
274 }
275 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
276
277 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
278 cid, &nonemb_cmd);
4183122d 279 if (!tag) {
99bc5d55
JSJ		 280 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
281 "BM_%d : mgmt_invalidate_icds could not be"
282 "submitted\n");
3cbb7a74
JK		 283 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
284 nonemb_cmd.va, nonemb_cmd.dma);
285
4183122d 286 return FAILED;
4183122d 287 }
e175defe 288
1957aa7f
JK		 289 rc = beiscsi_mccq_compl(phba, tag, NULL, &nonemb_cmd);
290 if (rc != -EBUSY)
291 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
292 nonemb_cmd.va, nonemb_cmd.dma);
293
4183122d
JK		 294 return iscsi_eh_abort(sc);
295}
296
297static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
298{
299 struct iscsi_task *abrt_task;
300 struct beiscsi_io_task *abrt_io_task;
301 struct iscsi_conn *conn;
302 struct beiscsi_conn *beiscsi_conn;
303 struct beiscsi_hba *phba;
304 struct iscsi_session *session;
305 struct iscsi_cls_session *cls_session;
306 struct invalidate_command_table *inv_tbl;
3cbb7a74 307 struct be_dma_mem nonemb_cmd;
4183122d 308 unsigned int cid, tag, i, num_invalidate;
1957aa7f 309 int rc;
4183122d
JK		 310
311 /* invalidate iocbs */
312 cls_session = starget_to_session(scsi_target(sc->device));
313 session = cls_session->dd_data;
659743b0 314 spin_lock_bh(&session->frwd_lock);
db7f7709 315 if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
659743b0 316 spin_unlock_bh(&session->frwd_lock);
db7f7709
JK		 317 return FAILED;
318 }
4183122d
JK		 319 conn = session->leadconn;
320 beiscsi_conn = conn->dd_data;
321 phba = beiscsi_conn->phba;
322 cid = beiscsi_conn->beiscsi_conn_cid;
323 inv_tbl = phba->inv_tbl;
324 memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
325 num_invalidate = 0;
326 for (i = 0; i < conn->session->cmds_max; i++) {
327 abrt_task = conn->session->cmds[i];
328 abrt_io_task = abrt_task->dd_data;
329 if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
330 continue;
331
126e964a 332 if (sc->device->lun != abrt_task->sc->device->lun)
4183122d
JK		 333 continue;
334
7626c06b
JK		 335 /* Invalidate WRB Posted for this Task */
336 AMAP_SET_BITS(struct amap_iscsi_wrb, invld,
337 abrt_io_task->pwrb_handle->pwrb,
338 1);
339
4183122d
JK		 340 inv_tbl->cid = cid;
341 inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
342 num_invalidate++;
343 inv_tbl++;
344 }
659743b0 345 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 346 inv_tbl = phba->inv_tbl;
347
3cbb7a74
JK		 348 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
349 sizeof(struct invalidate_commands_params_in),
350 &nonemb_cmd.dma);
351 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 352 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
353 "BM_%d : Failed to allocate memory for"
354 "mgmt_invalidate_icds\n");
3cbb7a74
JK		 355 return FAILED;
356 }
357 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
358 memset(nonemb_cmd.va, 0, nonemb_cmd.size);
359 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
360 cid, &nonemb_cmd);
4183122d 361 if (!tag) {
99bc5d55
JSJ		 362 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
363 "BM_%d : mgmt_invalidate_icds could not be"
364 " submitted\n");
3cbb7a74
JK		 365 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
366 nonemb_cmd.va, nonemb_cmd.dma);
4183122d 367 return FAILED;
4183122d 368 }
e175defe 369
1957aa7f
JK		 370 rc = beiscsi_mccq_compl(phba, tag, NULL, &nonemb_cmd);
371 if (rc != -EBUSY)
372 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
373 nonemb_cmd.va, nonemb_cmd.dma);
4183122d 374 return iscsi_eh_device_reset(sc);
4183122d
JK		 375}
376
c7acc5b8
JK		 377static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
378{
379 struct beiscsi_hba *phba = data;
f457a46f
MC		 380 struct mgmt_session_info *boot_sess = &phba->boot_sess;
381 struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
c7acc5b8
JK		 382 char *str = buf;
383 int rc;
384
385 switch (type) {
386 case ISCSI_BOOT_TGT_NAME:
387 rc = sprintf(buf, "%.*s\n",
f457a46f
MC		 388 (int)strlen(boot_sess->target_name),
389 (char *)&boot_sess->target_name);
c7acc5b8
JK		 390 break;
391 case ISCSI_BOOT_TGT_IP_ADDR:
f457a46f 392 if (boot_conn->dest_ipaddr.ip_type == 0x1)
c7acc5b8 393 rc = sprintf(buf, "%pI4\n",
0e43895e 394 (char *)&boot_conn->dest_ipaddr.addr);
c7acc5b8
JK		 395 else
396 rc = sprintf(str, "%pI6\n",
0e43895e 397 (char *)&boot_conn->dest_ipaddr.addr);
c7acc5b8
JK		 398 break;
399 case ISCSI_BOOT_TGT_PORT:
f457a46f 400 rc = sprintf(str, "%d\n", boot_conn->dest_port);
c7acc5b8
JK		 401 break;
402
403 case ISCSI_BOOT_TGT_CHAP_NAME:
404 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 405 boot_conn->negotiated_login_options.auth_data.chap.
406 target_chap_name_length,
407 (char *)&boot_conn->negotiated_login_options.
408 auth_data.chap.target_chap_name);
c7acc5b8
JK		 409 break;
410 case ISCSI_BOOT_TGT_CHAP_SECRET:
411 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 412 boot_conn->negotiated_login_options.auth_data.chap.
413 target_secret_length,
414 (char *)&boot_conn->negotiated_login_options.
415 auth_data.chap.target_secret);
c7acc5b8
JK		 416 break;
417 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
418 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 419 boot_conn->negotiated_login_options.auth_data.chap.
420 intr_chap_name_length,
421 (char *)&boot_conn->negotiated_login_options.
422 auth_data.chap.intr_chap_name);
c7acc5b8
JK		 423 break;
424 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
f457a46f
MC		 425 rc = sprintf(str, "%.*s\n",
426 boot_conn->negotiated_login_options.auth_data.chap.
427 intr_secret_length,
428 (char *)&boot_conn->negotiated_login_options.
429 auth_data.chap.intr_secret);
c7acc5b8
JK		 430 break;
431 case ISCSI_BOOT_TGT_FLAGS:
f457a46f 432 rc = sprintf(str, "2\n");
c7acc5b8
JK		 433 break;
434 case ISCSI_BOOT_TGT_NIC_ASSOC:
f457a46f 435 rc = sprintf(str, "0\n");
c7acc5b8
JK		 436 break;
437 default:
438 rc = -ENOSYS;
439 break;
440 }
441 return rc;
442}
443
444static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
445{
446 struct beiscsi_hba *phba = data;
447 char *str = buf;
448 int rc;
449
450 switch (type) {
451 case ISCSI_BOOT_INI_INITIATOR_NAME:
452 rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
453 break;
454 default:
455 rc = -ENOSYS;
456 break;
457 }
458 return rc;
459}
460
461static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
462{
463 struct beiscsi_hba *phba = data;
464 char *str = buf;
465 int rc;
466
467 switch (type) {
468 case ISCSI_BOOT_ETH_FLAGS:
f457a46f 469 rc = sprintf(str, "2\n");
c7acc5b8
JK		 470 break;
471 case ISCSI_BOOT_ETH_INDEX:
f457a46f 472 rc = sprintf(str, "0\n");
c7acc5b8
JK		 473 break;
474 case ISCSI_BOOT_ETH_MAC:
0e43895e
MC		 475 rc = beiscsi_get_macaddr(str, phba);
476 break;
c7acc5b8
JK		 477 default:
478 rc = -ENOSYS;
479 break;
480 }
481 return rc;
482}
483
484
587a1f16 485static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
c7acc5b8 486{
587a1f16 487 umode_t rc;
c7acc5b8
JK		 488
489 switch (type) {
490 case ISCSI_BOOT_TGT_NAME:
491 case ISCSI_BOOT_TGT_IP_ADDR:
492 case ISCSI_BOOT_TGT_PORT:
493 case ISCSI_BOOT_TGT_CHAP_NAME:
494 case ISCSI_BOOT_TGT_CHAP_SECRET:
495 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
496 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
497 case ISCSI_BOOT_TGT_NIC_ASSOC:
498 case ISCSI_BOOT_TGT_FLAGS:
499 rc = S_IRUGO;
500 break;
501 default:
502 rc = 0;
503 break;
504 }
505 return rc;
506}
507
587a1f16 508static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
c7acc5b8 509{
587a1f16 510 umode_t rc;
c7acc5b8
JK		 511
512 switch (type) {
513 case ISCSI_BOOT_INI_INITIATOR_NAME:
514 rc = S_IRUGO;
515 break;
516 default:
517 rc = 0;
518 break;
519 }
520 return rc;
521}
522
523
587a1f16 524static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
c7acc5b8 525{
587a1f16 526 umode_t rc;
c7acc5b8
JK		 527
528 switch (type) {
529 case ISCSI_BOOT_ETH_FLAGS:
530 case ISCSI_BOOT_ETH_MAC:
531 case ISCSI_BOOT_ETH_INDEX:
532 rc = S_IRUGO;
533 break;
534 default:
535 rc = 0;
536 break;
537 }
538 return rc;
539}
540
bfead3b2
JK		 541/*------------------- PCI Driver operations and data ----------------- */
542static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
543 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
f98c96b0 544 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
bfead3b2
JK		 545 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
546 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
547 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
139a1b1e 548 { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
bfead3b2
JK		 549 { 0 }
550};
551MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
552
99bc5d55 553
6733b39a
JK		 554static struct scsi_host_template beiscsi_sht = {
555 .module = THIS_MODULE,
2f635883 556 .name = "Emulex 10Gbe open-iscsi Initiator Driver",
6733b39a
JK		 557 .proc_name = DRV_NAME,
558 .queuecommand = iscsi_queuecommand,
6733b39a
JK		 559 .change_queue_depth = iscsi_change_queue_depth,
560 .slave_configure = beiscsi_slave_configure,
561 .target_alloc = iscsi_target_alloc,
4183122d
JK		 562 .eh_abort_handler = beiscsi_eh_abort,
563 .eh_device_reset_handler = beiscsi_eh_device_reset,
309ce156 564 .eh_target_reset_handler = iscsi_eh_session_reset,
99bc5d55 565 .shost_attrs = beiscsi_attrs,
6733b39a
JK		 566 .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
567 .can_queue = BE2_IO_DEPTH,
568 .this_id = -1,
569 .max_sectors = BEISCSI_MAX_SECTORS,
570 .cmd_per_lun = BEISCSI_CMD_PER_LUN,
571 .use_clustering = ENABLE_CLUSTERING,
ffce3e2e
JK		 572 .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
573
6733b39a 574};
6733b39a 575
bfead3b2 576static struct scsi_transport_template *beiscsi_scsi_transport;
6733b39a
JK		 577
578static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
579{
580 struct beiscsi_hba *phba;
581 struct Scsi_Host *shost;
582
583 shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
584 if (!shost) {
99bc5d55
JSJ		 585 dev_err(&pcidev->dev,
586 "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
6733b39a
JK		 587 return NULL;
588 }
589 shost->dma_boundary = pcidev->dma_mask;
590 shost->max_id = BE2_MAX_SESSIONS;
591 shost->max_channel = 0;
592 shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
593 shost->max_lun = BEISCSI_NUM_MAX_LUN;
594 shost->transportt = beiscsi_scsi_transport;
6733b39a
JK		 595 phba = iscsi_host_priv(shost);
596 memset(phba, 0, sizeof(*phba));
597 phba->shost = shost;
598 phba->pcidev = pci_dev_get(pcidev);
2807afb7 599 pci_set_drvdata(pcidev, phba);
0e43895e 600 phba->interface_handle = 0xFFFFFFFF;
6733b39a 601
6733b39a 602 return phba;
6733b39a
JK		 603}
604
605static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
606{
607 if (phba->csr_va) {
608 iounmap(phba->csr_va);
609 phba->csr_va = NULL;
610 }
611 if (phba->db_va) {
612 iounmap(phba->db_va);
613 phba->db_va = NULL;
614 }
615 if (phba->pci_va) {
616 iounmap(phba->pci_va);
617 phba->pci_va = NULL;
618 }
619}
620
621static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
622 struct pci_dev *pcidev)
623{
624 u8 __iomem *addr;
f98c96b0 625 int pcicfg_reg;
6733b39a
JK		 626
627 addr = ioremap_nocache(pci_resource_start(pcidev, 2),
628 pci_resource_len(pcidev, 2));
629 if (addr == NULL)
630 return -ENOMEM;
631 phba->ctrl.csr = addr;
632 phba->csr_va = addr;
633 phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
634
635 addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
636 if (addr == NULL)
637 goto pci_map_err;
638 phba->ctrl.db = addr;
639 phba->db_va = addr;
640 phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
641
f98c96b0
JK		 642 if (phba->generation == BE_GEN2)
643 pcicfg_reg = 1;
644 else
645 pcicfg_reg = 0;
646
647 addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
648 pci_resource_len(pcidev, pcicfg_reg));
649
6733b39a
JK		 650 if (addr == NULL)
651 goto pci_map_err;
652 phba->ctrl.pcicfg = addr;
653 phba->pci_va = addr;
f98c96b0 654 phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
6733b39a
JK		 655 return 0;
656
657pci_map_err:
658 beiscsi_unmap_pci_function(phba);
659 return -ENOMEM;
660}
661
662static int beiscsi_enable_pci(struct pci_dev *pcidev)
663{
664 int ret;
665
666 ret = pci_enable_device(pcidev);
667 if (ret) {
99bc5d55
JSJ		 668 dev_err(&pcidev->dev,
669 "beiscsi_enable_pci - enable device failed\n");
6733b39a
JK		 670 return ret;
671 }
672
bfead3b2 673 pci_set_master(pcidev);
6c57625b
JK		 674 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64));
675 if (ret) {
676 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
677 if (ret) {
678 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
679 pci_disable_device(pcidev);
680 return ret;
681 } else {
682 ret = pci_set_consistent_dma_mask(pcidev,
683 DMA_BIT_MASK(32));
684 }
685 } else {
686 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
6733b39a
JK		 687 if (ret) {
688 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
689 pci_disable_device(pcidev);
690 return ret;
691 }
692 }
693 return 0;
694}
695
696static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
697{
698 struct be_ctrl_info *ctrl = &phba->ctrl;
699 struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
700 struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
701 int status = 0;
702
703 ctrl->pdev = pdev;
704 status = beiscsi_map_pci_bars(phba, pdev);
705 if (status)
706 return status;
6733b39a
JK		 707 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
708 mbox_mem_alloc->va = pci_alloc_consistent(pdev,
709 mbox_mem_alloc->size,
710 &mbox_mem_alloc->dma);
711 if (!mbox_mem_alloc->va) {
712 beiscsi_unmap_pci_function(phba);
a49e06d5 713 return -ENOMEM;
6733b39a
JK		 714 }
715
716 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
717 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
718 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
719 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
720 spin_lock_init(&ctrl->mbox_lock);
bfead3b2
JK		 721 spin_lock_init(&phba->ctrl.mcc_lock);
722 spin_lock_init(&phba->ctrl.mcc_cq_lock);
723
6733b39a
JK		 724 return status;
725}
726
843ae752
JK		 727/**
728 * beiscsi_get_params()- Set the config paramters
729 * @phba: ptr device priv structure
730 **/
6733b39a
JK		 731static void beiscsi_get_params(struct beiscsi_hba *phba)
732{
843ae752
JK		 733 uint32_t total_cid_count = 0;
734 uint32_t total_icd_count = 0;
735 uint8_t ulp_num = 0;
736
737 total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) +
738 BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1);
739
cf987b79
JK		 740 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
741 uint32_t align_mask = 0;
742 uint32_t icd_post_per_page = 0;
743 uint32_t icd_count_unavailable = 0;
744 uint32_t icd_start = 0, icd_count = 0;
745 uint32_t icd_start_align = 0, icd_count_align = 0;
746
843ae752 747 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
cf987b79
JK		 748 icd_start = phba->fw_config.iscsi_icd_start[ulp_num];
749 icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
750
751 /* Get ICD count that can be posted on each page */
752 icd_post_per_page = (PAGE_SIZE / (BE2_SGE *
753 sizeof(struct iscsi_sge)));
754 align_mask = (icd_post_per_page - 1);
755
756 /* Check if icd_start is aligned ICD per page posting */
757 if (icd_start % icd_post_per_page) {
758 icd_start_align = ((icd_start +
759 icd_post_per_page) &
760 ~(align_mask));
761 phba->fw_config.
762 iscsi_icd_start[ulp_num] =
763 icd_start_align;
764 }
765
766 icd_count_align = (icd_count & ~align_mask);
767
768 /* ICD discarded in the process of alignment */
769 if (icd_start_align)
770 icd_count_unavailable = ((icd_start_align -
771 icd_start) +
772 (icd_count -
773 icd_count_align));
774
775 /* Updated ICD count available */
776 phba->fw_config.iscsi_icd_count[ulp_num] = (icd_count -
777 icd_count_unavailable);
778
779 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
780 "BM_%d : Aligned ICD values\n"
781 "\t ICD Start : %d\n"
782 "\t ICD Count : %d\n"
783 "\t ICD Discarded : %d\n",
784 phba->fw_config.
785 iscsi_icd_start[ulp_num],
786 phba->fw_config.
787 iscsi_icd_count[ulp_num],
788 icd_count_unavailable);
843ae752
JK		 789 break;
790 }
cf987b79 791 }
843ae752 792
cf987b79 793 total_icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
843ae752
JK		 794 phba->params.ios_per_ctrl = (total_icd_count -
795 (total_cid_count +
796 BE2_TMFS + BE2_NOPOUT_REQ));
797 phba->params.cxns_per_ctrl = total_cid_count;
798 phba->params.asyncpdus_per_ctrl = total_cid_count;
799 phba->params.icds_per_ctrl = total_icd_count;
6733b39a
JK		 800 phba->params.num_sge_per_io = BE2_SGE;
801 phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
802 phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
803 phba->params.eq_timer = 64;
843ae752
JK		 804 phba->params.num_eq_entries = 1024;
805 phba->params.num_cq_entries = 1024;
6733b39a
JK		 806 phba->params.wrbs_per_cxn = 256;
807}
808
809static void hwi_ring_eq_db(struct beiscsi_hba *phba,
810 unsigned int id, unsigned int clr_interrupt,
811 unsigned int num_processed,
812 unsigned char rearm, unsigned char event)
813{
814 u32 val = 0;
e08b3c8b 815
6733b39a
JK		 816 if (rearm)
817 val |= 1 << DB_EQ_REARM_SHIFT;
818 if (clr_interrupt)
819 val |= 1 << DB_EQ_CLR_SHIFT;
820 if (event)
821 val |= 1 << DB_EQ_EVNT_SHIFT;
e08b3c8b 822
6733b39a 823 val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
e08b3c8b
JK		 824 /* Setting lower order EQ_ID Bits */
825 val |= (id & DB_EQ_RING_ID_LOW_MASK);
826
827 /* Setting Higher order EQ_ID Bits */
828 val |= (((id >> DB_EQ_HIGH_FEILD_SHIFT) &
829 DB_EQ_RING_ID_HIGH_MASK)
830 << DB_EQ_HIGH_SET_SHIFT);
831
6733b39a
JK		 832 iowrite32(val, phba->db_va + DB_EQ_OFFSET);
833}
834
bfead3b2
JK		 835/**
836 * be_isr_mcc - The isr routine of the driver.
837 * @irq: Not used
838 * @dev_id: Pointer to host adapter structure
839 */
840static irqreturn_t be_isr_mcc(int irq, void *dev_id)
841{
842 struct beiscsi_hba *phba;
843 struct be_eq_entry *eqe = NULL;
844 struct be_queue_info *eq;
845 struct be_queue_info *mcc;
846 unsigned int num_eq_processed;
847 struct be_eq_obj *pbe_eq;
848 unsigned long flags;
849
850 pbe_eq = dev_id;
851 eq = &pbe_eq->q;
852 phba = pbe_eq->phba;
853 mcc = &phba->ctrl.mcc_obj.cq;
854 eqe = queue_tail_node(eq);
bfead3b2
JK		 855
856 num_eq_processed = 0;
857
858 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
859 & EQE_VALID_MASK) {
860 if (((eqe->dw[offsetof(struct amap_eq_entry,
861 resource_id) / 32] &
862 EQE_RESID_MASK) >> 16) == mcc->id) {
863 spin_lock_irqsave(&phba->isr_lock, flags);
72fb46a9 864 pbe_eq->todo_mcc_cq = true;
bfead3b2
JK		 865 spin_unlock_irqrestore(&phba->isr_lock, flags);
866 }
867 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
868 queue_tail_inc(eq);
869 eqe = queue_tail_node(eq);
870 num_eq_processed++;
871 }
72fb46a9
JSJ		 872 if (pbe_eq->todo_mcc_cq)
873 queue_work(phba->wq, &pbe_eq->work_cqs);
bfead3b2
JK		 874 if (num_eq_processed)
875 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
876
877 return IRQ_HANDLED;
878}
879
880/**
881 * be_isr_msix - The isr routine of the driver.
882 * @irq: Not used
883 * @dev_id: Pointer to host adapter structure
884 */
885static irqreturn_t be_isr_msix(int irq, void *dev_id)
886{
887 struct beiscsi_hba *phba;
888 struct be_eq_entry *eqe = NULL;
889 struct be_queue_info *eq;
890 struct be_queue_info *cq;
891 unsigned int num_eq_processed;
892 struct be_eq_obj *pbe_eq;
bfead3b2
JK		 893
894 pbe_eq = dev_id;
895 eq = &pbe_eq->q;
896 cq = pbe_eq->cq;
897 eqe = queue_tail_node(eq);
bfead3b2
JK		 898
899 phba = pbe_eq->phba;
900 num_eq_processed = 0;
89f8b33c
JA		 901 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
902 & EQE_VALID_MASK) {
903 if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
904 blk_iopoll_sched(&pbe_eq->iopoll);
bfead3b2 905
89f8b33c
JA		 906 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
907 queue_tail_inc(eq);
908 eqe = queue_tail_node(eq);
909 num_eq_processed++;
bfead3b2 910 }
72fb46a9
JSJ		 911
912 if (num_eq_processed)
913 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
914
915 return IRQ_HANDLED;
bfead3b2
JK		 916}
917
6733b39a
JK		 918/**
919 * be_isr - The isr routine of the driver.
920 * @irq: Not used
921 * @dev_id: Pointer to host adapter structure
922 */
923static irqreturn_t be_isr(int irq, void *dev_id)
924{
925 struct beiscsi_hba *phba;
926 struct hwi_controller *phwi_ctrlr;
927 struct hwi_context_memory *phwi_context;
928 struct be_eq_entry *eqe = NULL;
929 struct be_queue_info *eq;
bfead3b2 930 struct be_queue_info *mcc;
6733b39a 931 unsigned long flags, index;
bfead3b2 932 unsigned int num_mcceq_processed, num_ioeq_processed;
6733b39a 933 struct be_ctrl_info *ctrl;
bfead3b2 934 struct be_eq_obj *pbe_eq;
6733b39a
JK		 935 int isr;
936
937 phba = dev_id;
6eab04a8 938 ctrl = &phba->ctrl;
bfead3b2
JK		 939 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
940 (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
941 if (!isr)
942 return IRQ_NONE;
6733b39a
JK		 943
944 phwi_ctrlr = phba->phwi_ctrlr;
945 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 946 pbe_eq = &phwi_context->be_eq[0];
947
948 eq = &phwi_context->be_eq[0].q;
949 mcc = &phba->ctrl.mcc_obj.cq;
6733b39a
JK		 950 index = 0;
951 eqe = queue_tail_node(eq);
6733b39a 952
bfead3b2
JK		 953 num_ioeq_processed = 0;
954 num_mcceq_processed = 0;
89f8b33c
JA		 955 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
956 & EQE_VALID_MASK) {
957 if (((eqe->dw[offsetof(struct amap_eq_entry,
958 resource_id) / 32] &
959 EQE_RESID_MASK) >> 16) == mcc->id) {
960 spin_lock_irqsave(&phba->isr_lock, flags);
961 pbe_eq->todo_mcc_cq = true;
962 spin_unlock_irqrestore(&phba->isr_lock, flags);
963 num_mcceq_processed++;
964 } else {
965 if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
966 blk_iopoll_sched(&pbe_eq->iopoll);
bfead3b2 967 num_ioeq_processed++;
6733b39a 968 }
89f8b33c
JA		 969 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
970 queue_tail_inc(eq);
971 eqe = queue_tail_node(eq);
972 }
973 if (num_ioeq_processed || num_mcceq_processed) {
974 if (pbe_eq->todo_mcc_cq)
72fb46a9 975 queue_work(phba->wq, &pbe_eq->work_cqs);
6733b39a 976
89f8b33c 977 if ((num_mcceq_processed) && (!num_ioeq_processed))
bfead3b2 978 hwi_ring_eq_db(phba, eq->id, 0,
89f8b33c
JA		 979 (num_ioeq_processed +
980 num_mcceq_processed) , 1, 1);
981 else
982 hwi_ring_eq_db(phba, eq->id, 0,
983 (num_ioeq_processed +
984 num_mcceq_processed), 0, 1);
985
986 return IRQ_HANDLED;
987 } else
988 return IRQ_NONE;
6733b39a
JK		 989}
990
991static int beiscsi_init_irqs(struct beiscsi_hba *phba)
992{
993 struct pci_dev *pcidev = phba->pcidev;
bfead3b2
JK		 994 struct hwi_controller *phwi_ctrlr;
995 struct hwi_context_memory *phwi_context;
4f5af07e 996 int ret, msix_vec, i, j;
6733b39a 997
bfead3b2
JK		 998 phwi_ctrlr = phba->phwi_ctrlr;
999 phwi_context = phwi_ctrlr->phwi_ctxt;
1000
1001 if (phba->msix_enabled) {
1002 for (i = 0; i < phba->num_cpus; i++) {
8fcfb210
JK		 1003 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
1004 GFP_KERNEL);
1005 if (!phba->msi_name[i]) {
1006 ret = -ENOMEM;
1007 goto free_msix_irqs;
1008 }
1009
1010 sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
1011 phba->shost->host_no, i);
bfead3b2 1012 msix_vec = phba->msix_entries[i].vector;
8fcfb210
JK		 1013 ret = request_irq(msix_vec, be_isr_msix, 0,
1014 phba->msi_name[i],
bfead3b2 1015 &phwi_context->be_eq[i]);
4f5af07e 1016 if (ret) {
99bc5d55
JSJ		 1017 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1018 "BM_%d : beiscsi_init_irqs-Failed to"
1019 "register msix for i = %d\n",
1020 i);
8fcfb210 1021 kfree(phba->msi_name[i]);
4f5af07e
JK		 1022 goto free_msix_irqs;
1023 }
bfead3b2 1024 }
8fcfb210
JK		 1025 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
1026 if (!phba->msi_name[i]) {
1027 ret = -ENOMEM;
1028 goto free_msix_irqs;
1029 }
1030 sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
1031 phba->shost->host_no);
bfead3b2 1032 msix_vec = phba->msix_entries[i].vector;
8fcfb210 1033 ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
bfead3b2 1034 &phwi_context->be_eq[i]);
4f5af07e 1035 if (ret) {
99bc5d55
JSJ		 1036 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
1037 "BM_%d : beiscsi_init_irqs-"
1038 "Failed to register beiscsi_msix_mcc\n");
8fcfb210 1039 kfree(phba->msi_name[i]);
4f5af07e
JK		 1040 goto free_msix_irqs;
1041 }
1042
bfead3b2
JK		 1043 } else {
1044 ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
1045 "beiscsi", phba);
1046 if (ret) {
99bc5d55
JSJ		 1047 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1048 "BM_%d : beiscsi_init_irqs-"
1049 "Failed to register irq\\n");
bfead3b2
JK		 1050 return ret;
1051 }
6733b39a
JK		 1052 }
1053 return 0;
4f5af07e 1054free_msix_irqs:
8fcfb210
JK		 1055 for (j = i - 1; j >= 0; j--) {
1056 kfree(phba->msi_name[j]);
1057 msix_vec = phba->msix_entries[j].vector;
4f5af07e 1058 free_irq(msix_vec, &phwi_context->be_eq[j]);
8fcfb210 1059 }
4f5af07e 1060 return ret;
6733b39a
JK		 1061}
1062
e08b3c8b 1063void hwi_ring_cq_db(struct beiscsi_hba *phba,
6733b39a
JK		 1064 unsigned int id, unsigned int num_processed,
1065 unsigned char rearm, unsigned char event)
1066{
1067 u32 val = 0;
e08b3c8b 1068
6733b39a
JK		 1069 if (rearm)
1070 val |= 1 << DB_CQ_REARM_SHIFT;
e08b3c8b 1071
6733b39a 1072 val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
e08b3c8b
JK		 1073
1074 /* Setting lower order CQ_ID Bits */
1075 val |= (id & DB_CQ_RING_ID_LOW_MASK);
1076
1077 /* Setting Higher order CQ_ID Bits */
1078 val |= (((id >> DB_CQ_HIGH_FEILD_SHIFT) &
1079 DB_CQ_RING_ID_HIGH_MASK)
1080 << DB_CQ_HIGH_SET_SHIFT);
1081
6733b39a
JK		 1082 iowrite32(val, phba->db_va + DB_CQ_OFFSET);
1083}
1084
6733b39a
JK		 1085static unsigned int
1086beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
1087 struct beiscsi_hba *phba,
6733b39a
JK		 1088 struct pdu_base *ppdu,
1089 unsigned long pdu_len,
1090 void *pbuffer, unsigned long buf_len)
1091{
1092 struct iscsi_conn *conn = beiscsi_conn->conn;
1093 struct iscsi_session *session = conn->session;
bfead3b2
JK		 1094 struct iscsi_task *task;
1095 struct beiscsi_io_task *io_task;
1096 struct iscsi_hdr *login_hdr;
6733b39a
JK		 1097
1098 switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
1099 PDUBASE_OPCODE_MASK) {
1100 case ISCSI_OP_NOOP_IN:
1101 pbuffer = NULL;
1102 buf_len = 0;
1103 break;
1104 case ISCSI_OP_ASYNC_EVENT:
1105 break;
1106 case ISCSI_OP_REJECT:
1107 WARN_ON(!pbuffer);
1108 WARN_ON(!(buf_len == 48));
99bc5d55
JSJ		 1109 beiscsi_log(phba, KERN_ERR,
1110 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1111 "BM_%d : In ISCSI_OP_REJECT\n");
6733b39a
JK		 1112 break;
1113 case ISCSI_OP_LOGIN_RSP:
7bd6e25c 1114 case ISCSI_OP_TEXT_RSP:
bfead3b2
JK		 1115 task = conn->login_task;
1116 io_task = task->dd_data;
1117 login_hdr = (struct iscsi_hdr *)ppdu;
1118 login_hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1119 break;
1120 default:
99bc5d55
JSJ		 1121 beiscsi_log(phba, KERN_WARNING,
1122 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1123 "BM_%d : Unrecognized opcode 0x%x in async msg\n",
1124 (ppdu->
6733b39a 1125 dw[offsetof(struct amap_pdu_base, opcode) / 32]
99bc5d55 1126 & PDUBASE_OPCODE_MASK));
6733b39a
JK		 1127 return 1;
1128 }
1129
659743b0 1130 spin_lock_bh(&session->back_lock);
6733b39a 1131 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
659743b0 1132 spin_unlock_bh(&session->back_lock);
6733b39a
JK		 1133 return 0;
1134}
1135
1136static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
1137{
1138 struct sgl_handle *psgl_handle;
1139
1140 if (phba->io_sgl_hndl_avbl) {
99bc5d55
JSJ		 1141 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
1142 "BM_%d : In alloc_io_sgl_handle,"
1143 " io_sgl_alloc_index=%d\n",
1144 phba->io_sgl_alloc_index);
1145
6733b39a
JK		 1146 psgl_handle = phba->io_sgl_hndl_base[phba->
1147 io_sgl_alloc_index];
1148 phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
1149 phba->io_sgl_hndl_avbl--;
bfead3b2
JK		 1150 if (phba->io_sgl_alloc_index == (phba->params.
1151 ios_per_ctrl - 1))
6733b39a
JK		 1152 phba->io_sgl_alloc_index = 0;
1153 else
1154 phba->io_sgl_alloc_index++;
1155 } else
1156 psgl_handle = NULL;
1157 return psgl_handle;
1158}
1159
1160static void
1161free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
1162{
99bc5d55
JSJ		 1163 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
1164 "BM_%d : In free_,io_sgl_free_index=%d\n",
1165 phba->io_sgl_free_index);
1166
6733b39a
JK		 1167 if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
1168 /*
1169 * this can happen if clean_task is called on a task that
1170 * failed in xmit_task or alloc_pdu.
1171 */
99bc5d55
JSJ		 1172 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
1173 "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
1174 "value there=%p\n", phba->io_sgl_free_index,
1175 phba->io_sgl_hndl_base
1176 [phba->io_sgl_free_index]);
6733b39a
JK		 1177 return;
1178 }
1179 phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
1180 phba->io_sgl_hndl_avbl++;
1181 if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
1182 phba->io_sgl_free_index = 0;
1183 else
1184 phba->io_sgl_free_index++;
1185}
1186
1187/**
1188 * alloc_wrb_handle - To allocate a wrb handle
1189 * @phba: The hba pointer
1190 * @cid: The cid to use for allocation
6733b39a
JK		 1191 *
1192 * This happens under session_lock until submission to chip
1193 */
d5431488 1194struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
6733b39a
JK		 1195{
1196 struct hwi_wrb_context *pwrb_context;
1197 struct hwi_controller *phwi_ctrlr;
d5431488 1198 struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
a7909b39 1199 uint16_t cri_index = BE_GET_CRI_FROM_CID(cid);
6733b39a
JK		 1200
1201 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 1202 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
d5431488 1203 if (pwrb_context->wrb_handles_available >= 2) {
bfead3b2
JK		 1204 pwrb_handle = pwrb_context->pwrb_handle_base[
1205 pwrb_context->alloc_index];
1206 pwrb_context->wrb_handles_available--;
bfead3b2
JK		 1207 if (pwrb_context->alloc_index ==
1208 (phba->params.wrbs_per_cxn - 1))
1209 pwrb_context->alloc_index = 0;
1210 else
1211 pwrb_context->alloc_index++;
d5431488
JK		 1212 pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
1213 pwrb_context->alloc_index];
1214 pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
bfead3b2
JK		 1215 } else
1216 pwrb_handle = NULL;
6733b39a
JK		 1217 return pwrb_handle;
1218}
1219
1220/**
1221 * free_wrb_handle - To free the wrb handle back to pool
1222 * @phba: The hba pointer
1223 * @pwrb_context: The context to free from
1224 * @pwrb_handle: The wrb_handle to free
1225 *
1226 * This happens under session_lock until submission to chip
1227 */
1228static void
1229free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
1230 struct wrb_handle *pwrb_handle)
1231{
32951dd8 1232 pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
bfead3b2
JK		 1233 pwrb_context->wrb_handles_available++;
1234 if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
1235 pwrb_context->free_index = 0;
1236 else
1237 pwrb_context->free_index++;
1238
99bc5d55
JSJ		 1239 beiscsi_log(phba, KERN_INFO,
1240 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1241 "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
1242 "wrb_handles_available=%d\n",
1243 pwrb_handle, pwrb_context->free_index,
1244 pwrb_context->wrb_handles_available);
6733b39a
JK		 1245}
1246
1247static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
1248{
1249 struct sgl_handle *psgl_handle;
1250
1251 if (phba->eh_sgl_hndl_avbl) {
1252 psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
1253 phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
99bc5d55
JSJ		 1254 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
1255 "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
1256 phba->eh_sgl_alloc_index,
1257 phba->eh_sgl_alloc_index);
1258
6733b39a
JK		 1259 phba->eh_sgl_hndl_avbl--;
1260 if (phba->eh_sgl_alloc_index ==
1261 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
1262 1))
1263 phba->eh_sgl_alloc_index = 0;
1264 else
1265 phba->eh_sgl_alloc_index++;
1266 } else
1267 psgl_handle = NULL;
1268 return psgl_handle;
1269}
1270
1271void
1272free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
1273{
1274
99bc5d55
JSJ		 1275 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
1276 "BM_%d : In free_mgmt_sgl_handle,"
1277 "eh_sgl_free_index=%d\n",
1278 phba->eh_sgl_free_index);
1279
6733b39a
JK		 1280 if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
1281 /*
1282 * this can happen if clean_task is called on a task that
1283 * failed in xmit_task or alloc_pdu.
1284 */
99bc5d55
JSJ		 1285 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
1286 "BM_%d : Double Free in eh SGL ,"
1287 "eh_sgl_free_index=%d\n",
1288 phba->eh_sgl_free_index);
6733b39a
JK		 1289 return;
1290 }
1291 phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
1292 phba->eh_sgl_hndl_avbl++;
1293 if (phba->eh_sgl_free_index ==
1294 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
1295 phba->eh_sgl_free_index = 0;
1296 else
1297 phba->eh_sgl_free_index++;
1298}
1299
1300static void
1301be_complete_io(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1302 struct iscsi_task *task,
1303 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1304{
1305 struct beiscsi_io_task *io_task = task->dd_data;
1306 struct be_status_bhs *sts_bhs =
1307 (struct be_status_bhs *)io_task->cmd_bhs;
1308 struct iscsi_conn *conn = beiscsi_conn->conn;
6733b39a
JK		 1309 unsigned char *sense;
1310 u32 resid = 0, exp_cmdsn, max_cmdsn;
1311 u8 rsp, status, flags;
1312
73133261
JSJ		 1313 exp_cmdsn = csol_cqe->exp_cmdsn;
1314 max_cmdsn = (csol_cqe->exp_cmdsn +
1315 csol_cqe->cmd_wnd - 1);
1316 rsp = csol_cqe->i_resp;
1317 status = csol_cqe->i_sts;
1318 flags = csol_cqe->i_flags;
1319 resid = csol_cqe->res_cnt;
1320
bd535451 1321 if (!task->sc) {
da334977 1322 if (io_task->scsi_cmnd) {
bd535451 1323 scsi_dma_unmap(io_task->scsi_cmnd);
da334977
JK		 1324 io_task->scsi_cmnd = NULL;
1325 }
6733b39a 1326
bd535451
JK		 1327 return;
1328 }
6733b39a
JK		 1329 task->sc->result = (DID_OK << 16) | status;
1330 if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
1331 task->sc->result = DID_ERROR << 16;
1332 goto unmap;
1333 }
1334
1335 /* bidi not initially supported */
1336 if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
6733b39a
JK		 1337 if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
1338 task->sc->result = DID_ERROR << 16;
1339
1340 if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
1341 scsi_set_resid(task->sc, resid);
1342 if (!status && (scsi_bufflen(task->sc) - resid <
1343 task->sc->underflow))
1344 task->sc->result = DID_ERROR << 16;
1345 }
1346 }
1347
1348 if (status == SAM_STAT_CHECK_CONDITION) {
4053a4be 1349 u16 sense_len;
bfead3b2 1350 unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
4053a4be 1351
6733b39a 1352 sense = sts_bhs->sense_info + sizeof(unsigned short);
4053a4be 1353 sense_len = be16_to_cpu(*slen);
6733b39a
JK		 1354 memcpy(task->sc->sense_buffer, sense,
1355 min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
1356 }
756d29c8 1357
73133261
JSJ		 1358 if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ)
1359 conn->rxdata_octets += resid;
6733b39a
JK		 1360unmap:
1361 scsi_dma_unmap(io_task->scsi_cmnd);
da334977 1362 io_task->scsi_cmnd = NULL;
6733b39a
JK		 1363 iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
1364}
1365
1366static void
1367be_complete_logout(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1368 struct iscsi_task *task,
1369 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1370{
1371 struct iscsi_logout_rsp *hdr;
bfead3b2 1372 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1373 struct iscsi_conn *conn = beiscsi_conn->conn;
1374
1375 hdr = (struct iscsi_logout_rsp *)task->hdr;
7bd6e25c 1376 hdr->opcode = ISCSI_OP_LOGOUT_RSP;
6733b39a
JK		 1377 hdr->t2wait = 5;
1378 hdr->t2retain = 0;
73133261
JSJ		 1379 hdr->flags = csol_cqe->i_flags;
1380 hdr->response = csol_cqe->i_resp;
702dc5e8
JK		 1381 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
1382 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1383 csol_cqe->cmd_wnd - 1);
73133261 1384
7bd6e25c
JK		 1385 hdr->dlength[0] = 0;
1386 hdr->dlength[1] = 0;
1387 hdr->dlength[2] = 0;
6733b39a 1388 hdr->hlength = 0;
bfead3b2 1389 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1390 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1391}
1392
1393static void
1394be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1395 struct iscsi_task *task,
1396 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1397{
1398 struct iscsi_tm_rsp *hdr;
1399 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1400 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1401
1402 hdr = (struct iscsi_tm_rsp *)task->hdr;
7bd6e25c 1403 hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
73133261
JSJ		 1404 hdr->flags = csol_cqe->i_flags;
1405 hdr->response = csol_cqe->i_resp;
702dc5e8
JK		 1406 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
1407 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1408 csol_cqe->cmd_wnd - 1);
73133261 1409
bfead3b2 1410 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1411 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1412}
1413
1414static void
1415hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
1416 struct beiscsi_hba *phba, struct sol_cqe *psol)
1417{
1418 struct hwi_wrb_context *pwrb_context;
bfead3b2 1419 struct wrb_handle *pwrb_handle = NULL;
6733b39a 1420 struct hwi_controller *phwi_ctrlr;
bfead3b2
JK		 1421 struct iscsi_task *task;
1422 struct beiscsi_io_task *io_task;
a7909b39 1423 uint16_t wrb_index, cid, cri_index;
6733b39a
JK		 1424
1425 phwi_ctrlr = phba->phwi_ctrlr;
2c9dfd36
JK		 1426 if (is_chip_be2_be3r(phba)) {
1427 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
73133261 1428 wrb_idx, psol);
2c9dfd36 1429 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
73133261
JSJ		 1430 cid, psol);
1431 } else {
2c9dfd36 1432 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
73133261 1433 wrb_idx, psol);
2c9dfd36 1434 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
73133261
JSJ		 1435 cid, psol);
1436 }
1437
a7909b39
JK		 1438 cri_index = BE_GET_CRI_FROM_CID(cid);
1439 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
73133261 1440 pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index];
32951dd8 1441 task = pwrb_handle->pio_handle;
35e66019 1442
bfead3b2 1443 io_task = task->dd_data;
4a4a11b9
JK		 1444 memset(io_task->pwrb_handle->pwrb, 0, sizeof(struct iscsi_wrb));
1445 iscsi_put_task(task);
6733b39a
JK		 1446}
1447
1448static void
1449be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1450 struct iscsi_task *task,
1451 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1452{
1453 struct iscsi_nopin *hdr;
1454 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1455 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1456
1457 hdr = (struct iscsi_nopin *)task->hdr;
73133261
JSJ		 1458 hdr->flags = csol_cqe->i_flags;
1459 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
702dc5e8
JK		 1460 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1461 csol_cqe->cmd_wnd - 1);
73133261 1462
6733b39a 1463 hdr->opcode = ISCSI_OP_NOOP_IN;
bfead3b2 1464 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1465 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1466}
1467
73133261
JSJ		 1468static void adapter_get_sol_cqe(struct beiscsi_hba *phba,
1469 struct sol_cqe *psol,
1470 struct common_sol_cqe *csol_cqe)
1471{
2c9dfd36
JK		 1472 if (is_chip_be2_be3r(phba)) {
1473 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe,
1474 i_exp_cmd_sn, psol);
1475 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe,
1476 i_res_cnt, psol);
1477 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
1478 i_cmd_wnd, psol);
1479 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe,
1480 wrb_index, psol);
1481 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe,
1482 cid, psol);
1483 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe,
1484 hw_sts, psol);
1485 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe,
1486 i_resp, psol);
1487 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe,
1488 i_sts, psol);
1489 csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe,
1490 i_flags, psol);
1491 } else {
73133261
JSJ		 1492 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1493 i_exp_cmd_sn, psol);
1494 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1495 i_res_cnt, psol);
1496 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1497 wrb_index, psol);
1498 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1499 cid, psol);
1500 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1501 hw_sts, psol);
702dc5e8 1502 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2,
73133261
JSJ		 1503 i_cmd_wnd, psol);
1504 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1505 cmd_cmpl, psol))
1506 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1507 i_sts, psol);
1508 else
1509 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1510 i_sts, psol);
1511 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1512 u, psol))
1513 csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW;
1514
1515 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1516 o, psol))
1517 csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW;
73133261
JSJ		 1518 }
1519}
1520
1521
6733b39a
JK		 1522static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
1523 struct beiscsi_hba *phba, struct sol_cqe *psol)
1524{
1525 struct hwi_wrb_context *pwrb_context;
1526 struct wrb_handle *pwrb_handle;
1527 struct iscsi_wrb *pwrb = NULL;
1528 struct hwi_controller *phwi_ctrlr;
1529 struct iscsi_task *task;
bfead3b2 1530 unsigned int type;
6733b39a
JK		 1531 struct iscsi_conn *conn = beiscsi_conn->conn;
1532 struct iscsi_session *session = conn->session;
73133261 1533 struct common_sol_cqe csol_cqe = {0};
a7909b39 1534 uint16_t cri_index = 0;
6733b39a
JK		 1535
1536 phwi_ctrlr = phba->phwi_ctrlr;
73133261
JSJ		 1537
1538 /* Copy the elements to a common structure */
1539 adapter_get_sol_cqe(phba, psol, &csol_cqe);
1540
a7909b39
JK		 1541 cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid);
1542 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
73133261
JSJ		 1543
1544 pwrb_handle = pwrb_context->pwrb_handle_basestd[
1545 csol_cqe.wrb_index];
1546
32951dd8
JK		 1547 task = pwrb_handle->pio_handle;
1548 pwrb = pwrb_handle->pwrb;
73133261 1549 type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type;
32951dd8 1550
659743b0 1551 spin_lock_bh(&session->back_lock);
bfead3b2 1552 switch (type) {
6733b39a
JK		 1553 case HWH_TYPE_IO:
1554 case HWH_TYPE_IO_RD:
1555 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
dafab8e0 1556 ISCSI_OP_NOOP_OUT)
73133261 1557 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
dafab8e0 1558 else
73133261 1559 be_complete_io(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1560 break;
1561
1562 case HWH_TYPE_LOGOUT:
dafab8e0 1563 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
73133261 1564 be_complete_logout(beiscsi_conn, task, &csol_cqe);
dafab8e0 1565 else
73133261 1566 be_complete_tmf(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1567 break;
1568
1569 case HWH_TYPE_LOGIN:
99bc5d55
JSJ		 1570 beiscsi_log(phba, KERN_ERR,
1571 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1572 "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
1573 " hwi_complete_cmd- Solicited path\n");
6733b39a
JK		 1574 break;
1575
6733b39a 1576 case HWH_TYPE_NOP:
73133261 1577 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1578 break;
1579
1580 default:
99bc5d55
JSJ		 1581 beiscsi_log(phba, KERN_WARNING,
1582 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1583 "BM_%d : In hwi_complete_cmd, unknown type = %d"
1584 "wrb_index 0x%x CID 0x%x\n", type,
73133261
JSJ		 1585 csol_cqe.wrb_index,
1586 csol_cqe.cid);
6733b39a
JK		 1587 break;
1588 }
35e66019 1589
659743b0 1590 spin_unlock_bh(&session->back_lock);
6733b39a
JK		 1591}
1592
1593static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
1594 *pasync_ctx, unsigned int is_header,
1595 unsigned int host_write_ptr)
1596{
1597 if (is_header)
1598 return &pasync_ctx->async_entry[host_write_ptr].
1599 header_busy_list;
1600 else
1601 return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
1602}
1603
1604static struct async_pdu_handle *
1605hwi_get_async_handle(struct beiscsi_hba *phba,
1606 struct beiscsi_conn *beiscsi_conn,
1607 struct hwi_async_pdu_context *pasync_ctx,
1608 struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
1609{
1610 struct be_bus_address phys_addr;
1611 struct list_head *pbusy_list;
1612 struct async_pdu_handle *pasync_handle = NULL;
6733b39a 1613 unsigned char is_header = 0;
73133261
JSJ		 1614 unsigned int index, dpl;
1615
2c9dfd36
JK		 1616 if (is_chip_be2_be3r(phba)) {
1617 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
73133261 1618 dpl, pdpdu_cqe);
2c9dfd36 1619 index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
73133261
JSJ		 1620 index, pdpdu_cqe);
1621 } else {
2c9dfd36 1622 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
73133261 1623 dpl, pdpdu_cqe);
2c9dfd36 1624 index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
73133261
JSJ		 1625 index, pdpdu_cqe);
1626 }
6733b39a
JK		 1627
1628 phys_addr.u.a32.address_lo =
73133261
JSJ		 1629 (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1630 db_addr_lo) / 32] - dpl);
6733b39a 1631 phys_addr.u.a32.address_hi =
73133261
JSJ		 1632 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1633 db_addr_hi) / 32];
6733b39a
JK		 1634
1635 phys_addr.u.a64.address =
1636 *((unsigned long long *)(&phys_addr.u.a64.address));
1637
1638 switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
1639 & PDUCQE_CODE_MASK) {
1640 case UNSOL_HDR_NOTIFY:
1641 is_header = 1;
1642
73133261
JSJ		 1643 pbusy_list = hwi_get_async_busy_list(pasync_ctx,
1644 is_header, index);
6733b39a
JK		 1645 break;
1646 case UNSOL_DATA_NOTIFY:
73133261
JSJ		 1647 pbusy_list = hwi_get_async_busy_list(pasync_ctx,
1648 is_header, index);
6733b39a
JK		 1649 break;
1650 default:
1651 pbusy_list = NULL;
99bc5d55
JSJ		 1652 beiscsi_log(phba, KERN_WARNING,
1653 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1654 "BM_%d : Unexpected code=%d\n",
1655 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1656 code) / 32] & PDUCQE_CODE_MASK);
6733b39a
JK		 1657 return NULL;
1658 }
1659
6733b39a
JK		 1660 WARN_ON(list_empty(pbusy_list));
1661 list_for_each_entry(pasync_handle, pbusy_list, link) {
dc63aac6 1662 if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
6733b39a
JK		 1663 break;
1664 }
1665
1666 WARN_ON(!pasync_handle);
1667
8a86e833
JK		 1668 pasync_handle->cri = BE_GET_ASYNC_CRI_FROM_CID(
1669 beiscsi_conn->beiscsi_conn_cid);
6733b39a 1670 pasync_handle->is_header = is_header;
73133261
JSJ		 1671 pasync_handle->buffer_len = dpl;
1672 *pcq_index = index;
6733b39a 1673
6733b39a
JK		 1674 return pasync_handle;
1675}
1676
1677static unsigned int
99bc5d55
JSJ		 1678hwi_update_async_writables(struct beiscsi_hba *phba,
1679 struct hwi_async_pdu_context *pasync_ctx,
1680 unsigned int is_header, unsigned int cq_index)
6733b39a
JK		 1681{
1682 struct list_head *pbusy_list;
1683 struct async_pdu_handle *pasync_handle;
1684 unsigned int num_entries, writables = 0;
1685 unsigned int *pep_read_ptr, *pwritables;
1686
dc63aac6 1687 num_entries = pasync_ctx->num_entries;
6733b39a
JK		 1688 if (is_header) {
1689 pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
1690 pwritables = &pasync_ctx->async_header.writables;
6733b39a
JK		 1691 } else {
1692 pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
1693 pwritables = &pasync_ctx->async_data.writables;
6733b39a
JK		 1694 }
1695
1696 while ((*pep_read_ptr) != cq_index) {
1697 (*pep_read_ptr)++;
1698 *pep_read_ptr = (*pep_read_ptr) % num_entries;
1699
1700 pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
1701 *pep_read_ptr);
1702 if (writables == 0)
1703 WARN_ON(list_empty(pbusy_list));
1704
1705 if (!list_empty(pbusy_list)) {
1706 pasync_handle = list_entry(pbusy_list->next,
1707 struct async_pdu_handle,
1708 link);
1709 WARN_ON(!pasync_handle);
1710 pasync_handle->consumed = 1;
1711 }
1712
1713 writables++;
1714 }
1715
1716 if (!writables) {
99bc5d55
JSJ		 1717 beiscsi_log(phba, KERN_ERR,
1718 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1719 "BM_%d : Duplicate notification received - index 0x%x!!\n",
1720 cq_index);
6733b39a
JK		 1721 WARN_ON(1);
1722 }
1723
1724 *pwritables = *pwritables + writables;
1725 return 0;
1726}
1727
9728d8d0 1728static void hwi_free_async_msg(struct beiscsi_hba *phba,
8a86e833
JK		 1729 struct hwi_async_pdu_context *pasync_ctx,
1730 unsigned int cri)
6733b39a 1731{
6733b39a
JK		 1732 struct async_pdu_handle *pasync_handle, *tmp_handle;
1733 struct list_head *plist;
6733b39a 1734
6733b39a 1735 plist = &pasync_ctx->async_entry[cri].wait_queue.list;
6733b39a
JK		 1736 list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
1737 list_del(&pasync_handle->link);
1738
9728d8d0 1739 if (pasync_handle->is_header) {
6733b39a
JK		 1740 list_add_tail(&pasync_handle->link,
1741 &pasync_ctx->async_header.free_list);
1742 pasync_ctx->async_header.free_entries++;
6733b39a
JK		 1743 } else {
1744 list_add_tail(&pasync_handle->link,
1745 &pasync_ctx->async_data.free_list);
1746 pasync_ctx->async_data.free_entries++;
6733b39a
JK		 1747 }
1748 }
1749
1750 INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
1751 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
1752 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
6733b39a
JK		 1753}
1754
1755static struct phys_addr *
1756hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
1757 unsigned int is_header, unsigned int host_write_ptr)
1758{
1759 struct phys_addr *pasync_sge = NULL;
1760
1761 if (is_header)
1762 pasync_sge = pasync_ctx->async_header.ring_base;
1763 else
1764 pasync_sge = pasync_ctx->async_data.ring_base;
1765
1766 return pasync_sge + host_write_ptr;
1767}
1768
1769static void hwi_post_async_buffers(struct beiscsi_hba *phba,
8a86e833 1770 unsigned int is_header, uint8_t ulp_num)
6733b39a
JK		 1771{
1772 struct hwi_controller *phwi_ctrlr;
1773 struct hwi_async_pdu_context *pasync_ctx;
1774 struct async_pdu_handle *pasync_handle;
1775 struct list_head *pfree_link, *pbusy_list;
1776 struct phys_addr *pasync_sge;
1777 unsigned int ring_id, num_entries;
8a86e833 1778 unsigned int host_write_num, doorbell_offset;
6733b39a
JK		 1779 unsigned int writables;
1780 unsigned int i = 0;
1781 u32 doorbell = 0;
1782
1783 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833 1784 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num);
dc63aac6 1785 num_entries = pasync_ctx->num_entries;
6733b39a
JK		 1786
1787 if (is_header) {
6733b39a
JK		 1788 writables = min(pasync_ctx->async_header.writables,
1789 pasync_ctx->async_header.free_entries);
1790 pfree_link = pasync_ctx->async_header.free_list.next;
1791 host_write_num = pasync_ctx->async_header.host_write_ptr;
8a86e833
JK		 1792 ring_id = phwi_ctrlr->default_pdu_hdr[ulp_num].id;
1793 doorbell_offset = phwi_ctrlr->default_pdu_hdr[ulp_num].
1794 doorbell_offset;
6733b39a 1795 } else {
6733b39a
JK		 1796 writables = min(pasync_ctx->async_data.writables,
1797 pasync_ctx->async_data.free_entries);
1798 pfree_link = pasync_ctx->async_data.free_list.next;
1799 host_write_num = pasync_ctx->async_data.host_write_ptr;
8a86e833
JK		 1800 ring_id = phwi_ctrlr->default_pdu_data[ulp_num].id;
1801 doorbell_offset = phwi_ctrlr->default_pdu_data[ulp_num].
1802 doorbell_offset;
6733b39a
JK		 1803 }
1804
1805 writables = (writables / 8) * 8;
1806 if (writables) {
1807 for (i = 0; i < writables; i++) {
1808 pbusy_list =
1809 hwi_get_async_busy_list(pasync_ctx, is_header,
1810 host_write_num);
1811 pasync_handle =
1812 list_entry(pfree_link, struct async_pdu_handle,
1813 link);
1814 WARN_ON(!pasync_handle);
1815 pasync_handle->consumed = 0;
1816
1817 pfree_link = pfree_link->next;
1818
1819 pasync_sge = hwi_get_ring_address(pasync_ctx,
1820 is_header, host_write_num);
1821
1822 pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
1823 pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
1824
1825 list_move(&pasync_handle->link, pbusy_list);
1826
1827 host_write_num++;
1828 host_write_num = host_write_num % num_entries;
1829 }
1830
1831 if (is_header) {
1832 pasync_ctx->async_header.host_write_ptr =
1833 host_write_num;
1834 pasync_ctx->async_header.free_entries -= writables;
1835 pasync_ctx->async_header.writables -= writables;
1836 pasync_ctx->async_header.busy_entries += writables;
1837 } else {
1838 pasync_ctx->async_data.host_write_ptr = host_write_num;
1839 pasync_ctx->async_data.free_entries -= writables;
1840 pasync_ctx->async_data.writables -= writables;
1841 pasync_ctx->async_data.busy_entries += writables;
1842 }
1843
1844 doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
1845 doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
1846 doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
1847 doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
1848 << DB_DEF_PDU_CQPROC_SHIFT;
1849
8a86e833 1850 iowrite32(doorbell, phba->db_va + doorbell_offset);
6733b39a
JK		 1851 }
1852}
1853
1854static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
1855 struct beiscsi_conn *beiscsi_conn,
1856 struct i_t_dpdu_cqe *pdpdu_cqe)
1857{
1858 struct hwi_controller *phwi_ctrlr;
1859 struct hwi_async_pdu_context *pasync_ctx;
1860 struct async_pdu_handle *pasync_handle = NULL;
1861 unsigned int cq_index = -1;
8a86e833
JK		 1862 uint16_t cri_index = BE_GET_CRI_FROM_CID(
1863 beiscsi_conn->beiscsi_conn_cid);
6733b39a
JK		 1864
1865 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833
JK		 1866 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
1867 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
1868 cri_index));
6733b39a
JK		 1869
1870 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
1871 pdpdu_cqe, &cq_index);
1872 BUG_ON(pasync_handle->is_header != 0);
1873 if (pasync_handle->consumed == 0)
99bc5d55
JSJ		 1874 hwi_update_async_writables(phba, pasync_ctx,
1875 pasync_handle->is_header, cq_index);
6733b39a 1876
8a86e833
JK		 1877 hwi_free_async_msg(phba, pasync_ctx, pasync_handle->cri);
1878 hwi_post_async_buffers(phba, pasync_handle->is_header,
1879 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
1880 cri_index));
6733b39a
JK		 1881}
1882
1883static unsigned int
1884hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
1885 struct beiscsi_hba *phba,
1886 struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
1887{
1888 struct list_head *plist;
1889 struct async_pdu_handle *pasync_handle;
1890 void *phdr = NULL;
1891 unsigned int hdr_len = 0, buf_len = 0;
1892 unsigned int status, index = 0, offset = 0;
1893 void *pfirst_buffer = NULL;
1894 unsigned int num_buf = 0;
1895
1896 plist = &pasync_ctx->async_entry[cri].wait_queue.list;
1897
1898 list_for_each_entry(pasync_handle, plist, link) {
1899 if (index == 0) {
1900 phdr = pasync_handle->pbuffer;
1901 hdr_len = pasync_handle->buffer_len;
1902 } else {
1903 buf_len = pasync_handle->buffer_len;
1904 if (!num_buf) {
1905 pfirst_buffer = pasync_handle->pbuffer;
1906 num_buf++;
1907 }
1908 memcpy(pfirst_buffer + offset,
1909 pasync_handle->pbuffer, buf_len);
f2ba02b8 1910 offset += buf_len;
6733b39a
JK		 1911 }
1912 index++;
1913 }
1914
1915 status = beiscsi_process_async_pdu(beiscsi_conn, phba,
7da50879 1916 phdr, hdr_len, pfirst_buffer,
f2ba02b8 1917 offset);
6733b39a 1918
8a86e833 1919 hwi_free_async_msg(phba, pasync_ctx, cri);
6733b39a
JK		 1920 return 0;
1921}
1922
1923static unsigned int
1924hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
1925 struct beiscsi_hba *phba,
1926 struct async_pdu_handle *pasync_handle)
1927{
1928 struct hwi_async_pdu_context *pasync_ctx;
1929 struct hwi_controller *phwi_ctrlr;
1930 unsigned int bytes_needed = 0, status = 0;
1931 unsigned short cri = pasync_handle->cri;
1932 struct pdu_base *ppdu;
1933
1934 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833
JK		 1935 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
1936 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
1937 BE_GET_CRI_FROM_CID(beiscsi_conn->
1938 beiscsi_conn_cid)));
6733b39a
JK		 1939
1940 list_del(&pasync_handle->link);
1941 if (pasync_handle->is_header) {
1942 pasync_ctx->async_header.busy_entries--;
1943 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
8a86e833 1944 hwi_free_async_msg(phba, pasync_ctx, cri);
6733b39a
JK		 1945 BUG();
1946 }
1947
1948 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
1949 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
1950 pasync_ctx->async_entry[cri].wait_queue.hdr_len =
1951 (unsigned short)pasync_handle->buffer_len;
1952 list_add_tail(&pasync_handle->link,
1953 &pasync_ctx->async_entry[cri].wait_queue.list);
1954
1955 ppdu = pasync_handle->pbuffer;
1956 bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
1957 data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
1958 0xFFFF0000) | ((be16_to_cpu((ppdu->
1959 dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
1960 & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
1961
1962 if (status == 0) {
1963 pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
1964 bytes_needed;
1965
1966 if (bytes_needed == 0)
1967 status = hwi_fwd_async_msg(beiscsi_conn, phba,
1968 pasync_ctx, cri);
1969 }
1970 } else {
1971 pasync_ctx->async_data.busy_entries--;
1972 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
1973 list_add_tail(&pasync_handle->link,
1974 &pasync_ctx->async_entry[cri].wait_queue.
1975 list);
1976 pasync_ctx->async_entry[cri].wait_queue.
1977 bytes_received +=
1978 (unsigned short)pasync_handle->buffer_len;
1979
1980 if (pasync_ctx->async_entry[cri].wait_queue.
1981 bytes_received >=
1982 pasync_ctx->async_entry[cri].wait_queue.
1983 bytes_needed)
1984 status = hwi_fwd_async_msg(beiscsi_conn, phba,
1985 pasync_ctx, cri);
1986 }
1987 }
1988 return status;
1989}
1990
1991static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
1992 struct beiscsi_hba *phba,
1993 struct i_t_dpdu_cqe *pdpdu_cqe)
1994{
1995 struct hwi_controller *phwi_ctrlr;
1996 struct hwi_async_pdu_context *pasync_ctx;
1997 struct async_pdu_handle *pasync_handle = NULL;
1998 unsigned int cq_index = -1;
8a86e833
JK		 1999 uint16_t cri_index = BE_GET_CRI_FROM_CID(
2000 beiscsi_conn->beiscsi_conn_cid);
6733b39a
JK		 2001
2002 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833
JK		 2003 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
2004 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
2005 cri_index));
2006
6733b39a
JK		 2007 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
2008 pdpdu_cqe, &cq_index);
2009
2010 if (pasync_handle->consumed == 0)
99bc5d55
JSJ		 2011 hwi_update_async_writables(phba, pasync_ctx,
2012 pasync_handle->is_header, cq_index);
2013
6733b39a 2014 hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
8a86e833
JK		 2015 hwi_post_async_buffers(phba, pasync_handle->is_header,
2016 BEISCSI_GET_ULP_FROM_CRI(
2017 phwi_ctrlr, cri_index));
6733b39a
JK		 2018}
2019
756d29c8
JK		 2020static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
2021{
2022 struct be_queue_info *mcc_cq;
2023 struct be_mcc_compl *mcc_compl;
2024 unsigned int num_processed = 0;
2025
2026 mcc_cq = &phba->ctrl.mcc_obj.cq;
2027 mcc_compl = queue_tail_node(mcc_cq);
2028 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
2029 while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
2030
2031 if (num_processed >= 32) {
2032 hwi_ring_cq_db(phba, mcc_cq->id,
2033 num_processed, 0, 0);
2034 num_processed = 0;
2035 }
2036 if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
2037 /* Interpret flags as an async trailer */
2038 if (is_link_state_evt(mcc_compl->flags))
2039 /* Interpret compl as a async link evt */
2040 beiscsi_async_link_state_process(phba,
2041 (struct be_async_event_link_state *) mcc_compl);
2042 else
99bc5d55
JSJ		 2043 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
2044 "BM_%d : Unsupported Async Event, flags"
2045 " = 0x%08x\n",
2046 mcc_compl->flags);
756d29c8
JK		 2047 } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
2048 be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
2049 atomic_dec(&phba->ctrl.mcc_obj.q.used);
2050 }
2051
2052 mcc_compl->flags = 0;
2053 queue_tail_inc(mcc_cq);
2054 mcc_compl = queue_tail_node(mcc_cq);
2055 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
2056 num_processed++;
2057 }
2058
2059 if (num_processed > 0)
2060 hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
2061
2062}
bfead3b2 2063
6763daae
JSJ		 2064/**
2065 * beiscsi_process_cq()- Process the Completion Queue
2066 * @pbe_eq: Event Q on which the Completion has come
2067 *
2068 * return
2069 * Number of Completion Entries processed.
2070 **/
bfead3b2 2071static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
6733b39a 2072{
6733b39a
JK		 2073 struct be_queue_info *cq;
2074 struct sol_cqe *sol;
2075 struct dmsg_cqe *dmsg;
2076 unsigned int num_processed = 0;
2077 unsigned int tot_nump = 0;
0a513dd8 2078 unsigned short code = 0, cid = 0;
a7909b39 2079 uint16_t cri_index = 0;
6733b39a 2080 struct beiscsi_conn *beiscsi_conn;
c2462288
JK		 2081 struct beiscsi_endpoint *beiscsi_ep;
2082 struct iscsi_endpoint *ep;
bfead3b2 2083 struct beiscsi_hba *phba;
6733b39a 2084
bfead3b2 2085 cq = pbe_eq->cq;
6733b39a 2086 sol = queue_tail_node(cq);
bfead3b2 2087 phba = pbe_eq->phba;
6733b39a
JK		 2088
2089 while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
2090 CQE_VALID_MASK) {
2091 be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
2092
73133261
JSJ		 2093 code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
2094 32] & CQE_CODE_MASK);
2095
2096 /* Get the CID */
2c9dfd36
JK		 2097 if (is_chip_be2_be3r(phba)) {
2098 cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol);
2099 } else {
73133261
JSJ		 2100 if ((code == DRIVERMSG_NOTIFY) ||
2101 (code == UNSOL_HDR_NOTIFY) ||
2102 (code == UNSOL_DATA_NOTIFY))
2103 cid = AMAP_GET_BITS(
2104 struct amap_i_t_dpdu_cqe_v2,
2105 cid, sol);
2106 else
2107 cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
2108 cid, sol);
2c9dfd36 2109 }
32951dd8 2110
a7909b39
JK		 2111 cri_index = BE_GET_CRI_FROM_CID(cid);
2112 ep = phba->ep_array[cri_index];
c2462288
JK		 2113 beiscsi_ep = ep->dd_data;
2114 beiscsi_conn = beiscsi_ep->conn;
756d29c8 2115
6733b39a 2116 if (num_processed >= 32) {
bfead3b2 2117 hwi_ring_cq_db(phba, cq->id,
6733b39a
JK		 2118 num_processed, 0, 0);
2119 tot_nump += num_processed;
2120 num_processed = 0;
2121 }
2122
0a513dd8 2123 switch (code) {
6733b39a
JK		 2124 case SOL_CMD_COMPLETE:
2125 hwi_complete_cmd(beiscsi_conn, phba, sol);
2126 break;
2127 case DRIVERMSG_NOTIFY:
99bc5d55
JSJ		 2128 beiscsi_log(phba, KERN_INFO,
2129 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2130 "BM_%d : Received %s[%d] on CID : %d\n",
2131 cqe_desc[code], code, cid);
99bc5d55 2132
6733b39a
JK		 2133 dmsg = (struct dmsg_cqe *)sol;
2134 hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
2135 break;
2136 case UNSOL_HDR_NOTIFY:
99bc5d55
JSJ		 2137 beiscsi_log(phba, KERN_INFO,
2138 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2139 "BM_%d : Received %s[%d] on CID : %d\n",
2140 cqe_desc[code], code, cid);
99bc5d55 2141
8f09a3b9 2142 spin_lock_bh(&phba->async_pdu_lock);
bfead3b2
JK		 2143 hwi_process_default_pdu_ring(beiscsi_conn, phba,
2144 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 2145 spin_unlock_bh(&phba->async_pdu_lock);
bfead3b2 2146 break;
6733b39a 2147 case UNSOL_DATA_NOTIFY:
99bc5d55
JSJ		 2148 beiscsi_log(phba, KERN_INFO,
2149 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
6763daae
JSJ		 2150 "BM_%d : Received %s[%d] on CID : %d\n",
2151 cqe_desc[code], code, cid);
99bc5d55 2152
8f09a3b9 2153 spin_lock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2154 hwi_process_default_pdu_ring(beiscsi_conn, phba,
2155 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 2156 spin_unlock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2157 break;
2158 case CXN_INVALIDATE_INDEX_NOTIFY:
2159 case CMD_INVALIDATED_NOTIFY:
2160 case CXN_INVALIDATE_NOTIFY:
99bc5d55
JSJ		 2161 beiscsi_log(phba, KERN_ERR,
2162 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2163 "BM_%d : Ignoring %s[%d] on CID : %d\n",
2164 cqe_desc[code], code, cid);
6733b39a
JK		 2165 break;
2166 case SOL_CMD_KILLED_DATA_DIGEST_ERR:
2167 case CMD_KILLED_INVALID_STATSN_RCVD:
2168 case CMD_KILLED_INVALID_R2T_RCVD:
2169 case CMD_CXN_KILLED_LUN_INVALID:
2170 case CMD_CXN_KILLED_ICD_INVALID:
2171 case CMD_CXN_KILLED_ITT_INVALID:
2172 case CMD_CXN_KILLED_SEQ_OUTOFORDER:
2173 case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
99bc5d55
JSJ		 2174 beiscsi_log(phba, KERN_ERR,
2175 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
6763daae
JSJ		 2176 "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
2177 cqe_desc[code], code, cid);
6733b39a
JK		 2178 break;
2179 case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
99bc5d55
JSJ		 2180 beiscsi_log(phba, KERN_ERR,
2181 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2182 "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
2183 cqe_desc[code], code, cid);
8f09a3b9 2184 spin_lock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2185 hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
2186 (struct i_t_dpdu_cqe *) sol);
8f09a3b9 2187 spin_unlock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2188 break;
2189 case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
2190 case CXN_KILLED_BURST_LEN_MISMATCH:
2191 case CXN_KILLED_AHS_RCVD:
2192 case CXN_KILLED_HDR_DIGEST_ERR:
2193 case CXN_KILLED_UNKNOWN_HDR:
2194 case CXN_KILLED_STALE_ITT_TTT_RCVD:
2195 case CXN_KILLED_INVALID_ITT_TTT_RCVD:
2196 case CXN_KILLED_TIMED_OUT:
2197 case CXN_KILLED_FIN_RCVD:
6763daae
JSJ		 2198 case CXN_KILLED_RST_SENT:
2199 case CXN_KILLED_RST_RCVD:
6733b39a
JK		 2200 case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
2201 case CXN_KILLED_BAD_WRB_INDEX_ERROR:
2202 case CXN_KILLED_OVER_RUN_RESIDUAL:
2203 case CXN_KILLED_UNDER_RUN_RESIDUAL:
2204 case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
99bc5d55
JSJ		 2205 beiscsi_log(phba, KERN_ERR,
2206 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2207 "BM_%d : Event %s[%d] received on CID : %d\n",
2208 cqe_desc[code], code, cid);
0a513dd8
JSJ		 2209 if (beiscsi_conn)
2210 iscsi_conn_failure(beiscsi_conn->conn,
2211 ISCSI_ERR_CONN_FAILED);
6733b39a
JK		 2212 break;
2213 default:
99bc5d55
JSJ		 2214 beiscsi_log(phba, KERN_ERR,
2215 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2216 "BM_%d : Invalid CQE Event Received Code : %d"
2217 "CID 0x%x...\n",
0a513dd8 2218 code, cid);
6733b39a
JK		 2219 break;
2220 }
2221
2222 AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
2223 queue_tail_inc(cq);
2224 sol = queue_tail_node(cq);
2225 num_processed++;
2226 }
2227
2228 if (num_processed > 0) {
2229 tot_nump += num_processed;
bfead3b2 2230 hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
6733b39a
JK		 2231 }
2232 return tot_nump;
2233}
2234
756d29c8 2235void beiscsi_process_all_cqs(struct work_struct *work)
6733b39a
JK		 2236{
2237 unsigned long flags;
bfead3b2
JK		 2238 struct hwi_controller *phwi_ctrlr;
2239 struct hwi_context_memory *phwi_context;
72fb46a9
JSJ		 2240 struct beiscsi_hba *phba;
2241 struct be_eq_obj *pbe_eq =
2242 container_of(work, struct be_eq_obj, work_cqs);
6733b39a 2243
72fb46a9 2244 phba = pbe_eq->phba;
bfead3b2
JK		 2245 phwi_ctrlr = phba->phwi_ctrlr;
2246 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2 2247
72fb46a9 2248 if (pbe_eq->todo_mcc_cq) {
6733b39a 2249 spin_lock_irqsave(&phba->isr_lock, flags);
72fb46a9 2250 pbe_eq->todo_mcc_cq = false;
6733b39a 2251 spin_unlock_irqrestore(&phba->isr_lock, flags);
756d29c8 2252 beiscsi_process_mcc_isr(phba);
6733b39a
JK		 2253 }
2254
72fb46a9 2255 if (pbe_eq->todo_cq) {
6733b39a 2256 spin_lock_irqsave(&phba->isr_lock, flags);
72fb46a9 2257 pbe_eq->todo_cq = false;
6733b39a 2258 spin_unlock_irqrestore(&phba->isr_lock, flags);
bfead3b2 2259 beiscsi_process_cq(pbe_eq);
6733b39a 2260 }
72fb46a9
JSJ		 2261
2262 /* rearm EQ for further interrupts */
2263 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
6733b39a
JK		 2264}
2265
2266static int be_iopoll(struct blk_iopoll *iop, int budget)
2267{
ad3f428e 2268 unsigned int ret;
6733b39a 2269 struct beiscsi_hba *phba;
bfead3b2 2270 struct be_eq_obj *pbe_eq;
6733b39a 2271
bfead3b2
JK		 2272 pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
2273 ret = beiscsi_process_cq(pbe_eq);
73af08e1 2274 pbe_eq->cq_count += ret;
6733b39a 2275 if (ret < budget) {
bfead3b2 2276 phba = pbe_eq->phba;
6733b39a 2277 blk_iopoll_complete(iop);
99bc5d55
JSJ		 2278 beiscsi_log(phba, KERN_INFO,
2279 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
2280 "BM_%d : rearm pbe_eq->q.id =%d\n",
2281 pbe_eq->q.id);
bfead3b2 2282 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
6733b39a
JK		 2283 }
2284 return ret;
2285}
2286
09a1093a
JSJ		 2287static void
2288hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg,
2289 unsigned int num_sg, struct beiscsi_io_task *io_task)
2290{
2291 struct iscsi_sge *psgl;
2292 unsigned int sg_len, index;
2293 unsigned int sge_len = 0;
2294 unsigned long long addr;
2295 struct scatterlist *l_sg;
2296 unsigned int offset;
2297
2298 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb,
2299 io_task->bhs_pa.u.a32.address_lo);
2300 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb,
2301 io_task->bhs_pa.u.a32.address_hi);
2302
2303 l_sg = sg;
2304 for (index = 0; (index < num_sg) && (index < 2); index++,
2305 sg = sg_next(sg)) {
2306 if (index == 0) {
2307 sg_len = sg_dma_len(sg);
2308 addr = (u64) sg_dma_address(sg);
2309 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2310 sge0_addr_lo, pwrb,
2311 lower_32_bits(addr));
2312 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2313 sge0_addr_hi, pwrb,
2314 upper_32_bits(addr));
2315 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2316 sge0_len, pwrb,
2317 sg_len);
2318 sge_len = sg_len;
2319 } else {
2320 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset,
2321 pwrb, sge_len);
2322 sg_len = sg_dma_len(sg);
2323 addr = (u64) sg_dma_address(sg);
2324 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2325 sge1_addr_lo, pwrb,
2326 lower_32_bits(addr));
2327 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2328 sge1_addr_hi, pwrb,
2329 upper_32_bits(addr));
2330 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2331 sge1_len, pwrb,
2332 sg_len);
2333 }
2334 }
2335 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2336 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2337
2338 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2339
2340 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2341 io_task->bhs_pa.u.a32.address_hi);
2342 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2343 io_task->bhs_pa.u.a32.address_lo);
2344
2345 if (num_sg == 1) {
2346 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2347 1);
2348 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2349 0);
2350 } else if (num_sg == 2) {
2351 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2352 0);
2353 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2354 1);
2355 } else {
2356 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2357 0);
2358 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2359 0);
2360 }
2361
2362 sg = l_sg;
2363 psgl++;
2364 psgl++;
2365 offset = 0;
2366 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
2367 sg_len = sg_dma_len(sg);
2368 addr = (u64) sg_dma_address(sg);
2369 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2370 lower_32_bits(addr));
2371 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2372 upper_32_bits(addr));
2373 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2374 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2375 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2376 offset += sg_len;
2377 }
2378 psgl--;
2379 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2380}
2381
6733b39a
JK		 2382static void
2383hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
2384 unsigned int num_sg, struct beiscsi_io_task *io_task)
2385{
2386 struct iscsi_sge *psgl;
58ff4bd0 2387 unsigned int sg_len, index;
6733b39a
JK		 2388 unsigned int sge_len = 0;
2389 unsigned long long addr;
2390 struct scatterlist *l_sg;
2391 unsigned int offset;
2392
2393 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2394 io_task->bhs_pa.u.a32.address_lo);
2395 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2396 io_task->bhs_pa.u.a32.address_hi);
2397
2398 l_sg = sg;
48bd86cf
JK		 2399 for (index = 0; (index < num_sg) && (index < 2); index++,
2400 sg = sg_next(sg)) {
6733b39a
JK		 2401 if (index == 0) {
2402 sg_len = sg_dma_len(sg);
2403 addr = (u64) sg_dma_address(sg);
2404 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
457ff3b7 2405 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2406 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
457ff3b7 2407 ((u32)(addr >> 32)));
6733b39a
JK		 2408 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2409 sg_len);
2410 sge_len = sg_len;
6733b39a 2411 } else {
6733b39a
JK		 2412 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
2413 pwrb, sge_len);
2414 sg_len = sg_dma_len(sg);
2415 addr = (u64) sg_dma_address(sg);
2416 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
457ff3b7 2417 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2418 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
457ff3b7 2419 ((u32)(addr >> 32)));
6733b39a
JK		 2420 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
2421 sg_len);
2422 }
2423 }
2424 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2425 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2426
2427 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2428
2429 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2430 io_task->bhs_pa.u.a32.address_hi);
2431 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2432 io_task->bhs_pa.u.a32.address_lo);
2433
caf818f1
JK		 2434 if (num_sg == 1) {
2435 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2436 1);
2437 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2438 0);
2439 } else if (num_sg == 2) {
2440 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2441 0);
2442 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2443 1);
2444 } else {
2445 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2446 0);
2447 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2448 0);
2449 }
6733b39a
JK		 2450 sg = l_sg;
2451 psgl++;
2452 psgl++;
2453 offset = 0;
48bd86cf 2454 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
6733b39a
JK		 2455 sg_len = sg_dma_len(sg);
2456 addr = (u64) sg_dma_address(sg);
2457 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2458 (addr & 0xFFFFFFFF));
2459 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2460 (addr >> 32));
2461 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2462 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2463 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2464 offset += sg_len;
2465 }
2466 psgl--;
2467 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2468}
2469
d629c471
JSJ		 2470/**
2471 * hwi_write_buffer()- Populate the WRB with task info
2472 * @pwrb: ptr to the WRB entry
2473 * @task: iscsi task which is to be executed
2474 **/
6733b39a
JK		 2475static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
2476{
2477 struct iscsi_sge *psgl;
6733b39a
JK		 2478 struct beiscsi_io_task *io_task = task->dd_data;
2479 struct beiscsi_conn *beiscsi_conn = io_task->conn;
2480 struct beiscsi_hba *phba = beiscsi_conn->phba;
09a1093a 2481 uint8_t dsp_value = 0;
6733b39a
JK		 2482
2483 io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
2484 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2485 io_task->bhs_pa.u.a32.address_lo);
2486 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2487 io_task->bhs_pa.u.a32.address_hi);
2488
2489 if (task->data) {
09a1093a
JSJ		 2490
2491 /* Check for the data_count */
2492 dsp_value = (task->data_count) ? 1 : 0;
2493
2c9dfd36
JK		 2494 if (is_chip_be2_be3r(phba))
2495 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp,
09a1093a
JSJ		 2496 pwrb, dsp_value);
2497 else
2c9dfd36 2498 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp,
09a1093a
JSJ		 2499 pwrb, dsp_value);
2500
2501 /* Map addr only if there is data_count */
2502 if (dsp_value) {
d629c471
JSJ		 2503 io_task->mtask_addr = pci_map_single(phba->pcidev,
2504 task->data,
2505 task->data_count,
2506 PCI_DMA_TODEVICE);
d629c471 2507 io_task->mtask_data_count = task->data_count;
09a1093a 2508 } else
d629c471 2509 io_task->mtask_addr = 0;
09a1093a 2510
6733b39a 2511 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
d629c471 2512 lower_32_bits(io_task->mtask_addr));
6733b39a 2513 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
d629c471 2514 upper_32_bits(io_task->mtask_addr));
6733b39a
JK		 2515 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2516 task->data_count);
2517
2518 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
2519 } else {
2520 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
d629c471 2521 io_task->mtask_addr = 0;
6733b39a
JK		 2522 }
2523
2524 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2525
2526 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
2527
2528 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2529 io_task->bhs_pa.u.a32.address_hi);
2530 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2531 io_task->bhs_pa.u.a32.address_lo);
2532 if (task->data) {
2533 psgl++;
2534 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
2535 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
2536 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
2537 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
2538 AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
2539 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2540
2541 psgl++;
2542 if (task->data) {
2543 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
d629c471 2544 lower_32_bits(io_task->mtask_addr));
6733b39a 2545 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
d629c471 2546 upper_32_bits(io_task->mtask_addr));
6733b39a
JK		 2547 }
2548 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
2549 }
2550 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2551}
2552
843ae752
JK		 2553/**
2554 * beiscsi_find_mem_req()- Find mem needed
2555 * @phba: ptr to HBA struct
2556 **/
6733b39a
JK		 2557static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
2558{
8a86e833 2559 uint8_t mem_descr_index, ulp_num;
bfead3b2 2560 unsigned int num_cq_pages, num_async_pdu_buf_pages;
6733b39a
JK		 2561 unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
2562 unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
2563
2564 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
2565 sizeof(struct sol_cqe));
6733b39a
JK		 2566
2567 phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
2568
2569 phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
2570 BE_ISCSI_PDU_HEADER_SIZE;
2571 phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
2572 sizeof(struct hwi_context_memory);
2573
6733b39a
JK		 2574
2575 phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
2576 * (phba->params.wrbs_per_cxn)
2577 * phba->params.cxns_per_ctrl;
2578 wrb_sz_per_cxn = sizeof(struct wrb_handle) *
2579 (phba->params.wrbs_per_cxn);
2580 phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
2581 phba->params.cxns_per_ctrl);
2582
2583 phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
2584 phba->params.icds_per_ctrl;
2585 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
2586 phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
8a86e833
JK		 2587 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
2588 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 2589
8a86e833
JK		 2590 num_async_pdu_buf_sgl_pages =
2591 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2592 phba, ulp_num) *
2593 sizeof(struct phys_addr));
2594
2595 num_async_pdu_buf_pages =
2596 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2597 phba, ulp_num) *
2598 phba->params.defpdu_hdr_sz);
2599
2600 num_async_pdu_data_pages =
2601 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2602 phba, ulp_num) *
2603 phba->params.defpdu_data_sz);
2604
2605 num_async_pdu_data_sgl_pages =
2606 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2607 phba, ulp_num) *
2608 sizeof(struct phys_addr));
2609
a129d92f
JK		 2610 mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 +
2611 (ulp_num * MEM_DESCR_OFFSET));
2612 phba->mem_req[mem_descr_index] =
2613 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2614 BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
2615
8a86e833
JK		 2616 mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
2617 (ulp_num * MEM_DESCR_OFFSET));
2618 phba->mem_req[mem_descr_index] =
2619 num_async_pdu_buf_pages *
2620 PAGE_SIZE;
2621
2622 mem_descr_index = (HWI_MEM_ASYNC_DATA_BUF_ULP0 +
2623 (ulp_num * MEM_DESCR_OFFSET));
2624 phba->mem_req[mem_descr_index] =
2625 num_async_pdu_data_pages *
2626 PAGE_SIZE;
2627
2628 mem_descr_index = (HWI_MEM_ASYNC_HEADER_RING_ULP0 +
2629 (ulp_num * MEM_DESCR_OFFSET));
2630 phba->mem_req[mem_descr_index] =
2631 num_async_pdu_buf_sgl_pages *
2632 PAGE_SIZE;
2633
2634 mem_descr_index = (HWI_MEM_ASYNC_DATA_RING_ULP0 +
2635 (ulp_num * MEM_DESCR_OFFSET));
2636 phba->mem_req[mem_descr_index] =
2637 num_async_pdu_data_sgl_pages *
2638 PAGE_SIZE;
2639
2640 mem_descr_index = (HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
2641 (ulp_num * MEM_DESCR_OFFSET));
2642 phba->mem_req[mem_descr_index] =
2643 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2644 sizeof(struct async_pdu_handle);
2645
2646 mem_descr_index = (HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
2647 (ulp_num * MEM_DESCR_OFFSET));
2648 phba->mem_req[mem_descr_index] =
2649 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2650 sizeof(struct async_pdu_handle);
2651
2652 mem_descr_index = (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
2653 (ulp_num * MEM_DESCR_OFFSET));
2654 phba->mem_req[mem_descr_index] =
2655 sizeof(struct hwi_async_pdu_context) +
2656 (BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2657 sizeof(struct hwi_async_entry));
2658 }
2659 }
6733b39a
JK		 2660}
2661
2662static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
2663{
6733b39a 2664 dma_addr_t bus_add;
a7909b39
JK		 2665 struct hwi_controller *phwi_ctrlr;
2666 struct be_mem_descriptor *mem_descr;
6733b39a
JK		 2667 struct mem_array *mem_arr, *mem_arr_orig;
2668 unsigned int i, j, alloc_size, curr_alloc_size;
2669
3ec78271 2670 phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
6733b39a
JK		 2671 if (!phba->phwi_ctrlr)
2672 return -ENOMEM;
2673
a7909b39
JK		 2674 /* Allocate memory for wrb_context */
2675 phwi_ctrlr = phba->phwi_ctrlr;
2676 phwi_ctrlr->wrb_context = kzalloc(sizeof(struct hwi_wrb_context) *
2677 phba->params.cxns_per_ctrl,
2678 GFP_KERNEL);
2679 if (!phwi_ctrlr->wrb_context)
2680 return -ENOMEM;
2681
6733b39a
JK		 2682 phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
2683 GFP_KERNEL);
2684 if (!phba->init_mem) {
a7909b39 2685 kfree(phwi_ctrlr->wrb_context);
6733b39a
JK		 2686 kfree(phba->phwi_ctrlr);
2687 return -ENOMEM;
2688 }
2689
2690 mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
2691 GFP_KERNEL);
2692 if (!mem_arr_orig) {
2693 kfree(phba->init_mem);
a7909b39 2694 kfree(phwi_ctrlr->wrb_context);
6733b39a
JK		 2695 kfree(phba->phwi_ctrlr);
2696 return -ENOMEM;
2697 }
2698
2699 mem_descr = phba->init_mem;
2700 for (i = 0; i < SE_MEM_MAX; i++) {
8a86e833
JK		 2701 if (!phba->mem_req[i]) {
2702 mem_descr->mem_array = NULL;
2703 mem_descr++;
2704 continue;
2705 }
2706
6733b39a
JK		 2707 j = 0;
2708 mem_arr = mem_arr_orig;
2709 alloc_size = phba->mem_req[i];
2710 memset(mem_arr, 0, sizeof(struct mem_array) *
2711 BEISCSI_MAX_FRAGS_INIT);
2712 curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
2713 do {
2714 mem_arr->virtual_address = pci_alloc_consistent(
2715 phba->pcidev,
2716 curr_alloc_size,
2717 &bus_add);
2718 if (!mem_arr->virtual_address) {
2719 if (curr_alloc_size <= BE_MIN_MEM_SIZE)
2720 goto free_mem;
2721 if (curr_alloc_size -
2722 rounddown_pow_of_two(curr_alloc_size))
2723 curr_alloc_size = rounddown_pow_of_two
2724 (curr_alloc_size);
2725 else
2726 curr_alloc_size = curr_alloc_size / 2;
2727 } else {
2728 mem_arr->bus_address.u.
2729 a64.address = (__u64) bus_add;
2730 mem_arr->size = curr_alloc_size;
2731 alloc_size -= curr_alloc_size;
2732 curr_alloc_size = min(be_max_phys_size *
2733 1024, alloc_size);
2734 j++;
2735 mem_arr++;
2736 }
2737 } while (alloc_size);
2738 mem_descr->num_elements = j;
2739 mem_descr->size_in_bytes = phba->mem_req[i];
2740 mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
2741 GFP_KERNEL);
2742 if (!mem_descr->mem_array)
2743 goto free_mem;
2744
2745 memcpy(mem_descr->mem_array, mem_arr_orig,
2746 sizeof(struct mem_array) * j);
2747 mem_descr++;
2748 }
2749 kfree(mem_arr_orig);
2750 return 0;
2751free_mem:
2752 mem_descr->num_elements = j;
2753 while ((i) || (j)) {
2754 for (j = mem_descr->num_elements; j > 0; j--) {
2755 pci_free_consistent(phba->pcidev,
2756 mem_descr->mem_array[j - 1].size,
2757 mem_descr->mem_array[j - 1].
2758 virtual_address,
457ff3b7
JK		 2759 (unsigned long)mem_descr->
2760 mem_array[j - 1].
6733b39a
JK		 2761 bus_address.u.a64.address);
2762 }
2763 if (i) {
2764 i--;
2765 kfree(mem_descr->mem_array);
2766 mem_descr--;
2767 }
2768 }
2769 kfree(mem_arr_orig);
2770 kfree(phba->init_mem);
a7909b39 2771 kfree(phba->phwi_ctrlr->wrb_context);
6733b39a
JK		 2772 kfree(phba->phwi_ctrlr);
2773 return -ENOMEM;
2774}
2775
2776static int beiscsi_get_memory(struct beiscsi_hba *phba)
2777{
2778 beiscsi_find_mem_req(phba);
2779 return beiscsi_alloc_mem(phba);
2780}
2781
2782static void iscsi_init_global_templates(struct beiscsi_hba *phba)
2783{
2784 struct pdu_data_out *pdata_out;
2785 struct pdu_nop_out *pnop_out;
2786 struct be_mem_descriptor *mem_descr;
2787
2788 mem_descr = phba->init_mem;
2789 mem_descr += ISCSI_MEM_GLOBAL_HEADER;
2790 pdata_out =
2791 (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
2792 memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2793
2794 AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
2795 IIOC_SCSI_DATA);
2796
2797 pnop_out =
2798 (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
2799 virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
2800
2801 memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2802 AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
2803 AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
2804 AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
2805}
2806
3ec78271 2807static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
6733b39a
JK		 2808{
2809 struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
a7909b39 2810 struct hwi_context_memory *phwi_ctxt;
3ec78271 2811 struct wrb_handle *pwrb_handle = NULL;
6733b39a
JK		 2812 struct hwi_controller *phwi_ctrlr;
2813 struct hwi_wrb_context *pwrb_context;
3ec78271
JK		 2814 struct iscsi_wrb *pwrb = NULL;
2815 unsigned int num_cxn_wrbh = 0;
2816 unsigned int num_cxn_wrb = 0, j, idx = 0, index;
6733b39a
JK		 2817
2818 mem_descr_wrbh = phba->init_mem;
2819 mem_descr_wrbh += HWI_MEM_WRBH;
2820
2821 mem_descr_wrb = phba->init_mem;
2822 mem_descr_wrb += HWI_MEM_WRB;
6733b39a
JK		 2823 phwi_ctrlr = phba->phwi_ctrlr;
2824
a7909b39
JK		 2825 /* Allocate memory for WRBQ */
2826 phwi_ctxt = phwi_ctrlr->phwi_ctxt;
2827 phwi_ctxt->be_wrbq = kzalloc(sizeof(struct be_queue_info) *
843ae752 2828 phba->params.cxns_per_ctrl,
a7909b39
JK		 2829 GFP_KERNEL);
2830 if (!phwi_ctxt->be_wrbq) {
2831 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2832 "BM_%d : WRBQ Mem Alloc Failed\n");
2833 return -ENOMEM;
2834 }
2835
2836 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a 2837 pwrb_context = &phwi_ctrlr->wrb_context[index];
6733b39a
JK		 2838 pwrb_context->pwrb_handle_base =
2839 kzalloc(sizeof(struct wrb_handle *) *
2840 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271 2841 if (!pwrb_context->pwrb_handle_base) {
99bc5d55
JSJ		 2842 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2843 "BM_%d : Mem Alloc Failed. Failing to load\n");
3ec78271
JK		 2844 goto init_wrb_hndl_failed;
2845 }
6733b39a
JK		 2846 pwrb_context->pwrb_handle_basestd =
2847 kzalloc(sizeof(struct wrb_handle *) *
2848 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271 2849 if (!pwrb_context->pwrb_handle_basestd) {
99bc5d55
JSJ		 2850 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2851 "BM_%d : Mem Alloc Failed. Failing to load\n");
3ec78271
JK		 2852 goto init_wrb_hndl_failed;
2853 }
2854 if (!num_cxn_wrbh) {
2855 pwrb_handle =
2856 mem_descr_wrbh->mem_array[idx].virtual_address;
2857 num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
2858 ((sizeof(struct wrb_handle)) *
2859 phba->params.wrbs_per_cxn));
2860 idx++;
2861 }
2862 pwrb_context->alloc_index = 0;
2863 pwrb_context->wrb_handles_available = 0;
2864 pwrb_context->free_index = 0;
2865
6733b39a 2866 if (num_cxn_wrbh) {
6733b39a
JK		 2867 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2868 pwrb_context->pwrb_handle_base[j] = pwrb_handle;
2869 pwrb_context->pwrb_handle_basestd[j] =
2870 pwrb_handle;
2871 pwrb_context->wrb_handles_available++;
bfead3b2 2872 pwrb_handle->wrb_index = j;
6733b39a
JK		 2873 pwrb_handle++;
2874 }
6733b39a
JK		 2875 num_cxn_wrbh--;
2876 }
2877 }
2878 idx = 0;
a7909b39 2879 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a 2880 pwrb_context = &phwi_ctrlr->wrb_context[index];
3ec78271 2881 if (!num_cxn_wrb) {
6733b39a 2882 pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
7c56533c 2883 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
3ec78271
JK		 2884 ((sizeof(struct iscsi_wrb) *
2885 phba->params.wrbs_per_cxn));
2886 idx++;
2887 }
2888
2889 if (num_cxn_wrb) {
6733b39a
JK		 2890 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2891 pwrb_handle = pwrb_context->pwrb_handle_base[j];
2892 pwrb_handle->pwrb = pwrb;
2893 pwrb++;
2894 }
2895 num_cxn_wrb--;
2896 }
2897 }
3ec78271
JK		 2898 return 0;
2899init_wrb_hndl_failed:
2900 for (j = index; j > 0; j--) {
2901 pwrb_context = &phwi_ctrlr->wrb_context[j];
2902 kfree(pwrb_context->pwrb_handle_base);
2903 kfree(pwrb_context->pwrb_handle_basestd);
2904 }
2905 return -ENOMEM;
6733b39a
JK		 2906}
2907
a7909b39 2908static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
6733b39a 2909{
8a86e833 2910 uint8_t ulp_num;
6733b39a
JK		 2911 struct hwi_controller *phwi_ctrlr;
2912 struct hba_parameters *p = &phba->params;
2913 struct hwi_async_pdu_context *pasync_ctx;
2914 struct async_pdu_handle *pasync_header_h, *pasync_data_h;
dc63aac6 2915 unsigned int index, idx, num_per_mem, num_async_data;
6733b39a
JK		 2916 struct be_mem_descriptor *mem_descr;
2917
8a86e833
JK		 2918 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
2919 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 2920
8a86e833
JK		 2921 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2922 mem_descr += (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
2923 (ulp_num * MEM_DESCR_OFFSET));
2924
2925 phwi_ctrlr = phba->phwi_ctrlr;
2926 phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num] =
2927 (struct hwi_async_pdu_context *)
2928 mem_descr->mem_array[0].virtual_address;
2929
2930 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
2931 memset(pasync_ctx, 0, sizeof(*pasync_ctx));
2932
2933 pasync_ctx->async_entry =
2934 (struct hwi_async_entry *)
2935 ((long unsigned int)pasync_ctx +
2936 sizeof(struct hwi_async_pdu_context));
2937
2938 pasync_ctx->num_entries = BEISCSI_GET_CID_COUNT(phba,
2939 ulp_num);
2940 pasync_ctx->buffer_size = p->defpdu_hdr_sz;
2941
2942 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2943 mem_descr += HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
2944 (ulp_num * MEM_DESCR_OFFSET);
2945 if (mem_descr->mem_array[0].virtual_address) {
2946 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2947 "BM_%d : hwi_init_async_pdu_ctx"
2948 " HWI_MEM_ASYNC_HEADER_BUF_ULP%d va=%p\n",
2949 ulp_num,
2950 mem_descr->mem_array[0].
2951 virtual_address);
2952 } else
2953 beiscsi_log(phba, KERN_WARNING,
2954 BEISCSI_LOG_INIT,
2955 "BM_%d : No Virtual address for ULP : %d\n",
2956 ulp_num);
2957
2958 pasync_ctx->async_header.va_base =
6733b39a 2959 mem_descr->mem_array[0].virtual_address;
6733b39a 2960
8a86e833
JK		 2961 pasync_ctx->async_header.pa_base.u.a64.address =
2962 mem_descr->mem_array[0].
2963 bus_address.u.a64.address;
6733b39a 2964
8a86e833
JK		 2965 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2966 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
2967 (ulp_num * MEM_DESCR_OFFSET);
2968 if (mem_descr->mem_array[0].virtual_address) {
2969 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2970 "BM_%d : hwi_init_async_pdu_ctx"
2971 " HWI_MEM_ASYNC_HEADER_RING_ULP%d va=%p\n",
2972 ulp_num,
2973 mem_descr->mem_array[0].
2974 virtual_address);
2975 } else
2976 beiscsi_log(phba, KERN_WARNING,
2977 BEISCSI_LOG_INIT,
2978 "BM_%d : No Virtual address for ULP : %d\n",
2979 ulp_num);
2980
2981 pasync_ctx->async_header.ring_base =
2982 mem_descr->mem_array[0].virtual_address;
6733b39a 2983
8a86e833
JK		 2984 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2985 mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
2986 (ulp_num * MEM_DESCR_OFFSET);
2987 if (mem_descr->mem_array[0].virtual_address) {
2988 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2989 "BM_%d : hwi_init_async_pdu_ctx"
2990 " HWI_MEM_ASYNC_HEADER_HANDLE_ULP%d va=%p\n",
2991 ulp_num,
2992 mem_descr->mem_array[0].
2993 virtual_address);
2994 } else
2995 beiscsi_log(phba, KERN_WARNING,
2996 BEISCSI_LOG_INIT,
2997 "BM_%d : No Virtual address for ULP : %d\n",
2998 ulp_num);
2999
3000 pasync_ctx->async_header.handle_base =
3001 mem_descr->mem_array[0].virtual_address;
3002 pasync_ctx->async_header.writables = 0;
3003 INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
3004
3005 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3006 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
3007 (ulp_num * MEM_DESCR_OFFSET);
3008 if (mem_descr->mem_array[0].virtual_address) {
3009 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3010 "BM_%d : hwi_init_async_pdu_ctx"
3011 " HWI_MEM_ASYNC_DATA_RING_ULP%d va=%p\n",
3012 ulp_num,
3013 mem_descr->mem_array[0].
3014 virtual_address);
3015 } else
3016 beiscsi_log(phba, KERN_WARNING,
3017 BEISCSI_LOG_INIT,
3018 "BM_%d : No Virtual address for ULP : %d\n",
3019 ulp_num);
3020
3021 pasync_ctx->async_data.ring_base =
3022 mem_descr->mem_array[0].virtual_address;
6733b39a 3023
8a86e833
JK		 3024 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3025 mem_descr += HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
3026 (ulp_num * MEM_DESCR_OFFSET);
3027 if (!mem_descr->mem_array[0].virtual_address)
3028 beiscsi_log(phba, KERN_WARNING,
3029 BEISCSI_LOG_INIT,
3030 "BM_%d : No Virtual address for ULP : %d\n",
3031 ulp_num);
99bc5d55 3032
8a86e833
JK		 3033 pasync_ctx->async_data.handle_base =
3034 mem_descr->mem_array[0].virtual_address;
3035 pasync_ctx->async_data.writables = 0;
3036 INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
3037
3038 pasync_header_h =
3039 (struct async_pdu_handle *)
3040 pasync_ctx->async_header.handle_base;
3041 pasync_data_h =
3042 (struct async_pdu_handle *)
3043 pasync_ctx->async_data.handle_base;
3044
3045 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3046 mem_descr += HWI_MEM_ASYNC_DATA_BUF_ULP0 +
3047 (ulp_num * MEM_DESCR_OFFSET);
3048 if (mem_descr->mem_array[0].virtual_address) {
3049 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3050 "BM_%d : hwi_init_async_pdu_ctx"
3051 " HWI_MEM_ASYNC_DATA_BUF_ULP%d va=%p\n",
3052 ulp_num,
3053 mem_descr->mem_array[0].
3054 virtual_address);
3055 } else
3056 beiscsi_log(phba, KERN_WARNING,
3057 BEISCSI_LOG_INIT,
3058 "BM_%d : No Virtual address for ULP : %d\n",
3059 ulp_num);
3060
3061 idx = 0;
dc63aac6
JK		 3062 pasync_ctx->async_data.va_base =
3063 mem_descr->mem_array[idx].virtual_address;
3064 pasync_ctx->async_data.pa_base.u.a64.address =
3065 mem_descr->mem_array[idx].
3066 bus_address.u.a64.address;
3067
3068 num_async_data = ((mem_descr->mem_array[idx].size) /
3069 phba->params.defpdu_data_sz);
8a86e833 3070 num_per_mem = 0;
6733b39a 3071
8a86e833
JK		 3072 for (index = 0; index < BEISCSI_GET_CID_COUNT
3073 (phba, ulp_num); index++) {
3074 pasync_header_h->cri = -1;
3075 pasync_header_h->index = (char)index;
3076 INIT_LIST_HEAD(&pasync_header_h->link);
3077 pasync_header_h->pbuffer =
3078 (void *)((unsigned long)
3079 (pasync_ctx->
3080 async_header.va_base) +
3081 (p->defpdu_hdr_sz * index));
3082
3083 pasync_header_h->pa.u.a64.address =
3084 pasync_ctx->async_header.pa_base.u.a64.
3085 address + (p->defpdu_hdr_sz * index);
3086
3087 list_add_tail(&pasync_header_h->link,
3088 &pasync_ctx->async_header.
3089 free_list);
3090 pasync_header_h++;
3091 pasync_ctx->async_header.free_entries++;
3092 pasync_ctx->async_header.writables++;
3093
3094 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
3095 wait_queue.list);
3096 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
3097 header_busy_list);
3098 pasync_data_h->cri = -1;
3099 pasync_data_h->index = (char)index;
3100 INIT_LIST_HEAD(&pasync_data_h->link);
3101
3102 if (!num_async_data) {
3103 num_per_mem = 0;
3104 idx++;
3105 pasync_ctx->async_data.va_base =
3106 mem_descr->mem_array[idx].
3107 virtual_address;
3108 pasync_ctx->async_data.pa_base.u.
3109 a64.address =
3110 mem_descr->mem_array[idx].
3111 bus_address.u.a64.address;
3112 num_async_data =
3113 ((mem_descr->mem_array[idx].
3114 size) /
3115 phba->params.defpdu_data_sz);
3116 }
3117 pasync_data_h->pbuffer =
3118 (void *)((unsigned long)
3119 (pasync_ctx->async_data.va_base) +
3120 (p->defpdu_data_sz * num_per_mem));
3121
3122 pasync_data_h->pa.u.a64.address =
3123 pasync_ctx->async_data.pa_base.u.a64.
3124 address + (p->defpdu_data_sz *
3125 num_per_mem);
3126 num_per_mem++;
3127 num_async_data--;
3128
3129 list_add_tail(&pasync_data_h->link,
3130 &pasync_ctx->async_data.
3131 free_list);
3132 pasync_data_h++;
3133 pasync_ctx->async_data.free_entries++;
3134 pasync_ctx->async_data.writables++;
3135
3136 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
3137 data_busy_list);
3138 }
6733b39a 3139
8a86e833
JK		 3140 pasync_ctx->async_header.host_write_ptr = 0;
3141 pasync_ctx->async_header.ep_read_ptr = -1;
3142 pasync_ctx->async_data.host_write_ptr = 0;
3143 pasync_ctx->async_data.ep_read_ptr = -1;
3144 }
6733b39a
JK		 3145 }
3146
a7909b39 3147 return 0;
6733b39a
JK		 3148}
3149
3150static int
3151be_sgl_create_contiguous(void *virtual_address,
3152 u64 physical_address, u32 length,
3153 struct be_dma_mem *sgl)
3154{
3155 WARN_ON(!virtual_address);
3156 WARN_ON(!physical_address);
3157 WARN_ON(!length > 0);
3158 WARN_ON(!sgl);
3159
3160 sgl->va = virtual_address;
457ff3b7 3161 sgl->dma = (unsigned long)physical_address;
6733b39a
JK		 3162 sgl->size = length;
3163
3164 return 0;
3165}
3166
3167static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
3168{
3169 memset(sgl, 0, sizeof(*sgl));
3170}
3171
3172static void
3173hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
3174 struct mem_array *pmem, struct be_dma_mem *sgl)
3175{
3176 if (sgl->va)
3177 be_sgl_destroy_contiguous(sgl);
3178
3179 be_sgl_create_contiguous(pmem->virtual_address,
3180 pmem->bus_address.u.a64.address,
3181 pmem->size, sgl);
3182}
3183
3184static void
3185hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
3186 struct mem_array *pmem, struct be_dma_mem *sgl)
3187{
3188 if (sgl->va)
3189 be_sgl_destroy_contiguous(sgl);
3190
3191 be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
3192 pmem->bus_address.u.a64.address,
3193 pmem->size, sgl);
3194}
3195
3196static int be_fill_queue(struct be_queue_info *q,
3197 u16 len, u16 entry_size, void *vaddress)
3198{
3199 struct be_dma_mem *mem = &q->dma_mem;
3200
3201 memset(q, 0, sizeof(*q));
3202 q->len = len;
3203 q->entry_size = entry_size;
3204 mem->size = len * entry_size;
3205 mem->va = vaddress;
3206 if (!mem->va)
3207 return -ENOMEM;
3208 memset(mem->va, 0, mem->size);
3209 return 0;
3210}
3211
bfead3b2 3212static int beiscsi_create_eqs(struct beiscsi_hba *phba,
6733b39a
JK		 3213 struct hwi_context_memory *phwi_context)
3214{
bfead3b2 3215 unsigned int i, num_eq_pages;
99bc5d55 3216 int ret = 0, eq_for_mcc;
6733b39a
JK		 3217 struct be_queue_info *eq;
3218 struct be_dma_mem *mem;
6733b39a 3219 void *eq_vaddress;
bfead3b2 3220 dma_addr_t paddr;
6733b39a 3221
bfead3b2
JK		 3222 num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
3223 sizeof(struct be_eq_entry));
6733b39a 3224
bfead3b2
JK		 3225 if (phba->msix_enabled)
3226 eq_for_mcc = 1;
3227 else
3228 eq_for_mcc = 0;
3229 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
3230 eq = &phwi_context->be_eq[i].q;
3231 mem = &eq->dma_mem;
3232 phwi_context->be_eq[i].phba = phba;
3233 eq_vaddress = pci_alloc_consistent(phba->pcidev,
3234 num_eq_pages * PAGE_SIZE,
3235 &paddr);
3236 if (!eq_vaddress)
3237 goto create_eq_error;
3238
3239 mem->va = eq_vaddress;
3240 ret = be_fill_queue(eq, phba->params.num_eq_entries,
3241 sizeof(struct be_eq_entry), eq_vaddress);
3242 if (ret) {
99bc5d55
JSJ		 3243 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3244 "BM_%d : be_fill_queue Failed for EQ\n");
bfead3b2
JK		 3245 goto create_eq_error;
3246 }
6733b39a 3247
bfead3b2
JK		 3248 mem->dma = paddr;
3249 ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
3250 phwi_context->cur_eqd);
3251 if (ret) {
99bc5d55
JSJ		 3252 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3253 "BM_%d : beiscsi_cmd_eq_create"
3254 "Failed for EQ\n");
bfead3b2
JK		 3255 goto create_eq_error;
3256 }
99bc5d55
JSJ		 3257
3258 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3259 "BM_%d : eqid = %d\n",
3260 phwi_context->be_eq[i].q.id);
6733b39a 3261 }
6733b39a 3262 return 0;
bfead3b2 3263create_eq_error:
107dfcba 3264 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
bfead3b2
JK		 3265 eq = &phwi_context->be_eq[i].q;
3266 mem = &eq->dma_mem;
3267 if (mem->va)
3268 pci_free_consistent(phba->pcidev, num_eq_pages
3269 * PAGE_SIZE,
3270 mem->va, mem->dma);
3271 }
3272 return ret;
6733b39a
JK		 3273}
3274
bfead3b2 3275static int beiscsi_create_cqs(struct beiscsi_hba *phba,
6733b39a
JK		 3276 struct hwi_context_memory *phwi_context)
3277{
bfead3b2 3278 unsigned int i, num_cq_pages;
99bc5d55 3279 int ret = 0;
6733b39a
JK		 3280 struct be_queue_info *cq, *eq;
3281 struct be_dma_mem *mem;
bfead3b2 3282 struct be_eq_obj *pbe_eq;
6733b39a 3283 void *cq_vaddress;
bfead3b2 3284 dma_addr_t paddr;
6733b39a 3285
bfead3b2
JK		 3286 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
3287 sizeof(struct sol_cqe));
6733b39a 3288
bfead3b2
JK		 3289 for (i = 0; i < phba->num_cpus; i++) {
3290 cq = &phwi_context->be_cq[i];
3291 eq = &phwi_context->be_eq[i].q;
3292 pbe_eq = &phwi_context->be_eq[i];
3293 pbe_eq->cq = cq;
3294 pbe_eq->phba = phba;
3295 mem = &cq->dma_mem;
3296 cq_vaddress = pci_alloc_consistent(phba->pcidev,
3297 num_cq_pages * PAGE_SIZE,
3298 &paddr);
3299 if (!cq_vaddress)
3300 goto create_cq_error;
7da50879 3301 ret = be_fill_queue(cq, phba->params.num_cq_entries,
bfead3b2
JK		 3302 sizeof(struct sol_cqe), cq_vaddress);
3303 if (ret) {
99bc5d55
JSJ		 3304 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3305 "BM_%d : be_fill_queue Failed "
3306 "for ISCSI CQ\n");
bfead3b2
JK		 3307 goto create_cq_error;
3308 }
3309
3310 mem->dma = paddr;
3311 ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
3312 false, 0);
3313 if (ret) {
99bc5d55
JSJ		 3314 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3315 "BM_%d : beiscsi_cmd_eq_create"
3316 "Failed for ISCSI CQ\n");
bfead3b2
JK		 3317 goto create_cq_error;
3318 }
99bc5d55
JSJ		 3319 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3320 "BM_%d : iscsi cq_id is %d for eq_id %d\n"
3321 "iSCSI CQ CREATED\n", cq->id, eq->id);
6733b39a 3322 }
6733b39a 3323 return 0;
bfead3b2
JK		 3324
3325create_cq_error:
3326 for (i = 0; i < phba->num_cpus; i++) {
3327 cq = &phwi_context->be_cq[i];
3328 mem = &cq->dma_mem;
3329 if (mem->va)
3330 pci_free_consistent(phba->pcidev, num_cq_pages
3331 * PAGE_SIZE,
3332 mem->va, mem->dma);
3333 }
3334 return ret;
3335
6733b39a
JK		 3336}
3337
3338static int
3339beiscsi_create_def_hdr(struct beiscsi_hba *phba,
3340 struct hwi_context_memory *phwi_context,
3341 struct hwi_controller *phwi_ctrlr,
8a86e833 3342 unsigned int def_pdu_ring_sz, uint8_t ulp_num)
6733b39a
JK		 3343{
3344 unsigned int idx;
3345 int ret;
3346 struct be_queue_info *dq, *cq;
3347 struct be_dma_mem *mem;
3348 struct be_mem_descriptor *mem_descr;
3349 void *dq_vaddress;
3350
3351 idx = 0;
8a86e833 3352 dq = &phwi_context->be_def_hdrq[ulp_num];
bfead3b2 3353 cq = &phwi_context->be_cq[0];
6733b39a
JK		 3354 mem = &dq->dma_mem;
3355 mem_descr = phba->init_mem;
8a86e833
JK		 3356 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
3357 (ulp_num * MEM_DESCR_OFFSET);
6733b39a
JK		 3358 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
3359 ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
3360 sizeof(struct phys_addr),
3361 sizeof(struct phys_addr), dq_vaddress);
3362 if (ret) {
99bc5d55 3363 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3364 "BM_%d : be_fill_queue Failed for DEF PDU HDR on ULP : %d\n",
3365 ulp_num);
3366
6733b39a
JK		 3367 return ret;
3368 }
457ff3b7
JK		 3369 mem->dma = (unsigned long)mem_descr->mem_array[idx].
3370 bus_address.u.a64.address;
6733b39a
JK		 3371 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
3372 def_pdu_ring_sz,
8a86e833
JK		 3373 phba->params.defpdu_hdr_sz,
3374 BEISCSI_DEFQ_HDR, ulp_num);
6733b39a 3375 if (ret) {
99bc5d55 3376 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3377 "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR on ULP : %d\n",
3378 ulp_num);
3379
6733b39a
JK		 3380 return ret;
3381 }
99bc5d55 3382
8a86e833
JK		 3383 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3384 "BM_%d : iscsi hdr def pdu id for ULP : %d is %d\n",
3385 ulp_num,
3386 phwi_context->be_def_hdrq[ulp_num].id);
3387 hwi_post_async_buffers(phba, BEISCSI_DEFQ_HDR, ulp_num);
6733b39a
JK		 3388 return 0;
3389}
3390
3391static int
3392beiscsi_create_def_data(struct beiscsi_hba *phba,
3393 struct hwi_context_memory *phwi_context,
3394 struct hwi_controller *phwi_ctrlr,
8a86e833 3395 unsigned int def_pdu_ring_sz, uint8_t ulp_num)
6733b39a
JK		 3396{
3397 unsigned int idx;
3398 int ret;
3399 struct be_queue_info *dataq, *cq;
3400 struct be_dma_mem *mem;
3401 struct be_mem_descriptor *mem_descr;
3402 void *dq_vaddress;
3403
3404 idx = 0;
8a86e833 3405 dataq = &phwi_context->be_def_dataq[ulp_num];
bfead3b2 3406 cq = &phwi_context->be_cq[0];
6733b39a
JK		 3407 mem = &dataq->dma_mem;
3408 mem_descr = phba->init_mem;
8a86e833
JK		 3409 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
3410 (ulp_num * MEM_DESCR_OFFSET);
6733b39a
JK		 3411 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
3412 ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
3413 sizeof(struct phys_addr),
3414 sizeof(struct phys_addr), dq_vaddress);
3415 if (ret) {
99bc5d55 3416 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3417 "BM_%d : be_fill_queue Failed for DEF PDU "
3418 "DATA on ULP : %d\n",
3419 ulp_num);
3420
6733b39a
JK		 3421 return ret;
3422 }
457ff3b7
JK		 3423 mem->dma = (unsigned long)mem_descr->mem_array[idx].
3424 bus_address.u.a64.address;
6733b39a
JK		 3425 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
3426 def_pdu_ring_sz,
8a86e833
JK		 3427 phba->params.defpdu_data_sz,
3428 BEISCSI_DEFQ_DATA, ulp_num);
6733b39a 3429 if (ret) {
99bc5d55
JSJ		 3430 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3431 "BM_%d be_cmd_create_default_pdu_queue"
8a86e833
JK		 3432 " Failed for DEF PDU DATA on ULP : %d\n",
3433 ulp_num);
6733b39a
JK		 3434 return ret;
3435 }
8a86e833 3436
99bc5d55 3437 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
8a86e833
JK		 3438 "BM_%d : iscsi def data id on ULP : %d is %d\n",
3439 ulp_num,
3440 phwi_context->be_def_dataq[ulp_num].id);
99bc5d55 3441
8a86e833 3442 hwi_post_async_buffers(phba, BEISCSI_DEFQ_DATA, ulp_num);
99bc5d55 3443 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
8a86e833
JK		 3444 "BM_%d : DEFAULT PDU DATA RING CREATED"
3445 "on ULP : %d\n", ulp_num);
99bc5d55 3446
6733b39a
JK		 3447 return 0;
3448}
3449
15a90fe0
JK		 3450
3451static int
3452beiscsi_post_template_hdr(struct beiscsi_hba *phba)
3453{
3454 struct be_mem_descriptor *mem_descr;
3455 struct mem_array *pm_arr;
3456 struct be_dma_mem sgl;
a129d92f 3457 int status, ulp_num;
15a90fe0 3458
a129d92f
JK		 3459 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3460 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3461 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3462 mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 +
3463 (ulp_num * MEM_DESCR_OFFSET);
3464 pm_arr = mem_descr->mem_array;
15a90fe0 3465
a129d92f
JK		 3466 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
3467 status = be_cmd_iscsi_post_template_hdr(
3468 &phba->ctrl, &sgl);
15a90fe0 3469
a129d92f
JK		 3470 if (status != 0) {
3471 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3472 "BM_%d : Post Template HDR Failed for"
3473 "ULP_%d\n", ulp_num);
3474 return status;
3475 }
3476
3477 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3478 "BM_%d : Template HDR Pages Posted for"
3479 "ULP_%d\n", ulp_num);
15a90fe0
JK		 3480 }
3481 }
15a90fe0
JK		 3482 return 0;
3483}
3484
6733b39a
JK		 3485static int
3486beiscsi_post_pages(struct beiscsi_hba *phba)
3487{
3488 struct be_mem_descriptor *mem_descr;
3489 struct mem_array *pm_arr;
3490 unsigned int page_offset, i;
3491 struct be_dma_mem sgl;
843ae752 3492 int status, ulp_num = 0;
6733b39a
JK		 3493
3494 mem_descr = phba->init_mem;
3495 mem_descr += HWI_MEM_SGE;
3496 pm_arr = mem_descr->mem_array;
3497
90622db3
JK		 3498 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3499 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
3500 break;
3501
6733b39a 3502 page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
843ae752 3503 phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE;
6733b39a
JK		 3504 for (i = 0; i < mem_descr->num_elements; i++) {
3505 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
3506 status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
3507 page_offset,
3508 (pm_arr->size / PAGE_SIZE));
3509 page_offset += pm_arr->size / PAGE_SIZE;
3510 if (status != 0) {
99bc5d55
JSJ		 3511 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3512 "BM_%d : post sgl failed.\n");
6733b39a
JK		 3513 return status;
3514 }
3515 pm_arr++;
3516 }
99bc5d55
JSJ		 3517 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3518 "BM_%d : POSTED PAGES\n");
6733b39a
JK		 3519 return 0;
3520}
3521
bfead3b2
JK		 3522static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
3523{
3524 struct be_dma_mem *mem = &q->dma_mem;
c8b25598 3525 if (mem->va) {
bfead3b2
JK		 3526 pci_free_consistent(phba->pcidev, mem->size,
3527 mem->va, mem->dma);
c8b25598
JK		 3528 mem->va = NULL;
3529 }
bfead3b2
JK		 3530}
3531
3532static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
3533 u16 len, u16 entry_size)
3534{
3535 struct be_dma_mem *mem = &q->dma_mem;
3536
3537 memset(q, 0, sizeof(*q));
3538 q->len = len;
3539 q->entry_size = entry_size;
3540 mem->size = len * entry_size;
3541 mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
3542 if (!mem->va)
d3ad2bb3 3543 return -ENOMEM;
bfead3b2
JK		 3544 memset(mem->va, 0, mem->size);
3545 return 0;
3546}
3547
6733b39a
JK		 3548static int
3549beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
3550 struct hwi_context_memory *phwi_context,
3551 struct hwi_controller *phwi_ctrlr)
3552{
3553 unsigned int wrb_mem_index, offset, size, num_wrb_rings;
3554 u64 pa_addr_lo;
4eea99d5 3555 unsigned int idx, num, i, ulp_num;
6733b39a
JK		 3556 struct mem_array *pwrb_arr;
3557 void *wrb_vaddr;
3558 struct be_dma_mem sgl;
3559 struct be_mem_descriptor *mem_descr;
a7909b39 3560 struct hwi_wrb_context *pwrb_context;
6733b39a 3561 int status;
4eea99d5
JK		 3562 uint8_t ulp_count = 0, ulp_base_num = 0;
3563 uint16_t cid_count_ulp[BEISCSI_ULP_COUNT] = { 0 };
6733b39a
JK		 3564
3565 idx = 0;
3566 mem_descr = phba->init_mem;
3567 mem_descr += HWI_MEM_WRB;
3568 pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
3569 GFP_KERNEL);
3570 if (!pwrb_arr) {
99bc5d55
JSJ		 3571 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3572 "BM_%d : Memory alloc failed in create wrb ring.\n");
6733b39a
JK		 3573 return -ENOMEM;
3574 }
3575 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
3576 pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
3577 num_wrb_rings = mem_descr->mem_array[idx].size /
3578 (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
3579
3580 for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
3581 if (num_wrb_rings) {
3582 pwrb_arr[num].virtual_address = wrb_vaddr;
3583 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
3584 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
3585 sizeof(struct iscsi_wrb);
3586 wrb_vaddr += pwrb_arr[num].size;
3587 pa_addr_lo += pwrb_arr[num].size;
3588 num_wrb_rings--;
3589 } else {
3590 idx++;
3591 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
3592 pa_addr_lo = mem_descr->mem_array[idx].\
3593 bus_address.u.a64.address;
3594 num_wrb_rings = mem_descr->mem_array[idx].size /
3595 (phba->params.wrbs_per_cxn *
3596 sizeof(struct iscsi_wrb));
3597 pwrb_arr[num].virtual_address = wrb_vaddr;
3598 pwrb_arr[num].bus_address.u.a64.address\
3599 = pa_addr_lo;
3600 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
3601 sizeof(struct iscsi_wrb);
3602 wrb_vaddr += pwrb_arr[num].size;
3603 pa_addr_lo += pwrb_arr[num].size;
3604 num_wrb_rings--;
3605 }
3606 }
4eea99d5
JK		 3607
3608 /* Get the ULP Count */
3609 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3610 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3611 ulp_count++;
3612 ulp_base_num = ulp_num;
3613 cid_count_ulp[ulp_num] =
3614 BEISCSI_GET_CID_COUNT(phba, ulp_num);
3615 }
3616
6733b39a
JK		 3617 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3618 wrb_mem_index = 0;
3619 offset = 0;
3620 size = 0;
3621
4eea99d5
JK		 3622 if (ulp_count > 1) {
3623 ulp_base_num = (ulp_base_num + 1) % BEISCSI_ULP_COUNT;
3624
3625 if (!cid_count_ulp[ulp_base_num])
3626 ulp_base_num = (ulp_base_num + 1) %
3627 BEISCSI_ULP_COUNT;
3628
3629 cid_count_ulp[ulp_base_num]--;
3630 }
3631
3632
6733b39a
JK		 3633 hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
3634 status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
4eea99d5
JK		 3635 &phwi_context->be_wrbq[i],
3636 &phwi_ctrlr->wrb_context[i],
3637 ulp_base_num);
6733b39a 3638 if (status != 0) {
99bc5d55
JSJ		 3639 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3640 "BM_%d : wrbq create failed.");
1462b8ff 3641 kfree(pwrb_arr);
6733b39a
JK		 3642 return status;
3643 }
a7909b39 3644 pwrb_context = &phwi_ctrlr->wrb_context[i];
a7909b39 3645 BE_SET_CID_TO_CRI(i, pwrb_context->cid);
6733b39a
JK		 3646 }
3647 kfree(pwrb_arr);
3648 return 0;
3649}
3650
3651static void free_wrb_handles(struct beiscsi_hba *phba)
3652{
3653 unsigned int index;
3654 struct hwi_controller *phwi_ctrlr;
3655 struct hwi_wrb_context *pwrb_context;
3656
3657 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 3658 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a
JK		 3659 pwrb_context = &phwi_ctrlr->wrb_context[index];
3660 kfree(pwrb_context->pwrb_handle_base);
3661 kfree(pwrb_context->pwrb_handle_basestd);
3662 }
3663}
3664
bfead3b2
JK		 3665static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
3666{
3667 struct be_queue_info *q;
3668 struct be_ctrl_info *ctrl = &phba->ctrl;
3669
3670 q = &phba->ctrl.mcc_obj.q;
3671 if (q->created)
3672 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
3673 be_queue_free(phba, q);
3674
3675 q = &phba->ctrl.mcc_obj.cq;
3676 if (q->created)
3677 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
3678 be_queue_free(phba, q);
3679}
3680
6733b39a
JK		 3681static void hwi_cleanup(struct beiscsi_hba *phba)
3682{
3683 struct be_queue_info *q;
3684 struct be_ctrl_info *ctrl = &phba->ctrl;
3685 struct hwi_controller *phwi_ctrlr;
3686 struct hwi_context_memory *phwi_context;
a7909b39 3687 struct hwi_async_pdu_context *pasync_ctx;
8a86e833 3688 int i, eq_num, ulp_num;
6733b39a
JK		 3689
3690 phwi_ctrlr = phba->phwi_ctrlr;
3691 phwi_context = phwi_ctrlr->phwi_ctxt;
15a90fe0
JK		 3692
3693 be_cmd_iscsi_remove_template_hdr(ctrl);
3694
6733b39a
JK		 3695 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3696 q = &phwi_context->be_wrbq[i];
3697 if (q->created)
3698 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
3699 }
a7909b39 3700 kfree(phwi_context->be_wrbq);
6733b39a
JK		 3701 free_wrb_handles(phba);
3702
8a86e833
JK		 3703 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3704 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 3705
8a86e833
JK		 3706 q = &phwi_context->be_def_hdrq[ulp_num];
3707 if (q->created)
3708 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3709
3710 q = &phwi_context->be_def_dataq[ulp_num];
3711 if (q->created)
3712 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3713
3714 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
3715 }
3716 }
6733b39a
JK		 3717
3718 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
3719
bfead3b2
JK		 3720 for (i = 0; i < (phba->num_cpus); i++) {
3721 q = &phwi_context->be_cq[i];
3722 if (q->created)
3723 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
3724 }
3725 if (phba->msix_enabled)
3726 eq_num = 1;
3727 else
3728 eq_num = 0;
3729 for (i = 0; i < (phba->num_cpus + eq_num); i++) {
3730 q = &phwi_context->be_eq[i].q;
3731 if (q->created)
3732 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
3733 }
3734 be_mcc_queues_destroy(phba);
0283fbb1 3735 be_cmd_fw_uninit(ctrl);
bfead3b2 3736}
6733b39a 3737
bfead3b2
JK		 3738static int be_mcc_queues_create(struct beiscsi_hba *phba,
3739 struct hwi_context_memory *phwi_context)
3740{
3741 struct be_queue_info *q, *cq;
3742 struct be_ctrl_info *ctrl = &phba->ctrl;
3743
3744 /* Alloc MCC compl queue */
3745 cq = &phba->ctrl.mcc_obj.cq;
3746 if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
3747 sizeof(struct be_mcc_compl)))
3748 goto err;
3749 /* Ask BE to create MCC compl queue; */
3750 if (phba->msix_enabled) {
3751 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
3752 [phba->num_cpus].q, false, true, 0))
3753 goto mcc_cq_free;
3754 } else {
3755 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
3756 false, true, 0))
3757 goto mcc_cq_free;
3758 }
3759
3760 /* Alloc MCC queue */
3761 q = &phba->ctrl.mcc_obj.q;
3762 if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
3763 goto mcc_cq_destroy;
3764
3765 /* Ask BE to create MCC queue */
35e66019 3766 if (beiscsi_cmd_mccq_create(phba, q, cq))
bfead3b2
JK		 3767 goto mcc_q_free;
3768
3769 return 0;
3770
3771mcc_q_free:
3772 be_queue_free(phba, q);
3773mcc_cq_destroy:
3774 beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
3775mcc_cq_free:
3776 be_queue_free(phba, cq);
3777err:
d3ad2bb3 3778 return -ENOMEM;
bfead3b2
JK		 3779}
3780
107dfcba
JSJ		 3781/**
3782 * find_num_cpus()- Get the CPU online count
3783 * @phba: ptr to priv structure
3784 *
3785 * CPU count is used for creating EQ.
3786 **/
3787static void find_num_cpus(struct beiscsi_hba *phba)
bfead3b2
JK		 3788{
3789 int num_cpus = 0;
3790
3791 num_cpus = num_online_cpus();
bfead3b2 3792
22abeef0
JSJ		 3793 switch (phba->generation) {
3794 case BE_GEN2:
3795 case BE_GEN3:
3796 phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
3797 BEISCSI_MAX_NUM_CPUS : num_cpus;
3798 break;
3799 case BE_GEN4:
68c26a3a
JK		 3800 /*
3801 * If eqid_count == 1 fall back to
3802 * INTX mechanism
3803 **/
3804 if (phba->fw_config.eqid_count == 1) {
3805 enable_msix = 0;
3806 phba->num_cpus = 1;
3807 return;
3808 }
3809
3810 phba->num_cpus =
3811 (num_cpus > (phba->fw_config.eqid_count - 1)) ?
3812 (phba->fw_config.eqid_count - 1) : num_cpus;
22abeef0
JSJ		 3813 break;
3814 default:
3815 phba->num_cpus = 1;
3816 }
6733b39a
JK		 3817}
3818
3819static int hwi_init_port(struct beiscsi_hba *phba)
3820{
3821 struct hwi_controller *phwi_ctrlr;
3822 struct hwi_context_memory *phwi_context;
3823 unsigned int def_pdu_ring_sz;
3824 struct be_ctrl_info *ctrl = &phba->ctrl;
8a86e833 3825 int status, ulp_num;
6733b39a 3826
6733b39a 3827 phwi_ctrlr = phba->phwi_ctrlr;
6733b39a 3828 phwi_context = phwi_ctrlr->phwi_ctxt;
73af08e1 3829 phwi_context->max_eqd = 128;
bfead3b2 3830 phwi_context->min_eqd = 0;
73af08e1 3831 phwi_context->cur_eqd = 0;
6733b39a 3832 be_cmd_fw_initialize(&phba->ctrl);
bfead3b2
JK		 3833
3834 status = beiscsi_create_eqs(phba, phwi_context);
6733b39a 3835 if (status != 0) {
99bc5d55
JSJ		 3836 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3837 "BM_%d : EQ not created\n");
6733b39a
JK		 3838 goto error;
3839 }
3840
bfead3b2
JK		 3841 status = be_mcc_queues_create(phba, phwi_context);
3842 if (status != 0)
3843 goto error;
3844
3845 status = mgmt_check_supported_fw(ctrl, phba);
6733b39a 3846 if (status != 0) {
99bc5d55
JSJ		 3847 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3848 "BM_%d : Unsupported fw version\n");
6733b39a
JK		 3849 goto error;
3850 }
3851
bfead3b2 3852 status = beiscsi_create_cqs(phba, phwi_context);
6733b39a 3853 if (status != 0) {
99bc5d55
JSJ		 3854 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3855 "BM_%d : CQ not created\n");
6733b39a
JK		 3856 goto error;
3857 }
3858
8a86e833
JK		 3859 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3860 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 3861
8a86e833
JK		 3862 def_pdu_ring_sz =
3863 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
3864 sizeof(struct phys_addr);
3865
3866 status = beiscsi_create_def_hdr(phba, phwi_context,
3867 phwi_ctrlr,
3868 def_pdu_ring_sz,
3869 ulp_num);
3870 if (status != 0) {
3871 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3872 "BM_%d : Default Header not created for ULP : %d\n",
3873 ulp_num);
3874 goto error;
3875 }
3876
3877 status = beiscsi_create_def_data(phba, phwi_context,
3878 phwi_ctrlr,
3879 def_pdu_ring_sz,
3880 ulp_num);
3881 if (status != 0) {
3882 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3883 "BM_%d : Default Data not created for ULP : %d\n",
3884 ulp_num);
3885 goto error;
3886 }
3887 }
6733b39a
JK		 3888 }
3889
3890 status = beiscsi_post_pages(phba);
3891 if (status != 0) {
99bc5d55
JSJ		 3892 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3893 "BM_%d : Post SGL Pages Failed\n");
6733b39a
JK		 3894 goto error;
3895 }
3896
15a90fe0
JK		 3897 status = beiscsi_post_template_hdr(phba);
3898 if (status != 0) {
3899 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3900 "BM_%d : Template HDR Posting for CXN Failed\n");
3901 }
3902
6733b39a
JK		 3903 status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
3904 if (status != 0) {
99bc5d55
JSJ		 3905 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3906 "BM_%d : WRB Rings not created\n");
6733b39a
JK		 3907 goto error;
3908 }
3909
8a86e833
JK		 3910 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3911 uint16_t async_arr_idx = 0;
3912
3913 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3914 uint16_t cri = 0;
3915 struct hwi_async_pdu_context *pasync_ctx;
3916
3917 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(
3918 phwi_ctrlr, ulp_num);
3919 for (cri = 0; cri <
3920 phba->params.cxns_per_ctrl; cri++) {
3921 if (ulp_num == BEISCSI_GET_ULP_FROM_CRI
3922 (phwi_ctrlr, cri))
3923 pasync_ctx->cid_to_async_cri_map[
3924 phwi_ctrlr->wrb_context[cri].cid] =
3925 async_arr_idx++;
3926 }
3927 }
3928 }
3929
99bc5d55
JSJ		 3930 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3931 "BM_%d : hwi_init_port success\n");
6733b39a
JK		 3932 return 0;
3933
3934error:
99bc5d55
JSJ		 3935 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3936 "BM_%d : hwi_init_port failed");
6733b39a 3937 hwi_cleanup(phba);
a49e06d5 3938 return status;
6733b39a
JK		 3939}
3940
6733b39a
JK		 3941static int hwi_init_controller(struct beiscsi_hba *phba)
3942{
3943 struct hwi_controller *phwi_ctrlr;
3944
3945 phwi_ctrlr = phba->phwi_ctrlr;
3946 if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
3947 phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
3948 init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
99bc5d55
JSJ		 3949 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3950 "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
3951 phwi_ctrlr->phwi_ctxt);
6733b39a 3952 } else {
99bc5d55
JSJ		 3953 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3954 "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
3955 "than one element.Failing to load\n");
6733b39a
JK		 3956 return -ENOMEM;
3957 }
3958
3959 iscsi_init_global_templates(phba);
3ec78271
JK		 3960 if (beiscsi_init_wrb_handle(phba))
3961 return -ENOMEM;
3962
a7909b39
JK		 3963 if (hwi_init_async_pdu_ctx(phba)) {
3964 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3965 "BM_%d : hwi_init_async_pdu_ctx failed\n");
3966 return -ENOMEM;
3967 }
3968
6733b39a 3969 if (hwi_init_port(phba) != 0) {
99bc5d55
JSJ		 3970 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3971 "BM_%d : hwi_init_controller failed\n");
3972
6733b39a
JK		 3973 return -ENOMEM;
3974 }
3975 return 0;
3976}
3977
3978static void beiscsi_free_mem(struct beiscsi_hba *phba)
3979{
3980 struct be_mem_descriptor *mem_descr;
3981 int i, j;
3982
3983 mem_descr = phba->init_mem;
3984 i = 0;
3985 j = 0;
3986 for (i = 0; i < SE_MEM_MAX; i++) {
3987 for (j = mem_descr->num_elements; j > 0; j--) {
3988 pci_free_consistent(phba->pcidev,
3989 mem_descr->mem_array[j - 1].size,
3990 mem_descr->mem_array[j - 1].virtual_address,
457ff3b7
JK		 3991 (unsigned long)mem_descr->mem_array[j - 1].
3992 bus_address.u.a64.address);
6733b39a 3993 }
8a86e833 3994
6733b39a
JK		 3995 kfree(mem_descr->mem_array);
3996 mem_descr++;
3997 }
3998 kfree(phba->init_mem);
a7909b39 3999 kfree(phba->phwi_ctrlr->wrb_context);
6733b39a
JK		 4000 kfree(phba->phwi_ctrlr);
4001}
4002
4003static int beiscsi_init_controller(struct beiscsi_hba *phba)
4004{
4005 int ret = -ENOMEM;
4006
4007 ret = beiscsi_get_memory(phba);
4008 if (ret < 0) {
99bc5d55
JSJ		 4009 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4010 "BM_%d : beiscsi_dev_probe -"
4011 "Failed in beiscsi_alloc_memory\n");
6733b39a
JK		 4012 return ret;
4013 }
4014
4015 ret = hwi_init_controller(phba);
4016 if (ret)
4017 goto free_init;
99bc5d55
JSJ		 4018 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4019 "BM_%d : Return success from beiscsi_init_controller");
4020
6733b39a
JK		 4021 return 0;
4022
4023free_init:
4024 beiscsi_free_mem(phba);
a49e06d5 4025 return ret;
6733b39a
JK		 4026}
4027
4028static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
4029{
4030 struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
4031 struct sgl_handle *psgl_handle;
4032 struct iscsi_sge *pfrag;
90622db3
JK		 4033 unsigned int arr_index, i, idx;
4034 unsigned int ulp_icd_start, ulp_num = 0;
6733b39a
JK		 4035
4036 phba->io_sgl_hndl_avbl = 0;
4037 phba->eh_sgl_hndl_avbl = 0;
bfead3b2 4038
6733b39a
JK		 4039 mem_descr_sglh = phba->init_mem;
4040 mem_descr_sglh += HWI_MEM_SGLH;
4041 if (1 == mem_descr_sglh->num_elements) {
4042 phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
4043 phba->params.ios_per_ctrl,
4044 GFP_KERNEL);
4045 if (!phba->io_sgl_hndl_base) {
99bc5d55
JSJ		 4046 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4047 "BM_%d : Mem Alloc Failed. Failing to load\n");
6733b39a
JK		 4048 return -ENOMEM;
4049 }
4050 phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
4051 (phba->params.icds_per_ctrl -
4052 phba->params.ios_per_ctrl),
4053 GFP_KERNEL);
4054 if (!phba->eh_sgl_hndl_base) {
4055 kfree(phba->io_sgl_hndl_base);
99bc5d55
JSJ		 4056 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4057 "BM_%d : Mem Alloc Failed. Failing to load\n");
6733b39a
JK		 4058 return -ENOMEM;
4059 }
4060 } else {
99bc5d55
JSJ		 4061 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4062 "BM_%d : HWI_MEM_SGLH is more than one element."
4063 "Failing to load\n");
6733b39a
JK		 4064 return -ENOMEM;
4065 }
4066
4067 arr_index = 0;
4068 idx = 0;
4069 while (idx < mem_descr_sglh->num_elements) {
4070 psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
4071
4072 for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
4073 sizeof(struct sgl_handle)); i++) {
4074 if (arr_index < phba->params.ios_per_ctrl) {
4075 phba->io_sgl_hndl_base[arr_index] = psgl_handle;
4076 phba->io_sgl_hndl_avbl++;
4077 arr_index++;
4078 } else {
4079 phba->eh_sgl_hndl_base[arr_index -
4080 phba->params.ios_per_ctrl] =
4081 psgl_handle;
4082 arr_index++;
4083 phba->eh_sgl_hndl_avbl++;
4084 }
4085 psgl_handle++;
4086 }
4087 idx++;
4088 }
99bc5d55
JSJ		 4089 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4090 "BM_%d : phba->io_sgl_hndl_avbl=%d"
4091 "phba->eh_sgl_hndl_avbl=%d\n",
4092 phba->io_sgl_hndl_avbl,
4093 phba->eh_sgl_hndl_avbl);
4094
6733b39a
JK		 4095 mem_descr_sg = phba->init_mem;
4096 mem_descr_sg += HWI_MEM_SGE;
99bc5d55
JSJ		 4097 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4098 "\n BM_%d : mem_descr_sg->num_elements=%d\n",
4099 mem_descr_sg->num_elements);
4100
90622db3
JK		 4101 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
4102 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
4103 break;
4104
4105 ulp_icd_start = phba->fw_config.iscsi_icd_start[ulp_num];
4106
6733b39a
JK		 4107 arr_index = 0;
4108 idx = 0;
4109 while (idx < mem_descr_sg->num_elements) {
4110 pfrag = mem_descr_sg->mem_array[idx].virtual_address;
4111
4112 for (i = 0;
4113 i < (mem_descr_sg->mem_array[idx].size) /
4114 (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
4115 i++) {
4116 if (arr_index < phba->params.ios_per_ctrl)
4117 psgl_handle = phba->io_sgl_hndl_base[arr_index];
4118 else
4119 psgl_handle = phba->eh_sgl_hndl_base[arr_index -
4120 phba->params.ios_per_ctrl];
4121 psgl_handle->pfrag = pfrag;
4122 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
4123 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
4124 pfrag += phba->params.num_sge_per_io;
90622db3 4125 psgl_handle->sgl_index = ulp_icd_start + arr_index++;
6733b39a
JK		 4126 }
4127 idx++;
4128 }
4129 phba->io_sgl_free_index = 0;
4130 phba->io_sgl_alloc_index = 0;
4131 phba->eh_sgl_free_index = 0;
4132 phba->eh_sgl_alloc_index = 0;
4133 return 0;
4134}
4135
4136static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
4137{
0a3db7c0
JK		 4138 int ret;
4139 uint16_t i, ulp_num;
4140 struct ulp_cid_info *ptr_cid_info = NULL;
6733b39a 4141
0a3db7c0
JK		 4142 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4143 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4144 ptr_cid_info = kzalloc(sizeof(struct ulp_cid_info),
4145 GFP_KERNEL);
4146
4147 if (!ptr_cid_info) {
4148 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4149 "BM_%d : Failed to allocate memory"
4150 "for ULP_CID_INFO for ULP : %d\n",
4151 ulp_num);
4152 ret = -ENOMEM;
4153 goto free_memory;
4154
4155 }
4156
4157 /* Allocate memory for CID array */
4158 ptr_cid_info->cid_array = kzalloc(sizeof(void *) *
4159 BEISCSI_GET_CID_COUNT(phba,
4160 ulp_num), GFP_KERNEL);
4161 if (!ptr_cid_info->cid_array) {
4162 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4163 "BM_%d : Failed to allocate memory"
4164 "for CID_ARRAY for ULP : %d\n",
4165 ulp_num);
4166 kfree(ptr_cid_info);
4167 ptr_cid_info = NULL;
4168 ret = -ENOMEM;
4169
4170 goto free_memory;
4171 }
4172 ptr_cid_info->avlbl_cids = BEISCSI_GET_CID_COUNT(
4173 phba, ulp_num);
4174
4175 /* Save the cid_info_array ptr */
4176 phba->cid_array_info[ulp_num] = ptr_cid_info;
4177 }
6733b39a 4178 }
c2462288 4179 phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
a7909b39 4180 phba->params.cxns_per_ctrl, GFP_KERNEL);
6733b39a 4181 if (!phba->ep_array) {
99bc5d55
JSJ		 4182 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4183 "BM_%d : Failed to allocate memory in "
4184 "hba_setup_cid_tbls\n");
0a3db7c0
JK		 4185 ret = -ENOMEM;
4186
4187 goto free_memory;
6733b39a 4188 }
a7909b39
JK		 4189
4190 phba->conn_table = kzalloc(sizeof(struct beiscsi_conn *) *
4191 phba->params.cxns_per_ctrl, GFP_KERNEL);
4192 if (!phba->conn_table) {
4193 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4194 "BM_%d : Failed to allocate memory in"
4195 "hba_setup_cid_tbls\n");
4196
a7909b39 4197 kfree(phba->ep_array);
a7909b39 4198 phba->ep_array = NULL;
0a3db7c0 4199 ret = -ENOMEM;
6733b39a 4200 }
a7909b39 4201
0a3db7c0
JK		 4202 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
4203 ulp_num = phba->phwi_ctrlr->wrb_context[i].ulp_num;
4204
4205 ptr_cid_info = phba->cid_array_info[ulp_num];
4206 ptr_cid_info->cid_array[ptr_cid_info->cid_alloc++] =
4207 phba->phwi_ctrlr->wrb_context[i].cid;
4208
4209 }
4210
4211 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4212 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4213 ptr_cid_info = phba->cid_array_info[ulp_num];
a7909b39 4214
0a3db7c0
JK		 4215 ptr_cid_info->cid_alloc = 0;
4216 ptr_cid_info->cid_free = 0;
4217 }
4218 }
6733b39a 4219 return 0;
0a3db7c0
JK		 4220
4221free_memory:
4222 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4223 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4224 ptr_cid_info = phba->cid_array_info[ulp_num];
4225
4226 if (ptr_cid_info) {
4227 kfree(ptr_cid_info->cid_array);
4228 kfree(ptr_cid_info);
4229 phba->cid_array_info[ulp_num] = NULL;
4230 }
4231 }
4232 }
4233
4234 return ret;
6733b39a
JK		 4235}
4236
238f6b72 4237static void hwi_enable_intr(struct beiscsi_hba *phba)
6733b39a
JK		 4238{
4239 struct be_ctrl_info *ctrl = &phba->ctrl;
4240 struct hwi_controller *phwi_ctrlr;
4241 struct hwi_context_memory *phwi_context;
4242 struct be_queue_info *eq;
4243 u8 __iomem *addr;
bfead3b2 4244 u32 reg, i;
6733b39a
JK		 4245 u32 enabled;
4246
4247 phwi_ctrlr = phba->phwi_ctrlr;
4248 phwi_context = phwi_ctrlr->phwi_ctxt;
4249
6733b39a
JK		 4250 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
4251 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
4252 reg = ioread32(addr);
6733b39a
JK		 4253
4254 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4255 if (!enabled) {
4256 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
99bc5d55
JSJ		 4257 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4258 "BM_%d : reg =x%08x addr=%p\n", reg, addr);
6733b39a 4259 iowrite32(reg, addr);
665d6d94
JK		 4260 }
4261
4262 if (!phba->msix_enabled) {
4263 eq = &phwi_context->be_eq[0].q;
99bc5d55
JSJ		 4264 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4265 "BM_%d : eq->id=%d\n", eq->id);
4266
665d6d94
JK		 4267 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
4268 } else {
4269 for (i = 0; i <= phba->num_cpus; i++) {
4270 eq = &phwi_context->be_eq[i].q;
99bc5d55
JSJ		 4271 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4272 "BM_%d : eq->id=%d\n", eq->id);
bfead3b2
JK		 4273 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
4274 }
c03af1ae 4275 }
6733b39a
JK		 4276}
4277
4278static void hwi_disable_intr(struct beiscsi_hba *phba)
4279{
4280 struct be_ctrl_info *ctrl = &phba->ctrl;
4281
4282 u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
4283 u32 reg = ioread32(addr);
4284
4285 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4286 if (enabled) {
4287 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4288 iowrite32(reg, addr);
4289 } else
99bc5d55
JSJ		 4290 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
4291 "BM_%d : In hwi_disable_intr, Already Disabled\n");
6733b39a
JK		 4292}
4293
9aef4200
JSJ		 4294/**
4295 * beiscsi_get_boot_info()- Get the boot session info
4296 * @phba: The device priv structure instance
4297 *
4298 * Get the boot target info and store in driver priv structure
4299 *
4300 * return values
4301 * Success: 0
4302 * Failure: Non-Zero Value
4303 **/
c7acc5b8
JK		 4304static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
4305{
0e43895e 4306 struct be_cmd_get_session_resp *session_resp;
c7acc5b8 4307 struct be_dma_mem nonemb_cmd;
e175defe 4308 unsigned int tag;
9aef4200 4309 unsigned int s_handle;
f457a46f 4310 int ret = -ENOMEM;
c7acc5b8 4311
9aef4200
JSJ		 4312 /* Get the session handle of the boot target */
4313 ret = be_mgmt_get_boot_shandle(phba, &s_handle);
4314 if (ret) {
99bc5d55
JSJ		 4315 beiscsi_log(phba, KERN_ERR,
4316 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
4317 "BM_%d : No boot session\n");
9aef4200 4318 return ret;
c7acc5b8 4319 }
c7acc5b8
JK		 4320 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
4321 sizeof(*session_resp),
4322 &nonemb_cmd.dma);
4323 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 4324 beiscsi_log(phba, KERN_ERR,
4325 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
4326 "BM_%d : Failed to allocate memory for"
4327 "beiscsi_get_session_info\n");
4328
c7acc5b8
JK		 4329 return -ENOMEM;
4330 }
4331
4332 memset(nonemb_cmd.va, 0, sizeof(*session_resp));
9aef4200 4333 tag = mgmt_get_session_info(phba, s_handle,
0e43895e 4334 &nonemb_cmd);
c7acc5b8 4335 if (!tag) {
99bc5d55
JSJ		 4336 beiscsi_log(phba, KERN_ERR,
4337 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
4338 "BM_%d : beiscsi_get_session_info"
4339 " Failed\n");
4340
c7acc5b8 4341 goto boot_freemem;
e175defe 4342 }
c7acc5b8 4343
1957aa7f 4344 ret = beiscsi_mccq_compl(phba, tag, NULL, &nonemb_cmd);
e175defe 4345 if (ret) {
99bc5d55
JSJ		 4346 beiscsi_log(phba, KERN_ERR,
4347 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
e175defe 4348 "BM_%d : beiscsi_get_session_info Failed");
1957aa7f
JK		 4349
4350 if (ret != -EBUSY)
4351 goto boot_freemem;
4352 else
4353 return ret;
c7acc5b8 4354 }
e175defe 4355
c7acc5b8 4356 session_resp = nonemb_cmd.va ;
f457a46f 4357
c7acc5b8
JK		 4358 memcpy(&phba->boot_sess, &session_resp->session_info,
4359 sizeof(struct mgmt_session_info));
f457a46f
MC		 4360 ret = 0;
4361
c7acc5b8
JK		 4362boot_freemem:
4363 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
4364 nonemb_cmd.va, nonemb_cmd.dma);
f457a46f
MC		 4365 return ret;
4366}
4367
4368static void beiscsi_boot_release(void *data)
4369{
4370 struct beiscsi_hba *phba = data;
4371
4372 scsi_host_put(phba->shost);
4373}
4374
4375static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
4376{
4377 struct iscsi_boot_kobj *boot_kobj;
4378
4379 /* get boot info using mgmt cmd */
4380 if (beiscsi_get_boot_info(phba))
4381 /* Try to see if we can carry on without this */
4382 return 0;
4383
4384 phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
4385 if (!phba->boot_kset)
4386 return -ENOMEM;
4387
4388 /* get a ref because the show function will ref the phba */
4389 if (!scsi_host_get(phba->shost))
4390 goto free_kset;
4391 boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
4392 beiscsi_show_boot_tgt_info,
4393 beiscsi_tgt_get_attr_visibility,
4394 beiscsi_boot_release);
4395 if (!boot_kobj)
4396 goto put_shost;
4397
4398 if (!scsi_host_get(phba->shost))
4399 goto free_kset;
4400 boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
4401 beiscsi_show_boot_ini_info,
4402 beiscsi_ini_get_attr_visibility,
4403 beiscsi_boot_release);
4404 if (!boot_kobj)
4405 goto put_shost;
4406
4407 if (!scsi_host_get(phba->shost))
4408 goto free_kset;
4409 boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
4410 beiscsi_show_boot_eth_info,
4411 beiscsi_eth_get_attr_visibility,
4412 beiscsi_boot_release);
4413 if (!boot_kobj)
4414 goto put_shost;
4415 return 0;
4416
4417put_shost:
4418 scsi_host_put(phba->shost);
4419free_kset:
4420 iscsi_boot_destroy_kset(phba->boot_kset);
c7acc5b8
JK		 4421 return -ENOMEM;
4422}
4423
6733b39a
JK		 4424static int beiscsi_init_port(struct beiscsi_hba *phba)
4425{
4426 int ret;
4427
4428 ret = beiscsi_init_controller(phba);
4429 if (ret < 0) {
99bc5d55
JSJ		 4430 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4431 "BM_%d : beiscsi_dev_probe - Failed in"
4432 "beiscsi_init_controller\n");
6733b39a
JK		 4433 return ret;
4434 }
4435 ret = beiscsi_init_sgl_handle(phba);
4436 if (ret < 0) {
99bc5d55
JSJ		 4437 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4438 "BM_%d : beiscsi_dev_probe - Failed in"
4439 "beiscsi_init_sgl_handle\n");
6733b39a
JK		 4440 goto do_cleanup_ctrlr;
4441 }
4442
4443 if (hba_setup_cid_tbls(phba)) {
99bc5d55
JSJ		 4444 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4445 "BM_%d : Failed in hba_setup_cid_tbls\n");
6733b39a
JK		 4446 kfree(phba->io_sgl_hndl_base);
4447 kfree(phba->eh_sgl_hndl_base);
4448 goto do_cleanup_ctrlr;
4449 }
4450
4451 return ret;
4452
4453do_cleanup_ctrlr:
4454 hwi_cleanup(phba);
4455 return ret;
4456}
4457
4458static void hwi_purge_eq(struct beiscsi_hba *phba)
4459{
4460 struct hwi_controller *phwi_ctrlr;
4461 struct hwi_context_memory *phwi_context;
4462 struct be_queue_info *eq;
4463 struct be_eq_entry *eqe = NULL;
bfead3b2 4464 int i, eq_msix;
756d29c8 4465 unsigned int num_processed;
6733b39a
JK		 4466
4467 phwi_ctrlr = phba->phwi_ctrlr;
4468 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 4469 if (phba->msix_enabled)
4470 eq_msix = 1;
4471 else
4472 eq_msix = 0;
6733b39a 4473
bfead3b2
JK		 4474 for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
4475 eq = &phwi_context->be_eq[i].q;
6733b39a 4476 eqe = queue_tail_node(eq);
756d29c8 4477 num_processed = 0;
bfead3b2
JK		 4478 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
4479 & EQE_VALID_MASK) {
4480 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
4481 queue_tail_inc(eq);
4482 eqe = queue_tail_node(eq);
756d29c8 4483 num_processed++;
bfead3b2 4484 }
756d29c8
JK		 4485
4486 if (num_processed)
4487 hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
6733b39a
JK		 4488 }
4489}
4490
4491static void beiscsi_clean_port(struct beiscsi_hba *phba)
4492{
0a3db7c0
JK		 4493 int mgmt_status, ulp_num;
4494 struct ulp_cid_info *ptr_cid_info = NULL;
6733b39a 4495
bd41c2bd
JK		 4496 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4497 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4498 mgmt_status = mgmt_epfw_cleanup(phba, ulp_num);
4499 if (mgmt_status)
4500 beiscsi_log(phba, KERN_WARNING,
4501 BEISCSI_LOG_INIT,
4502 "BM_%d : mgmt_epfw_cleanup FAILED"
4503 " for ULP_%d\n", ulp_num);
4504 }
4505 }
756d29c8 4506
6733b39a 4507 hwi_purge_eq(phba);
756d29c8 4508 hwi_cleanup(phba);
6733b39a
JK		 4509 kfree(phba->io_sgl_hndl_base);
4510 kfree(phba->eh_sgl_hndl_base);
6733b39a 4511 kfree(phba->ep_array);
a7909b39 4512 kfree(phba->conn_table);
0a3db7c0
JK		 4513
4514 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4515 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4516 ptr_cid_info = phba->cid_array_info[ulp_num];
4517
4518 if (ptr_cid_info) {
4519 kfree(ptr_cid_info->cid_array);
4520 kfree(ptr_cid_info);
4521 phba->cid_array_info[ulp_num] = NULL;
4522 }
4523 }
4524 }
4525
6733b39a
JK		 4526}
4527
43f388b0
JK		 4528/**
4529 * beiscsi_free_mgmt_task_handles()- Free driver CXN resources
4530 * @beiscsi_conn: ptr to the conn to be cleaned up
4a4a11b9 4531 * @task: ptr to iscsi_task resource to be freed.
43f388b0
JK		 4532 *
4533 * Free driver mgmt resources binded to CXN.
4534 **/
4535void
4a4a11b9
JK		 4536beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
4537 struct iscsi_task *task)
43f388b0
JK		 4538{
4539 struct beiscsi_io_task *io_task;
4540 struct beiscsi_hba *phba = beiscsi_conn->phba;
4541 struct hwi_wrb_context *pwrb_context;
4542 struct hwi_controller *phwi_ctrlr;
a7909b39
JK		 4543 uint16_t cri_index = BE_GET_CRI_FROM_CID(
4544 beiscsi_conn->beiscsi_conn_cid);
43f388b0
JK		 4545
4546 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39
JK		 4547 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
4548
4a4a11b9 4549 io_task = task->dd_data;
43f388b0
JK		 4550
4551 if (io_task->pwrb_handle) {
4552 memset(io_task->pwrb_handle->pwrb, 0,
4553 sizeof(struct iscsi_wrb));
4554 free_wrb_handle(phba, pwrb_context,
4555 io_task->pwrb_handle);
4556 io_task->pwrb_handle = NULL;
4557 }
4558
4559 if (io_task->psgl_handle) {
4560 spin_lock_bh(&phba->mgmt_sgl_lock);
4561 free_mgmt_sgl_handle(phba,
4562 io_task->psgl_handle);
43f388b0 4563 io_task->psgl_handle = NULL;
4a4a11b9 4564 spin_unlock_bh(&phba->mgmt_sgl_lock);
43f388b0
JK		 4565 }
4566
4567 if (io_task->mtask_addr)
4568 pci_unmap_single(phba->pcidev,
4569 io_task->mtask_addr,
4570 io_task->mtask_data_count,
4571 PCI_DMA_TODEVICE);
4572}
4573
d629c471
JSJ		 4574/**
4575 * beiscsi_cleanup_task()- Free driver resources of the task
4576 * @task: ptr to the iscsi task
4577 *
4578 **/
1282ab76
MC		 4579static void beiscsi_cleanup_task(struct iscsi_task *task)
4580{
4581 struct beiscsi_io_task *io_task = task->dd_data;
4582 struct iscsi_conn *conn = task->conn;
4583 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4584 struct beiscsi_hba *phba = beiscsi_conn->phba;
4585 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
4586 struct hwi_wrb_context *pwrb_context;
4587 struct hwi_controller *phwi_ctrlr;
a7909b39
JK		 4588 uint16_t cri_index = BE_GET_CRI_FROM_CID(
4589 beiscsi_conn->beiscsi_conn_cid);
1282ab76
MC		 4590
4591 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 4592 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
1282ab76
MC		 4593
4594 if (io_task->cmd_bhs) {
4595 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
4596 io_task->bhs_pa.u.a64.address);
4597 io_task->cmd_bhs = NULL;
4598 }
4599
4600 if (task->sc) {
4601 if (io_task->pwrb_handle) {
4602 free_wrb_handle(phba, pwrb_context,
4603 io_task->pwrb_handle);
4604 io_task->pwrb_handle = NULL;
4605 }
4606
4607 if (io_task->psgl_handle) {
4608 spin_lock(&phba->io_sgl_lock);
4609 free_io_sgl_handle(phba, io_task->psgl_handle);
4610 spin_unlock(&phba->io_sgl_lock);
4611 io_task->psgl_handle = NULL;
4612 }
da334977
JK		 4613
4614 if (io_task->scsi_cmnd) {
4615 scsi_dma_unmap(io_task->scsi_cmnd);
4616 io_task->scsi_cmnd = NULL;
4617 }
1282ab76 4618 } else {
43f388b0 4619 if (!beiscsi_conn->login_in_progress)
4a4a11b9 4620 beiscsi_free_mgmt_task_handles(beiscsi_conn, task);
1282ab76
MC		 4621 }
4622}
4623
6733b39a
JK		 4624void
4625beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
4626 struct beiscsi_offload_params *params)
4627{
4628 struct wrb_handle *pwrb_handle;
6733b39a 4629 struct beiscsi_hba *phba = beiscsi_conn->phba;
1282ab76
MC		 4630 struct iscsi_task *task = beiscsi_conn->task;
4631 struct iscsi_session *session = task->conn->session;
6733b39a
JK		 4632 u32 doorbell = 0;
4633
4634 /*
4635 * We can always use 0 here because it is reserved by libiscsi for
4636 * login/startup related tasks.
4637 */
1282ab76 4638 beiscsi_conn->login_in_progress = 0;
659743b0 4639 spin_lock_bh(&session->back_lock);
1282ab76 4640 beiscsi_cleanup_task(task);
659743b0 4641 spin_unlock_bh(&session->back_lock);
1282ab76 4642
a7909b39 4643 pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid);
6733b39a 4644
acb9693c 4645 /* Check for the adapter family */
2c9dfd36 4646 if (is_chip_be2_be3r(phba))
acb9693c
JSJ		 4647 beiscsi_offload_cxn_v0(params, pwrb_handle,
4648 phba->init_mem);
2c9dfd36
JK		 4649 else
4650 beiscsi_offload_cxn_v2(params, pwrb_handle);
6733b39a 4651
acb9693c
JSJ		 4652 be_dws_le_to_cpu(pwrb_handle->pwrb,
4653 sizeof(struct iscsi_target_context_update_wrb));
6733b39a
JK		 4654
4655 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 4656 doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
bfead3b2 4657 << DB_DEF_PDU_WRB_INDEX_SHIFT;
6733b39a 4658 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4659 iowrite32(doorbell, phba->db_va +
4660 beiscsi_conn->doorbell_offset);
6733b39a
JK		 4661}
4662
4663static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
4664 int *index, int *age)
4665{
bfead3b2 4666 *index = (int)itt;
6733b39a
JK		 4667 if (age)
4668 *age = conn->session->age;
4669}
4670
4671/**
4672 * beiscsi_alloc_pdu - allocates pdu and related resources
4673 * @task: libiscsi task
4674 * @opcode: opcode of pdu for task
4675 *
4676 * This is called with the session lock held. It will allocate
4677 * the wrb and sgl if needed for the command. And it will prep
4678 * the pdu's itt. beiscsi_parse_pdu will later translate
4679 * the pdu itt to the libiscsi task itt.
4680 */
4681static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
4682{
4683 struct beiscsi_io_task *io_task = task->dd_data;
4684 struct iscsi_conn *conn = task->conn;
4685 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4686 struct beiscsi_hba *phba = beiscsi_conn->phba;
4687 struct hwi_wrb_context *pwrb_context;
4688 struct hwi_controller *phwi_ctrlr;
4689 itt_t itt;
a7909b39 4690 uint16_t cri_index = 0;
2afc95bf
JK		 4691 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
4692 dma_addr_t paddr;
6733b39a 4693
2afc95bf 4694 io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
bc7accec 4695 GFP_ATOMIC, &paddr);
2afc95bf
JK		 4696 if (!io_task->cmd_bhs)
4697 return -ENOMEM;
2afc95bf 4698 io_task->bhs_pa.u.a64.address = paddr;
bfead3b2 4699 io_task->libiscsi_itt = (itt_t)task->itt;
6733b39a
JK		 4700 io_task->conn = beiscsi_conn;
4701
4702 task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
4703 task->hdr_max = sizeof(struct be_cmd_bhs);
d2cecf0d 4704 io_task->psgl_handle = NULL;
3ec78271 4705 io_task->pwrb_handle = NULL;
6733b39a
JK		 4706
4707 if (task->sc) {
4708 spin_lock(&phba->io_sgl_lock);
4709 io_task->psgl_handle = alloc_io_sgl_handle(phba);
4710 spin_unlock(&phba->io_sgl_lock);
8359c79b
JSJ		 4711 if (!io_task->psgl_handle) {
4712 beiscsi_log(phba, KERN_ERR,
4713 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4714 "BM_%d : Alloc of IO_SGL_ICD Failed"
4715 "for the CID : %d\n",
4716 beiscsi_conn->beiscsi_conn_cid);
2afc95bf 4717 goto free_hndls;
8359c79b 4718 }
d2cecf0d 4719 io_task->pwrb_handle = alloc_wrb_handle(phba,
a7909b39 4720 beiscsi_conn->beiscsi_conn_cid);
8359c79b
JSJ		 4721 if (!io_task->pwrb_handle) {
4722 beiscsi_log(phba, KERN_ERR,
4723 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4724 "BM_%d : Alloc of WRB_HANDLE Failed"
4725 "for the CID : %d\n",
4726 beiscsi_conn->beiscsi_conn_cid);
d2cecf0d 4727 goto free_io_hndls;
8359c79b 4728 }
6733b39a
JK		 4729 } else {
4730 io_task->scsi_cmnd = NULL;
d7aea67b 4731 if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
43f388b0 4732 beiscsi_conn->task = task;
6733b39a
JK		 4733 if (!beiscsi_conn->login_in_progress) {
4734 spin_lock(&phba->mgmt_sgl_lock);
4735 io_task->psgl_handle = (struct sgl_handle *)
4736 alloc_mgmt_sgl_handle(phba);
4737 spin_unlock(&phba->mgmt_sgl_lock);
8359c79b
JSJ		 4738 if (!io_task->psgl_handle) {
4739 beiscsi_log(phba, KERN_ERR,
4740 BEISCSI_LOG_IO |
4741 BEISCSI_LOG_CONFIG,
4742 "BM_%d : Alloc of MGMT_SGL_ICD Failed"
4743 "for the CID : %d\n",
4744 beiscsi_conn->
4745 beiscsi_conn_cid);
2afc95bf 4746 goto free_hndls;
8359c79b 4747 }
2afc95bf 4748
6733b39a
JK		 4749 beiscsi_conn->login_in_progress = 1;
4750 beiscsi_conn->plogin_sgl_handle =
4751 io_task->psgl_handle;
d2cecf0d
JK		 4752 io_task->pwrb_handle =
4753 alloc_wrb_handle(phba,
a7909b39 4754 beiscsi_conn->beiscsi_conn_cid);
8359c79b
JSJ		 4755 if (!io_task->pwrb_handle) {
4756 beiscsi_log(phba, KERN_ERR,
4757 BEISCSI_LOG_IO |
4758 BEISCSI_LOG_CONFIG,
4759 "BM_%d : Alloc of WRB_HANDLE Failed"
4760 "for the CID : %d\n",
4761 beiscsi_conn->
4762 beiscsi_conn_cid);
4763 goto free_mgmt_hndls;
4764 }
d2cecf0d
JK		 4765 beiscsi_conn->plogin_wrb_handle =
4766 io_task->pwrb_handle;
4767
6733b39a
JK		 4768 } else {
4769 io_task->psgl_handle =
4770 beiscsi_conn->plogin_sgl_handle;
d2cecf0d
JK		 4771 io_task->pwrb_handle =
4772 beiscsi_conn->plogin_wrb_handle;
6733b39a
JK		 4773 }
4774 } else {
4775 spin_lock(&phba->mgmt_sgl_lock);
4776 io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
4777 spin_unlock(&phba->mgmt_sgl_lock);
8359c79b
JSJ		 4778 if (!io_task->psgl_handle) {
4779 beiscsi_log(phba, KERN_ERR,
4780 BEISCSI_LOG_IO |
4781 BEISCSI_LOG_CONFIG,
4782 "BM_%d : Alloc of MGMT_SGL_ICD Failed"
4783 "for the CID : %d\n",
4784 beiscsi_conn->
4785 beiscsi_conn_cid);
2afc95bf 4786 goto free_hndls;
8359c79b 4787 }
d2cecf0d
JK		 4788 io_task->pwrb_handle =
4789 alloc_wrb_handle(phba,
a7909b39 4790 beiscsi_conn->beiscsi_conn_cid);
8359c79b
JSJ		 4791 if (!io_task->pwrb_handle) {
4792 beiscsi_log(phba, KERN_ERR,
4793 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4794 "BM_%d : Alloc of WRB_HANDLE Failed"
4795 "for the CID : %d\n",
4796 beiscsi_conn->beiscsi_conn_cid);
d2cecf0d 4797 goto free_mgmt_hndls;
8359c79b 4798 }
d2cecf0d 4799
6733b39a
JK		 4800 }
4801 }
bfead3b2
JK		 4802 itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
4803 wrb_index << 16) | (unsigned int)
4804 (io_task->psgl_handle->sgl_index));
32951dd8 4805 io_task->pwrb_handle->pio_handle = task;
bfead3b2 4806
6733b39a
JK		 4807 io_task->cmd_bhs->iscsi_hdr.itt = itt;
4808 return 0;
2afc95bf 4809
d2cecf0d
JK		 4810free_io_hndls:
4811 spin_lock(&phba->io_sgl_lock);
4812 free_io_sgl_handle(phba, io_task->psgl_handle);
4813 spin_unlock(&phba->io_sgl_lock);
4814 goto free_hndls;
4815free_mgmt_hndls:
4816 spin_lock(&phba->mgmt_sgl_lock);
4817 free_mgmt_sgl_handle(phba, io_task->psgl_handle);
a7909b39 4818 io_task->psgl_handle = NULL;
d2cecf0d 4819 spin_unlock(&phba->mgmt_sgl_lock);
2afc95bf
JK		 4820free_hndls:
4821 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39
JK		 4822 cri_index = BE_GET_CRI_FROM_CID(
4823 beiscsi_conn->beiscsi_conn_cid);
4824 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
d2cecf0d
JK		 4825 if (io_task->pwrb_handle)
4826 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
2afc95bf
JK		 4827 io_task->pwrb_handle = NULL;
4828 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
4829 io_task->bhs_pa.u.a64.address);
1282ab76 4830 io_task->cmd_bhs = NULL;
2afc95bf 4831 return -ENOMEM;
6733b39a 4832}
09a1093a
JSJ		 4833int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg,
4834 unsigned int num_sg, unsigned int xferlen,
4835 unsigned int writedir)
4836{
4837
4838 struct beiscsi_io_task *io_task = task->dd_data;
4839 struct iscsi_conn *conn = task->conn;
4840 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4841 struct beiscsi_hba *phba = beiscsi_conn->phba;
4842 struct iscsi_wrb *pwrb = NULL;
4843 unsigned int doorbell = 0;
4844
4845 pwrb = io_task->pwrb_handle->pwrb;
09a1093a
JSJ		 4846
4847 io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
4848 io_task->bhs_len = sizeof(struct be_cmd_bhs);
4849
4850 if (writedir) {
4851 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
4852 INI_WR_CMD);
4853 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1);
4854 } else {
4855 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
4856 INI_RD_CMD);
4857 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0);
4858 }
4859
4860 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2,
4861 type, pwrb);
4862
4863 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb,
4864 cpu_to_be16(*(unsigned short *)
4865 &io_task->cmd_bhs->iscsi_hdr.lun));
4866 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen);
4867 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
4868 io_task->pwrb_handle->wrb_index);
4869 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
4870 be32_to_cpu(task->cmdsn));
4871 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
4872 io_task->psgl_handle->sgl_index);
4873
4874 hwi_write_sgl_v2(pwrb, sg, num_sg, io_task);
4875 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
4876 io_task->pwrb_handle->nxt_wrb_index);
4877
4878 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4879
4880 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
4881 doorbell |= (io_task->pwrb_handle->wrb_index &
4882 DB_DEF_PDU_WRB_INDEX_MASK) <<
4883 DB_DEF_PDU_WRB_INDEX_SHIFT;
4884 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4885 iowrite32(doorbell, phba->db_va +
4886 beiscsi_conn->doorbell_offset);
09a1093a
JSJ		 4887 return 0;
4888}
6733b39a 4889
6733b39a
JK		 4890static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
4891 unsigned int num_sg, unsigned int xferlen,
4892 unsigned int writedir)
4893{
4894
4895 struct beiscsi_io_task *io_task = task->dd_data;
4896 struct iscsi_conn *conn = task->conn;
4897 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4898 struct beiscsi_hba *phba = beiscsi_conn->phba;
4899 struct iscsi_wrb *pwrb = NULL;
4900 unsigned int doorbell = 0;
4901
4902 pwrb = io_task->pwrb_handle->pwrb;
6733b39a
JK		 4903 io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
4904 io_task->bhs_len = sizeof(struct be_cmd_bhs);
4905
4906 if (writedir) {
32951dd8
JK		 4907 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4908 INI_WR_CMD);
6733b39a 4909 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
6733b39a 4910 } else {
32951dd8
JK		 4911 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4912 INI_RD_CMD);
6733b39a
JK		 4913 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
4914 }
6733b39a 4915
09a1093a
JSJ		 4916 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb,
4917 type, pwrb);
4918
6733b39a 4919 AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
dc63aac6
JK		 4920 cpu_to_be16(*(unsigned short *)
4921 &io_task->cmd_bhs->iscsi_hdr.lun));
6733b39a
JK		 4922 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
4923 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
4924 io_task->pwrb_handle->wrb_index);
4925 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
4926 be32_to_cpu(task->cmdsn));
4927 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
4928 io_task->psgl_handle->sgl_index);
4929
4930 hwi_write_sgl(pwrb, sg, num_sg, io_task);
4931
4932 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
4933 io_task->pwrb_handle->nxt_wrb_index);
4934 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4935
4936 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 4937 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 4938 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
4939 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
4940
1e4be6ff
JK		 4941 iowrite32(doorbell, phba->db_va +
4942 beiscsi_conn->doorbell_offset);
6733b39a
JK		 4943 return 0;
4944}
4945
4946static int beiscsi_mtask(struct iscsi_task *task)
4947{
dafab8e0 4948 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 4949 struct iscsi_conn *conn = task->conn;
4950 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4951 struct beiscsi_hba *phba = beiscsi_conn->phba;
4952 struct iscsi_wrb *pwrb = NULL;
4953 unsigned int doorbell = 0;
dafab8e0 4954 unsigned int cid;
09a1093a 4955 unsigned int pwrb_typeoffset = 0;
6733b39a 4956
bfead3b2 4957 cid = beiscsi_conn->beiscsi_conn_cid;
6733b39a 4958 pwrb = io_task->pwrb_handle->pwrb;
caf818f1 4959 memset(pwrb, 0, sizeof(*pwrb));
09a1093a 4960
2c9dfd36 4961 if (is_chip_be2_be3r(phba)) {
09a1093a
JSJ		 4962 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
4963 be32_to_cpu(task->cmdsn));
4964 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
4965 io_task->pwrb_handle->wrb_index);
4966 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
4967 io_task->psgl_handle->sgl_index);
4968 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
4969 task->data_count);
4970 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
4971 io_task->pwrb_handle->nxt_wrb_index);
4972 pwrb_typeoffset = BE_WRB_TYPE_OFFSET;
2c9dfd36
JK		 4973 } else {
4974 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
4975 be32_to_cpu(task->cmdsn));
4976 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
4977 io_task->pwrb_handle->wrb_index);
4978 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
4979 io_task->psgl_handle->sgl_index);
4980 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb,
4981 task->data_count);
4982 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
4983 io_task->pwrb_handle->nxt_wrb_index);
4984 pwrb_typeoffset = SKH_WRB_TYPE_OFFSET;
09a1093a
JSJ		 4985 }
4986
dafab8e0 4987
6733b39a
JK		 4988 switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
4989 case ISCSI_OP_LOGIN:
6733b39a 4990 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
09a1093a 4991 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
6733b39a
JK		 4992 hwi_write_buffer(pwrb, task);
4993 break;
4994 case ISCSI_OP_NOOP_OUT:
1390b01b 4995 if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
09a1093a 4996 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
2c9dfd36
JK		 4997 if (is_chip_be2_be3r(phba))
4998 AMAP_SET_BITS(struct amap_iscsi_wrb,
09a1093a
JSJ		 4999 dmsg, pwrb, 1);
5000 else
2c9dfd36 5001 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
09a1093a 5002 dmsg, pwrb, 1);
1390b01b 5003 } else {
09a1093a 5004 ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset);
2c9dfd36
JK		 5005 if (is_chip_be2_be3r(phba))
5006 AMAP_SET_BITS(struct amap_iscsi_wrb,
09a1093a
JSJ		 5007 dmsg, pwrb, 0);
5008 else
2c9dfd36 5009 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
09a1093a 5010 dmsg, pwrb, 0);
1390b01b 5011 }
6733b39a
JK		 5012 hwi_write_buffer(pwrb, task);
5013 break;
5014 case ISCSI_OP_TEXT:
09a1093a 5015 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
6733b39a
JK		 5016 hwi_write_buffer(pwrb, task);
5017 break;
5018 case ISCSI_OP_SCSI_TMFUNC:
09a1093a 5019 ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset);
6733b39a
JK		 5020 hwi_write_buffer(pwrb, task);
5021 break;
5022 case ISCSI_OP_LOGOUT:
09a1093a 5023 ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset);
6733b39a
JK		 5024 hwi_write_buffer(pwrb, task);
5025 break;
5026
5027 default:
99bc5d55
JSJ		 5028 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
5029 "BM_%d : opcode =%d Not supported\n",
5030 task->hdr->opcode & ISCSI_OPCODE_MASK);
5031
6733b39a
JK		 5032 return -EINVAL;
5033 }
5034
09a1093a 5035 /* Set the task type */
2c9dfd36
JK		 5036 io_task->wrb_type = (is_chip_be2_be3r(phba)) ?
5037 AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) :
5038 AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb);
6733b39a 5039
bfead3b2 5040 doorbell |= cid & DB_WRB_POST_CID_MASK;
32951dd8 5041 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 5042 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
5043 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 5044 iowrite32(doorbell, phba->db_va +
5045 beiscsi_conn->doorbell_offset);
6733b39a
JK		 5046 return 0;
5047}
5048
5049static int beiscsi_task_xmit(struct iscsi_task *task)
5050{
6733b39a
JK		 5051 struct beiscsi_io_task *io_task = task->dd_data;
5052 struct scsi_cmnd *sc = task->sc;
09a1093a 5053 struct beiscsi_hba *phba = NULL;
6733b39a
JK		 5054 struct scatterlist *sg;
5055 int num_sg;
5056 unsigned int writedir = 0, xferlen = 0;
5057
09a1093a
JSJ		 5058 phba = ((struct beiscsi_conn *)task->conn->dd_data)->phba;
5059
6733b39a
JK		 5060 if (!sc)
5061 return beiscsi_mtask(task);
5062
5063 io_task->scsi_cmnd = sc;
5064 num_sg = scsi_dma_map(sc);
5065 if (num_sg < 0) {
99bc5d55
JSJ		 5066 struct iscsi_conn *conn = task->conn;
5067 struct beiscsi_hba *phba = NULL;
5068
5069 phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
afb96058
JK		 5070 beiscsi_log(phba, KERN_ERR,
5071 BEISCSI_LOG_IO | BEISCSI_LOG_ISCSI,
5072 "BM_%d : scsi_dma_map Failed "
5073 "Driver_ITT : 0x%x ITT : 0x%x Xferlen : 0x%x\n",
5074 be32_to_cpu(io_task->cmd_bhs->iscsi_hdr.itt),
5075 io_task->libiscsi_itt, scsi_bufflen(sc));
99bc5d55 5076
6733b39a
JK		 5077 return num_sg;
5078 }
6733b39a
JK		 5079 xferlen = scsi_bufflen(sc);
5080 sg = scsi_sglist(sc);
99bc5d55 5081 if (sc->sc_data_direction == DMA_TO_DEVICE)
6733b39a 5082 writedir = 1;
99bc5d55 5083 else
6733b39a 5084 writedir = 0;
99bc5d55 5085
09a1093a 5086 return phba->iotask_fn(task, sg, num_sg, xferlen, writedir);
6733b39a
JK		 5087}
5088
ffce3e2e
JK		 5089/**
5090 * beiscsi_bsg_request - handle bsg request from ISCSI transport
5091 * @job: job to handle
5092 */
5093static int beiscsi_bsg_request(struct bsg_job *job)
5094{
5095 struct Scsi_Host *shost;
5096 struct beiscsi_hba *phba;
5097 struct iscsi_bsg_request *bsg_req = job->request;
5098 int rc = -EINVAL;
5099 unsigned int tag;
5100 struct be_dma_mem nonemb_cmd;
5101 struct be_cmd_resp_hdr *resp;
5102 struct iscsi_bsg_reply *bsg_reply = job->reply;
5103 unsigned short status, extd_status;
5104
5105 shost = iscsi_job_to_shost(job);
5106 phba = iscsi_host_priv(shost);
5107
5108 switch (bsg_req->msgcode) {
5109 case ISCSI_BSG_HST_VENDOR:
5110 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
5111 job->request_payload.payload_len,
5112 &nonemb_cmd.dma);
5113 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 5114 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
5115 "BM_%d : Failed to allocate memory for "
5116 "beiscsi_bsg_request\n");
8359c79b 5117 return -ENOMEM;
ffce3e2e
JK		 5118 }
5119 tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
5120 &nonemb_cmd);
5121 if (!tag) {
99bc5d55 5122 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
8359c79b 5123 "BM_%d : MBX Tag Allocation Failed\n");
99bc5d55 5124
ffce3e2e
JK		 5125 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
5126 nonemb_cmd.va, nonemb_cmd.dma);
5127 return -EAGAIN;
e175defe
JSJ		 5128 }
5129
5130 rc = wait_event_interruptible_timeout(
5131 phba->ctrl.mcc_wait[tag],
5132 phba->ctrl.mcc_numtag[tag],
5133 msecs_to_jiffies(
5134 BEISCSI_HOST_MBX_TIMEOUT));
ffce3e2e
JK		 5135 extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
5136 status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
5137 free_mcc_tag(&phba->ctrl, tag);
5138 resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
5139 sg_copy_from_buffer(job->reply_payload.sg_list,
5140 job->reply_payload.sg_cnt,
5141 nonemb_cmd.va, (resp->response_length
5142 + sizeof(*resp)));
5143 bsg_reply->reply_payload_rcv_len = resp->response_length;
5144 bsg_reply->result = status;
5145 bsg_job_done(job, bsg_reply->result,
5146 bsg_reply->reply_payload_rcv_len);
5147 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
5148 nonemb_cmd.va, nonemb_cmd.dma);
5149 if (status || extd_status) {
99bc5d55 5150 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
8359c79b 5151 "BM_%d : MBX Cmd Failed"
99bc5d55
JSJ		 5152 " status = %d extd_status = %d\n",
5153 status, extd_status);
5154
ffce3e2e 5155 return -EIO;
8359c79b
JSJ		 5156 } else {
5157 rc = 0;
ffce3e2e
JK		 5158 }
5159 break;
5160
5161 default:
99bc5d55
JSJ		 5162 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
5163 "BM_%d : Unsupported bsg command: 0x%x\n",
5164 bsg_req->msgcode);
ffce3e2e
JK		 5165 break;
5166 }
5167
5168 return rc;
5169}
5170
99bc5d55
JSJ		 5171void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
5172{
5173 /* Set the logging parameter */
5174 beiscsi_log_enable_init(phba, beiscsi_log_enable);
5175}
5176
4d4d1ef8
JSJ		 5177/*
5178 * beiscsi_quiesce()- Cleanup Driver resources
5179 * @phba: Instance Priv structure
3567f36a 5180 * @unload_state:i Clean or EEH unload state
4d4d1ef8
JSJ		 5181 *
5182 * Free the OS and HW resources held by the driver
5183 **/
3567f36a
JK		 5184static void beiscsi_quiesce(struct beiscsi_hba *phba,
5185 uint32_t unload_state)
6733b39a 5186{
bfead3b2
JK		 5187 struct hwi_controller *phwi_ctrlr;
5188 struct hwi_context_memory *phwi_context;
5189 struct be_eq_obj *pbe_eq;
5190 unsigned int i, msix_vec;
6733b39a 5191
bfead3b2
JK		 5192 phwi_ctrlr = phba->phwi_ctrlr;
5193 phwi_context = phwi_ctrlr->phwi_ctxt;
6733b39a 5194 hwi_disable_intr(phba);
bfead3b2
JK		 5195 if (phba->msix_enabled) {
5196 for (i = 0; i <= phba->num_cpus; i++) {
5197 msix_vec = phba->msix_entries[i].vector;
3567f36a 5198 synchronize_irq(msix_vec);
bfead3b2 5199 free_irq(msix_vec, &phwi_context->be_eq[i]);
8fcfb210 5200 kfree(phba->msi_name[i]);
bfead3b2
JK		 5201 }
5202 } else
3567f36a
JK		 5203 if (phba->pcidev->irq) {
5204 synchronize_irq(phba->pcidev->irq);
bfead3b2 5205 free_irq(phba->pcidev->irq, phba);
3567f36a 5206 }
bfead3b2 5207 pci_disable_msix(phba->pcidev);
3567f36a 5208
89f8b33c
JA		 5209 for (i = 0; i < phba->num_cpus; i++) {
5210 pbe_eq = &phwi_context->be_eq[i];
5211 blk_iopoll_disable(&pbe_eq->iopoll);
5212 }
6733b39a 5213
3567f36a
JK		 5214 if (unload_state == BEISCSI_CLEAN_UNLOAD) {
5215 destroy_workqueue(phba->wq);
5216 beiscsi_clean_port(phba);
5217 beiscsi_free_mem(phba);
e9b91193 5218
3567f36a
JK		 5219 beiscsi_unmap_pci_function(phba);
5220 pci_free_consistent(phba->pcidev,
5221 phba->ctrl.mbox_mem_alloced.size,
5222 phba->ctrl.mbox_mem_alloced.va,
5223 phba->ctrl.mbox_mem_alloced.dma);
5224 } else {
5225 hwi_purge_eq(phba);
5226 hwi_cleanup(phba);
5227 }
7a158003
JSJ		 5228
5229 cancel_delayed_work_sync(&phba->beiscsi_hw_check_task);
25602c97
JK		 5230}
5231
5232static void beiscsi_remove(struct pci_dev *pcidev)
5233{
5234
5235 struct beiscsi_hba *phba = NULL;
5236
5237 phba = pci_get_drvdata(pcidev);
5238 if (!phba) {
5239 dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
5240 return;
5241 }
5242
0e43895e 5243 beiscsi_destroy_def_ifaces(phba);
3567f36a 5244 beiscsi_quiesce(phba, BEISCSI_CLEAN_UNLOAD);
9d045163 5245 iscsi_boot_destroy_kset(phba->boot_kset);
6733b39a
JK		 5246 iscsi_host_remove(phba->shost);
5247 pci_dev_put(phba->pcidev);
5248 iscsi_host_free(phba->shost);
3567f36a
JK		 5249 pci_disable_pcie_error_reporting(pcidev);
5250 pci_set_drvdata(pcidev, NULL);
8dce69ff 5251 pci_disable_device(pcidev);
6733b39a
JK		 5252}
5253
25602c97
JK		 5254static void beiscsi_shutdown(struct pci_dev *pcidev)
5255{
5256
5257 struct beiscsi_hba *phba = NULL;
5258
5259 phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
5260 if (!phba) {
5261 dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
5262 return;
5263 }
5264
9343be74
JK		 5265 phba->state = BE_ADAPTER_STATE_SHUTDOWN;
5266 iscsi_host_for_each_session(phba->shost, be2iscsi_fail_session);
3567f36a 5267 beiscsi_quiesce(phba, BEISCSI_CLEAN_UNLOAD);
8dce69ff 5268 pci_disable_device(pcidev);
25602c97
JK		 5269}
5270
bfead3b2
JK		 5271static void beiscsi_msix_enable(struct beiscsi_hba *phba)
5272{
5273 int i, status;
5274
5275 for (i = 0; i <= phba->num_cpus; i++)
5276 phba->msix_entries[i].entry = i;
5277
5278 status = pci_enable_msix(phba->pcidev, phba->msix_entries,
5279 (phba->num_cpus + 1));
5280 if (!status)
5281 phba->msix_enabled = true;
5282
5283 return;
5284}
5285
73af08e1
JK		 5286static void be_eqd_update(struct beiscsi_hba *phba)
5287{
5288 struct be_set_eqd set_eqd[MAX_CPUS];
5289 struct be_aic_obj *aic;
5290 struct be_eq_obj *pbe_eq;
5291 struct hwi_controller *phwi_ctrlr;
5292 struct hwi_context_memory *phwi_context;
5293 int eqd, i, num = 0;
5294 ulong now;
5295 u32 pps, delta;
5296 unsigned int tag;
5297
5298 phwi_ctrlr = phba->phwi_ctrlr;
5299 phwi_context = phwi_ctrlr->phwi_ctxt;
5300
5301 for (i = 0; i <= phba->num_cpus; i++) {
5302 aic = &phba->aic_obj[i];
5303 pbe_eq = &phwi_context->be_eq[i];
5304 now = jiffies;
5305 if (!aic->jiffs || time_before(now, aic->jiffs) ||
5306 pbe_eq->cq_count < aic->eq_prev) {
5307 aic->jiffs = now;
5308 aic->eq_prev = pbe_eq->cq_count;
5309 continue;
5310 }
5311 delta = jiffies_to_msecs(now - aic->jiffs);
5312 pps = (((u32)(pbe_eq->cq_count - aic->eq_prev) * 1000) / delta);
5313 eqd = (pps / 1500) << 2;
5314
5315 if (eqd < 8)
5316 eqd = 0;
5317 eqd = min_t(u32, eqd, phwi_context->max_eqd);
5318 eqd = max_t(u32, eqd, phwi_context->min_eqd);
5319
5320 aic->jiffs = now;
5321 aic->eq_prev = pbe_eq->cq_count;
5322
5323 if (eqd != aic->prev_eqd) {
5324 set_eqd[num].delay_multiplier = (eqd * 65)/100;
5325 set_eqd[num].eq_id = pbe_eq->q.id;
5326 aic->prev_eqd = eqd;
5327 num++;
5328 }
5329 }
5330 if (num) {
5331 tag = be_cmd_modify_eq_delay(phba, set_eqd, num);
5332 if (tag)
5333 beiscsi_mccq_compl(phba, tag, NULL, NULL);
5334 }
5335}
5336
7a158003
JSJ		 5337/*
5338 * beiscsi_hw_health_check()- Check adapter health
5339 * @work: work item to check HW health
5340 *
5341 * Check if adapter in an unrecoverable state or not.
5342 **/
5343static void
5344beiscsi_hw_health_check(struct work_struct *work)
5345{
5346 struct beiscsi_hba *phba =
5347 container_of(work, struct beiscsi_hba,
5348 beiscsi_hw_check_task.work);
5349
73af08e1
JK		 5350 be_eqd_update(phba);
5351
7a158003
JSJ		 5352 beiscsi_ue_detect(phba);
5353
5354 schedule_delayed_work(&phba->beiscsi_hw_check_task,
5355 msecs_to_jiffies(1000));
5356}
5357
3567f36a
JK		 5358
5359static pci_ers_result_t beiscsi_eeh_err_detected(struct pci_dev *pdev,
5360 pci_channel_state_t state)
5361{
5362 struct beiscsi_hba *phba = NULL;
5363
5364 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5365 phba->state |= BE_ADAPTER_PCI_ERR;
5366
5367 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5368 "BM_%d : EEH error detected\n");
5369
5370 beiscsi_quiesce(phba, BEISCSI_EEH_UNLOAD);
5371
5372 if (state == pci_channel_io_perm_failure) {
5373 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5374 "BM_%d : EEH : State PERM Failure");
5375 return PCI_ERS_RESULT_DISCONNECT;
5376 }
5377
5378 pci_disable_device(pdev);
5379
5380 /* The error could cause the FW to trigger a flash debug dump.
5381 * Resetting the card while flash dump is in progress
5382 * can cause it not to recover; wait for it to finish.
5383 * Wait only for first function as it is needed only once per
5384 * adapter.
5385 **/
5386 if (pdev->devfn == 0)
5387 ssleep(30);
5388
5389 return PCI_ERS_RESULT_NEED_RESET;
5390}
5391
5392static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev)
5393{
5394 struct beiscsi_hba *phba = NULL;
5395 int status = 0;
5396
5397 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5398
5399 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5400 "BM_%d : EEH Reset\n");
5401
5402 status = pci_enable_device(pdev);
5403 if (status)
5404 return PCI_ERS_RESULT_DISCONNECT;
5405
5406 pci_set_master(pdev);
5407 pci_set_power_state(pdev, PCI_D0);
5408 pci_restore_state(pdev);
5409
5410 /* Wait for the CHIP Reset to complete */
5411 status = be_chk_reset_complete(phba);
5412 if (!status) {
5413 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5414 "BM_%d : EEH Reset Completed\n");
5415 } else {
5416 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5417 "BM_%d : EEH Reset Completion Failure\n");
5418 return PCI_ERS_RESULT_DISCONNECT;
5419 }
5420
5421 pci_cleanup_aer_uncorrect_error_status(pdev);
5422 return PCI_ERS_RESULT_RECOVERED;
5423}
5424
5425static void beiscsi_eeh_resume(struct pci_dev *pdev)
5426{
5427 int ret = 0, i;
5428 struct be_eq_obj *pbe_eq;
5429 struct beiscsi_hba *phba = NULL;
5430 struct hwi_controller *phwi_ctrlr;
5431 struct hwi_context_memory *phwi_context;
5432
5433 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5434 pci_save_state(pdev);
5435
5436 if (enable_msix)
5437 find_num_cpus(phba);
5438 else
5439 phba->num_cpus = 1;
5440
5441 if (enable_msix) {
5442 beiscsi_msix_enable(phba);
5443 if (!phba->msix_enabled)
5444 phba->num_cpus = 1;
5445 }
5446
5447 ret = beiscsi_cmd_reset_function(phba);
5448 if (ret) {
5449 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5450 "BM_%d : Reset Failed\n");
5451 goto ret_err;
5452 }
5453
5454 ret = be_chk_reset_complete(phba);
5455 if (ret) {
5456 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5457 "BM_%d : Failed to get out of reset.\n");
5458 goto ret_err;
5459 }
5460
5461 beiscsi_get_params(phba);
5462 phba->shost->max_id = phba->params.cxns_per_ctrl;
5463 phba->shost->can_queue = phba->params.ios_per_ctrl;
5464 ret = hwi_init_controller(phba);
5465
5466 for (i = 0; i < MAX_MCC_CMD; i++) {
5467 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5468 phba->ctrl.mcc_tag[i] = i + 1;
5469 phba->ctrl.mcc_numtag[i + 1] = 0;
5470 phba->ctrl.mcc_tag_available++;
5471 }
5472
5473 phwi_ctrlr = phba->phwi_ctrlr;
5474 phwi_context = phwi_ctrlr->phwi_ctxt;
5475
89f8b33c 5476 for (i = 0; i < phba->num_cpus; i++) {
3567f36a 5477 pbe_eq = &phwi_context->be_eq[i];
89f8b33c
JA		 5478 blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
5479 be_iopoll);
5480 blk_iopoll_enable(&pbe_eq->iopoll);
3567f36a
JK		 5481 }
5482
89f8b33c
JA		 5483 i = (phba->msix_enabled) ? i : 0;
5484 /* Work item for MCC handling */
5485 pbe_eq = &phwi_context->be_eq[i];
5486 INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
5487
3567f36a
JK		 5488 ret = beiscsi_init_irqs(phba);
5489 if (ret < 0) {
5490 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5491 "BM_%d : beiscsi_eeh_resume - "
5492 "Failed to beiscsi_init_irqs\n");
5493 goto ret_err;
5494 }
5495
5496 hwi_enable_intr(phba);
5497 phba->state &= ~BE_ADAPTER_PCI_ERR;
5498
5499 return;
5500ret_err:
5501 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5502 "BM_%d : AER EEH Resume Failed\n");
5503}
5504
6f039790
GKH		 5505static int beiscsi_dev_probe(struct pci_dev *pcidev,
5506 const struct pci_device_id *id)
6733b39a
JK		 5507{
5508 struct beiscsi_hba *phba = NULL;
bfead3b2
JK		 5509 struct hwi_controller *phwi_ctrlr;
5510 struct hwi_context_memory *phwi_context;
5511 struct be_eq_obj *pbe_eq;
3567f36a 5512 int ret = 0, i;
6733b39a
JK		 5513
5514 ret = beiscsi_enable_pci(pcidev);
5515 if (ret < 0) {
99bc5d55
JSJ		 5516 dev_err(&pcidev->dev,
5517 "beiscsi_dev_probe - Failed to enable pci device\n");
6733b39a
JK		 5518 return ret;
5519 }
5520
5521 phba = beiscsi_hba_alloc(pcidev);
5522 if (!phba) {
99bc5d55
JSJ		 5523 dev_err(&pcidev->dev,
5524 "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
6733b39a
JK		 5525 goto disable_pci;
5526 }
5527
3567f36a
JK		 5528 /* Enable EEH reporting */
5529 ret = pci_enable_pcie_error_reporting(pcidev);
5530 if (ret)
5531 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5532 "BM_%d : PCIe Error Reporting "
5533 "Enabling Failed\n");
5534
5535 pci_save_state(pcidev);
5536
99bc5d55
JSJ		 5537 /* Initialize Driver configuration Paramters */
5538 beiscsi_hba_attrs_init(phba);
5539
e175defe 5540 phba->fw_timeout = false;
6c83185a 5541 phba->mac_addr_set = false;
e175defe
JSJ		 5542
5543
f98c96b0
JK		 5544 switch (pcidev->device) {
5545 case BE_DEVICE_ID1:
5546 case OC_DEVICE_ID1:
5547 case OC_DEVICE_ID2:
5548 phba->generation = BE_GEN2;
09a1093a 5549 phba->iotask_fn = beiscsi_iotask;
f98c96b0
JK		 5550 break;
5551 case BE_DEVICE_ID2:
5552 case OC_DEVICE_ID3:
5553 phba->generation = BE_GEN3;
09a1093a 5554 phba->iotask_fn = beiscsi_iotask;
f98c96b0 5555 break;
139a1b1e
JSJ		 5556 case OC_SKH_ID1:
5557 phba->generation = BE_GEN4;
09a1093a 5558 phba->iotask_fn = beiscsi_iotask_v2;
bf9131cb 5559 break;
f98c96b0
JK		 5560 default:
5561 phba->generation = 0;
5562 }
5563
6733b39a
JK		 5564 ret = be_ctrl_init(phba, pcidev);
5565 if (ret) {
99bc5d55
JSJ		 5566 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5567 "BM_%d : beiscsi_dev_probe-"
5568 "Failed in be_ctrl_init\n");
6733b39a
JK		 5569 goto hba_free;
5570 }
5571
4d4d1ef8
JSJ		 5572 ret = beiscsi_cmd_reset_function(phba);
5573 if (ret) {
5574 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
92665a66 5575 "BM_%d : Reset Failed\n");
4d4d1ef8
JSJ		 5576 goto hba_free;
5577 }
5578 ret = be_chk_reset_complete(phba);
5579 if (ret) {
5580 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
92665a66 5581 "BM_%d : Failed to get out of reset.\n");
4d4d1ef8 5582 goto hba_free;
e9b91193
JK		 5583 }
5584
6733b39a
JK		 5585 spin_lock_init(&phba->io_sgl_lock);
5586 spin_lock_init(&phba->mgmt_sgl_lock);
5587 spin_lock_init(&phba->isr_lock);
8f09a3b9 5588 spin_lock_init(&phba->async_pdu_lock);
7da50879
JK		 5589 ret = mgmt_get_fw_config(&phba->ctrl, phba);
5590 if (ret != 0) {
99bc5d55
JSJ		 5591 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5592 "BM_%d : Error getting fw config\n");
7da50879
JK		 5593 goto free_port;
5594 }
68c26a3a
JK		 5595
5596 if (enable_msix)
5597 find_num_cpus(phba);
5598 else
5599 phba->num_cpus = 1;
5600
5601 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
5602 "BM_%d : num_cpus = %d\n",
5603 phba->num_cpus);
5604
5605 if (enable_msix) {
5606 beiscsi_msix_enable(phba);
5607 if (!phba->msix_enabled)
5608 phba->num_cpus = 1;
5609 }
5610
843ae752 5611 phba->shost->max_id = phba->params.cxns_per_ctrl;
6733b39a 5612 beiscsi_get_params(phba);
aa874f07 5613 phba->shost->can_queue = phba->params.ios_per_ctrl;
6733b39a
JK		 5614 ret = beiscsi_init_port(phba);
5615 if (ret < 0) {
99bc5d55
JSJ		 5616 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5617 "BM_%d : beiscsi_dev_probe-"
5618 "Failed in beiscsi_init_port\n");
6733b39a
JK		 5619 goto free_port;
5620 }
5621
3567f36a 5622 for (i = 0; i < MAX_MCC_CMD; i++) {
756d29c8
JK		 5623 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5624 phba->ctrl.mcc_tag[i] = i + 1;
5625 phba->ctrl.mcc_numtag[i + 1] = 0;
5626 phba->ctrl.mcc_tag_available++;
1957aa7f
JK		 5627 memset(&phba->ctrl.ptag_state[i].tag_mem_state, 0,
5628 sizeof(struct beiscsi_mcc_tag_state));
756d29c8
JK		 5629 }
5630
5631 phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
5632
72fb46a9 5633 snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
6733b39a 5634 phba->shost->host_no);
d8537548 5635 phba->wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 1, phba->wq_name);
6733b39a 5636 if (!phba->wq) {
99bc5d55
JSJ		 5637 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5638 "BM_%d : beiscsi_dev_probe-"
5639 "Failed to allocate work queue\n");
6733b39a
JK		 5640 goto free_twq;
5641 }
5642
7a158003
JSJ		 5643 INIT_DELAYED_WORK(&phba->beiscsi_hw_check_task,
5644 beiscsi_hw_health_check);
6733b39a 5645
bfead3b2
JK		 5646 phwi_ctrlr = phba->phwi_ctrlr;
5647 phwi_context = phwi_ctrlr->phwi_ctxt;
72fb46a9 5648
89f8b33c 5649 for (i = 0; i < phba->num_cpus; i++) {
72fb46a9 5650 pbe_eq = &phwi_context->be_eq[i];
89f8b33c
JA		 5651 blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
5652 be_iopoll);
5653 blk_iopoll_enable(&pbe_eq->iopoll);
6733b39a 5654 }
72fb46a9 5655
89f8b33c
JA		 5656 i = (phba->msix_enabled) ? i : 0;
5657 /* Work item for MCC handling */
5658 pbe_eq = &phwi_context->be_eq[i];
5659 INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
5660
6733b39a
JK		 5661 ret = beiscsi_init_irqs(phba);
5662 if (ret < 0) {
99bc5d55
JSJ		 5663 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5664 "BM_%d : beiscsi_dev_probe-"
5665 "Failed to beiscsi_init_irqs\n");
6733b39a
JK		 5666 goto free_blkenbld;
5667 }
238f6b72 5668 hwi_enable_intr(phba);
f457a46f 5669
0598b8af
JK		 5670 if (iscsi_host_add(phba->shost, &phba->pcidev->dev))
5671 goto free_blkenbld;
5672
f457a46f
MC		 5673 if (beiscsi_setup_boot_info(phba))
5674 /*
5675 * log error but continue, because we may not be using
5676 * iscsi boot.
5677 */
99bc5d55
JSJ		 5678 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5679 "BM_%d : Could not set up "
5680 "iSCSI boot info.\n");
f457a46f 5681
0e43895e 5682 beiscsi_create_def_ifaces(phba);
7a158003
JSJ		 5683 schedule_delayed_work(&phba->beiscsi_hw_check_task,
5684 msecs_to_jiffies(1000));
5685
99bc5d55
JSJ		 5686 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
5687 "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
6733b39a
JK		 5688 return 0;
5689
6733b39a
JK		 5690free_blkenbld:
5691 destroy_workqueue(phba->wq);
89f8b33c
JA		 5692 for (i = 0; i < phba->num_cpus; i++) {
5693 pbe_eq = &phwi_context->be_eq[i];
5694 blk_iopoll_disable(&pbe_eq->iopoll);
5695 }
6733b39a
JK		 5696free_twq:
5697 beiscsi_clean_port(phba);
5698 beiscsi_free_mem(phba);
5699free_port:
5700 pci_free_consistent(phba->pcidev,
5701 phba->ctrl.mbox_mem_alloced.size,
5702 phba->ctrl.mbox_mem_alloced.va,
5703 phba->ctrl.mbox_mem_alloced.dma);
5704 beiscsi_unmap_pci_function(phba);
5705hba_free:
238f6b72
JK		 5706 if (phba->msix_enabled)
5707 pci_disable_msix(phba->pcidev);
6733b39a
JK		 5708 iscsi_host_remove(phba->shost);
5709 pci_dev_put(phba->pcidev);
5710 iscsi_host_free(phba->shost);
5711disable_pci:
5712 pci_disable_device(pcidev);
5713 return ret;
5714}
5715
3567f36a
JK		 5716static struct pci_error_handlers beiscsi_eeh_handlers = {
5717 .error_detected = beiscsi_eeh_err_detected,
5718 .slot_reset = beiscsi_eeh_reset,
5719 .resume = beiscsi_eeh_resume,
5720};
5721
6733b39a
JK		 5722struct iscsi_transport beiscsi_iscsi_transport = {
5723 .owner = THIS_MODULE,
5724 .name = DRV_NAME,
9db0fb3a 5725 .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
6733b39a 5726 CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
6733b39a
JK		 5727 .create_session = beiscsi_session_create,
5728 .destroy_session = beiscsi_session_destroy,
5729 .create_conn = beiscsi_conn_create,
5730 .bind_conn = beiscsi_conn_bind,
5731 .destroy_conn = iscsi_conn_teardown,
3128c6c7 5732 .attr_is_visible = be2iscsi_attr_is_visible,
0e43895e
MC		 5733 .set_iface_param = be2iscsi_iface_set_param,
5734 .get_iface_param = be2iscsi_iface_get_param,
6733b39a 5735 .set_param = beiscsi_set_param,
c7f7fd5b 5736 .get_conn_param = iscsi_conn_get_param,
6733b39a
JK		 5737 .get_session_param = iscsi_session_get_param,
5738 .get_host_param = beiscsi_get_host_param,
5739 .start_conn = beiscsi_conn_start,
fa95d206 5740 .stop_conn = iscsi_conn_stop,
6733b39a
JK		 5741 .send_pdu = iscsi_conn_send_pdu,
5742 .xmit_task = beiscsi_task_xmit,
5743 .cleanup_task = beiscsi_cleanup_task,
5744 .alloc_pdu = beiscsi_alloc_pdu,
5745 .parse_pdu_itt = beiscsi_parse_pdu,
5746 .get_stats = beiscsi_conn_get_stats,
c7f7fd5b 5747 .get_ep_param = beiscsi_ep_get_param,
6733b39a
JK		 5748 .ep_connect = beiscsi_ep_connect,
5749 .ep_poll = beiscsi_ep_poll,
5750 .ep_disconnect = beiscsi_ep_disconnect,
5751 .session_recovery_timedout = iscsi_session_recovery_timedout,
ffce3e2e 5752 .bsg_request = beiscsi_bsg_request,
6733b39a
JK		 5753};
5754
5755static struct pci_driver beiscsi_pci_driver = {
5756 .name = DRV_NAME,
5757 .probe = beiscsi_dev_probe,
5758 .remove = beiscsi_remove,
25602c97 5759 .shutdown = beiscsi_shutdown,
3567f36a
JK		 5760 .id_table = beiscsi_pci_id_table,
5761 .err_handler = &beiscsi_eeh_handlers
6733b39a
JK		 5762};
5763
bfead3b2 5764
6733b39a
JK		 5765static int __init beiscsi_module_init(void)
5766{
5767 int ret;
5768
5769 beiscsi_scsi_transport =
5770 iscsi_register_transport(&beiscsi_iscsi_transport);
5771 if (!beiscsi_scsi_transport) {
99bc5d55
JSJ		 5772 printk(KERN_ERR
5773 "beiscsi_module_init - Unable to register beiscsi transport.\n");
f55a24f2 5774 return -ENOMEM;
6733b39a 5775 }
99bc5d55
JSJ		 5776 printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
5777 &beiscsi_iscsi_transport);
6733b39a
JK		 5778
5779 ret = pci_register_driver(&beiscsi_pci_driver);
5780 if (ret) {
99bc5d55
JSJ		 5781 printk(KERN_ERR
5782 "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
6733b39a
JK		 5783 goto unregister_iscsi_transport;
5784 }
5785 return 0;
5786
5787unregister_iscsi_transport:
5788 iscsi_unregister_transport(&beiscsi_iscsi_transport);
5789 return ret;
5790}
5791
5792static void __exit beiscsi_module_exit(void)
5793{
5794 pci_unregister_driver(&beiscsi_pci_driver);
5795 iscsi_unregister_transport(&beiscsi_iscsi_transport);
5796}
5797
5798module_init(beiscsi_module_init);
5799module_exit(beiscsi_module_exit);
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