]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/scsi/be2iscsi/be_main.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] be2iscsi: Fix typo function name mismatch
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / be2iscsi / be_main.c
CommitLineData
6733b39a 1/**
255fa9a3 2 * Copyright (C) 2005 - 2011 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
255fa9a3 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
6733b39a
JK		 11 *
12 * Contact Information:
255fa9a3 13 * linux-drivers@emulex.com
6733b39a 14 *
255fa9a3
JK		 15 * Emulex
16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a 18 */
255fa9a3 19
6733b39a
JK		 20#include <linux/reboot.h>
21#include <linux/delay.h>
5a0e3ad6 22#include <linux/slab.h>
6733b39a
JK		 23#include <linux/interrupt.h>
24#include <linux/blkdev.h>
25#include <linux/pci.h>
26#include <linux/string.h>
27#include <linux/kernel.h>
28#include <linux/semaphore.h>
c7acc5b8 29#include <linux/iscsi_boot_sysfs.h>
acf3368f 30#include <linux/module.h>
6733b39a
JK		 31
32#include <scsi/libiscsi.h>
33#include <scsi/scsi_transport_iscsi.h>
34#include <scsi/scsi_transport.h>
35#include <scsi/scsi_cmnd.h>
36#include <scsi/scsi_device.h>
37#include <scsi/scsi_host.h>
38#include <scsi/scsi.h>
39#include "be_main.h"
40#include "be_iscsi.h"
41#include "be_mgmt.h"
42
43static unsigned int be_iopoll_budget = 10;
44static unsigned int be_max_phys_size = 64;
bfead3b2 45static unsigned int enable_msix = 1;
e9b91193
JK		 46static unsigned int gcrashmode = 0;
47static unsigned int num_hba = 0;
6733b39a
JK		 48
49MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
50MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
51MODULE_AUTHOR("ServerEngines Corporation");
52MODULE_LICENSE("GPL");
53module_param(be_iopoll_budget, int, 0);
54module_param(enable_msix, int, 0);
55module_param(be_max_phys_size, uint, S_IRUGO);
56MODULE_PARM_DESC(be_max_phys_size, "Maximum Size (In Kilobytes) of physically"
57 "contiguous memory that can be allocated."
58 "Range is 16 - 128");
59
60static int beiscsi_slave_configure(struct scsi_device *sdev)
61{
62 blk_queue_max_segment_size(sdev->request_queue, 65536);
63 return 0;
64}
65
4183122d
JK		 66static int beiscsi_eh_abort(struct scsi_cmnd *sc)
67{
68 struct iscsi_cls_session *cls_session;
69 struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
70 struct beiscsi_io_task *aborted_io_task;
71 struct iscsi_conn *conn;
72 struct beiscsi_conn *beiscsi_conn;
73 struct beiscsi_hba *phba;
74 struct iscsi_session *session;
75 struct invalidate_command_table *inv_tbl;
3cbb7a74 76 struct be_dma_mem nonemb_cmd;
4183122d
JK		 77 unsigned int cid, tag, num_invalidate;
78
79 cls_session = starget_to_session(scsi_target(sc->device));
80 session = cls_session->dd_data;
81
82 spin_lock_bh(&session->lock);
83 if (!aborted_task || !aborted_task->sc) {
84 /* we raced */
85 spin_unlock_bh(&session->lock);
86 return SUCCESS;
87 }
88
89 aborted_io_task = aborted_task->dd_data;
90 if (!aborted_io_task->scsi_cmnd) {
91 /* raced or invalid command */
92 spin_unlock_bh(&session->lock);
93 return SUCCESS;
94 }
95 spin_unlock_bh(&session->lock);
96 conn = aborted_task->conn;
97 beiscsi_conn = conn->dd_data;
98 phba = beiscsi_conn->phba;
99
100 /* invalidate iocb */
101 cid = beiscsi_conn->beiscsi_conn_cid;
102 inv_tbl = phba->inv_tbl;
103 memset(inv_tbl, 0x0, sizeof(*inv_tbl));
104 inv_tbl->cid = cid;
105 inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
106 num_invalidate = 1;
3cbb7a74
JK		 107 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
108 sizeof(struct invalidate_commands_params_in),
109 &nonemb_cmd.dma);
110 if (nonemb_cmd.va == NULL) {
111 SE_DEBUG(DBG_LVL_1,
112 "Failed to allocate memory for"
113 "mgmt_invalidate_icds\n");
114 return FAILED;
115 }
116 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
117
118 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
119 cid, &nonemb_cmd);
4183122d
JK		 120 if (!tag) {
121 shost_printk(KERN_WARNING, phba->shost,
122 "mgmt_invalidate_icds could not be"
123 " submitted\n");
3cbb7a74
JK		 124 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
125 nonemb_cmd.va, nonemb_cmd.dma);
126
4183122d
JK		 127 return FAILED;
128 } else {
129 wait_event_interruptible(phba->ctrl.mcc_wait[tag],
130 phba->ctrl.mcc_numtag[tag]);
131 free_mcc_tag(&phba->ctrl, tag);
132 }
3cbb7a74
JK		 133 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
134 nonemb_cmd.va, nonemb_cmd.dma);
4183122d
JK		 135 return iscsi_eh_abort(sc);
136}
137
138static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
139{
140 struct iscsi_task *abrt_task;
141 struct beiscsi_io_task *abrt_io_task;
142 struct iscsi_conn *conn;
143 struct beiscsi_conn *beiscsi_conn;
144 struct beiscsi_hba *phba;
145 struct iscsi_session *session;
146 struct iscsi_cls_session *cls_session;
147 struct invalidate_command_table *inv_tbl;
3cbb7a74 148 struct be_dma_mem nonemb_cmd;
4183122d
JK		 149 unsigned int cid, tag, i, num_invalidate;
150 int rc = FAILED;
151
152 /* invalidate iocbs */
153 cls_session = starget_to_session(scsi_target(sc->device));
154 session = cls_session->dd_data;
155 spin_lock_bh(&session->lock);
156 if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN)
157 goto unlock;
158
159 conn = session->leadconn;
160 beiscsi_conn = conn->dd_data;
161 phba = beiscsi_conn->phba;
162 cid = beiscsi_conn->beiscsi_conn_cid;
163 inv_tbl = phba->inv_tbl;
164 memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
165 num_invalidate = 0;
166 for (i = 0; i < conn->session->cmds_max; i++) {
167 abrt_task = conn->session->cmds[i];
168 abrt_io_task = abrt_task->dd_data;
169 if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
170 continue;
171
172 if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
173 continue;
174
175 inv_tbl->cid = cid;
176 inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
177 num_invalidate++;
178 inv_tbl++;
179 }
180 spin_unlock_bh(&session->lock);
181 inv_tbl = phba->inv_tbl;
182
3cbb7a74
JK		 183 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
184 sizeof(struct invalidate_commands_params_in),
185 &nonemb_cmd.dma);
186 if (nonemb_cmd.va == NULL) {
187 SE_DEBUG(DBG_LVL_1,
188 "Failed to allocate memory for"
189 "mgmt_invalidate_icds\n");
190 return FAILED;
191 }
192 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
193 memset(nonemb_cmd.va, 0, nonemb_cmd.size);
194 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
195 cid, &nonemb_cmd);
4183122d
JK		 196 if (!tag) {
197 shost_printk(KERN_WARNING, phba->shost,
198 "mgmt_invalidate_icds could not be"
199 " submitted\n");
3cbb7a74
JK		 200 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
201 nonemb_cmd.va, nonemb_cmd.dma);
4183122d
JK		 202 return FAILED;
203 } else {
204 wait_event_interruptible(phba->ctrl.mcc_wait[tag],
205 phba->ctrl.mcc_numtag[tag]);
206 free_mcc_tag(&phba->ctrl, tag);
207 }
3cbb7a74
JK		 208 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
209 nonemb_cmd.va, nonemb_cmd.dma);
4183122d
JK		 210 return iscsi_eh_device_reset(sc);
211unlock:
212 spin_unlock_bh(&session->lock);
213 return rc;
214}
215
c7acc5b8
JK		 216static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
217{
218 struct beiscsi_hba *phba = data;
f457a46f
MC		 219 struct mgmt_session_info *boot_sess = &phba->boot_sess;
220 struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
c7acc5b8
JK		 221 char *str = buf;
222 int rc;
223
224 switch (type) {
225 case ISCSI_BOOT_TGT_NAME:
226 rc = sprintf(buf, "%.*s\n",
f457a46f
MC		 227 (int)strlen(boot_sess->target_name),
228 (char *)&boot_sess->target_name);
c7acc5b8
JK		 229 break;
230 case ISCSI_BOOT_TGT_IP_ADDR:
f457a46f 231 if (boot_conn->dest_ipaddr.ip_type == 0x1)
c7acc5b8 232 rc = sprintf(buf, "%pI4\n",
f457a46f 233 (char *)&boot_conn->dest_ipaddr.ip_address);
c7acc5b8
JK		 234 else
235 rc = sprintf(str, "%pI6\n",
f457a46f 236 (char *)&boot_conn->dest_ipaddr.ip_address);
c7acc5b8
JK		 237 break;
238 case ISCSI_BOOT_TGT_PORT:
f457a46f 239 rc = sprintf(str, "%d\n", boot_conn->dest_port);
c7acc5b8
JK		 240 break;
241
242 case ISCSI_BOOT_TGT_CHAP_NAME:
243 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 244 boot_conn->negotiated_login_options.auth_data.chap.
245 target_chap_name_length,
246 (char *)&boot_conn->negotiated_login_options.
247 auth_data.chap.target_chap_name);
c7acc5b8
JK		 248 break;
249 case ISCSI_BOOT_TGT_CHAP_SECRET:
250 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 251 boot_conn->negotiated_login_options.auth_data.chap.
252 target_secret_length,
253 (char *)&boot_conn->negotiated_login_options.
254 auth_data.chap.target_secret);
c7acc5b8
JK		 255 break;
256 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
257 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 258 boot_conn->negotiated_login_options.auth_data.chap.
259 intr_chap_name_length,
260 (char *)&boot_conn->negotiated_login_options.
261 auth_data.chap.intr_chap_name);
c7acc5b8
JK		 262 break;
263 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
f457a46f
MC		 264 rc = sprintf(str, "%.*s\n",
265 boot_conn->negotiated_login_options.auth_data.chap.
266 intr_secret_length,
267 (char *)&boot_conn->negotiated_login_options.
268 auth_data.chap.intr_secret);
c7acc5b8
JK		 269 break;
270 case ISCSI_BOOT_TGT_FLAGS:
f457a46f 271 rc = sprintf(str, "2\n");
c7acc5b8
JK		 272 break;
273 case ISCSI_BOOT_TGT_NIC_ASSOC:
f457a46f 274 rc = sprintf(str, "0\n");
c7acc5b8
JK		 275 break;
276 default:
277 rc = -ENOSYS;
278 break;
279 }
280 return rc;
281}
282
283static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
284{
285 struct beiscsi_hba *phba = data;
286 char *str = buf;
287 int rc;
288
289 switch (type) {
290 case ISCSI_BOOT_INI_INITIATOR_NAME:
291 rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
292 break;
293 default:
294 rc = -ENOSYS;
295 break;
296 }
297 return rc;
298}
299
300static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
301{
302 struct beiscsi_hba *phba = data;
303 char *str = buf;
304 int rc;
305
306 switch (type) {
307 case ISCSI_BOOT_ETH_FLAGS:
f457a46f 308 rc = sprintf(str, "2\n");
c7acc5b8
JK		 309 break;
310 case ISCSI_BOOT_ETH_INDEX:
f457a46f 311 rc = sprintf(str, "0\n");
c7acc5b8
JK		 312 break;
313 case ISCSI_BOOT_ETH_MAC:
314 rc = beiscsi_get_macaddr(buf, phba);
315 if (rc < 0) {
316 SE_DEBUG(DBG_LVL_1, "beiscsi_get_macaddr Failed\n");
317 return rc;
318 }
319 break;
320 default:
321 rc = -ENOSYS;
322 break;
323 }
324 return rc;
325}
326
327
587a1f16 328static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
c7acc5b8 329{
587a1f16 330 umode_t rc;
c7acc5b8
JK		 331
332 switch (type) {
333 case ISCSI_BOOT_TGT_NAME:
334 case ISCSI_BOOT_TGT_IP_ADDR:
335 case ISCSI_BOOT_TGT_PORT:
336 case ISCSI_BOOT_TGT_CHAP_NAME:
337 case ISCSI_BOOT_TGT_CHAP_SECRET:
338 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
339 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
340 case ISCSI_BOOT_TGT_NIC_ASSOC:
341 case ISCSI_BOOT_TGT_FLAGS:
342 rc = S_IRUGO;
343 break;
344 default:
345 rc = 0;
346 break;
347 }
348 return rc;
349}
350
587a1f16 351static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
c7acc5b8 352{
587a1f16 353 umode_t rc;
c7acc5b8
JK		 354
355 switch (type) {
356 case ISCSI_BOOT_INI_INITIATOR_NAME:
357 rc = S_IRUGO;
358 break;
359 default:
360 rc = 0;
361 break;
362 }
363 return rc;
364}
365
366
587a1f16 367static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
c7acc5b8 368{
587a1f16 369 umode_t rc;
c7acc5b8
JK		 370
371 switch (type) {
372 case ISCSI_BOOT_ETH_FLAGS:
373 case ISCSI_BOOT_ETH_MAC:
374 case ISCSI_BOOT_ETH_INDEX:
375 rc = S_IRUGO;
376 break;
377 default:
378 rc = 0;
379 break;
380 }
381 return rc;
382}
383
bfead3b2
JK		 384/*------------------- PCI Driver operations and data ----------------- */
385static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
386 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
f98c96b0 387 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
bfead3b2
JK		 388 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
389 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
390 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
bfead3b2
JK		 391 { 0 }
392};
393MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
394
6733b39a
JK		 395static struct scsi_host_template beiscsi_sht = {
396 .module = THIS_MODULE,
397 .name = "ServerEngines 10Gbe open-iscsi Initiator Driver",
398 .proc_name = DRV_NAME,
399 .queuecommand = iscsi_queuecommand,
6733b39a
JK		 400 .change_queue_depth = iscsi_change_queue_depth,
401 .slave_configure = beiscsi_slave_configure,
402 .target_alloc = iscsi_target_alloc,
4183122d
JK		 403 .eh_abort_handler = beiscsi_eh_abort,
404 .eh_device_reset_handler = beiscsi_eh_device_reset,
309ce156 405 .eh_target_reset_handler = iscsi_eh_session_reset,
6733b39a
JK		 406 .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
407 .can_queue = BE2_IO_DEPTH,
408 .this_id = -1,
409 .max_sectors = BEISCSI_MAX_SECTORS,
410 .cmd_per_lun = BEISCSI_CMD_PER_LUN,
411 .use_clustering = ENABLE_CLUSTERING,
412};
6733b39a 413
bfead3b2 414static struct scsi_transport_template *beiscsi_scsi_transport;
6733b39a
JK		 415
416static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
417{
418 struct beiscsi_hba *phba;
419 struct Scsi_Host *shost;
420
421 shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
422 if (!shost) {
423 dev_err(&pcidev->dev, "beiscsi_hba_alloc -"
457ff3b7 424 "iscsi_host_alloc failed\n");
6733b39a
JK		 425 return NULL;
426 }
427 shost->dma_boundary = pcidev->dma_mask;
428 shost->max_id = BE2_MAX_SESSIONS;
429 shost->max_channel = 0;
430 shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
431 shost->max_lun = BEISCSI_NUM_MAX_LUN;
432 shost->transportt = beiscsi_scsi_transport;
6733b39a
JK		 433 phba = iscsi_host_priv(shost);
434 memset(phba, 0, sizeof(*phba));
435 phba->shost = shost;
436 phba->pcidev = pci_dev_get(pcidev);
2807afb7 437 pci_set_drvdata(pcidev, phba);
6733b39a
JK		 438
439 if (iscsi_host_add(shost, &phba->pcidev->dev))
440 goto free_devices;
c7acc5b8 441
6733b39a
JK		 442 return phba;
443
444free_devices:
445 pci_dev_put(phba->pcidev);
446 iscsi_host_free(phba->shost);
447 return NULL;
448}
449
450static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
451{
452 if (phba->csr_va) {
453 iounmap(phba->csr_va);
454 phba->csr_va = NULL;
455 }
456 if (phba->db_va) {
457 iounmap(phba->db_va);
458 phba->db_va = NULL;
459 }
460 if (phba->pci_va) {
461 iounmap(phba->pci_va);
462 phba->pci_va = NULL;
463 }
464}
465
466static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
467 struct pci_dev *pcidev)
468{
469 u8 __iomem *addr;
f98c96b0 470 int pcicfg_reg;
6733b39a
JK		 471
472 addr = ioremap_nocache(pci_resource_start(pcidev, 2),
473 pci_resource_len(pcidev, 2));
474 if (addr == NULL)
475 return -ENOMEM;
476 phba->ctrl.csr = addr;
477 phba->csr_va = addr;
478 phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
479
480 addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
481 if (addr == NULL)
482 goto pci_map_err;
483 phba->ctrl.db = addr;
484 phba->db_va = addr;
485 phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
486
f98c96b0
JK		 487 if (phba->generation == BE_GEN2)
488 pcicfg_reg = 1;
489 else
490 pcicfg_reg = 0;
491
492 addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
493 pci_resource_len(pcidev, pcicfg_reg));
494
6733b39a
JK		 495 if (addr == NULL)
496 goto pci_map_err;
497 phba->ctrl.pcicfg = addr;
498 phba->pci_va = addr;
f98c96b0 499 phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
6733b39a
JK		 500 return 0;
501
502pci_map_err:
503 beiscsi_unmap_pci_function(phba);
504 return -ENOMEM;
505}
506
507static int beiscsi_enable_pci(struct pci_dev *pcidev)
508{
509 int ret;
510
511 ret = pci_enable_device(pcidev);
512 if (ret) {
513 dev_err(&pcidev->dev, "beiscsi_enable_pci - enable device "
514 "failed. Returning -ENODEV\n");
515 return ret;
516 }
517
bfead3b2 518 pci_set_master(pcidev);
6733b39a
JK		 519 if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
520 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
521 if (ret) {
522 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
523 pci_disable_device(pcidev);
524 return ret;
525 }
526 }
527 return 0;
528}
529
530static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
531{
532 struct be_ctrl_info *ctrl = &phba->ctrl;
533 struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
534 struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
535 int status = 0;
536
537 ctrl->pdev = pdev;
538 status = beiscsi_map_pci_bars(phba, pdev);
539 if (status)
540 return status;
6733b39a
JK		 541 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
542 mbox_mem_alloc->va = pci_alloc_consistent(pdev,
543 mbox_mem_alloc->size,
544 &mbox_mem_alloc->dma);
545 if (!mbox_mem_alloc->va) {
546 beiscsi_unmap_pci_function(phba);
547 status = -ENOMEM;
548 return status;
549 }
550
551 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
552 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
553 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
554 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
555 spin_lock_init(&ctrl->mbox_lock);
bfead3b2
JK		 556 spin_lock_init(&phba->ctrl.mcc_lock);
557 spin_lock_init(&phba->ctrl.mcc_cq_lock);
558
6733b39a
JK		 559 return status;
560}
561
562static void beiscsi_get_params(struct beiscsi_hba *phba)
563{
7da50879
JK		 564 phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
565 - (phba->fw_config.iscsi_cid_count
566 + BE2_TMFS
567 + BE2_NOPOUT_REQ));
568 phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
ed58ea2a 569 phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2;
6eab04a8 570 phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
6733b39a
JK		 571 phba->params.num_sge_per_io = BE2_SGE;
572 phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
573 phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
574 phba->params.eq_timer = 64;
575 phba->params.num_eq_entries =
7da50879
JK		 576 (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
577 + BE2_TMFS) / 512) + 1) * 512;
6733b39a
JK		 578 phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
579 ? 1024 : phba->params.num_eq_entries;
457ff3b7 580 SE_DEBUG(DBG_LVL_8, "phba->params.num_eq_entries=%d\n",
7da50879 581 phba->params.num_eq_entries);
6733b39a 582 phba->params.num_cq_entries =
7da50879
JK		 583 (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
584 + BE2_TMFS) / 512) + 1) * 512;
6733b39a
JK		 585 phba->params.wrbs_per_cxn = 256;
586}
587
588static void hwi_ring_eq_db(struct beiscsi_hba *phba,
589 unsigned int id, unsigned int clr_interrupt,
590 unsigned int num_processed,
591 unsigned char rearm, unsigned char event)
592{
593 u32 val = 0;
594 val |= id & DB_EQ_RING_ID_MASK;
595 if (rearm)
596 val |= 1 << DB_EQ_REARM_SHIFT;
597 if (clr_interrupt)
598 val |= 1 << DB_EQ_CLR_SHIFT;
599 if (event)
600 val |= 1 << DB_EQ_EVNT_SHIFT;
601 val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
602 iowrite32(val, phba->db_va + DB_EQ_OFFSET);
603}
604
bfead3b2
JK		 605/**
606 * be_isr_mcc - The isr routine of the driver.
607 * @irq: Not used
608 * @dev_id: Pointer to host adapter structure
609 */
610static irqreturn_t be_isr_mcc(int irq, void *dev_id)
611{
612 struct beiscsi_hba *phba;
613 struct be_eq_entry *eqe = NULL;
614 struct be_queue_info *eq;
615 struct be_queue_info *mcc;
616 unsigned int num_eq_processed;
617 struct be_eq_obj *pbe_eq;
618 unsigned long flags;
619
620 pbe_eq = dev_id;
621 eq = &pbe_eq->q;
622 phba = pbe_eq->phba;
623 mcc = &phba->ctrl.mcc_obj.cq;
624 eqe = queue_tail_node(eq);
625 if (!eqe)
626 SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
627
628 num_eq_processed = 0;
629
630 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
631 & EQE_VALID_MASK) {
632 if (((eqe->dw[offsetof(struct amap_eq_entry,
633 resource_id) / 32] &
634 EQE_RESID_MASK) >> 16) == mcc->id) {
635 spin_lock_irqsave(&phba->isr_lock, flags);
636 phba->todo_mcc_cq = 1;
637 spin_unlock_irqrestore(&phba->isr_lock, flags);
638 }
639 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
640 queue_tail_inc(eq);
641 eqe = queue_tail_node(eq);
642 num_eq_processed++;
643 }
644 if (phba->todo_mcc_cq)
645 queue_work(phba->wq, &phba->work_cqs);
646 if (num_eq_processed)
647 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
648
649 return IRQ_HANDLED;
650}
651
652/**
653 * be_isr_msix - The isr routine of the driver.
654 * @irq: Not used
655 * @dev_id: Pointer to host adapter structure
656 */
657static irqreturn_t be_isr_msix(int irq, void *dev_id)
658{
659 struct beiscsi_hba *phba;
660 struct be_eq_entry *eqe = NULL;
661 struct be_queue_info *eq;
662 struct be_queue_info *cq;
663 unsigned int num_eq_processed;
664 struct be_eq_obj *pbe_eq;
665 unsigned long flags;
666
667 pbe_eq = dev_id;
668 eq = &pbe_eq->q;
669 cq = pbe_eq->cq;
670 eqe = queue_tail_node(eq);
671 if (!eqe)
672 SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
673
674 phba = pbe_eq->phba;
675 num_eq_processed = 0;
676 if (blk_iopoll_enabled) {
677 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
678 & EQE_VALID_MASK) {
679 if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
680 blk_iopoll_sched(&pbe_eq->iopoll);
681
682 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
683 queue_tail_inc(eq);
684 eqe = queue_tail_node(eq);
685 num_eq_processed++;
686 }
687 if (num_eq_processed)
688 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
689
690 return IRQ_HANDLED;
691 } else {
692 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
693 & EQE_VALID_MASK) {
694 spin_lock_irqsave(&phba->isr_lock, flags);
695 phba->todo_cq = 1;
696 spin_unlock_irqrestore(&phba->isr_lock, flags);
697 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
698 queue_tail_inc(eq);
699 eqe = queue_tail_node(eq);
700 num_eq_processed++;
701 }
702 if (phba->todo_cq)
703 queue_work(phba->wq, &phba->work_cqs);
704
705 if (num_eq_processed)
706 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
707
708 return IRQ_HANDLED;
709 }
710}
711
6733b39a
JK		 712/**
713 * be_isr - The isr routine of the driver.
714 * @irq: Not used
715 * @dev_id: Pointer to host adapter structure
716 */
717static irqreturn_t be_isr(int irq, void *dev_id)
718{
719 struct beiscsi_hba *phba;
720 struct hwi_controller *phwi_ctrlr;
721 struct hwi_context_memory *phwi_context;
722 struct be_eq_entry *eqe = NULL;
723 struct be_queue_info *eq;
724 struct be_queue_info *cq;
bfead3b2 725 struct be_queue_info *mcc;
6733b39a 726 unsigned long flags, index;
bfead3b2 727 unsigned int num_mcceq_processed, num_ioeq_processed;
6733b39a 728 struct be_ctrl_info *ctrl;
bfead3b2 729 struct be_eq_obj *pbe_eq;
6733b39a
JK		 730 int isr;
731
732 phba = dev_id;
6eab04a8 733 ctrl = &phba->ctrl;
bfead3b2
JK		 734 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
735 (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
736 if (!isr)
737 return IRQ_NONE;
6733b39a
JK		 738
739 phwi_ctrlr = phba->phwi_ctrlr;
740 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 741 pbe_eq = &phwi_context->be_eq[0];
742
743 eq = &phwi_context->be_eq[0].q;
744 mcc = &phba->ctrl.mcc_obj.cq;
6733b39a
JK		 745 index = 0;
746 eqe = queue_tail_node(eq);
747 if (!eqe)
748 SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
749
bfead3b2
JK		 750 num_ioeq_processed = 0;
751 num_mcceq_processed = 0;
6733b39a
JK		 752 if (blk_iopoll_enabled) {
753 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
754 & EQE_VALID_MASK) {
bfead3b2
JK		 755 if (((eqe->dw[offsetof(struct amap_eq_entry,
756 resource_id) / 32] &
757 EQE_RESID_MASK) >> 16) == mcc->id) {
758 spin_lock_irqsave(&phba->isr_lock, flags);
759 phba->todo_mcc_cq = 1;
760 spin_unlock_irqrestore(&phba->isr_lock, flags);
761 num_mcceq_processed++;
762 } else {
763 if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
764 blk_iopoll_sched(&pbe_eq->iopoll);
765 num_ioeq_processed++;
766 }
6733b39a
JK		 767 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
768 queue_tail_inc(eq);
769 eqe = queue_tail_node(eq);
6733b39a 770 }
bfead3b2
JK		 771 if (num_ioeq_processed || num_mcceq_processed) {
772 if (phba->todo_mcc_cq)
773 queue_work(phba->wq, &phba->work_cqs);
774
756d29c8 775 if ((num_mcceq_processed) && (!num_ioeq_processed))
bfead3b2
JK		 776 hwi_ring_eq_db(phba, eq->id, 0,
777 (num_ioeq_processed +
778 num_mcceq_processed) , 1, 1);
779 else
780 hwi_ring_eq_db(phba, eq->id, 0,
781 (num_ioeq_processed +
782 num_mcceq_processed), 0, 1);
783
6733b39a
JK		 784 return IRQ_HANDLED;
785 } else
786 return IRQ_NONE;
787 } else {
bfead3b2 788 cq = &phwi_context->be_cq[0];
6733b39a
JK		 789 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
790 & EQE_VALID_MASK) {
791
792 if (((eqe->dw[offsetof(struct amap_eq_entry,
793 resource_id) / 32] &
794 EQE_RESID_MASK) >> 16) != cq->id) {
795 spin_lock_irqsave(&phba->isr_lock, flags);
796 phba->todo_mcc_cq = 1;
797 spin_unlock_irqrestore(&phba->isr_lock, flags);
798 } else {
799 spin_lock_irqsave(&phba->isr_lock, flags);
800 phba->todo_cq = 1;
801 spin_unlock_irqrestore(&phba->isr_lock, flags);
802 }
803 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
804 queue_tail_inc(eq);
805 eqe = queue_tail_node(eq);
bfead3b2 806 num_ioeq_processed++;
6733b39a
JK		 807 }
808 if (phba->todo_cq || phba->todo_mcc_cq)
809 queue_work(phba->wq, &phba->work_cqs);
810
bfead3b2
JK		 811 if (num_ioeq_processed) {
812 hwi_ring_eq_db(phba, eq->id, 0,
813 num_ioeq_processed, 1, 1);
6733b39a
JK		 814 return IRQ_HANDLED;
815 } else
816 return IRQ_NONE;
817 }
818}
819
820static int beiscsi_init_irqs(struct beiscsi_hba *phba)
821{
822 struct pci_dev *pcidev = phba->pcidev;
bfead3b2
JK		 823 struct hwi_controller *phwi_ctrlr;
824 struct hwi_context_memory *phwi_context;
4f5af07e 825 int ret, msix_vec, i, j;
6733b39a 826
bfead3b2
JK		 827 phwi_ctrlr = phba->phwi_ctrlr;
828 phwi_context = phwi_ctrlr->phwi_ctxt;
829
830 if (phba->msix_enabled) {
831 for (i = 0; i < phba->num_cpus; i++) {
8fcfb210
JK		 832 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
833 GFP_KERNEL);
834 if (!phba->msi_name[i]) {
835 ret = -ENOMEM;
836 goto free_msix_irqs;
837 }
838
839 sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
840 phba->shost->host_no, i);
bfead3b2 841 msix_vec = phba->msix_entries[i].vector;
8fcfb210
JK		 842 ret = request_irq(msix_vec, be_isr_msix, 0,
843 phba->msi_name[i],
bfead3b2 844 &phwi_context->be_eq[i]);
4f5af07e
JK		 845 if (ret) {
846 shost_printk(KERN_ERR, phba->shost,
847 "beiscsi_init_irqs-Failed to"
848 "register msix for i = %d\n", i);
8fcfb210 849 kfree(phba->msi_name[i]);
4f5af07e
JK		 850 goto free_msix_irqs;
851 }
bfead3b2 852 }
8fcfb210
JK		 853 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
854 if (!phba->msi_name[i]) {
855 ret = -ENOMEM;
856 goto free_msix_irqs;
857 }
858 sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
859 phba->shost->host_no);
bfead3b2 860 msix_vec = phba->msix_entries[i].vector;
8fcfb210 861 ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
bfead3b2 862 &phwi_context->be_eq[i]);
4f5af07e
JK		 863 if (ret) {
864 shost_printk(KERN_ERR, phba->shost, "beiscsi_init_irqs-"
865 "Failed to register beiscsi_msix_mcc\n");
8fcfb210 866 kfree(phba->msi_name[i]);
4f5af07e
JK		 867 goto free_msix_irqs;
868 }
869
bfead3b2
JK		 870 } else {
871 ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
872 "beiscsi", phba);
873 if (ret) {
874 shost_printk(KERN_ERR, phba->shost, "beiscsi_init_irqs-"
875 "Failed to register irq\\n");
876 return ret;
877 }
6733b39a
JK		 878 }
879 return 0;
4f5af07e 880free_msix_irqs:
8fcfb210
JK		 881 for (j = i - 1; j >= 0; j--) {
882 kfree(phba->msi_name[j]);
883 msix_vec = phba->msix_entries[j].vector;
4f5af07e 884 free_irq(msix_vec, &phwi_context->be_eq[j]);
8fcfb210 885 }
4f5af07e 886 return ret;
6733b39a
JK		 887}
888
889static void hwi_ring_cq_db(struct beiscsi_hba *phba,
890 unsigned int id, unsigned int num_processed,
891 unsigned char rearm, unsigned char event)
892{
893 u32 val = 0;
894 val |= id & DB_CQ_RING_ID_MASK;
895 if (rearm)
896 val |= 1 << DB_CQ_REARM_SHIFT;
897 val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
898 iowrite32(val, phba->db_va + DB_CQ_OFFSET);
899}
900
6733b39a
JK		 901static unsigned int
902beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
903 struct beiscsi_hba *phba,
904 unsigned short cid,
905 struct pdu_base *ppdu,
906 unsigned long pdu_len,
907 void *pbuffer, unsigned long buf_len)
908{
909 struct iscsi_conn *conn = beiscsi_conn->conn;
910 struct iscsi_session *session = conn->session;
bfead3b2
JK		 911 struct iscsi_task *task;
912 struct beiscsi_io_task *io_task;
913 struct iscsi_hdr *login_hdr;
6733b39a
JK		 914
915 switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
916 PDUBASE_OPCODE_MASK) {
917 case ISCSI_OP_NOOP_IN:
918 pbuffer = NULL;
919 buf_len = 0;
920 break;
921 case ISCSI_OP_ASYNC_EVENT:
922 break;
923 case ISCSI_OP_REJECT:
924 WARN_ON(!pbuffer);
925 WARN_ON(!(buf_len == 48));
926 SE_DEBUG(DBG_LVL_1, "In ISCSI_OP_REJECT\n");
927 break;
928 case ISCSI_OP_LOGIN_RSP:
7bd6e25c 929 case ISCSI_OP_TEXT_RSP:
bfead3b2
JK		 930 task = conn->login_task;
931 io_task = task->dd_data;
932 login_hdr = (struct iscsi_hdr *)ppdu;
933 login_hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 934 break;
935 default:
936 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 937 "Unrecognized opcode 0x%x in async msg\n",
6733b39a
JK		 938 (ppdu->
939 dw[offsetof(struct amap_pdu_base, opcode) / 32]
940 & PDUBASE_OPCODE_MASK));
941 return 1;
942 }
943
944 spin_lock_bh(&session->lock);
945 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
946 spin_unlock_bh(&session->lock);
947 return 0;
948}
949
950static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
951{
952 struct sgl_handle *psgl_handle;
953
954 if (phba->io_sgl_hndl_avbl) {
955 SE_DEBUG(DBG_LVL_8,
457ff3b7 956 "In alloc_io_sgl_handle,io_sgl_alloc_index=%d\n",
6733b39a
JK		 957 phba->io_sgl_alloc_index);
958 psgl_handle = phba->io_sgl_hndl_base[phba->
959 io_sgl_alloc_index];
960 phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
961 phba->io_sgl_hndl_avbl--;
bfead3b2
JK		 962 if (phba->io_sgl_alloc_index == (phba->params.
963 ios_per_ctrl - 1))
6733b39a
JK		 964 phba->io_sgl_alloc_index = 0;
965 else
966 phba->io_sgl_alloc_index++;
967 } else
968 psgl_handle = NULL;
969 return psgl_handle;
970}
971
972static void
973free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
974{
457ff3b7 975 SE_DEBUG(DBG_LVL_8, "In free_,io_sgl_free_index=%d\n",
6733b39a
JK		 976 phba->io_sgl_free_index);
977 if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
978 /*
979 * this can happen if clean_task is called on a task that
980 * failed in xmit_task or alloc_pdu.
981 */
982 SE_DEBUG(DBG_LVL_8,
983 "Double Free in IO SGL io_sgl_free_index=%d,"
457ff3b7 984 "value there=%p\n", phba->io_sgl_free_index,
6733b39a
JK		 985 phba->io_sgl_hndl_base[phba->io_sgl_free_index]);
986 return;
987 }
988 phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
989 phba->io_sgl_hndl_avbl++;
990 if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
991 phba->io_sgl_free_index = 0;
992 else
993 phba->io_sgl_free_index++;
994}
995
996/**
997 * alloc_wrb_handle - To allocate a wrb handle
998 * @phba: The hba pointer
999 * @cid: The cid to use for allocation
6733b39a
JK		 1000 *
1001 * This happens under session_lock until submission to chip
1002 */
d5431488 1003struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
6733b39a
JK		 1004{
1005 struct hwi_wrb_context *pwrb_context;
1006 struct hwi_controller *phwi_ctrlr;
d5431488 1007 struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
6733b39a
JK		 1008
1009 phwi_ctrlr = phba->phwi_ctrlr;
1010 pwrb_context = &phwi_ctrlr->wrb_context[cid];
d5431488 1011 if (pwrb_context->wrb_handles_available >= 2) {
bfead3b2
JK		 1012 pwrb_handle = pwrb_context->pwrb_handle_base[
1013 pwrb_context->alloc_index];
1014 pwrb_context->wrb_handles_available--;
bfead3b2
JK		 1015 if (pwrb_context->alloc_index ==
1016 (phba->params.wrbs_per_cxn - 1))
1017 pwrb_context->alloc_index = 0;
1018 else
1019 pwrb_context->alloc_index++;
d5431488
JK		 1020 pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
1021 pwrb_context->alloc_index];
1022 pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
bfead3b2
JK		 1023 } else
1024 pwrb_handle = NULL;
6733b39a
JK		 1025 return pwrb_handle;
1026}
1027
1028/**
1029 * free_wrb_handle - To free the wrb handle back to pool
1030 * @phba: The hba pointer
1031 * @pwrb_context: The context to free from
1032 * @pwrb_handle: The wrb_handle to free
1033 *
1034 * This happens under session_lock until submission to chip
1035 */
1036static void
1037free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
1038 struct wrb_handle *pwrb_handle)
1039{
32951dd8 1040 pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
bfead3b2
JK		 1041 pwrb_context->wrb_handles_available++;
1042 if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
1043 pwrb_context->free_index = 0;
1044 else
1045 pwrb_context->free_index++;
1046
6733b39a 1047 SE_DEBUG(DBG_LVL_8,
bfead3b2 1048 "FREE WRB: pwrb_handle=%p free_index=0x%x"
457ff3b7 1049 "wrb_handles_available=%d\n",
6733b39a 1050 pwrb_handle, pwrb_context->free_index,
bfead3b2 1051 pwrb_context->wrb_handles_available);
6733b39a
JK		 1052}
1053
1054static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
1055{
1056 struct sgl_handle *psgl_handle;
1057
1058 if (phba->eh_sgl_hndl_avbl) {
1059 psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
1060 phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
457ff3b7 1061 SE_DEBUG(DBG_LVL_8, "mgmt_sgl_alloc_index=%d=0x%x\n",
6733b39a
JK		 1062 phba->eh_sgl_alloc_index, phba->eh_sgl_alloc_index);
1063 phba->eh_sgl_hndl_avbl--;
1064 if (phba->eh_sgl_alloc_index ==
1065 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
1066 1))
1067 phba->eh_sgl_alloc_index = 0;
1068 else
1069 phba->eh_sgl_alloc_index++;
1070 } else
1071 psgl_handle = NULL;
1072 return psgl_handle;
1073}
1074
1075void
1076free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
1077{
1078
457ff3b7 1079 SE_DEBUG(DBG_LVL_8, "In free_mgmt_sgl_handle,eh_sgl_free_index=%d\n",
bfead3b2 1080 phba->eh_sgl_free_index);
6733b39a
JK		 1081 if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
1082 /*
1083 * this can happen if clean_task is called on a task that
1084 * failed in xmit_task or alloc_pdu.
1085 */
1086 SE_DEBUG(DBG_LVL_8,
457ff3b7 1087 "Double Free in eh SGL ,eh_sgl_free_index=%d\n",
6733b39a
JK		 1088 phba->eh_sgl_free_index);
1089 return;
1090 }
1091 phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
1092 phba->eh_sgl_hndl_avbl++;
1093 if (phba->eh_sgl_free_index ==
1094 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
1095 phba->eh_sgl_free_index = 0;
1096 else
1097 phba->eh_sgl_free_index++;
1098}
1099
1100static void
1101be_complete_io(struct beiscsi_conn *beiscsi_conn,
1102 struct iscsi_task *task, struct sol_cqe *psol)
1103{
1104 struct beiscsi_io_task *io_task = task->dd_data;
1105 struct be_status_bhs *sts_bhs =
1106 (struct be_status_bhs *)io_task->cmd_bhs;
1107 struct iscsi_conn *conn = beiscsi_conn->conn;
6733b39a
JK		 1108 unsigned char *sense;
1109 u32 resid = 0, exp_cmdsn, max_cmdsn;
1110 u8 rsp, status, flags;
1111
bfead3b2 1112 exp_cmdsn = (psol->
6733b39a
JK		 1113 dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
1114 & SOL_EXP_CMD_SN_MASK);
bfead3b2 1115 max_cmdsn = ((psol->
6733b39a
JK		 1116 dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
1117 & SOL_EXP_CMD_SN_MASK) +
1118 ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
1119 / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
1120 rsp = ((psol->dw[offsetof(struct amap_sol_cqe, i_resp) / 32]
1121 & SOL_RESP_MASK) >> 16);
1122 status = ((psol->dw[offsetof(struct amap_sol_cqe, i_sts) / 32]
1123 & SOL_STS_MASK) >> 8);
1124 flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
1125 & SOL_FLAGS_MASK) >> 24) | 0x80;
bd535451
JK		 1126 if (!task->sc) {
1127 if (io_task->scsi_cmnd)
1128 scsi_dma_unmap(io_task->scsi_cmnd);
6733b39a 1129
bd535451
JK		 1130 return;
1131 }
6733b39a
JK		 1132 task->sc->result = (DID_OK << 16) | status;
1133 if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
1134 task->sc->result = DID_ERROR << 16;
1135 goto unmap;
1136 }
1137
1138 /* bidi not initially supported */
1139 if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
1140 resid = (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) /
1141 32] & SOL_RES_CNT_MASK);
1142
1143 if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
1144 task->sc->result = DID_ERROR << 16;
1145
1146 if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
1147 scsi_set_resid(task->sc, resid);
1148 if (!status && (scsi_bufflen(task->sc) - resid <
1149 task->sc->underflow))
1150 task->sc->result = DID_ERROR << 16;
1151 }
1152 }
1153
1154 if (status == SAM_STAT_CHECK_CONDITION) {
4053a4be 1155 u16 sense_len;
bfead3b2 1156 unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
4053a4be 1157
6733b39a 1158 sense = sts_bhs->sense_info + sizeof(unsigned short);
4053a4be 1159 sense_len = be16_to_cpu(*slen);
6733b39a
JK		 1160 memcpy(task->sc->sense_buffer, sense,
1161 min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
1162 }
756d29c8 1163
6733b39a
JK		 1164 if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) {
1165 if (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
1166 & SOL_RES_CNT_MASK)
1167 conn->rxdata_octets += (psol->
bfead3b2
JK		 1168 dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
1169 & SOL_RES_CNT_MASK);
6733b39a
JK		 1170 }
1171unmap:
1172 scsi_dma_unmap(io_task->scsi_cmnd);
1173 iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
1174}
1175
1176static void
1177be_complete_logout(struct beiscsi_conn *beiscsi_conn,
1178 struct iscsi_task *task, struct sol_cqe *psol)
1179{
1180 struct iscsi_logout_rsp *hdr;
bfead3b2 1181 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1182 struct iscsi_conn *conn = beiscsi_conn->conn;
1183
1184 hdr = (struct iscsi_logout_rsp *)task->hdr;
7bd6e25c 1185 hdr->opcode = ISCSI_OP_LOGOUT_RSP;
6733b39a
JK		 1186 hdr->t2wait = 5;
1187 hdr->t2retain = 0;
1188 hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
1189 & SOL_FLAGS_MASK) >> 24) | 0x80;
1190 hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
1191 32] & SOL_RESP_MASK);
1192 hdr->exp_cmdsn = cpu_to_be32(psol->
1193 dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
1194 & SOL_EXP_CMD_SN_MASK);
1195 hdr->max_cmdsn = be32_to_cpu((psol->
1196 dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
1197 & SOL_EXP_CMD_SN_MASK) +
1198 ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
1199 / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
7bd6e25c
JK		 1200 hdr->dlength[0] = 0;
1201 hdr->dlength[1] = 0;
1202 hdr->dlength[2] = 0;
6733b39a 1203 hdr->hlength = 0;
bfead3b2 1204 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1205 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1206}
1207
1208static void
1209be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
1210 struct iscsi_task *task, struct sol_cqe *psol)
1211{
1212 struct iscsi_tm_rsp *hdr;
1213 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1214 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1215
1216 hdr = (struct iscsi_tm_rsp *)task->hdr;
7bd6e25c 1217 hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
6733b39a
JK		 1218 hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
1219 & SOL_FLAGS_MASK) >> 24) | 0x80;
1220 hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
1221 32] & SOL_RESP_MASK);
1222 hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
bfead3b2 1223 i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
6733b39a
JK		 1224 hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
1225 i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
1226 ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
1227 / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
bfead3b2 1228 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1229 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1230}
1231
1232static void
1233hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
1234 struct beiscsi_hba *phba, struct sol_cqe *psol)
1235{
1236 struct hwi_wrb_context *pwrb_context;
bfead3b2 1237 struct wrb_handle *pwrb_handle = NULL;
6733b39a 1238 struct hwi_controller *phwi_ctrlr;
bfead3b2
JK		 1239 struct iscsi_task *task;
1240 struct beiscsi_io_task *io_task;
6733b39a
JK		 1241 struct iscsi_conn *conn = beiscsi_conn->conn;
1242 struct iscsi_session *session = conn->session;
1243
1244 phwi_ctrlr = phba->phwi_ctrlr;
32951dd8 1245 pwrb_context = &phwi_ctrlr->wrb_context[((psol->
35e66019 1246 dw[offsetof(struct amap_sol_cqe, cid) / 32] &
7da50879
JK		 1247 SOL_CID_MASK) >> 6) -
1248 phba->fw_config.iscsi_cid_start];
32951dd8 1249 pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
35e66019
JK		 1250 dw[offsetof(struct amap_sol_cqe, wrb_index) /
1251 32] & SOL_WRB_INDEX_MASK) >> 16)];
32951dd8 1252 task = pwrb_handle->pio_handle;
35e66019 1253
bfead3b2 1254 io_task = task->dd_data;
1282ab76 1255 spin_lock_bh(&phba->mgmt_sgl_lock);
bfead3b2 1256 free_mgmt_sgl_handle(phba, io_task->psgl_handle);
1282ab76 1257 spin_unlock_bh(&phba->mgmt_sgl_lock);
6733b39a
JK		 1258 spin_lock_bh(&session->lock);
1259 free_wrb_handle(phba, pwrb_context, pwrb_handle);
1260 spin_unlock_bh(&session->lock);
1261}
1262
1263static void
1264be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
1265 struct iscsi_task *task, struct sol_cqe *psol)
1266{
1267 struct iscsi_nopin *hdr;
1268 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1269 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1270
1271 hdr = (struct iscsi_nopin *)task->hdr;
1272 hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
1273 & SOL_FLAGS_MASK) >> 24) | 0x80;
1274 hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
1275 i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
1276 hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
1277 i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
1278 ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
1279 / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
1280 hdr->opcode = ISCSI_OP_NOOP_IN;
bfead3b2 1281 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1282 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1283}
1284
1285static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
1286 struct beiscsi_hba *phba, struct sol_cqe *psol)
1287{
1288 struct hwi_wrb_context *pwrb_context;
1289 struct wrb_handle *pwrb_handle;
1290 struct iscsi_wrb *pwrb = NULL;
1291 struct hwi_controller *phwi_ctrlr;
1292 struct iscsi_task *task;
bfead3b2 1293 unsigned int type;
6733b39a
JK		 1294 struct iscsi_conn *conn = beiscsi_conn->conn;
1295 struct iscsi_session *session = conn->session;
1296
1297 phwi_ctrlr = phba->phwi_ctrlr;
32951dd8 1298 pwrb_context = &phwi_ctrlr->wrb_context[((psol->dw[offsetof
35e66019 1299 (struct amap_sol_cqe, cid) / 32]
7da50879
JK		 1300 & SOL_CID_MASK) >> 6) -
1301 phba->fw_config.iscsi_cid_start];
32951dd8 1302 pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
35e66019
JK		 1303 dw[offsetof(struct amap_sol_cqe, wrb_index) /
1304 32] & SOL_WRB_INDEX_MASK) >> 16)];
32951dd8
JK		 1305 task = pwrb_handle->pio_handle;
1306 pwrb = pwrb_handle->pwrb;
1307 type = (pwrb->dw[offsetof(struct amap_iscsi_wrb, type) / 32] &
1308 WRB_TYPE_MASK) >> 28;
1309
bfead3b2
JK		 1310 spin_lock_bh(&session->lock);
1311 switch (type) {
6733b39a
JK		 1312 case HWH_TYPE_IO:
1313 case HWH_TYPE_IO_RD:
1314 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
dafab8e0 1315 ISCSI_OP_NOOP_OUT)
6733b39a 1316 be_complete_nopin_resp(beiscsi_conn, task, psol);
dafab8e0 1317 else
6733b39a
JK		 1318 be_complete_io(beiscsi_conn, task, psol);
1319 break;
1320
1321 case HWH_TYPE_LOGOUT:
dafab8e0
JK		 1322 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
1323 be_complete_logout(beiscsi_conn, task, psol);
1324 else
1325 be_complete_tmf(beiscsi_conn, task, psol);
1326
6733b39a
JK		 1327 break;
1328
1329 case HWH_TYPE_LOGIN:
1330 SE_DEBUG(DBG_LVL_1,
1331 "\t\t No HWH_TYPE_LOGIN Expected in hwi_complete_cmd"
457ff3b7 1332 "- Solicited path\n");
6733b39a
JK		 1333 break;
1334
6733b39a
JK		 1335 case HWH_TYPE_NOP:
1336 be_complete_nopin_resp(beiscsi_conn, task, psol);
1337 break;
1338
1339 default:
32951dd8 1340 shost_printk(KERN_WARNING, phba->shost,
35e66019
JK		 1341 "In hwi_complete_cmd, unknown type = %d"
1342 "wrb_index 0x%x CID 0x%x\n", type,
1343 ((psol->dw[offsetof(struct amap_iscsi_wrb,
1344 type) / 32] & SOL_WRB_INDEX_MASK) >> 16),
1345 ((psol->dw[offsetof(struct amap_sol_cqe,
1346 cid) / 32] & SOL_CID_MASK) >> 6));
6733b39a
JK		 1347 break;
1348 }
35e66019 1349
6733b39a
JK		 1350 spin_unlock_bh(&session->lock);
1351}
1352
1353static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
1354 *pasync_ctx, unsigned int is_header,
1355 unsigned int host_write_ptr)
1356{
1357 if (is_header)
1358 return &pasync_ctx->async_entry[host_write_ptr].
1359 header_busy_list;
1360 else
1361 return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
1362}
1363
1364static struct async_pdu_handle *
1365hwi_get_async_handle(struct beiscsi_hba *phba,
1366 struct beiscsi_conn *beiscsi_conn,
1367 struct hwi_async_pdu_context *pasync_ctx,
1368 struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
1369{
1370 struct be_bus_address phys_addr;
1371 struct list_head *pbusy_list;
1372 struct async_pdu_handle *pasync_handle = NULL;
6733b39a
JK		 1373 unsigned char is_header = 0;
1374
1375 phys_addr.u.a32.address_lo =
1376 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_lo) / 32] -
1377 ((pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
1378 & PDUCQE_DPL_MASK) >> 16);
1379 phys_addr.u.a32.address_hi =
1380 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_hi) / 32];
1381
1382 phys_addr.u.a64.address =
1383 *((unsigned long long *)(&phys_addr.u.a64.address));
1384
1385 switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
1386 & PDUCQE_CODE_MASK) {
1387 case UNSOL_HDR_NOTIFY:
1388 is_header = 1;
1389
1390 pbusy_list = hwi_get_async_busy_list(pasync_ctx, 1,
1391 (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1392 index) / 32] & PDUCQE_INDEX_MASK));
6733b39a
JK		 1393 break;
1394 case UNSOL_DATA_NOTIFY:
1395 pbusy_list = hwi_get_async_busy_list(pasync_ctx, 0, (pdpdu_cqe->
1396 dw[offsetof(struct amap_i_t_dpdu_cqe,
1397 index) / 32] & PDUCQE_INDEX_MASK));
6733b39a
JK		 1398 break;
1399 default:
1400 pbusy_list = NULL;
1401 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 1402 "Unexpected code=%d\n",
6733b39a
JK		 1403 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1404 code) / 32] & PDUCQE_CODE_MASK);
1405 return NULL;
1406 }
1407
6733b39a
JK		 1408 WARN_ON(list_empty(pbusy_list));
1409 list_for_each_entry(pasync_handle, pbusy_list, link) {
dc63aac6 1410 if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
6733b39a
JK		 1411 break;
1412 }
1413
1414 WARN_ON(!pasync_handle);
1415
7da50879
JK		 1416 pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid -
1417 phba->fw_config.iscsi_cid_start;
6733b39a
JK		 1418 pasync_handle->is_header = is_header;
1419 pasync_handle->buffer_len = ((pdpdu_cqe->
1420 dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
1421 & PDUCQE_DPL_MASK) >> 16);
1422
1423 *pcq_index = (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1424 index) / 32] & PDUCQE_INDEX_MASK);
1425 return pasync_handle;
1426}
1427
1428static unsigned int
1429hwi_update_async_writables(struct hwi_async_pdu_context *pasync_ctx,
1430 unsigned int is_header, unsigned int cq_index)
1431{
1432 struct list_head *pbusy_list;
1433 struct async_pdu_handle *pasync_handle;
1434 unsigned int num_entries, writables = 0;
1435 unsigned int *pep_read_ptr, *pwritables;
1436
dc63aac6 1437 num_entries = pasync_ctx->num_entries;
6733b39a
JK		 1438 if (is_header) {
1439 pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
1440 pwritables = &pasync_ctx->async_header.writables;
6733b39a
JK		 1441 } else {
1442 pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
1443 pwritables = &pasync_ctx->async_data.writables;
6733b39a
JK		 1444 }
1445
1446 while ((*pep_read_ptr) != cq_index) {
1447 (*pep_read_ptr)++;
1448 *pep_read_ptr = (*pep_read_ptr) % num_entries;
1449
1450 pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
1451 *pep_read_ptr);
1452 if (writables == 0)
1453 WARN_ON(list_empty(pbusy_list));
1454
1455 if (!list_empty(pbusy_list)) {
1456 pasync_handle = list_entry(pbusy_list->next,
1457 struct async_pdu_handle,
1458 link);
1459 WARN_ON(!pasync_handle);
1460 pasync_handle->consumed = 1;
1461 }
1462
1463 writables++;
1464 }
1465
1466 if (!writables) {
1467 SE_DEBUG(DBG_LVL_1,
1468 "Duplicate notification received - index 0x%x!!\n",
1469 cq_index);
1470 WARN_ON(1);
1471 }
1472
1473 *pwritables = *pwritables + writables;
1474 return 0;
1475}
1476
1477static unsigned int hwi_free_async_msg(struct beiscsi_hba *phba,
1478 unsigned int cri)
1479{
1480 struct hwi_controller *phwi_ctrlr;
1481 struct hwi_async_pdu_context *pasync_ctx;
1482 struct async_pdu_handle *pasync_handle, *tmp_handle;
1483 struct list_head *plist;
1484 unsigned int i = 0;
1485
1486 phwi_ctrlr = phba->phwi_ctrlr;
1487 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
1488
1489 plist = &pasync_ctx->async_entry[cri].wait_queue.list;
1490
1491 list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
1492 list_del(&pasync_handle->link);
1493
1494 if (i == 0) {
1495 list_add_tail(&pasync_handle->link,
1496 &pasync_ctx->async_header.free_list);
1497 pasync_ctx->async_header.free_entries++;
1498 i++;
1499 } else {
1500 list_add_tail(&pasync_handle->link,
1501 &pasync_ctx->async_data.free_list);
1502 pasync_ctx->async_data.free_entries++;
1503 i++;
1504 }
1505 }
1506
1507 INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
1508 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
1509 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
1510 return 0;
1511}
1512
1513static struct phys_addr *
1514hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
1515 unsigned int is_header, unsigned int host_write_ptr)
1516{
1517 struct phys_addr *pasync_sge = NULL;
1518
1519 if (is_header)
1520 pasync_sge = pasync_ctx->async_header.ring_base;
1521 else
1522 pasync_sge = pasync_ctx->async_data.ring_base;
1523
1524 return pasync_sge + host_write_ptr;
1525}
1526
1527static void hwi_post_async_buffers(struct beiscsi_hba *phba,
1528 unsigned int is_header)
1529{
1530 struct hwi_controller *phwi_ctrlr;
1531 struct hwi_async_pdu_context *pasync_ctx;
1532 struct async_pdu_handle *pasync_handle;
1533 struct list_head *pfree_link, *pbusy_list;
1534 struct phys_addr *pasync_sge;
1535 unsigned int ring_id, num_entries;
1536 unsigned int host_write_num;
1537 unsigned int writables;
1538 unsigned int i = 0;
1539 u32 doorbell = 0;
1540
1541 phwi_ctrlr = phba->phwi_ctrlr;
1542 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
dc63aac6 1543 num_entries = pasync_ctx->num_entries;
6733b39a
JK		 1544
1545 if (is_header) {
6733b39a
JK		 1546 writables = min(pasync_ctx->async_header.writables,
1547 pasync_ctx->async_header.free_entries);
1548 pfree_link = pasync_ctx->async_header.free_list.next;
1549 host_write_num = pasync_ctx->async_header.host_write_ptr;
1550 ring_id = phwi_ctrlr->default_pdu_hdr.id;
1551 } else {
6733b39a
JK		 1552 writables = min(pasync_ctx->async_data.writables,
1553 pasync_ctx->async_data.free_entries);
1554 pfree_link = pasync_ctx->async_data.free_list.next;
1555 host_write_num = pasync_ctx->async_data.host_write_ptr;
1556 ring_id = phwi_ctrlr->default_pdu_data.id;
1557 }
1558
1559 writables = (writables / 8) * 8;
1560 if (writables) {
1561 for (i = 0; i < writables; i++) {
1562 pbusy_list =
1563 hwi_get_async_busy_list(pasync_ctx, is_header,
1564 host_write_num);
1565 pasync_handle =
1566 list_entry(pfree_link, struct async_pdu_handle,
1567 link);
1568 WARN_ON(!pasync_handle);
1569 pasync_handle->consumed = 0;
1570
1571 pfree_link = pfree_link->next;
1572
1573 pasync_sge = hwi_get_ring_address(pasync_ctx,
1574 is_header, host_write_num);
1575
1576 pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
1577 pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
1578
1579 list_move(&pasync_handle->link, pbusy_list);
1580
1581 host_write_num++;
1582 host_write_num = host_write_num % num_entries;
1583 }
1584
1585 if (is_header) {
1586 pasync_ctx->async_header.host_write_ptr =
1587 host_write_num;
1588 pasync_ctx->async_header.free_entries -= writables;
1589 pasync_ctx->async_header.writables -= writables;
1590 pasync_ctx->async_header.busy_entries += writables;
1591 } else {
1592 pasync_ctx->async_data.host_write_ptr = host_write_num;
1593 pasync_ctx->async_data.free_entries -= writables;
1594 pasync_ctx->async_data.writables -= writables;
1595 pasync_ctx->async_data.busy_entries += writables;
1596 }
1597
1598 doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
1599 doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
1600 doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
1601 doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
1602 << DB_DEF_PDU_CQPROC_SHIFT;
1603
1604 iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
1605 }
1606}
1607
1608static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
1609 struct beiscsi_conn *beiscsi_conn,
1610 struct i_t_dpdu_cqe *pdpdu_cqe)
1611{
1612 struct hwi_controller *phwi_ctrlr;
1613 struct hwi_async_pdu_context *pasync_ctx;
1614 struct async_pdu_handle *pasync_handle = NULL;
1615 unsigned int cq_index = -1;
1616
1617 phwi_ctrlr = phba->phwi_ctrlr;
1618 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
1619
1620 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
1621 pdpdu_cqe, &cq_index);
1622 BUG_ON(pasync_handle->is_header != 0);
1623 if (pasync_handle->consumed == 0)
1624 hwi_update_async_writables(pasync_ctx, pasync_handle->is_header,
1625 cq_index);
1626
1627 hwi_free_async_msg(phba, pasync_handle->cri);
1628 hwi_post_async_buffers(phba, pasync_handle->is_header);
1629}
1630
1631static unsigned int
1632hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
1633 struct beiscsi_hba *phba,
1634 struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
1635{
1636 struct list_head *plist;
1637 struct async_pdu_handle *pasync_handle;
1638 void *phdr = NULL;
1639 unsigned int hdr_len = 0, buf_len = 0;
1640 unsigned int status, index = 0, offset = 0;
1641 void *pfirst_buffer = NULL;
1642 unsigned int num_buf = 0;
1643
1644 plist = &pasync_ctx->async_entry[cri].wait_queue.list;
1645
1646 list_for_each_entry(pasync_handle, plist, link) {
1647 if (index == 0) {
1648 phdr = pasync_handle->pbuffer;
1649 hdr_len = pasync_handle->buffer_len;
1650 } else {
1651 buf_len = pasync_handle->buffer_len;
1652 if (!num_buf) {
1653 pfirst_buffer = pasync_handle->pbuffer;
1654 num_buf++;
1655 }
1656 memcpy(pfirst_buffer + offset,
1657 pasync_handle->pbuffer, buf_len);
f2ba02b8 1658 offset += buf_len;
6733b39a
JK		 1659 }
1660 index++;
1661 }
1662
1663 status = beiscsi_process_async_pdu(beiscsi_conn, phba,
7da50879
JK		 1664 (beiscsi_conn->beiscsi_conn_cid -
1665 phba->fw_config.iscsi_cid_start),
1666 phdr, hdr_len, pfirst_buffer,
f2ba02b8 1667 offset);
6733b39a
JK		 1668
1669 if (status == 0)
1670 hwi_free_async_msg(phba, cri);
1671 return 0;
1672}
1673
1674static unsigned int
1675hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
1676 struct beiscsi_hba *phba,
1677 struct async_pdu_handle *pasync_handle)
1678{
1679 struct hwi_async_pdu_context *pasync_ctx;
1680 struct hwi_controller *phwi_ctrlr;
1681 unsigned int bytes_needed = 0, status = 0;
1682 unsigned short cri = pasync_handle->cri;
1683 struct pdu_base *ppdu;
1684
1685 phwi_ctrlr = phba->phwi_ctrlr;
1686 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
1687
1688 list_del(&pasync_handle->link);
1689 if (pasync_handle->is_header) {
1690 pasync_ctx->async_header.busy_entries--;
1691 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
1692 hwi_free_async_msg(phba, cri);
1693 BUG();
1694 }
1695
1696 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
1697 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
1698 pasync_ctx->async_entry[cri].wait_queue.hdr_len =
1699 (unsigned short)pasync_handle->buffer_len;
1700 list_add_tail(&pasync_handle->link,
1701 &pasync_ctx->async_entry[cri].wait_queue.list);
1702
1703 ppdu = pasync_handle->pbuffer;
1704 bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
1705 data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
1706 0xFFFF0000) | ((be16_to_cpu((ppdu->
1707 dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
1708 & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
1709
1710 if (status == 0) {
1711 pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
1712 bytes_needed;
1713
1714 if (bytes_needed == 0)
1715 status = hwi_fwd_async_msg(beiscsi_conn, phba,
1716 pasync_ctx, cri);
1717 }
1718 } else {
1719 pasync_ctx->async_data.busy_entries--;
1720 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
1721 list_add_tail(&pasync_handle->link,
1722 &pasync_ctx->async_entry[cri].wait_queue.
1723 list);
1724 pasync_ctx->async_entry[cri].wait_queue.
1725 bytes_received +=
1726 (unsigned short)pasync_handle->buffer_len;
1727
1728 if (pasync_ctx->async_entry[cri].wait_queue.
1729 bytes_received >=
1730 pasync_ctx->async_entry[cri].wait_queue.
1731 bytes_needed)
1732 status = hwi_fwd_async_msg(beiscsi_conn, phba,
1733 pasync_ctx, cri);
1734 }
1735 }
1736 return status;
1737}
1738
1739static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
1740 struct beiscsi_hba *phba,
1741 struct i_t_dpdu_cqe *pdpdu_cqe)
1742{
1743 struct hwi_controller *phwi_ctrlr;
1744 struct hwi_async_pdu_context *pasync_ctx;
1745 struct async_pdu_handle *pasync_handle = NULL;
1746 unsigned int cq_index = -1;
1747
1748 phwi_ctrlr = phba->phwi_ctrlr;
1749 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
1750 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
1751 pdpdu_cqe, &cq_index);
1752
1753 if (pasync_handle->consumed == 0)
1754 hwi_update_async_writables(pasync_ctx, pasync_handle->is_header,
1755 cq_index);
1756 hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
1757 hwi_post_async_buffers(phba, pasync_handle->is_header);
1758}
1759
756d29c8
JK		 1760static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
1761{
1762 struct be_queue_info *mcc_cq;
1763 struct be_mcc_compl *mcc_compl;
1764 unsigned int num_processed = 0;
1765
1766 mcc_cq = &phba->ctrl.mcc_obj.cq;
1767 mcc_compl = queue_tail_node(mcc_cq);
1768 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
1769 while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
1770
1771 if (num_processed >= 32) {
1772 hwi_ring_cq_db(phba, mcc_cq->id,
1773 num_processed, 0, 0);
1774 num_processed = 0;
1775 }
1776 if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
1777 /* Interpret flags as an async trailer */
1778 if (is_link_state_evt(mcc_compl->flags))
1779 /* Interpret compl as a async link evt */
1780 beiscsi_async_link_state_process(phba,
1781 (struct be_async_event_link_state *) mcc_compl);
1782 else
1783 SE_DEBUG(DBG_LVL_1,
1784 " Unsupported Async Event, flags"
457ff3b7 1785 " = 0x%08x\n", mcc_compl->flags);
756d29c8
JK		 1786 } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
1787 be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
1788 atomic_dec(&phba->ctrl.mcc_obj.q.used);
1789 }
1790
1791 mcc_compl->flags = 0;
1792 queue_tail_inc(mcc_cq);
1793 mcc_compl = queue_tail_node(mcc_cq);
1794 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
1795 num_processed++;
1796 }
1797
1798 if (num_processed > 0)
1799 hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
1800
1801}
bfead3b2
JK		 1802
1803static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
6733b39a 1804{
6733b39a
JK		 1805 struct be_queue_info *cq;
1806 struct sol_cqe *sol;
1807 struct dmsg_cqe *dmsg;
1808 unsigned int num_processed = 0;
1809 unsigned int tot_nump = 0;
1810 struct beiscsi_conn *beiscsi_conn;
c2462288
JK		 1811 struct beiscsi_endpoint *beiscsi_ep;
1812 struct iscsi_endpoint *ep;
bfead3b2 1813 struct beiscsi_hba *phba;
6733b39a 1814
bfead3b2 1815 cq = pbe_eq->cq;
6733b39a 1816 sol = queue_tail_node(cq);
bfead3b2 1817 phba = pbe_eq->phba;
6733b39a
JK		 1818
1819 while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
1820 CQE_VALID_MASK) {
1821 be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
1822
32951dd8 1823 ep = phba->ep_array[(u32) ((sol->
c2462288
JK		 1824 dw[offsetof(struct amap_sol_cqe, cid) / 32] &
1825 SOL_CID_MASK) >> 6) -
7da50879 1826 phba->fw_config.iscsi_cid_start];
32951dd8 1827
c2462288
JK		 1828 beiscsi_ep = ep->dd_data;
1829 beiscsi_conn = beiscsi_ep->conn;
756d29c8 1830
6733b39a 1831 if (num_processed >= 32) {
bfead3b2 1832 hwi_ring_cq_db(phba, cq->id,
6733b39a
JK		 1833 num_processed, 0, 0);
1834 tot_nump += num_processed;
1835 num_processed = 0;
1836 }
1837
1838 switch ((u32) sol->dw[offsetof(struct amap_sol_cqe, code) /
1839 32] & CQE_CODE_MASK) {
1840 case SOL_CMD_COMPLETE:
1841 hwi_complete_cmd(beiscsi_conn, phba, sol);
1842 break;
1843 case DRIVERMSG_NOTIFY:
457ff3b7 1844 SE_DEBUG(DBG_LVL_8, "Received DRIVERMSG_NOTIFY\n");
6733b39a
JK		 1845 dmsg = (struct dmsg_cqe *)sol;
1846 hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
1847 break;
1848 case UNSOL_HDR_NOTIFY:
bfead3b2
JK		 1849 SE_DEBUG(DBG_LVL_8, "Received UNSOL_HDR_ NOTIFY\n");
1850 hwi_process_default_pdu_ring(beiscsi_conn, phba,
1851 (struct i_t_dpdu_cqe *)sol);
1852 break;
6733b39a 1853 case UNSOL_DATA_NOTIFY:
bfead3b2 1854 SE_DEBUG(DBG_LVL_8, "Received UNSOL_DATA_NOTIFY\n");
6733b39a
JK		 1855 hwi_process_default_pdu_ring(beiscsi_conn, phba,
1856 (struct i_t_dpdu_cqe *)sol);
1857 break;
1858 case CXN_INVALIDATE_INDEX_NOTIFY:
1859 case CMD_INVALIDATED_NOTIFY:
1860 case CXN_INVALIDATE_NOTIFY:
1861 SE_DEBUG(DBG_LVL_1,
1862 "Ignoring CQ Error notification for cmd/cxn"
1863 "invalidate\n");
1864 break;
1865 case SOL_CMD_KILLED_DATA_DIGEST_ERR:
1866 case CMD_KILLED_INVALID_STATSN_RCVD:
1867 case CMD_KILLED_INVALID_R2T_RCVD:
1868 case CMD_CXN_KILLED_LUN_INVALID:
1869 case CMD_CXN_KILLED_ICD_INVALID:
1870 case CMD_CXN_KILLED_ITT_INVALID:
1871 case CMD_CXN_KILLED_SEQ_OUTOFORDER:
1872 case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
32951dd8 1873 SE_DEBUG(DBG_LVL_1,
6733b39a
JK		 1874 "CQ Error notification for cmd.. "
1875 "code %d cid 0x%x\n",
1876 sol->dw[offsetof(struct amap_sol_cqe, code) /
1877 32] & CQE_CODE_MASK,
1878 (sol->dw[offsetof(struct amap_sol_cqe, cid) /
1879 32] & SOL_CID_MASK));
1880 break;
1881 case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
1882 SE_DEBUG(DBG_LVL_1,
1883 "Digest error on def pdu ring, dropping..\n");
1884 hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
1885 (struct i_t_dpdu_cqe *) sol);
1886 break;
1887 case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
1888 case CXN_KILLED_BURST_LEN_MISMATCH:
1889 case CXN_KILLED_AHS_RCVD:
1890 case CXN_KILLED_HDR_DIGEST_ERR:
1891 case CXN_KILLED_UNKNOWN_HDR:
1892 case CXN_KILLED_STALE_ITT_TTT_RCVD:
1893 case CXN_KILLED_INVALID_ITT_TTT_RCVD:
1894 case CXN_KILLED_TIMED_OUT:
1895 case CXN_KILLED_FIN_RCVD:
1896 case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
1897 case CXN_KILLED_BAD_WRB_INDEX_ERROR:
1898 case CXN_KILLED_OVER_RUN_RESIDUAL:
1899 case CXN_KILLED_UNDER_RUN_RESIDUAL:
1900 case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
32951dd8 1901 SE_DEBUG(DBG_LVL_1, "CQ Error %d, reset CID "
6733b39a
JK		 1902 "0x%x...\n",
1903 sol->dw[offsetof(struct amap_sol_cqe, code) /
1904 32] & CQE_CODE_MASK,
7da50879
JK		 1905 (sol->dw[offsetof(struct amap_sol_cqe, cid) /
1906 32] & CQE_CID_MASK));
6733b39a
JK		 1907 iscsi_conn_failure(beiscsi_conn->conn,
1908 ISCSI_ERR_CONN_FAILED);
1909 break;
1910 case CXN_KILLED_RST_SENT:
1911 case CXN_KILLED_RST_RCVD:
32951dd8 1912 SE_DEBUG(DBG_LVL_1, "CQ Error %d, reset"
bfead3b2 1913 "received/sent on CID 0x%x...\n",
6733b39a
JK		 1914 sol->dw[offsetof(struct amap_sol_cqe, code) /
1915 32] & CQE_CODE_MASK,
7da50879
JK		 1916 (sol->dw[offsetof(struct amap_sol_cqe, cid) /
1917 32] & CQE_CID_MASK));
6733b39a
JK		 1918 iscsi_conn_failure(beiscsi_conn->conn,
1919 ISCSI_ERR_CONN_FAILED);
1920 break;
1921 default:
1922 SE_DEBUG(DBG_LVL_1, "CQ Error Invalid code= %d "
1923 "received on CID 0x%x...\n",
1924 sol->dw[offsetof(struct amap_sol_cqe, code) /
1925 32] & CQE_CODE_MASK,
7da50879
JK		 1926 (sol->dw[offsetof(struct amap_sol_cqe, cid) /
1927 32] & CQE_CID_MASK));
6733b39a
JK		 1928 break;
1929 }
1930
1931 AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
1932 queue_tail_inc(cq);
1933 sol = queue_tail_node(cq);
1934 num_processed++;
1935 }
1936
1937 if (num_processed > 0) {
1938 tot_nump += num_processed;
bfead3b2 1939 hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
6733b39a
JK		 1940 }
1941 return tot_nump;
1942}
1943
756d29c8 1944void beiscsi_process_all_cqs(struct work_struct *work)
6733b39a
JK		 1945{
1946 unsigned long flags;
bfead3b2
JK		 1947 struct hwi_controller *phwi_ctrlr;
1948 struct hwi_context_memory *phwi_context;
1949 struct be_eq_obj *pbe_eq;
6733b39a
JK		 1950 struct beiscsi_hba *phba =
1951 container_of(work, struct beiscsi_hba, work_cqs);
1952
bfead3b2
JK		 1953 phwi_ctrlr = phba->phwi_ctrlr;
1954 phwi_context = phwi_ctrlr->phwi_ctxt;
1955 if (phba->msix_enabled)
1956 pbe_eq = &phwi_context->be_eq[phba->num_cpus];
1957 else
1958 pbe_eq = &phwi_context->be_eq[0];
1959
6733b39a
JK		 1960 if (phba->todo_mcc_cq) {
1961 spin_lock_irqsave(&phba->isr_lock, flags);
1962 phba->todo_mcc_cq = 0;
1963 spin_unlock_irqrestore(&phba->isr_lock, flags);
756d29c8 1964 beiscsi_process_mcc_isr(phba);
6733b39a
JK		 1965 }
1966
1967 if (phba->todo_cq) {
1968 spin_lock_irqsave(&phba->isr_lock, flags);
1969 phba->todo_cq = 0;
1970 spin_unlock_irqrestore(&phba->isr_lock, flags);
bfead3b2 1971 beiscsi_process_cq(pbe_eq);
6733b39a
JK		 1972 }
1973}
1974
1975static int be_iopoll(struct blk_iopoll *iop, int budget)
1976{
1977 static unsigned int ret;
1978 struct beiscsi_hba *phba;
bfead3b2 1979 struct be_eq_obj *pbe_eq;
6733b39a 1980
bfead3b2
JK		 1981 pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
1982 ret = beiscsi_process_cq(pbe_eq);
6733b39a 1983 if (ret < budget) {
bfead3b2 1984 phba = pbe_eq->phba;
6733b39a 1985 blk_iopoll_complete(iop);
bfead3b2
JK		 1986 SE_DEBUG(DBG_LVL_8, "rearm pbe_eq->q.id =%d\n", pbe_eq->q.id);
1987 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
6733b39a
JK		 1988 }
1989 return ret;
1990}
1991
1992static void
1993hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
1994 unsigned int num_sg, struct beiscsi_io_task *io_task)
1995{
1996 struct iscsi_sge *psgl;
58ff4bd0 1997 unsigned int sg_len, index;
6733b39a
JK		 1998 unsigned int sge_len = 0;
1999 unsigned long long addr;
2000 struct scatterlist *l_sg;
2001 unsigned int offset;
2002
2003 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2004 io_task->bhs_pa.u.a32.address_lo);
2005 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2006 io_task->bhs_pa.u.a32.address_hi);
2007
2008 l_sg = sg;
48bd86cf
JK		 2009 for (index = 0; (index < num_sg) && (index < 2); index++,
2010 sg = sg_next(sg)) {
6733b39a
JK		 2011 if (index == 0) {
2012 sg_len = sg_dma_len(sg);
2013 addr = (u64) sg_dma_address(sg);
2014 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
457ff3b7 2015 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2016 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
457ff3b7 2017 ((u32)(addr >> 32)));
6733b39a
JK		 2018 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2019 sg_len);
2020 sge_len = sg_len;
6733b39a 2021 } else {
6733b39a
JK		 2022 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
2023 pwrb, sge_len);
2024 sg_len = sg_dma_len(sg);
2025 addr = (u64) sg_dma_address(sg);
2026 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
457ff3b7 2027 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2028 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
457ff3b7 2029 ((u32)(addr >> 32)));
6733b39a
JK		 2030 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
2031 sg_len);
2032 }
2033 }
2034 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2035 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2036
2037 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2038
2039 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2040 io_task->bhs_pa.u.a32.address_hi);
2041 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2042 io_task->bhs_pa.u.a32.address_lo);
2043
caf818f1
JK		 2044 if (num_sg == 1) {
2045 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2046 1);
2047 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2048 0);
2049 } else if (num_sg == 2) {
2050 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2051 0);
2052 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2053 1);
2054 } else {
2055 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2056 0);
2057 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2058 0);
2059 }
6733b39a
JK		 2060 sg = l_sg;
2061 psgl++;
2062 psgl++;
2063 offset = 0;
48bd86cf 2064 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
6733b39a
JK		 2065 sg_len = sg_dma_len(sg);
2066 addr = (u64) sg_dma_address(sg);
2067 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2068 (addr & 0xFFFFFFFF));
2069 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2070 (addr >> 32));
2071 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2072 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2073 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2074 offset += sg_len;
2075 }
2076 psgl--;
2077 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2078}
2079
2080static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
2081{
2082 struct iscsi_sge *psgl;
2083 unsigned long long addr;
2084 struct beiscsi_io_task *io_task = task->dd_data;
2085 struct beiscsi_conn *beiscsi_conn = io_task->conn;
2086 struct beiscsi_hba *phba = beiscsi_conn->phba;
2087
2088 io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
2089 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2090 io_task->bhs_pa.u.a32.address_lo);
2091 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2092 io_task->bhs_pa.u.a32.address_hi);
2093
2094 if (task->data) {
2095 if (task->data_count) {
2096 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
2097 addr = (u64) pci_map_single(phba->pcidev,
2098 task->data,
2099 task->data_count, 1);
2100 } else {
2101 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
2102 addr = 0;
2103 }
2104 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
457ff3b7 2105 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2106 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
457ff3b7 2107 ((u32)(addr >> 32)));
6733b39a
JK		 2108 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2109 task->data_count);
2110
2111 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
2112 } else {
2113 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
2114 addr = 0;
2115 }
2116
2117 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2118
2119 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
2120
2121 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2122 io_task->bhs_pa.u.a32.address_hi);
2123 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2124 io_task->bhs_pa.u.a32.address_lo);
2125 if (task->data) {
2126 psgl++;
2127 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
2128 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
2129 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
2130 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
2131 AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
2132 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2133
2134 psgl++;
2135 if (task->data) {
2136 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
457ff3b7 2137 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2138 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
457ff3b7 2139 ((u32)(addr >> 32)));
6733b39a
JK		 2140 }
2141 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
2142 }
2143 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2144}
2145
2146static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
2147{
bfead3b2 2148 unsigned int num_cq_pages, num_async_pdu_buf_pages;
6733b39a
JK		 2149 unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
2150 unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
2151
2152 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
2153 sizeof(struct sol_cqe));
6733b39a
JK		 2154 num_async_pdu_buf_pages =
2155 PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
2156 phba->params.defpdu_hdr_sz);
2157 num_async_pdu_buf_sgl_pages =
2158 PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
2159 sizeof(struct phys_addr));
2160 num_async_pdu_data_pages =
2161 PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
2162 phba->params.defpdu_data_sz);
2163 num_async_pdu_data_sgl_pages =
2164 PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
2165 sizeof(struct phys_addr));
2166
2167 phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
2168
2169 phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
2170 BE_ISCSI_PDU_HEADER_SIZE;
2171 phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
2172 sizeof(struct hwi_context_memory);
2173
6733b39a
JK		 2174
2175 phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
2176 * (phba->params.wrbs_per_cxn)
2177 * phba->params.cxns_per_ctrl;
2178 wrb_sz_per_cxn = sizeof(struct wrb_handle) *
2179 (phba->params.wrbs_per_cxn);
2180 phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
2181 phba->params.cxns_per_ctrl);
2182
2183 phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
2184 phba->params.icds_per_ctrl;
2185 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
2186 phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
2187
2188 phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
2189 num_async_pdu_buf_pages * PAGE_SIZE;
2190 phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
2191 num_async_pdu_data_pages * PAGE_SIZE;
2192 phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
2193 num_async_pdu_buf_sgl_pages * PAGE_SIZE;
2194 phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
2195 num_async_pdu_data_sgl_pages * PAGE_SIZE;
2196 phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
2197 phba->params.asyncpdus_per_ctrl *
2198 sizeof(struct async_pdu_handle);
2199 phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
2200 phba->params.asyncpdus_per_ctrl *
2201 sizeof(struct async_pdu_handle);
2202 phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
2203 sizeof(struct hwi_async_pdu_context) +
2204 (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
2205}
2206
2207static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
2208{
2209 struct be_mem_descriptor *mem_descr;
2210 dma_addr_t bus_add;
2211 struct mem_array *mem_arr, *mem_arr_orig;
2212 unsigned int i, j, alloc_size, curr_alloc_size;
2213
3ec78271 2214 phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
6733b39a
JK		 2215 if (!phba->phwi_ctrlr)
2216 return -ENOMEM;
2217
2218 phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
2219 GFP_KERNEL);
2220 if (!phba->init_mem) {
2221 kfree(phba->phwi_ctrlr);
2222 return -ENOMEM;
2223 }
2224
2225 mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
2226 GFP_KERNEL);
2227 if (!mem_arr_orig) {
2228 kfree(phba->init_mem);
2229 kfree(phba->phwi_ctrlr);
2230 return -ENOMEM;
2231 }
2232
2233 mem_descr = phba->init_mem;
2234 for (i = 0; i < SE_MEM_MAX; i++) {
2235 j = 0;
2236 mem_arr = mem_arr_orig;
2237 alloc_size = phba->mem_req[i];
2238 memset(mem_arr, 0, sizeof(struct mem_array) *
2239 BEISCSI_MAX_FRAGS_INIT);
2240 curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
2241 do {
2242 mem_arr->virtual_address = pci_alloc_consistent(
2243 phba->pcidev,
2244 curr_alloc_size,
2245 &bus_add);
2246 if (!mem_arr->virtual_address) {
2247 if (curr_alloc_size <= BE_MIN_MEM_SIZE)
2248 goto free_mem;
2249 if (curr_alloc_size -
2250 rounddown_pow_of_two(curr_alloc_size))
2251 curr_alloc_size = rounddown_pow_of_two
2252 (curr_alloc_size);
2253 else
2254 curr_alloc_size = curr_alloc_size / 2;
2255 } else {
2256 mem_arr->bus_address.u.
2257 a64.address = (__u64) bus_add;
2258 mem_arr->size = curr_alloc_size;
2259 alloc_size -= curr_alloc_size;
2260 curr_alloc_size = min(be_max_phys_size *
2261 1024, alloc_size);
2262 j++;
2263 mem_arr++;
2264 }
2265 } while (alloc_size);
2266 mem_descr->num_elements = j;
2267 mem_descr->size_in_bytes = phba->mem_req[i];
2268 mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
2269 GFP_KERNEL);
2270 if (!mem_descr->mem_array)
2271 goto free_mem;
2272
2273 memcpy(mem_descr->mem_array, mem_arr_orig,
2274 sizeof(struct mem_array) * j);
2275 mem_descr++;
2276 }
2277 kfree(mem_arr_orig);
2278 return 0;
2279free_mem:
2280 mem_descr->num_elements = j;
2281 while ((i) || (j)) {
2282 for (j = mem_descr->num_elements; j > 0; j--) {
2283 pci_free_consistent(phba->pcidev,
2284 mem_descr->mem_array[j - 1].size,
2285 mem_descr->mem_array[j - 1].
2286 virtual_address,
457ff3b7
JK		 2287 (unsigned long)mem_descr->
2288 mem_array[j - 1].
6733b39a
JK		 2289 bus_address.u.a64.address);
2290 }
2291 if (i) {
2292 i--;
2293 kfree(mem_descr->mem_array);
2294 mem_descr--;
2295 }
2296 }
2297 kfree(mem_arr_orig);
2298 kfree(phba->init_mem);
2299 kfree(phba->phwi_ctrlr);
2300 return -ENOMEM;
2301}
2302
2303static int beiscsi_get_memory(struct beiscsi_hba *phba)
2304{
2305 beiscsi_find_mem_req(phba);
2306 return beiscsi_alloc_mem(phba);
2307}
2308
2309static void iscsi_init_global_templates(struct beiscsi_hba *phba)
2310{
2311 struct pdu_data_out *pdata_out;
2312 struct pdu_nop_out *pnop_out;
2313 struct be_mem_descriptor *mem_descr;
2314
2315 mem_descr = phba->init_mem;
2316 mem_descr += ISCSI_MEM_GLOBAL_HEADER;
2317 pdata_out =
2318 (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
2319 memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2320
2321 AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
2322 IIOC_SCSI_DATA);
2323
2324 pnop_out =
2325 (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
2326 virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
2327
2328 memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2329 AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
2330 AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
2331 AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
2332}
2333
3ec78271 2334static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
6733b39a
JK		 2335{
2336 struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
3ec78271 2337 struct wrb_handle *pwrb_handle = NULL;
6733b39a
JK		 2338 struct hwi_controller *phwi_ctrlr;
2339 struct hwi_wrb_context *pwrb_context;
3ec78271
JK		 2340 struct iscsi_wrb *pwrb = NULL;
2341 unsigned int num_cxn_wrbh = 0;
2342 unsigned int num_cxn_wrb = 0, j, idx = 0, index;
6733b39a
JK		 2343
2344 mem_descr_wrbh = phba->init_mem;
2345 mem_descr_wrbh += HWI_MEM_WRBH;
2346
2347 mem_descr_wrb = phba->init_mem;
2348 mem_descr_wrb += HWI_MEM_WRB;
6733b39a
JK		 2349 phwi_ctrlr = phba->phwi_ctrlr;
2350
2351 for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
2352 pwrb_context = &phwi_ctrlr->wrb_context[index];
6733b39a
JK		 2353 pwrb_context->pwrb_handle_base =
2354 kzalloc(sizeof(struct wrb_handle *) *
2355 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271
JK		 2356 if (!pwrb_context->pwrb_handle_base) {
2357 shost_printk(KERN_ERR, phba->shost,
2358 "Mem Alloc Failed. Failing to load\n");
2359 goto init_wrb_hndl_failed;
2360 }
6733b39a
JK		 2361 pwrb_context->pwrb_handle_basestd =
2362 kzalloc(sizeof(struct wrb_handle *) *
2363 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271
JK		 2364 if (!pwrb_context->pwrb_handle_basestd) {
2365 shost_printk(KERN_ERR, phba->shost,
2366 "Mem Alloc Failed. Failing to load\n");
2367 goto init_wrb_hndl_failed;
2368 }
2369 if (!num_cxn_wrbh) {
2370 pwrb_handle =
2371 mem_descr_wrbh->mem_array[idx].virtual_address;
2372 num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
2373 ((sizeof(struct wrb_handle)) *
2374 phba->params.wrbs_per_cxn));
2375 idx++;
2376 }
2377 pwrb_context->alloc_index = 0;
2378 pwrb_context->wrb_handles_available = 0;
2379 pwrb_context->free_index = 0;
2380
6733b39a 2381 if (num_cxn_wrbh) {
6733b39a
JK		 2382 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2383 pwrb_context->pwrb_handle_base[j] = pwrb_handle;
2384 pwrb_context->pwrb_handle_basestd[j] =
2385 pwrb_handle;
2386 pwrb_context->wrb_handles_available++;
bfead3b2 2387 pwrb_handle->wrb_index = j;
6733b39a
JK		 2388 pwrb_handle++;
2389 }
6733b39a
JK		 2390 num_cxn_wrbh--;
2391 }
2392 }
2393 idx = 0;
ed58ea2a 2394 for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
6733b39a 2395 pwrb_context = &phwi_ctrlr->wrb_context[index];
3ec78271 2396 if (!num_cxn_wrb) {
6733b39a 2397 pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
7c56533c 2398 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
3ec78271
JK		 2399 ((sizeof(struct iscsi_wrb) *
2400 phba->params.wrbs_per_cxn));
2401 idx++;
2402 }
2403
2404 if (num_cxn_wrb) {
6733b39a
JK		 2405 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2406 pwrb_handle = pwrb_context->pwrb_handle_base[j];
2407 pwrb_handle->pwrb = pwrb;
2408 pwrb++;
2409 }
2410 num_cxn_wrb--;
2411 }
2412 }
3ec78271
JK		 2413 return 0;
2414init_wrb_hndl_failed:
2415 for (j = index; j > 0; j--) {
2416 pwrb_context = &phwi_ctrlr->wrb_context[j];
2417 kfree(pwrb_context->pwrb_handle_base);
2418 kfree(pwrb_context->pwrb_handle_basestd);
2419 }
2420 return -ENOMEM;
6733b39a
JK		 2421}
2422
2423static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
2424{
2425 struct hwi_controller *phwi_ctrlr;
2426 struct hba_parameters *p = &phba->params;
2427 struct hwi_async_pdu_context *pasync_ctx;
2428 struct async_pdu_handle *pasync_header_h, *pasync_data_h;
dc63aac6 2429 unsigned int index, idx, num_per_mem, num_async_data;
6733b39a
JK		 2430 struct be_mem_descriptor *mem_descr;
2431
2432 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2433 mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
2434
2435 phwi_ctrlr = phba->phwi_ctrlr;
2436 phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
2437 mem_descr->mem_array[0].virtual_address;
2438 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
2439 memset(pasync_ctx, 0, sizeof(*pasync_ctx));
2440
dc63aac6
JK		 2441 pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
2442 pasync_ctx->buffer_size = p->defpdu_hdr_sz;
6733b39a
JK		 2443
2444 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2445 mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
2446 if (mem_descr->mem_array[0].virtual_address) {
2447 SE_DEBUG(DBG_LVL_8,
2448 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_BUF"
457ff3b7 2449 "va=%p\n", mem_descr->mem_array[0].virtual_address);
6733b39a
JK		 2450 } else
2451 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 2452 "No Virtual address\n");
6733b39a
JK		 2453
2454 pasync_ctx->async_header.va_base =
2455 mem_descr->mem_array[0].virtual_address;
2456
2457 pasync_ctx->async_header.pa_base.u.a64.address =
2458 mem_descr->mem_array[0].bus_address.u.a64.address;
2459
2460 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2461 mem_descr += HWI_MEM_ASYNC_HEADER_RING;
2462 if (mem_descr->mem_array[0].virtual_address) {
2463 SE_DEBUG(DBG_LVL_8,
2464 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_RING"
457ff3b7 2465 "va=%p\n", mem_descr->mem_array[0].virtual_address);
6733b39a
JK		 2466 } else
2467 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 2468 "No Virtual address\n");
6733b39a
JK		 2469 pasync_ctx->async_header.ring_base =
2470 mem_descr->mem_array[0].virtual_address;
2471
2472 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2473 mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
2474 if (mem_descr->mem_array[0].virtual_address) {
2475 SE_DEBUG(DBG_LVL_8,
2476 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_HANDLE"
457ff3b7 2477 "va=%p\n", mem_descr->mem_array[0].virtual_address);
6733b39a
JK		 2478 } else
2479 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 2480 "No Virtual address\n");
6733b39a
JK		 2481
2482 pasync_ctx->async_header.handle_base =
2483 mem_descr->mem_array[0].virtual_address;
2484 pasync_ctx->async_header.writables = 0;
2485 INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
2486
6733b39a
JK		 2487
2488 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2489 mem_descr += HWI_MEM_ASYNC_DATA_RING;
2490 if (mem_descr->mem_array[0].virtual_address) {
2491 SE_DEBUG(DBG_LVL_8,
2492 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_DATA_RING"
457ff3b7 2493 "va=%p\n", mem_descr->mem_array[0].virtual_address);
6733b39a
JK		 2494 } else
2495 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 2496 "No Virtual address\n");
6733b39a
JK		 2497
2498 pasync_ctx->async_data.ring_base =
2499 mem_descr->mem_array[0].virtual_address;
2500
2501 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2502 mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
2503 if (!mem_descr->mem_array[0].virtual_address)
2504 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 2505 "No Virtual address\n");
6733b39a
JK		 2506
2507 pasync_ctx->async_data.handle_base =
2508 mem_descr->mem_array[0].virtual_address;
2509 pasync_ctx->async_data.writables = 0;
2510 INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
2511
2512 pasync_header_h =
2513 (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
2514 pasync_data_h =
2515 (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
2516
dc63aac6
JK		 2517 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2518 mem_descr += HWI_MEM_ASYNC_DATA_BUF;
2519 if (mem_descr->mem_array[0].virtual_address) {
2520 SE_DEBUG(DBG_LVL_8,
2521 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_DATA_BUF"
2522 "va=%p\n", mem_descr->mem_array[0].virtual_address);
2523 } else
2524 shost_printk(KERN_WARNING, phba->shost,
2525 "No Virtual address\n");
2526 idx = 0;
2527 pasync_ctx->async_data.va_base =
2528 mem_descr->mem_array[idx].virtual_address;
2529 pasync_ctx->async_data.pa_base.u.a64.address =
2530 mem_descr->mem_array[idx].bus_address.u.a64.address;
2531
2532 num_async_data = ((mem_descr->mem_array[idx].size) /
2533 phba->params.defpdu_data_sz);
2534 num_per_mem = 0;
2535
6733b39a
JK		 2536 for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
2537 pasync_header_h->cri = -1;
2538 pasync_header_h->index = (char)index;
2539 INIT_LIST_HEAD(&pasync_header_h->link);
2540 pasync_header_h->pbuffer =
2541 (void *)((unsigned long)
2542 (pasync_ctx->async_header.va_base) +
2543 (p->defpdu_hdr_sz * index));
2544
2545 pasync_header_h->pa.u.a64.address =
2546 pasync_ctx->async_header.pa_base.u.a64.address +
2547 (p->defpdu_hdr_sz * index);
2548
2549 list_add_tail(&pasync_header_h->link,
2550 &pasync_ctx->async_header.free_list);
2551 pasync_header_h++;
2552 pasync_ctx->async_header.free_entries++;
2553 pasync_ctx->async_header.writables++;
2554
2555 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
2556 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
2557 header_busy_list);
2558 pasync_data_h->cri = -1;
2559 pasync_data_h->index = (char)index;
2560 INIT_LIST_HEAD(&pasync_data_h->link);
dc63aac6
JK		 2561
2562 if (!num_async_data) {
2563 num_per_mem = 0;
2564 idx++;
2565 pasync_ctx->async_data.va_base =
2566 mem_descr->mem_array[idx].virtual_address;
2567 pasync_ctx->async_data.pa_base.u.a64.address =
2568 mem_descr->mem_array[idx].
2569 bus_address.u.a64.address;
2570
2571 num_async_data = ((mem_descr->mem_array[idx].size) /
2572 phba->params.defpdu_data_sz);
2573 }
6733b39a
JK		 2574 pasync_data_h->pbuffer =
2575 (void *)((unsigned long)
2576 (pasync_ctx->async_data.va_base) +
dc63aac6 2577 (p->defpdu_data_sz * num_per_mem));
6733b39a
JK		 2578
2579 pasync_data_h->pa.u.a64.address =
2580 pasync_ctx->async_data.pa_base.u.a64.address +
dc63aac6
JK		 2581 (p->defpdu_data_sz * num_per_mem);
2582 num_per_mem++;
2583 num_async_data--;
6733b39a
JK		 2584
2585 list_add_tail(&pasync_data_h->link,
2586 &pasync_ctx->async_data.free_list);
2587 pasync_data_h++;
2588 pasync_ctx->async_data.free_entries++;
2589 pasync_ctx->async_data.writables++;
2590
2591 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
2592 }
2593
2594 pasync_ctx->async_header.host_write_ptr = 0;
2595 pasync_ctx->async_header.ep_read_ptr = -1;
2596 pasync_ctx->async_data.host_write_ptr = 0;
2597 pasync_ctx->async_data.ep_read_ptr = -1;
2598}
2599
2600static int
2601be_sgl_create_contiguous(void *virtual_address,
2602 u64 physical_address, u32 length,
2603 struct be_dma_mem *sgl)
2604{
2605 WARN_ON(!virtual_address);
2606 WARN_ON(!physical_address);
2607 WARN_ON(!length > 0);
2608 WARN_ON(!sgl);
2609
2610 sgl->va = virtual_address;
457ff3b7 2611 sgl->dma = (unsigned long)physical_address;
6733b39a
JK		 2612 sgl->size = length;
2613
2614 return 0;
2615}
2616
2617static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
2618{
2619 memset(sgl, 0, sizeof(*sgl));
2620}
2621
2622static void
2623hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
2624 struct mem_array *pmem, struct be_dma_mem *sgl)
2625{
2626 if (sgl->va)
2627 be_sgl_destroy_contiguous(sgl);
2628
2629 be_sgl_create_contiguous(pmem->virtual_address,
2630 pmem->bus_address.u.a64.address,
2631 pmem->size, sgl);
2632}
2633
2634static void
2635hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
2636 struct mem_array *pmem, struct be_dma_mem *sgl)
2637{
2638 if (sgl->va)
2639 be_sgl_destroy_contiguous(sgl);
2640
2641 be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
2642 pmem->bus_address.u.a64.address,
2643 pmem->size, sgl);
2644}
2645
2646static int be_fill_queue(struct be_queue_info *q,
2647 u16 len, u16 entry_size, void *vaddress)
2648{
2649 struct be_dma_mem *mem = &q->dma_mem;
2650
2651 memset(q, 0, sizeof(*q));
2652 q->len = len;
2653 q->entry_size = entry_size;
2654 mem->size = len * entry_size;
2655 mem->va = vaddress;
2656 if (!mem->va)
2657 return -ENOMEM;
2658 memset(mem->va, 0, mem->size);
2659 return 0;
2660}
2661
bfead3b2 2662static int beiscsi_create_eqs(struct beiscsi_hba *phba,
6733b39a
JK		 2663 struct hwi_context_memory *phwi_context)
2664{
bfead3b2
JK		 2665 unsigned int i, num_eq_pages;
2666 int ret, eq_for_mcc;
6733b39a
JK		 2667 struct be_queue_info *eq;
2668 struct be_dma_mem *mem;
6733b39a 2669 void *eq_vaddress;
bfead3b2 2670 dma_addr_t paddr;
6733b39a 2671
bfead3b2
JK		 2672 num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
2673 sizeof(struct be_eq_entry));
6733b39a 2674
bfead3b2
JK		 2675 if (phba->msix_enabled)
2676 eq_for_mcc = 1;
2677 else
2678 eq_for_mcc = 0;
2679 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
2680 eq = &phwi_context->be_eq[i].q;
2681 mem = &eq->dma_mem;
2682 phwi_context->be_eq[i].phba = phba;
2683 eq_vaddress = pci_alloc_consistent(phba->pcidev,
2684 num_eq_pages * PAGE_SIZE,
2685 &paddr);
2686 if (!eq_vaddress)
2687 goto create_eq_error;
2688
2689 mem->va = eq_vaddress;
2690 ret = be_fill_queue(eq, phba->params.num_eq_entries,
2691 sizeof(struct be_eq_entry), eq_vaddress);
2692 if (ret) {
2693 shost_printk(KERN_ERR, phba->shost,
457ff3b7 2694 "be_fill_queue Failed for EQ\n");
bfead3b2
JK		 2695 goto create_eq_error;
2696 }
6733b39a 2697
bfead3b2
JK		 2698 mem->dma = paddr;
2699 ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
2700 phwi_context->cur_eqd);
2701 if (ret) {
2702 shost_printk(KERN_ERR, phba->shost,
2703 "beiscsi_cmd_eq_create"
457ff3b7 2704 "Failedfor EQ\n");
bfead3b2
JK		 2705 goto create_eq_error;
2706 }
2707 SE_DEBUG(DBG_LVL_8, "eqid = %d\n", phwi_context->be_eq[i].q.id);
6733b39a 2708 }
6733b39a 2709 return 0;
bfead3b2
JK		 2710create_eq_error:
2711 for (i = 0; i < (phba->num_cpus + 1); i++) {
2712 eq = &phwi_context->be_eq[i].q;
2713 mem = &eq->dma_mem;
2714 if (mem->va)
2715 pci_free_consistent(phba->pcidev, num_eq_pages
2716 * PAGE_SIZE,
2717 mem->va, mem->dma);
2718 }
2719 return ret;
6733b39a
JK		 2720}
2721
bfead3b2 2722static int beiscsi_create_cqs(struct beiscsi_hba *phba,
6733b39a
JK		 2723 struct hwi_context_memory *phwi_context)
2724{
bfead3b2 2725 unsigned int i, num_cq_pages;
6733b39a
JK		 2726 int ret;
2727 struct be_queue_info *cq, *eq;
2728 struct be_dma_mem *mem;
bfead3b2 2729 struct be_eq_obj *pbe_eq;
6733b39a 2730 void *cq_vaddress;
bfead3b2 2731 dma_addr_t paddr;
6733b39a 2732
bfead3b2
JK		 2733 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
2734 sizeof(struct sol_cqe));
6733b39a 2735
bfead3b2
JK		 2736 for (i = 0; i < phba->num_cpus; i++) {
2737 cq = &phwi_context->be_cq[i];
2738 eq = &phwi_context->be_eq[i].q;
2739 pbe_eq = &phwi_context->be_eq[i];
2740 pbe_eq->cq = cq;
2741 pbe_eq->phba = phba;
2742 mem = &cq->dma_mem;
2743 cq_vaddress = pci_alloc_consistent(phba->pcidev,
2744 num_cq_pages * PAGE_SIZE,
2745 &paddr);
2746 if (!cq_vaddress)
2747 goto create_cq_error;
7da50879 2748 ret = be_fill_queue(cq, phba->params.num_cq_entries,
bfead3b2
JK		 2749 sizeof(struct sol_cqe), cq_vaddress);
2750 if (ret) {
2751 shost_printk(KERN_ERR, phba->shost,
457ff3b7 2752 "be_fill_queue Failed for ISCSI CQ\n");
bfead3b2
JK		 2753 goto create_cq_error;
2754 }
2755
2756 mem->dma = paddr;
2757 ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
2758 false, 0);
2759 if (ret) {
2760 shost_printk(KERN_ERR, phba->shost,
2761 "beiscsi_cmd_eq_create"
457ff3b7 2762 "Failed for ISCSI CQ\n");
bfead3b2
JK		 2763 goto create_cq_error;
2764 }
2765 SE_DEBUG(DBG_LVL_8, "iscsi cq_id is %d for eq_id %d\n",
2766 cq->id, eq->id);
2767 SE_DEBUG(DBG_LVL_8, "ISCSI CQ CREATED\n");
6733b39a 2768 }
6733b39a 2769 return 0;
bfead3b2
JK		 2770
2771create_cq_error:
2772 for (i = 0; i < phba->num_cpus; i++) {
2773 cq = &phwi_context->be_cq[i];
2774 mem = &cq->dma_mem;
2775 if (mem->va)
2776 pci_free_consistent(phba->pcidev, num_cq_pages
2777 * PAGE_SIZE,
2778 mem->va, mem->dma);
2779 }
2780 return ret;
2781
6733b39a
JK		 2782}
2783
2784static int
2785beiscsi_create_def_hdr(struct beiscsi_hba *phba,
2786 struct hwi_context_memory *phwi_context,
2787 struct hwi_controller *phwi_ctrlr,
2788 unsigned int def_pdu_ring_sz)
2789{
2790 unsigned int idx;
2791 int ret;
2792 struct be_queue_info *dq, *cq;
2793 struct be_dma_mem *mem;
2794 struct be_mem_descriptor *mem_descr;
2795 void *dq_vaddress;
2796
2797 idx = 0;
2798 dq = &phwi_context->be_def_hdrq;
bfead3b2 2799 cq = &phwi_context->be_cq[0];
6733b39a
JK		 2800 mem = &dq->dma_mem;
2801 mem_descr = phba->init_mem;
2802 mem_descr += HWI_MEM_ASYNC_HEADER_RING;
2803 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
2804 ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
2805 sizeof(struct phys_addr),
2806 sizeof(struct phys_addr), dq_vaddress);
2807 if (ret) {
2808 shost_printk(KERN_ERR, phba->shost,
2809 "be_fill_queue Failed for DEF PDU HDR\n");
2810 return ret;
2811 }
457ff3b7
JK		 2812 mem->dma = (unsigned long)mem_descr->mem_array[idx].
2813 bus_address.u.a64.address;
6733b39a
JK		 2814 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
2815 def_pdu_ring_sz,
2816 phba->params.defpdu_hdr_sz);
2817 if (ret) {
2818 shost_printk(KERN_ERR, phba->shost,
2819 "be_cmd_create_default_pdu_queue Failed DEFHDR\n");
2820 return ret;
2821 }
2822 phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
2823 SE_DEBUG(DBG_LVL_8, "iscsi def pdu id is %d\n",
2824 phwi_context->be_def_hdrq.id);
2825 hwi_post_async_buffers(phba, 1);
2826 return 0;
2827}
2828
2829static int
2830beiscsi_create_def_data(struct beiscsi_hba *phba,
2831 struct hwi_context_memory *phwi_context,
2832 struct hwi_controller *phwi_ctrlr,
2833 unsigned int def_pdu_ring_sz)
2834{
2835 unsigned int idx;
2836 int ret;
2837 struct be_queue_info *dataq, *cq;
2838 struct be_dma_mem *mem;
2839 struct be_mem_descriptor *mem_descr;
2840 void *dq_vaddress;
2841
2842 idx = 0;
2843 dataq = &phwi_context->be_def_dataq;
bfead3b2 2844 cq = &phwi_context->be_cq[0];
6733b39a
JK		 2845 mem = &dataq->dma_mem;
2846 mem_descr = phba->init_mem;
2847 mem_descr += HWI_MEM_ASYNC_DATA_RING;
2848 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
2849 ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
2850 sizeof(struct phys_addr),
2851 sizeof(struct phys_addr), dq_vaddress);
2852 if (ret) {
2853 shost_printk(KERN_ERR, phba->shost,
2854 "be_fill_queue Failed for DEF PDU DATA\n");
2855 return ret;
2856 }
457ff3b7
JK		 2857 mem->dma = (unsigned long)mem_descr->mem_array[idx].
2858 bus_address.u.a64.address;
6733b39a
JK		 2859 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
2860 def_pdu_ring_sz,
2861 phba->params.defpdu_data_sz);
2862 if (ret) {
2863 shost_printk(KERN_ERR, phba->shost,
2864 "be_cmd_create_default_pdu_queue Failed"
2865 " for DEF PDU DATA\n");
2866 return ret;
2867 }
2868 phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
2869 SE_DEBUG(DBG_LVL_8, "iscsi def data id is %d\n",
2870 phwi_context->be_def_dataq.id);
2871 hwi_post_async_buffers(phba, 0);
457ff3b7 2872 SE_DEBUG(DBG_LVL_8, "DEFAULT PDU DATA RING CREATED\n");
6733b39a
JK		 2873 return 0;
2874}
2875
2876static int
2877beiscsi_post_pages(struct beiscsi_hba *phba)
2878{
2879 struct be_mem_descriptor *mem_descr;
2880 struct mem_array *pm_arr;
2881 unsigned int page_offset, i;
2882 struct be_dma_mem sgl;
2883 int status;
2884
2885 mem_descr = phba->init_mem;
2886 mem_descr += HWI_MEM_SGE;
2887 pm_arr = mem_descr->mem_array;
2888
2889 page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
2890 phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
2891 for (i = 0; i < mem_descr->num_elements; i++) {
2892 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
2893 status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
2894 page_offset,
2895 (pm_arr->size / PAGE_SIZE));
2896 page_offset += pm_arr->size / PAGE_SIZE;
2897 if (status != 0) {
2898 shost_printk(KERN_ERR, phba->shost,
2899 "post sgl failed.\n");
2900 return status;
2901 }
2902 pm_arr++;
2903 }
457ff3b7 2904 SE_DEBUG(DBG_LVL_8, "POSTED PAGES\n");
6733b39a
JK		 2905 return 0;
2906}
2907
bfead3b2
JK		 2908static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
2909{
2910 struct be_dma_mem *mem = &q->dma_mem;
2911 if (mem->va)
2912 pci_free_consistent(phba->pcidev, mem->size,
2913 mem->va, mem->dma);
2914}
2915
2916static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
2917 u16 len, u16 entry_size)
2918{
2919 struct be_dma_mem *mem = &q->dma_mem;
2920
2921 memset(q, 0, sizeof(*q));
2922 q->len = len;
2923 q->entry_size = entry_size;
2924 mem->size = len * entry_size;
2925 mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
2926 if (!mem->va)
d3ad2bb3 2927 return -ENOMEM;
bfead3b2
JK		 2928 memset(mem->va, 0, mem->size);
2929 return 0;
2930}
2931
6733b39a
JK		 2932static int
2933beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
2934 struct hwi_context_memory *phwi_context,
2935 struct hwi_controller *phwi_ctrlr)
2936{
2937 unsigned int wrb_mem_index, offset, size, num_wrb_rings;
2938 u64 pa_addr_lo;
2939 unsigned int idx, num, i;
2940 struct mem_array *pwrb_arr;
2941 void *wrb_vaddr;
2942 struct be_dma_mem sgl;
2943 struct be_mem_descriptor *mem_descr;
2944 int status;
2945
2946 idx = 0;
2947 mem_descr = phba->init_mem;
2948 mem_descr += HWI_MEM_WRB;
2949 pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
2950 GFP_KERNEL);
2951 if (!pwrb_arr) {
2952 shost_printk(KERN_ERR, phba->shost,
2953 "Memory alloc failed in create wrb ring.\n");
2954 return -ENOMEM;
2955 }
2956 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
2957 pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
2958 num_wrb_rings = mem_descr->mem_array[idx].size /
2959 (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
2960
2961 for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
2962 if (num_wrb_rings) {
2963 pwrb_arr[num].virtual_address = wrb_vaddr;
2964 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
2965 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
2966 sizeof(struct iscsi_wrb);
2967 wrb_vaddr += pwrb_arr[num].size;
2968 pa_addr_lo += pwrb_arr[num].size;
2969 num_wrb_rings--;
2970 } else {
2971 idx++;
2972 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
2973 pa_addr_lo = mem_descr->mem_array[idx].\
2974 bus_address.u.a64.address;
2975 num_wrb_rings = mem_descr->mem_array[idx].size /
2976 (phba->params.wrbs_per_cxn *
2977 sizeof(struct iscsi_wrb));
2978 pwrb_arr[num].virtual_address = wrb_vaddr;
2979 pwrb_arr[num].bus_address.u.a64.address\
2980 = pa_addr_lo;
2981 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
2982 sizeof(struct iscsi_wrb);
2983 wrb_vaddr += pwrb_arr[num].size;
2984 pa_addr_lo += pwrb_arr[num].size;
2985 num_wrb_rings--;
2986 }
2987 }
2988 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
2989 wrb_mem_index = 0;
2990 offset = 0;
2991 size = 0;
2992
2993 hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
2994 status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
2995 &phwi_context->be_wrbq[i]);
2996 if (status != 0) {
2997 shost_printk(KERN_ERR, phba->shost,
2998 "wrbq create failed.");
1462b8ff 2999 kfree(pwrb_arr);
6733b39a
JK		 3000 return status;
3001 }
7da50879
JK		 3002 phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i].
3003 id;
6733b39a
JK		 3004 }
3005 kfree(pwrb_arr);
3006 return 0;
3007}
3008
3009static void free_wrb_handles(struct beiscsi_hba *phba)
3010{
3011 unsigned int index;
3012 struct hwi_controller *phwi_ctrlr;
3013 struct hwi_wrb_context *pwrb_context;
3014
3015 phwi_ctrlr = phba->phwi_ctrlr;
3016 for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
3017 pwrb_context = &phwi_ctrlr->wrb_context[index];
3018 kfree(pwrb_context->pwrb_handle_base);
3019 kfree(pwrb_context->pwrb_handle_basestd);
3020 }
3021}
3022
bfead3b2
JK		 3023static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
3024{
3025 struct be_queue_info *q;
3026 struct be_ctrl_info *ctrl = &phba->ctrl;
3027
3028 q = &phba->ctrl.mcc_obj.q;
3029 if (q->created)
3030 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
3031 be_queue_free(phba, q);
3032
3033 q = &phba->ctrl.mcc_obj.cq;
3034 if (q->created)
3035 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
3036 be_queue_free(phba, q);
3037}
3038
6733b39a
JK		 3039static void hwi_cleanup(struct beiscsi_hba *phba)
3040{
3041 struct be_queue_info *q;
3042 struct be_ctrl_info *ctrl = &phba->ctrl;
3043 struct hwi_controller *phwi_ctrlr;
3044 struct hwi_context_memory *phwi_context;
bfead3b2 3045 int i, eq_num;
6733b39a
JK		 3046
3047 phwi_ctrlr = phba->phwi_ctrlr;
3048 phwi_context = phwi_ctrlr->phwi_ctxt;
3049 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3050 q = &phwi_context->be_wrbq[i];
3051 if (q->created)
3052 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
3053 }
6733b39a
JK		 3054 free_wrb_handles(phba);
3055
3056 q = &phwi_context->be_def_hdrq;
3057 if (q->created)
3058 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3059
3060 q = &phwi_context->be_def_dataq;
3061 if (q->created)
3062 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3063
3064 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
3065
bfead3b2
JK		 3066 for (i = 0; i < (phba->num_cpus); i++) {
3067 q = &phwi_context->be_cq[i];
3068 if (q->created)
3069 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
3070 }
3071 if (phba->msix_enabled)
3072 eq_num = 1;
3073 else
3074 eq_num = 0;
3075 for (i = 0; i < (phba->num_cpus + eq_num); i++) {
3076 q = &phwi_context->be_eq[i].q;
3077 if (q->created)
3078 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
3079 }
3080 be_mcc_queues_destroy(phba);
3081}
6733b39a 3082
bfead3b2
JK		 3083static int be_mcc_queues_create(struct beiscsi_hba *phba,
3084 struct hwi_context_memory *phwi_context)
3085{
3086 struct be_queue_info *q, *cq;
3087 struct be_ctrl_info *ctrl = &phba->ctrl;
3088
3089 /* Alloc MCC compl queue */
3090 cq = &phba->ctrl.mcc_obj.cq;
3091 if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
3092 sizeof(struct be_mcc_compl)))
3093 goto err;
3094 /* Ask BE to create MCC compl queue; */
3095 if (phba->msix_enabled) {
3096 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
3097 [phba->num_cpus].q, false, true, 0))
3098 goto mcc_cq_free;
3099 } else {
3100 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
3101 false, true, 0))
3102 goto mcc_cq_free;
3103 }
3104
3105 /* Alloc MCC queue */
3106 q = &phba->ctrl.mcc_obj.q;
3107 if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
3108 goto mcc_cq_destroy;
3109
3110 /* Ask BE to create MCC queue */
35e66019 3111 if (beiscsi_cmd_mccq_create(phba, q, cq))
bfead3b2
JK		 3112 goto mcc_q_free;
3113
3114 return 0;
3115
3116mcc_q_free:
3117 be_queue_free(phba, q);
3118mcc_cq_destroy:
3119 beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
3120mcc_cq_free:
3121 be_queue_free(phba, cq);
3122err:
d3ad2bb3 3123 return -ENOMEM;
bfead3b2
JK		 3124}
3125
3126static int find_num_cpus(void)
3127{
3128 int num_cpus = 0;
3129
3130 num_cpus = num_online_cpus();
3131 if (num_cpus >= MAX_CPUS)
3132 num_cpus = MAX_CPUS - 1;
3133
457ff3b7 3134 SE_DEBUG(DBG_LVL_8, "num_cpus = %d\n", num_cpus);
bfead3b2 3135 return num_cpus;
6733b39a
JK		 3136}
3137
3138static int hwi_init_port(struct beiscsi_hba *phba)
3139{
3140 struct hwi_controller *phwi_ctrlr;
3141 struct hwi_context_memory *phwi_context;
3142 unsigned int def_pdu_ring_sz;
3143 struct be_ctrl_info *ctrl = &phba->ctrl;
3144 int status;
3145
3146 def_pdu_ring_sz =
3147 phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
3148 phwi_ctrlr = phba->phwi_ctrlr;
6733b39a 3149 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 3150 phwi_context->max_eqd = 0;
3151 phwi_context->min_eqd = 0;
3152 phwi_context->cur_eqd = 64;
6733b39a 3153 be_cmd_fw_initialize(&phba->ctrl);
bfead3b2
JK		 3154
3155 status = beiscsi_create_eqs(phba, phwi_context);
6733b39a 3156 if (status != 0) {
457ff3b7 3157 shost_printk(KERN_ERR, phba->shost, "EQ not created\n");
6733b39a
JK		 3158 goto error;
3159 }
3160
bfead3b2
JK		 3161 status = be_mcc_queues_create(phba, phwi_context);
3162 if (status != 0)
3163 goto error;
3164
3165 status = mgmt_check_supported_fw(ctrl, phba);
6733b39a
JK		 3166 if (status != 0) {
3167 shost_printk(KERN_ERR, phba->shost,
457ff3b7 3168 "Unsupported fw version\n");
6733b39a
JK		 3169 goto error;
3170 }
3171
bfead3b2 3172 status = beiscsi_create_cqs(phba, phwi_context);
6733b39a
JK		 3173 if (status != 0) {
3174 shost_printk(KERN_ERR, phba->shost, "CQ not created\n");
3175 goto error;
3176 }
3177
3178 status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
3179 def_pdu_ring_sz);
3180 if (status != 0) {
3181 shost_printk(KERN_ERR, phba->shost,
3182 "Default Header not created\n");
3183 goto error;
3184 }
3185
3186 status = beiscsi_create_def_data(phba, phwi_context,
3187 phwi_ctrlr, def_pdu_ring_sz);
3188 if (status != 0) {
3189 shost_printk(KERN_ERR, phba->shost,
3190 "Default Data not created\n");
3191 goto error;
3192 }
3193
3194 status = beiscsi_post_pages(phba);
3195 if (status != 0) {
3196 shost_printk(KERN_ERR, phba->shost, "Post SGL Pages Failed\n");
3197 goto error;
3198 }
3199
3200 status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
3201 if (status != 0) {
3202 shost_printk(KERN_ERR, phba->shost,
3203 "WRB Rings not created\n");
3204 goto error;
3205 }
3206
3207 SE_DEBUG(DBG_LVL_8, "hwi_init_port success\n");
3208 return 0;
3209
3210error:
3211 shost_printk(KERN_ERR, phba->shost, "hwi_init_port failed");
3212 hwi_cleanup(phba);
3213 return -ENOMEM;
3214}
3215
6733b39a
JK		 3216static int hwi_init_controller(struct beiscsi_hba *phba)
3217{
3218 struct hwi_controller *phwi_ctrlr;
3219
3220 phwi_ctrlr = phba->phwi_ctrlr;
3221 if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
3222 phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
3223 init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
457ff3b7 3224 SE_DEBUG(DBG_LVL_8, " phwi_ctrlr->phwi_ctxt=%p\n",
6733b39a
JK		 3225 phwi_ctrlr->phwi_ctxt);
3226 } else {
3227 shost_printk(KERN_ERR, phba->shost,
3228 "HWI_MEM_ADDN_CONTEXT is more than one element."
3229 "Failing to load\n");
3230 return -ENOMEM;
3231 }
3232
3233 iscsi_init_global_templates(phba);
3ec78271
JK		 3234 if (beiscsi_init_wrb_handle(phba))
3235 return -ENOMEM;
3236
6733b39a
JK		 3237 hwi_init_async_pdu_ctx(phba);
3238 if (hwi_init_port(phba) != 0) {
3239 shost_printk(KERN_ERR, phba->shost,
3240 "hwi_init_controller failed\n");
3241 return -ENOMEM;
3242 }
3243 return 0;
3244}
3245
3246static void beiscsi_free_mem(struct beiscsi_hba *phba)
3247{
3248 struct be_mem_descriptor *mem_descr;
3249 int i, j;
3250
3251 mem_descr = phba->init_mem;
3252 i = 0;
3253 j = 0;
3254 for (i = 0; i < SE_MEM_MAX; i++) {
3255 for (j = mem_descr->num_elements; j > 0; j--) {
3256 pci_free_consistent(phba->pcidev,
3257 mem_descr->mem_array[j - 1].size,
3258 mem_descr->mem_array[j - 1].virtual_address,
457ff3b7
JK		 3259 (unsigned long)mem_descr->mem_array[j - 1].
3260 bus_address.u.a64.address);
6733b39a
JK		 3261 }
3262 kfree(mem_descr->mem_array);
3263 mem_descr++;
3264 }
3265 kfree(phba->init_mem);
3266 kfree(phba->phwi_ctrlr);
3267}
3268
3269static int beiscsi_init_controller(struct beiscsi_hba *phba)
3270{
3271 int ret = -ENOMEM;
3272
3273 ret = beiscsi_get_memory(phba);
3274 if (ret < 0) {
3275 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe -"
457ff3b7 3276 "Failed in beiscsi_alloc_memory\n");
6733b39a
JK		 3277 return ret;
3278 }
3279
3280 ret = hwi_init_controller(phba);
3281 if (ret)
3282 goto free_init;
3283 SE_DEBUG(DBG_LVL_8, "Return success from beiscsi_init_controller");
3284 return 0;
3285
3286free_init:
3287 beiscsi_free_mem(phba);
3288 return -ENOMEM;
3289}
3290
3291static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
3292{
3293 struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
3294 struct sgl_handle *psgl_handle;
3295 struct iscsi_sge *pfrag;
3296 unsigned int arr_index, i, idx;
3297
3298 phba->io_sgl_hndl_avbl = 0;
3299 phba->eh_sgl_hndl_avbl = 0;
bfead3b2 3300
6733b39a
JK		 3301 mem_descr_sglh = phba->init_mem;
3302 mem_descr_sglh += HWI_MEM_SGLH;
3303 if (1 == mem_descr_sglh->num_elements) {
3304 phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
3305 phba->params.ios_per_ctrl,
3306 GFP_KERNEL);
3307 if (!phba->io_sgl_hndl_base) {
3308 shost_printk(KERN_ERR, phba->shost,
3309 "Mem Alloc Failed. Failing to load\n");
3310 return -ENOMEM;
3311 }
3312 phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
3313 (phba->params.icds_per_ctrl -
3314 phba->params.ios_per_ctrl),
3315 GFP_KERNEL);
3316 if (!phba->eh_sgl_hndl_base) {
3317 kfree(phba->io_sgl_hndl_base);
3318 shost_printk(KERN_ERR, phba->shost,
3319 "Mem Alloc Failed. Failing to load\n");
3320 return -ENOMEM;
3321 }
3322 } else {
3323 shost_printk(KERN_ERR, phba->shost,
3324 "HWI_MEM_SGLH is more than one element."
3325 "Failing to load\n");
3326 return -ENOMEM;
3327 }
3328
3329 arr_index = 0;
3330 idx = 0;
3331 while (idx < mem_descr_sglh->num_elements) {
3332 psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
3333
3334 for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
3335 sizeof(struct sgl_handle)); i++) {
3336 if (arr_index < phba->params.ios_per_ctrl) {
3337 phba->io_sgl_hndl_base[arr_index] = psgl_handle;
3338 phba->io_sgl_hndl_avbl++;
3339 arr_index++;
3340 } else {
3341 phba->eh_sgl_hndl_base[arr_index -
3342 phba->params.ios_per_ctrl] =
3343 psgl_handle;
3344 arr_index++;
3345 phba->eh_sgl_hndl_avbl++;
3346 }
3347 psgl_handle++;
3348 }
3349 idx++;
3350 }
3351 SE_DEBUG(DBG_LVL_8,
3352 "phba->io_sgl_hndl_avbl=%d"
457ff3b7 3353 "phba->eh_sgl_hndl_avbl=%d\n",
6733b39a
JK		 3354 phba->io_sgl_hndl_avbl,
3355 phba->eh_sgl_hndl_avbl);
3356 mem_descr_sg = phba->init_mem;
3357 mem_descr_sg += HWI_MEM_SGE;
457ff3b7 3358 SE_DEBUG(DBG_LVL_8, "\n mem_descr_sg->num_elements=%d\n",
6733b39a
JK		 3359 mem_descr_sg->num_elements);
3360 arr_index = 0;
3361 idx = 0;
3362 while (idx < mem_descr_sg->num_elements) {
3363 pfrag = mem_descr_sg->mem_array[idx].virtual_address;
3364
3365 for (i = 0;
3366 i < (mem_descr_sg->mem_array[idx].size) /
3367 (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
3368 i++) {
3369 if (arr_index < phba->params.ios_per_ctrl)
3370 psgl_handle = phba->io_sgl_hndl_base[arr_index];
3371 else
3372 psgl_handle = phba->eh_sgl_hndl_base[arr_index -
3373 phba->params.ios_per_ctrl];
3374 psgl_handle->pfrag = pfrag;
3375 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
3376 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
3377 pfrag += phba->params.num_sge_per_io;
3378 psgl_handle->sgl_index =
7da50879 3379 phba->fw_config.iscsi_icd_start + arr_index++;
6733b39a
JK		 3380 }
3381 idx++;
3382 }
3383 phba->io_sgl_free_index = 0;
3384 phba->io_sgl_alloc_index = 0;
3385 phba->eh_sgl_free_index = 0;
3386 phba->eh_sgl_alloc_index = 0;
3387 return 0;
3388}
3389
3390static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
3391{
3392 int i, new_cid;
3393
c2462288 3394 phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
6733b39a
JK		 3395 GFP_KERNEL);
3396 if (!phba->cid_array) {
3397 shost_printk(KERN_ERR, phba->shost,
3398 "Failed to allocate memory in "
3399 "hba_setup_cid_tbls\n");
3400 return -ENOMEM;
3401 }
c2462288 3402 phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
6733b39a
JK		 3403 phba->params.cxns_per_ctrl * 2, GFP_KERNEL);
3404 if (!phba->ep_array) {
3405 shost_printk(KERN_ERR, phba->shost,
3406 "Failed to allocate memory in "
457ff3b7 3407 "hba_setup_cid_tbls\n");
6733b39a
JK		 3408 kfree(phba->cid_array);
3409 return -ENOMEM;
3410 }
7da50879 3411 new_cid = phba->fw_config.iscsi_cid_start;
6733b39a
JK		 3412 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3413 phba->cid_array[i] = new_cid;
3414 new_cid += 2;
3415 }
3416 phba->avlbl_cids = phba->params.cxns_per_ctrl;
3417 return 0;
3418}
3419
238f6b72 3420static void hwi_enable_intr(struct beiscsi_hba *phba)
6733b39a
JK		 3421{
3422 struct be_ctrl_info *ctrl = &phba->ctrl;
3423 struct hwi_controller *phwi_ctrlr;
3424 struct hwi_context_memory *phwi_context;
3425 struct be_queue_info *eq;
3426 u8 __iomem *addr;
bfead3b2 3427 u32 reg, i;
6733b39a
JK		 3428 u32 enabled;
3429
3430 phwi_ctrlr = phba->phwi_ctrlr;
3431 phwi_context = phwi_ctrlr->phwi_ctxt;
3432
6733b39a
JK		 3433 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
3434 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
3435 reg = ioread32(addr);
6733b39a
JK		 3436
3437 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
3438 if (!enabled) {
3439 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
457ff3b7 3440 SE_DEBUG(DBG_LVL_8, "reg =x%08x addr=%p\n", reg, addr);
6733b39a 3441 iowrite32(reg, addr);
665d6d94
JK		 3442 }
3443
3444 if (!phba->msix_enabled) {
3445 eq = &phwi_context->be_eq[0].q;
3446 SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
3447 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
3448 } else {
3449 for (i = 0; i <= phba->num_cpus; i++) {
3450 eq = &phwi_context->be_eq[i].q;
457ff3b7 3451 SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
bfead3b2
JK		 3452 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
3453 }
c03af1ae 3454 }
6733b39a
JK		 3455}
3456
3457static void hwi_disable_intr(struct beiscsi_hba *phba)
3458{
3459 struct be_ctrl_info *ctrl = &phba->ctrl;
3460
3461 u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
3462 u32 reg = ioread32(addr);
3463
3464 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
3465 if (enabled) {
3466 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
3467 iowrite32(reg, addr);
3468 } else
3469 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 3470 "In hwi_disable_intr, Already Disabled\n");
6733b39a
JK		 3471}
3472
c7acc5b8
JK		 3473static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
3474{
3475 struct be_cmd_resp_get_boot_target *boot_resp;
3476 struct be_cmd_resp_get_session *session_resp;
3477 struct be_mcc_wrb *wrb;
3478 struct be_dma_mem nonemb_cmd;
3479 unsigned int tag, wrb_num;
3480 unsigned short status, extd_status;
3481 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
f457a46f 3482 int ret = -ENOMEM;
c7acc5b8
JK		 3483
3484 tag = beiscsi_get_boot_target(phba);
3485 if (!tag) {
3486 SE_DEBUG(DBG_LVL_1, "be_cmd_get_mac_addr Failed\n");
3487 return -EAGAIN;
3488 } else
3489 wait_event_interruptible(phba->ctrl.mcc_wait[tag],
3490 phba->ctrl.mcc_numtag[tag]);
3491
3492 wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
3493 extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
3494 status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
3495 if (status || extd_status) {
3496 SE_DEBUG(DBG_LVL_1, "be_cmd_get_mac_addr Failed"
3497 " status = %d extd_status = %d\n",
3498 status, extd_status);
3499 free_mcc_tag(&phba->ctrl, tag);
3500 return -EBUSY;
3501 }
3502 wrb = queue_get_wrb(mccq, wrb_num);
3503 free_mcc_tag(&phba->ctrl, tag);
3504 boot_resp = embedded_payload(wrb);
3505
3506 if (boot_resp->boot_session_handle < 0) {
f457a46f 3507 shost_printk(KERN_INFO, phba->shost, "No Boot Session.\n");
c7acc5b8
JK		 3508 return -ENXIO;
3509 }
3510
3511 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
3512 sizeof(*session_resp),
3513 &nonemb_cmd.dma);
3514 if (nonemb_cmd.va == NULL) {
3515 SE_DEBUG(DBG_LVL_1,
3516 "Failed to allocate memory for"
3517 "beiscsi_get_session_info\n");
3518 return -ENOMEM;
3519 }
3520
3521 memset(nonemb_cmd.va, 0, sizeof(*session_resp));
3522 tag = beiscsi_get_session_info(phba,
3523 boot_resp->boot_session_handle, &nonemb_cmd);
3524 if (!tag) {
3525 SE_DEBUG(DBG_LVL_1, "beiscsi_get_session_info"
3526 " Failed\n");
3527 goto boot_freemem;
3528 } else
3529 wait_event_interruptible(phba->ctrl.mcc_wait[tag],
3530 phba->ctrl.mcc_numtag[tag]);
3531
3532 wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
3533 extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
3534 status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
3535 if (status || extd_status) {
3536 SE_DEBUG(DBG_LVL_1, "beiscsi_get_session_info Failed"
3537 " status = %d extd_status = %d\n",
3538 status, extd_status);
3539 free_mcc_tag(&phba->ctrl, tag);
3540 goto boot_freemem;
3541 }
3542 wrb = queue_get_wrb(mccq, wrb_num);
3543 free_mcc_tag(&phba->ctrl, tag);
3544 session_resp = nonemb_cmd.va ;
f457a46f 3545
c7acc5b8
JK		 3546 memcpy(&phba->boot_sess, &session_resp->session_info,
3547 sizeof(struct mgmt_session_info));
f457a46f
MC		 3548 ret = 0;
3549
c7acc5b8
JK		 3550boot_freemem:
3551 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
3552 nonemb_cmd.va, nonemb_cmd.dma);
f457a46f
MC		 3553 return ret;
3554}
3555
3556static void beiscsi_boot_release(void *data)
3557{
3558 struct beiscsi_hba *phba = data;
3559
3560 scsi_host_put(phba->shost);
3561}
3562
3563static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
3564{
3565 struct iscsi_boot_kobj *boot_kobj;
3566
3567 /* get boot info using mgmt cmd */
3568 if (beiscsi_get_boot_info(phba))
3569 /* Try to see if we can carry on without this */
3570 return 0;
3571
3572 phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
3573 if (!phba->boot_kset)
3574 return -ENOMEM;
3575
3576 /* get a ref because the show function will ref the phba */
3577 if (!scsi_host_get(phba->shost))
3578 goto free_kset;
3579 boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
3580 beiscsi_show_boot_tgt_info,
3581 beiscsi_tgt_get_attr_visibility,
3582 beiscsi_boot_release);
3583 if (!boot_kobj)
3584 goto put_shost;
3585
3586 if (!scsi_host_get(phba->shost))
3587 goto free_kset;
3588 boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
3589 beiscsi_show_boot_ini_info,
3590 beiscsi_ini_get_attr_visibility,
3591 beiscsi_boot_release);
3592 if (!boot_kobj)
3593 goto put_shost;
3594
3595 if (!scsi_host_get(phba->shost))
3596 goto free_kset;
3597 boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
3598 beiscsi_show_boot_eth_info,
3599 beiscsi_eth_get_attr_visibility,
3600 beiscsi_boot_release);
3601 if (!boot_kobj)
3602 goto put_shost;
3603 return 0;
3604
3605put_shost:
3606 scsi_host_put(phba->shost);
3607free_kset:
3608 iscsi_boot_destroy_kset(phba->boot_kset);
c7acc5b8
JK		 3609 return -ENOMEM;
3610}
3611
6733b39a
JK		 3612static int beiscsi_init_port(struct beiscsi_hba *phba)
3613{
3614 int ret;
3615
3616 ret = beiscsi_init_controller(phba);
3617 if (ret < 0) {
3618 shost_printk(KERN_ERR, phba->shost,
3619 "beiscsi_dev_probe - Failed in"
457ff3b7 3620 "beiscsi_init_controller\n");
6733b39a
JK		 3621 return ret;
3622 }
3623 ret = beiscsi_init_sgl_handle(phba);
3624 if (ret < 0) {
3625 shost_printk(KERN_ERR, phba->shost,
3626 "beiscsi_dev_probe - Failed in"
457ff3b7 3627 "beiscsi_init_sgl_handle\n");
6733b39a
JK		 3628 goto do_cleanup_ctrlr;
3629 }
3630
3631 if (hba_setup_cid_tbls(phba)) {
3632 shost_printk(KERN_ERR, phba->shost,
3633 "Failed in hba_setup_cid_tbls\n");
3634 kfree(phba->io_sgl_hndl_base);
3635 kfree(phba->eh_sgl_hndl_base);
3636 goto do_cleanup_ctrlr;
3637 }
3638
3639 return ret;
3640
3641do_cleanup_ctrlr:
3642 hwi_cleanup(phba);
3643 return ret;
3644}
3645
3646static void hwi_purge_eq(struct beiscsi_hba *phba)
3647{
3648 struct hwi_controller *phwi_ctrlr;
3649 struct hwi_context_memory *phwi_context;
3650 struct be_queue_info *eq;
3651 struct be_eq_entry *eqe = NULL;
bfead3b2 3652 int i, eq_msix;
756d29c8 3653 unsigned int num_processed;
6733b39a
JK		 3654
3655 phwi_ctrlr = phba->phwi_ctrlr;
3656 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 3657 if (phba->msix_enabled)
3658 eq_msix = 1;
3659 else
3660 eq_msix = 0;
6733b39a 3661
bfead3b2
JK		 3662 for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
3663 eq = &phwi_context->be_eq[i].q;
6733b39a 3664 eqe = queue_tail_node(eq);
756d29c8 3665 num_processed = 0;
bfead3b2
JK		 3666 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
3667 & EQE_VALID_MASK) {
3668 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
3669 queue_tail_inc(eq);
3670 eqe = queue_tail_node(eq);
756d29c8 3671 num_processed++;
bfead3b2 3672 }
756d29c8
JK		 3673
3674 if (num_processed)
3675 hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
6733b39a
JK		 3676 }
3677}
3678
3679static void beiscsi_clean_port(struct beiscsi_hba *phba)
3680{
03a12310 3681 int mgmt_status;
6733b39a
JK		 3682
3683 mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
3684 if (mgmt_status)
3685 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 3686 "mgmt_epfw_cleanup FAILED\n");
756d29c8 3687
6733b39a 3688 hwi_purge_eq(phba);
756d29c8 3689 hwi_cleanup(phba);
6733b39a
JK		 3690 kfree(phba->io_sgl_hndl_base);
3691 kfree(phba->eh_sgl_hndl_base);
3692 kfree(phba->cid_array);
3693 kfree(phba->ep_array);
3694}
3695
1282ab76
MC		 3696static void beiscsi_cleanup_task(struct iscsi_task *task)
3697{
3698 struct beiscsi_io_task *io_task = task->dd_data;
3699 struct iscsi_conn *conn = task->conn;
3700 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
3701 struct beiscsi_hba *phba = beiscsi_conn->phba;
3702 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
3703 struct hwi_wrb_context *pwrb_context;
3704 struct hwi_controller *phwi_ctrlr;
3705
3706 phwi_ctrlr = phba->phwi_ctrlr;
3707 pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid
3708 - phba->fw_config.iscsi_cid_start];
3709
3710 if (io_task->cmd_bhs) {
3711 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
3712 io_task->bhs_pa.u.a64.address);
3713 io_task->cmd_bhs = NULL;
3714 }
3715
3716 if (task->sc) {
3717 if (io_task->pwrb_handle) {
3718 free_wrb_handle(phba, pwrb_context,
3719 io_task->pwrb_handle);
3720 io_task->pwrb_handle = NULL;
3721 }
3722
3723 if (io_task->psgl_handle) {
3724 spin_lock(&phba->io_sgl_lock);
3725 free_io_sgl_handle(phba, io_task->psgl_handle);
3726 spin_unlock(&phba->io_sgl_lock);
3727 io_task->psgl_handle = NULL;
3728 }
3729 } else {
3730 if (!beiscsi_conn->login_in_progress) {
3731 if (io_task->pwrb_handle) {
3732 free_wrb_handle(phba, pwrb_context,
3733 io_task->pwrb_handle);
3734 io_task->pwrb_handle = NULL;
3735 }
3736 if (io_task->psgl_handle) {
3737 spin_lock(&phba->mgmt_sgl_lock);
3738 free_mgmt_sgl_handle(phba,
3739 io_task->psgl_handle);
3740 spin_unlock(&phba->mgmt_sgl_lock);
3741 io_task->psgl_handle = NULL;
3742 }
3743 }
3744 }
3745}
3746
6733b39a
JK		 3747void
3748beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
3749 struct beiscsi_offload_params *params)
3750{
3751 struct wrb_handle *pwrb_handle;
3752 struct iscsi_target_context_update_wrb *pwrb = NULL;
3753 struct be_mem_descriptor *mem_descr;
3754 struct beiscsi_hba *phba = beiscsi_conn->phba;
1282ab76
MC		 3755 struct iscsi_task *task = beiscsi_conn->task;
3756 struct iscsi_session *session = task->conn->session;
6733b39a
JK		 3757 u32 doorbell = 0;
3758
3759 /*
3760 * We can always use 0 here because it is reserved by libiscsi for
3761 * login/startup related tasks.
3762 */
1282ab76
MC		 3763 beiscsi_conn->login_in_progress = 0;
3764 spin_lock_bh(&session->lock);
3765 beiscsi_cleanup_task(task);
3766 spin_unlock_bh(&session->lock);
3767
7da50879 3768 pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid -
d5431488 3769 phba->fw_config.iscsi_cid_start));
6733b39a
JK		 3770 pwrb = (struct iscsi_target_context_update_wrb *)pwrb_handle->pwrb;
3771 memset(pwrb, 0, sizeof(*pwrb));
3772 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
3773 max_burst_length, pwrb, params->dw[offsetof
3774 (struct amap_beiscsi_offload_params,
3775 max_burst_length) / 32]);
3776 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
3777 max_send_data_segment_length, pwrb,
3778 params->dw[offsetof(struct amap_beiscsi_offload_params,
3779 max_send_data_segment_length) / 32]);
3780 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
3781 first_burst_length,
3782 pwrb,
3783 params->dw[offsetof(struct amap_beiscsi_offload_params,
3784 first_burst_length) / 32]);
3785
3786 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, erl, pwrb,
3787 (params->dw[offsetof(struct amap_beiscsi_offload_params,
3788 erl) / 32] & OFFLD_PARAMS_ERL));
3789 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, dde, pwrb,
3790 (params->dw[offsetof(struct amap_beiscsi_offload_params,
3791 dde) / 32] & OFFLD_PARAMS_DDE) >> 2);
3792 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, hde, pwrb,
3793 (params->dw[offsetof(struct amap_beiscsi_offload_params,
3794 hde) / 32] & OFFLD_PARAMS_HDE) >> 3);
3795 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ir2t, pwrb,
3796 (params->dw[offsetof(struct amap_beiscsi_offload_params,
3797 ir2t) / 32] & OFFLD_PARAMS_IR2T) >> 4);
3798 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, imd, pwrb,
3799 (params->dw[offsetof(struct amap_beiscsi_offload_params,
3800 imd) / 32] & OFFLD_PARAMS_IMD) >> 5);
3801 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, stat_sn,
3802 pwrb,
3803 (params->dw[offsetof(struct amap_beiscsi_offload_params,
3804 exp_statsn) / 32] + 1));
3805 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, type, pwrb,
3806 0x7);
3807 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, wrb_idx,
3808 pwrb, pwrb_handle->wrb_index);
3809 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ptr2nextwrb,
3810 pwrb, pwrb_handle->nxt_wrb_index);
3811 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
3812 session_state, pwrb, 0);
3813 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, compltonack,
3814 pwrb, 1);
3815 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, notpredblq,
3816 pwrb, 0);
3817 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, mode, pwrb,
3818 0);
3819
3820 mem_descr = phba->init_mem;
3821 mem_descr += ISCSI_MEM_GLOBAL_HEADER;
3822
3823 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
3824 pad_buffer_addr_hi, pwrb,
3825 mem_descr->mem_array[0].bus_address.u.a32.address_hi);
3826 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
3827 pad_buffer_addr_lo, pwrb,
3828 mem_descr->mem_array[0].bus_address.u.a32.address_lo);
3829
3830 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_target_context_update_wrb));
3831
3832 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 3833 doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
bfead3b2 3834 << DB_DEF_PDU_WRB_INDEX_SHIFT;
6733b39a
JK		 3835 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
3836
3837 iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
3838}
3839
3840static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
3841 int *index, int *age)
3842{
bfead3b2 3843 *index = (int)itt;
6733b39a
JK		 3844 if (age)
3845 *age = conn->session->age;
3846}
3847
3848/**
3849 * beiscsi_alloc_pdu - allocates pdu and related resources
3850 * @task: libiscsi task
3851 * @opcode: opcode of pdu for task
3852 *
3853 * This is called with the session lock held. It will allocate
3854 * the wrb and sgl if needed for the command. And it will prep
3855 * the pdu's itt. beiscsi_parse_pdu will later translate
3856 * the pdu itt to the libiscsi task itt.
3857 */
3858static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
3859{
3860 struct beiscsi_io_task *io_task = task->dd_data;
3861 struct iscsi_conn *conn = task->conn;
3862 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
3863 struct beiscsi_hba *phba = beiscsi_conn->phba;
3864 struct hwi_wrb_context *pwrb_context;
3865 struct hwi_controller *phwi_ctrlr;
3866 itt_t itt;
2afc95bf
JK		 3867 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
3868 dma_addr_t paddr;
6733b39a 3869
2afc95bf 3870 io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
bc7accec 3871 GFP_ATOMIC, &paddr);
2afc95bf
JK		 3872 if (!io_task->cmd_bhs)
3873 return -ENOMEM;
2afc95bf 3874 io_task->bhs_pa.u.a64.address = paddr;
bfead3b2 3875 io_task->libiscsi_itt = (itt_t)task->itt;
6733b39a
JK		 3876 io_task->conn = beiscsi_conn;
3877
3878 task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
3879 task->hdr_max = sizeof(struct be_cmd_bhs);
d2cecf0d 3880 io_task->psgl_handle = NULL;
3ec78271 3881 io_task->pwrb_handle = NULL;
6733b39a
JK		 3882
3883 if (task->sc) {
3884 spin_lock(&phba->io_sgl_lock);
3885 io_task->psgl_handle = alloc_io_sgl_handle(phba);
3886 spin_unlock(&phba->io_sgl_lock);
2afc95bf
JK		 3887 if (!io_task->psgl_handle)
3888 goto free_hndls;
d2cecf0d
JK		 3889 io_task->pwrb_handle = alloc_wrb_handle(phba,
3890 beiscsi_conn->beiscsi_conn_cid -
3891 phba->fw_config.iscsi_cid_start);
3892 if (!io_task->pwrb_handle)
3893 goto free_io_hndls;
6733b39a
JK		 3894 } else {
3895 io_task->scsi_cmnd = NULL;
d7aea67b 3896 if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
6733b39a
JK		 3897 if (!beiscsi_conn->login_in_progress) {
3898 spin_lock(&phba->mgmt_sgl_lock);
3899 io_task->psgl_handle = (struct sgl_handle *)
3900 alloc_mgmt_sgl_handle(phba);
3901 spin_unlock(&phba->mgmt_sgl_lock);
2afc95bf
JK		 3902 if (!io_task->psgl_handle)
3903 goto free_hndls;
3904
6733b39a
JK		 3905 beiscsi_conn->login_in_progress = 1;
3906 beiscsi_conn->plogin_sgl_handle =
3907 io_task->psgl_handle;
d2cecf0d
JK		 3908 io_task->pwrb_handle =
3909 alloc_wrb_handle(phba,
3910 beiscsi_conn->beiscsi_conn_cid -
3911 phba->fw_config.iscsi_cid_start);
3912 if (!io_task->pwrb_handle)
3913 goto free_io_hndls;
3914 beiscsi_conn->plogin_wrb_handle =
3915 io_task->pwrb_handle;
3916
6733b39a
JK		 3917 } else {
3918 io_task->psgl_handle =
3919 beiscsi_conn->plogin_sgl_handle;
d2cecf0d
JK		 3920 io_task->pwrb_handle =
3921 beiscsi_conn->plogin_wrb_handle;
6733b39a 3922 }
1282ab76 3923 beiscsi_conn->task = task;
6733b39a
JK		 3924 } else {
3925 spin_lock(&phba->mgmt_sgl_lock);
3926 io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
3927 spin_unlock(&phba->mgmt_sgl_lock);
2afc95bf
JK		 3928 if (!io_task->psgl_handle)
3929 goto free_hndls;
d2cecf0d
JK		 3930 io_task->pwrb_handle =
3931 alloc_wrb_handle(phba,
3932 beiscsi_conn->beiscsi_conn_cid -
3933 phba->fw_config.iscsi_cid_start);
3934 if (!io_task->pwrb_handle)
3935 goto free_mgmt_hndls;
3936
6733b39a
JK		 3937 }
3938 }
bfead3b2
JK		 3939 itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
3940 wrb_index << 16) | (unsigned int)
3941 (io_task->psgl_handle->sgl_index));
32951dd8 3942 io_task->pwrb_handle->pio_handle = task;
bfead3b2 3943
6733b39a
JK		 3944 io_task->cmd_bhs->iscsi_hdr.itt = itt;
3945 return 0;
2afc95bf 3946
d2cecf0d
JK		 3947free_io_hndls:
3948 spin_lock(&phba->io_sgl_lock);
3949 free_io_sgl_handle(phba, io_task->psgl_handle);
3950 spin_unlock(&phba->io_sgl_lock);
3951 goto free_hndls;
3952free_mgmt_hndls:
3953 spin_lock(&phba->mgmt_sgl_lock);
3954 free_mgmt_sgl_handle(phba, io_task->psgl_handle);
3955 spin_unlock(&phba->mgmt_sgl_lock);
2afc95bf
JK		 3956free_hndls:
3957 phwi_ctrlr = phba->phwi_ctrlr;
7da50879
JK		 3958 pwrb_context = &phwi_ctrlr->wrb_context[
3959 beiscsi_conn->beiscsi_conn_cid -
3960 phba->fw_config.iscsi_cid_start];
d2cecf0d
JK		 3961 if (io_task->pwrb_handle)
3962 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
2afc95bf
JK		 3963 io_task->pwrb_handle = NULL;
3964 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
3965 io_task->bhs_pa.u.a64.address);
1282ab76 3966 io_task->cmd_bhs = NULL;
457ff3b7 3967 SE_DEBUG(DBG_LVL_1, "Alloc of SGL_ICD Failed\n");
2afc95bf 3968 return -ENOMEM;
6733b39a
JK		 3969}
3970
6733b39a
JK		 3971static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
3972 unsigned int num_sg, unsigned int xferlen,
3973 unsigned int writedir)
3974{
3975
3976 struct beiscsi_io_task *io_task = task->dd_data;
3977 struct iscsi_conn *conn = task->conn;
3978 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
3979 struct beiscsi_hba *phba = beiscsi_conn->phba;
3980 struct iscsi_wrb *pwrb = NULL;
3981 unsigned int doorbell = 0;
3982
3983 pwrb = io_task->pwrb_handle->pwrb;
6733b39a
JK		 3984 io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
3985 io_task->bhs_len = sizeof(struct be_cmd_bhs);
3986
3987 if (writedir) {
6733b39a
JK		 3988 memset(&io_task->cmd_bhs->iscsi_data_pdu, 0, 48);
3989 AMAP_SET_BITS(struct amap_pdu_data_out, itt,
3990 &io_task->cmd_bhs->iscsi_data_pdu,
3991 (unsigned int)io_task->cmd_bhs->iscsi_hdr.itt);
3992 AMAP_SET_BITS(struct amap_pdu_data_out, opcode,
3993 &io_task->cmd_bhs->iscsi_data_pdu,
3994 ISCSI_OPCODE_SCSI_DATA_OUT);
3995 AMAP_SET_BITS(struct amap_pdu_data_out, final_bit,
3996 &io_task->cmd_bhs->iscsi_data_pdu, 1);
32951dd8
JK		 3997 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
3998 INI_WR_CMD);
6733b39a 3999 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
6733b39a 4000 } else {
32951dd8
JK		 4001 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4002 INI_RD_CMD);
6733b39a
JK		 4003 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
4004 }
4005 memcpy(&io_task->cmd_bhs->iscsi_data_pdu.
4006 dw[offsetof(struct amap_pdu_data_out, lun) / 32],
516f43a2 4007 &io_task->cmd_bhs->iscsi_hdr.lun, sizeof(struct scsi_lun));
6733b39a
JK		 4008
4009 AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
dc63aac6
JK		 4010 cpu_to_be16(*(unsigned short *)
4011 &io_task->cmd_bhs->iscsi_hdr.lun));
6733b39a
JK		 4012 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
4013 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
4014 io_task->pwrb_handle->wrb_index);
4015 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
4016 be32_to_cpu(task->cmdsn));
4017 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
4018 io_task->psgl_handle->sgl_index);
4019
4020 hwi_write_sgl(pwrb, sg, num_sg, io_task);
4021
4022 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
4023 io_task->pwrb_handle->nxt_wrb_index);
4024 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4025
4026 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 4027 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 4028 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
4029 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
4030
4031 iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
4032 return 0;
4033}
4034
4035static int beiscsi_mtask(struct iscsi_task *task)
4036{
dafab8e0 4037 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 4038 struct iscsi_conn *conn = task->conn;
4039 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4040 struct beiscsi_hba *phba = beiscsi_conn->phba;
4041 struct iscsi_wrb *pwrb = NULL;
4042 unsigned int doorbell = 0;
dafab8e0 4043 unsigned int cid;
6733b39a 4044
bfead3b2 4045 cid = beiscsi_conn->beiscsi_conn_cid;
6733b39a 4046 pwrb = io_task->pwrb_handle->pwrb;
caf818f1 4047 memset(pwrb, 0, sizeof(*pwrb));
6733b39a
JK		 4048 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
4049 be32_to_cpu(task->cmdsn));
4050 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
4051 io_task->pwrb_handle->wrb_index);
4052 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
4053 io_task->psgl_handle->sgl_index);
dafab8e0 4054
6733b39a
JK		 4055 switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
4056 case ISCSI_OP_LOGIN:
32951dd8
JK		 4057 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4058 TGT_DM_CMD);
6733b39a
JK		 4059 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
4060 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
4061 hwi_write_buffer(pwrb, task);
4062 break;
4063 case ISCSI_OP_NOOP_OUT:
1390b01b
JK		 4064 if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
4065 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4066 TGT_DM_CMD);
4067 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt,
4068 pwrb, 0);
685e16fd 4069 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 1);
1390b01b
JK		 4070 } else {
4071 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4072 INI_RD_CMD);
685e16fd 4073 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
1390b01b 4074 }
6733b39a
JK		 4075 hwi_write_buffer(pwrb, task);
4076 break;
4077 case ISCSI_OP_TEXT:
32951dd8 4078 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
b30c6dab 4079 TGT_DM_CMD);
0ecb0b45 4080 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
6733b39a
JK		 4081 hwi_write_buffer(pwrb, task);
4082 break;
4083 case ISCSI_OP_SCSI_TMFUNC:
32951dd8
JK		 4084 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4085 INI_TMF_CMD);
6733b39a
JK		 4086 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
4087 hwi_write_buffer(pwrb, task);
4088 break;
4089 case ISCSI_OP_LOGOUT:
4090 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
4091 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
dafab8e0 4092 HWH_TYPE_LOGOUT);
6733b39a
JK		 4093 hwi_write_buffer(pwrb, task);
4094 break;
4095
4096 default:
457ff3b7 4097 SE_DEBUG(DBG_LVL_1, "opcode =%d Not supported\n",
6733b39a
JK		 4098 task->hdr->opcode & ISCSI_OPCODE_MASK);
4099 return -EINVAL;
4100 }
4101
4102 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
51a46250 4103 task->data_count);
6733b39a
JK		 4104 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
4105 io_task->pwrb_handle->nxt_wrb_index);
4106 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4107
bfead3b2 4108 doorbell |= cid & DB_WRB_POST_CID_MASK;
32951dd8 4109 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 4110 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
4111 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
4112 iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
4113 return 0;
4114}
4115
4116static int beiscsi_task_xmit(struct iscsi_task *task)
4117{
6733b39a
JK		 4118 struct beiscsi_io_task *io_task = task->dd_data;
4119 struct scsi_cmnd *sc = task->sc;
6733b39a
JK		 4120 struct scatterlist *sg;
4121 int num_sg;
4122 unsigned int writedir = 0, xferlen = 0;
4123
6733b39a
JK		 4124 if (!sc)
4125 return beiscsi_mtask(task);
4126
4127 io_task->scsi_cmnd = sc;
4128 num_sg = scsi_dma_map(sc);
4129 if (num_sg < 0) {
4130 SE_DEBUG(DBG_LVL_1, " scsi_dma_map Failed\n")
4131 return num_sg;
4132 }
6733b39a
JK		 4133 xferlen = scsi_bufflen(sc);
4134 sg = scsi_sglist(sc);
4135 if (sc->sc_data_direction == DMA_TO_DEVICE) {
4136 writedir = 1;
457ff3b7 4137 SE_DEBUG(DBG_LVL_4, "task->imm_count=0x%08x\n",
6733b39a
JK		 4138 task->imm_count);
4139 } else
4140 writedir = 0;
4141 return beiscsi_iotask(task, sg, num_sg, xferlen, writedir);
4142}
4143
25602c97 4144static void beiscsi_quiesce(struct beiscsi_hba *phba)
6733b39a 4145{
bfead3b2
JK		 4146 struct hwi_controller *phwi_ctrlr;
4147 struct hwi_context_memory *phwi_context;
4148 struct be_eq_obj *pbe_eq;
4149 unsigned int i, msix_vec;
e9b91193
JK		 4150 u8 *real_offset = 0;
4151 u32 value = 0;
6733b39a 4152
bfead3b2
JK		 4153 phwi_ctrlr = phba->phwi_ctrlr;
4154 phwi_context = phwi_ctrlr->phwi_ctxt;
6733b39a 4155 hwi_disable_intr(phba);
bfead3b2
JK		 4156 if (phba->msix_enabled) {
4157 for (i = 0; i <= phba->num_cpus; i++) {
4158 msix_vec = phba->msix_entries[i].vector;
4159 free_irq(msix_vec, &phwi_context->be_eq[i]);
8fcfb210 4160 kfree(phba->msi_name[i]);
bfead3b2
JK		 4161 }
4162 } else
4163 if (phba->pcidev->irq)
4164 free_irq(phba->pcidev->irq, phba);
4165 pci_disable_msix(phba->pcidev);
6733b39a
JK		 4166 destroy_workqueue(phba->wq);
4167 if (blk_iopoll_enabled)
bfead3b2
JK		 4168 for (i = 0; i < phba->num_cpus; i++) {
4169 pbe_eq = &phwi_context->be_eq[i];
4170 blk_iopoll_disable(&pbe_eq->iopoll);
4171 }
6733b39a
JK		 4172
4173 beiscsi_clean_port(phba);
4174 beiscsi_free_mem(phba);
e9b91193
JK		 4175 real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
4176
4177 value = readl((void *)real_offset);
4178
4179 if (value & 0x00010000) {
4180 value &= 0xfffeffff;
4181 writel(value, (void *)real_offset);
4182 }
6733b39a
JK		 4183 beiscsi_unmap_pci_function(phba);
4184 pci_free_consistent(phba->pcidev,
4185 phba->ctrl.mbox_mem_alloced.size,
4186 phba->ctrl.mbox_mem_alloced.va,
4187 phba->ctrl.mbox_mem_alloced.dma);
25602c97
JK		 4188}
4189
4190static void beiscsi_remove(struct pci_dev *pcidev)
4191{
4192
4193 struct beiscsi_hba *phba = NULL;
4194
4195 phba = pci_get_drvdata(pcidev);
4196 if (!phba) {
4197 dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
4198 return;
4199 }
4200
4201 beiscsi_quiesce(phba);
9d045163 4202 iscsi_boot_destroy_kset(phba->boot_kset);
6733b39a
JK		 4203 iscsi_host_remove(phba->shost);
4204 pci_dev_put(phba->pcidev);
4205 iscsi_host_free(phba->shost);
8dce69ff 4206 pci_disable_device(pcidev);
6733b39a
JK		 4207}
4208
25602c97
JK		 4209static void beiscsi_shutdown(struct pci_dev *pcidev)
4210{
4211
4212 struct beiscsi_hba *phba = NULL;
4213
4214 phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
4215 if (!phba) {
4216 dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
4217 return;
4218 }
4219
4220 beiscsi_quiesce(phba);
8dce69ff 4221 pci_disable_device(pcidev);
25602c97
JK		 4222}
4223
bfead3b2
JK		 4224static void beiscsi_msix_enable(struct beiscsi_hba *phba)
4225{
4226 int i, status;
4227
4228 for (i = 0; i <= phba->num_cpus; i++)
4229 phba->msix_entries[i].entry = i;
4230
4231 status = pci_enable_msix(phba->pcidev, phba->msix_entries,
4232 (phba->num_cpus + 1));
4233 if (!status)
4234 phba->msix_enabled = true;
4235
4236 return;
4237}
4238
6733b39a
JK		 4239static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev,
4240 const struct pci_device_id *id)
4241{
4242 struct beiscsi_hba *phba = NULL;
bfead3b2
JK		 4243 struct hwi_controller *phwi_ctrlr;
4244 struct hwi_context_memory *phwi_context;
4245 struct be_eq_obj *pbe_eq;
238f6b72 4246 int ret, num_cpus, i;
e9b91193
JK		 4247 u8 *real_offset = 0;
4248 u32 value = 0;
6733b39a
JK		 4249
4250 ret = beiscsi_enable_pci(pcidev);
4251 if (ret < 0) {
82284c09
DC		 4252 dev_err(&pcidev->dev, "beiscsi_dev_probe-"
4253 " Failed to enable pci device\n");
6733b39a
JK		 4254 return ret;
4255 }
4256
4257 phba = beiscsi_hba_alloc(pcidev);
4258 if (!phba) {
4259 dev_err(&pcidev->dev, "beiscsi_dev_probe-"
457ff3b7 4260 " Failed in beiscsi_hba_alloc\n");
6733b39a
JK		 4261 goto disable_pci;
4262 }
4263
f98c96b0
JK		 4264 switch (pcidev->device) {
4265 case BE_DEVICE_ID1:
4266 case OC_DEVICE_ID1:
4267 case OC_DEVICE_ID2:
4268 phba->generation = BE_GEN2;
4269 break;
4270 case BE_DEVICE_ID2:
4271 case OC_DEVICE_ID3:
4272 phba->generation = BE_GEN3;
4273 break;
4274 default:
4275 phba->generation = 0;
4276 }
4277
bfead3b2
JK		 4278 if (enable_msix)
4279 num_cpus = find_num_cpus();
4280 else
4281 num_cpus = 1;
4282 phba->num_cpus = num_cpus;
457ff3b7 4283 SE_DEBUG(DBG_LVL_8, "num_cpus = %d\n", phba->num_cpus);
bfead3b2
JK		 4284
4285 if (enable_msix)
4286 beiscsi_msix_enable(phba);
6733b39a
JK		 4287 ret = be_ctrl_init(phba, pcidev);
4288 if (ret) {
4289 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
4290 "Failed in be_ctrl_init\n");
4291 goto hba_free;
4292 }
4293
e9b91193
JK		 4294 if (!num_hba) {
4295 real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
4296 value = readl((void *)real_offset);
4297 if (value & 0x00010000) {
4298 gcrashmode++;
4299 shost_printk(KERN_ERR, phba->shost,
4300 "Loading Driver in crashdump mode\n");
e5285860 4301 ret = beiscsi_cmd_reset_function(phba);
e9b91193
JK		 4302 if (ret) {
4303 shost_printk(KERN_ERR, phba->shost,
4304 "Reset Failed. Aborting Crashdump\n");
4305 goto hba_free;
4306 }
4307 ret = be_chk_reset_complete(phba);
4308 if (ret) {
4309 shost_printk(KERN_ERR, phba->shost,
4310 "Failed to get out of reset."
4311 "Aborting Crashdump\n");
4312 goto hba_free;
4313 }
4314 } else {
4315 value |= 0x00010000;
4316 writel(value, (void *)real_offset);
4317 num_hba++;
4318 }
4319 }
4320
6733b39a
JK		 4321 spin_lock_init(&phba->io_sgl_lock);
4322 spin_lock_init(&phba->mgmt_sgl_lock);
4323 spin_lock_init(&phba->isr_lock);
7da50879
JK		 4324 ret = mgmt_get_fw_config(&phba->ctrl, phba);
4325 if (ret != 0) {
4326 shost_printk(KERN_ERR, phba->shost,
4327 "Error getting fw config\n");
4328 goto free_port;
4329 }
4330 phba->shost->max_id = phba->fw_config.iscsi_cid_count;
6733b39a 4331 beiscsi_get_params(phba);
aa874f07 4332 phba->shost->can_queue = phba->params.ios_per_ctrl;
6733b39a
JK		 4333 ret = beiscsi_init_port(phba);
4334 if (ret < 0) {
4335 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
4336 "Failed in beiscsi_init_port\n");
4337 goto free_port;
4338 }
4339
756d29c8
JK		 4340 for (i = 0; i < MAX_MCC_CMD ; i++) {
4341 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
4342 phba->ctrl.mcc_tag[i] = i + 1;
4343 phba->ctrl.mcc_numtag[i + 1] = 0;
4344 phba->ctrl.mcc_tag_available++;
4345 }
4346
4347 phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
4348
6733b39a
JK		 4349 snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_q_irq%u",
4350 phba->shost->host_no);
278274d5 4351 phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1);
6733b39a
JK		 4352 if (!phba->wq) {
4353 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
4354 "Failed to allocate work queue\n");
4355 goto free_twq;
4356 }
4357
4358 INIT_WORK(&phba->work_cqs, beiscsi_process_all_cqs);
4359
bfead3b2
JK		 4360 phwi_ctrlr = phba->phwi_ctrlr;
4361 phwi_context = phwi_ctrlr->phwi_ctxt;
6733b39a 4362 if (blk_iopoll_enabled) {
bfead3b2
JK		 4363 for (i = 0; i < phba->num_cpus; i++) {
4364 pbe_eq = &phwi_context->be_eq[i];
4365 blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
4366 be_iopoll);
4367 blk_iopoll_enable(&pbe_eq->iopoll);
4368 }
6733b39a 4369 }
6733b39a
JK		 4370 ret = beiscsi_init_irqs(phba);
4371 if (ret < 0) {
4372 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
4373 "Failed to beiscsi_init_irqs\n");
4374 goto free_blkenbld;
4375 }
238f6b72 4376 hwi_enable_intr(phba);
f457a46f
MC		 4377
4378 if (beiscsi_setup_boot_info(phba))
4379 /*
4380 * log error but continue, because we may not be using
4381 * iscsi boot.
4382 */
4383 shost_printk(KERN_ERR, phba->shost, "Could not set up "
4384 "iSCSI boot info.");
4385
457ff3b7 4386 SE_DEBUG(DBG_LVL_8, "\n\n\n SUCCESS - DRIVER LOADED\n\n\n");
6733b39a
JK		 4387 return 0;
4388
6733b39a
JK		 4389free_blkenbld:
4390 destroy_workqueue(phba->wq);
4391 if (blk_iopoll_enabled)
bfead3b2
JK		 4392 for (i = 0; i < phba->num_cpus; i++) {
4393 pbe_eq = &phwi_context->be_eq[i];
4394 blk_iopoll_disable(&pbe_eq->iopoll);
4395 }
6733b39a
JK		 4396free_twq:
4397 beiscsi_clean_port(phba);
4398 beiscsi_free_mem(phba);
4399free_port:
e9b91193
JK		 4400 real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
4401
4402 value = readl((void *)real_offset);
4403
4404 if (value & 0x00010000) {
4405 value &= 0xfffeffff;
4406 writel(value, (void *)real_offset);
4407 }
4408
6733b39a
JK		 4409 pci_free_consistent(phba->pcidev,
4410 phba->ctrl.mbox_mem_alloced.size,
4411 phba->ctrl.mbox_mem_alloced.va,
4412 phba->ctrl.mbox_mem_alloced.dma);
4413 beiscsi_unmap_pci_function(phba);
4414hba_free:
238f6b72
JK		 4415 if (phba->msix_enabled)
4416 pci_disable_msix(phba->pcidev);
6733b39a
JK		 4417 iscsi_host_remove(phba->shost);
4418 pci_dev_put(phba->pcidev);
4419 iscsi_host_free(phba->shost);
4420disable_pci:
4421 pci_disable_device(pcidev);
4422 return ret;
4423}
4424
4425struct iscsi_transport beiscsi_iscsi_transport = {
4426 .owner = THIS_MODULE,
4427 .name = DRV_NAME,
9db0fb3a 4428 .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
6733b39a 4429 CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
6733b39a
JK		 4430 .create_session = beiscsi_session_create,
4431 .destroy_session = beiscsi_session_destroy,
4432 .create_conn = beiscsi_conn_create,
4433 .bind_conn = beiscsi_conn_bind,
4434 .destroy_conn = iscsi_conn_teardown,
3128c6c7 4435 .attr_is_visible = be2iscsi_attr_is_visible,
6733b39a 4436 .set_param = beiscsi_set_param,
c7f7fd5b 4437 .get_conn_param = iscsi_conn_get_param,
6733b39a
JK		 4438 .get_session_param = iscsi_session_get_param,
4439 .get_host_param = beiscsi_get_host_param,
4440 .start_conn = beiscsi_conn_start,
fa95d206 4441 .stop_conn = iscsi_conn_stop,
6733b39a
JK		 4442 .send_pdu = iscsi_conn_send_pdu,
4443 .xmit_task = beiscsi_task_xmit,
4444 .cleanup_task = beiscsi_cleanup_task,
4445 .alloc_pdu = beiscsi_alloc_pdu,
4446 .parse_pdu_itt = beiscsi_parse_pdu,
4447 .get_stats = beiscsi_conn_get_stats,
c7f7fd5b 4448 .get_ep_param = beiscsi_ep_get_param,
6733b39a
JK		 4449 .ep_connect = beiscsi_ep_connect,
4450 .ep_poll = beiscsi_ep_poll,
4451 .ep_disconnect = beiscsi_ep_disconnect,
4452 .session_recovery_timedout = iscsi_session_recovery_timedout,
4453};
4454
4455static struct pci_driver beiscsi_pci_driver = {
4456 .name = DRV_NAME,
4457 .probe = beiscsi_dev_probe,
4458 .remove = beiscsi_remove,
25602c97 4459 .shutdown = beiscsi_shutdown,
6733b39a
JK		 4460 .id_table = beiscsi_pci_id_table
4461};
4462
bfead3b2 4463
6733b39a
JK		 4464static int __init beiscsi_module_init(void)
4465{
4466 int ret;
4467
4468 beiscsi_scsi_transport =
4469 iscsi_register_transport(&beiscsi_iscsi_transport);
4470 if (!beiscsi_scsi_transport) {
4471 SE_DEBUG(DBG_LVL_1,
4472 "beiscsi_module_init - Unable to register beiscsi"
4473 "transport.\n");
f55a24f2 4474 return -ENOMEM;
6733b39a 4475 }
457ff3b7 4476 SE_DEBUG(DBG_LVL_8, "In beiscsi_module_init, tt=%p\n",
6733b39a
JK		 4477 &beiscsi_iscsi_transport);
4478
4479 ret = pci_register_driver(&beiscsi_pci_driver);
4480 if (ret) {
4481 SE_DEBUG(DBG_LVL_1,
4482 "beiscsi_module_init - Unable to register"
4483 "beiscsi pci driver.\n");
4484 goto unregister_iscsi_transport;
4485 }
4486 return 0;
4487
4488unregister_iscsi_transport:
4489 iscsi_unregister_transport(&beiscsi_iscsi_transport);
4490 return ret;
4491}
4492
4493static void __exit beiscsi_module_exit(void)
4494{
4495 pci_unregister_driver(&beiscsi_pci_driver);
4496 iscsi_unregister_transport(&beiscsi_iscsi_transport);
4497}
4498
4499module_init(beiscsi_module_init);
4500module_exit(beiscsi_module_exit);
ubuntu-bionic-kernel mirror