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[SCSI] be2iscsi: Fix in the Asynchronous Code Path
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / be2iscsi / be_main.c
CommitLineData
6733b39a 1/**
255fa9a3 2 * Copyright (C) 2005 - 2011 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
255fa9a3 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
6733b39a
JK		 11 *
12 * Contact Information:
255fa9a3 13 * linux-drivers@emulex.com
6733b39a 14 *
255fa9a3
JK		 15 * Emulex
16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a 18 */
255fa9a3 19
6733b39a
JK		 20#include <linux/reboot.h>
21#include <linux/delay.h>
5a0e3ad6 22#include <linux/slab.h>
6733b39a
JK		 23#include <linux/interrupt.h>
24#include <linux/blkdev.h>
25#include <linux/pci.h>
26#include <linux/string.h>
27#include <linux/kernel.h>
28#include <linux/semaphore.h>
c7acc5b8 29#include <linux/iscsi_boot_sysfs.h>
acf3368f 30#include <linux/module.h>
6733b39a
JK		 31
32#include <scsi/libiscsi.h>
33#include <scsi/scsi_transport_iscsi.h>
34#include <scsi/scsi_transport.h>
35#include <scsi/scsi_cmnd.h>
36#include <scsi/scsi_device.h>
37#include <scsi/scsi_host.h>
38#include <scsi/scsi.h>
39#include "be_main.h"
40#include "be_iscsi.h"
41#include "be_mgmt.h"
42
43static unsigned int be_iopoll_budget = 10;
44static unsigned int be_max_phys_size = 64;
bfead3b2 45static unsigned int enable_msix = 1;
e9b91193
JK		 46static unsigned int gcrashmode = 0;
47static unsigned int num_hba = 0;
6733b39a
JK		 48
49MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
50MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
51MODULE_AUTHOR("ServerEngines Corporation");
52MODULE_LICENSE("GPL");
53module_param(be_iopoll_budget, int, 0);
54module_param(enable_msix, int, 0);
55module_param(be_max_phys_size, uint, S_IRUGO);
56MODULE_PARM_DESC(be_max_phys_size, "Maximum Size (In Kilobytes) of physically"
57 "contiguous memory that can be allocated."
58 "Range is 16 - 128");
59
60static int beiscsi_slave_configure(struct scsi_device *sdev)
61{
62 blk_queue_max_segment_size(sdev->request_queue, 65536);
63 return 0;
64}
65
4183122d
JK		 66static int beiscsi_eh_abort(struct scsi_cmnd *sc)
67{
68 struct iscsi_cls_session *cls_session;
69 struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
70 struct beiscsi_io_task *aborted_io_task;
71 struct iscsi_conn *conn;
72 struct beiscsi_conn *beiscsi_conn;
73 struct beiscsi_hba *phba;
74 struct iscsi_session *session;
75 struct invalidate_command_table *inv_tbl;
3cbb7a74 76 struct be_dma_mem nonemb_cmd;
4183122d
JK		 77 unsigned int cid, tag, num_invalidate;
78
79 cls_session = starget_to_session(scsi_target(sc->device));
80 session = cls_session->dd_data;
81
82 spin_lock_bh(&session->lock);
83 if (!aborted_task || !aborted_task->sc) {
84 /* we raced */
85 spin_unlock_bh(&session->lock);
86 return SUCCESS;
87 }
88
89 aborted_io_task = aborted_task->dd_data;
90 if (!aborted_io_task->scsi_cmnd) {
91 /* raced or invalid command */
92 spin_unlock_bh(&session->lock);
93 return SUCCESS;
94 }
95 spin_unlock_bh(&session->lock);
96 conn = aborted_task->conn;
97 beiscsi_conn = conn->dd_data;
98 phba = beiscsi_conn->phba;
99
100 /* invalidate iocb */
101 cid = beiscsi_conn->beiscsi_conn_cid;
102 inv_tbl = phba->inv_tbl;
103 memset(inv_tbl, 0x0, sizeof(*inv_tbl));
104 inv_tbl->cid = cid;
105 inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
106 num_invalidate = 1;
3cbb7a74
JK		 107 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
108 sizeof(struct invalidate_commands_params_in),
109 &nonemb_cmd.dma);
110 if (nonemb_cmd.va == NULL) {
111 SE_DEBUG(DBG_LVL_1,
112 "Failed to allocate memory for"
113 "mgmt_invalidate_icds\n");
114 return FAILED;
115 }
116 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
117
118 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
119 cid, &nonemb_cmd);
4183122d
JK		 120 if (!tag) {
121 shost_printk(KERN_WARNING, phba->shost,
122 "mgmt_invalidate_icds could not be"
123 " submitted\n");
3cbb7a74
JK		 124 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
125 nonemb_cmd.va, nonemb_cmd.dma);
126
4183122d
JK		 127 return FAILED;
128 } else {
129 wait_event_interruptible(phba->ctrl.mcc_wait[tag],
130 phba->ctrl.mcc_numtag[tag]);
131 free_mcc_tag(&phba->ctrl, tag);
132 }
3cbb7a74
JK		 133 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
134 nonemb_cmd.va, nonemb_cmd.dma);
4183122d
JK		 135 return iscsi_eh_abort(sc);
136}
137
138static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
139{
140 struct iscsi_task *abrt_task;
141 struct beiscsi_io_task *abrt_io_task;
142 struct iscsi_conn *conn;
143 struct beiscsi_conn *beiscsi_conn;
144 struct beiscsi_hba *phba;
145 struct iscsi_session *session;
146 struct iscsi_cls_session *cls_session;
147 struct invalidate_command_table *inv_tbl;
3cbb7a74 148 struct be_dma_mem nonemb_cmd;
4183122d
JK		 149 unsigned int cid, tag, i, num_invalidate;
150 int rc = FAILED;
151
152 /* invalidate iocbs */
153 cls_session = starget_to_session(scsi_target(sc->device));
154 session = cls_session->dd_data;
155 spin_lock_bh(&session->lock);
156 if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN)
157 goto unlock;
158
159 conn = session->leadconn;
160 beiscsi_conn = conn->dd_data;
161 phba = beiscsi_conn->phba;
162 cid = beiscsi_conn->beiscsi_conn_cid;
163 inv_tbl = phba->inv_tbl;
164 memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
165 num_invalidate = 0;
166 for (i = 0; i < conn->session->cmds_max; i++) {
167 abrt_task = conn->session->cmds[i];
168 abrt_io_task = abrt_task->dd_data;
169 if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
170 continue;
171
172 if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
173 continue;
174
175 inv_tbl->cid = cid;
176 inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
177 num_invalidate++;
178 inv_tbl++;
179 }
180 spin_unlock_bh(&session->lock);
181 inv_tbl = phba->inv_tbl;
182
3cbb7a74
JK		 183 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
184 sizeof(struct invalidate_commands_params_in),
185 &nonemb_cmd.dma);
186 if (nonemb_cmd.va == NULL) {
187 SE_DEBUG(DBG_LVL_1,
188 "Failed to allocate memory for"
189 "mgmt_invalidate_icds\n");
190 return FAILED;
191 }
192 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
193 memset(nonemb_cmd.va, 0, nonemb_cmd.size);
194 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
195 cid, &nonemb_cmd);
4183122d
JK		 196 if (!tag) {
197 shost_printk(KERN_WARNING, phba->shost,
198 "mgmt_invalidate_icds could not be"
199 " submitted\n");
3cbb7a74
JK		 200 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
201 nonemb_cmd.va, nonemb_cmd.dma);
4183122d
JK		 202 return FAILED;
203 } else {
204 wait_event_interruptible(phba->ctrl.mcc_wait[tag],
205 phba->ctrl.mcc_numtag[tag]);
206 free_mcc_tag(&phba->ctrl, tag);
207 }
3cbb7a74
JK		 208 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
209 nonemb_cmd.va, nonemb_cmd.dma);
4183122d
JK		 210 return iscsi_eh_device_reset(sc);
211unlock:
212 spin_unlock_bh(&session->lock);
213 return rc;
214}
215
c7acc5b8
JK		 216static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
217{
218 struct beiscsi_hba *phba = data;
f457a46f
MC		 219 struct mgmt_session_info *boot_sess = &phba->boot_sess;
220 struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
c7acc5b8
JK		 221 char *str = buf;
222 int rc;
223
224 switch (type) {
225 case ISCSI_BOOT_TGT_NAME:
226 rc = sprintf(buf, "%.*s\n",
f457a46f
MC		 227 (int)strlen(boot_sess->target_name),
228 (char *)&boot_sess->target_name);
c7acc5b8
JK		 229 break;
230 case ISCSI_BOOT_TGT_IP_ADDR:
f457a46f 231 if (boot_conn->dest_ipaddr.ip_type == 0x1)
c7acc5b8 232 rc = sprintf(buf, "%pI4\n",
f457a46f 233 (char *)&boot_conn->dest_ipaddr.ip_address);
c7acc5b8
JK		 234 else
235 rc = sprintf(str, "%pI6\n",
f457a46f 236 (char *)&boot_conn->dest_ipaddr.ip_address);
c7acc5b8
JK		 237 break;
238 case ISCSI_BOOT_TGT_PORT:
f457a46f 239 rc = sprintf(str, "%d\n", boot_conn->dest_port);
c7acc5b8
JK		 240 break;
241
242 case ISCSI_BOOT_TGT_CHAP_NAME:
243 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 244 boot_conn->negotiated_login_options.auth_data.chap.
245 target_chap_name_length,
246 (char *)&boot_conn->negotiated_login_options.
247 auth_data.chap.target_chap_name);
c7acc5b8
JK		 248 break;
249 case ISCSI_BOOT_TGT_CHAP_SECRET:
250 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 251 boot_conn->negotiated_login_options.auth_data.chap.
252 target_secret_length,
253 (char *)&boot_conn->negotiated_login_options.
254 auth_data.chap.target_secret);
c7acc5b8
JK		 255 break;
256 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
257 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 258 boot_conn->negotiated_login_options.auth_data.chap.
259 intr_chap_name_length,
260 (char *)&boot_conn->negotiated_login_options.
261 auth_data.chap.intr_chap_name);
c7acc5b8
JK		 262 break;
263 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
f457a46f
MC		 264 rc = sprintf(str, "%.*s\n",
265 boot_conn->negotiated_login_options.auth_data.chap.
266 intr_secret_length,
267 (char *)&boot_conn->negotiated_login_options.
268 auth_data.chap.intr_secret);
c7acc5b8
JK		 269 break;
270 case ISCSI_BOOT_TGT_FLAGS:
f457a46f 271 rc = sprintf(str, "2\n");
c7acc5b8
JK		 272 break;
273 case ISCSI_BOOT_TGT_NIC_ASSOC:
f457a46f 274 rc = sprintf(str, "0\n");
c7acc5b8
JK		 275 break;
276 default:
277 rc = -ENOSYS;
278 break;
279 }
280 return rc;
281}
282
283static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
284{
285 struct beiscsi_hba *phba = data;
286 char *str = buf;
287 int rc;
288
289 switch (type) {
290 case ISCSI_BOOT_INI_INITIATOR_NAME:
291 rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
292 break;
293 default:
294 rc = -ENOSYS;
295 break;
296 }
297 return rc;
298}
299
300static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
301{
302 struct beiscsi_hba *phba = data;
303 char *str = buf;
304 int rc;
305
306 switch (type) {
307 case ISCSI_BOOT_ETH_FLAGS:
f457a46f 308 rc = sprintf(str, "2\n");
c7acc5b8
JK		 309 break;
310 case ISCSI_BOOT_ETH_INDEX:
f457a46f 311 rc = sprintf(str, "0\n");
c7acc5b8
JK		 312 break;
313 case ISCSI_BOOT_ETH_MAC:
314 rc = beiscsi_get_macaddr(buf, phba);
315 if (rc < 0) {
316 SE_DEBUG(DBG_LVL_1, "beiscsi_get_macaddr Failed\n");
317 return rc;
318 }
319 break;
320 default:
321 rc = -ENOSYS;
322 break;
323 }
324 return rc;
325}
326
327
587a1f16 328static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
c7acc5b8 329{
587a1f16 330 umode_t rc;
c7acc5b8
JK		 331
332 switch (type) {
333 case ISCSI_BOOT_TGT_NAME:
334 case ISCSI_BOOT_TGT_IP_ADDR:
335 case ISCSI_BOOT_TGT_PORT:
336 case ISCSI_BOOT_TGT_CHAP_NAME:
337 case ISCSI_BOOT_TGT_CHAP_SECRET:
338 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
339 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
340 case ISCSI_BOOT_TGT_NIC_ASSOC:
341 case ISCSI_BOOT_TGT_FLAGS:
342 rc = S_IRUGO;
343 break;
344 default:
345 rc = 0;
346 break;
347 }
348 return rc;
349}
350
587a1f16 351static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
c7acc5b8 352{
587a1f16 353 umode_t rc;
c7acc5b8
JK		 354
355 switch (type) {
356 case ISCSI_BOOT_INI_INITIATOR_NAME:
357 rc = S_IRUGO;
358 break;
359 default:
360 rc = 0;
361 break;
362 }
363 return rc;
364}
365
366
587a1f16 367static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
c7acc5b8 368{
587a1f16 369 umode_t rc;
c7acc5b8
JK		 370
371 switch (type) {
372 case ISCSI_BOOT_ETH_FLAGS:
373 case ISCSI_BOOT_ETH_MAC:
374 case ISCSI_BOOT_ETH_INDEX:
375 rc = S_IRUGO;
376 break;
377 default:
378 rc = 0;
379 break;
380 }
381 return rc;
382}
383
bfead3b2
JK		 384/*------------------- PCI Driver operations and data ----------------- */
385static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
386 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
f98c96b0 387 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
bfead3b2
JK		 388 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
389 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
390 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
bfead3b2
JK		 391 { 0 }
392};
393MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
394
6733b39a
JK		 395static struct scsi_host_template beiscsi_sht = {
396 .module = THIS_MODULE,
397 .name = "ServerEngines 10Gbe open-iscsi Initiator Driver",
398 .proc_name = DRV_NAME,
399 .queuecommand = iscsi_queuecommand,
6733b39a
JK		 400 .change_queue_depth = iscsi_change_queue_depth,
401 .slave_configure = beiscsi_slave_configure,
402 .target_alloc = iscsi_target_alloc,
4183122d
JK		 403 .eh_abort_handler = beiscsi_eh_abort,
404 .eh_device_reset_handler = beiscsi_eh_device_reset,
309ce156 405 .eh_target_reset_handler = iscsi_eh_session_reset,
6733b39a
JK		 406 .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
407 .can_queue = BE2_IO_DEPTH,
408 .this_id = -1,
409 .max_sectors = BEISCSI_MAX_SECTORS,
410 .cmd_per_lun = BEISCSI_CMD_PER_LUN,
411 .use_clustering = ENABLE_CLUSTERING,
412};
6733b39a 413
bfead3b2 414static struct scsi_transport_template *beiscsi_scsi_transport;
6733b39a
JK		 415
416static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
417{
418 struct beiscsi_hba *phba;
419 struct Scsi_Host *shost;
420
421 shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
422 if (!shost) {
423 dev_err(&pcidev->dev, "beiscsi_hba_alloc -"
457ff3b7 424 "iscsi_host_alloc failed\n");
6733b39a
JK		 425 return NULL;
426 }
427 shost->dma_boundary = pcidev->dma_mask;
428 shost->max_id = BE2_MAX_SESSIONS;
429 shost->max_channel = 0;
430 shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
431 shost->max_lun = BEISCSI_NUM_MAX_LUN;
432 shost->transportt = beiscsi_scsi_transport;
6733b39a
JK		 433 phba = iscsi_host_priv(shost);
434 memset(phba, 0, sizeof(*phba));
435 phba->shost = shost;
436 phba->pcidev = pci_dev_get(pcidev);
2807afb7 437 pci_set_drvdata(pcidev, phba);
6733b39a
JK		 438
439 if (iscsi_host_add(shost, &phba->pcidev->dev))
440 goto free_devices;
c7acc5b8 441
6733b39a
JK		 442 return phba;
443
444free_devices:
445 pci_dev_put(phba->pcidev);
446 iscsi_host_free(phba->shost);
447 return NULL;
448}
449
450static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
451{
452 if (phba->csr_va) {
453 iounmap(phba->csr_va);
454 phba->csr_va = NULL;
455 }
456 if (phba->db_va) {
457 iounmap(phba->db_va);
458 phba->db_va = NULL;
459 }
460 if (phba->pci_va) {
461 iounmap(phba->pci_va);
462 phba->pci_va = NULL;
463 }
464}
465
466static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
467 struct pci_dev *pcidev)
468{
469 u8 __iomem *addr;
f98c96b0 470 int pcicfg_reg;
6733b39a
JK		 471
472 addr = ioremap_nocache(pci_resource_start(pcidev, 2),
473 pci_resource_len(pcidev, 2));
474 if (addr == NULL)
475 return -ENOMEM;
476 phba->ctrl.csr = addr;
477 phba->csr_va = addr;
478 phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
479
480 addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
481 if (addr == NULL)
482 goto pci_map_err;
483 phba->ctrl.db = addr;
484 phba->db_va = addr;
485 phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
486
f98c96b0
JK		 487 if (phba->generation == BE_GEN2)
488 pcicfg_reg = 1;
489 else
490 pcicfg_reg = 0;
491
492 addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
493 pci_resource_len(pcidev, pcicfg_reg));
494
6733b39a
JK		 495 if (addr == NULL)
496 goto pci_map_err;
497 phba->ctrl.pcicfg = addr;
498 phba->pci_va = addr;
f98c96b0 499 phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
6733b39a
JK		 500 return 0;
501
502pci_map_err:
503 beiscsi_unmap_pci_function(phba);
504 return -ENOMEM;
505}
506
507static int beiscsi_enable_pci(struct pci_dev *pcidev)
508{
509 int ret;
510
511 ret = pci_enable_device(pcidev);
512 if (ret) {
513 dev_err(&pcidev->dev, "beiscsi_enable_pci - enable device "
514 "failed. Returning -ENODEV\n");
515 return ret;
516 }
517
bfead3b2 518 pci_set_master(pcidev);
6733b39a
JK		 519 if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
520 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
521 if (ret) {
522 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
523 pci_disable_device(pcidev);
524 return ret;
525 }
526 }
527 return 0;
528}
529
530static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
531{
532 struct be_ctrl_info *ctrl = &phba->ctrl;
533 struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
534 struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
535 int status = 0;
536
537 ctrl->pdev = pdev;
538 status = beiscsi_map_pci_bars(phba, pdev);
539 if (status)
540 return status;
6733b39a
JK		 541 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
542 mbox_mem_alloc->va = pci_alloc_consistent(pdev,
543 mbox_mem_alloc->size,
544 &mbox_mem_alloc->dma);
545 if (!mbox_mem_alloc->va) {
546 beiscsi_unmap_pci_function(phba);
547 status = -ENOMEM;
548 return status;
549 }
550
551 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
552 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
553 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
554 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
555 spin_lock_init(&ctrl->mbox_lock);
bfead3b2
JK		 556 spin_lock_init(&phba->ctrl.mcc_lock);
557 spin_lock_init(&phba->ctrl.mcc_cq_lock);
558
6733b39a
JK		 559 return status;
560}
561
562static void beiscsi_get_params(struct beiscsi_hba *phba)
563{
7da50879
JK		 564 phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
565 - (phba->fw_config.iscsi_cid_count
566 + BE2_TMFS
567 + BE2_NOPOUT_REQ));
568 phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
ed58ea2a 569 phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2;
6eab04a8 570 phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
6733b39a
JK		 571 phba->params.num_sge_per_io = BE2_SGE;
572 phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
573 phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
574 phba->params.eq_timer = 64;
575 phba->params.num_eq_entries =
7da50879
JK		 576 (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
577 + BE2_TMFS) / 512) + 1) * 512;
6733b39a
JK		 578 phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
579 ? 1024 : phba->params.num_eq_entries;
457ff3b7 580 SE_DEBUG(DBG_LVL_8, "phba->params.num_eq_entries=%d\n",
7da50879 581 phba->params.num_eq_entries);
6733b39a 582 phba->params.num_cq_entries =
7da50879
JK		 583 (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
584 + BE2_TMFS) / 512) + 1) * 512;
6733b39a
JK		 585 phba->params.wrbs_per_cxn = 256;
586}
587
588static void hwi_ring_eq_db(struct beiscsi_hba *phba,
589 unsigned int id, unsigned int clr_interrupt,
590 unsigned int num_processed,
591 unsigned char rearm, unsigned char event)
592{
593 u32 val = 0;
594 val |= id & DB_EQ_RING_ID_MASK;
595 if (rearm)
596 val |= 1 << DB_EQ_REARM_SHIFT;
597 if (clr_interrupt)
598 val |= 1 << DB_EQ_CLR_SHIFT;
599 if (event)
600 val |= 1 << DB_EQ_EVNT_SHIFT;
601 val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
602 iowrite32(val, phba->db_va + DB_EQ_OFFSET);
603}
604
bfead3b2
JK		 605/**
606 * be_isr_mcc - The isr routine of the driver.
607 * @irq: Not used
608 * @dev_id: Pointer to host adapter structure
609 */
610static irqreturn_t be_isr_mcc(int irq, void *dev_id)
611{
612 struct beiscsi_hba *phba;
613 struct be_eq_entry *eqe = NULL;
614 struct be_queue_info *eq;
615 struct be_queue_info *mcc;
616 unsigned int num_eq_processed;
617 struct be_eq_obj *pbe_eq;
618 unsigned long flags;
619
620 pbe_eq = dev_id;
621 eq = &pbe_eq->q;
622 phba = pbe_eq->phba;
623 mcc = &phba->ctrl.mcc_obj.cq;
624 eqe = queue_tail_node(eq);
625 if (!eqe)
626 SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
627
628 num_eq_processed = 0;
629
630 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
631 & EQE_VALID_MASK) {
632 if (((eqe->dw[offsetof(struct amap_eq_entry,
633 resource_id) / 32] &
634 EQE_RESID_MASK) >> 16) == mcc->id) {
635 spin_lock_irqsave(&phba->isr_lock, flags);
636 phba->todo_mcc_cq = 1;
637 spin_unlock_irqrestore(&phba->isr_lock, flags);
638 }
639 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
640 queue_tail_inc(eq);
641 eqe = queue_tail_node(eq);
642 num_eq_processed++;
643 }
644 if (phba->todo_mcc_cq)
645 queue_work(phba->wq, &phba->work_cqs);
646 if (num_eq_processed)
647 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
648
649 return IRQ_HANDLED;
650}
651
652/**
653 * be_isr_msix - The isr routine of the driver.
654 * @irq: Not used
655 * @dev_id: Pointer to host adapter structure
656 */
657static irqreturn_t be_isr_msix(int irq, void *dev_id)
658{
659 struct beiscsi_hba *phba;
660 struct be_eq_entry *eqe = NULL;
661 struct be_queue_info *eq;
662 struct be_queue_info *cq;
663 unsigned int num_eq_processed;
664 struct be_eq_obj *pbe_eq;
665 unsigned long flags;
666
667 pbe_eq = dev_id;
668 eq = &pbe_eq->q;
669 cq = pbe_eq->cq;
670 eqe = queue_tail_node(eq);
671 if (!eqe)
672 SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
673
674 phba = pbe_eq->phba;
675 num_eq_processed = 0;
676 if (blk_iopoll_enabled) {
677 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
678 & EQE_VALID_MASK) {
679 if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
680 blk_iopoll_sched(&pbe_eq->iopoll);
681
682 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
683 queue_tail_inc(eq);
684 eqe = queue_tail_node(eq);
685 num_eq_processed++;
686 }
687 if (num_eq_processed)
688 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
689
690 return IRQ_HANDLED;
691 } else {
692 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
693 & EQE_VALID_MASK) {
694 spin_lock_irqsave(&phba->isr_lock, flags);
695 phba->todo_cq = 1;
696 spin_unlock_irqrestore(&phba->isr_lock, flags);
697 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
698 queue_tail_inc(eq);
699 eqe = queue_tail_node(eq);
700 num_eq_processed++;
701 }
702 if (phba->todo_cq)
703 queue_work(phba->wq, &phba->work_cqs);
704
705 if (num_eq_processed)
706 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
707
708 return IRQ_HANDLED;
709 }
710}
711
6733b39a
JK		 712/**
713 * be_isr - The isr routine of the driver.
714 * @irq: Not used
715 * @dev_id: Pointer to host adapter structure
716 */
717static irqreturn_t be_isr(int irq, void *dev_id)
718{
719 struct beiscsi_hba *phba;
720 struct hwi_controller *phwi_ctrlr;
721 struct hwi_context_memory *phwi_context;
722 struct be_eq_entry *eqe = NULL;
723 struct be_queue_info *eq;
724 struct be_queue_info *cq;
bfead3b2 725 struct be_queue_info *mcc;
6733b39a 726 unsigned long flags, index;
bfead3b2 727 unsigned int num_mcceq_processed, num_ioeq_processed;
6733b39a 728 struct be_ctrl_info *ctrl;
bfead3b2 729 struct be_eq_obj *pbe_eq;
6733b39a
JK		 730 int isr;
731
732 phba = dev_id;
6eab04a8 733 ctrl = &phba->ctrl;
bfead3b2
JK		 734 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
735 (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
736 if (!isr)
737 return IRQ_NONE;
6733b39a
JK		 738
739 phwi_ctrlr = phba->phwi_ctrlr;
740 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 741 pbe_eq = &phwi_context->be_eq[0];
742
743 eq = &phwi_context->be_eq[0].q;
744 mcc = &phba->ctrl.mcc_obj.cq;
6733b39a
JK		 745 index = 0;
746 eqe = queue_tail_node(eq);
747 if (!eqe)
748 SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
749
bfead3b2
JK		 750 num_ioeq_processed = 0;
751 num_mcceq_processed = 0;
6733b39a
JK		 752 if (blk_iopoll_enabled) {
753 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
754 & EQE_VALID_MASK) {
bfead3b2
JK		 755 if (((eqe->dw[offsetof(struct amap_eq_entry,
756 resource_id) / 32] &
757 EQE_RESID_MASK) >> 16) == mcc->id) {
758 spin_lock_irqsave(&phba->isr_lock, flags);
759 phba->todo_mcc_cq = 1;
760 spin_unlock_irqrestore(&phba->isr_lock, flags);
761 num_mcceq_processed++;
762 } else {
763 if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
764 blk_iopoll_sched(&pbe_eq->iopoll);
765 num_ioeq_processed++;
766 }
6733b39a
JK		 767 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
768 queue_tail_inc(eq);
769 eqe = queue_tail_node(eq);
6733b39a 770 }
bfead3b2
JK		 771 if (num_ioeq_processed || num_mcceq_processed) {
772 if (phba->todo_mcc_cq)
773 queue_work(phba->wq, &phba->work_cqs);
774
756d29c8 775 if ((num_mcceq_processed) && (!num_ioeq_processed))
bfead3b2
JK		 776 hwi_ring_eq_db(phba, eq->id, 0,
777 (num_ioeq_processed +
778 num_mcceq_processed) , 1, 1);
779 else
780 hwi_ring_eq_db(phba, eq->id, 0,
781 (num_ioeq_processed +
782 num_mcceq_processed), 0, 1);
783
6733b39a
JK		 784 return IRQ_HANDLED;
785 } else
786 return IRQ_NONE;
787 } else {
bfead3b2 788 cq = &phwi_context->be_cq[0];
6733b39a
JK		 789 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
790 & EQE_VALID_MASK) {
791
792 if (((eqe->dw[offsetof(struct amap_eq_entry,
793 resource_id) / 32] &
794 EQE_RESID_MASK) >> 16) != cq->id) {
795 spin_lock_irqsave(&phba->isr_lock, flags);
796 phba->todo_mcc_cq = 1;
797 spin_unlock_irqrestore(&phba->isr_lock, flags);
798 } else {
799 spin_lock_irqsave(&phba->isr_lock, flags);
800 phba->todo_cq = 1;
801 spin_unlock_irqrestore(&phba->isr_lock, flags);
802 }
803 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
804 queue_tail_inc(eq);
805 eqe = queue_tail_node(eq);
bfead3b2 806 num_ioeq_processed++;
6733b39a
JK		 807 }
808 if (phba->todo_cq || phba->todo_mcc_cq)
809 queue_work(phba->wq, &phba->work_cqs);
810
bfead3b2
JK		 811 if (num_ioeq_processed) {
812 hwi_ring_eq_db(phba, eq->id, 0,
813 num_ioeq_processed, 1, 1);
6733b39a
JK		 814 return IRQ_HANDLED;
815 } else
816 return IRQ_NONE;
817 }
818}
819
820static int beiscsi_init_irqs(struct beiscsi_hba *phba)
821{
822 struct pci_dev *pcidev = phba->pcidev;
bfead3b2
JK		 823 struct hwi_controller *phwi_ctrlr;
824 struct hwi_context_memory *phwi_context;
4f5af07e 825 int ret, msix_vec, i, j;
6733b39a 826
bfead3b2
JK		 827 phwi_ctrlr = phba->phwi_ctrlr;
828 phwi_context = phwi_ctrlr->phwi_ctxt;
829
830 if (phba->msix_enabled) {
831 for (i = 0; i < phba->num_cpus; i++) {
8fcfb210
JK		 832 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
833 GFP_KERNEL);
834 if (!phba->msi_name[i]) {
835 ret = -ENOMEM;
836 goto free_msix_irqs;
837 }
838
839 sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
840 phba->shost->host_no, i);
bfead3b2 841 msix_vec = phba->msix_entries[i].vector;
8fcfb210
JK		 842 ret = request_irq(msix_vec, be_isr_msix, 0,
843 phba->msi_name[i],
bfead3b2 844 &phwi_context->be_eq[i]);
4f5af07e
JK		 845 if (ret) {
846 shost_printk(KERN_ERR, phba->shost,
847 "beiscsi_init_irqs-Failed to"
848 "register msix for i = %d\n", i);
8fcfb210 849 kfree(phba->msi_name[i]);
4f5af07e
JK		 850 goto free_msix_irqs;
851 }
bfead3b2 852 }
8fcfb210
JK		 853 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
854 if (!phba->msi_name[i]) {
855 ret = -ENOMEM;
856 goto free_msix_irqs;
857 }
858 sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
859 phba->shost->host_no);
bfead3b2 860 msix_vec = phba->msix_entries[i].vector;
8fcfb210 861 ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
bfead3b2 862 &phwi_context->be_eq[i]);
4f5af07e
JK		 863 if (ret) {
864 shost_printk(KERN_ERR, phba->shost, "beiscsi_init_irqs-"
865 "Failed to register beiscsi_msix_mcc\n");
8fcfb210 866 kfree(phba->msi_name[i]);
4f5af07e
JK		 867 goto free_msix_irqs;
868 }
869
bfead3b2
JK		 870 } else {
871 ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
872 "beiscsi", phba);
873 if (ret) {
874 shost_printk(KERN_ERR, phba->shost, "beiscsi_init_irqs-"
875 "Failed to register irq\\n");
876 return ret;
877 }
6733b39a
JK		 878 }
879 return 0;
4f5af07e 880free_msix_irqs:
8fcfb210
JK		 881 for (j = i - 1; j >= 0; j--) {
882 kfree(phba->msi_name[j]);
883 msix_vec = phba->msix_entries[j].vector;
4f5af07e 884 free_irq(msix_vec, &phwi_context->be_eq[j]);
8fcfb210 885 }
4f5af07e 886 return ret;
6733b39a
JK		 887}
888
889static void hwi_ring_cq_db(struct beiscsi_hba *phba,
890 unsigned int id, unsigned int num_processed,
891 unsigned char rearm, unsigned char event)
892{
893 u32 val = 0;
894 val |= id & DB_CQ_RING_ID_MASK;
895 if (rearm)
896 val |= 1 << DB_CQ_REARM_SHIFT;
897 val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
898 iowrite32(val, phba->db_va + DB_CQ_OFFSET);
899}
900
6733b39a
JK		 901static unsigned int
902beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
903 struct beiscsi_hba *phba,
904 unsigned short cid,
905 struct pdu_base *ppdu,
906 unsigned long pdu_len,
907 void *pbuffer, unsigned long buf_len)
908{
909 struct iscsi_conn *conn = beiscsi_conn->conn;
910 struct iscsi_session *session = conn->session;
bfead3b2
JK		 911 struct iscsi_task *task;
912 struct beiscsi_io_task *io_task;
913 struct iscsi_hdr *login_hdr;
6733b39a
JK		 914
915 switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
916 PDUBASE_OPCODE_MASK) {
917 case ISCSI_OP_NOOP_IN:
918 pbuffer = NULL;
919 buf_len = 0;
920 break;
921 case ISCSI_OP_ASYNC_EVENT:
922 break;
923 case ISCSI_OP_REJECT:
924 WARN_ON(!pbuffer);
925 WARN_ON(!(buf_len == 48));
926 SE_DEBUG(DBG_LVL_1, "In ISCSI_OP_REJECT\n");
927 break;
928 case ISCSI_OP_LOGIN_RSP:
7bd6e25c 929 case ISCSI_OP_TEXT_RSP:
bfead3b2
JK		 930 task = conn->login_task;
931 io_task = task->dd_data;
932 login_hdr = (struct iscsi_hdr *)ppdu;
933 login_hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 934 break;
935 default:
936 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 937 "Unrecognized opcode 0x%x in async msg\n",
6733b39a
JK		 938 (ppdu->
939 dw[offsetof(struct amap_pdu_base, opcode) / 32]
940 & PDUBASE_OPCODE_MASK));
941 return 1;
942 }
943
944 spin_lock_bh(&session->lock);
945 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
946 spin_unlock_bh(&session->lock);
947 return 0;
948}
949
950static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
951{
952 struct sgl_handle *psgl_handle;
953
954 if (phba->io_sgl_hndl_avbl) {
955 SE_DEBUG(DBG_LVL_8,
457ff3b7 956 "In alloc_io_sgl_handle,io_sgl_alloc_index=%d\n",
6733b39a
JK		 957 phba->io_sgl_alloc_index);
958 psgl_handle = phba->io_sgl_hndl_base[phba->
959 io_sgl_alloc_index];
960 phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
961 phba->io_sgl_hndl_avbl--;
bfead3b2
JK		 962 if (phba->io_sgl_alloc_index == (phba->params.
963 ios_per_ctrl - 1))
6733b39a
JK		 964 phba->io_sgl_alloc_index = 0;
965 else
966 phba->io_sgl_alloc_index++;
967 } else
968 psgl_handle = NULL;
969 return psgl_handle;
970}
971
972static void
973free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
974{
457ff3b7 975 SE_DEBUG(DBG_LVL_8, "In free_,io_sgl_free_index=%d\n",
6733b39a
JK		 976 phba->io_sgl_free_index);
977 if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
978 /*
979 * this can happen if clean_task is called on a task that
980 * failed in xmit_task or alloc_pdu.
981 */
982 SE_DEBUG(DBG_LVL_8,
983 "Double Free in IO SGL io_sgl_free_index=%d,"
457ff3b7 984 "value there=%p\n", phba->io_sgl_free_index,
6733b39a
JK		 985 phba->io_sgl_hndl_base[phba->io_sgl_free_index]);
986 return;
987 }
988 phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
989 phba->io_sgl_hndl_avbl++;
990 if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
991 phba->io_sgl_free_index = 0;
992 else
993 phba->io_sgl_free_index++;
994}
995
996/**
997 * alloc_wrb_handle - To allocate a wrb handle
998 * @phba: The hba pointer
999 * @cid: The cid to use for allocation
6733b39a
JK		 1000 *
1001 * This happens under session_lock until submission to chip
1002 */
d5431488 1003struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
6733b39a
JK		 1004{
1005 struct hwi_wrb_context *pwrb_context;
1006 struct hwi_controller *phwi_ctrlr;
d5431488 1007 struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
6733b39a
JK		 1008
1009 phwi_ctrlr = phba->phwi_ctrlr;
1010 pwrb_context = &phwi_ctrlr->wrb_context[cid];
d5431488 1011 if (pwrb_context->wrb_handles_available >= 2) {
bfead3b2
JK		 1012 pwrb_handle = pwrb_context->pwrb_handle_base[
1013 pwrb_context->alloc_index];
1014 pwrb_context->wrb_handles_available--;
bfead3b2
JK		 1015 if (pwrb_context->alloc_index ==
1016 (phba->params.wrbs_per_cxn - 1))
1017 pwrb_context->alloc_index = 0;
1018 else
1019 pwrb_context->alloc_index++;
d5431488
JK		 1020 pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
1021 pwrb_context->alloc_index];
1022 pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
bfead3b2
JK		 1023 } else
1024 pwrb_handle = NULL;
6733b39a
JK		 1025 return pwrb_handle;
1026}
1027
1028/**
1029 * free_wrb_handle - To free the wrb handle back to pool
1030 * @phba: The hba pointer
1031 * @pwrb_context: The context to free from
1032 * @pwrb_handle: The wrb_handle to free
1033 *
1034 * This happens under session_lock until submission to chip
1035 */
1036static void
1037free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
1038 struct wrb_handle *pwrb_handle)
1039{
32951dd8 1040 pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
bfead3b2
JK		 1041 pwrb_context->wrb_handles_available++;
1042 if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
1043 pwrb_context->free_index = 0;
1044 else
1045 pwrb_context->free_index++;
1046
6733b39a 1047 SE_DEBUG(DBG_LVL_8,
bfead3b2 1048 "FREE WRB: pwrb_handle=%p free_index=0x%x"
457ff3b7 1049 "wrb_handles_available=%d\n",
6733b39a 1050 pwrb_handle, pwrb_context->free_index,
bfead3b2 1051 pwrb_context->wrb_handles_available);
6733b39a
JK		 1052}
1053
1054static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
1055{
1056 struct sgl_handle *psgl_handle;
1057
1058 if (phba->eh_sgl_hndl_avbl) {
1059 psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
1060 phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
457ff3b7 1061 SE_DEBUG(DBG_LVL_8, "mgmt_sgl_alloc_index=%d=0x%x\n",
6733b39a
JK		 1062 phba->eh_sgl_alloc_index, phba->eh_sgl_alloc_index);
1063 phba->eh_sgl_hndl_avbl--;
1064 if (phba->eh_sgl_alloc_index ==
1065 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
1066 1))
1067 phba->eh_sgl_alloc_index = 0;
1068 else
1069 phba->eh_sgl_alloc_index++;
1070 } else
1071 psgl_handle = NULL;
1072 return psgl_handle;
1073}
1074
1075void
1076free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
1077{
1078
457ff3b7 1079 SE_DEBUG(DBG_LVL_8, "In free_mgmt_sgl_handle,eh_sgl_free_index=%d\n",
bfead3b2 1080 phba->eh_sgl_free_index);
6733b39a
JK		 1081 if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
1082 /*
1083 * this can happen if clean_task is called on a task that
1084 * failed in xmit_task or alloc_pdu.
1085 */
1086 SE_DEBUG(DBG_LVL_8,
457ff3b7 1087 "Double Free in eh SGL ,eh_sgl_free_index=%d\n",
6733b39a
JK		 1088 phba->eh_sgl_free_index);
1089 return;
1090 }
1091 phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
1092 phba->eh_sgl_hndl_avbl++;
1093 if (phba->eh_sgl_free_index ==
1094 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
1095 phba->eh_sgl_free_index = 0;
1096 else
1097 phba->eh_sgl_free_index++;
1098}
1099
1100static void
1101be_complete_io(struct beiscsi_conn *beiscsi_conn,
1102 struct iscsi_task *task, struct sol_cqe *psol)
1103{
1104 struct beiscsi_io_task *io_task = task->dd_data;
1105 struct be_status_bhs *sts_bhs =
1106 (struct be_status_bhs *)io_task->cmd_bhs;
1107 struct iscsi_conn *conn = beiscsi_conn->conn;
6733b39a
JK		 1108 unsigned char *sense;
1109 u32 resid = 0, exp_cmdsn, max_cmdsn;
1110 u8 rsp, status, flags;
1111
bfead3b2 1112 exp_cmdsn = (psol->
6733b39a
JK		 1113 dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
1114 & SOL_EXP_CMD_SN_MASK);
bfead3b2 1115 max_cmdsn = ((psol->
6733b39a
JK		 1116 dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
1117 & SOL_EXP_CMD_SN_MASK) +
1118 ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
1119 / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
1120 rsp = ((psol->dw[offsetof(struct amap_sol_cqe, i_resp) / 32]
1121 & SOL_RESP_MASK) >> 16);
1122 status = ((psol->dw[offsetof(struct amap_sol_cqe, i_sts) / 32]
1123 & SOL_STS_MASK) >> 8);
1124 flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
1125 & SOL_FLAGS_MASK) >> 24) | 0x80;
bd535451
JK		 1126 if (!task->sc) {
1127 if (io_task->scsi_cmnd)
1128 scsi_dma_unmap(io_task->scsi_cmnd);
6733b39a 1129
bd535451
JK		 1130 return;
1131 }
6733b39a
JK		 1132 task->sc->result = (DID_OK << 16) | status;
1133 if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
1134 task->sc->result = DID_ERROR << 16;
1135 goto unmap;
1136 }
1137
1138 /* bidi not initially supported */
1139 if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
1140 resid = (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) /
1141 32] & SOL_RES_CNT_MASK);
1142
1143 if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
1144 task->sc->result = DID_ERROR << 16;
1145
1146 if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
1147 scsi_set_resid(task->sc, resid);
1148 if (!status && (scsi_bufflen(task->sc) - resid <
1149 task->sc->underflow))
1150 task->sc->result = DID_ERROR << 16;
1151 }
1152 }
1153
1154 if (status == SAM_STAT_CHECK_CONDITION) {
4053a4be 1155 u16 sense_len;
bfead3b2 1156 unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
4053a4be 1157
6733b39a 1158 sense = sts_bhs->sense_info + sizeof(unsigned short);
4053a4be 1159 sense_len = be16_to_cpu(*slen);
6733b39a
JK		 1160 memcpy(task->sc->sense_buffer, sense,
1161 min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
1162 }
756d29c8 1163
6733b39a
JK		 1164 if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) {
1165 if (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
1166 & SOL_RES_CNT_MASK)
1167 conn->rxdata_octets += (psol->
bfead3b2
JK		 1168 dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
1169 & SOL_RES_CNT_MASK);
6733b39a
JK		 1170 }
1171unmap:
1172 scsi_dma_unmap(io_task->scsi_cmnd);
1173 iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
1174}
1175
1176static void
1177be_complete_logout(struct beiscsi_conn *beiscsi_conn,
1178 struct iscsi_task *task, struct sol_cqe *psol)
1179{
1180 struct iscsi_logout_rsp *hdr;
bfead3b2 1181 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1182 struct iscsi_conn *conn = beiscsi_conn->conn;
1183
1184 hdr = (struct iscsi_logout_rsp *)task->hdr;
7bd6e25c 1185 hdr->opcode = ISCSI_OP_LOGOUT_RSP;
6733b39a
JK		 1186 hdr->t2wait = 5;
1187 hdr->t2retain = 0;
1188 hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
1189 & SOL_FLAGS_MASK) >> 24) | 0x80;
1190 hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
1191 32] & SOL_RESP_MASK);
1192 hdr->exp_cmdsn = cpu_to_be32(psol->
1193 dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
1194 & SOL_EXP_CMD_SN_MASK);
1195 hdr->max_cmdsn = be32_to_cpu((psol->
1196 dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
1197 & SOL_EXP_CMD_SN_MASK) +
1198 ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
1199 / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
7bd6e25c
JK		 1200 hdr->dlength[0] = 0;
1201 hdr->dlength[1] = 0;
1202 hdr->dlength[2] = 0;
6733b39a 1203 hdr->hlength = 0;
bfead3b2 1204 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1205 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1206}
1207
1208static void
1209be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
1210 struct iscsi_task *task, struct sol_cqe *psol)
1211{
1212 struct iscsi_tm_rsp *hdr;
1213 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1214 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1215
1216 hdr = (struct iscsi_tm_rsp *)task->hdr;
7bd6e25c 1217 hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
6733b39a
JK		 1218 hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
1219 & SOL_FLAGS_MASK) >> 24) | 0x80;
1220 hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
1221 32] & SOL_RESP_MASK);
1222 hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
bfead3b2 1223 i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
6733b39a
JK		 1224 hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
1225 i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
1226 ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
1227 / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
bfead3b2 1228 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1229 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1230}
1231
1232static void
1233hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
1234 struct beiscsi_hba *phba, struct sol_cqe *psol)
1235{
1236 struct hwi_wrb_context *pwrb_context;
bfead3b2 1237 struct wrb_handle *pwrb_handle = NULL;
6733b39a 1238 struct hwi_controller *phwi_ctrlr;
bfead3b2
JK		 1239 struct iscsi_task *task;
1240 struct beiscsi_io_task *io_task;
6733b39a
JK		 1241 struct iscsi_conn *conn = beiscsi_conn->conn;
1242 struct iscsi_session *session = conn->session;
1243
1244 phwi_ctrlr = phba->phwi_ctrlr;
32951dd8 1245 pwrb_context = &phwi_ctrlr->wrb_context[((psol->
35e66019 1246 dw[offsetof(struct amap_sol_cqe, cid) / 32] &
7da50879
JK		 1247 SOL_CID_MASK) >> 6) -
1248 phba->fw_config.iscsi_cid_start];
32951dd8 1249 pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
35e66019
JK		 1250 dw[offsetof(struct amap_sol_cqe, wrb_index) /
1251 32] & SOL_WRB_INDEX_MASK) >> 16)];
32951dd8 1252 task = pwrb_handle->pio_handle;
35e66019 1253
bfead3b2
JK		 1254 io_task = task->dd_data;
1255 spin_lock(&phba->mgmt_sgl_lock);
1256 free_mgmt_sgl_handle(phba, io_task->psgl_handle);
1257 spin_unlock(&phba->mgmt_sgl_lock);
6733b39a
JK		 1258 spin_lock_bh(&session->lock);
1259 free_wrb_handle(phba, pwrb_context, pwrb_handle);
1260 spin_unlock_bh(&session->lock);
1261}
1262
1263static void
1264be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
1265 struct iscsi_task *task, struct sol_cqe *psol)
1266{
1267 struct iscsi_nopin *hdr;
1268 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1269 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1270
1271 hdr = (struct iscsi_nopin *)task->hdr;
1272 hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
1273 & SOL_FLAGS_MASK) >> 24) | 0x80;
1274 hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
1275 i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
1276 hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
1277 i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
1278 ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
1279 / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
1280 hdr->opcode = ISCSI_OP_NOOP_IN;
bfead3b2 1281 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1282 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1283}
1284
1285static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
1286 struct beiscsi_hba *phba, struct sol_cqe *psol)
1287{
1288 struct hwi_wrb_context *pwrb_context;
1289 struct wrb_handle *pwrb_handle;
1290 struct iscsi_wrb *pwrb = NULL;
1291 struct hwi_controller *phwi_ctrlr;
1292 struct iscsi_task *task;
bfead3b2 1293 unsigned int type;
6733b39a
JK		 1294 struct iscsi_conn *conn = beiscsi_conn->conn;
1295 struct iscsi_session *session = conn->session;
1296
1297 phwi_ctrlr = phba->phwi_ctrlr;
32951dd8 1298 pwrb_context = &phwi_ctrlr->wrb_context[((psol->dw[offsetof
35e66019 1299 (struct amap_sol_cqe, cid) / 32]
7da50879
JK		 1300 & SOL_CID_MASK) >> 6) -
1301 phba->fw_config.iscsi_cid_start];
32951dd8 1302 pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
35e66019
JK		 1303 dw[offsetof(struct amap_sol_cqe, wrb_index) /
1304 32] & SOL_WRB_INDEX_MASK) >> 16)];
32951dd8
JK		 1305 task = pwrb_handle->pio_handle;
1306 pwrb = pwrb_handle->pwrb;
1307 type = (pwrb->dw[offsetof(struct amap_iscsi_wrb, type) / 32] &
1308 WRB_TYPE_MASK) >> 28;
1309
bfead3b2
JK		 1310 spin_lock_bh(&session->lock);
1311 switch (type) {
6733b39a
JK		 1312 case HWH_TYPE_IO:
1313 case HWH_TYPE_IO_RD:
1314 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
dafab8e0 1315 ISCSI_OP_NOOP_OUT)
6733b39a 1316 be_complete_nopin_resp(beiscsi_conn, task, psol);
dafab8e0 1317 else
6733b39a
JK		 1318 be_complete_io(beiscsi_conn, task, psol);
1319 break;
1320
1321 case HWH_TYPE_LOGOUT:
dafab8e0
JK		 1322 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
1323 be_complete_logout(beiscsi_conn, task, psol);
1324 else
1325 be_complete_tmf(beiscsi_conn, task, psol);
1326
6733b39a
JK		 1327 break;
1328
1329 case HWH_TYPE_LOGIN:
1330 SE_DEBUG(DBG_LVL_1,
1331 "\t\t No HWH_TYPE_LOGIN Expected in hwi_complete_cmd"
457ff3b7 1332 "- Solicited path\n");
6733b39a
JK		 1333 break;
1334
6733b39a
JK		 1335 case HWH_TYPE_NOP:
1336 be_complete_nopin_resp(beiscsi_conn, task, psol);
1337 break;
1338
1339 default:
32951dd8 1340 shost_printk(KERN_WARNING, phba->shost,
35e66019
JK		 1341 "In hwi_complete_cmd, unknown type = %d"
1342 "wrb_index 0x%x CID 0x%x\n", type,
1343 ((psol->dw[offsetof(struct amap_iscsi_wrb,
1344 type) / 32] & SOL_WRB_INDEX_MASK) >> 16),
1345 ((psol->dw[offsetof(struct amap_sol_cqe,
1346 cid) / 32] & SOL_CID_MASK) >> 6));
6733b39a
JK		 1347 break;
1348 }
35e66019 1349
6733b39a
JK		 1350 spin_unlock_bh(&session->lock);
1351}
1352
1353static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
1354 *pasync_ctx, unsigned int is_header,
1355 unsigned int host_write_ptr)
1356{
1357 if (is_header)
1358 return &pasync_ctx->async_entry[host_write_ptr].
1359 header_busy_list;
1360 else
1361 return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
1362}
1363
1364static struct async_pdu_handle *
1365hwi_get_async_handle(struct beiscsi_hba *phba,
1366 struct beiscsi_conn *beiscsi_conn,
1367 struct hwi_async_pdu_context *pasync_ctx,
1368 struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
1369{
1370 struct be_bus_address phys_addr;
1371 struct list_head *pbusy_list;
1372 struct async_pdu_handle *pasync_handle = NULL;
6733b39a
JK		 1373 unsigned char is_header = 0;
1374
1375 phys_addr.u.a32.address_lo =
1376 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_lo) / 32] -
1377 ((pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
1378 & PDUCQE_DPL_MASK) >> 16);
1379 phys_addr.u.a32.address_hi =
1380 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_hi) / 32];
1381
1382 phys_addr.u.a64.address =
1383 *((unsigned long long *)(&phys_addr.u.a64.address));
1384
1385 switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
1386 & PDUCQE_CODE_MASK) {
1387 case UNSOL_HDR_NOTIFY:
1388 is_header = 1;
1389
1390 pbusy_list = hwi_get_async_busy_list(pasync_ctx, 1,
1391 (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1392 index) / 32] & PDUCQE_INDEX_MASK));
6733b39a
JK		 1393 break;
1394 case UNSOL_DATA_NOTIFY:
1395 pbusy_list = hwi_get_async_busy_list(pasync_ctx, 0, (pdpdu_cqe->
1396 dw[offsetof(struct amap_i_t_dpdu_cqe,
1397 index) / 32] & PDUCQE_INDEX_MASK));
6733b39a
JK		 1398 break;
1399 default:
1400 pbusy_list = NULL;
1401 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 1402 "Unexpected code=%d\n",
6733b39a
JK		 1403 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1404 code) / 32] & PDUCQE_CODE_MASK);
1405 return NULL;
1406 }
1407
6733b39a
JK		 1408 WARN_ON(list_empty(pbusy_list));
1409 list_for_each_entry(pasync_handle, pbusy_list, link) {
dc63aac6 1410 if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
6733b39a
JK		 1411 break;
1412 }
1413
1414 WARN_ON(!pasync_handle);
1415
7da50879
JK		 1416 pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid -
1417 phba->fw_config.iscsi_cid_start;
6733b39a
JK		 1418 pasync_handle->is_header = is_header;
1419 pasync_handle->buffer_len = ((pdpdu_cqe->
1420 dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
1421 & PDUCQE_DPL_MASK) >> 16);
1422
1423 *pcq_index = (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1424 index) / 32] & PDUCQE_INDEX_MASK);
1425 return pasync_handle;
1426}
1427
1428static unsigned int
1429hwi_update_async_writables(struct hwi_async_pdu_context *pasync_ctx,
1430 unsigned int is_header, unsigned int cq_index)
1431{
1432 struct list_head *pbusy_list;
1433 struct async_pdu_handle *pasync_handle;
1434 unsigned int num_entries, writables = 0;
1435 unsigned int *pep_read_ptr, *pwritables;
1436
dc63aac6 1437 num_entries = pasync_ctx->num_entries;
6733b39a
JK		 1438 if (is_header) {
1439 pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
1440 pwritables = &pasync_ctx->async_header.writables;
6733b39a
JK		 1441 } else {
1442 pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
1443 pwritables = &pasync_ctx->async_data.writables;
6733b39a
JK		 1444 }
1445
1446 while ((*pep_read_ptr) != cq_index) {
1447 (*pep_read_ptr)++;
1448 *pep_read_ptr = (*pep_read_ptr) % num_entries;
1449
1450 pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
1451 *pep_read_ptr);
1452 if (writables == 0)
1453 WARN_ON(list_empty(pbusy_list));
1454
1455 if (!list_empty(pbusy_list)) {
1456 pasync_handle = list_entry(pbusy_list->next,
1457 struct async_pdu_handle,
1458 link);
1459 WARN_ON(!pasync_handle);
1460 pasync_handle->consumed = 1;
1461 }
1462
1463 writables++;
1464 }
1465
1466 if (!writables) {
1467 SE_DEBUG(DBG_LVL_1,
1468 "Duplicate notification received - index 0x%x!!\n",
1469 cq_index);
1470 WARN_ON(1);
1471 }
1472
1473 *pwritables = *pwritables + writables;
1474 return 0;
1475}
1476
1477static unsigned int hwi_free_async_msg(struct beiscsi_hba *phba,
1478 unsigned int cri)
1479{
1480 struct hwi_controller *phwi_ctrlr;
1481 struct hwi_async_pdu_context *pasync_ctx;
1482 struct async_pdu_handle *pasync_handle, *tmp_handle;
1483 struct list_head *plist;
1484 unsigned int i = 0;
1485
1486 phwi_ctrlr = phba->phwi_ctrlr;
1487 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
1488
1489 plist = &pasync_ctx->async_entry[cri].wait_queue.list;
1490
1491 list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
1492 list_del(&pasync_handle->link);
1493
1494 if (i == 0) {
1495 list_add_tail(&pasync_handle->link,
1496 &pasync_ctx->async_header.free_list);
1497 pasync_ctx->async_header.free_entries++;
1498 i++;
1499 } else {
1500 list_add_tail(&pasync_handle->link,
1501 &pasync_ctx->async_data.free_list);
1502 pasync_ctx->async_data.free_entries++;
1503 i++;
1504 }
1505 }
1506
1507 INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
1508 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
1509 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
1510 return 0;
1511}
1512
1513static struct phys_addr *
1514hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
1515 unsigned int is_header, unsigned int host_write_ptr)
1516{
1517 struct phys_addr *pasync_sge = NULL;
1518
1519 if (is_header)
1520 pasync_sge = pasync_ctx->async_header.ring_base;
1521 else
1522 pasync_sge = pasync_ctx->async_data.ring_base;
1523
1524 return pasync_sge + host_write_ptr;
1525}
1526
1527static void hwi_post_async_buffers(struct beiscsi_hba *phba,
1528 unsigned int is_header)
1529{
1530 struct hwi_controller *phwi_ctrlr;
1531 struct hwi_async_pdu_context *pasync_ctx;
1532 struct async_pdu_handle *pasync_handle;
1533 struct list_head *pfree_link, *pbusy_list;
1534 struct phys_addr *pasync_sge;
1535 unsigned int ring_id, num_entries;
1536 unsigned int host_write_num;
1537 unsigned int writables;
1538 unsigned int i = 0;
1539 u32 doorbell = 0;
1540
1541 phwi_ctrlr = phba->phwi_ctrlr;
1542 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
dc63aac6 1543 num_entries = pasync_ctx->num_entries;
6733b39a
JK		 1544
1545 if (is_header) {
6733b39a
JK		 1546 writables = min(pasync_ctx->async_header.writables,
1547 pasync_ctx->async_header.free_entries);
1548 pfree_link = pasync_ctx->async_header.free_list.next;
1549 host_write_num = pasync_ctx->async_header.host_write_ptr;
1550 ring_id = phwi_ctrlr->default_pdu_hdr.id;
1551 } else {
6733b39a
JK		 1552 writables = min(pasync_ctx->async_data.writables,
1553 pasync_ctx->async_data.free_entries);
1554 pfree_link = pasync_ctx->async_data.free_list.next;
1555 host_write_num = pasync_ctx->async_data.host_write_ptr;
1556 ring_id = phwi_ctrlr->default_pdu_data.id;
1557 }
1558
1559 writables = (writables / 8) * 8;
1560 if (writables) {
1561 for (i = 0; i < writables; i++) {
1562 pbusy_list =
1563 hwi_get_async_busy_list(pasync_ctx, is_header,
1564 host_write_num);
1565 pasync_handle =
1566 list_entry(pfree_link, struct async_pdu_handle,
1567 link);
1568 WARN_ON(!pasync_handle);
1569 pasync_handle->consumed = 0;
1570
1571 pfree_link = pfree_link->next;
1572
1573 pasync_sge = hwi_get_ring_address(pasync_ctx,
1574 is_header, host_write_num);
1575
1576 pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
1577 pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
1578
1579 list_move(&pasync_handle->link, pbusy_list);
1580
1581 host_write_num++;
1582 host_write_num = host_write_num % num_entries;
1583 }
1584
1585 if (is_header) {
1586 pasync_ctx->async_header.host_write_ptr =
1587 host_write_num;
1588 pasync_ctx->async_header.free_entries -= writables;
1589 pasync_ctx->async_header.writables -= writables;
1590 pasync_ctx->async_header.busy_entries += writables;
1591 } else {
1592 pasync_ctx->async_data.host_write_ptr = host_write_num;
1593 pasync_ctx->async_data.free_entries -= writables;
1594 pasync_ctx->async_data.writables -= writables;
1595 pasync_ctx->async_data.busy_entries += writables;
1596 }
1597
1598 doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
1599 doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
1600 doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
1601 doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
1602 << DB_DEF_PDU_CQPROC_SHIFT;
1603
1604 iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
1605 }
1606}
1607
1608static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
1609 struct beiscsi_conn *beiscsi_conn,
1610 struct i_t_dpdu_cqe *pdpdu_cqe)
1611{
1612 struct hwi_controller *phwi_ctrlr;
1613 struct hwi_async_pdu_context *pasync_ctx;
1614 struct async_pdu_handle *pasync_handle = NULL;
1615 unsigned int cq_index = -1;
1616
1617 phwi_ctrlr = phba->phwi_ctrlr;
1618 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
1619
1620 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
1621 pdpdu_cqe, &cq_index);
1622 BUG_ON(pasync_handle->is_header != 0);
1623 if (pasync_handle->consumed == 0)
1624 hwi_update_async_writables(pasync_ctx, pasync_handle->is_header,
1625 cq_index);
1626
1627 hwi_free_async_msg(phba, pasync_handle->cri);
1628 hwi_post_async_buffers(phba, pasync_handle->is_header);
1629}
1630
1631static unsigned int
1632hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
1633 struct beiscsi_hba *phba,
1634 struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
1635{
1636 struct list_head *plist;
1637 struct async_pdu_handle *pasync_handle;
1638 void *phdr = NULL;
1639 unsigned int hdr_len = 0, buf_len = 0;
1640 unsigned int status, index = 0, offset = 0;
1641 void *pfirst_buffer = NULL;
1642 unsigned int num_buf = 0;
1643
1644 plist = &pasync_ctx->async_entry[cri].wait_queue.list;
1645
1646 list_for_each_entry(pasync_handle, plist, link) {
1647 if (index == 0) {
1648 phdr = pasync_handle->pbuffer;
1649 hdr_len = pasync_handle->buffer_len;
1650 } else {
1651 buf_len = pasync_handle->buffer_len;
1652 if (!num_buf) {
1653 pfirst_buffer = pasync_handle->pbuffer;
1654 num_buf++;
1655 }
1656 memcpy(pfirst_buffer + offset,
1657 pasync_handle->pbuffer, buf_len);
1658 offset = buf_len;
1659 }
1660 index++;
1661 }
1662
1663 status = beiscsi_process_async_pdu(beiscsi_conn, phba,
7da50879
JK		 1664 (beiscsi_conn->beiscsi_conn_cid -
1665 phba->fw_config.iscsi_cid_start),
1666 phdr, hdr_len, pfirst_buffer,
1667 buf_len);
6733b39a
JK		 1668
1669 if (status == 0)
1670 hwi_free_async_msg(phba, cri);
1671 return 0;
1672}
1673
1674static unsigned int
1675hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
1676 struct beiscsi_hba *phba,
1677 struct async_pdu_handle *pasync_handle)
1678{
1679 struct hwi_async_pdu_context *pasync_ctx;
1680 struct hwi_controller *phwi_ctrlr;
1681 unsigned int bytes_needed = 0, status = 0;
1682 unsigned short cri = pasync_handle->cri;
1683 struct pdu_base *ppdu;
1684
1685 phwi_ctrlr = phba->phwi_ctrlr;
1686 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
1687
1688 list_del(&pasync_handle->link);
1689 if (pasync_handle->is_header) {
1690 pasync_ctx->async_header.busy_entries--;
1691 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
1692 hwi_free_async_msg(phba, cri);
1693 BUG();
1694 }
1695
1696 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
1697 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
1698 pasync_ctx->async_entry[cri].wait_queue.hdr_len =
1699 (unsigned short)pasync_handle->buffer_len;
1700 list_add_tail(&pasync_handle->link,
1701 &pasync_ctx->async_entry[cri].wait_queue.list);
1702
1703 ppdu = pasync_handle->pbuffer;
1704 bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
1705 data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
1706 0xFFFF0000) | ((be16_to_cpu((ppdu->
1707 dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
1708 & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
1709
1710 if (status == 0) {
1711 pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
1712 bytes_needed;
1713
1714 if (bytes_needed == 0)
1715 status = hwi_fwd_async_msg(beiscsi_conn, phba,
1716 pasync_ctx, cri);
1717 }
1718 } else {
1719 pasync_ctx->async_data.busy_entries--;
1720 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
1721 list_add_tail(&pasync_handle->link,
1722 &pasync_ctx->async_entry[cri].wait_queue.
1723 list);
1724 pasync_ctx->async_entry[cri].wait_queue.
1725 bytes_received +=
1726 (unsigned short)pasync_handle->buffer_len;
1727
1728 if (pasync_ctx->async_entry[cri].wait_queue.
1729 bytes_received >=
1730 pasync_ctx->async_entry[cri].wait_queue.
1731 bytes_needed)
1732 status = hwi_fwd_async_msg(beiscsi_conn, phba,
1733 pasync_ctx, cri);
1734 }
1735 }
1736 return status;
1737}
1738
1739static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
1740 struct beiscsi_hba *phba,
1741 struct i_t_dpdu_cqe *pdpdu_cqe)
1742{
1743 struct hwi_controller *phwi_ctrlr;
1744 struct hwi_async_pdu_context *pasync_ctx;
1745 struct async_pdu_handle *pasync_handle = NULL;
1746 unsigned int cq_index = -1;
1747
1748 phwi_ctrlr = phba->phwi_ctrlr;
1749 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
1750 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
1751 pdpdu_cqe, &cq_index);
1752
1753 if (pasync_handle->consumed == 0)
1754 hwi_update_async_writables(pasync_ctx, pasync_handle->is_header,
1755 cq_index);
1756 hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
1757 hwi_post_async_buffers(phba, pasync_handle->is_header);
1758}
1759
756d29c8
JK		 1760static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
1761{
1762 struct be_queue_info *mcc_cq;
1763 struct be_mcc_compl *mcc_compl;
1764 unsigned int num_processed = 0;
1765
1766 mcc_cq = &phba->ctrl.mcc_obj.cq;
1767 mcc_compl = queue_tail_node(mcc_cq);
1768 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
1769 while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
1770
1771 if (num_processed >= 32) {
1772 hwi_ring_cq_db(phba, mcc_cq->id,
1773 num_processed, 0, 0);
1774 num_processed = 0;
1775 }
1776 if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
1777 /* Interpret flags as an async trailer */
1778 if (is_link_state_evt(mcc_compl->flags))
1779 /* Interpret compl as a async link evt */
1780 beiscsi_async_link_state_process(phba,
1781 (struct be_async_event_link_state *) mcc_compl);
1782 else
1783 SE_DEBUG(DBG_LVL_1,
1784 " Unsupported Async Event, flags"
457ff3b7 1785 " = 0x%08x\n", mcc_compl->flags);
756d29c8
JK		 1786 } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
1787 be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
1788 atomic_dec(&phba->ctrl.mcc_obj.q.used);
1789 }
1790
1791 mcc_compl->flags = 0;
1792 queue_tail_inc(mcc_cq);
1793 mcc_compl = queue_tail_node(mcc_cq);
1794 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
1795 num_processed++;
1796 }
1797
1798 if (num_processed > 0)
1799 hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
1800
1801}
bfead3b2
JK		 1802
1803static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
6733b39a 1804{
6733b39a
JK		 1805 struct be_queue_info *cq;
1806 struct sol_cqe *sol;
1807 struct dmsg_cqe *dmsg;
1808 unsigned int num_processed = 0;
1809 unsigned int tot_nump = 0;
1810 struct beiscsi_conn *beiscsi_conn;
c2462288
JK		 1811 struct beiscsi_endpoint *beiscsi_ep;
1812 struct iscsi_endpoint *ep;
bfead3b2 1813 struct beiscsi_hba *phba;
6733b39a 1814
bfead3b2 1815 cq = pbe_eq->cq;
6733b39a 1816 sol = queue_tail_node(cq);
bfead3b2 1817 phba = pbe_eq->phba;
6733b39a
JK		 1818
1819 while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
1820 CQE_VALID_MASK) {
1821 be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
1822
32951dd8 1823 ep = phba->ep_array[(u32) ((sol->
c2462288
JK		 1824 dw[offsetof(struct amap_sol_cqe, cid) / 32] &
1825 SOL_CID_MASK) >> 6) -
7da50879 1826 phba->fw_config.iscsi_cid_start];
32951dd8 1827
c2462288
JK		 1828 beiscsi_ep = ep->dd_data;
1829 beiscsi_conn = beiscsi_ep->conn;
756d29c8 1830
6733b39a 1831 if (num_processed >= 32) {
bfead3b2 1832 hwi_ring_cq_db(phba, cq->id,
6733b39a
JK		 1833 num_processed, 0, 0);
1834 tot_nump += num_processed;
1835 num_processed = 0;
1836 }
1837
1838 switch ((u32) sol->dw[offsetof(struct amap_sol_cqe, code) /
1839 32] & CQE_CODE_MASK) {
1840 case SOL_CMD_COMPLETE:
1841 hwi_complete_cmd(beiscsi_conn, phba, sol);
1842 break;
1843 case DRIVERMSG_NOTIFY:
457ff3b7 1844 SE_DEBUG(DBG_LVL_8, "Received DRIVERMSG_NOTIFY\n");
6733b39a
JK		 1845 dmsg = (struct dmsg_cqe *)sol;
1846 hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
1847 break;
1848 case UNSOL_HDR_NOTIFY:
bfead3b2
JK		 1849 SE_DEBUG(DBG_LVL_8, "Received UNSOL_HDR_ NOTIFY\n");
1850 hwi_process_default_pdu_ring(beiscsi_conn, phba,
1851 (struct i_t_dpdu_cqe *)sol);
1852 break;
6733b39a 1853 case UNSOL_DATA_NOTIFY:
bfead3b2 1854 SE_DEBUG(DBG_LVL_8, "Received UNSOL_DATA_NOTIFY\n");
6733b39a
JK		 1855 hwi_process_default_pdu_ring(beiscsi_conn, phba,
1856 (struct i_t_dpdu_cqe *)sol);
1857 break;
1858 case CXN_INVALIDATE_INDEX_NOTIFY:
1859 case CMD_INVALIDATED_NOTIFY:
1860 case CXN_INVALIDATE_NOTIFY:
1861 SE_DEBUG(DBG_LVL_1,
1862 "Ignoring CQ Error notification for cmd/cxn"
1863 "invalidate\n");
1864 break;
1865 case SOL_CMD_KILLED_DATA_DIGEST_ERR:
1866 case CMD_KILLED_INVALID_STATSN_RCVD:
1867 case CMD_KILLED_INVALID_R2T_RCVD:
1868 case CMD_CXN_KILLED_LUN_INVALID:
1869 case CMD_CXN_KILLED_ICD_INVALID:
1870 case CMD_CXN_KILLED_ITT_INVALID:
1871 case CMD_CXN_KILLED_SEQ_OUTOFORDER:
1872 case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
32951dd8 1873 SE_DEBUG(DBG_LVL_1,
6733b39a
JK		 1874 "CQ Error notification for cmd.. "
1875 "code %d cid 0x%x\n",
1876 sol->dw[offsetof(struct amap_sol_cqe, code) /
1877 32] & CQE_CODE_MASK,
1878 (sol->dw[offsetof(struct amap_sol_cqe, cid) /
1879 32] & SOL_CID_MASK));
1880 break;
1881 case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
1882 SE_DEBUG(DBG_LVL_1,
1883 "Digest error on def pdu ring, dropping..\n");
1884 hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
1885 (struct i_t_dpdu_cqe *) sol);
1886 break;
1887 case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
1888 case CXN_KILLED_BURST_LEN_MISMATCH:
1889 case CXN_KILLED_AHS_RCVD:
1890 case CXN_KILLED_HDR_DIGEST_ERR:
1891 case CXN_KILLED_UNKNOWN_HDR:
1892 case CXN_KILLED_STALE_ITT_TTT_RCVD:
1893 case CXN_KILLED_INVALID_ITT_TTT_RCVD:
1894 case CXN_KILLED_TIMED_OUT:
1895 case CXN_KILLED_FIN_RCVD:
1896 case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
1897 case CXN_KILLED_BAD_WRB_INDEX_ERROR:
1898 case CXN_KILLED_OVER_RUN_RESIDUAL:
1899 case CXN_KILLED_UNDER_RUN_RESIDUAL:
1900 case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
32951dd8 1901 SE_DEBUG(DBG_LVL_1, "CQ Error %d, reset CID "
6733b39a
JK		 1902 "0x%x...\n",
1903 sol->dw[offsetof(struct amap_sol_cqe, code) /
1904 32] & CQE_CODE_MASK,
7da50879
JK		 1905 (sol->dw[offsetof(struct amap_sol_cqe, cid) /
1906 32] & CQE_CID_MASK));
6733b39a
JK		 1907 iscsi_conn_failure(beiscsi_conn->conn,
1908 ISCSI_ERR_CONN_FAILED);
1909 break;
1910 case CXN_KILLED_RST_SENT:
1911 case CXN_KILLED_RST_RCVD:
32951dd8 1912 SE_DEBUG(DBG_LVL_1, "CQ Error %d, reset"
bfead3b2 1913 "received/sent on CID 0x%x...\n",
6733b39a
JK		 1914 sol->dw[offsetof(struct amap_sol_cqe, code) /
1915 32] & CQE_CODE_MASK,
7da50879
JK		 1916 (sol->dw[offsetof(struct amap_sol_cqe, cid) /
1917 32] & CQE_CID_MASK));
6733b39a
JK		 1918 iscsi_conn_failure(beiscsi_conn->conn,
1919 ISCSI_ERR_CONN_FAILED);
1920 break;
1921 default:
1922 SE_DEBUG(DBG_LVL_1, "CQ Error Invalid code= %d "
1923 "received on CID 0x%x...\n",
1924 sol->dw[offsetof(struct amap_sol_cqe, code) /
1925 32] & CQE_CODE_MASK,
7da50879
JK		 1926 (sol->dw[offsetof(struct amap_sol_cqe, cid) /
1927 32] & CQE_CID_MASK));
6733b39a
JK		 1928 break;
1929 }
1930
1931 AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
1932 queue_tail_inc(cq);
1933 sol = queue_tail_node(cq);
1934 num_processed++;
1935 }
1936
1937 if (num_processed > 0) {
1938 tot_nump += num_processed;
bfead3b2 1939 hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
6733b39a
JK		 1940 }
1941 return tot_nump;
1942}
1943
756d29c8 1944void beiscsi_process_all_cqs(struct work_struct *work)
6733b39a
JK		 1945{
1946 unsigned long flags;
bfead3b2
JK		 1947 struct hwi_controller *phwi_ctrlr;
1948 struct hwi_context_memory *phwi_context;
1949 struct be_eq_obj *pbe_eq;
6733b39a
JK		 1950 struct beiscsi_hba *phba =
1951 container_of(work, struct beiscsi_hba, work_cqs);
1952
bfead3b2
JK		 1953 phwi_ctrlr = phba->phwi_ctrlr;
1954 phwi_context = phwi_ctrlr->phwi_ctxt;
1955 if (phba->msix_enabled)
1956 pbe_eq = &phwi_context->be_eq[phba->num_cpus];
1957 else
1958 pbe_eq = &phwi_context->be_eq[0];
1959
6733b39a
JK		 1960 if (phba->todo_mcc_cq) {
1961 spin_lock_irqsave(&phba->isr_lock, flags);
1962 phba->todo_mcc_cq = 0;
1963 spin_unlock_irqrestore(&phba->isr_lock, flags);
756d29c8 1964 beiscsi_process_mcc_isr(phba);
6733b39a
JK		 1965 }
1966
1967 if (phba->todo_cq) {
1968 spin_lock_irqsave(&phba->isr_lock, flags);
1969 phba->todo_cq = 0;
1970 spin_unlock_irqrestore(&phba->isr_lock, flags);
bfead3b2 1971 beiscsi_process_cq(pbe_eq);
6733b39a
JK		 1972 }
1973}
1974
1975static int be_iopoll(struct blk_iopoll *iop, int budget)
1976{
1977 static unsigned int ret;
1978 struct beiscsi_hba *phba;
bfead3b2 1979 struct be_eq_obj *pbe_eq;
6733b39a 1980
bfead3b2
JK		 1981 pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
1982 ret = beiscsi_process_cq(pbe_eq);
6733b39a 1983 if (ret < budget) {
bfead3b2 1984 phba = pbe_eq->phba;
6733b39a 1985 blk_iopoll_complete(iop);
bfead3b2
JK		 1986 SE_DEBUG(DBG_LVL_8, "rearm pbe_eq->q.id =%d\n", pbe_eq->q.id);
1987 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
6733b39a
JK		 1988 }
1989 return ret;
1990}
1991
1992static void
1993hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
1994 unsigned int num_sg, struct beiscsi_io_task *io_task)
1995{
1996 struct iscsi_sge *psgl;
58ff4bd0 1997 unsigned int sg_len, index;
6733b39a
JK		 1998 unsigned int sge_len = 0;
1999 unsigned long long addr;
2000 struct scatterlist *l_sg;
2001 unsigned int offset;
2002
2003 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2004 io_task->bhs_pa.u.a32.address_lo);
2005 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2006 io_task->bhs_pa.u.a32.address_hi);
2007
2008 l_sg = sg;
48bd86cf
JK		 2009 for (index = 0; (index < num_sg) && (index < 2); index++,
2010 sg = sg_next(sg)) {
6733b39a
JK		 2011 if (index == 0) {
2012 sg_len = sg_dma_len(sg);
2013 addr = (u64) sg_dma_address(sg);
2014 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
457ff3b7 2015 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2016 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
457ff3b7 2017 ((u32)(addr >> 32)));
6733b39a
JK		 2018 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2019 sg_len);
2020 sge_len = sg_len;
6733b39a 2021 } else {
6733b39a
JK		 2022 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
2023 pwrb, sge_len);
2024 sg_len = sg_dma_len(sg);
2025 addr = (u64) sg_dma_address(sg);
2026 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
457ff3b7 2027 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2028 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
457ff3b7 2029 ((u32)(addr >> 32)));
6733b39a
JK		 2030 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
2031 sg_len);
2032 }
2033 }
2034 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2035 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2036
2037 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2038
2039 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2040 io_task->bhs_pa.u.a32.address_hi);
2041 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2042 io_task->bhs_pa.u.a32.address_lo);
2043
caf818f1
JK		 2044 if (num_sg == 1) {
2045 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2046 1);
2047 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2048 0);
2049 } else if (num_sg == 2) {
2050 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2051 0);
2052 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2053 1);
2054 } else {
2055 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2056 0);
2057 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2058 0);
2059 }
6733b39a
JK		 2060 sg = l_sg;
2061 psgl++;
2062 psgl++;
2063 offset = 0;
48bd86cf 2064 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
6733b39a
JK		 2065 sg_len = sg_dma_len(sg);
2066 addr = (u64) sg_dma_address(sg);
2067 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2068 (addr & 0xFFFFFFFF));
2069 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2070 (addr >> 32));
2071 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2072 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2073 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2074 offset += sg_len;
2075 }
2076 psgl--;
2077 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2078}
2079
2080static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
2081{
2082 struct iscsi_sge *psgl;
2083 unsigned long long addr;
2084 struct beiscsi_io_task *io_task = task->dd_data;
2085 struct beiscsi_conn *beiscsi_conn = io_task->conn;
2086 struct beiscsi_hba *phba = beiscsi_conn->phba;
2087
2088 io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
2089 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2090 io_task->bhs_pa.u.a32.address_lo);
2091 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2092 io_task->bhs_pa.u.a32.address_hi);
2093
2094 if (task->data) {
2095 if (task->data_count) {
2096 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
2097 addr = (u64) pci_map_single(phba->pcidev,
2098 task->data,
2099 task->data_count, 1);
2100 } else {
2101 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
2102 addr = 0;
2103 }
2104 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
457ff3b7 2105 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2106 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
457ff3b7 2107 ((u32)(addr >> 32)));
6733b39a
JK		 2108 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2109 task->data_count);
2110
2111 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
2112 } else {
2113 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
2114 addr = 0;
2115 }
2116
2117 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2118
2119 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
2120
2121 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2122 io_task->bhs_pa.u.a32.address_hi);
2123 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2124 io_task->bhs_pa.u.a32.address_lo);
2125 if (task->data) {
2126 psgl++;
2127 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
2128 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
2129 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
2130 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
2131 AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
2132 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2133
2134 psgl++;
2135 if (task->data) {
2136 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
457ff3b7 2137 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2138 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
457ff3b7 2139 ((u32)(addr >> 32)));
6733b39a
JK		 2140 }
2141 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
2142 }
2143 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2144}
2145
2146static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
2147{
bfead3b2 2148 unsigned int num_cq_pages, num_async_pdu_buf_pages;
6733b39a
JK		 2149 unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
2150 unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
2151
2152 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
2153 sizeof(struct sol_cqe));
6733b39a
JK		 2154 num_async_pdu_buf_pages =
2155 PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
2156 phba->params.defpdu_hdr_sz);
2157 num_async_pdu_buf_sgl_pages =
2158 PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
2159 sizeof(struct phys_addr));
2160 num_async_pdu_data_pages =
2161 PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
2162 phba->params.defpdu_data_sz);
2163 num_async_pdu_data_sgl_pages =
2164 PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
2165 sizeof(struct phys_addr));
2166
2167 phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
2168
2169 phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
2170 BE_ISCSI_PDU_HEADER_SIZE;
2171 phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
2172 sizeof(struct hwi_context_memory);
2173
6733b39a
JK		 2174
2175 phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
2176 * (phba->params.wrbs_per_cxn)
2177 * phba->params.cxns_per_ctrl;
2178 wrb_sz_per_cxn = sizeof(struct wrb_handle) *
2179 (phba->params.wrbs_per_cxn);
2180 phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
2181 phba->params.cxns_per_ctrl);
2182
2183 phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
2184 phba->params.icds_per_ctrl;
2185 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
2186 phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
2187
2188 phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
2189 num_async_pdu_buf_pages * PAGE_SIZE;
2190 phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
2191 num_async_pdu_data_pages * PAGE_SIZE;
2192 phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
2193 num_async_pdu_buf_sgl_pages * PAGE_SIZE;
2194 phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
2195 num_async_pdu_data_sgl_pages * PAGE_SIZE;
2196 phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
2197 phba->params.asyncpdus_per_ctrl *
2198 sizeof(struct async_pdu_handle);
2199 phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
2200 phba->params.asyncpdus_per_ctrl *
2201 sizeof(struct async_pdu_handle);
2202 phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
2203 sizeof(struct hwi_async_pdu_context) +
2204 (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
2205}
2206
2207static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
2208{
2209 struct be_mem_descriptor *mem_descr;
2210 dma_addr_t bus_add;
2211 struct mem_array *mem_arr, *mem_arr_orig;
2212 unsigned int i, j, alloc_size, curr_alloc_size;
2213
2214 phba->phwi_ctrlr = kmalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
2215 if (!phba->phwi_ctrlr)
2216 return -ENOMEM;
2217
2218 phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
2219 GFP_KERNEL);
2220 if (!phba->init_mem) {
2221 kfree(phba->phwi_ctrlr);
2222 return -ENOMEM;
2223 }
2224
2225 mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
2226 GFP_KERNEL);
2227 if (!mem_arr_orig) {
2228 kfree(phba->init_mem);
2229 kfree(phba->phwi_ctrlr);
2230 return -ENOMEM;
2231 }
2232
2233 mem_descr = phba->init_mem;
2234 for (i = 0; i < SE_MEM_MAX; i++) {
2235 j = 0;
2236 mem_arr = mem_arr_orig;
2237 alloc_size = phba->mem_req[i];
2238 memset(mem_arr, 0, sizeof(struct mem_array) *
2239 BEISCSI_MAX_FRAGS_INIT);
2240 curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
2241 do {
2242 mem_arr->virtual_address = pci_alloc_consistent(
2243 phba->pcidev,
2244 curr_alloc_size,
2245 &bus_add);
2246 if (!mem_arr->virtual_address) {
2247 if (curr_alloc_size <= BE_MIN_MEM_SIZE)
2248 goto free_mem;
2249 if (curr_alloc_size -
2250 rounddown_pow_of_two(curr_alloc_size))
2251 curr_alloc_size = rounddown_pow_of_two
2252 (curr_alloc_size);
2253 else
2254 curr_alloc_size = curr_alloc_size / 2;
2255 } else {
2256 mem_arr->bus_address.u.
2257 a64.address = (__u64) bus_add;
2258 mem_arr->size = curr_alloc_size;
2259 alloc_size -= curr_alloc_size;
2260 curr_alloc_size = min(be_max_phys_size *
2261 1024, alloc_size);
2262 j++;
2263 mem_arr++;
2264 }
2265 } while (alloc_size);
2266 mem_descr->num_elements = j;
2267 mem_descr->size_in_bytes = phba->mem_req[i];
2268 mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
2269 GFP_KERNEL);
2270 if (!mem_descr->mem_array)
2271 goto free_mem;
2272
2273 memcpy(mem_descr->mem_array, mem_arr_orig,
2274 sizeof(struct mem_array) * j);
2275 mem_descr++;
2276 }
2277 kfree(mem_arr_orig);
2278 return 0;
2279free_mem:
2280 mem_descr->num_elements = j;
2281 while ((i) || (j)) {
2282 for (j = mem_descr->num_elements; j > 0; j--) {
2283 pci_free_consistent(phba->pcidev,
2284 mem_descr->mem_array[j - 1].size,
2285 mem_descr->mem_array[j - 1].
2286 virtual_address,
457ff3b7
JK		 2287 (unsigned long)mem_descr->
2288 mem_array[j - 1].
6733b39a
JK		 2289 bus_address.u.a64.address);
2290 }
2291 if (i) {
2292 i--;
2293 kfree(mem_descr->mem_array);
2294 mem_descr--;
2295 }
2296 }
2297 kfree(mem_arr_orig);
2298 kfree(phba->init_mem);
2299 kfree(phba->phwi_ctrlr);
2300 return -ENOMEM;
2301}
2302
2303static int beiscsi_get_memory(struct beiscsi_hba *phba)
2304{
2305 beiscsi_find_mem_req(phba);
2306 return beiscsi_alloc_mem(phba);
2307}
2308
2309static void iscsi_init_global_templates(struct beiscsi_hba *phba)
2310{
2311 struct pdu_data_out *pdata_out;
2312 struct pdu_nop_out *pnop_out;
2313 struct be_mem_descriptor *mem_descr;
2314
2315 mem_descr = phba->init_mem;
2316 mem_descr += ISCSI_MEM_GLOBAL_HEADER;
2317 pdata_out =
2318 (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
2319 memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2320
2321 AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
2322 IIOC_SCSI_DATA);
2323
2324 pnop_out =
2325 (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
2326 virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
2327
2328 memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2329 AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
2330 AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
2331 AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
2332}
2333
2334static void beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
2335{
2336 struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
2337 struct wrb_handle *pwrb_handle;
2338 struct hwi_controller *phwi_ctrlr;
2339 struct hwi_wrb_context *pwrb_context;
2340 struct iscsi_wrb *pwrb;
2341 unsigned int num_cxn_wrbh;
2342 unsigned int num_cxn_wrb, j, idx, index;
2343
2344 mem_descr_wrbh = phba->init_mem;
2345 mem_descr_wrbh += HWI_MEM_WRBH;
2346
2347 mem_descr_wrb = phba->init_mem;
2348 mem_descr_wrb += HWI_MEM_WRB;
2349
2350 idx = 0;
2351 pwrb_handle = mem_descr_wrbh->mem_array[idx].virtual_address;
2352 num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
2353 ((sizeof(struct wrb_handle)) *
2354 phba->params.wrbs_per_cxn));
2355 phwi_ctrlr = phba->phwi_ctrlr;
2356
2357 for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
2358 pwrb_context = &phwi_ctrlr->wrb_context[index];
6733b39a
JK		 2359 pwrb_context->pwrb_handle_base =
2360 kzalloc(sizeof(struct wrb_handle *) *
2361 phba->params.wrbs_per_cxn, GFP_KERNEL);
2362 pwrb_context->pwrb_handle_basestd =
2363 kzalloc(sizeof(struct wrb_handle *) *
2364 phba->params.wrbs_per_cxn, GFP_KERNEL);
2365 if (num_cxn_wrbh) {
2366 pwrb_context->alloc_index = 0;
2367 pwrb_context->wrb_handles_available = 0;
2368 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2369 pwrb_context->pwrb_handle_base[j] = pwrb_handle;
2370 pwrb_context->pwrb_handle_basestd[j] =
2371 pwrb_handle;
2372 pwrb_context->wrb_handles_available++;
bfead3b2 2373 pwrb_handle->wrb_index = j;
6733b39a
JK		 2374 pwrb_handle++;
2375 }
2376 pwrb_context->free_index = 0;
2377 num_cxn_wrbh--;
2378 } else {
2379 idx++;
2380 pwrb_handle =
2381 mem_descr_wrbh->mem_array[idx].virtual_address;
2382 num_cxn_wrbh =
2383 ((mem_descr_wrbh->mem_array[idx].size) /
2384 ((sizeof(struct wrb_handle)) *
2385 phba->params.wrbs_per_cxn));
2386 pwrb_context->alloc_index = 0;
2387 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2388 pwrb_context->pwrb_handle_base[j] = pwrb_handle;
2389 pwrb_context->pwrb_handle_basestd[j] =
2390 pwrb_handle;
2391 pwrb_context->wrb_handles_available++;
bfead3b2 2392 pwrb_handle->wrb_index = j;
6733b39a
JK		 2393 pwrb_handle++;
2394 }
2395 pwrb_context->free_index = 0;
2396 num_cxn_wrbh--;
2397 }
2398 }
2399 idx = 0;
2400 pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
7c56533c
JK		 2401 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
2402 ((sizeof(struct iscsi_wrb) *
2403 phba->params.wrbs_per_cxn));
ed58ea2a 2404 for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
6733b39a
JK		 2405 pwrb_context = &phwi_ctrlr->wrb_context[index];
2406 if (num_cxn_wrb) {
2407 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2408 pwrb_handle = pwrb_context->pwrb_handle_base[j];
2409 pwrb_handle->pwrb = pwrb;
2410 pwrb++;
2411 }
2412 num_cxn_wrb--;
2413 } else {
2414 idx++;
2415 pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
7c56533c
JK		 2416 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
2417 ((sizeof(struct iscsi_wrb) *
2418 phba->params.wrbs_per_cxn));
6733b39a
JK		 2419 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2420 pwrb_handle = pwrb_context->pwrb_handle_base[j];
2421 pwrb_handle->pwrb = pwrb;
2422 pwrb++;
2423 }
2424 num_cxn_wrb--;
2425 }
2426 }
2427}
2428
2429static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
2430{
2431 struct hwi_controller *phwi_ctrlr;
2432 struct hba_parameters *p = &phba->params;
2433 struct hwi_async_pdu_context *pasync_ctx;
2434 struct async_pdu_handle *pasync_header_h, *pasync_data_h;
dc63aac6 2435 unsigned int index, idx, num_per_mem, num_async_data;
6733b39a
JK		 2436 struct be_mem_descriptor *mem_descr;
2437
2438 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2439 mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
2440
2441 phwi_ctrlr = phba->phwi_ctrlr;
2442 phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
2443 mem_descr->mem_array[0].virtual_address;
2444 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
2445 memset(pasync_ctx, 0, sizeof(*pasync_ctx));
2446
dc63aac6
JK		 2447 pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
2448 pasync_ctx->buffer_size = p->defpdu_hdr_sz;
6733b39a
JK		 2449
2450 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2451 mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
2452 if (mem_descr->mem_array[0].virtual_address) {
2453 SE_DEBUG(DBG_LVL_8,
2454 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_BUF"
457ff3b7 2455 "va=%p\n", mem_descr->mem_array[0].virtual_address);
6733b39a
JK		 2456 } else
2457 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 2458 "No Virtual address\n");
6733b39a
JK		 2459
2460 pasync_ctx->async_header.va_base =
2461 mem_descr->mem_array[0].virtual_address;
2462
2463 pasync_ctx->async_header.pa_base.u.a64.address =
2464 mem_descr->mem_array[0].bus_address.u.a64.address;
2465
2466 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2467 mem_descr += HWI_MEM_ASYNC_HEADER_RING;
2468 if (mem_descr->mem_array[0].virtual_address) {
2469 SE_DEBUG(DBG_LVL_8,
2470 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_RING"
457ff3b7 2471 "va=%p\n", mem_descr->mem_array[0].virtual_address);
6733b39a
JK		 2472 } else
2473 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 2474 "No Virtual address\n");
6733b39a
JK		 2475 pasync_ctx->async_header.ring_base =
2476 mem_descr->mem_array[0].virtual_address;
2477
2478 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2479 mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
2480 if (mem_descr->mem_array[0].virtual_address) {
2481 SE_DEBUG(DBG_LVL_8,
2482 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_HANDLE"
457ff3b7 2483 "va=%p\n", mem_descr->mem_array[0].virtual_address);
6733b39a
JK		 2484 } else
2485 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 2486 "No Virtual address\n");
6733b39a
JK		 2487
2488 pasync_ctx->async_header.handle_base =
2489 mem_descr->mem_array[0].virtual_address;
2490 pasync_ctx->async_header.writables = 0;
2491 INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
2492
6733b39a
JK		 2493
2494 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2495 mem_descr += HWI_MEM_ASYNC_DATA_RING;
2496 if (mem_descr->mem_array[0].virtual_address) {
2497 SE_DEBUG(DBG_LVL_8,
2498 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_DATA_RING"
457ff3b7 2499 "va=%p\n", mem_descr->mem_array[0].virtual_address);
6733b39a
JK		 2500 } else
2501 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 2502 "No Virtual address\n");
6733b39a
JK		 2503
2504 pasync_ctx->async_data.ring_base =
2505 mem_descr->mem_array[0].virtual_address;
2506
2507 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2508 mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
2509 if (!mem_descr->mem_array[0].virtual_address)
2510 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 2511 "No Virtual address\n");
6733b39a
JK		 2512
2513 pasync_ctx->async_data.handle_base =
2514 mem_descr->mem_array[0].virtual_address;
2515 pasync_ctx->async_data.writables = 0;
2516 INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
2517
2518 pasync_header_h =
2519 (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
2520 pasync_data_h =
2521 (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
2522
dc63aac6
JK		 2523 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2524 mem_descr += HWI_MEM_ASYNC_DATA_BUF;
2525 if (mem_descr->mem_array[0].virtual_address) {
2526 SE_DEBUG(DBG_LVL_8,
2527 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_DATA_BUF"
2528 "va=%p\n", mem_descr->mem_array[0].virtual_address);
2529 } else
2530 shost_printk(KERN_WARNING, phba->shost,
2531 "No Virtual address\n");
2532 idx = 0;
2533 pasync_ctx->async_data.va_base =
2534 mem_descr->mem_array[idx].virtual_address;
2535 pasync_ctx->async_data.pa_base.u.a64.address =
2536 mem_descr->mem_array[idx].bus_address.u.a64.address;
2537
2538 num_async_data = ((mem_descr->mem_array[idx].size) /
2539 phba->params.defpdu_data_sz);
2540 num_per_mem = 0;
2541
6733b39a
JK		 2542 for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
2543 pasync_header_h->cri = -1;
2544 pasync_header_h->index = (char)index;
2545 INIT_LIST_HEAD(&pasync_header_h->link);
2546 pasync_header_h->pbuffer =
2547 (void *)((unsigned long)
2548 (pasync_ctx->async_header.va_base) +
2549 (p->defpdu_hdr_sz * index));
2550
2551 pasync_header_h->pa.u.a64.address =
2552 pasync_ctx->async_header.pa_base.u.a64.address +
2553 (p->defpdu_hdr_sz * index);
2554
2555 list_add_tail(&pasync_header_h->link,
2556 &pasync_ctx->async_header.free_list);
2557 pasync_header_h++;
2558 pasync_ctx->async_header.free_entries++;
2559 pasync_ctx->async_header.writables++;
2560
2561 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
2562 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
2563 header_busy_list);
2564 pasync_data_h->cri = -1;
2565 pasync_data_h->index = (char)index;
2566 INIT_LIST_HEAD(&pasync_data_h->link);
dc63aac6
JK		 2567
2568 if (!num_async_data) {
2569 num_per_mem = 0;
2570 idx++;
2571 pasync_ctx->async_data.va_base =
2572 mem_descr->mem_array[idx].virtual_address;
2573 pasync_ctx->async_data.pa_base.u.a64.address =
2574 mem_descr->mem_array[idx].
2575 bus_address.u.a64.address;
2576
2577 num_async_data = ((mem_descr->mem_array[idx].size) /
2578 phba->params.defpdu_data_sz);
2579 }
6733b39a
JK		 2580 pasync_data_h->pbuffer =
2581 (void *)((unsigned long)
2582 (pasync_ctx->async_data.va_base) +
dc63aac6 2583 (p->defpdu_data_sz * num_per_mem));
6733b39a
JK		 2584
2585 pasync_data_h->pa.u.a64.address =
2586 pasync_ctx->async_data.pa_base.u.a64.address +
dc63aac6
JK		 2587 (p->defpdu_data_sz * num_per_mem);
2588 num_per_mem++;
2589 num_async_data--;
6733b39a
JK		 2590
2591 list_add_tail(&pasync_data_h->link,
2592 &pasync_ctx->async_data.free_list);
2593 pasync_data_h++;
2594 pasync_ctx->async_data.free_entries++;
2595 pasync_ctx->async_data.writables++;
2596
2597 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
2598 }
2599
2600 pasync_ctx->async_header.host_write_ptr = 0;
2601 pasync_ctx->async_header.ep_read_ptr = -1;
2602 pasync_ctx->async_data.host_write_ptr = 0;
2603 pasync_ctx->async_data.ep_read_ptr = -1;
2604}
2605
2606static int
2607be_sgl_create_contiguous(void *virtual_address,
2608 u64 physical_address, u32 length,
2609 struct be_dma_mem *sgl)
2610{
2611 WARN_ON(!virtual_address);
2612 WARN_ON(!physical_address);
2613 WARN_ON(!length > 0);
2614 WARN_ON(!sgl);
2615
2616 sgl->va = virtual_address;
457ff3b7 2617 sgl->dma = (unsigned long)physical_address;
6733b39a
JK		 2618 sgl->size = length;
2619
2620 return 0;
2621}
2622
2623static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
2624{
2625 memset(sgl, 0, sizeof(*sgl));
2626}
2627
2628static void
2629hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
2630 struct mem_array *pmem, struct be_dma_mem *sgl)
2631{
2632 if (sgl->va)
2633 be_sgl_destroy_contiguous(sgl);
2634
2635 be_sgl_create_contiguous(pmem->virtual_address,
2636 pmem->bus_address.u.a64.address,
2637 pmem->size, sgl);
2638}
2639
2640static void
2641hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
2642 struct mem_array *pmem, struct be_dma_mem *sgl)
2643{
2644 if (sgl->va)
2645 be_sgl_destroy_contiguous(sgl);
2646
2647 be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
2648 pmem->bus_address.u.a64.address,
2649 pmem->size, sgl);
2650}
2651
2652static int be_fill_queue(struct be_queue_info *q,
2653 u16 len, u16 entry_size, void *vaddress)
2654{
2655 struct be_dma_mem *mem = &q->dma_mem;
2656
2657 memset(q, 0, sizeof(*q));
2658 q->len = len;
2659 q->entry_size = entry_size;
2660 mem->size = len * entry_size;
2661 mem->va = vaddress;
2662 if (!mem->va)
2663 return -ENOMEM;
2664 memset(mem->va, 0, mem->size);
2665 return 0;
2666}
2667
bfead3b2 2668static int beiscsi_create_eqs(struct beiscsi_hba *phba,
6733b39a
JK		 2669 struct hwi_context_memory *phwi_context)
2670{
bfead3b2
JK		 2671 unsigned int i, num_eq_pages;
2672 int ret, eq_for_mcc;
6733b39a
JK		 2673 struct be_queue_info *eq;
2674 struct be_dma_mem *mem;
6733b39a 2675 void *eq_vaddress;
bfead3b2 2676 dma_addr_t paddr;
6733b39a 2677
bfead3b2
JK		 2678 num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
2679 sizeof(struct be_eq_entry));
6733b39a 2680
bfead3b2
JK		 2681 if (phba->msix_enabled)
2682 eq_for_mcc = 1;
2683 else
2684 eq_for_mcc = 0;
2685 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
2686 eq = &phwi_context->be_eq[i].q;
2687 mem = &eq->dma_mem;
2688 phwi_context->be_eq[i].phba = phba;
2689 eq_vaddress = pci_alloc_consistent(phba->pcidev,
2690 num_eq_pages * PAGE_SIZE,
2691 &paddr);
2692 if (!eq_vaddress)
2693 goto create_eq_error;
2694
2695 mem->va = eq_vaddress;
2696 ret = be_fill_queue(eq, phba->params.num_eq_entries,
2697 sizeof(struct be_eq_entry), eq_vaddress);
2698 if (ret) {
2699 shost_printk(KERN_ERR, phba->shost,
457ff3b7 2700 "be_fill_queue Failed for EQ\n");
bfead3b2
JK		 2701 goto create_eq_error;
2702 }
6733b39a 2703
bfead3b2
JK		 2704 mem->dma = paddr;
2705 ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
2706 phwi_context->cur_eqd);
2707 if (ret) {
2708 shost_printk(KERN_ERR, phba->shost,
2709 "beiscsi_cmd_eq_create"
457ff3b7 2710 "Failedfor EQ\n");
bfead3b2
JK		 2711 goto create_eq_error;
2712 }
2713 SE_DEBUG(DBG_LVL_8, "eqid = %d\n", phwi_context->be_eq[i].q.id);
6733b39a 2714 }
6733b39a 2715 return 0;
bfead3b2
JK		 2716create_eq_error:
2717 for (i = 0; i < (phba->num_cpus + 1); i++) {
2718 eq = &phwi_context->be_eq[i].q;
2719 mem = &eq->dma_mem;
2720 if (mem->va)
2721 pci_free_consistent(phba->pcidev, num_eq_pages
2722 * PAGE_SIZE,
2723 mem->va, mem->dma);
2724 }
2725 return ret;
6733b39a
JK		 2726}
2727
bfead3b2 2728static int beiscsi_create_cqs(struct beiscsi_hba *phba,
6733b39a
JK		 2729 struct hwi_context_memory *phwi_context)
2730{
bfead3b2 2731 unsigned int i, num_cq_pages;
6733b39a
JK		 2732 int ret;
2733 struct be_queue_info *cq, *eq;
2734 struct be_dma_mem *mem;
bfead3b2 2735 struct be_eq_obj *pbe_eq;
6733b39a 2736 void *cq_vaddress;
bfead3b2 2737 dma_addr_t paddr;
6733b39a 2738
bfead3b2
JK		 2739 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
2740 sizeof(struct sol_cqe));
6733b39a 2741
bfead3b2
JK		 2742 for (i = 0; i < phba->num_cpus; i++) {
2743 cq = &phwi_context->be_cq[i];
2744 eq = &phwi_context->be_eq[i].q;
2745 pbe_eq = &phwi_context->be_eq[i];
2746 pbe_eq->cq = cq;
2747 pbe_eq->phba = phba;
2748 mem = &cq->dma_mem;
2749 cq_vaddress = pci_alloc_consistent(phba->pcidev,
2750 num_cq_pages * PAGE_SIZE,
2751 &paddr);
2752 if (!cq_vaddress)
2753 goto create_cq_error;
7da50879 2754 ret = be_fill_queue(cq, phba->params.num_cq_entries,
bfead3b2
JK		 2755 sizeof(struct sol_cqe), cq_vaddress);
2756 if (ret) {
2757 shost_printk(KERN_ERR, phba->shost,
457ff3b7 2758 "be_fill_queue Failed for ISCSI CQ\n");
bfead3b2
JK		 2759 goto create_cq_error;
2760 }
2761
2762 mem->dma = paddr;
2763 ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
2764 false, 0);
2765 if (ret) {
2766 shost_printk(KERN_ERR, phba->shost,
2767 "beiscsi_cmd_eq_create"
457ff3b7 2768 "Failed for ISCSI CQ\n");
bfead3b2
JK		 2769 goto create_cq_error;
2770 }
2771 SE_DEBUG(DBG_LVL_8, "iscsi cq_id is %d for eq_id %d\n",
2772 cq->id, eq->id);
2773 SE_DEBUG(DBG_LVL_8, "ISCSI CQ CREATED\n");
6733b39a 2774 }
6733b39a 2775 return 0;
bfead3b2
JK		 2776
2777create_cq_error:
2778 for (i = 0; i < phba->num_cpus; i++) {
2779 cq = &phwi_context->be_cq[i];
2780 mem = &cq->dma_mem;
2781 if (mem->va)
2782 pci_free_consistent(phba->pcidev, num_cq_pages
2783 * PAGE_SIZE,
2784 mem->va, mem->dma);
2785 }
2786 return ret;
2787
6733b39a
JK		 2788}
2789
2790static int
2791beiscsi_create_def_hdr(struct beiscsi_hba *phba,
2792 struct hwi_context_memory *phwi_context,
2793 struct hwi_controller *phwi_ctrlr,
2794 unsigned int def_pdu_ring_sz)
2795{
2796 unsigned int idx;
2797 int ret;
2798 struct be_queue_info *dq, *cq;
2799 struct be_dma_mem *mem;
2800 struct be_mem_descriptor *mem_descr;
2801 void *dq_vaddress;
2802
2803 idx = 0;
2804 dq = &phwi_context->be_def_hdrq;
bfead3b2 2805 cq = &phwi_context->be_cq[0];
6733b39a
JK		 2806 mem = &dq->dma_mem;
2807 mem_descr = phba->init_mem;
2808 mem_descr += HWI_MEM_ASYNC_HEADER_RING;
2809 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
2810 ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
2811 sizeof(struct phys_addr),
2812 sizeof(struct phys_addr), dq_vaddress);
2813 if (ret) {
2814 shost_printk(KERN_ERR, phba->shost,
2815 "be_fill_queue Failed for DEF PDU HDR\n");
2816 return ret;
2817 }
457ff3b7
JK		 2818 mem->dma = (unsigned long)mem_descr->mem_array[idx].
2819 bus_address.u.a64.address;
6733b39a
JK		 2820 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
2821 def_pdu_ring_sz,
2822 phba->params.defpdu_hdr_sz);
2823 if (ret) {
2824 shost_printk(KERN_ERR, phba->shost,
2825 "be_cmd_create_default_pdu_queue Failed DEFHDR\n");
2826 return ret;
2827 }
2828 phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
2829 SE_DEBUG(DBG_LVL_8, "iscsi def pdu id is %d\n",
2830 phwi_context->be_def_hdrq.id);
2831 hwi_post_async_buffers(phba, 1);
2832 return 0;
2833}
2834
2835static int
2836beiscsi_create_def_data(struct beiscsi_hba *phba,
2837 struct hwi_context_memory *phwi_context,
2838 struct hwi_controller *phwi_ctrlr,
2839 unsigned int def_pdu_ring_sz)
2840{
2841 unsigned int idx;
2842 int ret;
2843 struct be_queue_info *dataq, *cq;
2844 struct be_dma_mem *mem;
2845 struct be_mem_descriptor *mem_descr;
2846 void *dq_vaddress;
2847
2848 idx = 0;
2849 dataq = &phwi_context->be_def_dataq;
bfead3b2 2850 cq = &phwi_context->be_cq[0];
6733b39a
JK		 2851 mem = &dataq->dma_mem;
2852 mem_descr = phba->init_mem;
2853 mem_descr += HWI_MEM_ASYNC_DATA_RING;
2854 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
2855 ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
2856 sizeof(struct phys_addr),
2857 sizeof(struct phys_addr), dq_vaddress);
2858 if (ret) {
2859 shost_printk(KERN_ERR, phba->shost,
2860 "be_fill_queue Failed for DEF PDU DATA\n");
2861 return ret;
2862 }
457ff3b7
JK		 2863 mem->dma = (unsigned long)mem_descr->mem_array[idx].
2864 bus_address.u.a64.address;
6733b39a
JK		 2865 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
2866 def_pdu_ring_sz,
2867 phba->params.defpdu_data_sz);
2868 if (ret) {
2869 shost_printk(KERN_ERR, phba->shost,
2870 "be_cmd_create_default_pdu_queue Failed"
2871 " for DEF PDU DATA\n");
2872 return ret;
2873 }
2874 phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
2875 SE_DEBUG(DBG_LVL_8, "iscsi def data id is %d\n",
2876 phwi_context->be_def_dataq.id);
2877 hwi_post_async_buffers(phba, 0);
457ff3b7 2878 SE_DEBUG(DBG_LVL_8, "DEFAULT PDU DATA RING CREATED\n");
6733b39a
JK		 2879 return 0;
2880}
2881
2882static int
2883beiscsi_post_pages(struct beiscsi_hba *phba)
2884{
2885 struct be_mem_descriptor *mem_descr;
2886 struct mem_array *pm_arr;
2887 unsigned int page_offset, i;
2888 struct be_dma_mem sgl;
2889 int status;
2890
2891 mem_descr = phba->init_mem;
2892 mem_descr += HWI_MEM_SGE;
2893 pm_arr = mem_descr->mem_array;
2894
2895 page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
2896 phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
2897 for (i = 0; i < mem_descr->num_elements; i++) {
2898 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
2899 status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
2900 page_offset,
2901 (pm_arr->size / PAGE_SIZE));
2902 page_offset += pm_arr->size / PAGE_SIZE;
2903 if (status != 0) {
2904 shost_printk(KERN_ERR, phba->shost,
2905 "post sgl failed.\n");
2906 return status;
2907 }
2908 pm_arr++;
2909 }
457ff3b7 2910 SE_DEBUG(DBG_LVL_8, "POSTED PAGES\n");
6733b39a
JK		 2911 return 0;
2912}
2913
bfead3b2
JK		 2914static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
2915{
2916 struct be_dma_mem *mem = &q->dma_mem;
2917 if (mem->va)
2918 pci_free_consistent(phba->pcidev, mem->size,
2919 mem->va, mem->dma);
2920}
2921
2922static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
2923 u16 len, u16 entry_size)
2924{
2925 struct be_dma_mem *mem = &q->dma_mem;
2926
2927 memset(q, 0, sizeof(*q));
2928 q->len = len;
2929 q->entry_size = entry_size;
2930 mem->size = len * entry_size;
2931 mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
2932 if (!mem->va)
d3ad2bb3 2933 return -ENOMEM;
bfead3b2
JK		 2934 memset(mem->va, 0, mem->size);
2935 return 0;
2936}
2937
6733b39a
JK		 2938static int
2939beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
2940 struct hwi_context_memory *phwi_context,
2941 struct hwi_controller *phwi_ctrlr)
2942{
2943 unsigned int wrb_mem_index, offset, size, num_wrb_rings;
2944 u64 pa_addr_lo;
2945 unsigned int idx, num, i;
2946 struct mem_array *pwrb_arr;
2947 void *wrb_vaddr;
2948 struct be_dma_mem sgl;
2949 struct be_mem_descriptor *mem_descr;
2950 int status;
2951
2952 idx = 0;
2953 mem_descr = phba->init_mem;
2954 mem_descr += HWI_MEM_WRB;
2955 pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
2956 GFP_KERNEL);
2957 if (!pwrb_arr) {
2958 shost_printk(KERN_ERR, phba->shost,
2959 "Memory alloc failed in create wrb ring.\n");
2960 return -ENOMEM;
2961 }
2962 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
2963 pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
2964 num_wrb_rings = mem_descr->mem_array[idx].size /
2965 (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
2966
2967 for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
2968 if (num_wrb_rings) {
2969 pwrb_arr[num].virtual_address = wrb_vaddr;
2970 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
2971 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
2972 sizeof(struct iscsi_wrb);
2973 wrb_vaddr += pwrb_arr[num].size;
2974 pa_addr_lo += pwrb_arr[num].size;
2975 num_wrb_rings--;
2976 } else {
2977 idx++;
2978 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
2979 pa_addr_lo = mem_descr->mem_array[idx].\
2980 bus_address.u.a64.address;
2981 num_wrb_rings = mem_descr->mem_array[idx].size /
2982 (phba->params.wrbs_per_cxn *
2983 sizeof(struct iscsi_wrb));
2984 pwrb_arr[num].virtual_address = wrb_vaddr;
2985 pwrb_arr[num].bus_address.u.a64.address\
2986 = pa_addr_lo;
2987 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
2988 sizeof(struct iscsi_wrb);
2989 wrb_vaddr += pwrb_arr[num].size;
2990 pa_addr_lo += pwrb_arr[num].size;
2991 num_wrb_rings--;
2992 }
2993 }
2994 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
2995 wrb_mem_index = 0;
2996 offset = 0;
2997 size = 0;
2998
2999 hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
3000 status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
3001 &phwi_context->be_wrbq[i]);
3002 if (status != 0) {
3003 shost_printk(KERN_ERR, phba->shost,
3004 "wrbq create failed.");
1462b8ff 3005 kfree(pwrb_arr);
6733b39a
JK		 3006 return status;
3007 }
7da50879
JK		 3008 phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i].
3009 id;
6733b39a
JK		 3010 }
3011 kfree(pwrb_arr);
3012 return 0;
3013}
3014
3015static void free_wrb_handles(struct beiscsi_hba *phba)
3016{
3017 unsigned int index;
3018 struct hwi_controller *phwi_ctrlr;
3019 struct hwi_wrb_context *pwrb_context;
3020
3021 phwi_ctrlr = phba->phwi_ctrlr;
3022 for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
3023 pwrb_context = &phwi_ctrlr->wrb_context[index];
3024 kfree(pwrb_context->pwrb_handle_base);
3025 kfree(pwrb_context->pwrb_handle_basestd);
3026 }
3027}
3028
bfead3b2
JK		 3029static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
3030{
3031 struct be_queue_info *q;
3032 struct be_ctrl_info *ctrl = &phba->ctrl;
3033
3034 q = &phba->ctrl.mcc_obj.q;
3035 if (q->created)
3036 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
3037 be_queue_free(phba, q);
3038
3039 q = &phba->ctrl.mcc_obj.cq;
3040 if (q->created)
3041 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
3042 be_queue_free(phba, q);
3043}
3044
6733b39a
JK		 3045static void hwi_cleanup(struct beiscsi_hba *phba)
3046{
3047 struct be_queue_info *q;
3048 struct be_ctrl_info *ctrl = &phba->ctrl;
3049 struct hwi_controller *phwi_ctrlr;
3050 struct hwi_context_memory *phwi_context;
bfead3b2 3051 int i, eq_num;
6733b39a
JK		 3052
3053 phwi_ctrlr = phba->phwi_ctrlr;
3054 phwi_context = phwi_ctrlr->phwi_ctxt;
3055 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3056 q = &phwi_context->be_wrbq[i];
3057 if (q->created)
3058 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
3059 }
6733b39a
JK		 3060 free_wrb_handles(phba);
3061
3062 q = &phwi_context->be_def_hdrq;
3063 if (q->created)
3064 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3065
3066 q = &phwi_context->be_def_dataq;
3067 if (q->created)
3068 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3069
3070 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
3071
bfead3b2
JK		 3072 for (i = 0; i < (phba->num_cpus); i++) {
3073 q = &phwi_context->be_cq[i];
3074 if (q->created)
3075 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
3076 }
3077 if (phba->msix_enabled)
3078 eq_num = 1;
3079 else
3080 eq_num = 0;
3081 for (i = 0; i < (phba->num_cpus + eq_num); i++) {
3082 q = &phwi_context->be_eq[i].q;
3083 if (q->created)
3084 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
3085 }
3086 be_mcc_queues_destroy(phba);
3087}
6733b39a 3088
bfead3b2
JK		 3089static int be_mcc_queues_create(struct beiscsi_hba *phba,
3090 struct hwi_context_memory *phwi_context)
3091{
3092 struct be_queue_info *q, *cq;
3093 struct be_ctrl_info *ctrl = &phba->ctrl;
3094
3095 /* Alloc MCC compl queue */
3096 cq = &phba->ctrl.mcc_obj.cq;
3097 if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
3098 sizeof(struct be_mcc_compl)))
3099 goto err;
3100 /* Ask BE to create MCC compl queue; */
3101 if (phba->msix_enabled) {
3102 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
3103 [phba->num_cpus].q, false, true, 0))
3104 goto mcc_cq_free;
3105 } else {
3106 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
3107 false, true, 0))
3108 goto mcc_cq_free;
3109 }
3110
3111 /* Alloc MCC queue */
3112 q = &phba->ctrl.mcc_obj.q;
3113 if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
3114 goto mcc_cq_destroy;
3115
3116 /* Ask BE to create MCC queue */
35e66019 3117 if (beiscsi_cmd_mccq_create(phba, q, cq))
bfead3b2
JK		 3118 goto mcc_q_free;
3119
3120 return 0;
3121
3122mcc_q_free:
3123 be_queue_free(phba, q);
3124mcc_cq_destroy:
3125 beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
3126mcc_cq_free:
3127 be_queue_free(phba, cq);
3128err:
d3ad2bb3 3129 return -ENOMEM;
bfead3b2
JK		 3130}
3131
3132static int find_num_cpus(void)
3133{
3134 int num_cpus = 0;
3135
3136 num_cpus = num_online_cpus();
3137 if (num_cpus >= MAX_CPUS)
3138 num_cpus = MAX_CPUS - 1;
3139
457ff3b7 3140 SE_DEBUG(DBG_LVL_8, "num_cpus = %d\n", num_cpus);
bfead3b2 3141 return num_cpus;
6733b39a
JK		 3142}
3143
3144static int hwi_init_port(struct beiscsi_hba *phba)
3145{
3146 struct hwi_controller *phwi_ctrlr;
3147 struct hwi_context_memory *phwi_context;
3148 unsigned int def_pdu_ring_sz;
3149 struct be_ctrl_info *ctrl = &phba->ctrl;
3150 int status;
3151
3152 def_pdu_ring_sz =
3153 phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
3154 phwi_ctrlr = phba->phwi_ctrlr;
6733b39a 3155 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 3156 phwi_context->max_eqd = 0;
3157 phwi_context->min_eqd = 0;
3158 phwi_context->cur_eqd = 64;
6733b39a 3159 be_cmd_fw_initialize(&phba->ctrl);
bfead3b2
JK		 3160
3161 status = beiscsi_create_eqs(phba, phwi_context);
6733b39a 3162 if (status != 0) {
457ff3b7 3163 shost_printk(KERN_ERR, phba->shost, "EQ not created\n");
6733b39a
JK		 3164 goto error;
3165 }
3166
bfead3b2
JK		 3167 status = be_mcc_queues_create(phba, phwi_context);
3168 if (status != 0)
3169 goto error;
3170
3171 status = mgmt_check_supported_fw(ctrl, phba);
6733b39a
JK		 3172 if (status != 0) {
3173 shost_printk(KERN_ERR, phba->shost,
457ff3b7 3174 "Unsupported fw version\n");
6733b39a
JK		 3175 goto error;
3176 }
3177
bfead3b2 3178 status = beiscsi_create_cqs(phba, phwi_context);
6733b39a
JK		 3179 if (status != 0) {
3180 shost_printk(KERN_ERR, phba->shost, "CQ not created\n");
3181 goto error;
3182 }
3183
3184 status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
3185 def_pdu_ring_sz);
3186 if (status != 0) {
3187 shost_printk(KERN_ERR, phba->shost,
3188 "Default Header not created\n");
3189 goto error;
3190 }
3191
3192 status = beiscsi_create_def_data(phba, phwi_context,
3193 phwi_ctrlr, def_pdu_ring_sz);
3194 if (status != 0) {
3195 shost_printk(KERN_ERR, phba->shost,
3196 "Default Data not created\n");
3197 goto error;
3198 }
3199
3200 status = beiscsi_post_pages(phba);
3201 if (status != 0) {
3202 shost_printk(KERN_ERR, phba->shost, "Post SGL Pages Failed\n");
3203 goto error;
3204 }
3205
3206 status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
3207 if (status != 0) {
3208 shost_printk(KERN_ERR, phba->shost,
3209 "WRB Rings not created\n");
3210 goto error;
3211 }
3212
3213 SE_DEBUG(DBG_LVL_8, "hwi_init_port success\n");
3214 return 0;
3215
3216error:
3217 shost_printk(KERN_ERR, phba->shost, "hwi_init_port failed");
3218 hwi_cleanup(phba);
3219 return -ENOMEM;
3220}
3221
6733b39a
JK		 3222static int hwi_init_controller(struct beiscsi_hba *phba)
3223{
3224 struct hwi_controller *phwi_ctrlr;
3225
3226 phwi_ctrlr = phba->phwi_ctrlr;
3227 if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
3228 phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
3229 init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
457ff3b7 3230 SE_DEBUG(DBG_LVL_8, " phwi_ctrlr->phwi_ctxt=%p\n",
6733b39a
JK		 3231 phwi_ctrlr->phwi_ctxt);
3232 } else {
3233 shost_printk(KERN_ERR, phba->shost,
3234 "HWI_MEM_ADDN_CONTEXT is more than one element."
3235 "Failing to load\n");
3236 return -ENOMEM;
3237 }
3238
3239 iscsi_init_global_templates(phba);
3240 beiscsi_init_wrb_handle(phba);
3241 hwi_init_async_pdu_ctx(phba);
3242 if (hwi_init_port(phba) != 0) {
3243 shost_printk(KERN_ERR, phba->shost,
3244 "hwi_init_controller failed\n");
3245 return -ENOMEM;
3246 }
3247 return 0;
3248}
3249
3250static void beiscsi_free_mem(struct beiscsi_hba *phba)
3251{
3252 struct be_mem_descriptor *mem_descr;
3253 int i, j;
3254
3255 mem_descr = phba->init_mem;
3256 i = 0;
3257 j = 0;
3258 for (i = 0; i < SE_MEM_MAX; i++) {
3259 for (j = mem_descr->num_elements; j > 0; j--) {
3260 pci_free_consistent(phba->pcidev,
3261 mem_descr->mem_array[j - 1].size,
3262 mem_descr->mem_array[j - 1].virtual_address,
457ff3b7
JK		 3263 (unsigned long)mem_descr->mem_array[j - 1].
3264 bus_address.u.a64.address);
6733b39a
JK		 3265 }
3266 kfree(mem_descr->mem_array);
3267 mem_descr++;
3268 }
3269 kfree(phba->init_mem);
3270 kfree(phba->phwi_ctrlr);
3271}
3272
3273static int beiscsi_init_controller(struct beiscsi_hba *phba)
3274{
3275 int ret = -ENOMEM;
3276
3277 ret = beiscsi_get_memory(phba);
3278 if (ret < 0) {
3279 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe -"
457ff3b7 3280 "Failed in beiscsi_alloc_memory\n");
6733b39a
JK		 3281 return ret;
3282 }
3283
3284 ret = hwi_init_controller(phba);
3285 if (ret)
3286 goto free_init;
3287 SE_DEBUG(DBG_LVL_8, "Return success from beiscsi_init_controller");
3288 return 0;
3289
3290free_init:
3291 beiscsi_free_mem(phba);
3292 return -ENOMEM;
3293}
3294
3295static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
3296{
3297 struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
3298 struct sgl_handle *psgl_handle;
3299 struct iscsi_sge *pfrag;
3300 unsigned int arr_index, i, idx;
3301
3302 phba->io_sgl_hndl_avbl = 0;
3303 phba->eh_sgl_hndl_avbl = 0;
bfead3b2 3304
6733b39a
JK		 3305 mem_descr_sglh = phba->init_mem;
3306 mem_descr_sglh += HWI_MEM_SGLH;
3307 if (1 == mem_descr_sglh->num_elements) {
3308 phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
3309 phba->params.ios_per_ctrl,
3310 GFP_KERNEL);
3311 if (!phba->io_sgl_hndl_base) {
3312 shost_printk(KERN_ERR, phba->shost,
3313 "Mem Alloc Failed. Failing to load\n");
3314 return -ENOMEM;
3315 }
3316 phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
3317 (phba->params.icds_per_ctrl -
3318 phba->params.ios_per_ctrl),
3319 GFP_KERNEL);
3320 if (!phba->eh_sgl_hndl_base) {
3321 kfree(phba->io_sgl_hndl_base);
3322 shost_printk(KERN_ERR, phba->shost,
3323 "Mem Alloc Failed. Failing to load\n");
3324 return -ENOMEM;
3325 }
3326 } else {
3327 shost_printk(KERN_ERR, phba->shost,
3328 "HWI_MEM_SGLH is more than one element."
3329 "Failing to load\n");
3330 return -ENOMEM;
3331 }
3332
3333 arr_index = 0;
3334 idx = 0;
3335 while (idx < mem_descr_sglh->num_elements) {
3336 psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
3337
3338 for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
3339 sizeof(struct sgl_handle)); i++) {
3340 if (arr_index < phba->params.ios_per_ctrl) {
3341 phba->io_sgl_hndl_base[arr_index] = psgl_handle;
3342 phba->io_sgl_hndl_avbl++;
3343 arr_index++;
3344 } else {
3345 phba->eh_sgl_hndl_base[arr_index -
3346 phba->params.ios_per_ctrl] =
3347 psgl_handle;
3348 arr_index++;
3349 phba->eh_sgl_hndl_avbl++;
3350 }
3351 psgl_handle++;
3352 }
3353 idx++;
3354 }
3355 SE_DEBUG(DBG_LVL_8,
3356 "phba->io_sgl_hndl_avbl=%d"
457ff3b7 3357 "phba->eh_sgl_hndl_avbl=%d\n",
6733b39a
JK		 3358 phba->io_sgl_hndl_avbl,
3359 phba->eh_sgl_hndl_avbl);
3360 mem_descr_sg = phba->init_mem;
3361 mem_descr_sg += HWI_MEM_SGE;
457ff3b7 3362 SE_DEBUG(DBG_LVL_8, "\n mem_descr_sg->num_elements=%d\n",
6733b39a
JK		 3363 mem_descr_sg->num_elements);
3364 arr_index = 0;
3365 idx = 0;
3366 while (idx < mem_descr_sg->num_elements) {
3367 pfrag = mem_descr_sg->mem_array[idx].virtual_address;
3368
3369 for (i = 0;
3370 i < (mem_descr_sg->mem_array[idx].size) /
3371 (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
3372 i++) {
3373 if (arr_index < phba->params.ios_per_ctrl)
3374 psgl_handle = phba->io_sgl_hndl_base[arr_index];
3375 else
3376 psgl_handle = phba->eh_sgl_hndl_base[arr_index -
3377 phba->params.ios_per_ctrl];
3378 psgl_handle->pfrag = pfrag;
3379 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
3380 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
3381 pfrag += phba->params.num_sge_per_io;
3382 psgl_handle->sgl_index =
7da50879 3383 phba->fw_config.iscsi_icd_start + arr_index++;
6733b39a
JK		 3384 }
3385 idx++;
3386 }
3387 phba->io_sgl_free_index = 0;
3388 phba->io_sgl_alloc_index = 0;
3389 phba->eh_sgl_free_index = 0;
3390 phba->eh_sgl_alloc_index = 0;
3391 return 0;
3392}
3393
3394static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
3395{
3396 int i, new_cid;
3397
c2462288 3398 phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
6733b39a
JK		 3399 GFP_KERNEL);
3400 if (!phba->cid_array) {
3401 shost_printk(KERN_ERR, phba->shost,
3402 "Failed to allocate memory in "
3403 "hba_setup_cid_tbls\n");
3404 return -ENOMEM;
3405 }
c2462288 3406 phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
6733b39a
JK		 3407 phba->params.cxns_per_ctrl * 2, GFP_KERNEL);
3408 if (!phba->ep_array) {
3409 shost_printk(KERN_ERR, phba->shost,
3410 "Failed to allocate memory in "
457ff3b7 3411 "hba_setup_cid_tbls\n");
6733b39a
JK		 3412 kfree(phba->cid_array);
3413 return -ENOMEM;
3414 }
7da50879 3415 new_cid = phba->fw_config.iscsi_cid_start;
6733b39a
JK		 3416 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3417 phba->cid_array[i] = new_cid;
3418 new_cid += 2;
3419 }
3420 phba->avlbl_cids = phba->params.cxns_per_ctrl;
3421 return 0;
3422}
3423
238f6b72 3424static void hwi_enable_intr(struct beiscsi_hba *phba)
6733b39a
JK		 3425{
3426 struct be_ctrl_info *ctrl = &phba->ctrl;
3427 struct hwi_controller *phwi_ctrlr;
3428 struct hwi_context_memory *phwi_context;
3429 struct be_queue_info *eq;
3430 u8 __iomem *addr;
bfead3b2 3431 u32 reg, i;
6733b39a
JK		 3432 u32 enabled;
3433
3434 phwi_ctrlr = phba->phwi_ctrlr;
3435 phwi_context = phwi_ctrlr->phwi_ctxt;
3436
6733b39a
JK		 3437 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
3438 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
3439 reg = ioread32(addr);
6733b39a
JK		 3440
3441 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
3442 if (!enabled) {
3443 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
457ff3b7 3444 SE_DEBUG(DBG_LVL_8, "reg =x%08x addr=%p\n", reg, addr);
6733b39a 3445 iowrite32(reg, addr);
665d6d94
JK		 3446 }
3447
3448 if (!phba->msix_enabled) {
3449 eq = &phwi_context->be_eq[0].q;
3450 SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
3451 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
3452 } else {
3453 for (i = 0; i <= phba->num_cpus; i++) {
3454 eq = &phwi_context->be_eq[i].q;
457ff3b7 3455 SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
bfead3b2
JK		 3456 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
3457 }
c03af1ae 3458 }
6733b39a
JK		 3459}
3460
3461static void hwi_disable_intr(struct beiscsi_hba *phba)
3462{
3463 struct be_ctrl_info *ctrl = &phba->ctrl;
3464
3465 u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
3466 u32 reg = ioread32(addr);
3467
3468 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
3469 if (enabled) {
3470 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
3471 iowrite32(reg, addr);
3472 } else
3473 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 3474 "In hwi_disable_intr, Already Disabled\n");
6733b39a
JK		 3475}
3476
c7acc5b8
JK		 3477static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
3478{
3479 struct be_cmd_resp_get_boot_target *boot_resp;
3480 struct be_cmd_resp_get_session *session_resp;
3481 struct be_mcc_wrb *wrb;
3482 struct be_dma_mem nonemb_cmd;
3483 unsigned int tag, wrb_num;
3484 unsigned short status, extd_status;
3485 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
f457a46f 3486 int ret = -ENOMEM;
c7acc5b8
JK		 3487
3488 tag = beiscsi_get_boot_target(phba);
3489 if (!tag) {
3490 SE_DEBUG(DBG_LVL_1, "be_cmd_get_mac_addr Failed\n");
3491 return -EAGAIN;
3492 } else
3493 wait_event_interruptible(phba->ctrl.mcc_wait[tag],
3494 phba->ctrl.mcc_numtag[tag]);
3495
3496 wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
3497 extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
3498 status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
3499 if (status || extd_status) {
3500 SE_DEBUG(DBG_LVL_1, "be_cmd_get_mac_addr Failed"
3501 " status = %d extd_status = %d\n",
3502 status, extd_status);
3503 free_mcc_tag(&phba->ctrl, tag);
3504 return -EBUSY;
3505 }
3506 wrb = queue_get_wrb(mccq, wrb_num);
3507 free_mcc_tag(&phba->ctrl, tag);
3508 boot_resp = embedded_payload(wrb);
3509
3510 if (boot_resp->boot_session_handle < 0) {
f457a46f 3511 shost_printk(KERN_INFO, phba->shost, "No Boot Session.\n");
c7acc5b8
JK		 3512 return -ENXIO;
3513 }
3514
3515 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
3516 sizeof(*session_resp),
3517 &nonemb_cmd.dma);
3518 if (nonemb_cmd.va == NULL) {
3519 SE_DEBUG(DBG_LVL_1,
3520 "Failed to allocate memory for"
3521 "beiscsi_get_session_info\n");
3522 return -ENOMEM;
3523 }
3524
3525 memset(nonemb_cmd.va, 0, sizeof(*session_resp));
3526 tag = beiscsi_get_session_info(phba,
3527 boot_resp->boot_session_handle, &nonemb_cmd);
3528 if (!tag) {
3529 SE_DEBUG(DBG_LVL_1, "beiscsi_get_session_info"
3530 " Failed\n");
3531 goto boot_freemem;
3532 } else
3533 wait_event_interruptible(phba->ctrl.mcc_wait[tag],
3534 phba->ctrl.mcc_numtag[tag]);
3535
3536 wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
3537 extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
3538 status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
3539 if (status || extd_status) {
3540 SE_DEBUG(DBG_LVL_1, "beiscsi_get_session_info Failed"
3541 " status = %d extd_status = %d\n",
3542 status, extd_status);
3543 free_mcc_tag(&phba->ctrl, tag);
3544 goto boot_freemem;
3545 }
3546 wrb = queue_get_wrb(mccq, wrb_num);
3547 free_mcc_tag(&phba->ctrl, tag);
3548 session_resp = nonemb_cmd.va ;
f457a46f 3549
c7acc5b8
JK		 3550 memcpy(&phba->boot_sess, &session_resp->session_info,
3551 sizeof(struct mgmt_session_info));
f457a46f
MC		 3552 ret = 0;
3553
c7acc5b8
JK		 3554boot_freemem:
3555 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
3556 nonemb_cmd.va, nonemb_cmd.dma);
f457a46f
MC		 3557 return ret;
3558}
3559
3560static void beiscsi_boot_release(void *data)
3561{
3562 struct beiscsi_hba *phba = data;
3563
3564 scsi_host_put(phba->shost);
3565}
3566
3567static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
3568{
3569 struct iscsi_boot_kobj *boot_kobj;
3570
3571 /* get boot info using mgmt cmd */
3572 if (beiscsi_get_boot_info(phba))
3573 /* Try to see if we can carry on without this */
3574 return 0;
3575
3576 phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
3577 if (!phba->boot_kset)
3578 return -ENOMEM;
3579
3580 /* get a ref because the show function will ref the phba */
3581 if (!scsi_host_get(phba->shost))
3582 goto free_kset;
3583 boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
3584 beiscsi_show_boot_tgt_info,
3585 beiscsi_tgt_get_attr_visibility,
3586 beiscsi_boot_release);
3587 if (!boot_kobj)
3588 goto put_shost;
3589
3590 if (!scsi_host_get(phba->shost))
3591 goto free_kset;
3592 boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
3593 beiscsi_show_boot_ini_info,
3594 beiscsi_ini_get_attr_visibility,
3595 beiscsi_boot_release);
3596 if (!boot_kobj)
3597 goto put_shost;
3598
3599 if (!scsi_host_get(phba->shost))
3600 goto free_kset;
3601 boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
3602 beiscsi_show_boot_eth_info,
3603 beiscsi_eth_get_attr_visibility,
3604 beiscsi_boot_release);
3605 if (!boot_kobj)
3606 goto put_shost;
3607 return 0;
3608
3609put_shost:
3610 scsi_host_put(phba->shost);
3611free_kset:
3612 iscsi_boot_destroy_kset(phba->boot_kset);
c7acc5b8
JK		 3613 return -ENOMEM;
3614}
3615
6733b39a
JK		 3616static int beiscsi_init_port(struct beiscsi_hba *phba)
3617{
3618 int ret;
3619
3620 ret = beiscsi_init_controller(phba);
3621 if (ret < 0) {
3622 shost_printk(KERN_ERR, phba->shost,
3623 "beiscsi_dev_probe - Failed in"
457ff3b7 3624 "beiscsi_init_controller\n");
6733b39a
JK		 3625 return ret;
3626 }
3627 ret = beiscsi_init_sgl_handle(phba);
3628 if (ret < 0) {
3629 shost_printk(KERN_ERR, phba->shost,
3630 "beiscsi_dev_probe - Failed in"
457ff3b7 3631 "beiscsi_init_sgl_handle\n");
6733b39a
JK		 3632 goto do_cleanup_ctrlr;
3633 }
3634
3635 if (hba_setup_cid_tbls(phba)) {
3636 shost_printk(KERN_ERR, phba->shost,
3637 "Failed in hba_setup_cid_tbls\n");
3638 kfree(phba->io_sgl_hndl_base);
3639 kfree(phba->eh_sgl_hndl_base);
3640 goto do_cleanup_ctrlr;
3641 }
3642
3643 return ret;
3644
3645do_cleanup_ctrlr:
3646 hwi_cleanup(phba);
3647 return ret;
3648}
3649
3650static void hwi_purge_eq(struct beiscsi_hba *phba)
3651{
3652 struct hwi_controller *phwi_ctrlr;
3653 struct hwi_context_memory *phwi_context;
3654 struct be_queue_info *eq;
3655 struct be_eq_entry *eqe = NULL;
bfead3b2 3656 int i, eq_msix;
756d29c8 3657 unsigned int num_processed;
6733b39a
JK		 3658
3659 phwi_ctrlr = phba->phwi_ctrlr;
3660 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 3661 if (phba->msix_enabled)
3662 eq_msix = 1;
3663 else
3664 eq_msix = 0;
6733b39a 3665
bfead3b2
JK		 3666 for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
3667 eq = &phwi_context->be_eq[i].q;
6733b39a 3668 eqe = queue_tail_node(eq);
756d29c8 3669 num_processed = 0;
bfead3b2
JK		 3670 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
3671 & EQE_VALID_MASK) {
3672 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
3673 queue_tail_inc(eq);
3674 eqe = queue_tail_node(eq);
756d29c8 3675 num_processed++;
bfead3b2 3676 }
756d29c8
JK		 3677
3678 if (num_processed)
3679 hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
6733b39a
JK		 3680 }
3681}
3682
3683static void beiscsi_clean_port(struct beiscsi_hba *phba)
3684{
03a12310 3685 int mgmt_status;
6733b39a
JK		 3686
3687 mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
3688 if (mgmt_status)
3689 shost_printk(KERN_WARNING, phba->shost,
457ff3b7 3690 "mgmt_epfw_cleanup FAILED\n");
756d29c8 3691
6733b39a 3692 hwi_purge_eq(phba);
756d29c8 3693 hwi_cleanup(phba);
6733b39a
JK		 3694 kfree(phba->io_sgl_hndl_base);
3695 kfree(phba->eh_sgl_hndl_base);
3696 kfree(phba->cid_array);
3697 kfree(phba->ep_array);
3698}
3699
3700void
3701beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
3702 struct beiscsi_offload_params *params)
3703{
3704 struct wrb_handle *pwrb_handle;
3705 struct iscsi_target_context_update_wrb *pwrb = NULL;
3706 struct be_mem_descriptor *mem_descr;
3707 struct beiscsi_hba *phba = beiscsi_conn->phba;
3708 u32 doorbell = 0;
3709
3710 /*
3711 * We can always use 0 here because it is reserved by libiscsi for
3712 * login/startup related tasks.
3713 */
7da50879 3714 pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid -
d5431488 3715 phba->fw_config.iscsi_cid_start));
6733b39a
JK		 3716 pwrb = (struct iscsi_target_context_update_wrb *)pwrb_handle->pwrb;
3717 memset(pwrb, 0, sizeof(*pwrb));
3718 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
3719 max_burst_length, pwrb, params->dw[offsetof
3720 (struct amap_beiscsi_offload_params,
3721 max_burst_length) / 32]);
3722 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
3723 max_send_data_segment_length, pwrb,
3724 params->dw[offsetof(struct amap_beiscsi_offload_params,
3725 max_send_data_segment_length) / 32]);
3726 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
3727 first_burst_length,
3728 pwrb,
3729 params->dw[offsetof(struct amap_beiscsi_offload_params,
3730 first_burst_length) / 32]);
3731
3732 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, erl, pwrb,
3733 (params->dw[offsetof(struct amap_beiscsi_offload_params,
3734 erl) / 32] & OFFLD_PARAMS_ERL));
3735 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, dde, pwrb,
3736 (params->dw[offsetof(struct amap_beiscsi_offload_params,
3737 dde) / 32] & OFFLD_PARAMS_DDE) >> 2);
3738 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, hde, pwrb,
3739 (params->dw[offsetof(struct amap_beiscsi_offload_params,
3740 hde) / 32] & OFFLD_PARAMS_HDE) >> 3);
3741 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ir2t, pwrb,
3742 (params->dw[offsetof(struct amap_beiscsi_offload_params,
3743 ir2t) / 32] & OFFLD_PARAMS_IR2T) >> 4);
3744 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, imd, pwrb,
3745 (params->dw[offsetof(struct amap_beiscsi_offload_params,
3746 imd) / 32] & OFFLD_PARAMS_IMD) >> 5);
3747 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, stat_sn,
3748 pwrb,
3749 (params->dw[offsetof(struct amap_beiscsi_offload_params,
3750 exp_statsn) / 32] + 1));
3751 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, type, pwrb,
3752 0x7);
3753 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, wrb_idx,
3754 pwrb, pwrb_handle->wrb_index);
3755 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ptr2nextwrb,
3756 pwrb, pwrb_handle->nxt_wrb_index);
3757 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
3758 session_state, pwrb, 0);
3759 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, compltonack,
3760 pwrb, 1);
3761 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, notpredblq,
3762 pwrb, 0);
3763 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, mode, pwrb,
3764 0);
3765
3766 mem_descr = phba->init_mem;
3767 mem_descr += ISCSI_MEM_GLOBAL_HEADER;
3768
3769 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
3770 pad_buffer_addr_hi, pwrb,
3771 mem_descr->mem_array[0].bus_address.u.a32.address_hi);
3772 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
3773 pad_buffer_addr_lo, pwrb,
3774 mem_descr->mem_array[0].bus_address.u.a32.address_lo);
3775
3776 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_target_context_update_wrb));
3777
3778 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 3779 doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
bfead3b2 3780 << DB_DEF_PDU_WRB_INDEX_SHIFT;
6733b39a
JK		 3781 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
3782
3783 iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
3784}
3785
3786static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
3787 int *index, int *age)
3788{
bfead3b2 3789 *index = (int)itt;
6733b39a
JK		 3790 if (age)
3791 *age = conn->session->age;
3792}
3793
3794/**
3795 * beiscsi_alloc_pdu - allocates pdu and related resources
3796 * @task: libiscsi task
3797 * @opcode: opcode of pdu for task
3798 *
3799 * This is called with the session lock held. It will allocate
3800 * the wrb and sgl if needed for the command. And it will prep
3801 * the pdu's itt. beiscsi_parse_pdu will later translate
3802 * the pdu itt to the libiscsi task itt.
3803 */
3804static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
3805{
3806 struct beiscsi_io_task *io_task = task->dd_data;
3807 struct iscsi_conn *conn = task->conn;
3808 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
3809 struct beiscsi_hba *phba = beiscsi_conn->phba;
3810 struct hwi_wrb_context *pwrb_context;
3811 struct hwi_controller *phwi_ctrlr;
3812 itt_t itt;
2afc95bf
JK		 3813 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
3814 dma_addr_t paddr;
6733b39a 3815
2afc95bf 3816 io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
bc7accec 3817 GFP_ATOMIC, &paddr);
2afc95bf
JK		 3818 if (!io_task->cmd_bhs)
3819 return -ENOMEM;
2afc95bf 3820 io_task->bhs_pa.u.a64.address = paddr;
bfead3b2 3821 io_task->libiscsi_itt = (itt_t)task->itt;
6733b39a
JK		 3822 io_task->conn = beiscsi_conn;
3823
3824 task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
3825 task->hdr_max = sizeof(struct be_cmd_bhs);
d2cecf0d
JK		 3826 io_task->psgl_handle = NULL;
3827 io_task->psgl_handle = NULL;
6733b39a
JK		 3828
3829 if (task->sc) {
3830 spin_lock(&phba->io_sgl_lock);
3831 io_task->psgl_handle = alloc_io_sgl_handle(phba);
3832 spin_unlock(&phba->io_sgl_lock);
2afc95bf
JK		 3833 if (!io_task->psgl_handle)
3834 goto free_hndls;
d2cecf0d
JK		 3835 io_task->pwrb_handle = alloc_wrb_handle(phba,
3836 beiscsi_conn->beiscsi_conn_cid -
3837 phba->fw_config.iscsi_cid_start);
3838 if (!io_task->pwrb_handle)
3839 goto free_io_hndls;
6733b39a
JK		 3840 } else {
3841 io_task->scsi_cmnd = NULL;
d7aea67b 3842 if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
6733b39a
JK		 3843 if (!beiscsi_conn->login_in_progress) {
3844 spin_lock(&phba->mgmt_sgl_lock);
3845 io_task->psgl_handle = (struct sgl_handle *)
3846 alloc_mgmt_sgl_handle(phba);
3847 spin_unlock(&phba->mgmt_sgl_lock);
2afc95bf
JK		 3848 if (!io_task->psgl_handle)
3849 goto free_hndls;
3850
6733b39a
JK		 3851 beiscsi_conn->login_in_progress = 1;
3852 beiscsi_conn->plogin_sgl_handle =
3853 io_task->psgl_handle;
d2cecf0d
JK		 3854 io_task->pwrb_handle =
3855 alloc_wrb_handle(phba,
3856 beiscsi_conn->beiscsi_conn_cid -
3857 phba->fw_config.iscsi_cid_start);
3858 if (!io_task->pwrb_handle)
3859 goto free_io_hndls;
3860 beiscsi_conn->plogin_wrb_handle =
3861 io_task->pwrb_handle;
3862
6733b39a
JK		 3863 } else {
3864 io_task->psgl_handle =
3865 beiscsi_conn->plogin_sgl_handle;
d2cecf0d
JK		 3866 io_task->pwrb_handle =
3867 beiscsi_conn->plogin_wrb_handle;
6733b39a
JK		 3868 }
3869 } else {
3870 spin_lock(&phba->mgmt_sgl_lock);
3871 io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
3872 spin_unlock(&phba->mgmt_sgl_lock);
2afc95bf
JK		 3873 if (!io_task->psgl_handle)
3874 goto free_hndls;
d2cecf0d
JK		 3875 io_task->pwrb_handle =
3876 alloc_wrb_handle(phba,
3877 beiscsi_conn->beiscsi_conn_cid -
3878 phba->fw_config.iscsi_cid_start);
3879 if (!io_task->pwrb_handle)
3880 goto free_mgmt_hndls;
3881
6733b39a
JK		 3882 }
3883 }
bfead3b2
JK		 3884 itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
3885 wrb_index << 16) | (unsigned int)
3886 (io_task->psgl_handle->sgl_index));
32951dd8 3887 io_task->pwrb_handle->pio_handle = task;
bfead3b2 3888
6733b39a
JK		 3889 io_task->cmd_bhs->iscsi_hdr.itt = itt;
3890 return 0;
2afc95bf 3891
d2cecf0d
JK		 3892free_io_hndls:
3893 spin_lock(&phba->io_sgl_lock);
3894 free_io_sgl_handle(phba, io_task->psgl_handle);
3895 spin_unlock(&phba->io_sgl_lock);
3896 goto free_hndls;
3897free_mgmt_hndls:
3898 spin_lock(&phba->mgmt_sgl_lock);
3899 free_mgmt_sgl_handle(phba, io_task->psgl_handle);
3900 spin_unlock(&phba->mgmt_sgl_lock);
2afc95bf
JK		 3901free_hndls:
3902 phwi_ctrlr = phba->phwi_ctrlr;
7da50879
JK		 3903 pwrb_context = &phwi_ctrlr->wrb_context[
3904 beiscsi_conn->beiscsi_conn_cid -
3905 phba->fw_config.iscsi_cid_start];
d2cecf0d
JK		 3906 if (io_task->pwrb_handle)
3907 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
2afc95bf
JK		 3908 io_task->pwrb_handle = NULL;
3909 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
3910 io_task->bhs_pa.u.a64.address);
457ff3b7 3911 SE_DEBUG(DBG_LVL_1, "Alloc of SGL_ICD Failed\n");
2afc95bf 3912 return -ENOMEM;
6733b39a
JK		 3913}
3914
3915static void beiscsi_cleanup_task(struct iscsi_task *task)
3916{
3917 struct beiscsi_io_task *io_task = task->dd_data;
3918 struct iscsi_conn *conn = task->conn;
3919 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
3920 struct beiscsi_hba *phba = beiscsi_conn->phba;
2afc95bf 3921 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
6733b39a
JK		 3922 struct hwi_wrb_context *pwrb_context;
3923 struct hwi_controller *phwi_ctrlr;
3924
3925 phwi_ctrlr = phba->phwi_ctrlr;
7da50879
JK		 3926 pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid
3927 - phba->fw_config.iscsi_cid_start];
6733b39a
JK		 3928 if (io_task->pwrb_handle) {
3929 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
3930 io_task->pwrb_handle = NULL;
3931 }
3932
2afc95bf
JK		 3933 if (io_task->cmd_bhs) {
3934 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
3935 io_task->bhs_pa.u.a64.address);
3936 }
3937
6733b39a
JK		 3938 if (task->sc) {
3939 if (io_task->psgl_handle) {
3940 spin_lock(&phba->io_sgl_lock);
3941 free_io_sgl_handle(phba, io_task->psgl_handle);
3942 spin_unlock(&phba->io_sgl_lock);
3943 io_task->psgl_handle = NULL;
3944 }
3945 } else {
1227633a
MC		 3946 if (task->hdr &&
3947 ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN))
6733b39a
JK		 3948 return;
3949 if (io_task->psgl_handle) {
3950 spin_lock(&phba->mgmt_sgl_lock);
3951 free_mgmt_sgl_handle(phba, io_task->psgl_handle);
3952 spin_unlock(&phba->mgmt_sgl_lock);
3953 io_task->psgl_handle = NULL;
3954 }
3955 }
3956}
3957
3958static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
3959 unsigned int num_sg, unsigned int xferlen,
3960 unsigned int writedir)
3961{
3962
3963 struct beiscsi_io_task *io_task = task->dd_data;
3964 struct iscsi_conn *conn = task->conn;
3965 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
3966 struct beiscsi_hba *phba = beiscsi_conn->phba;
3967 struct iscsi_wrb *pwrb = NULL;
3968 unsigned int doorbell = 0;
3969
3970 pwrb = io_task->pwrb_handle->pwrb;
6733b39a
JK		 3971 io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
3972 io_task->bhs_len = sizeof(struct be_cmd_bhs);
3973
3974 if (writedir) {
6733b39a
JK		 3975 memset(&io_task->cmd_bhs->iscsi_data_pdu, 0, 48);
3976 AMAP_SET_BITS(struct amap_pdu_data_out, itt,
3977 &io_task->cmd_bhs->iscsi_data_pdu,
3978 (unsigned int)io_task->cmd_bhs->iscsi_hdr.itt);
3979 AMAP_SET_BITS(struct amap_pdu_data_out, opcode,
3980 &io_task->cmd_bhs->iscsi_data_pdu,
3981 ISCSI_OPCODE_SCSI_DATA_OUT);
3982 AMAP_SET_BITS(struct amap_pdu_data_out, final_bit,
3983 &io_task->cmd_bhs->iscsi_data_pdu, 1);
32951dd8
JK		 3984 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
3985 INI_WR_CMD);
6733b39a 3986 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
6733b39a 3987 } else {
32951dd8
JK		 3988 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
3989 INI_RD_CMD);
6733b39a
JK		 3990 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
3991 }
3992 memcpy(&io_task->cmd_bhs->iscsi_data_pdu.
3993 dw[offsetof(struct amap_pdu_data_out, lun) / 32],
516f43a2 3994 &io_task->cmd_bhs->iscsi_hdr.lun, sizeof(struct scsi_lun));
6733b39a
JK		 3995
3996 AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
dc63aac6
JK		 3997 cpu_to_be16(*(unsigned short *)
3998 &io_task->cmd_bhs->iscsi_hdr.lun));
6733b39a
JK		 3999 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
4000 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
4001 io_task->pwrb_handle->wrb_index);
4002 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
4003 be32_to_cpu(task->cmdsn));
4004 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
4005 io_task->psgl_handle->sgl_index);
4006
4007 hwi_write_sgl(pwrb, sg, num_sg, io_task);
4008
4009 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
4010 io_task->pwrb_handle->nxt_wrb_index);
4011 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4012
4013 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 4014 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 4015 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
4016 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
4017
4018 iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
4019 return 0;
4020}
4021
4022static int beiscsi_mtask(struct iscsi_task *task)
4023{
dafab8e0 4024 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 4025 struct iscsi_conn *conn = task->conn;
4026 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4027 struct beiscsi_hba *phba = beiscsi_conn->phba;
4028 struct iscsi_wrb *pwrb = NULL;
4029 unsigned int doorbell = 0;
dafab8e0 4030 unsigned int cid;
6733b39a 4031
bfead3b2 4032 cid = beiscsi_conn->beiscsi_conn_cid;
6733b39a 4033 pwrb = io_task->pwrb_handle->pwrb;
caf818f1 4034 memset(pwrb, 0, sizeof(*pwrb));
6733b39a
JK		 4035 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
4036 be32_to_cpu(task->cmdsn));
4037 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
4038 io_task->pwrb_handle->wrb_index);
4039 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
4040 io_task->psgl_handle->sgl_index);
dafab8e0 4041
6733b39a
JK		 4042 switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
4043 case ISCSI_OP_LOGIN:
32951dd8
JK		 4044 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4045 TGT_DM_CMD);
6733b39a
JK		 4046 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
4047 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
4048 hwi_write_buffer(pwrb, task);
4049 break;
4050 case ISCSI_OP_NOOP_OUT:
1390b01b
JK		 4051 if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
4052 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4053 TGT_DM_CMD);
4054 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt,
4055 pwrb, 0);
685e16fd 4056 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 1);
1390b01b
JK		 4057 } else {
4058 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4059 INI_RD_CMD);
685e16fd 4060 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
1390b01b 4061 }
6733b39a
JK		 4062 hwi_write_buffer(pwrb, task);
4063 break;
4064 case ISCSI_OP_TEXT:
32951dd8 4065 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
b30c6dab 4066 TGT_DM_CMD);
0ecb0b45 4067 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
6733b39a
JK		 4068 hwi_write_buffer(pwrb, task);
4069 break;
4070 case ISCSI_OP_SCSI_TMFUNC:
32951dd8
JK		 4071 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4072 INI_TMF_CMD);
6733b39a
JK		 4073 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
4074 hwi_write_buffer(pwrb, task);
4075 break;
4076 case ISCSI_OP_LOGOUT:
4077 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
4078 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
dafab8e0 4079 HWH_TYPE_LOGOUT);
6733b39a
JK		 4080 hwi_write_buffer(pwrb, task);
4081 break;
4082
4083 default:
457ff3b7 4084 SE_DEBUG(DBG_LVL_1, "opcode =%d Not supported\n",
6733b39a
JK		 4085 task->hdr->opcode & ISCSI_OPCODE_MASK);
4086 return -EINVAL;
4087 }
4088
4089 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
51a46250 4090 task->data_count);
6733b39a
JK		 4091 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
4092 io_task->pwrb_handle->nxt_wrb_index);
4093 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4094
bfead3b2 4095 doorbell |= cid & DB_WRB_POST_CID_MASK;
32951dd8 4096 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 4097 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
4098 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
4099 iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
4100 return 0;
4101}
4102
4103static int beiscsi_task_xmit(struct iscsi_task *task)
4104{
6733b39a
JK		 4105 struct beiscsi_io_task *io_task = task->dd_data;
4106 struct scsi_cmnd *sc = task->sc;
6733b39a
JK		 4107 struct scatterlist *sg;
4108 int num_sg;
4109 unsigned int writedir = 0, xferlen = 0;
4110
6733b39a
JK		 4111 if (!sc)
4112 return beiscsi_mtask(task);
4113
4114 io_task->scsi_cmnd = sc;
4115 num_sg = scsi_dma_map(sc);
4116 if (num_sg < 0) {
4117 SE_DEBUG(DBG_LVL_1, " scsi_dma_map Failed\n")
4118 return num_sg;
4119 }
6733b39a
JK		 4120 xferlen = scsi_bufflen(sc);
4121 sg = scsi_sglist(sc);
4122 if (sc->sc_data_direction == DMA_TO_DEVICE) {
4123 writedir = 1;
457ff3b7 4124 SE_DEBUG(DBG_LVL_4, "task->imm_count=0x%08x\n",
6733b39a
JK		 4125 task->imm_count);
4126 } else
4127 writedir = 0;
4128 return beiscsi_iotask(task, sg, num_sg, xferlen, writedir);
4129}
4130
25602c97 4131static void beiscsi_quiesce(struct beiscsi_hba *phba)
6733b39a 4132{
bfead3b2
JK		 4133 struct hwi_controller *phwi_ctrlr;
4134 struct hwi_context_memory *phwi_context;
4135 struct be_eq_obj *pbe_eq;
4136 unsigned int i, msix_vec;
e9b91193
JK		 4137 u8 *real_offset = 0;
4138 u32 value = 0;
6733b39a 4139
bfead3b2
JK		 4140 phwi_ctrlr = phba->phwi_ctrlr;
4141 phwi_context = phwi_ctrlr->phwi_ctxt;
6733b39a 4142 hwi_disable_intr(phba);
bfead3b2
JK		 4143 if (phba->msix_enabled) {
4144 for (i = 0; i <= phba->num_cpus; i++) {
4145 msix_vec = phba->msix_entries[i].vector;
4146 free_irq(msix_vec, &phwi_context->be_eq[i]);
8fcfb210 4147 kfree(phba->msi_name[i]);
bfead3b2
JK		 4148 }
4149 } else
4150 if (phba->pcidev->irq)
4151 free_irq(phba->pcidev->irq, phba);
4152 pci_disable_msix(phba->pcidev);
6733b39a
JK		 4153 destroy_workqueue(phba->wq);
4154 if (blk_iopoll_enabled)
bfead3b2
JK		 4155 for (i = 0; i < phba->num_cpus; i++) {
4156 pbe_eq = &phwi_context->be_eq[i];
4157 blk_iopoll_disable(&pbe_eq->iopoll);
4158 }
6733b39a
JK		 4159
4160 beiscsi_clean_port(phba);
4161 beiscsi_free_mem(phba);
e9b91193
JK		 4162 real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
4163
4164 value = readl((void *)real_offset);
4165
4166 if (value & 0x00010000) {
4167 value &= 0xfffeffff;
4168 writel(value, (void *)real_offset);
4169 }
6733b39a
JK		 4170 beiscsi_unmap_pci_function(phba);
4171 pci_free_consistent(phba->pcidev,
4172 phba->ctrl.mbox_mem_alloced.size,
4173 phba->ctrl.mbox_mem_alloced.va,
4174 phba->ctrl.mbox_mem_alloced.dma);
25602c97
JK		 4175}
4176
4177static void beiscsi_remove(struct pci_dev *pcidev)
4178{
4179
4180 struct beiscsi_hba *phba = NULL;
4181
4182 phba = pci_get_drvdata(pcidev);
4183 if (!phba) {
4184 dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
4185 return;
4186 }
4187
4188 beiscsi_quiesce(phba);
9d045163 4189 iscsi_boot_destroy_kset(phba->boot_kset);
6733b39a
JK		 4190 iscsi_host_remove(phba->shost);
4191 pci_dev_put(phba->pcidev);
4192 iscsi_host_free(phba->shost);
8dce69ff 4193 pci_disable_device(pcidev);
6733b39a
JK		 4194}
4195
25602c97
JK		 4196static void beiscsi_shutdown(struct pci_dev *pcidev)
4197{
4198
4199 struct beiscsi_hba *phba = NULL;
4200
4201 phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
4202 if (!phba) {
4203 dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
4204 return;
4205 }
4206
4207 beiscsi_quiesce(phba);
8dce69ff 4208 pci_disable_device(pcidev);
25602c97
JK		 4209}
4210
bfead3b2
JK		 4211static void beiscsi_msix_enable(struct beiscsi_hba *phba)
4212{
4213 int i, status;
4214
4215 for (i = 0; i <= phba->num_cpus; i++)
4216 phba->msix_entries[i].entry = i;
4217
4218 status = pci_enable_msix(phba->pcidev, phba->msix_entries,
4219 (phba->num_cpus + 1));
4220 if (!status)
4221 phba->msix_enabled = true;
4222
4223 return;
4224}
4225
6733b39a
JK		 4226static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev,
4227 const struct pci_device_id *id)
4228{
4229 struct beiscsi_hba *phba = NULL;
bfead3b2
JK		 4230 struct hwi_controller *phwi_ctrlr;
4231 struct hwi_context_memory *phwi_context;
4232 struct be_eq_obj *pbe_eq;
238f6b72 4233 int ret, num_cpus, i;
e9b91193
JK		 4234 u8 *real_offset = 0;
4235 u32 value = 0;
6733b39a
JK		 4236
4237 ret = beiscsi_enable_pci(pcidev);
4238 if (ret < 0) {
82284c09
DC		 4239 dev_err(&pcidev->dev, "beiscsi_dev_probe-"
4240 " Failed to enable pci device\n");
6733b39a
JK		 4241 return ret;
4242 }
4243
4244 phba = beiscsi_hba_alloc(pcidev);
4245 if (!phba) {
4246 dev_err(&pcidev->dev, "beiscsi_dev_probe-"
457ff3b7 4247 " Failed in beiscsi_hba_alloc\n");
6733b39a
JK		 4248 goto disable_pci;
4249 }
4250
f98c96b0
JK		 4251 switch (pcidev->device) {
4252 case BE_DEVICE_ID1:
4253 case OC_DEVICE_ID1:
4254 case OC_DEVICE_ID2:
4255 phba->generation = BE_GEN2;
4256 break;
4257 case BE_DEVICE_ID2:
4258 case OC_DEVICE_ID3:
4259 phba->generation = BE_GEN3;
4260 break;
4261 default:
4262 phba->generation = 0;
4263 }
4264
bfead3b2
JK		 4265 if (enable_msix)
4266 num_cpus = find_num_cpus();
4267 else
4268 num_cpus = 1;
4269 phba->num_cpus = num_cpus;
457ff3b7 4270 SE_DEBUG(DBG_LVL_8, "num_cpus = %d\n", phba->num_cpus);
bfead3b2
JK		 4271
4272 if (enable_msix)
4273 beiscsi_msix_enable(phba);
6733b39a
JK		 4274 ret = be_ctrl_init(phba, pcidev);
4275 if (ret) {
4276 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
4277 "Failed in be_ctrl_init\n");
4278 goto hba_free;
4279 }
4280
e9b91193
JK		 4281 if (!num_hba) {
4282 real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
4283 value = readl((void *)real_offset);
4284 if (value & 0x00010000) {
4285 gcrashmode++;
4286 shost_printk(KERN_ERR, phba->shost,
4287 "Loading Driver in crashdump mode\n");
e5285860 4288 ret = beiscsi_cmd_reset_function(phba);
e9b91193
JK		 4289 if (ret) {
4290 shost_printk(KERN_ERR, phba->shost,
4291 "Reset Failed. Aborting Crashdump\n");
4292 goto hba_free;
4293 }
4294 ret = be_chk_reset_complete(phba);
4295 if (ret) {
4296 shost_printk(KERN_ERR, phba->shost,
4297 "Failed to get out of reset."
4298 "Aborting Crashdump\n");
4299 goto hba_free;
4300 }
4301 } else {
4302 value |= 0x00010000;
4303 writel(value, (void *)real_offset);
4304 num_hba++;
4305 }
4306 }
4307
6733b39a
JK		 4308 spin_lock_init(&phba->io_sgl_lock);
4309 spin_lock_init(&phba->mgmt_sgl_lock);
4310 spin_lock_init(&phba->isr_lock);
7da50879
JK		 4311 ret = mgmt_get_fw_config(&phba->ctrl, phba);
4312 if (ret != 0) {
4313 shost_printk(KERN_ERR, phba->shost,
4314 "Error getting fw config\n");
4315 goto free_port;
4316 }
4317 phba->shost->max_id = phba->fw_config.iscsi_cid_count;
6733b39a 4318 beiscsi_get_params(phba);
aa874f07 4319 phba->shost->can_queue = phba->params.ios_per_ctrl;
6733b39a
JK		 4320 ret = beiscsi_init_port(phba);
4321 if (ret < 0) {
4322 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
4323 "Failed in beiscsi_init_port\n");
4324 goto free_port;
4325 }
4326
756d29c8
JK		 4327 for (i = 0; i < MAX_MCC_CMD ; i++) {
4328 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
4329 phba->ctrl.mcc_tag[i] = i + 1;
4330 phba->ctrl.mcc_numtag[i + 1] = 0;
4331 phba->ctrl.mcc_tag_available++;
4332 }
4333
4334 phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
4335
6733b39a
JK		 4336 snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_q_irq%u",
4337 phba->shost->host_no);
278274d5 4338 phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1);
6733b39a
JK		 4339 if (!phba->wq) {
4340 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
4341 "Failed to allocate work queue\n");
4342 goto free_twq;
4343 }
4344
4345 INIT_WORK(&phba->work_cqs, beiscsi_process_all_cqs);
4346
bfead3b2
JK		 4347 phwi_ctrlr = phba->phwi_ctrlr;
4348 phwi_context = phwi_ctrlr->phwi_ctxt;
6733b39a 4349 if (blk_iopoll_enabled) {
bfead3b2
JK		 4350 for (i = 0; i < phba->num_cpus; i++) {
4351 pbe_eq = &phwi_context->be_eq[i];
4352 blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
4353 be_iopoll);
4354 blk_iopoll_enable(&pbe_eq->iopoll);
4355 }
6733b39a 4356 }
6733b39a
JK		 4357 ret = beiscsi_init_irqs(phba);
4358 if (ret < 0) {
4359 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
4360 "Failed to beiscsi_init_irqs\n");
4361 goto free_blkenbld;
4362 }
238f6b72 4363 hwi_enable_intr(phba);
f457a46f
MC		 4364
4365 if (beiscsi_setup_boot_info(phba))
4366 /*
4367 * log error but continue, because we may not be using
4368 * iscsi boot.
4369 */
4370 shost_printk(KERN_ERR, phba->shost, "Could not set up "
4371 "iSCSI boot info.");
4372
457ff3b7 4373 SE_DEBUG(DBG_LVL_8, "\n\n\n SUCCESS - DRIVER LOADED\n\n\n");
6733b39a
JK		 4374 return 0;
4375
6733b39a
JK		 4376free_blkenbld:
4377 destroy_workqueue(phba->wq);
4378 if (blk_iopoll_enabled)
bfead3b2
JK		 4379 for (i = 0; i < phba->num_cpus; i++) {
4380 pbe_eq = &phwi_context->be_eq[i];
4381 blk_iopoll_disable(&pbe_eq->iopoll);
4382 }
6733b39a
JK		 4383free_twq:
4384 beiscsi_clean_port(phba);
4385 beiscsi_free_mem(phba);
4386free_port:
e9b91193
JK		 4387 real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
4388
4389 value = readl((void *)real_offset);
4390
4391 if (value & 0x00010000) {
4392 value &= 0xfffeffff;
4393 writel(value, (void *)real_offset);
4394 }
4395
6733b39a
JK		 4396 pci_free_consistent(phba->pcidev,
4397 phba->ctrl.mbox_mem_alloced.size,
4398 phba->ctrl.mbox_mem_alloced.va,
4399 phba->ctrl.mbox_mem_alloced.dma);
4400 beiscsi_unmap_pci_function(phba);
4401hba_free:
238f6b72
JK		 4402 if (phba->msix_enabled)
4403 pci_disable_msix(phba->pcidev);
6733b39a
JK		 4404 iscsi_host_remove(phba->shost);
4405 pci_dev_put(phba->pcidev);
4406 iscsi_host_free(phba->shost);
4407disable_pci:
4408 pci_disable_device(pcidev);
4409 return ret;
4410}
4411
4412struct iscsi_transport beiscsi_iscsi_transport = {
4413 .owner = THIS_MODULE,
4414 .name = DRV_NAME,
9db0fb3a 4415 .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
6733b39a 4416 CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
6733b39a
JK		 4417 .create_session = beiscsi_session_create,
4418 .destroy_session = beiscsi_session_destroy,
4419 .create_conn = beiscsi_conn_create,
4420 .bind_conn = beiscsi_conn_bind,
4421 .destroy_conn = iscsi_conn_teardown,
3128c6c7 4422 .attr_is_visible = be2iscsi_attr_is_visible,
6733b39a 4423 .set_param = beiscsi_set_param,
c7f7fd5b 4424 .get_conn_param = iscsi_conn_get_param,
6733b39a
JK		 4425 .get_session_param = iscsi_session_get_param,
4426 .get_host_param = beiscsi_get_host_param,
4427 .start_conn = beiscsi_conn_start,
fa95d206 4428 .stop_conn = iscsi_conn_stop,
6733b39a
JK		 4429 .send_pdu = iscsi_conn_send_pdu,
4430 .xmit_task = beiscsi_task_xmit,
4431 .cleanup_task = beiscsi_cleanup_task,
4432 .alloc_pdu = beiscsi_alloc_pdu,
4433 .parse_pdu_itt = beiscsi_parse_pdu,
4434 .get_stats = beiscsi_conn_get_stats,
c7f7fd5b 4435 .get_ep_param = beiscsi_ep_get_param,
6733b39a
JK		 4436 .ep_connect = beiscsi_ep_connect,
4437 .ep_poll = beiscsi_ep_poll,
4438 .ep_disconnect = beiscsi_ep_disconnect,
4439 .session_recovery_timedout = iscsi_session_recovery_timedout,
4440};
4441
4442static struct pci_driver beiscsi_pci_driver = {
4443 .name = DRV_NAME,
4444 .probe = beiscsi_dev_probe,
4445 .remove = beiscsi_remove,
25602c97 4446 .shutdown = beiscsi_shutdown,
6733b39a
JK		 4447 .id_table = beiscsi_pci_id_table
4448};
4449
bfead3b2 4450
6733b39a
JK		 4451static int __init beiscsi_module_init(void)
4452{
4453 int ret;
4454
4455 beiscsi_scsi_transport =
4456 iscsi_register_transport(&beiscsi_iscsi_transport);
4457 if (!beiscsi_scsi_transport) {
4458 SE_DEBUG(DBG_LVL_1,
4459 "beiscsi_module_init - Unable to register beiscsi"
4460 "transport.\n");
f55a24f2 4461 return -ENOMEM;
6733b39a 4462 }
457ff3b7 4463 SE_DEBUG(DBG_LVL_8, "In beiscsi_module_init, tt=%p\n",
6733b39a
JK		 4464 &beiscsi_iscsi_transport);
4465
4466 ret = pci_register_driver(&beiscsi_pci_driver);
4467 if (ret) {
4468 SE_DEBUG(DBG_LVL_1,
4469 "beiscsi_module_init - Unable to register"
4470 "beiscsi pci driver.\n");
4471 goto unregister_iscsi_transport;
4472 }
4473 return 0;
4474
4475unregister_iscsi_transport:
4476 iscsi_unregister_transport(&beiscsi_iscsi_transport);
4477 return ret;
4478}
4479
4480static void __exit beiscsi_module_exit(void)
4481{
4482 pci_unregister_driver(&beiscsi_pci_driver);
4483 iscsi_unregister_transport(&beiscsi_iscsi_transport);
4484}
4485
4486module_init(beiscsi_module_init);
4487module_exit(beiscsi_module_exit);
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