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[SCSI] be2iscsi: Fix CID allocation/freeing to support Dual chute mode
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / be2iscsi / be_main.h
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6733b39a 1/**
533c165f 2 * Copyright (C) 2005 - 2013 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
255fa9a3 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
6733b39a
JK		 11 *
12 * Contact Information:
255fa9a3 13 * linux-drivers@emulex.com
6733b39a 14 *
255fa9a3
JK		 15 * Emulex
16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a
JK		 18 */
19
20#ifndef _BEISCSI_MAIN_
21#define _BEISCSI_MAIN_
22
6733b39a
JK		 23#include <linux/kernel.h>
24#include <linux/pci.h>
82c57028 25#include <linux/if_ether.h>
6733b39a 26#include <linux/in.h>
99bc5d55
JSJ		 27#include <linux/ctype.h>
28#include <linux/module.h>
6733b39a
JK		 29#include <scsi/scsi.h>
30#include <scsi/scsi_cmnd.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_host.h>
33#include <scsi/iscsi_proto.h>
34#include <scsi/libiscsi.h>
35#include <scsi/scsi_transport_iscsi.h>
36
6733b39a 37#define DRV_NAME "be2iscsi"
96e58ce0 38#define BUILD_STR "10.0.467.0"
2f635883
JK		 39#define BE_NAME "Emulex OneConnect" \
40 "Open-iSCSI Driver version" BUILD_STR
6733b39a
JK		 41#define DRV_DESC BE_NAME " " "Driver"
42
457ff3b7 43#define BE_VENDOR_ID 0x19A2
139a1b1e 44#define ELX_VENDOR_ID 0x10DF
f98c96b0 45/* DEVICE ID's for BE2 */
6733b39a
JK		 46#define BE_DEVICE_ID1 0x212
47#define OC_DEVICE_ID1 0x702
48#define OC_DEVICE_ID2 0x703
f98c96b0
JK		 49
50/* DEVICE ID's for BE3 */
51#define BE_DEVICE_ID2 0x222
bfead3b2 52#define OC_DEVICE_ID3 0x712
6733b39a 53
139a1b1e
JSJ		 54/* DEVICE ID for SKH */
55#define OC_SKH_ID1 0x722
56
7da50879
JK		 57#define BE2_IO_DEPTH 1024
58#define BE2_MAX_SESSIONS 256
6733b39a 59#define BE2_CMDS_PER_CXN 128
6733b39a
JK		 60#define BE2_TMFS 16
61#define BE2_NOPOUT_REQ 16
6733b39a
JK		 62#define BE2_SGE 32
63#define BE2_DEFPDU_HDR_SZ 64
64#define BE2_DEFPDU_DATA_SZ 8192
6733b39a 65
22abeef0
JSJ		 66#define MAX_CPUS 64
67#define BEISCSI_MAX_NUM_CPUS 7
bf9131cb 68#define OC_SKH_MAX_NUM_CPUS 31
22abeef0 69
22661e25 70#define BEISCSI_VER_STRLEN 32
22abeef0 71
aa359032 72#define BEISCSI_SGLIST_ELEMENTS 30
6733b39a 73
6733b39a 74#define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
e919dee8 75#define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */
15a90fe0 76#define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
6733b39a
JK		 77
78#define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
79#define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
80#define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
81#define BEISCSI_MAX_FRAGS_INIT 192
457ff3b7 82#define BE_NUM_MSIX_ENTRIES 1
e9b91193
JK		 83
84#define MPU_EP_CONTROL 0
85#define MPU_EP_SEMAPHORE 0xac
86#define BE2_SOFT_RESET 0x5c
87#define BE2_PCI_ONLINE0 0xb0
88#define BE2_PCI_ONLINE1 0xb4
89#define BE2_SET_RESET 0x80
90#define BE2_MPU_IRAM_ONLINE 0x00000080
6733b39a
JK		 91
92#define BE_SENSE_INFO_SIZE 258
93#define BE_ISCSI_PDU_HEADER_SIZE 64
94#define BE_MIN_MEM_SIZE 16384
bfead3b2 95#define MAX_CMD_SZ 65536
6733b39a
JK		 96#define IIOC_SCSI_DATA 0x05 /* Write Operation */
97
9aef4200 98#define INVALID_SESS_HANDLE 0xFFFFFFFF
6733b39a 99
bfead3b2
JK		 100#define BE_ADAPTER_UP 0x00000000
101#define BE_ADAPTER_LINK_DOWN 0x00000001
6733b39a
JK		 102/**
103 * hardware needs the async PDU buffers to be posted in multiples of 8
104 * So have atleast 8 of them by default
105 */
106
8a86e833
JK		 107#define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) \
108 (phwi->phwi_ctxt->pasync_ctx[ulp_num])
6733b39a
JK		 109
110/********* Memory BAR register ************/
457ff3b7 111#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
6733b39a
JK		 112/**
113 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
114 * Disable" may still globally block interrupts in addition to individual
115 * interrupt masks; a mechanism for the device driver to block all interrupts
116 * atomically without having to arbitrate for the PCI Interrupt Disable bit
117 * with the OS.
118 */
119#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
120
121/********* ISR0 Register offset **********/
457ff3b7 122#define CEV_ISR0_OFFSET 0xC18
6733b39a
JK		 123#define CEV_ISR_SIZE 4
124
125/**
126 * Macros for reading/writing a protection domain or CSR registers
127 * in BladeEngine.
128 */
129
130#define DB_TXULP0_OFFSET 0x40
131#define DB_RXULP0_OFFSET 0xA0
132/********* Event Q door bell *************/
133#define DB_EQ_OFFSET DB_CQ_OFFSET
134#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
135/* Clear the interrupt for this eq */
136#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
137/* Must be 1 */
138#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
139/* Number of event entries processed */
140#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
141/* Rearm bit */
142#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
143
144/********* Compl Q door bell *************/
457ff3b7 145#define DB_CQ_OFFSET 0x120
6733b39a
JK		 146#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
147/* Number of event entries processed */
457ff3b7 148#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
6733b39a 149/* Rearm bit */
457ff3b7 150#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
6733b39a
JK		 151
152#define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
8a86e833
JK		 153#define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
154 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
155#define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
156 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
6733b39a
JK		 157
158#define PAGES_REQUIRED(x) \
159 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
160
8fcfb210
JK		 161#define BEISCSI_MSI_NAME 20 /* size of msi_name string */
162
a129d92f 163#define MEM_DESCR_OFFSET 8
8a86e833
JK		 164#define BEISCSI_DEFQ_HDR 1
165#define BEISCSI_DEFQ_DATA 0
6733b39a
JK		 166enum be_mem_enum {
167 HWI_MEM_ADDN_CONTEXT,
6733b39a
JK		 168 HWI_MEM_WRB,
169 HWI_MEM_WRBH,
bfead3b2 170 HWI_MEM_SGLH,
6733b39a 171 HWI_MEM_SGE,
a129d92f
JK		 172 HWI_MEM_TEMPLATE_HDR_ULP0,
173 HWI_MEM_ASYNC_HEADER_BUF_ULP0, /* 6 */
8a86e833
JK		 174 HWI_MEM_ASYNC_DATA_BUF_ULP0,
175 HWI_MEM_ASYNC_HEADER_RING_ULP0,
176 HWI_MEM_ASYNC_DATA_RING_ULP0,
177 HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
a129d92f 178 HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
8a86e833 179 HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
a129d92f
JK		 180 HWI_MEM_TEMPLATE_HDR_ULP1,
181 HWI_MEM_ASYNC_HEADER_BUF_ULP1, /* 14 */
8a86e833
JK		 182 HWI_MEM_ASYNC_DATA_BUF_ULP1,
183 HWI_MEM_ASYNC_HEADER_RING_ULP1,
184 HWI_MEM_ASYNC_DATA_RING_ULP1,
185 HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
a129d92f 186 HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
8a86e833 187 HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
6733b39a 188 ISCSI_MEM_GLOBAL_HEADER,
bfead3b2 189 SE_MEM_MAX
6733b39a
JK		 190};
191
192struct be_bus_address32 {
193 unsigned int address_lo;
194 unsigned int address_hi;
195};
196
197struct be_bus_address64 {
198 unsigned long long address;
199};
200
201struct be_bus_address {
202 union {
203 struct be_bus_address32 a32;
204 struct be_bus_address64 a64;
205 } u;
206};
207
208struct mem_array {
209 struct be_bus_address bus_address; /* Bus address of location */
210 void *virtual_address; /* virtual address to the location */
211 unsigned int size; /* Size required by memory block */
212};
213
214struct be_mem_descriptor {
215 unsigned int index; /* Index of this memory parameter */
216 unsigned int category; /* type indicates cached/non-cached */
217 unsigned int num_elements; /* number of elements in this
218 * descriptor
219 */
220 unsigned int alignment_mask; /* Alignment mask for this block */
221 unsigned int size_in_bytes; /* Size required by memory block */
222 struct mem_array *mem_array;
223};
224
225struct sgl_handle {
226 unsigned int sgl_index;
bfead3b2
JK		 227 unsigned int type;
228 unsigned int cid;
229 struct iscsi_task *task;
6733b39a
JK		 230 struct iscsi_sge *pfrag;
231};
232
233struct hba_parameters {
234 unsigned int ios_per_ctrl;
235 unsigned int cxns_per_ctrl;
236 unsigned int asyncpdus_per_ctrl;
237 unsigned int icds_per_ctrl;
238 unsigned int num_sge_per_io;
239 unsigned int defpdu_hdr_sz;
240 unsigned int defpdu_data_sz;
241 unsigned int num_cq_entries;
242 unsigned int num_eq_entries;
243 unsigned int wrbs_per_cxn;
244 unsigned int crashmode;
245 unsigned int hba_num;
246
247 unsigned int mgmt_ws_sz;
248 unsigned int hwi_ws_sz;
249
250 unsigned int eto;
251 unsigned int ldto;
252
253 unsigned int dbg_flags;
254 unsigned int num_cxn;
255
256 unsigned int eq_timer;
257 /**
258 * These are calculated from other params. They're here
259 * for debug purposes
260 */
261 unsigned int num_mcc_pages;
262 unsigned int num_mcc_cq_pages;
263 unsigned int num_cq_pages;
264 unsigned int num_eq_pages;
265
266 unsigned int num_async_pdu_buf_pages;
267 unsigned int num_async_pdu_buf_sgl_pages;
268 unsigned int num_async_pdu_buf_cq_pages;
269
270 unsigned int num_async_pdu_hdr_pages;
271 unsigned int num_async_pdu_hdr_sgl_pages;
272 unsigned int num_async_pdu_hdr_cq_pages;
273
274 unsigned int num_sge;
275};
276
4183122d
JK		 277struct invalidate_command_table {
278 unsigned short icd;
279 unsigned short cid;
280} __packed;
281
4eea99d5
JK		 282#define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
283 (phwi_ctrlr->wrb_context[cri].ulp_num)
284struct hwi_wrb_context {
285 struct list_head wrb_handle_list;
286 struct list_head wrb_handle_drvr_list;
287 struct wrb_handle **pwrb_handle_base;
288 struct wrb_handle **pwrb_handle_basestd;
289 struct iscsi_wrb *plast_wrb;
290 unsigned short alloc_index;
291 unsigned short free_index;
292 unsigned short wrb_handles_available;
293 unsigned short cid;
294 uint8_t ulp_num; /* ULP to which CID binded */
295 uint16_t register_set;
296 uint16_t doorbell_format;
297 uint32_t doorbell_offset;
298};
299
0a3db7c0
JK		 300struct ulp_cid_info {
301 unsigned short *cid_array;
302 unsigned short avlbl_cids;
303 unsigned short cid_alloc;
304 unsigned short cid_free;
305};
306
4eea99d5 307#include "be.h"
2c9dfd36
JK		 308#define chip_be2(phba) (phba->generation == BE_GEN2)
309#define chip_be3_r(phba) (phba->generation == BE_GEN3)
310#define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
843ae752
JK		 311
312#define BEISCSI_ULP0 0
313#define BEISCSI_ULP1 1
314#define BEISCSI_ULP_COUNT 2
315#define BEISCSI_ULP0_LOADED 0x01
316#define BEISCSI_ULP1_LOADED 0x02
0a3db7c0
JK		 317
318#define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
319 (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
320#define BEISCSI_ULP0_AVLBL_CID(phba) \
321 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
322#define BEISCSI_ULP1_AVLBL_CID(phba) \
323 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
324
6733b39a
JK		 325struct beiscsi_hba {
326 struct hba_parameters params;
327 struct hwi_controller *phwi_ctrlr;
328 unsigned int mem_req[SE_MEM_MAX];
329 /* PCI BAR mapped addresses */
330 u8 __iomem *csr_va; /* CSR */
331 u8 __iomem *db_va; /* Door Bell */
332 u8 __iomem *pci_va; /* PCI Config */
333 struct be_bus_address csr_pa; /* CSR */
334 struct be_bus_address db_pa; /* CSR */
335 struct be_bus_address pci_pa; /* CSR */
336 /* PCI representation of our HBA */
337 struct pci_dev *pcidev;
6733b39a 338 unsigned short asic_revision;
bfead3b2
JK		 339 unsigned int num_cpus;
340 unsigned int nxt_cqid;
22abeef0
JSJ		 341 struct msix_entry msix_entries[MAX_CPUS];
342 char *msi_name[MAX_CPUS];
bfead3b2 343 bool msix_enabled;
6733b39a
JK		 344 struct be_mem_descriptor *init_mem;
345
346 unsigned short io_sgl_alloc_index;
347 unsigned short io_sgl_free_index;
348 unsigned short io_sgl_hndl_avbl;
349 struct sgl_handle **io_sgl_hndl_base;
bfead3b2 350 struct sgl_handle **sgl_hndl_array;
6733b39a
JK		 351
352 unsigned short eh_sgl_alloc_index;
353 unsigned short eh_sgl_free_index;
354 unsigned short eh_sgl_hndl_avbl;
355 struct sgl_handle **eh_sgl_hndl_base;
356 spinlock_t io_sgl_lock;
357 spinlock_t mgmt_sgl_lock;
358 spinlock_t isr_lock;
8f09a3b9 359 spinlock_t async_pdu_lock;
6733b39a 360 unsigned int age;
6733b39a 361 struct list_head hba_queue;
a7909b39
JK		 362#define BE_MAX_SESSION 2048
363#define BE_SET_CID_TO_CRI(cri_index, cid) \
364 (phba->cid_to_cri_map[cid] = cri_index)
365#define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
366 unsigned short cid_to_cri_map[BE_MAX_SESSION];
0a3db7c0 367 struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
6733b39a 368 struct iscsi_endpoint **ep_array;
a7909b39 369 struct beiscsi_conn **conn_table;
c7acc5b8 370 struct iscsi_boot_kset *boot_kset;
6733b39a 371 struct Scsi_Host *shost;
0e43895e
MC		 372 struct iscsi_iface *ipv4_iface;
373 struct iscsi_iface *ipv6_iface;
6733b39a
JK		 374 struct {
375 /**
376 * group together since they are used most frequently
377 * for cid to cri conversion
378 */
6733b39a 379 unsigned int phys_port;
843ae752
JK		 380 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
381#define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
8a86e833 382 (phba->fw_config.iscsi_cid_count[ulp_num])
843ae752
JK		 383 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
384 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
385 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
386 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
387 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
6733b39a 388
bfead3b2 389 unsigned short iscsi_features;
843ae752
JK		 390 uint16_t dual_ulp_aware;
391 unsigned long ulp_supported;
6733b39a
JK		 392 } fw_config;
393
e175defe
JSJ		 394 unsigned int state;
395 bool fw_timeout;
396 bool ue_detected;
397 struct delayed_work beiscsi_hw_check_task;
398
6c83185a 399 bool mac_addr_set;
6733b39a 400 u8 mac_address[ETH_ALEN];
22661e25 401 char fw_ver_str[BEISCSI_VER_STRLEN];
6733b39a
JK		 402 char wq_name[20];
403 struct workqueue_struct *wq; /* The actuak work queue */
6733b39a 404 struct be_ctrl_info ctrl;
f98c96b0 405 unsigned int generation;
0e43895e 406 unsigned int interface_handle;
c7acc5b8 407 struct mgmt_session_info boot_sess;
4183122d
JK		 408 struct invalidate_command_table inv_tbl[128];
409
99bc5d55 410 unsigned int attr_log_enable;
09a1093a
JSJ		 411 int (*iotask_fn)(struct iscsi_task *,
412 struct scatterlist *sg,
413 uint32_t num_sg, uint32_t xferlen,
414 uint32_t writedir);
6733b39a
JK		 415};
416
b8b9e1b8
JK		 417struct beiscsi_session {
418 struct pci_pool *bhs_pool;
419};
420
6733b39a
JK		 421/**
422 * struct beiscsi_conn - iscsi connection structure
423 */
424struct beiscsi_conn {
425 struct iscsi_conn *conn;
426 struct beiscsi_hba *phba;
427 u32 exp_statsn;
428 u32 beiscsi_conn_cid;
429 struct beiscsi_endpoint *ep;
430 unsigned short login_in_progress;
d2cecf0d 431 struct wrb_handle *plogin_wrb_handle;
6733b39a 432 struct sgl_handle *plogin_sgl_handle;
b8b9e1b8 433 struct beiscsi_session *beiscsi_sess;
bfead3b2 434 struct iscsi_task *task;
6733b39a
JK		 435};
436
437/* This structure is used by the chip */
438struct pdu_data_out {
439 u32 dw[12];
440};
441/**
442 * Pseudo amap definition in which each bit of the actual structure is defined
443 * as a byte: used to calculate offset/shift/mask of each field
444 */
445struct amap_pdu_data_out {
446 u8 opcode[6]; /* opcode */
447 u8 rsvd0[2]; /* should be 0 */
448 u8 rsvd1[7];
449 u8 final_bit; /* F bit */
450 u8 rsvd2[16];
451 u8 ahs_length[8]; /* no AHS */
452 u8 data_len_hi[8];
453 u8 data_len_lo[16]; /* DataSegmentLength */
454 u8 lun[64];
455 u8 itt[32]; /* ITT; initiator task tag */
456 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
457 u8 rsvd3[32];
458 u8 exp_stat_sn[32];
459 u8 rsvd4[32];
460 u8 data_sn[32];
461 u8 buffer_offset[32];
462 u8 rsvd5[32];
463};
464
465struct be_cmd_bhs {
12352183 466 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 467 unsigned char pad1[16];
468 struct pdu_data_out iscsi_data_pdu;
469 unsigned char pad2[BE_SENSE_INFO_SIZE -
470 sizeof(struct pdu_data_out)];
471};
472
473struct beiscsi_io_task {
474 struct wrb_handle *pwrb_handle;
475 struct sgl_handle *psgl_handle;
476 struct beiscsi_conn *conn;
477 struct scsi_cmnd *scsi_cmnd;
478 unsigned int cmd_sn;
479 unsigned int flags;
480 unsigned short cid;
481 unsigned short header_len;
bfead3b2 482 itt_t libiscsi_itt;
6733b39a
JK		 483 struct be_cmd_bhs *cmd_bhs;
484 struct be_bus_address bhs_pa;
485 unsigned short bhs_len;
d629c471
JSJ		 486 dma_addr_t mtask_addr;
487 uint32_t mtask_data_count;
09a1093a 488 uint8_t wrb_type;
6733b39a
JK		 489};
490
491struct be_nonio_bhs {
492 struct iscsi_hdr iscsi_hdr;
493 unsigned char pad1[16];
494 struct pdu_data_out iscsi_data_pdu;
495 unsigned char pad2[BE_SENSE_INFO_SIZE -
496 sizeof(struct pdu_data_out)];
497};
498
499struct be_status_bhs {
12352183 500 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 501 unsigned char pad1[16];
502 /**
503 * The plus 2 below is to hold the sense info length that gets
504 * DMA'ed by RxULP
505 */
506 unsigned char sense_info[BE_SENSE_INFO_SIZE];
507};
508
509struct iscsi_sge {
510 u32 dw[4];
511};
512
513/**
514 * Pseudo amap definition in which each bit of the actual structure is defined
515 * as a byte: used to calculate offset/shift/mask of each field
516 */
517struct amap_iscsi_sge {
518 u8 addr_hi[32];
519 u8 addr_lo[32];
520 u8 sge_offset[22]; /* DWORD 2 */
521 u8 rsvd0[9]; /* DWORD 2 */
522 u8 last_sge; /* DWORD 2 */
523 u8 len[17]; /* DWORD 3 */
524 u8 rsvd1[15]; /* DWORD 3 */
525};
526
527struct beiscsi_offload_params {
7331613e 528 u32 dw[6];
6733b39a
JK		 529};
530
531#define OFFLD_PARAMS_ERL 0x00000003
532#define OFFLD_PARAMS_DDE 0x00000004
533#define OFFLD_PARAMS_HDE 0x00000008
534#define OFFLD_PARAMS_IR2T 0x00000010
535#define OFFLD_PARAMS_IMD 0x00000020
acb9693c
JSJ		 536#define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040
537#define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080
538#define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
6733b39a
JK		 539
540/**
541 * Pseudo amap definition in which each bit of the actual structure is defined
542 * as a byte: used to calculate offset/shift/mask of each field
543 */
544struct amap_beiscsi_offload_params {
545 u8 max_burst_length[32];
546 u8 max_send_data_segment_length[32];
547 u8 first_burst_length[32];
548 u8 erl[2];
549 u8 dde[1];
550 u8 hde[1];
551 u8 ir2t[1];
552 u8 imd[1];
acb9693c
JSJ		 553 u8 data_seq_inorder[1];
554 u8 pdu_seq_inorder[1];
555 u8 max_r2t[16];
556 u8 pad[8];
6733b39a 557 u8 exp_statsn[32];
7331613e 558 u8 max_recv_data_segment_length[32];
6733b39a
JK		 559};
560
561/* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
562 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
563
564struct async_pdu_handle {
565 struct list_head link;
566 struct be_bus_address pa;
567 void *pbuffer;
568 unsigned int consumed;
569 unsigned char index;
570 unsigned char is_header;
571 unsigned short cri;
572 unsigned long buffer_len;
573};
574
575struct hwi_async_entry {
576 struct {
577 unsigned char hdr_received;
578 unsigned char hdr_len;
579 unsigned short bytes_received;
580 unsigned int bytes_needed;
581 struct list_head list;
582 } wait_queue;
583
584 struct list_head header_busy_list;
585 struct list_head data_busy_list;
586};
587
6733b39a
JK		 588struct hwi_async_pdu_context {
589 struct {
590 struct be_bus_address pa_base;
591 void *va_base;
592 void *ring_base;
593 struct async_pdu_handle *handle_base;
594
595 unsigned int host_write_ptr;
596 unsigned int ep_read_ptr;
597 unsigned int writables;
598
599 unsigned int free_entries;
600 unsigned int busy_entries;
6733b39a
JK		 601
602 struct list_head free_list;
603 } async_header;
604
605 struct {
606 struct be_bus_address pa_base;
607 void *va_base;
608 void *ring_base;
609 struct async_pdu_handle *handle_base;
610
611 unsigned int host_write_ptr;
612 unsigned int ep_read_ptr;
613 unsigned int writables;
614
615 unsigned int free_entries;
616 unsigned int busy_entries;
6733b39a 617 struct list_head free_list;
6733b39a
JK		 618 } async_data;
619
dc63aac6
JK		 620 unsigned int buffer_size;
621 unsigned int num_entries;
8a86e833
JK		 622#define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
623 unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
6733b39a
JK		 624 /**
625 * This is a varying size list! Do not add anything
626 * after this entry!!
627 */
a7909b39 628 struct hwi_async_entry *async_entry;
6733b39a
JK		 629};
630
631#define PDUCQE_CODE_MASK 0x0000003F
632#define PDUCQE_DPL_MASK 0xFFFF0000
633#define PDUCQE_INDEX_MASK 0x0000FFFF
634
635struct i_t_dpdu_cqe {
636 u32 dw[4];
637} __packed;
638
639/**
640 * Pseudo amap definition in which each bit of the actual structure is defined
641 * as a byte: used to calculate offset/shift/mask of each field
642 */
643struct amap_i_t_dpdu_cqe {
644 u8 db_addr_hi[32];
645 u8 db_addr_lo[32];
646 u8 code[6];
647 u8 cid[10];
648 u8 dpl[16];
649 u8 index[16];
650 u8 num_cons[10];
651 u8 rsvd0[4];
652 u8 final;
653 u8 valid;
654} __packed;
655
73133261
JSJ		 656struct amap_i_t_dpdu_cqe_v2 {
657 u8 db_addr_hi[32]; /* DWORD 0 */
658 u8 db_addr_lo[32]; /* DWORD 1 */
659 u8 code[6]; /* DWORD 2 */
660 u8 num_cons; /* DWORD 2*/
661 u8 rsvd0[8]; /* DWORD 2 */
662 u8 dpl[17]; /* DWORD 2 */
663 u8 index[16]; /* DWORD 3 */
664 u8 cid[13]; /* DWORD 3 */
665 u8 rsvd1; /* DWORD 3 */
666 u8 final; /* DWORD 3 */
667 u8 valid; /* DWORD 3 */
668} __packed;
669
6733b39a
JK		 670#define CQE_VALID_MASK 0x80000000
671#define CQE_CODE_MASK 0x0000003F
672#define CQE_CID_MASK 0x0000FFC0
673
674#define EQE_VALID_MASK 0x00000001
675#define EQE_MAJORCODE_MASK 0x0000000E
676#define EQE_RESID_MASK 0xFFFF0000
677
678struct be_eq_entry {
679 u32 dw[1];
680} __packed;
681
682/**
683 * Pseudo amap definition in which each bit of the actual structure is defined
684 * as a byte: used to calculate offset/shift/mask of each field
685 */
686struct amap_eq_entry {
687 u8 valid; /* DWORD 0 */
688 u8 major_code[3]; /* DWORD 0 */
689 u8 minor_code[12]; /* DWORD 0 */
690 u8 resource_id[16]; /* DWORD 0 */
691
692} __packed;
693
694struct cq_db {
695 u32 dw[1];
696} __packed;
697
698/**
699 * Pseudo amap definition in which each bit of the actual structure is defined
700 * as a byte: used to calculate offset/shift/mask of each field
701 */
702struct amap_cq_db {
703 u8 qid[10];
704 u8 event[1];
705 u8 rsvd0[5];
706 u8 num_popped[13];
707 u8 rearm[1];
708 u8 rsvd1[2];
709} __packed;
710
711void beiscsi_process_eq(struct beiscsi_hba *phba);
712
6733b39a
JK		 713struct iscsi_wrb {
714 u32 dw[16];
715} __packed;
716
717#define WRB_TYPE_MASK 0xF0000000
09a1093a
JSJ		 718#define SKH_WRB_TYPE_OFFSET 27
719#define BE_WRB_TYPE_OFFSET 28
720
721#define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
722 (pwrb->dw[0] |= (wrb_type << type_offset))
6733b39a
JK		 723
724/**
725 * Pseudo amap definition in which each bit of the actual structure is defined
726 * as a byte: used to calculate offset/shift/mask of each field
727 */
728struct amap_iscsi_wrb {
729 u8 lun[14]; /* DWORD 0 */
730 u8 lt; /* DWORD 0 */
731 u8 invld; /* DWORD 0 */
732 u8 wrb_idx[8]; /* DWORD 0 */
733 u8 dsp; /* DWORD 0 */
734 u8 dmsg; /* DWORD 0 */
735 u8 undr_run; /* DWORD 0 */
736 u8 over_run; /* DWORD 0 */
737 u8 type[4]; /* DWORD 0 */
738 u8 ptr2nextwrb[8]; /* DWORD 1 */
739 u8 r2t_exp_dtl[24]; /* DWORD 1 */
740 u8 sgl_icd_idx[12]; /* DWORD 2 */
741 u8 rsvd0[20]; /* DWORD 2 */
742 u8 exp_data_sn[32]; /* DWORD 3 */
743 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
744 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
745 u8 cmdsn_itt[32]; /* DWORD 6 */
746 u8 dif_ref_tag[32]; /* DWORD 7 */
747 u8 sge0_addr_hi[32]; /* DWORD 8 */
748 u8 sge0_addr_lo[32]; /* DWORD 9 */
749 u8 sge0_offset[22]; /* DWORD 10 */
750 u8 pbs; /* DWORD 10 */
751 u8 dif_mode[2]; /* DWORD 10 */
752 u8 rsvd1[6]; /* DWORD 10 */
753 u8 sge0_last; /* DWORD 10 */
754 u8 sge0_len[17]; /* DWORD 11 */
755 u8 dif_meta_tag[14]; /* DWORD 11 */
756 u8 sge0_in_ddr; /* DWORD 11 */
757 u8 sge1_addr_hi[32]; /* DWORD 12 */
758 u8 sge1_addr_lo[32]; /* DWORD 13 */
759 u8 sge1_r2t_offset[22]; /* DWORD 14 */
760 u8 rsvd2[9]; /* DWORD 14 */
761 u8 sge1_last; /* DWORD 14 */
762 u8 sge1_len[17]; /* DWORD 15 */
763 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
764 u8 rsvd3[2]; /* DWORD 15 */
765 u8 sge1_in_ddr; /* DWORD 15 */
766
767} __packed;
768
09a1093a
JSJ		 769struct amap_iscsi_wrb_v2 {
770 u8 r2t_exp_dtl[25]; /* DWORD 0 */
771 u8 rsvd0[2]; /* DWORD 0*/
772 u8 type[5]; /* DWORD 0 */
773 u8 ptr2nextwrb[8]; /* DWORD 1 */
774 u8 wrb_idx[8]; /* DWORD 1 */
775 u8 lun[16]; /* DWORD 1 */
776 u8 sgl_idx[16]; /* DWORD 2 */
777 u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
778 u8 exp_data_sn[32]; /* DWORD 3 */
779 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
780 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
781 u8 cq_id[16]; /* DWORD 6 */
782 u8 rsvd1[16]; /* DWORD 6 */
783 u8 cmdsn_itt[32]; /* DWORD 7 */
784 u8 sge0_addr_hi[32]; /* DWORD 8 */
785 u8 sge0_addr_lo[32]; /* DWORD 9 */
786 u8 sge0_offset[24]; /* DWORD 10 */
787 u8 rsvd2[7]; /* DWORD 10 */
788 u8 sge0_last; /* DWORD 10 */
789 u8 sge0_len[17]; /* DWORD 11 */
790 u8 rsvd3[7]; /* DWORD 11 */
791 u8 diff_enbl; /* DWORD 11 */
792 u8 u_run; /* DWORD 11 */
793 u8 o_run; /* DWORD 11 */
794 u8 invalid; /* DWORD 11 */
795 u8 dsp; /* DWORD 11 */
796 u8 dmsg; /* DWORD 11 */
797 u8 rsvd4; /* DWORD 11 */
798 u8 lt; /* DWORD 11 */
799 u8 sge1_addr_hi[32]; /* DWORD 12 */
800 u8 sge1_addr_lo[32]; /* DWORD 13 */
801 u8 sge1_r2t_offset[24]; /* DWORD 14 */
802 u8 rsvd5[7]; /* DWORD 14 */
803 u8 sge1_last; /* DWORD 14 */
804 u8 sge1_len[17]; /* DWORD 15 */
805 u8 rsvd6[15]; /* DWORD 15 */
806} __packed;
807
808
d5431488 809struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
6733b39a
JK		 810void
811free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
812
756d29c8 813void beiscsi_process_all_cqs(struct work_struct *work);
4a4a11b9
JK		 814void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
815 struct iscsi_task *task);
756d29c8 816
7a158003
JSJ		 817static inline bool beiscsi_error(struct beiscsi_hba *phba)
818{
819 return phba->ue_detected || phba->fw_timeout;
820}
821
6733b39a
JK		 822struct pdu_nop_out {
823 u32 dw[12];
824};
825
826/**
827 * Pseudo amap definition in which each bit of the actual structure is defined
828 * as a byte: used to calculate offset/shift/mask of each field
829 */
830struct amap_pdu_nop_out {
831 u8 opcode[6]; /* opcode 0x00 */
832 u8 i_bit; /* I Bit */
833 u8 x_bit; /* reserved; should be 0 */
834 u8 fp_bit_filler1[7];
835 u8 f_bit; /* always 1 */
836 u8 reserved1[16];
837 u8 ahs_length[8]; /* no AHS */
838 u8 data_len_hi[8];
839 u8 data_len_lo[16]; /* DataSegmentLength */
840 u8 lun[64];
841 u8 itt[32]; /* initiator id for ping or 0xffffffff */
842 u8 ttt[32]; /* target id for ping or 0xffffffff */
843 u8 cmd_sn[32];
844 u8 exp_stat_sn[32];
845 u8 reserved5[128];
846};
847
848#define PDUBASE_OPCODE_MASK 0x0000003F
849#define PDUBASE_DATALENHI_MASK 0x0000FF00
850#define PDUBASE_DATALENLO_MASK 0xFFFF0000
851
852struct pdu_base {
853 u32 dw[16];
854} __packed;
855
856/**
857 * Pseudo amap definition in which each bit of the actual structure is defined
858 * as a byte: used to calculate offset/shift/mask of each field
859 */
860struct amap_pdu_base {
861 u8 opcode[6];
862 u8 i_bit; /* immediate bit */
863 u8 x_bit; /* reserved, always 0 */
864 u8 reserved1[24]; /* opcode-specific fields */
865 u8 ahs_length[8]; /* length units is 4 byte words */
866 u8 data_len_hi[8];
867 u8 data_len_lo[16]; /* DatasegmentLength */
868 u8 lun[64]; /* lun or opcode-specific fields */
869 u8 itt[32]; /* initiator task tag */
870 u8 reserved4[224];
871};
872
873struct iscsi_target_context_update_wrb {
874 u32 dw[16];
875} __packed;
876
877/**
878 * Pseudo amap definition in which each bit of the actual structure is defined
879 * as a byte: used to calculate offset/shift/mask of each field
880 */
acb9693c 881#define BE_TGT_CTX_UPDT_CMD 0x07
6733b39a
JK		 882struct amap_iscsi_target_context_update_wrb {
883 u8 lun[14]; /* DWORD 0 */
884 u8 lt; /* DWORD 0 */
885 u8 invld; /* DWORD 0 */
886 u8 wrb_idx[8]; /* DWORD 0 */
887 u8 dsp; /* DWORD 0 */
888 u8 dmsg; /* DWORD 0 */
889 u8 undr_run; /* DWORD 0 */
890 u8 over_run; /* DWORD 0 */
891 u8 type[4]; /* DWORD 0 */
892 u8 ptr2nextwrb[8]; /* DWORD 1 */
893 u8 max_burst_length[19]; /* DWORD 1 */
894 u8 rsvd0[5]; /* DWORD 1 */
895 u8 rsvd1[15]; /* DWORD 2 */
896 u8 max_send_data_segment_length[17]; /* DWORD 2 */
897 u8 first_burst_length[14]; /* DWORD 3 */
898 u8 rsvd2[2]; /* DWORD 3 */
899 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
900 u8 rsvd3[5]; /* DWORD 3 */
901 u8 session_state[3]; /* DWORD 3 */
902 u8 rsvd4[16]; /* DWORD 4 */
903 u8 tx_jumbo; /* DWORD 4 */
904 u8 hde; /* DWORD 4 */
905 u8 dde; /* DWORD 4 */
906 u8 erl[2]; /* DWORD 4 */
907 u8 domain_id[5]; /* DWORD 4 */
908 u8 mode; /* DWORD 4 */
909 u8 imd; /* DWORD 4 */
910 u8 ir2t; /* DWORD 4 */
911 u8 notpredblq[2]; /* DWORD 4 */
912 u8 compltonack; /* DWORD 4 */
913 u8 stat_sn[32]; /* DWORD 5 */
914 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
915 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
916 u8 pad_addr_hi[32]; /* DWORD 8 */
917 u8 pad_addr_lo[32]; /* DWORD 9 */
918 u8 rsvd5[32]; /* DWORD 10 */
919 u8 rsvd6[32]; /* DWORD 11 */
920 u8 rsvd7[32]; /* DWORD 12 */
921 u8 rsvd8[32]; /* DWORD 13 */
922 u8 rsvd9[32]; /* DWORD 14 */
923 u8 rsvd10[32]; /* DWORD 15 */
924
925} __packed;
926
acb9693c
JSJ		 927#define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024)
928#define BEISCSI_MAX_CXNS 1
929struct amap_iscsi_target_context_update_wrb_v2 {
930 u8 max_burst_length[24]; /* DWORD 0 */
931 u8 rsvd0[3]; /* DWORD 0 */
932 u8 type[5]; /* DWORD 0 */
933 u8 ptr2nextwrb[8]; /* DWORD 1 */
934 u8 wrb_idx[8]; /* DWORD 1 */
935 u8 rsvd1[16]; /* DWORD 1 */
936 u8 max_send_data_segment_length[24]; /* DWORD 2 */
937 u8 rsvd2[8]; /* DWORD 2 */
938 u8 first_burst_length[24]; /* DWORD 3 */
939 u8 rsvd3[8]; /* DOWRD 3 */
940 u8 max_r2t[16]; /* DWORD 4 */
7331613e 941 u8 rsvd4; /* DWORD 4 */
acb9693c
JSJ		 942 u8 hde; /* DWORD 4 */
943 u8 dde; /* DWORD 4 */
944 u8 erl[2]; /* DWORD 4 */
7331613e 945 u8 rsvd5[6]; /* DWORD 4 */
acb9693c
JSJ		 946 u8 imd; /* DWORD 4 */
947 u8 ir2t; /* DWORD 4 */
7331613e 948 u8 rsvd6[3]; /* DWORD 4 */
acb9693c 949 u8 stat_sn[32]; /* DWORD 5 */
7331613e
JK		 950 u8 rsvd7[32]; /* DWORD 6 */
951 u8 rsvd8[32]; /* DWORD 7 */
acb9693c 952 u8 max_recv_dataseg_len[24]; /* DWORD 8 */
7331613e
JK		 953 u8 rsvd9[8]; /* DWORD 8 */
954 u8 rsvd10[32]; /* DWORD 9 */
955 u8 rsvd11[32]; /* DWORD 10 */
acb9693c 956 u8 max_cxns[16]; /* DWORD 11 */
7331613e 957 u8 rsvd12[11]; /* DWORD 11*/
acb9693c 958 u8 invld; /* DWORD 11 */
7331613e 959 u8 rsvd13;/* DWORD 11*/
acb9693c
JSJ		 960 u8 dmsg; /* DWORD 11 */
961 u8 data_seq_inorder; /* DWORD 11 */
962 u8 pdu_seq_inorder; /* DWORD 11 */
7331613e
JK		 963 u8 rsvd14[32]; /*DWORD 12 */
964 u8 rsvd15[32]; /* DWORD 13 */
965 u8 rsvd16[32]; /* DWORD 14 */
966 u8 rsvd17[32]; /* DWORD 15 */
acb9693c
JSJ		 967} __packed;
968
969
6733b39a
JK		 970struct be_ring {
971 u32 pages; /* queue size in pages */
972 u32 id; /* queue id assigned by beklib */
973 u32 num; /* number of elements in queue */
974 u32 cidx; /* consumer index */
975 u32 pidx; /* producer index -- not used by most rings */
976 u32 item_size; /* size in bytes of one object */
8a86e833
JK		 977 u8 ulp_num; /* ULP to which CID binded */
978 u16 register_set;
979 u16 doorbell_format;
980 u32 doorbell_offset;
6733b39a
JK		 981
982 void *va; /* The virtual address of the ring. This
983 * should be last to allow 32 & 64 bit debugger
984 * extensions to work.
985 */
986};
987
6733b39a
JK		 988struct hwi_controller {
989 struct list_head io_sgl_list;
990 struct list_head eh_sgl_list;
991 struct sgl_handle *psgl_handle_base;
992 unsigned int wrb_mem_index;
993
a7909b39 994 struct hwi_wrb_context *wrb_context;
6733b39a 995 struct mcc_wrb *pmcc_wrb_base;
8a86e833
JK		 996 struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
997 struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
6733b39a 998 struct hwi_context_memory *phwi_ctxt;
6733b39a
JK		 999};
1000
1001enum hwh_type_enum {
1002 HWH_TYPE_IO = 1,
1003 HWH_TYPE_LOGOUT = 2,
1004 HWH_TYPE_TMF = 3,
1005 HWH_TYPE_NOP = 4,
1006 HWH_TYPE_IO_RD = 5,
1007 HWH_TYPE_LOGIN = 11,
1008 HWH_TYPE_INVALID = 0xFFFFFFFF
1009};
1010
1011struct wrb_handle {
1012 enum hwh_type_enum type;
1013 unsigned short wrb_index;
1014 unsigned short nxt_wrb_index;
1015
1016 struct iscsi_task *pio_handle;
1017 struct iscsi_wrb *pwrb;
1018};
1019
1020struct hwi_context_memory {
bfead3b2
JK		 1021 /* Adaptive interrupt coalescing (AIC) info */
1022 u16 min_eqd; /* in usecs */
1023 u16 max_eqd; /* in usecs */
1024 u16 cur_eqd; /* in usecs */
1025 struct be_eq_obj be_eq[MAX_CPUS];
22abeef0 1026 struct be_queue_info be_cq[MAX_CPUS - 1];
6733b39a 1027
a7909b39 1028 struct be_queue_info *be_wrbq;
8a86e833
JK		 1029 struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1030 struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1031 struct hwi_async_pdu_context *pasync_ctx[BEISCSI_ULP_COUNT];
6733b39a
JK		 1032};
1033
99bc5d55
JSJ		 1034/* Logging related definitions */
1035#define BEISCSI_LOG_INIT 0x0001 /* Initialization events */
1036#define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */
1037#define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */
1038#define BEISCSI_LOG_EH 0x0008 /* Error Handler */
1039#define BEISCSI_LOG_IO 0x0010 /* IO Code Path */
1040#define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */
1041
1042#define beiscsi_log(phba, level, mask, fmt, arg...) \
1043do { \
1044 uint32_t log_value = phba->attr_log_enable; \
1045 if (((mask) & log_value) || (level[1] <= '3')) \
1046 shost_printk(level, phba->shost, \
1047 fmt, __LINE__, ##arg); \
1048} while (0)
1049
6733b39a 1050#endif
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