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[SCSI] libiscsi: Make iscsi_eh_target_reset start with session reset
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / be2iscsi / be_main.h
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6733b39a 1/**
d2eeb1ac 2 * Copyright (C) 2005 - 2010 ServerEngines
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Written by: Jayamohan Kallickal (jayamohank@serverengines.com)
11 *
12 * Contact Information:
13 * linux-drivers@serverengines.com
14 *
15 * ServerEngines
16 * 209 N. Fair Oaks Ave
17 * Sunnyvale, CA 94085
18 *
19 */
20
21#ifndef _BEISCSI_MAIN_
22#define _BEISCSI_MAIN_
23
6733b39a
JK		 24#include <linux/kernel.h>
25#include <linux/pci.h>
26#include <linux/in.h>
6733b39a
JK		 27#include <scsi/scsi.h>
28#include <scsi/scsi_cmnd.h>
29#include <scsi/scsi_device.h>
30#include <scsi/scsi_host.h>
31#include <scsi/iscsi_proto.h>
32#include <scsi/libiscsi.h>
33#include <scsi/scsi_transport_iscsi.h>
34
35#include "be.h"
6733b39a
JK		 36#define DRV_NAME "be2iscsi"
37#define BUILD_STR "2.0.527.0"
6733b39a
JK		 38#define BE_NAME "ServerEngines BladeEngine2" \
39 "Linux iSCSI Driver version" BUILD_STR
40#define DRV_DESC BE_NAME " " "Driver"
41
42#define BE_VENDOR_ID 0x19A2
f98c96b0 43/* DEVICE ID's for BE2 */
6733b39a
JK		 44#define BE_DEVICE_ID1 0x212
45#define OC_DEVICE_ID1 0x702
46#define OC_DEVICE_ID2 0x703
f98c96b0
JK		 47
48/* DEVICE ID's for BE3 */
49#define BE_DEVICE_ID2 0x222
bfead3b2 50#define OC_DEVICE_ID3 0x712
6733b39a 51
7da50879
JK		 52#define BE2_IO_DEPTH 1024
53#define BE2_MAX_SESSIONS 256
6733b39a 54#define BE2_CMDS_PER_CXN 128
6733b39a
JK		 55#define BE2_TMFS 16
56#define BE2_NOPOUT_REQ 16
6733b39a
JK		 57#define BE2_SGE 32
58#define BE2_DEFPDU_HDR_SZ 64
59#define BE2_DEFPDU_DATA_SZ 8192
6733b39a 60
bfead3b2 61#define MAX_CPUS 31
aa359032 62#define BEISCSI_SGLIST_ELEMENTS 30
6733b39a 63
6733b39a 64#define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
aa359032 65#define BEISCSI_MAX_SECTORS 256 /* scsi_host->max_sectors */
6733b39a
JK		 66
67#define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
68#define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
69#define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
70#define BEISCSI_MAX_FRAGS_INIT 192
71#define BE_NUM_MSIX_ENTRIES 1
72#define MPU_EP_SEMAPHORE 0xac
73
74#define BE_SENSE_INFO_SIZE 258
75#define BE_ISCSI_PDU_HEADER_SIZE 64
76#define BE_MIN_MEM_SIZE 16384
bfead3b2 77#define MAX_CMD_SZ 65536
6733b39a
JK		 78#define IIOC_SCSI_DATA 0x05 /* Write Operation */
79
80#define DBG_LVL 0x00000001
81#define DBG_LVL_1 0x00000001
82#define DBG_LVL_2 0x00000002
83#define DBG_LVL_3 0x00000004
84#define DBG_LVL_4 0x00000008
85#define DBG_LVL_5 0x00000010
86#define DBG_LVL_6 0x00000020
87#define DBG_LVL_7 0x00000040
88#define DBG_LVL_8 0x00000080
89
90#define SE_DEBUG(debug_mask, fmt, args...) \
91do { \
92 if (debug_mask & DBG_LVL) { \
93 printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\
94 printk(fmt, ##args); \
95 } \
96} while (0);
97
bfead3b2
JK		 98#define BE_ADAPTER_UP 0x00000000
99#define BE_ADAPTER_LINK_DOWN 0x00000001
6733b39a
JK		 100/**
101 * hardware needs the async PDU buffers to be posted in multiples of 8
102 * So have atleast 8 of them by default
103 */
104
105#define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
106
107/********* Memory BAR register ************/
108#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
109/**
110 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
111 * Disable" may still globally block interrupts in addition to individual
112 * interrupt masks; a mechanism for the device driver to block all interrupts
113 * atomically without having to arbitrate for the PCI Interrupt Disable bit
114 * with the OS.
115 */
116#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
117
118/********* ISR0 Register offset **********/
119#define CEV_ISR0_OFFSET 0xC18
120#define CEV_ISR_SIZE 4
121
122/**
123 * Macros for reading/writing a protection domain or CSR registers
124 * in BladeEngine.
125 */
126
127#define DB_TXULP0_OFFSET 0x40
128#define DB_RXULP0_OFFSET 0xA0
129/********* Event Q door bell *************/
130#define DB_EQ_OFFSET DB_CQ_OFFSET
131#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
132/* Clear the interrupt for this eq */
133#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
134/* Must be 1 */
135#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
136/* Number of event entries processed */
137#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
138/* Rearm bit */
139#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
140
141/********* Compl Q door bell *************/
142#define DB_CQ_OFFSET 0x120
143#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
144/* Number of event entries processed */
145#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
146/* Rearm bit */
147#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
148
149#define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
150#define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
151 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
152#define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
153 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
154
155#define PAGES_REQUIRED(x) \
156 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
157
158enum be_mem_enum {
159 HWI_MEM_ADDN_CONTEXT,
6733b39a
JK		 160 HWI_MEM_WRB,
161 HWI_MEM_WRBH,
bfead3b2 162 HWI_MEM_SGLH,
6733b39a 163 HWI_MEM_SGE,
bfead3b2 164 HWI_MEM_ASYNC_HEADER_BUF, /* 5 */
6733b39a
JK		 165 HWI_MEM_ASYNC_DATA_BUF,
166 HWI_MEM_ASYNC_HEADER_RING,
bfead3b2 167 HWI_MEM_ASYNC_DATA_RING,
6733b39a 168 HWI_MEM_ASYNC_HEADER_HANDLE,
bfead3b2 169 HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */
6733b39a
JK		 170 HWI_MEM_ASYNC_PDU_CONTEXT,
171 ISCSI_MEM_GLOBAL_HEADER,
bfead3b2 172 SE_MEM_MAX
6733b39a
JK		 173};
174
175struct be_bus_address32 {
176 unsigned int address_lo;
177 unsigned int address_hi;
178};
179
180struct be_bus_address64 {
181 unsigned long long address;
182};
183
184struct be_bus_address {
185 union {
186 struct be_bus_address32 a32;
187 struct be_bus_address64 a64;
188 } u;
189};
190
191struct mem_array {
192 struct be_bus_address bus_address; /* Bus address of location */
193 void *virtual_address; /* virtual address to the location */
194 unsigned int size; /* Size required by memory block */
195};
196
197struct be_mem_descriptor {
198 unsigned int index; /* Index of this memory parameter */
199 unsigned int category; /* type indicates cached/non-cached */
200 unsigned int num_elements; /* number of elements in this
201 * descriptor
202 */
203 unsigned int alignment_mask; /* Alignment mask for this block */
204 unsigned int size_in_bytes; /* Size required by memory block */
205 struct mem_array *mem_array;
206};
207
208struct sgl_handle {
209 unsigned int sgl_index;
bfead3b2
JK		 210 unsigned int type;
211 unsigned int cid;
212 struct iscsi_task *task;
6733b39a
JK		 213 struct iscsi_sge *pfrag;
214};
215
216struct hba_parameters {
217 unsigned int ios_per_ctrl;
218 unsigned int cxns_per_ctrl;
219 unsigned int asyncpdus_per_ctrl;
220 unsigned int icds_per_ctrl;
221 unsigned int num_sge_per_io;
222 unsigned int defpdu_hdr_sz;
223 unsigned int defpdu_data_sz;
224 unsigned int num_cq_entries;
225 unsigned int num_eq_entries;
226 unsigned int wrbs_per_cxn;
227 unsigned int crashmode;
228 unsigned int hba_num;
229
230 unsigned int mgmt_ws_sz;
231 unsigned int hwi_ws_sz;
232
233 unsigned int eto;
234 unsigned int ldto;
235
236 unsigned int dbg_flags;
237 unsigned int num_cxn;
238
239 unsigned int eq_timer;
240 /**
241 * These are calculated from other params. They're here
242 * for debug purposes
243 */
244 unsigned int num_mcc_pages;
245 unsigned int num_mcc_cq_pages;
246 unsigned int num_cq_pages;
247 unsigned int num_eq_pages;
248
249 unsigned int num_async_pdu_buf_pages;
250 unsigned int num_async_pdu_buf_sgl_pages;
251 unsigned int num_async_pdu_buf_cq_pages;
252
253 unsigned int num_async_pdu_hdr_pages;
254 unsigned int num_async_pdu_hdr_sgl_pages;
255 unsigned int num_async_pdu_hdr_cq_pages;
256
257 unsigned int num_sge;
258};
259
260struct beiscsi_hba {
261 struct hba_parameters params;
262 struct hwi_controller *phwi_ctrlr;
263 unsigned int mem_req[SE_MEM_MAX];
264 /* PCI BAR mapped addresses */
265 u8 __iomem *csr_va; /* CSR */
266 u8 __iomem *db_va; /* Door Bell */
267 u8 __iomem *pci_va; /* PCI Config */
268 struct be_bus_address csr_pa; /* CSR */
269 struct be_bus_address db_pa; /* CSR */
270 struct be_bus_address pci_pa; /* CSR */
271 /* PCI representation of our HBA */
272 struct pci_dev *pcidev;
273 unsigned int state;
274 unsigned short asic_revision;
bfead3b2
JK		 275 unsigned int num_cpus;
276 unsigned int nxt_cqid;
277 struct msix_entry msix_entries[MAX_CPUS + 1];
278 bool msix_enabled;
6733b39a
JK		 279 struct be_mem_descriptor *init_mem;
280
281 unsigned short io_sgl_alloc_index;
282 unsigned short io_sgl_free_index;
283 unsigned short io_sgl_hndl_avbl;
284 struct sgl_handle **io_sgl_hndl_base;
bfead3b2 285 struct sgl_handle **sgl_hndl_array;
6733b39a
JK		 286
287 unsigned short eh_sgl_alloc_index;
288 unsigned short eh_sgl_free_index;
289 unsigned short eh_sgl_hndl_avbl;
290 struct sgl_handle **eh_sgl_hndl_base;
291 spinlock_t io_sgl_lock;
292 spinlock_t mgmt_sgl_lock;
293 spinlock_t isr_lock;
294 unsigned int age;
295 unsigned short avlbl_cids;
296 unsigned short cid_alloc;
297 unsigned short cid_free;
298 struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
299 struct list_head hba_queue;
300 unsigned short *cid_array;
301 struct iscsi_endpoint **ep_array;
302 struct Scsi_Host *shost;
303 struct {
304 /**
305 * group together since they are used most frequently
306 * for cid to cri conversion
307 */
308 unsigned int iscsi_cid_start;
309 unsigned int phys_port;
310
311 unsigned int isr_offset;
312 unsigned int iscsi_icd_start;
313 unsigned int iscsi_cid_count;
314 unsigned int iscsi_icd_count;
315 unsigned int pci_function;
316
317 unsigned short cid_alloc;
318 unsigned short cid_free;
319 unsigned short avlbl_cids;
bfead3b2 320 unsigned short iscsi_features;
6733b39a
JK		 321 spinlock_t cid_lock;
322 } fw_config;
323
324 u8 mac_address[ETH_ALEN];
325 unsigned short todo_cq;
326 unsigned short todo_mcc_cq;
327 char wq_name[20];
328 struct workqueue_struct *wq; /* The actuak work queue */
329 struct work_struct work_cqs; /* The work being queued */
330 struct be_ctrl_info ctrl;
f98c96b0 331 unsigned int generation;
6733b39a
JK		 332};
333
b8b9e1b8
JK		 334struct beiscsi_session {
335 struct pci_pool *bhs_pool;
336};
337
6733b39a
JK		 338/**
339 * struct beiscsi_conn - iscsi connection structure
340 */
341struct beiscsi_conn {
342 struct iscsi_conn *conn;
343 struct beiscsi_hba *phba;
344 u32 exp_statsn;
345 u32 beiscsi_conn_cid;
346 struct beiscsi_endpoint *ep;
347 unsigned short login_in_progress;
348 struct sgl_handle *plogin_sgl_handle;
b8b9e1b8 349 struct beiscsi_session *beiscsi_sess;
bfead3b2 350 struct iscsi_task *task;
6733b39a
JK		 351};
352
353/* This structure is used by the chip */
354struct pdu_data_out {
355 u32 dw[12];
356};
357/**
358 * Pseudo amap definition in which each bit of the actual structure is defined
359 * as a byte: used to calculate offset/shift/mask of each field
360 */
361struct amap_pdu_data_out {
362 u8 opcode[6]; /* opcode */
363 u8 rsvd0[2]; /* should be 0 */
364 u8 rsvd1[7];
365 u8 final_bit; /* F bit */
366 u8 rsvd2[16];
367 u8 ahs_length[8]; /* no AHS */
368 u8 data_len_hi[8];
369 u8 data_len_lo[16]; /* DataSegmentLength */
370 u8 lun[64];
371 u8 itt[32]; /* ITT; initiator task tag */
372 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
373 u8 rsvd3[32];
374 u8 exp_stat_sn[32];
375 u8 rsvd4[32];
376 u8 data_sn[32];
377 u8 buffer_offset[32];
378 u8 rsvd5[32];
379};
380
381struct be_cmd_bhs {
382 struct iscsi_cmd iscsi_hdr;
383 unsigned char pad1[16];
384 struct pdu_data_out iscsi_data_pdu;
385 unsigned char pad2[BE_SENSE_INFO_SIZE -
386 sizeof(struct pdu_data_out)];
387};
388
389struct beiscsi_io_task {
390 struct wrb_handle *pwrb_handle;
391 struct sgl_handle *psgl_handle;
392 struct beiscsi_conn *conn;
393 struct scsi_cmnd *scsi_cmnd;
394 unsigned int cmd_sn;
395 unsigned int flags;
396 unsigned short cid;
397 unsigned short header_len;
bfead3b2 398 itt_t libiscsi_itt;
6733b39a
JK		 399 struct be_cmd_bhs *cmd_bhs;
400 struct be_bus_address bhs_pa;
401 unsigned short bhs_len;
402};
403
404struct be_nonio_bhs {
405 struct iscsi_hdr iscsi_hdr;
406 unsigned char pad1[16];
407 struct pdu_data_out iscsi_data_pdu;
408 unsigned char pad2[BE_SENSE_INFO_SIZE -
409 sizeof(struct pdu_data_out)];
410};
411
412struct be_status_bhs {
413 struct iscsi_cmd iscsi_hdr;
414 unsigned char pad1[16];
415 /**
416 * The plus 2 below is to hold the sense info length that gets
417 * DMA'ed by RxULP
418 */
419 unsigned char sense_info[BE_SENSE_INFO_SIZE];
420};
421
422struct iscsi_sge {
423 u32 dw[4];
424};
425
426/**
427 * Pseudo amap definition in which each bit of the actual structure is defined
428 * as a byte: used to calculate offset/shift/mask of each field
429 */
430struct amap_iscsi_sge {
431 u8 addr_hi[32];
432 u8 addr_lo[32];
433 u8 sge_offset[22]; /* DWORD 2 */
434 u8 rsvd0[9]; /* DWORD 2 */
435 u8 last_sge; /* DWORD 2 */
436 u8 len[17]; /* DWORD 3 */
437 u8 rsvd1[15]; /* DWORD 3 */
438};
439
440struct beiscsi_offload_params {
441 u32 dw[5];
442};
443
444#define OFFLD_PARAMS_ERL 0x00000003
445#define OFFLD_PARAMS_DDE 0x00000004
446#define OFFLD_PARAMS_HDE 0x00000008
447#define OFFLD_PARAMS_IR2T 0x00000010
448#define OFFLD_PARAMS_IMD 0x00000020
449
450/**
451 * Pseudo amap definition in which each bit of the actual structure is defined
452 * as a byte: used to calculate offset/shift/mask of each field
453 */
454struct amap_beiscsi_offload_params {
455 u8 max_burst_length[32];
456 u8 max_send_data_segment_length[32];
457 u8 first_burst_length[32];
458 u8 erl[2];
459 u8 dde[1];
460 u8 hde[1];
461 u8 ir2t[1];
462 u8 imd[1];
463 u8 pad[26];
464 u8 exp_statsn[32];
465};
466
467/* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
468 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
469
470struct async_pdu_handle {
471 struct list_head link;
472 struct be_bus_address pa;
473 void *pbuffer;
474 unsigned int consumed;
475 unsigned char index;
476 unsigned char is_header;
477 unsigned short cri;
478 unsigned long buffer_len;
479};
480
481struct hwi_async_entry {
482 struct {
483 unsigned char hdr_received;
484 unsigned char hdr_len;
485 unsigned short bytes_received;
486 unsigned int bytes_needed;
487 struct list_head list;
488 } wait_queue;
489
490 struct list_head header_busy_list;
491 struct list_head data_busy_list;
492};
493
494#define BE_MIN_ASYNC_ENTRIES 128
495
496struct hwi_async_pdu_context {
497 struct {
498 struct be_bus_address pa_base;
499 void *va_base;
500 void *ring_base;
501 struct async_pdu_handle *handle_base;
502
503 unsigned int host_write_ptr;
504 unsigned int ep_read_ptr;
505 unsigned int writables;
506
507 unsigned int free_entries;
508 unsigned int busy_entries;
509 unsigned int buffer_size;
510 unsigned int num_entries;
511
512 struct list_head free_list;
513 } async_header;
514
515 struct {
516 struct be_bus_address pa_base;
517 void *va_base;
518 void *ring_base;
519 struct async_pdu_handle *handle_base;
520
521 unsigned int host_write_ptr;
522 unsigned int ep_read_ptr;
523 unsigned int writables;
524
525 unsigned int free_entries;
526 unsigned int busy_entries;
527 unsigned int buffer_size;
528 struct list_head free_list;
529 unsigned int num_entries;
530 } async_data;
531
532 /**
533 * This is a varying size list! Do not add anything
534 * after this entry!!
535 */
536 struct hwi_async_entry async_entry[BE_MIN_ASYNC_ENTRIES];
537};
538
539#define PDUCQE_CODE_MASK 0x0000003F
540#define PDUCQE_DPL_MASK 0xFFFF0000
541#define PDUCQE_INDEX_MASK 0x0000FFFF
542
543struct i_t_dpdu_cqe {
544 u32 dw[4];
545} __packed;
546
547/**
548 * Pseudo amap definition in which each bit of the actual structure is defined
549 * as a byte: used to calculate offset/shift/mask of each field
550 */
551struct amap_i_t_dpdu_cqe {
552 u8 db_addr_hi[32];
553 u8 db_addr_lo[32];
554 u8 code[6];
555 u8 cid[10];
556 u8 dpl[16];
557 u8 index[16];
558 u8 num_cons[10];
559 u8 rsvd0[4];
560 u8 final;
561 u8 valid;
562} __packed;
563
564#define CQE_VALID_MASK 0x80000000
565#define CQE_CODE_MASK 0x0000003F
566#define CQE_CID_MASK 0x0000FFC0
567
568#define EQE_VALID_MASK 0x00000001
569#define EQE_MAJORCODE_MASK 0x0000000E
570#define EQE_RESID_MASK 0xFFFF0000
571
572struct be_eq_entry {
573 u32 dw[1];
574} __packed;
575
576/**
577 * Pseudo amap definition in which each bit of the actual structure is defined
578 * as a byte: used to calculate offset/shift/mask of each field
579 */
580struct amap_eq_entry {
581 u8 valid; /* DWORD 0 */
582 u8 major_code[3]; /* DWORD 0 */
583 u8 minor_code[12]; /* DWORD 0 */
584 u8 resource_id[16]; /* DWORD 0 */
585
586} __packed;
587
588struct cq_db {
589 u32 dw[1];
590} __packed;
591
592/**
593 * Pseudo amap definition in which each bit of the actual structure is defined
594 * as a byte: used to calculate offset/shift/mask of each field
595 */
596struct amap_cq_db {
597 u8 qid[10];
598 u8 event[1];
599 u8 rsvd0[5];
600 u8 num_popped[13];
601 u8 rearm[1];
602 u8 rsvd1[2];
603} __packed;
604
605void beiscsi_process_eq(struct beiscsi_hba *phba);
606
6733b39a
JK		 607struct iscsi_wrb {
608 u32 dw[16];
609} __packed;
610
611#define WRB_TYPE_MASK 0xF0000000
612
613/**
614 * Pseudo amap definition in which each bit of the actual structure is defined
615 * as a byte: used to calculate offset/shift/mask of each field
616 */
617struct amap_iscsi_wrb {
618 u8 lun[14]; /* DWORD 0 */
619 u8 lt; /* DWORD 0 */
620 u8 invld; /* DWORD 0 */
621 u8 wrb_idx[8]; /* DWORD 0 */
622 u8 dsp; /* DWORD 0 */
623 u8 dmsg; /* DWORD 0 */
624 u8 undr_run; /* DWORD 0 */
625 u8 over_run; /* DWORD 0 */
626 u8 type[4]; /* DWORD 0 */
627 u8 ptr2nextwrb[8]; /* DWORD 1 */
628 u8 r2t_exp_dtl[24]; /* DWORD 1 */
629 u8 sgl_icd_idx[12]; /* DWORD 2 */
630 u8 rsvd0[20]; /* DWORD 2 */
631 u8 exp_data_sn[32]; /* DWORD 3 */
632 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
633 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
634 u8 cmdsn_itt[32]; /* DWORD 6 */
635 u8 dif_ref_tag[32]; /* DWORD 7 */
636 u8 sge0_addr_hi[32]; /* DWORD 8 */
637 u8 sge0_addr_lo[32]; /* DWORD 9 */
638 u8 sge0_offset[22]; /* DWORD 10 */
639 u8 pbs; /* DWORD 10 */
640 u8 dif_mode[2]; /* DWORD 10 */
641 u8 rsvd1[6]; /* DWORD 10 */
642 u8 sge0_last; /* DWORD 10 */
643 u8 sge0_len[17]; /* DWORD 11 */
644 u8 dif_meta_tag[14]; /* DWORD 11 */
645 u8 sge0_in_ddr; /* DWORD 11 */
646 u8 sge1_addr_hi[32]; /* DWORD 12 */
647 u8 sge1_addr_lo[32]; /* DWORD 13 */
648 u8 sge1_r2t_offset[22]; /* DWORD 14 */
649 u8 rsvd2[9]; /* DWORD 14 */
650 u8 sge1_last; /* DWORD 14 */
651 u8 sge1_len[17]; /* DWORD 15 */
652 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
653 u8 rsvd3[2]; /* DWORD 15 */
654 u8 sge1_in_ddr; /* DWORD 15 */
655
656} __packed;
657
d5431488 658struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
6733b39a
JK		 659void
660free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
661
756d29c8
JK		 662void beiscsi_process_all_cqs(struct work_struct *work);
663
6733b39a
JK		 664struct pdu_nop_out {
665 u32 dw[12];
666};
667
668/**
669 * Pseudo amap definition in which each bit of the actual structure is defined
670 * as a byte: used to calculate offset/shift/mask of each field
671 */
672struct amap_pdu_nop_out {
673 u8 opcode[6]; /* opcode 0x00 */
674 u8 i_bit; /* I Bit */
675 u8 x_bit; /* reserved; should be 0 */
676 u8 fp_bit_filler1[7];
677 u8 f_bit; /* always 1 */
678 u8 reserved1[16];
679 u8 ahs_length[8]; /* no AHS */
680 u8 data_len_hi[8];
681 u8 data_len_lo[16]; /* DataSegmentLength */
682 u8 lun[64];
683 u8 itt[32]; /* initiator id for ping or 0xffffffff */
684 u8 ttt[32]; /* target id for ping or 0xffffffff */
685 u8 cmd_sn[32];
686 u8 exp_stat_sn[32];
687 u8 reserved5[128];
688};
689
690#define PDUBASE_OPCODE_MASK 0x0000003F
691#define PDUBASE_DATALENHI_MASK 0x0000FF00
692#define PDUBASE_DATALENLO_MASK 0xFFFF0000
693
694struct pdu_base {
695 u32 dw[16];
696} __packed;
697
698/**
699 * Pseudo amap definition in which each bit of the actual structure is defined
700 * as a byte: used to calculate offset/shift/mask of each field
701 */
702struct amap_pdu_base {
703 u8 opcode[6];
704 u8 i_bit; /* immediate bit */
705 u8 x_bit; /* reserved, always 0 */
706 u8 reserved1[24]; /* opcode-specific fields */
707 u8 ahs_length[8]; /* length units is 4 byte words */
708 u8 data_len_hi[8];
709 u8 data_len_lo[16]; /* DatasegmentLength */
710 u8 lun[64]; /* lun or opcode-specific fields */
711 u8 itt[32]; /* initiator task tag */
712 u8 reserved4[224];
713};
714
715struct iscsi_target_context_update_wrb {
716 u32 dw[16];
717} __packed;
718
719/**
720 * Pseudo amap definition in which each bit of the actual structure is defined
721 * as a byte: used to calculate offset/shift/mask of each field
722 */
723struct amap_iscsi_target_context_update_wrb {
724 u8 lun[14]; /* DWORD 0 */
725 u8 lt; /* DWORD 0 */
726 u8 invld; /* DWORD 0 */
727 u8 wrb_idx[8]; /* DWORD 0 */
728 u8 dsp; /* DWORD 0 */
729 u8 dmsg; /* DWORD 0 */
730 u8 undr_run; /* DWORD 0 */
731 u8 over_run; /* DWORD 0 */
732 u8 type[4]; /* DWORD 0 */
733 u8 ptr2nextwrb[8]; /* DWORD 1 */
734 u8 max_burst_length[19]; /* DWORD 1 */
735 u8 rsvd0[5]; /* DWORD 1 */
736 u8 rsvd1[15]; /* DWORD 2 */
737 u8 max_send_data_segment_length[17]; /* DWORD 2 */
738 u8 first_burst_length[14]; /* DWORD 3 */
739 u8 rsvd2[2]; /* DWORD 3 */
740 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
741 u8 rsvd3[5]; /* DWORD 3 */
742 u8 session_state[3]; /* DWORD 3 */
743 u8 rsvd4[16]; /* DWORD 4 */
744 u8 tx_jumbo; /* DWORD 4 */
745 u8 hde; /* DWORD 4 */
746 u8 dde; /* DWORD 4 */
747 u8 erl[2]; /* DWORD 4 */
748 u8 domain_id[5]; /* DWORD 4 */
749 u8 mode; /* DWORD 4 */
750 u8 imd; /* DWORD 4 */
751 u8 ir2t; /* DWORD 4 */
752 u8 notpredblq[2]; /* DWORD 4 */
753 u8 compltonack; /* DWORD 4 */
754 u8 stat_sn[32]; /* DWORD 5 */
755 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
756 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
757 u8 pad_addr_hi[32]; /* DWORD 8 */
758 u8 pad_addr_lo[32]; /* DWORD 9 */
759 u8 rsvd5[32]; /* DWORD 10 */
760 u8 rsvd6[32]; /* DWORD 11 */
761 u8 rsvd7[32]; /* DWORD 12 */
762 u8 rsvd8[32]; /* DWORD 13 */
763 u8 rsvd9[32]; /* DWORD 14 */
764 u8 rsvd10[32]; /* DWORD 15 */
765
766} __packed;
767
768struct be_ring {
769 u32 pages; /* queue size in pages */
770 u32 id; /* queue id assigned by beklib */
771 u32 num; /* number of elements in queue */
772 u32 cidx; /* consumer index */
773 u32 pidx; /* producer index -- not used by most rings */
774 u32 item_size; /* size in bytes of one object */
775
776 void *va; /* The virtual address of the ring. This
777 * should be last to allow 32 & 64 bit debugger
778 * extensions to work.
779 */
780};
781
782struct hwi_wrb_context {
783 struct list_head wrb_handle_list;
784 struct list_head wrb_handle_drvr_list;
785 struct wrb_handle **pwrb_handle_base;
786 struct wrb_handle **pwrb_handle_basestd;
787 struct iscsi_wrb *plast_wrb;
788 unsigned short alloc_index;
789 unsigned short free_index;
790 unsigned short wrb_handles_available;
791 unsigned short cid;
792};
793
794struct hwi_controller {
795 struct list_head io_sgl_list;
796 struct list_head eh_sgl_list;
797 struct sgl_handle *psgl_handle_base;
798 unsigned int wrb_mem_index;
799
800 struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
801 struct mcc_wrb *pmcc_wrb_base;
802 struct be_ring default_pdu_hdr;
803 struct be_ring default_pdu_data;
804 struct hwi_context_memory *phwi_ctxt;
6733b39a
JK		 805};
806
807enum hwh_type_enum {
808 HWH_TYPE_IO = 1,
809 HWH_TYPE_LOGOUT = 2,
810 HWH_TYPE_TMF = 3,
811 HWH_TYPE_NOP = 4,
812 HWH_TYPE_IO_RD = 5,
813 HWH_TYPE_LOGIN = 11,
814 HWH_TYPE_INVALID = 0xFFFFFFFF
815};
816
817struct wrb_handle {
818 enum hwh_type_enum type;
819 unsigned short wrb_index;
820 unsigned short nxt_wrb_index;
821
822 struct iscsi_task *pio_handle;
823 struct iscsi_wrb *pwrb;
824};
825
826struct hwi_context_memory {
bfead3b2
JK		 827 /* Adaptive interrupt coalescing (AIC) info */
828 u16 min_eqd; /* in usecs */
829 u16 max_eqd; /* in usecs */
830 u16 cur_eqd; /* in usecs */
831 struct be_eq_obj be_eq[MAX_CPUS];
832 struct be_queue_info be_cq[MAX_CPUS];
6733b39a
JK		 833
834 struct be_queue_info be_def_hdrq;
835 struct be_queue_info be_def_dataq;
836
837 struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
838 struct be_mcc_wrb_context *pbe_mcc_context;
839
840 struct hwi_async_pdu_context *pasync_ctx;
841};
842
843#endif
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