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[SCSI] be2iscsi: add 10Gbps iSCSI - BladeEngine 2 driver
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / be2iscsi / be_main.h
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6733b39a
JK		 1/**
2 * Copyright (C) 2005 - 2009 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Written by: Jayamohan Kallickal (jayamohank@serverengines.com)
11 *
12 * Contact Information:
13 * linux-drivers@serverengines.com
14 *
15 * ServerEngines
16 * 209 N. Fair Oaks Ave
17 * Sunnyvale, CA 94085
18 *
19 */
20
21#ifndef _BEISCSI_MAIN_
22#define _BEISCSI_MAIN_
23
24
25#include <linux/kernel.h>
26#include <linux/pci.h>
27#include <linux/in.h>
28#include <linux/blk-iopoll.h>
29#include <scsi/scsi.h>
30#include <scsi/scsi_cmnd.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_host.h>
33#include <scsi/iscsi_proto.h>
34#include <scsi/libiscsi.h>
35#include <scsi/scsi_transport_iscsi.h>
36
37#include "be.h"
38
39
40
41#define DRV_NAME "be2iscsi"
42#define BUILD_STR "2.0.527.0"
43
44#define BE_NAME "ServerEngines BladeEngine2" \
45 "Linux iSCSI Driver version" BUILD_STR
46#define DRV_DESC BE_NAME " " "Driver"
47
48#define BE_VENDOR_ID 0x19A2
49#define BE_DEVICE_ID1 0x212
50#define OC_DEVICE_ID1 0x702
51#define OC_DEVICE_ID2 0x703
52
53#define BE2_MAX_SESSIONS 64
54#define BE2_CMDS_PER_CXN 128
55#define BE2_LOGOUTS BE2_MAX_SESSIONS
56#define BE2_TMFS 16
57#define BE2_NOPOUT_REQ 16
58#define BE2_ASYNCPDUS BE2_MAX_SESSIONS
59#define BE2_MAX_ICDS 2048
60#define BE2_SGE 32
61#define BE2_DEFPDU_HDR_SZ 64
62#define BE2_DEFPDU_DATA_SZ 8192
63#define BE2_IO_DEPTH \
64 (BE2_MAX_ICDS / 2 - (BE2_LOGOUTS + BE2_TMFS + BE2_NOPOUT_REQ))
65
66#define BEISCSI_SGLIST_ELEMENTS BE2_SGE
67
68#define BEISCSI_MAX_CMNDS 1024 /* Max IO's per Ctrlr sht->can_queue */
69#define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
70#define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */
71
72#define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
73#define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
74#define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
75#define BEISCSI_MAX_FRAGS_INIT 192
76#define BE_NUM_MSIX_ENTRIES 1
77#define MPU_EP_SEMAPHORE 0xac
78
79#define BE_SENSE_INFO_SIZE 258
80#define BE_ISCSI_PDU_HEADER_SIZE 64
81#define BE_MIN_MEM_SIZE 16384
82
83#define IIOC_SCSI_DATA 0x05 /* Write Operation */
84
85#define DBG_LVL 0x00000001
86#define DBG_LVL_1 0x00000001
87#define DBG_LVL_2 0x00000002
88#define DBG_LVL_3 0x00000004
89#define DBG_LVL_4 0x00000008
90#define DBG_LVL_5 0x00000010
91#define DBG_LVL_6 0x00000020
92#define DBG_LVL_7 0x00000040
93#define DBG_LVL_8 0x00000080
94
95#define SE_DEBUG(debug_mask, fmt, args...) \
96do { \
97 if (debug_mask & DBG_LVL) { \
98 printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\
99 printk(fmt, ##args); \
100 } \
101} while (0);
102
103/**
104 * hardware needs the async PDU buffers to be posted in multiples of 8
105 * So have atleast 8 of them by default
106 */
107
108#define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
109
110/********* Memory BAR register ************/
111#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
112/**
113 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
114 * Disable" may still globally block interrupts in addition to individual
115 * interrupt masks; a mechanism for the device driver to block all interrupts
116 * atomically without having to arbitrate for the PCI Interrupt Disable bit
117 * with the OS.
118 */
119#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
120
121/********* ISR0 Register offset **********/
122#define CEV_ISR0_OFFSET 0xC18
123#define CEV_ISR_SIZE 4
124
125/**
126 * Macros for reading/writing a protection domain or CSR registers
127 * in BladeEngine.
128 */
129
130#define DB_TXULP0_OFFSET 0x40
131#define DB_RXULP0_OFFSET 0xA0
132/********* Event Q door bell *************/
133#define DB_EQ_OFFSET DB_CQ_OFFSET
134#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
135/* Clear the interrupt for this eq */
136#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
137/* Must be 1 */
138#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
139/* Number of event entries processed */
140#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
141/* Rearm bit */
142#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
143
144/********* Compl Q door bell *************/
145#define DB_CQ_OFFSET 0x120
146#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
147/* Number of event entries processed */
148#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
149/* Rearm bit */
150#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
151
152#define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
153#define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
154 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
155#define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
156 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
157
158#define PAGES_REQUIRED(x) \
159 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
160
161enum be_mem_enum {
162 HWI_MEM_ADDN_CONTEXT,
163 HWI_MEM_CQ,
164 HWI_MEM_EQ,
165 HWI_MEM_WRB,
166 HWI_MEM_WRBH,
167 HWI_MEM_SGLH, /* 5 */
168 HWI_MEM_SGE,
169 HWI_MEM_ASYNC_HEADER_BUF,
170 HWI_MEM_ASYNC_DATA_BUF,
171 HWI_MEM_ASYNC_HEADER_RING,
172 HWI_MEM_ASYNC_DATA_RING, /* 10 */
173 HWI_MEM_ASYNC_HEADER_HANDLE,
174 HWI_MEM_ASYNC_DATA_HANDLE,
175 HWI_MEM_ASYNC_PDU_CONTEXT,
176 ISCSI_MEM_GLOBAL_HEADER,
177 SE_MEM_MAX /* 15 */
178};
179
180struct be_bus_address32 {
181 unsigned int address_lo;
182 unsigned int address_hi;
183};
184
185struct be_bus_address64 {
186 unsigned long long address;
187};
188
189struct be_bus_address {
190 union {
191 struct be_bus_address32 a32;
192 struct be_bus_address64 a64;
193 } u;
194};
195
196struct mem_array {
197 struct be_bus_address bus_address; /* Bus address of location */
198 void *virtual_address; /* virtual address to the location */
199 unsigned int size; /* Size required by memory block */
200};
201
202struct be_mem_descriptor {
203 unsigned int index; /* Index of this memory parameter */
204 unsigned int category; /* type indicates cached/non-cached */
205 unsigned int num_elements; /* number of elements in this
206 * descriptor
207 */
208 unsigned int alignment_mask; /* Alignment mask for this block */
209 unsigned int size_in_bytes; /* Size required by memory block */
210 struct mem_array *mem_array;
211};
212
213struct sgl_handle {
214 unsigned int sgl_index;
215 struct iscsi_sge *pfrag;
216};
217
218struct hba_parameters {
219 unsigned int ios_per_ctrl;
220 unsigned int cxns_per_ctrl;
221 unsigned int asyncpdus_per_ctrl;
222 unsigned int icds_per_ctrl;
223 unsigned int num_sge_per_io;
224 unsigned int defpdu_hdr_sz;
225 unsigned int defpdu_data_sz;
226 unsigned int num_cq_entries;
227 unsigned int num_eq_entries;
228 unsigned int wrbs_per_cxn;
229 unsigned int crashmode;
230 unsigned int hba_num;
231
232 unsigned int mgmt_ws_sz;
233 unsigned int hwi_ws_sz;
234
235 unsigned int eto;
236 unsigned int ldto;
237
238 unsigned int dbg_flags;
239 unsigned int num_cxn;
240
241 unsigned int eq_timer;
242 /**
243 * These are calculated from other params. They're here
244 * for debug purposes
245 */
246 unsigned int num_mcc_pages;
247 unsigned int num_mcc_cq_pages;
248 unsigned int num_cq_pages;
249 unsigned int num_eq_pages;
250
251 unsigned int num_async_pdu_buf_pages;
252 unsigned int num_async_pdu_buf_sgl_pages;
253 unsigned int num_async_pdu_buf_cq_pages;
254
255 unsigned int num_async_pdu_hdr_pages;
256 unsigned int num_async_pdu_hdr_sgl_pages;
257 unsigned int num_async_pdu_hdr_cq_pages;
258
259 unsigned int num_sge;
260};
261
262struct beiscsi_hba {
263 struct hba_parameters params;
264 struct hwi_controller *phwi_ctrlr;
265 unsigned int mem_req[SE_MEM_MAX];
266 /* PCI BAR mapped addresses */
267 u8 __iomem *csr_va; /* CSR */
268 u8 __iomem *db_va; /* Door Bell */
269 u8 __iomem *pci_va; /* PCI Config */
270 struct be_bus_address csr_pa; /* CSR */
271 struct be_bus_address db_pa; /* CSR */
272 struct be_bus_address pci_pa; /* CSR */
273 /* PCI representation of our HBA */
274 struct pci_dev *pcidev;
275 unsigned int state;
276 unsigned short asic_revision;
277 struct blk_iopoll iopoll;
278 struct be_mem_descriptor *init_mem;
279
280 unsigned short io_sgl_alloc_index;
281 unsigned short io_sgl_free_index;
282 unsigned short io_sgl_hndl_avbl;
283 struct sgl_handle **io_sgl_hndl_base;
284
285 unsigned short eh_sgl_alloc_index;
286 unsigned short eh_sgl_free_index;
287 unsigned short eh_sgl_hndl_avbl;
288 struct sgl_handle **eh_sgl_hndl_base;
289 spinlock_t io_sgl_lock;
290 spinlock_t mgmt_sgl_lock;
291 spinlock_t isr_lock;
292 unsigned int age;
293 unsigned short avlbl_cids;
294 unsigned short cid_alloc;
295 unsigned short cid_free;
296 struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
297 struct list_head hba_queue;
298 unsigned short *cid_array;
299 struct iscsi_endpoint **ep_array;
300 struct Scsi_Host *shost;
301 struct {
302 /**
303 * group together since they are used most frequently
304 * for cid to cri conversion
305 */
306 unsigned int iscsi_cid_start;
307 unsigned int phys_port;
308
309 unsigned int isr_offset;
310 unsigned int iscsi_icd_start;
311 unsigned int iscsi_cid_count;
312 unsigned int iscsi_icd_count;
313 unsigned int pci_function;
314
315 unsigned short cid_alloc;
316 unsigned short cid_free;
317 unsigned short avlbl_cids;
318 spinlock_t cid_lock;
319 } fw_config;
320
321 u8 mac_address[ETH_ALEN];
322 unsigned short todo_cq;
323 unsigned short todo_mcc_cq;
324 char wq_name[20];
325 struct workqueue_struct *wq; /* The actuak work queue */
326 struct work_struct work_cqs; /* The work being queued */
327 struct be_ctrl_info ctrl;
328};
329
330/**
331 * struct beiscsi_conn - iscsi connection structure
332 */
333struct beiscsi_conn {
334 struct iscsi_conn *conn;
335 struct beiscsi_hba *phba;
336 u32 exp_statsn;
337 u32 beiscsi_conn_cid;
338 struct beiscsi_endpoint *ep;
339 unsigned short login_in_progress;
340 struct sgl_handle *plogin_sgl_handle;
341};
342
343/* This structure is used by the chip */
344struct pdu_data_out {
345 u32 dw[12];
346};
347/**
348 * Pseudo amap definition in which each bit of the actual structure is defined
349 * as a byte: used to calculate offset/shift/mask of each field
350 */
351struct amap_pdu_data_out {
352 u8 opcode[6]; /* opcode */
353 u8 rsvd0[2]; /* should be 0 */
354 u8 rsvd1[7];
355 u8 final_bit; /* F bit */
356 u8 rsvd2[16];
357 u8 ahs_length[8]; /* no AHS */
358 u8 data_len_hi[8];
359 u8 data_len_lo[16]; /* DataSegmentLength */
360 u8 lun[64];
361 u8 itt[32]; /* ITT; initiator task tag */
362 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
363 u8 rsvd3[32];
364 u8 exp_stat_sn[32];
365 u8 rsvd4[32];
366 u8 data_sn[32];
367 u8 buffer_offset[32];
368 u8 rsvd5[32];
369};
370
371struct be_cmd_bhs {
372 struct iscsi_cmd iscsi_hdr;
373 unsigned char pad1[16];
374 struct pdu_data_out iscsi_data_pdu;
375 unsigned char pad2[BE_SENSE_INFO_SIZE -
376 sizeof(struct pdu_data_out)];
377};
378
379struct beiscsi_io_task {
380 struct wrb_handle *pwrb_handle;
381 struct sgl_handle *psgl_handle;
382 struct beiscsi_conn *conn;
383 struct scsi_cmnd *scsi_cmnd;
384 unsigned int cmd_sn;
385 unsigned int flags;
386 unsigned short cid;
387 unsigned short header_len;
388
389 unsigned int alloc_size;
390 struct be_cmd_bhs *cmd_bhs;
391 struct be_bus_address bhs_pa;
392 unsigned short bhs_len;
393};
394
395struct be_nonio_bhs {
396 struct iscsi_hdr iscsi_hdr;
397 unsigned char pad1[16];
398 struct pdu_data_out iscsi_data_pdu;
399 unsigned char pad2[BE_SENSE_INFO_SIZE -
400 sizeof(struct pdu_data_out)];
401};
402
403struct be_status_bhs {
404 struct iscsi_cmd iscsi_hdr;
405 unsigned char pad1[16];
406 /**
407 * The plus 2 below is to hold the sense info length that gets
408 * DMA'ed by RxULP
409 */
410 unsigned char sense_info[BE_SENSE_INFO_SIZE];
411};
412
413struct iscsi_sge {
414 u32 dw[4];
415};
416
417/**
418 * Pseudo amap definition in which each bit of the actual structure is defined
419 * as a byte: used to calculate offset/shift/mask of each field
420 */
421struct amap_iscsi_sge {
422 u8 addr_hi[32];
423 u8 addr_lo[32];
424 u8 sge_offset[22]; /* DWORD 2 */
425 u8 rsvd0[9]; /* DWORD 2 */
426 u8 last_sge; /* DWORD 2 */
427 u8 len[17]; /* DWORD 3 */
428 u8 rsvd1[15]; /* DWORD 3 */
429};
430
431struct beiscsi_offload_params {
432 u32 dw[5];
433};
434
435#define OFFLD_PARAMS_ERL 0x00000003
436#define OFFLD_PARAMS_DDE 0x00000004
437#define OFFLD_PARAMS_HDE 0x00000008
438#define OFFLD_PARAMS_IR2T 0x00000010
439#define OFFLD_PARAMS_IMD 0x00000020
440
441/**
442 * Pseudo amap definition in which each bit of the actual structure is defined
443 * as a byte: used to calculate offset/shift/mask of each field
444 */
445struct amap_beiscsi_offload_params {
446 u8 max_burst_length[32];
447 u8 max_send_data_segment_length[32];
448 u8 first_burst_length[32];
449 u8 erl[2];
450 u8 dde[1];
451 u8 hde[1];
452 u8 ir2t[1];
453 u8 imd[1];
454 u8 pad[26];
455 u8 exp_statsn[32];
456};
457
458/* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
459 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
460
461struct async_pdu_handle {
462 struct list_head link;
463 struct be_bus_address pa;
464 void *pbuffer;
465 unsigned int consumed;
466 unsigned char index;
467 unsigned char is_header;
468 unsigned short cri;
469 unsigned long buffer_len;
470};
471
472struct hwi_async_entry {
473 struct {
474 unsigned char hdr_received;
475 unsigned char hdr_len;
476 unsigned short bytes_received;
477 unsigned int bytes_needed;
478 struct list_head list;
479 } wait_queue;
480
481 struct list_head header_busy_list;
482 struct list_head data_busy_list;
483};
484
485#define BE_MIN_ASYNC_ENTRIES 128
486
487struct hwi_async_pdu_context {
488 struct {
489 struct be_bus_address pa_base;
490 void *va_base;
491 void *ring_base;
492 struct async_pdu_handle *handle_base;
493
494 unsigned int host_write_ptr;
495 unsigned int ep_read_ptr;
496 unsigned int writables;
497
498 unsigned int free_entries;
499 unsigned int busy_entries;
500 unsigned int buffer_size;
501 unsigned int num_entries;
502
503 struct list_head free_list;
504 } async_header;
505
506 struct {
507 struct be_bus_address pa_base;
508 void *va_base;
509 void *ring_base;
510 struct async_pdu_handle *handle_base;
511
512 unsigned int host_write_ptr;
513 unsigned int ep_read_ptr;
514 unsigned int writables;
515
516 unsigned int free_entries;
517 unsigned int busy_entries;
518 unsigned int buffer_size;
519 struct list_head free_list;
520 unsigned int num_entries;
521 } async_data;
522
523 /**
524 * This is a varying size list! Do not add anything
525 * after this entry!!
526 */
527 struct hwi_async_entry async_entry[BE_MIN_ASYNC_ENTRIES];
528};
529
530#define PDUCQE_CODE_MASK 0x0000003F
531#define PDUCQE_DPL_MASK 0xFFFF0000
532#define PDUCQE_INDEX_MASK 0x0000FFFF
533
534struct i_t_dpdu_cqe {
535 u32 dw[4];
536} __packed;
537
538/**
539 * Pseudo amap definition in which each bit of the actual structure is defined
540 * as a byte: used to calculate offset/shift/mask of each field
541 */
542struct amap_i_t_dpdu_cqe {
543 u8 db_addr_hi[32];
544 u8 db_addr_lo[32];
545 u8 code[6];
546 u8 cid[10];
547 u8 dpl[16];
548 u8 index[16];
549 u8 num_cons[10];
550 u8 rsvd0[4];
551 u8 final;
552 u8 valid;
553} __packed;
554
555#define CQE_VALID_MASK 0x80000000
556#define CQE_CODE_MASK 0x0000003F
557#define CQE_CID_MASK 0x0000FFC0
558
559#define EQE_VALID_MASK 0x00000001
560#define EQE_MAJORCODE_MASK 0x0000000E
561#define EQE_RESID_MASK 0xFFFF0000
562
563struct be_eq_entry {
564 u32 dw[1];
565} __packed;
566
567/**
568 * Pseudo amap definition in which each bit of the actual structure is defined
569 * as a byte: used to calculate offset/shift/mask of each field
570 */
571struct amap_eq_entry {
572 u8 valid; /* DWORD 0 */
573 u8 major_code[3]; /* DWORD 0 */
574 u8 minor_code[12]; /* DWORD 0 */
575 u8 resource_id[16]; /* DWORD 0 */
576
577} __packed;
578
579struct cq_db {
580 u32 dw[1];
581} __packed;
582
583/**
584 * Pseudo amap definition in which each bit of the actual structure is defined
585 * as a byte: used to calculate offset/shift/mask of each field
586 */
587struct amap_cq_db {
588 u8 qid[10];
589 u8 event[1];
590 u8 rsvd0[5];
591 u8 num_popped[13];
592 u8 rearm[1];
593 u8 rsvd1[2];
594} __packed;
595
596void beiscsi_process_eq(struct beiscsi_hba *phba);
597
598
599struct iscsi_wrb {
600 u32 dw[16];
601} __packed;
602
603#define WRB_TYPE_MASK 0xF0000000
604
605/**
606 * Pseudo amap definition in which each bit of the actual structure is defined
607 * as a byte: used to calculate offset/shift/mask of each field
608 */
609struct amap_iscsi_wrb {
610 u8 lun[14]; /* DWORD 0 */
611 u8 lt; /* DWORD 0 */
612 u8 invld; /* DWORD 0 */
613 u8 wrb_idx[8]; /* DWORD 0 */
614 u8 dsp; /* DWORD 0 */
615 u8 dmsg; /* DWORD 0 */
616 u8 undr_run; /* DWORD 0 */
617 u8 over_run; /* DWORD 0 */
618 u8 type[4]; /* DWORD 0 */
619 u8 ptr2nextwrb[8]; /* DWORD 1 */
620 u8 r2t_exp_dtl[24]; /* DWORD 1 */
621 u8 sgl_icd_idx[12]; /* DWORD 2 */
622 u8 rsvd0[20]; /* DWORD 2 */
623 u8 exp_data_sn[32]; /* DWORD 3 */
624 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
625 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
626 u8 cmdsn_itt[32]; /* DWORD 6 */
627 u8 dif_ref_tag[32]; /* DWORD 7 */
628 u8 sge0_addr_hi[32]; /* DWORD 8 */
629 u8 sge0_addr_lo[32]; /* DWORD 9 */
630 u8 sge0_offset[22]; /* DWORD 10 */
631 u8 pbs; /* DWORD 10 */
632 u8 dif_mode[2]; /* DWORD 10 */
633 u8 rsvd1[6]; /* DWORD 10 */
634 u8 sge0_last; /* DWORD 10 */
635 u8 sge0_len[17]; /* DWORD 11 */
636 u8 dif_meta_tag[14]; /* DWORD 11 */
637 u8 sge0_in_ddr; /* DWORD 11 */
638 u8 sge1_addr_hi[32]; /* DWORD 12 */
639 u8 sge1_addr_lo[32]; /* DWORD 13 */
640 u8 sge1_r2t_offset[22]; /* DWORD 14 */
641 u8 rsvd2[9]; /* DWORD 14 */
642 u8 sge1_last; /* DWORD 14 */
643 u8 sge1_len[17]; /* DWORD 15 */
644 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
645 u8 rsvd3[2]; /* DWORD 15 */
646 u8 sge1_in_ddr; /* DWORD 15 */
647
648} __packed;
649
650struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
651 int index);
652void
653free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
654
655struct pdu_nop_out {
656 u32 dw[12];
657};
658
659/**
660 * Pseudo amap definition in which each bit of the actual structure is defined
661 * as a byte: used to calculate offset/shift/mask of each field
662 */
663struct amap_pdu_nop_out {
664 u8 opcode[6]; /* opcode 0x00 */
665 u8 i_bit; /* I Bit */
666 u8 x_bit; /* reserved; should be 0 */
667 u8 fp_bit_filler1[7];
668 u8 f_bit; /* always 1 */
669 u8 reserved1[16];
670 u8 ahs_length[8]; /* no AHS */
671 u8 data_len_hi[8];
672 u8 data_len_lo[16]; /* DataSegmentLength */
673 u8 lun[64];
674 u8 itt[32]; /* initiator id for ping or 0xffffffff */
675 u8 ttt[32]; /* target id for ping or 0xffffffff */
676 u8 cmd_sn[32];
677 u8 exp_stat_sn[32];
678 u8 reserved5[128];
679};
680
681#define PDUBASE_OPCODE_MASK 0x0000003F
682#define PDUBASE_DATALENHI_MASK 0x0000FF00
683#define PDUBASE_DATALENLO_MASK 0xFFFF0000
684
685struct pdu_base {
686 u32 dw[16];
687} __packed;
688
689/**
690 * Pseudo amap definition in which each bit of the actual structure is defined
691 * as a byte: used to calculate offset/shift/mask of each field
692 */
693struct amap_pdu_base {
694 u8 opcode[6];
695 u8 i_bit; /* immediate bit */
696 u8 x_bit; /* reserved, always 0 */
697 u8 reserved1[24]; /* opcode-specific fields */
698 u8 ahs_length[8]; /* length units is 4 byte words */
699 u8 data_len_hi[8];
700 u8 data_len_lo[16]; /* DatasegmentLength */
701 u8 lun[64]; /* lun or opcode-specific fields */
702 u8 itt[32]; /* initiator task tag */
703 u8 reserved4[224];
704};
705
706struct iscsi_target_context_update_wrb {
707 u32 dw[16];
708} __packed;
709
710/**
711 * Pseudo amap definition in which each bit of the actual structure is defined
712 * as a byte: used to calculate offset/shift/mask of each field
713 */
714struct amap_iscsi_target_context_update_wrb {
715 u8 lun[14]; /* DWORD 0 */
716 u8 lt; /* DWORD 0 */
717 u8 invld; /* DWORD 0 */
718 u8 wrb_idx[8]; /* DWORD 0 */
719 u8 dsp; /* DWORD 0 */
720 u8 dmsg; /* DWORD 0 */
721 u8 undr_run; /* DWORD 0 */
722 u8 over_run; /* DWORD 0 */
723 u8 type[4]; /* DWORD 0 */
724 u8 ptr2nextwrb[8]; /* DWORD 1 */
725 u8 max_burst_length[19]; /* DWORD 1 */
726 u8 rsvd0[5]; /* DWORD 1 */
727 u8 rsvd1[15]; /* DWORD 2 */
728 u8 max_send_data_segment_length[17]; /* DWORD 2 */
729 u8 first_burst_length[14]; /* DWORD 3 */
730 u8 rsvd2[2]; /* DWORD 3 */
731 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
732 u8 rsvd3[5]; /* DWORD 3 */
733 u8 session_state[3]; /* DWORD 3 */
734 u8 rsvd4[16]; /* DWORD 4 */
735 u8 tx_jumbo; /* DWORD 4 */
736 u8 hde; /* DWORD 4 */
737 u8 dde; /* DWORD 4 */
738 u8 erl[2]; /* DWORD 4 */
739 u8 domain_id[5]; /* DWORD 4 */
740 u8 mode; /* DWORD 4 */
741 u8 imd; /* DWORD 4 */
742 u8 ir2t; /* DWORD 4 */
743 u8 notpredblq[2]; /* DWORD 4 */
744 u8 compltonack; /* DWORD 4 */
745 u8 stat_sn[32]; /* DWORD 5 */
746 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
747 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
748 u8 pad_addr_hi[32]; /* DWORD 8 */
749 u8 pad_addr_lo[32]; /* DWORD 9 */
750 u8 rsvd5[32]; /* DWORD 10 */
751 u8 rsvd6[32]; /* DWORD 11 */
752 u8 rsvd7[32]; /* DWORD 12 */
753 u8 rsvd8[32]; /* DWORD 13 */
754 u8 rsvd9[32]; /* DWORD 14 */
755 u8 rsvd10[32]; /* DWORD 15 */
756
757} __packed;
758
759struct be_ring {
760 u32 pages; /* queue size in pages */
761 u32 id; /* queue id assigned by beklib */
762 u32 num; /* number of elements in queue */
763 u32 cidx; /* consumer index */
764 u32 pidx; /* producer index -- not used by most rings */
765 u32 item_size; /* size in bytes of one object */
766
767 void *va; /* The virtual address of the ring. This
768 * should be last to allow 32 & 64 bit debugger
769 * extensions to work.
770 */
771};
772
773struct hwi_wrb_context {
774 struct list_head wrb_handle_list;
775 struct list_head wrb_handle_drvr_list;
776 struct wrb_handle **pwrb_handle_base;
777 struct wrb_handle **pwrb_handle_basestd;
778 struct iscsi_wrb *plast_wrb;
779 unsigned short alloc_index;
780 unsigned short free_index;
781 unsigned short wrb_handles_available;
782 unsigned short cid;
783};
784
785struct hwi_controller {
786 struct list_head io_sgl_list;
787 struct list_head eh_sgl_list;
788 struct sgl_handle *psgl_handle_base;
789 unsigned int wrb_mem_index;
790
791 struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
792 struct mcc_wrb *pmcc_wrb_base;
793 struct be_ring default_pdu_hdr;
794 struct be_ring default_pdu_data;
795 struct hwi_context_memory *phwi_ctxt;
796 unsigned short cq_errors[CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN];
797};
798
799enum hwh_type_enum {
800 HWH_TYPE_IO = 1,
801 HWH_TYPE_LOGOUT = 2,
802 HWH_TYPE_TMF = 3,
803 HWH_TYPE_NOP = 4,
804 HWH_TYPE_IO_RD = 5,
805 HWH_TYPE_LOGIN = 11,
806 HWH_TYPE_INVALID = 0xFFFFFFFF
807};
808
809struct wrb_handle {
810 enum hwh_type_enum type;
811 unsigned short wrb_index;
812 unsigned short nxt_wrb_index;
813
814 struct iscsi_task *pio_handle;
815 struct iscsi_wrb *pwrb;
816};
817
818struct hwi_context_memory {
819 struct be_eq_obj be_eq;
820 struct be_queue_info be_cq;
821 struct be_queue_info be_mcc_cq;
822 struct be_queue_info be_mcc;
823
824 struct be_queue_info be_def_hdrq;
825 struct be_queue_info be_def_dataq;
826
827 struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
828 struct be_mcc_wrb_context *pbe_mcc_context;
829
830 struct hwi_async_pdu_context *pasync_ctx;
831};
832
833#endif
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