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[SCSI] be2iscsi: Fix the MCCQ count leakage
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / be2iscsi / be_main.h
CommitLineData
6733b39a 1/**
533c165f 2 * Copyright (C) 2005 - 2013 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
255fa9a3 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
6733b39a
JK		 11 *
12 * Contact Information:
255fa9a3 13 * linux-drivers@emulex.com
6733b39a 14 *
255fa9a3
JK		 15 * Emulex
16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a
JK		 18 */
19
20#ifndef _BEISCSI_MAIN_
21#define _BEISCSI_MAIN_
22
6733b39a
JK		 23#include <linux/kernel.h>
24#include <linux/pci.h>
82c57028 25#include <linux/if_ether.h>
6733b39a 26#include <linux/in.h>
99bc5d55
JSJ		 27#include <linux/ctype.h>
28#include <linux/module.h>
6733b39a
JK		 29#include <scsi/scsi.h>
30#include <scsi/scsi_cmnd.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_host.h>
33#include <scsi/iscsi_proto.h>
34#include <scsi/libiscsi.h>
35#include <scsi/scsi_transport_iscsi.h>
36
37#include "be.h"
6733b39a 38#define DRV_NAME "be2iscsi"
96e58ce0 39#define BUILD_STR "10.0.467.0"
2f635883
JK		 40#define BE_NAME "Emulex OneConnect" \
41 "Open-iSCSI Driver version" BUILD_STR
6733b39a
JK		 42#define DRV_DESC BE_NAME " " "Driver"
43
457ff3b7 44#define BE_VENDOR_ID 0x19A2
139a1b1e 45#define ELX_VENDOR_ID 0x10DF
f98c96b0 46/* DEVICE ID's for BE2 */
6733b39a
JK		 47#define BE_DEVICE_ID1 0x212
48#define OC_DEVICE_ID1 0x702
49#define OC_DEVICE_ID2 0x703
f98c96b0
JK		 50
51/* DEVICE ID's for BE3 */
52#define BE_DEVICE_ID2 0x222
bfead3b2 53#define OC_DEVICE_ID3 0x712
6733b39a 54
139a1b1e
JSJ		 55/* DEVICE ID for SKH */
56#define OC_SKH_ID1 0x722
57
7da50879
JK		 58#define BE2_IO_DEPTH 1024
59#define BE2_MAX_SESSIONS 256
6733b39a 60#define BE2_CMDS_PER_CXN 128
6733b39a
JK		 61#define BE2_TMFS 16
62#define BE2_NOPOUT_REQ 16
6733b39a
JK		 63#define BE2_SGE 32
64#define BE2_DEFPDU_HDR_SZ 64
65#define BE2_DEFPDU_DATA_SZ 8192
6733b39a 66
22abeef0
JSJ		 67#define MAX_CPUS 64
68#define BEISCSI_MAX_NUM_CPUS 7
bf9131cb 69#define OC_SKH_MAX_NUM_CPUS 31
22abeef0 70
22661e25 71#define BEISCSI_VER_STRLEN 32
22abeef0 72
aa359032 73#define BEISCSI_SGLIST_ELEMENTS 30
6733b39a 74
6733b39a 75#define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
e919dee8 76#define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */
15a90fe0 77#define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
6733b39a
JK		 78
79#define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
80#define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
81#define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
82#define BEISCSI_MAX_FRAGS_INIT 192
457ff3b7 83#define BE_NUM_MSIX_ENTRIES 1
e9b91193
JK		 84
85#define MPU_EP_CONTROL 0
86#define MPU_EP_SEMAPHORE 0xac
87#define BE2_SOFT_RESET 0x5c
88#define BE2_PCI_ONLINE0 0xb0
89#define BE2_PCI_ONLINE1 0xb4
90#define BE2_SET_RESET 0x80
91#define BE2_MPU_IRAM_ONLINE 0x00000080
6733b39a
JK		 92
93#define BE_SENSE_INFO_SIZE 258
94#define BE_ISCSI_PDU_HEADER_SIZE 64
95#define BE_MIN_MEM_SIZE 16384
bfead3b2 96#define MAX_CMD_SZ 65536
6733b39a
JK		 97#define IIOC_SCSI_DATA 0x05 /* Write Operation */
98
9aef4200 99#define INVALID_SESS_HANDLE 0xFFFFFFFF
6733b39a 100
bfead3b2
JK		 101#define BE_ADAPTER_UP 0x00000000
102#define BE_ADAPTER_LINK_DOWN 0x00000001
6733b39a
JK		 103/**
104 * hardware needs the async PDU buffers to be posted in multiples of 8
105 * So have atleast 8 of them by default
106 */
107
108#define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
109
110/********* Memory BAR register ************/
457ff3b7 111#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
6733b39a
JK		 112/**
113 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
114 * Disable" may still globally block interrupts in addition to individual
115 * interrupt masks; a mechanism for the device driver to block all interrupts
116 * atomically without having to arbitrate for the PCI Interrupt Disable bit
117 * with the OS.
118 */
119#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
120
121/********* ISR0 Register offset **********/
457ff3b7 122#define CEV_ISR0_OFFSET 0xC18
6733b39a
JK		 123#define CEV_ISR_SIZE 4
124
125/**
126 * Macros for reading/writing a protection domain or CSR registers
127 * in BladeEngine.
128 */
129
130#define DB_TXULP0_OFFSET 0x40
131#define DB_RXULP0_OFFSET 0xA0
132/********* Event Q door bell *************/
133#define DB_EQ_OFFSET DB_CQ_OFFSET
134#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
135/* Clear the interrupt for this eq */
136#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
137/* Must be 1 */
138#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
139/* Number of event entries processed */
140#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
141/* Rearm bit */
142#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
143
144/********* Compl Q door bell *************/
457ff3b7 145#define DB_CQ_OFFSET 0x120
6733b39a
JK		 146#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
147/* Number of event entries processed */
457ff3b7 148#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
6733b39a 149/* Rearm bit */
457ff3b7 150#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
6733b39a
JK		 151
152#define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
153#define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
154 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
155#define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
156 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
157
158#define PAGES_REQUIRED(x) \
159 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
160
8fcfb210
JK		 161#define BEISCSI_MSI_NAME 20 /* size of msi_name string */
162
6733b39a
JK		 163enum be_mem_enum {
164 HWI_MEM_ADDN_CONTEXT,
6733b39a
JK		 165 HWI_MEM_WRB,
166 HWI_MEM_WRBH,
bfead3b2 167 HWI_MEM_SGLH,
6733b39a 168 HWI_MEM_SGE,
15a90fe0 169 HWI_MEM_TEMPLATE_HDR,
457ff3b7 170 HWI_MEM_ASYNC_HEADER_BUF, /* 5 */
6733b39a
JK		 171 HWI_MEM_ASYNC_DATA_BUF,
172 HWI_MEM_ASYNC_HEADER_RING,
bfead3b2 173 HWI_MEM_ASYNC_DATA_RING,
6733b39a 174 HWI_MEM_ASYNC_HEADER_HANDLE,
457ff3b7 175 HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */
6733b39a
JK		 176 HWI_MEM_ASYNC_PDU_CONTEXT,
177 ISCSI_MEM_GLOBAL_HEADER,
bfead3b2 178 SE_MEM_MAX
6733b39a
JK		 179};
180
181struct be_bus_address32 {
182 unsigned int address_lo;
183 unsigned int address_hi;
184};
185
186struct be_bus_address64 {
187 unsigned long long address;
188};
189
190struct be_bus_address {
191 union {
192 struct be_bus_address32 a32;
193 struct be_bus_address64 a64;
194 } u;
195};
196
197struct mem_array {
198 struct be_bus_address bus_address; /* Bus address of location */
199 void *virtual_address; /* virtual address to the location */
200 unsigned int size; /* Size required by memory block */
201};
202
203struct be_mem_descriptor {
204 unsigned int index; /* Index of this memory parameter */
205 unsigned int category; /* type indicates cached/non-cached */
206 unsigned int num_elements; /* number of elements in this
207 * descriptor
208 */
209 unsigned int alignment_mask; /* Alignment mask for this block */
210 unsigned int size_in_bytes; /* Size required by memory block */
211 struct mem_array *mem_array;
212};
213
214struct sgl_handle {
215 unsigned int sgl_index;
bfead3b2
JK		 216 unsigned int type;
217 unsigned int cid;
218 struct iscsi_task *task;
6733b39a
JK		 219 struct iscsi_sge *pfrag;
220};
221
222struct hba_parameters {
223 unsigned int ios_per_ctrl;
224 unsigned int cxns_per_ctrl;
225 unsigned int asyncpdus_per_ctrl;
226 unsigned int icds_per_ctrl;
227 unsigned int num_sge_per_io;
228 unsigned int defpdu_hdr_sz;
229 unsigned int defpdu_data_sz;
230 unsigned int num_cq_entries;
231 unsigned int num_eq_entries;
232 unsigned int wrbs_per_cxn;
233 unsigned int crashmode;
234 unsigned int hba_num;
235
236 unsigned int mgmt_ws_sz;
237 unsigned int hwi_ws_sz;
238
239 unsigned int eto;
240 unsigned int ldto;
241
242 unsigned int dbg_flags;
243 unsigned int num_cxn;
244
245 unsigned int eq_timer;
246 /**
247 * These are calculated from other params. They're here
248 * for debug purposes
249 */
250 unsigned int num_mcc_pages;
251 unsigned int num_mcc_cq_pages;
252 unsigned int num_cq_pages;
253 unsigned int num_eq_pages;
254
255 unsigned int num_async_pdu_buf_pages;
256 unsigned int num_async_pdu_buf_sgl_pages;
257 unsigned int num_async_pdu_buf_cq_pages;
258
259 unsigned int num_async_pdu_hdr_pages;
260 unsigned int num_async_pdu_hdr_sgl_pages;
261 unsigned int num_async_pdu_hdr_cq_pages;
262
263 unsigned int num_sge;
264};
265
4183122d
JK		 266struct invalidate_command_table {
267 unsigned short icd;
268 unsigned short cid;
269} __packed;
270
2c9dfd36
JK		 271#define chip_be2(phba) (phba->generation == BE_GEN2)
272#define chip_be3_r(phba) (phba->generation == BE_GEN3)
273#define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
6733b39a
JK		 274struct beiscsi_hba {
275 struct hba_parameters params;
276 struct hwi_controller *phwi_ctrlr;
277 unsigned int mem_req[SE_MEM_MAX];
278 /* PCI BAR mapped addresses */
279 u8 __iomem *csr_va; /* CSR */
280 u8 __iomem *db_va; /* Door Bell */
281 u8 __iomem *pci_va; /* PCI Config */
282 struct be_bus_address csr_pa; /* CSR */
283 struct be_bus_address db_pa; /* CSR */
284 struct be_bus_address pci_pa; /* CSR */
285 /* PCI representation of our HBA */
286 struct pci_dev *pcidev;
6733b39a 287 unsigned short asic_revision;
bfead3b2
JK		 288 unsigned int num_cpus;
289 unsigned int nxt_cqid;
22abeef0
JSJ		 290 struct msix_entry msix_entries[MAX_CPUS];
291 char *msi_name[MAX_CPUS];
bfead3b2 292 bool msix_enabled;
6733b39a
JK		 293 struct be_mem_descriptor *init_mem;
294
295 unsigned short io_sgl_alloc_index;
296 unsigned short io_sgl_free_index;
297 unsigned short io_sgl_hndl_avbl;
298 struct sgl_handle **io_sgl_hndl_base;
bfead3b2 299 struct sgl_handle **sgl_hndl_array;
6733b39a
JK		 300
301 unsigned short eh_sgl_alloc_index;
302 unsigned short eh_sgl_free_index;
303 unsigned short eh_sgl_hndl_avbl;
304 struct sgl_handle **eh_sgl_hndl_base;
305 spinlock_t io_sgl_lock;
306 spinlock_t mgmt_sgl_lock;
307 spinlock_t isr_lock;
308 unsigned int age;
309 unsigned short avlbl_cids;
310 unsigned short cid_alloc;
311 unsigned short cid_free;
6733b39a 312 struct list_head hba_queue;
a7909b39
JK		 313#define BE_MAX_SESSION 2048
314#define BE_SET_CID_TO_CRI(cri_index, cid) \
315 (phba->cid_to_cri_map[cid] = cri_index)
316#define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
317 unsigned short cid_to_cri_map[BE_MAX_SESSION];
6733b39a
JK		 318 unsigned short *cid_array;
319 struct iscsi_endpoint **ep_array;
a7909b39 320 struct beiscsi_conn **conn_table;
c7acc5b8 321 struct iscsi_boot_kset *boot_kset;
6733b39a 322 struct Scsi_Host *shost;
0e43895e
MC		 323 struct iscsi_iface *ipv4_iface;
324 struct iscsi_iface *ipv6_iface;
6733b39a
JK		 325 struct {
326 /**
327 * group together since they are used most frequently
328 * for cid to cri conversion
329 */
330 unsigned int iscsi_cid_start;
331 unsigned int phys_port;
332
333 unsigned int isr_offset;
334 unsigned int iscsi_icd_start;
335 unsigned int iscsi_cid_count;
336 unsigned int iscsi_icd_count;
337 unsigned int pci_function;
338
339 unsigned short cid_alloc;
340 unsigned short cid_free;
341 unsigned short avlbl_cids;
bfead3b2 342 unsigned short iscsi_features;
6733b39a
JK		 343 spinlock_t cid_lock;
344 } fw_config;
345
e175defe
JSJ		 346 unsigned int state;
347 bool fw_timeout;
348 bool ue_detected;
349 struct delayed_work beiscsi_hw_check_task;
350
6733b39a 351 u8 mac_address[ETH_ALEN];
22661e25 352 char fw_ver_str[BEISCSI_VER_STRLEN];
6733b39a
JK		 353 char wq_name[20];
354 struct workqueue_struct *wq; /* The actuak work queue */
6733b39a 355 struct be_ctrl_info ctrl;
f98c96b0 356 unsigned int generation;
0e43895e 357 unsigned int interface_handle;
c7acc5b8 358 struct mgmt_session_info boot_sess;
4183122d
JK		 359 struct invalidate_command_table inv_tbl[128];
360
99bc5d55 361 unsigned int attr_log_enable;
09a1093a
JSJ		 362 int (*iotask_fn)(struct iscsi_task *,
363 struct scatterlist *sg,
364 uint32_t num_sg, uint32_t xferlen,
365 uint32_t writedir);
6733b39a
JK		 366};
367
b8b9e1b8
JK		 368struct beiscsi_session {
369 struct pci_pool *bhs_pool;
370};
371
6733b39a
JK		 372/**
373 * struct beiscsi_conn - iscsi connection structure
374 */
375struct beiscsi_conn {
376 struct iscsi_conn *conn;
377 struct beiscsi_hba *phba;
378 u32 exp_statsn;
379 u32 beiscsi_conn_cid;
380 struct beiscsi_endpoint *ep;
381 unsigned short login_in_progress;
d2cecf0d 382 struct wrb_handle *plogin_wrb_handle;
6733b39a 383 struct sgl_handle *plogin_sgl_handle;
b8b9e1b8 384 struct beiscsi_session *beiscsi_sess;
bfead3b2 385 struct iscsi_task *task;
6733b39a
JK		 386};
387
388/* This structure is used by the chip */
389struct pdu_data_out {
390 u32 dw[12];
391};
392/**
393 * Pseudo amap definition in which each bit of the actual structure is defined
394 * as a byte: used to calculate offset/shift/mask of each field
395 */
396struct amap_pdu_data_out {
397 u8 opcode[6]; /* opcode */
398 u8 rsvd0[2]; /* should be 0 */
399 u8 rsvd1[7];
400 u8 final_bit; /* F bit */
401 u8 rsvd2[16];
402 u8 ahs_length[8]; /* no AHS */
403 u8 data_len_hi[8];
404 u8 data_len_lo[16]; /* DataSegmentLength */
405 u8 lun[64];
406 u8 itt[32]; /* ITT; initiator task tag */
407 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
408 u8 rsvd3[32];
409 u8 exp_stat_sn[32];
410 u8 rsvd4[32];
411 u8 data_sn[32];
412 u8 buffer_offset[32];
413 u8 rsvd5[32];
414};
415
416struct be_cmd_bhs {
12352183 417 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 418 unsigned char pad1[16];
419 struct pdu_data_out iscsi_data_pdu;
420 unsigned char pad2[BE_SENSE_INFO_SIZE -
421 sizeof(struct pdu_data_out)];
422};
423
424struct beiscsi_io_task {
425 struct wrb_handle *pwrb_handle;
426 struct sgl_handle *psgl_handle;
427 struct beiscsi_conn *conn;
428 struct scsi_cmnd *scsi_cmnd;
429 unsigned int cmd_sn;
430 unsigned int flags;
431 unsigned short cid;
432 unsigned short header_len;
bfead3b2 433 itt_t libiscsi_itt;
6733b39a
JK		 434 struct be_cmd_bhs *cmd_bhs;
435 struct be_bus_address bhs_pa;
436 unsigned short bhs_len;
d629c471
JSJ		 437 dma_addr_t mtask_addr;
438 uint32_t mtask_data_count;
09a1093a 439 uint8_t wrb_type;
6733b39a
JK		 440};
441
442struct be_nonio_bhs {
443 struct iscsi_hdr iscsi_hdr;
444 unsigned char pad1[16];
445 struct pdu_data_out iscsi_data_pdu;
446 unsigned char pad2[BE_SENSE_INFO_SIZE -
447 sizeof(struct pdu_data_out)];
448};
449
450struct be_status_bhs {
12352183 451 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 452 unsigned char pad1[16];
453 /**
454 * The plus 2 below is to hold the sense info length that gets
455 * DMA'ed by RxULP
456 */
457 unsigned char sense_info[BE_SENSE_INFO_SIZE];
458};
459
460struct iscsi_sge {
461 u32 dw[4];
462};
463
464/**
465 * Pseudo amap definition in which each bit of the actual structure is defined
466 * as a byte: used to calculate offset/shift/mask of each field
467 */
468struct amap_iscsi_sge {
469 u8 addr_hi[32];
470 u8 addr_lo[32];
471 u8 sge_offset[22]; /* DWORD 2 */
472 u8 rsvd0[9]; /* DWORD 2 */
473 u8 last_sge; /* DWORD 2 */
474 u8 len[17]; /* DWORD 3 */
475 u8 rsvd1[15]; /* DWORD 3 */
476};
477
478struct beiscsi_offload_params {
479 u32 dw[5];
480};
481
482#define OFFLD_PARAMS_ERL 0x00000003
483#define OFFLD_PARAMS_DDE 0x00000004
484#define OFFLD_PARAMS_HDE 0x00000008
485#define OFFLD_PARAMS_IR2T 0x00000010
486#define OFFLD_PARAMS_IMD 0x00000020
acb9693c
JSJ		 487#define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040
488#define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080
489#define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
6733b39a
JK		 490
491/**
492 * Pseudo amap definition in which each bit of the actual structure is defined
493 * as a byte: used to calculate offset/shift/mask of each field
494 */
495struct amap_beiscsi_offload_params {
496 u8 max_burst_length[32];
497 u8 max_send_data_segment_length[32];
498 u8 first_burst_length[32];
499 u8 erl[2];
500 u8 dde[1];
501 u8 hde[1];
502 u8 ir2t[1];
503 u8 imd[1];
acb9693c
JSJ		 504 u8 data_seq_inorder[1];
505 u8 pdu_seq_inorder[1];
506 u8 max_r2t[16];
507 u8 pad[8];
6733b39a
JK		 508 u8 exp_statsn[32];
509};
510
511/* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
512 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
513
514struct async_pdu_handle {
515 struct list_head link;
516 struct be_bus_address pa;
517 void *pbuffer;
518 unsigned int consumed;
519 unsigned char index;
520 unsigned char is_header;
521 unsigned short cri;
522 unsigned long buffer_len;
523};
524
525struct hwi_async_entry {
526 struct {
527 unsigned char hdr_received;
528 unsigned char hdr_len;
529 unsigned short bytes_received;
530 unsigned int bytes_needed;
531 struct list_head list;
532 } wait_queue;
533
534 struct list_head header_busy_list;
535 struct list_head data_busy_list;
536};
537
6733b39a
JK		 538struct hwi_async_pdu_context {
539 struct {
540 struct be_bus_address pa_base;
541 void *va_base;
542 void *ring_base;
543 struct async_pdu_handle *handle_base;
544
545 unsigned int host_write_ptr;
546 unsigned int ep_read_ptr;
547 unsigned int writables;
548
549 unsigned int free_entries;
550 unsigned int busy_entries;
6733b39a
JK		 551
552 struct list_head free_list;
553 } async_header;
554
555 struct {
556 struct be_bus_address pa_base;
557 void *va_base;
558 void *ring_base;
559 struct async_pdu_handle *handle_base;
560
561 unsigned int host_write_ptr;
562 unsigned int ep_read_ptr;
563 unsigned int writables;
564
565 unsigned int free_entries;
566 unsigned int busy_entries;
6733b39a 567 struct list_head free_list;
6733b39a
JK		 568 } async_data;
569
dc63aac6
JK		 570 unsigned int buffer_size;
571 unsigned int num_entries;
572
6733b39a
JK		 573 /**
574 * This is a varying size list! Do not add anything
575 * after this entry!!
576 */
a7909b39 577 struct hwi_async_entry *async_entry;
6733b39a
JK		 578};
579
580#define PDUCQE_CODE_MASK 0x0000003F
581#define PDUCQE_DPL_MASK 0xFFFF0000
582#define PDUCQE_INDEX_MASK 0x0000FFFF
583
584struct i_t_dpdu_cqe {
585 u32 dw[4];
586} __packed;
587
588/**
589 * Pseudo amap definition in which each bit of the actual structure is defined
590 * as a byte: used to calculate offset/shift/mask of each field
591 */
592struct amap_i_t_dpdu_cqe {
593 u8 db_addr_hi[32];
594 u8 db_addr_lo[32];
595 u8 code[6];
596 u8 cid[10];
597 u8 dpl[16];
598 u8 index[16];
599 u8 num_cons[10];
600 u8 rsvd0[4];
601 u8 final;
602 u8 valid;
603} __packed;
604
73133261
JSJ		 605struct amap_i_t_dpdu_cqe_v2 {
606 u8 db_addr_hi[32]; /* DWORD 0 */
607 u8 db_addr_lo[32]; /* DWORD 1 */
608 u8 code[6]; /* DWORD 2 */
609 u8 num_cons; /* DWORD 2*/
610 u8 rsvd0[8]; /* DWORD 2 */
611 u8 dpl[17]; /* DWORD 2 */
612 u8 index[16]; /* DWORD 3 */
613 u8 cid[13]; /* DWORD 3 */
614 u8 rsvd1; /* DWORD 3 */
615 u8 final; /* DWORD 3 */
616 u8 valid; /* DWORD 3 */
617} __packed;
618
6733b39a
JK		 619#define CQE_VALID_MASK 0x80000000
620#define CQE_CODE_MASK 0x0000003F
621#define CQE_CID_MASK 0x0000FFC0
622
623#define EQE_VALID_MASK 0x00000001
624#define EQE_MAJORCODE_MASK 0x0000000E
625#define EQE_RESID_MASK 0xFFFF0000
626
627struct be_eq_entry {
628 u32 dw[1];
629} __packed;
630
631/**
632 * Pseudo amap definition in which each bit of the actual structure is defined
633 * as a byte: used to calculate offset/shift/mask of each field
634 */
635struct amap_eq_entry {
636 u8 valid; /* DWORD 0 */
637 u8 major_code[3]; /* DWORD 0 */
638 u8 minor_code[12]; /* DWORD 0 */
639 u8 resource_id[16]; /* DWORD 0 */
640
641} __packed;
642
643struct cq_db {
644 u32 dw[1];
645} __packed;
646
647/**
648 * Pseudo amap definition in which each bit of the actual structure is defined
649 * as a byte: used to calculate offset/shift/mask of each field
650 */
651struct amap_cq_db {
652 u8 qid[10];
653 u8 event[1];
654 u8 rsvd0[5];
655 u8 num_popped[13];
656 u8 rearm[1];
657 u8 rsvd1[2];
658} __packed;
659
660void beiscsi_process_eq(struct beiscsi_hba *phba);
661
6733b39a
JK		 662struct iscsi_wrb {
663 u32 dw[16];
664} __packed;
665
666#define WRB_TYPE_MASK 0xF0000000
09a1093a
JSJ		 667#define SKH_WRB_TYPE_OFFSET 27
668#define BE_WRB_TYPE_OFFSET 28
669
670#define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
671 (pwrb->dw[0] |= (wrb_type << type_offset))
6733b39a
JK		 672
673/**
674 * Pseudo amap definition in which each bit of the actual structure is defined
675 * as a byte: used to calculate offset/shift/mask of each field
676 */
677struct amap_iscsi_wrb {
678 u8 lun[14]; /* DWORD 0 */
679 u8 lt; /* DWORD 0 */
680 u8 invld; /* DWORD 0 */
681 u8 wrb_idx[8]; /* DWORD 0 */
682 u8 dsp; /* DWORD 0 */
683 u8 dmsg; /* DWORD 0 */
684 u8 undr_run; /* DWORD 0 */
685 u8 over_run; /* DWORD 0 */
686 u8 type[4]; /* DWORD 0 */
687 u8 ptr2nextwrb[8]; /* DWORD 1 */
688 u8 r2t_exp_dtl[24]; /* DWORD 1 */
689 u8 sgl_icd_idx[12]; /* DWORD 2 */
690 u8 rsvd0[20]; /* DWORD 2 */
691 u8 exp_data_sn[32]; /* DWORD 3 */
692 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
693 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
694 u8 cmdsn_itt[32]; /* DWORD 6 */
695 u8 dif_ref_tag[32]; /* DWORD 7 */
696 u8 sge0_addr_hi[32]; /* DWORD 8 */
697 u8 sge0_addr_lo[32]; /* DWORD 9 */
698 u8 sge0_offset[22]; /* DWORD 10 */
699 u8 pbs; /* DWORD 10 */
700 u8 dif_mode[2]; /* DWORD 10 */
701 u8 rsvd1[6]; /* DWORD 10 */
702 u8 sge0_last; /* DWORD 10 */
703 u8 sge0_len[17]; /* DWORD 11 */
704 u8 dif_meta_tag[14]; /* DWORD 11 */
705 u8 sge0_in_ddr; /* DWORD 11 */
706 u8 sge1_addr_hi[32]; /* DWORD 12 */
707 u8 sge1_addr_lo[32]; /* DWORD 13 */
708 u8 sge1_r2t_offset[22]; /* DWORD 14 */
709 u8 rsvd2[9]; /* DWORD 14 */
710 u8 sge1_last; /* DWORD 14 */
711 u8 sge1_len[17]; /* DWORD 15 */
712 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
713 u8 rsvd3[2]; /* DWORD 15 */
714 u8 sge1_in_ddr; /* DWORD 15 */
715
716} __packed;
717
09a1093a
JSJ		 718struct amap_iscsi_wrb_v2 {
719 u8 r2t_exp_dtl[25]; /* DWORD 0 */
720 u8 rsvd0[2]; /* DWORD 0*/
721 u8 type[5]; /* DWORD 0 */
722 u8 ptr2nextwrb[8]; /* DWORD 1 */
723 u8 wrb_idx[8]; /* DWORD 1 */
724 u8 lun[16]; /* DWORD 1 */
725 u8 sgl_idx[16]; /* DWORD 2 */
726 u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
727 u8 exp_data_sn[32]; /* DWORD 3 */
728 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
729 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
730 u8 cq_id[16]; /* DWORD 6 */
731 u8 rsvd1[16]; /* DWORD 6 */
732 u8 cmdsn_itt[32]; /* DWORD 7 */
733 u8 sge0_addr_hi[32]; /* DWORD 8 */
734 u8 sge0_addr_lo[32]; /* DWORD 9 */
735 u8 sge0_offset[24]; /* DWORD 10 */
736 u8 rsvd2[7]; /* DWORD 10 */
737 u8 sge0_last; /* DWORD 10 */
738 u8 sge0_len[17]; /* DWORD 11 */
739 u8 rsvd3[7]; /* DWORD 11 */
740 u8 diff_enbl; /* DWORD 11 */
741 u8 u_run; /* DWORD 11 */
742 u8 o_run; /* DWORD 11 */
743 u8 invalid; /* DWORD 11 */
744 u8 dsp; /* DWORD 11 */
745 u8 dmsg; /* DWORD 11 */
746 u8 rsvd4; /* DWORD 11 */
747 u8 lt; /* DWORD 11 */
748 u8 sge1_addr_hi[32]; /* DWORD 12 */
749 u8 sge1_addr_lo[32]; /* DWORD 13 */
750 u8 sge1_r2t_offset[24]; /* DWORD 14 */
751 u8 rsvd5[7]; /* DWORD 14 */
752 u8 sge1_last; /* DWORD 14 */
753 u8 sge1_len[17]; /* DWORD 15 */
754 u8 rsvd6[15]; /* DWORD 15 */
755} __packed;
756
757
d5431488 758struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
6733b39a
JK		 759void
760free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
761
756d29c8 762void beiscsi_process_all_cqs(struct work_struct *work);
4a4a11b9
JK		 763void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
764 struct iscsi_task *task);
756d29c8 765
7a158003
JSJ		 766static inline bool beiscsi_error(struct beiscsi_hba *phba)
767{
768 return phba->ue_detected || phba->fw_timeout;
769}
770
6733b39a
JK		 771struct pdu_nop_out {
772 u32 dw[12];
773};
774
775/**
776 * Pseudo amap definition in which each bit of the actual structure is defined
777 * as a byte: used to calculate offset/shift/mask of each field
778 */
779struct amap_pdu_nop_out {
780 u8 opcode[6]; /* opcode 0x00 */
781 u8 i_bit; /* I Bit */
782 u8 x_bit; /* reserved; should be 0 */
783 u8 fp_bit_filler1[7];
784 u8 f_bit; /* always 1 */
785 u8 reserved1[16];
786 u8 ahs_length[8]; /* no AHS */
787 u8 data_len_hi[8];
788 u8 data_len_lo[16]; /* DataSegmentLength */
789 u8 lun[64];
790 u8 itt[32]; /* initiator id for ping or 0xffffffff */
791 u8 ttt[32]; /* target id for ping or 0xffffffff */
792 u8 cmd_sn[32];
793 u8 exp_stat_sn[32];
794 u8 reserved5[128];
795};
796
797#define PDUBASE_OPCODE_MASK 0x0000003F
798#define PDUBASE_DATALENHI_MASK 0x0000FF00
799#define PDUBASE_DATALENLO_MASK 0xFFFF0000
800
801struct pdu_base {
802 u32 dw[16];
803} __packed;
804
805/**
806 * Pseudo amap definition in which each bit of the actual structure is defined
807 * as a byte: used to calculate offset/shift/mask of each field
808 */
809struct amap_pdu_base {
810 u8 opcode[6];
811 u8 i_bit; /* immediate bit */
812 u8 x_bit; /* reserved, always 0 */
813 u8 reserved1[24]; /* opcode-specific fields */
814 u8 ahs_length[8]; /* length units is 4 byte words */
815 u8 data_len_hi[8];
816 u8 data_len_lo[16]; /* DatasegmentLength */
817 u8 lun[64]; /* lun or opcode-specific fields */
818 u8 itt[32]; /* initiator task tag */
819 u8 reserved4[224];
820};
821
822struct iscsi_target_context_update_wrb {
823 u32 dw[16];
824} __packed;
825
826/**
827 * Pseudo amap definition in which each bit of the actual structure is defined
828 * as a byte: used to calculate offset/shift/mask of each field
829 */
acb9693c 830#define BE_TGT_CTX_UPDT_CMD 0x07
6733b39a
JK		 831struct amap_iscsi_target_context_update_wrb {
832 u8 lun[14]; /* DWORD 0 */
833 u8 lt; /* DWORD 0 */
834 u8 invld; /* DWORD 0 */
835 u8 wrb_idx[8]; /* DWORD 0 */
836 u8 dsp; /* DWORD 0 */
837 u8 dmsg; /* DWORD 0 */
838 u8 undr_run; /* DWORD 0 */
839 u8 over_run; /* DWORD 0 */
840 u8 type[4]; /* DWORD 0 */
841 u8 ptr2nextwrb[8]; /* DWORD 1 */
842 u8 max_burst_length[19]; /* DWORD 1 */
843 u8 rsvd0[5]; /* DWORD 1 */
844 u8 rsvd1[15]; /* DWORD 2 */
845 u8 max_send_data_segment_length[17]; /* DWORD 2 */
846 u8 first_burst_length[14]; /* DWORD 3 */
847 u8 rsvd2[2]; /* DWORD 3 */
848 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
849 u8 rsvd3[5]; /* DWORD 3 */
850 u8 session_state[3]; /* DWORD 3 */
851 u8 rsvd4[16]; /* DWORD 4 */
852 u8 tx_jumbo; /* DWORD 4 */
853 u8 hde; /* DWORD 4 */
854 u8 dde; /* DWORD 4 */
855 u8 erl[2]; /* DWORD 4 */
856 u8 domain_id[5]; /* DWORD 4 */
857 u8 mode; /* DWORD 4 */
858 u8 imd; /* DWORD 4 */
859 u8 ir2t; /* DWORD 4 */
860 u8 notpredblq[2]; /* DWORD 4 */
861 u8 compltonack; /* DWORD 4 */
862 u8 stat_sn[32]; /* DWORD 5 */
863 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
864 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
865 u8 pad_addr_hi[32]; /* DWORD 8 */
866 u8 pad_addr_lo[32]; /* DWORD 9 */
867 u8 rsvd5[32]; /* DWORD 10 */
868 u8 rsvd6[32]; /* DWORD 11 */
869 u8 rsvd7[32]; /* DWORD 12 */
870 u8 rsvd8[32]; /* DWORD 13 */
871 u8 rsvd9[32]; /* DWORD 14 */
872 u8 rsvd10[32]; /* DWORD 15 */
873
874} __packed;
875
acb9693c
JSJ		 876#define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024)
877#define BEISCSI_MAX_CXNS 1
878struct amap_iscsi_target_context_update_wrb_v2 {
879 u8 max_burst_length[24]; /* DWORD 0 */
880 u8 rsvd0[3]; /* DWORD 0 */
881 u8 type[5]; /* DWORD 0 */
882 u8 ptr2nextwrb[8]; /* DWORD 1 */
883 u8 wrb_idx[8]; /* DWORD 1 */
884 u8 rsvd1[16]; /* DWORD 1 */
885 u8 max_send_data_segment_length[24]; /* DWORD 2 */
886 u8 rsvd2[8]; /* DWORD 2 */
887 u8 first_burst_length[24]; /* DWORD 3 */
888 u8 rsvd3[8]; /* DOWRD 3 */
889 u8 max_r2t[16]; /* DWORD 4 */
890 u8 rsvd4[10]; /* DWORD 4 */
891 u8 hde; /* DWORD 4 */
892 u8 dde; /* DWORD 4 */
893 u8 erl[2]; /* DWORD 4 */
894 u8 imd; /* DWORD 4 */
895 u8 ir2t; /* DWORD 4 */
896 u8 stat_sn[32]; /* DWORD 5 */
897 u8 rsvd5[32]; /* DWORD 6 */
898 u8 rsvd6[32]; /* DWORD 7 */
899 u8 max_recv_dataseg_len[24]; /* DWORD 8 */
900 u8 rsvd7[8]; /* DWORD 8 */
901 u8 rsvd8[32]; /* DWORD 9 */
902 u8 rsvd9[32]; /* DWORD 10 */
903 u8 max_cxns[16]; /* DWORD 11 */
904 u8 rsvd10[11]; /* DWORD 11*/
905 u8 invld; /* DWORD 11 */
906 u8 rsvd11;/* DWORD 11*/
907 u8 dmsg; /* DWORD 11 */
908 u8 data_seq_inorder; /* DWORD 11 */
909 u8 pdu_seq_inorder; /* DWORD 11 */
910 u8 rsvd12[32]; /*DWORD 12 */
911 u8 rsvd13[32]; /* DWORD 13 */
912 u8 rsvd14[32]; /* DWORD 14 */
913 u8 rsvd15[32]; /* DWORD 15 */
914} __packed;
915
916
6733b39a
JK		 917struct be_ring {
918 u32 pages; /* queue size in pages */
919 u32 id; /* queue id assigned by beklib */
920 u32 num; /* number of elements in queue */
921 u32 cidx; /* consumer index */
922 u32 pidx; /* producer index -- not used by most rings */
923 u32 item_size; /* size in bytes of one object */
924
925 void *va; /* The virtual address of the ring. This
926 * should be last to allow 32 & 64 bit debugger
927 * extensions to work.
928 */
929};
930
931struct hwi_wrb_context {
932 struct list_head wrb_handle_list;
933 struct list_head wrb_handle_drvr_list;
934 struct wrb_handle **pwrb_handle_base;
935 struct wrb_handle **pwrb_handle_basestd;
936 struct iscsi_wrb *plast_wrb;
937 unsigned short alloc_index;
938 unsigned short free_index;
939 unsigned short wrb_handles_available;
940 unsigned short cid;
941};
942
943struct hwi_controller {
944 struct list_head io_sgl_list;
945 struct list_head eh_sgl_list;
946 struct sgl_handle *psgl_handle_base;
947 unsigned int wrb_mem_index;
948
a7909b39 949 struct hwi_wrb_context *wrb_context;
6733b39a
JK		 950 struct mcc_wrb *pmcc_wrb_base;
951 struct be_ring default_pdu_hdr;
952 struct be_ring default_pdu_data;
953 struct hwi_context_memory *phwi_ctxt;
6733b39a
JK		 954};
955
956enum hwh_type_enum {
957 HWH_TYPE_IO = 1,
958 HWH_TYPE_LOGOUT = 2,
959 HWH_TYPE_TMF = 3,
960 HWH_TYPE_NOP = 4,
961 HWH_TYPE_IO_RD = 5,
962 HWH_TYPE_LOGIN = 11,
963 HWH_TYPE_INVALID = 0xFFFFFFFF
964};
965
966struct wrb_handle {
967 enum hwh_type_enum type;
968 unsigned short wrb_index;
969 unsigned short nxt_wrb_index;
970
971 struct iscsi_task *pio_handle;
972 struct iscsi_wrb *pwrb;
973};
974
975struct hwi_context_memory {
bfead3b2
JK		 976 /* Adaptive interrupt coalescing (AIC) info */
977 u16 min_eqd; /* in usecs */
978 u16 max_eqd; /* in usecs */
979 u16 cur_eqd; /* in usecs */
980 struct be_eq_obj be_eq[MAX_CPUS];
22abeef0 981 struct be_queue_info be_cq[MAX_CPUS - 1];
6733b39a
JK		 982
983 struct be_queue_info be_def_hdrq;
984 struct be_queue_info be_def_dataq;
985
a7909b39 986 struct be_queue_info *be_wrbq;
6733b39a
JK		 987 struct hwi_async_pdu_context *pasync_ctx;
988};
989
99bc5d55
JSJ		 990/* Logging related definitions */
991#define BEISCSI_LOG_INIT 0x0001 /* Initialization events */
992#define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */
993#define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */
994#define BEISCSI_LOG_EH 0x0008 /* Error Handler */
995#define BEISCSI_LOG_IO 0x0010 /* IO Code Path */
996#define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */
997
998#define beiscsi_log(phba, level, mask, fmt, arg...) \
999do { \
1000 uint32_t log_value = phba->attr_log_enable; \
1001 if (((mask) & log_value) || (level[1] <= '3')) \
1002 shost_printk(level, phba->shost, \
1003 fmt, __LINE__, ##arg); \
1004} while (0)
1005
6733b39a 1006#endif
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