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[SCSI] bfa: fix endianess issue for firmware stats
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / bfa / bfa_ioc.c
CommitLineData
7725ccfd 1/*
a36c61f9 2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
7725ccfd
JH		 3 * All rights reserved
4 * www.brocade.com
5 *
6 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License (GPL) Version 2 as
10 * published by the Free Software Foundation
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 */
17
f16a1750 18#include "bfad_drv.h"
7826f304 19#include "bfad_im.h"
a36c61f9 20#include "bfa_ioc.h"
11189208 21#include "bfi_reg.h"
a36c61f9
KG		 22#include "bfa_defs.h"
23#include "bfa_defs_svc.h"
7725ccfd 24
7af074dc 25BFA_TRC_FILE(CNA, IOC);
7725ccfd 26
5fbe25c7 27/*
7725ccfd
JH		 28 * IOC local definitions
29 */
a36c61f9
KG		 30#define BFA_IOC_TOV 3000 /* msecs */
31#define BFA_IOC_HWSEM_TOV 500 /* msecs */
32#define BFA_IOC_HB_TOV 500 /* msecs */
a36c61f9 33#define BFA_IOC_TOV_RECOVER BFA_IOC_HB_TOV
775c7742 34#define BFA_IOC_POLL_TOV BFA_TIMER_FREQ
7725ccfd
JH		 35
36#define bfa_ioc_timer_start(__ioc) \
37 bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->ioc_timer, \
38 bfa_ioc_timeout, (__ioc), BFA_IOC_TOV)
39#define bfa_ioc_timer_stop(__ioc) bfa_timer_stop(&(__ioc)->ioc_timer)
40
a36c61f9
KG		 41#define bfa_hb_timer_start(__ioc) \
42 bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->hb_timer, \
43 bfa_ioc_hb_check, (__ioc), BFA_IOC_HB_TOV)
44#define bfa_hb_timer_stop(__ioc) bfa_timer_stop(&(__ioc)->hb_timer)
45
7725ccfd 46#define BFA_DBG_FWTRC_OFF(_fn) (BFI_IOC_TRC_OFF + BFA_DBG_FWTRC_LEN * (_fn))
7725ccfd 47
5fbe25c7 48/*
0a20de44
KG		 49 * Asic specific macros : see bfa_hw_cb.c and bfa_hw_ct.c for details.
50 */
51
a36c61f9 52#define bfa_ioc_firmware_lock(__ioc) \
0a20de44 53 ((__ioc)->ioc_hwif->ioc_firmware_lock(__ioc))
a36c61f9 54#define bfa_ioc_firmware_unlock(__ioc) \
0a20de44 55 ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc))
0a20de44
KG		 56#define bfa_ioc_reg_init(__ioc) ((__ioc)->ioc_hwif->ioc_reg_init(__ioc))
57#define bfa_ioc_map_port(__ioc) ((__ioc)->ioc_hwif->ioc_map_port(__ioc))
f1d584d7
KG		 58#define bfa_ioc_notify_fail(__ioc) \
59 ((__ioc)->ioc_hwif->ioc_notify_fail(__ioc))
45d7f0cc
JH		 60#define bfa_ioc_sync_start(__ioc) \
61 ((__ioc)->ioc_hwif->ioc_sync_start(__ioc))
f1d584d7
KG		 62#define bfa_ioc_sync_join(__ioc) \
63 ((__ioc)->ioc_hwif->ioc_sync_join(__ioc))
64#define bfa_ioc_sync_leave(__ioc) \
65 ((__ioc)->ioc_hwif->ioc_sync_leave(__ioc))
66#define bfa_ioc_sync_ack(__ioc) \
67 ((__ioc)->ioc_hwif->ioc_sync_ack(__ioc))
68#define bfa_ioc_sync_complete(__ioc) \
69 ((__ioc)->ioc_hwif->ioc_sync_complete(__ioc))
c679b599
VMG		 70#define bfa_ioc_set_cur_ioc_fwstate(__ioc, __fwstate) \
71 ((__ioc)->ioc_hwif->ioc_set_fwstate(__ioc, __fwstate))
72#define bfa_ioc_get_cur_ioc_fwstate(__ioc) \
73 ((__ioc)->ioc_hwif->ioc_get_fwstate(__ioc))
74#define bfa_ioc_set_alt_ioc_fwstate(__ioc, __fwstate) \
75 ((__ioc)->ioc_hwif->ioc_set_alt_fwstate(__ioc, __fwstate))
76#define bfa_ioc_get_alt_ioc_fwstate(__ioc) \
77 ((__ioc)->ioc_hwif->ioc_get_alt_fwstate(__ioc))
a36c61f9
KG		 78
79#define bfa_ioc_mbox_cmd_pending(__ioc) \
80 (!list_empty(&((__ioc)->mbox_mod.cmd_q)) || \
53440260 81 readl((__ioc)->ioc_regs.hfn_mbox_cmd))
a36c61f9
KG		 82
83bfa_boolean_t bfa_auto_recover = BFA_TRUE;
7725ccfd
JH		 84
85/*
86 * forward declarations
87 */
a36c61f9 88static void bfa_ioc_hw_sem_get(struct bfa_ioc_s *ioc);
a36c61f9
KG		 89static void bfa_ioc_hwinit(struct bfa_ioc_s *ioc, bfa_boolean_t force);
90static void bfa_ioc_timeout(void *ioc);
775c7742 91static void bfa_ioc_poll_fwinit(struct bfa_ioc_s *ioc);
a36c61f9
KG		 92static void bfa_ioc_send_enable(struct bfa_ioc_s *ioc);
93static void bfa_ioc_send_disable(struct bfa_ioc_s *ioc);
94static void bfa_ioc_send_getattr(struct bfa_ioc_s *ioc);
95static void bfa_ioc_hb_monitor(struct bfa_ioc_s *ioc);
a36c61f9 96static void bfa_ioc_mbox_poll(struct bfa_ioc_s *ioc);
8b070b4a 97static void bfa_ioc_mbox_flush(struct bfa_ioc_s *ioc);
a36c61f9 98static void bfa_ioc_recover(struct bfa_ioc_s *ioc);
d37779f8
KG		 99static void bfa_ioc_event_notify(struct bfa_ioc_s *ioc ,
100 enum bfa_ioc_event_e event);
a36c61f9
KG		 101static void bfa_ioc_disable_comp(struct bfa_ioc_s *ioc);
102static void bfa_ioc_lpu_stop(struct bfa_ioc_s *ioc);
4e78efef 103static void bfa_ioc_fail_notify(struct bfa_ioc_s *ioc);
a36c61f9 104static void bfa_ioc_pf_fwmismatch(struct bfa_ioc_s *ioc);
7725ccfd 105
5fbe25c7 106/*
a36c61f9 107 * IOC state machine definitions/declarations
7725ccfd
JH		 108 */
109enum ioc_event {
a36c61f9
KG		 110 IOC_E_RESET = 1, /* IOC reset request */
111 IOC_E_ENABLE = 2, /* IOC enable request */
112 IOC_E_DISABLE = 3, /* IOC disable request */
113 IOC_E_DETACH = 4, /* driver detach cleanup */
114 IOC_E_ENABLED = 5, /* f/w enabled */
115 IOC_E_FWRSP_GETATTR = 6, /* IOC get attribute response */
116 IOC_E_DISABLED = 7, /* f/w disabled */
775c7742
KG		 117 IOC_E_PFFAILED = 8, /* failure notice by iocpf sm */
118 IOC_E_HBFAIL = 9, /* heartbeat failure */
119 IOC_E_HWERROR = 10, /* hardware error interrupt */
120 IOC_E_TIMEOUT = 11, /* timeout */
5a0adaed 121 IOC_E_HWFAILED = 12, /* PCI mapping failure notice */
7725ccfd
JH		 122};
123
a36c61f9 124bfa_fsm_state_decl(bfa_ioc, uninit, struct bfa_ioc_s, enum ioc_event);
7725ccfd 125bfa_fsm_state_decl(bfa_ioc, reset, struct bfa_ioc_s, enum ioc_event);
7725ccfd
JH		 126bfa_fsm_state_decl(bfa_ioc, enabling, struct bfa_ioc_s, enum ioc_event);
127bfa_fsm_state_decl(bfa_ioc, getattr, struct bfa_ioc_s, enum ioc_event);
128bfa_fsm_state_decl(bfa_ioc, op, struct bfa_ioc_s, enum ioc_event);
4e78efef 129bfa_fsm_state_decl(bfa_ioc, fail_retry, struct bfa_ioc_s, enum ioc_event);
a36c61f9 130bfa_fsm_state_decl(bfa_ioc, fail, struct bfa_ioc_s, enum ioc_event);
7725ccfd
JH		 131bfa_fsm_state_decl(bfa_ioc, disabling, struct bfa_ioc_s, enum ioc_event);
132bfa_fsm_state_decl(bfa_ioc, disabled, struct bfa_ioc_s, enum ioc_event);
5a0adaed 133bfa_fsm_state_decl(bfa_ioc, hwfail, struct bfa_ioc_s, enum ioc_event);
7725ccfd
JH		 134
135static struct bfa_sm_table_s ioc_sm_table[] = {
a36c61f9 136 {BFA_SM(bfa_ioc_sm_uninit), BFA_IOC_UNINIT},
7725ccfd 137 {BFA_SM(bfa_ioc_sm_reset), BFA_IOC_RESET},
a36c61f9 138 {BFA_SM(bfa_ioc_sm_enabling), BFA_IOC_ENABLING},
7725ccfd
JH		 139 {BFA_SM(bfa_ioc_sm_getattr), BFA_IOC_GETATTR},
140 {BFA_SM(bfa_ioc_sm_op), BFA_IOC_OPERATIONAL},
4e78efef 141 {BFA_SM(bfa_ioc_sm_fail_retry), BFA_IOC_INITFAIL},
a36c61f9 142 {BFA_SM(bfa_ioc_sm_fail), BFA_IOC_FAIL},
7725ccfd
JH		 143 {BFA_SM(bfa_ioc_sm_disabling), BFA_IOC_DISABLING},
144 {BFA_SM(bfa_ioc_sm_disabled), BFA_IOC_DISABLED},
5a0adaed 145 {BFA_SM(bfa_ioc_sm_hwfail), BFA_IOC_HWFAIL},
7725ccfd
JH		 146};
147
5fbe25c7 148/*
a36c61f9
KG		 149 * IOCPF state machine definitions/declarations
150 */
151
152#define bfa_iocpf_timer_start(__ioc) \
153 bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->ioc_timer, \
154 bfa_iocpf_timeout, (__ioc), BFA_IOC_TOV)
155#define bfa_iocpf_timer_stop(__ioc) bfa_timer_stop(&(__ioc)->ioc_timer)
156
775c7742 157#define bfa_iocpf_poll_timer_start(__ioc) \
a36c61f9 158 bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->ioc_timer, \
775c7742 159 bfa_iocpf_poll_timeout, (__ioc), BFA_IOC_POLL_TOV)
a36c61f9
KG		 160
161#define bfa_sem_timer_start(__ioc) \
162 bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->sem_timer, \
163 bfa_iocpf_sem_timeout, (__ioc), BFA_IOC_HWSEM_TOV)
164#define bfa_sem_timer_stop(__ioc) bfa_timer_stop(&(__ioc)->sem_timer)
165
166/*
167 * Forward declareations for iocpf state machine
168 */
a36c61f9
KG		 169static void bfa_iocpf_timeout(void *ioc_arg);
170static void bfa_iocpf_sem_timeout(void *ioc_arg);
775c7742 171static void bfa_iocpf_poll_timeout(void *ioc_arg);
a36c61f9 172
5fbe25c7 173/*
a36c61f9
KG		 174 * IOCPF state machine events
175 */
176enum iocpf_event {
177 IOCPF_E_ENABLE = 1, /* IOCPF enable request */
178 IOCPF_E_DISABLE = 2, /* IOCPF disable request */
179 IOCPF_E_STOP = 3, /* stop on driver detach */
180 IOCPF_E_FWREADY = 4, /* f/w initialization done */
181 IOCPF_E_FWRSP_ENABLE = 5, /* enable f/w response */
182 IOCPF_E_FWRSP_DISABLE = 6, /* disable f/w response */
183 IOCPF_E_FAIL = 7, /* failure notice by ioc sm */
184 IOCPF_E_INITFAIL = 8, /* init fail notice by ioc sm */
185 IOCPF_E_GETATTRFAIL = 9, /* init fail notice by ioc sm */
186 IOCPF_E_SEMLOCKED = 10, /* h/w semaphore is locked */
187 IOCPF_E_TIMEOUT = 11, /* f/w response timeout */
5a0adaed 188 IOCPF_E_SEM_ERROR = 12, /* h/w sem mapping error */
a36c61f9
KG		 189};
190
5fbe25c7 191/*
a36c61f9
KG		 192 * IOCPF states
193 */
194enum bfa_iocpf_state {
195 BFA_IOCPF_RESET = 1, /* IOC is in reset state */
196 BFA_IOCPF_SEMWAIT = 2, /* Waiting for IOC h/w semaphore */
197 BFA_IOCPF_HWINIT = 3, /* IOC h/w is being initialized */
198 BFA_IOCPF_READY = 4, /* IOCPF is initialized */
199 BFA_IOCPF_INITFAIL = 5, /* IOCPF failed */
200 BFA_IOCPF_FAIL = 6, /* IOCPF failed */
201 BFA_IOCPF_DISABLING = 7, /* IOCPF is being disabled */
202 BFA_IOCPF_DISABLED = 8, /* IOCPF is disabled */
203 BFA_IOCPF_FWMISMATCH = 9, /* IOC f/w different from drivers */
204};
205
206bfa_fsm_state_decl(bfa_iocpf, reset, struct bfa_iocpf_s, enum iocpf_event);
207bfa_fsm_state_decl(bfa_iocpf, fwcheck, struct bfa_iocpf_s, enum iocpf_event);
208bfa_fsm_state_decl(bfa_iocpf, mismatch, struct bfa_iocpf_s, enum iocpf_event);
209bfa_fsm_state_decl(bfa_iocpf, semwait, struct bfa_iocpf_s, enum iocpf_event);
210bfa_fsm_state_decl(bfa_iocpf, hwinit, struct bfa_iocpf_s, enum iocpf_event);
211bfa_fsm_state_decl(bfa_iocpf, enabling, struct bfa_iocpf_s, enum iocpf_event);
212bfa_fsm_state_decl(bfa_iocpf, ready, struct bfa_iocpf_s, enum iocpf_event);
f1d584d7
KG		 213bfa_fsm_state_decl(bfa_iocpf, initfail_sync, struct bfa_iocpf_s,
214 enum iocpf_event);
a36c61f9 215bfa_fsm_state_decl(bfa_iocpf, initfail, struct bfa_iocpf_s, enum iocpf_event);
f1d584d7 216bfa_fsm_state_decl(bfa_iocpf, fail_sync, struct bfa_iocpf_s, enum iocpf_event);
a36c61f9
KG		 217bfa_fsm_state_decl(bfa_iocpf, fail, struct bfa_iocpf_s, enum iocpf_event);
218bfa_fsm_state_decl(bfa_iocpf, disabling, struct bfa_iocpf_s, enum iocpf_event);
f1d584d7
KG		 219bfa_fsm_state_decl(bfa_iocpf, disabling_sync, struct bfa_iocpf_s,
220 enum iocpf_event);
a36c61f9
KG		 221bfa_fsm_state_decl(bfa_iocpf, disabled, struct bfa_iocpf_s, enum iocpf_event);
222
223static struct bfa_sm_table_s iocpf_sm_table[] = {
224 {BFA_SM(bfa_iocpf_sm_reset), BFA_IOCPF_RESET},
225 {BFA_SM(bfa_iocpf_sm_fwcheck), BFA_IOCPF_FWMISMATCH},
226 {BFA_SM(bfa_iocpf_sm_mismatch), BFA_IOCPF_FWMISMATCH},
227 {BFA_SM(bfa_iocpf_sm_semwait), BFA_IOCPF_SEMWAIT},
228 {BFA_SM(bfa_iocpf_sm_hwinit), BFA_IOCPF_HWINIT},
229 {BFA_SM(bfa_iocpf_sm_enabling), BFA_IOCPF_HWINIT},
230 {BFA_SM(bfa_iocpf_sm_ready), BFA_IOCPF_READY},
f1d584d7 231 {BFA_SM(bfa_iocpf_sm_initfail_sync), BFA_IOCPF_INITFAIL},
a36c61f9 232 {BFA_SM(bfa_iocpf_sm_initfail), BFA_IOCPF_INITFAIL},
f1d584d7 233 {BFA_SM(bfa_iocpf_sm_fail_sync), BFA_IOCPF_FAIL},
a36c61f9
KG		 234 {BFA_SM(bfa_iocpf_sm_fail), BFA_IOCPF_FAIL},
235 {BFA_SM(bfa_iocpf_sm_disabling), BFA_IOCPF_DISABLING},
f1d584d7 236 {BFA_SM(bfa_iocpf_sm_disabling_sync), BFA_IOCPF_DISABLING},
a36c61f9
KG		 237 {BFA_SM(bfa_iocpf_sm_disabled), BFA_IOCPF_DISABLED},
238};
239
5fbe25c7 240/*
a36c61f9
KG		 241 * IOC State Machine
242 */
243
5fbe25c7 244/*
a36c61f9
KG		 245 * Beginning state. IOC uninit state.
246 */
247
248static void
249bfa_ioc_sm_uninit_entry(struct bfa_ioc_s *ioc)
250{
251}
252
5fbe25c7 253/*
a36c61f9
KG		 254 * IOC is in uninit state.
255 */
256static void
257bfa_ioc_sm_uninit(struct bfa_ioc_s *ioc, enum ioc_event event)
258{
259 bfa_trc(ioc, event);
260
261 switch (event) {
262 case IOC_E_RESET:
263 bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
264 break;
265
266 default:
267 bfa_sm_fault(ioc, event);
268 }
269}
5fbe25c7 270/*
7725ccfd
JH		 271 * Reset entry actions -- initialize state machine
272 */
273static void
274bfa_ioc_sm_reset_entry(struct bfa_ioc_s *ioc)
275{
a36c61f9 276 bfa_fsm_set_state(&ioc->iocpf, bfa_iocpf_sm_reset);
7725ccfd
JH		 277}
278
5fbe25c7 279/*
a36c61f9 280 * IOC is in reset state.
7725ccfd
JH		 281 */
282static void
283bfa_ioc_sm_reset(struct bfa_ioc_s *ioc, enum ioc_event event)
284{
285 bfa_trc(ioc, event);
286
287 switch (event) {
288 case IOC_E_ENABLE:
a36c61f9 289 bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling);
7725ccfd
JH		 290 break;
291
292 case IOC_E_DISABLE:
293 bfa_ioc_disable_comp(ioc);
294 break;
295
296 case IOC_E_DETACH:
a36c61f9 297 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
7725ccfd
JH		 298 break;
299
300 default:
301 bfa_sm_fault(ioc, event);
302 }
303}
304
a36c61f9
KG		 305
306static void
307bfa_ioc_sm_enabling_entry(struct bfa_ioc_s *ioc)
308{
f7f73812 309 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_ENABLE);
a36c61f9
KG		 310}
311
5fbe25c7 312/*
a36c61f9
KG		 313 * Host IOC function is being enabled, awaiting response from firmware.
314 * Semaphore is acquired.
7725ccfd
JH		 315 */
316static void
a36c61f9 317bfa_ioc_sm_enabling(struct bfa_ioc_s *ioc, enum ioc_event event)
7725ccfd 318{
a36c61f9
KG		 319 bfa_trc(ioc, event);
320
321 switch (event) {
322 case IOC_E_ENABLED:
323 bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr);
324 break;
325
4e78efef
KG		 326 case IOC_E_PFFAILED:
327 /* !!! fall through !!! */
a36c61f9 328 case IOC_E_HWERROR:
4e78efef 329 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
775c7742 330 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
4e78efef
KG		 331 if (event != IOC_E_PFFAILED)
332 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_INITFAIL);
a36c61f9
KG		 333 break;
334
5a0adaed
KG		 335 case IOC_E_HWFAILED:
336 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
337 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail);
338 break;
339
a36c61f9
KG		 340 case IOC_E_DISABLE:
341 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
342 break;
343
344 case IOC_E_DETACH:
345 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
f7f73812 346 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_STOP);
a36c61f9
KG		 347 break;
348
349 case IOC_E_ENABLE:
350 break;
351
352 default:
353 bfa_sm_fault(ioc, event);
354 }
355}
356
357
358static void
359bfa_ioc_sm_getattr_entry(struct bfa_ioc_s *ioc)
360{
361 bfa_ioc_timer_start(ioc);
362 bfa_ioc_send_getattr(ioc);
7725ccfd
JH		 363}
364
5fbe25c7 365/*
a36c61f9 366 * IOC configuration in progress. Timer is active.
7725ccfd
JH		 367 */
368static void
a36c61f9 369bfa_ioc_sm_getattr(struct bfa_ioc_s *ioc, enum ioc_event event)
7725ccfd
JH		 370{
371 bfa_trc(ioc, event);
372
373 switch (event) {
a36c61f9
KG		 374 case IOC_E_FWRSP_GETATTR:
375 bfa_ioc_timer_stop(ioc);
a36c61f9
KG		 376 bfa_fsm_set_state(ioc, bfa_ioc_sm_op);
377 break;
378
4e78efef 379 case IOC_E_PFFAILED:
a36c61f9
KG		 380 case IOC_E_HWERROR:
381 bfa_ioc_timer_stop(ioc);
4e78efef 382 /* !!! fall through !!! */
a36c61f9 383 case IOC_E_TIMEOUT:
4e78efef 384 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
775c7742 385 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
4e78efef
KG		 386 if (event != IOC_E_PFFAILED)
387 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_GETATTRFAIL);
7725ccfd
JH		 388 break;
389
390 case IOC_E_DISABLE:
a36c61f9
KG		 391 bfa_ioc_timer_stop(ioc);
392 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
393 break;
394
395 case IOC_E_ENABLE:
396 break;
397
398 default:
399 bfa_sm_fault(ioc, event);
400 }
401}
402
a36c61f9
KG		 403static void
404bfa_ioc_sm_op_entry(struct bfa_ioc_s *ioc)
405{
406 struct bfad_s *bfad = (struct bfad_s *)ioc->bfa->bfad;
407
408 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_OK);
d37779f8 409 bfa_ioc_event_notify(ioc, BFA_IOC_E_ENABLED);
db9d8a75 410 bfa_ioc_hb_monitor(ioc);
88166242 411 BFA_LOG(KERN_INFO, bfad, bfa_log_level, "IOC enabled\n");
7826f304 412 bfa_ioc_aen_post(ioc, BFA_IOC_AEN_ENABLE);
a36c61f9
KG		 413}
414
415static void
416bfa_ioc_sm_op(struct bfa_ioc_s *ioc, enum ioc_event event)
417{
418 bfa_trc(ioc, event);
419
420 switch (event) {
421 case IOC_E_ENABLE:
422 break;
423
424 case IOC_E_DISABLE:
f7f73812 425 bfa_hb_timer_stop(ioc);
a36c61f9
KG		 426 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
427 break;
428
4e78efef 429 case IOC_E_PFFAILED:
a36c61f9 430 case IOC_E_HWERROR:
f7f73812 431 bfa_hb_timer_stop(ioc);
a36c61f9 432 /* !!! fall through !!! */
a36c61f9 433 case IOC_E_HBFAIL:
4e78efef
KG		 434 if (ioc->iocpf.auto_recover)
435 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail_retry);
436 else
437 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
438
775c7742
KG		 439 bfa_ioc_fail_notify(ioc);
440
4e78efef
KG		 441 if (event != IOC_E_PFFAILED)
442 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FAIL);
a36c61f9
KG		 443 break;
444
445 default:
446 bfa_sm_fault(ioc, event);
447 }
448}
449
450
451static void
452bfa_ioc_sm_disabling_entry(struct bfa_ioc_s *ioc)
453{
454 struct bfad_s *bfad = (struct bfad_s *)ioc->bfa->bfad;
f7f73812 455 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_DISABLE);
88166242 456 BFA_LOG(KERN_INFO, bfad, bfa_log_level, "IOC disabled\n");
7826f304 457 bfa_ioc_aen_post(ioc, BFA_IOC_AEN_DISABLE);
a36c61f9
KG		 458}
459
5fbe25c7 460/*
a36c61f9
KG		 461 * IOC is being disabled
462 */
463static void
464bfa_ioc_sm_disabling(struct bfa_ioc_s *ioc, enum ioc_event event)
465{
466 bfa_trc(ioc, event);
467
468 switch (event) {
469 case IOC_E_DISABLED:
470 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
471 break;
472
473 case IOC_E_HWERROR:
7725ccfd 474 /*
a36c61f9
KG		 475 * No state change. Will move to disabled state
476 * after iocpf sm completes failure processing and
477 * moves to disabled state.
7725ccfd 478 */
f7f73812 479 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FAIL);
a36c61f9 480 break;
7725ccfd 481
5a0adaed
KG		 482 case IOC_E_HWFAILED:
483 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail);
484 bfa_ioc_disable_comp(ioc);
485 break;
486
a36c61f9
KG		 487 default:
488 bfa_sm_fault(ioc, event);
489 }
490}
491
5fbe25c7 492/*
a36c61f9
KG		 493 * IOC disable completion entry.
494 */
495static void
496bfa_ioc_sm_disabled_entry(struct bfa_ioc_s *ioc)
497{
498 bfa_ioc_disable_comp(ioc);
499}
500
501static void
502bfa_ioc_sm_disabled(struct bfa_ioc_s *ioc, enum ioc_event event)
503{
504 bfa_trc(ioc, event);
505
506 switch (event) {
507 case IOC_E_ENABLE:
508 bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling);
7725ccfd
JH		 509 break;
510
a36c61f9
KG		 511 case IOC_E_DISABLE:
512 ioc->cbfn->disable_cbfn(ioc->bfa);
513 break;
514
515 case IOC_E_DETACH:
516 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
f7f73812 517 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_STOP);
7725ccfd
JH		 518 break;
519
520 default:
521 bfa_sm_fault(ioc, event);
522 }
523}
524
a36c61f9
KG		 525
526static void
4e78efef 527bfa_ioc_sm_fail_retry_entry(struct bfa_ioc_s *ioc)
a36c61f9 528{
4e78efef 529 bfa_trc(ioc, 0);
a36c61f9
KG		 530}
531
5fbe25c7 532/*
f1d584d7 533 * Hardware initialization retry.
7725ccfd
JH		 534 */
535static void
4e78efef 536bfa_ioc_sm_fail_retry(struct bfa_ioc_s *ioc, enum ioc_event event)
7725ccfd 537{
a36c61f9
KG		 538 bfa_trc(ioc, event);
539
540 switch (event) {
541 case IOC_E_ENABLED:
542 bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr);
543 break;
544
4e78efef
KG		 545 case IOC_E_PFFAILED:
546 case IOC_E_HWERROR:
5fbe25c7 547 /*
4e78efef 548 * Initialization retry failed.
a36c61f9
KG		 549 */
550 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
775c7742 551 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
4e78efef
KG		 552 if (event != IOC_E_PFFAILED)
553 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_INITFAIL);
554 break;
555
5a0adaed
KG		 556 case IOC_E_HWFAILED:
557 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
558 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail);
559 break;
560
4e78efef 561 case IOC_E_ENABLE:
a36c61f9
KG		 562 break;
563
564 case IOC_E_DISABLE:
565 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
566 break;
567
568 case IOC_E_DETACH:
569 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
f7f73812 570 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_STOP);
a36c61f9
KG		 571 break;
572
573 default:
574 bfa_sm_fault(ioc, event);
575 }
576}
577
578
579static void
580bfa_ioc_sm_fail_entry(struct bfa_ioc_s *ioc)
581{
4e78efef 582 bfa_trc(ioc, 0);
7725ccfd
JH		 583}
584
5fbe25c7 585/*
a36c61f9 586 * IOC failure.
7725ccfd
JH		 587 */
588static void
a36c61f9 589bfa_ioc_sm_fail(struct bfa_ioc_s *ioc, enum ioc_event event)
7725ccfd
JH		 590{
591 bfa_trc(ioc, event);
592
593 switch (event) {
a36c61f9 594
a36c61f9
KG		 595 case IOC_E_ENABLE:
596 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
597 break;
598
7725ccfd 599 case IOC_E_DISABLE:
a36c61f9
KG		 600 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
601 break;
602
f1d584d7
KG		 603 case IOC_E_DETACH:
604 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
605 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_STOP);
606 break;
607
a36c61f9 608 case IOC_E_HWERROR:
881c1b3c 609 case IOC_E_HWFAILED:
7725ccfd 610 /*
881c1b3c 611 * HB failure / HW error notification, ignore.
7725ccfd 612 */
a36c61f9
KG		 613 break;
614 default:
615 bfa_sm_fault(ioc, event);
616 }
617}
7725ccfd 618
5a0adaed
KG		 619static void
620bfa_ioc_sm_hwfail_entry(struct bfa_ioc_s *ioc)
621{
622 bfa_trc(ioc, 0);
623}
624
625static void
626bfa_ioc_sm_hwfail(struct bfa_ioc_s *ioc, enum ioc_event event)
627{
628 bfa_trc(ioc, event);
629
630 switch (event) {
631 case IOC_E_ENABLE:
632 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
633 break;
634
635 case IOC_E_DISABLE:
636 ioc->cbfn->disable_cbfn(ioc->bfa);
637 break;
638
639 case IOC_E_DETACH:
640 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
641 break;
642
881c1b3c
KG		 643 case IOC_E_HWERROR:
644 /* Ignore - already in hwfail state */
645 break;
646
5a0adaed
KG		 647 default:
648 bfa_sm_fault(ioc, event);
649 }
650}
651
5fbe25c7 652/*
a36c61f9
KG		 653 * IOCPF State Machine
654 */
655
5fbe25c7 656/*
a36c61f9
KG		 657 * Reset entry actions -- initialize state machine
658 */
659static void
660bfa_iocpf_sm_reset_entry(struct bfa_iocpf_s *iocpf)
661{
775c7742 662 iocpf->fw_mismatch_notified = BFA_FALSE;
a36c61f9
KG		 663 iocpf->auto_recover = bfa_auto_recover;
664}
665
5fbe25c7 666/*
a36c61f9
KG		 667 * Beginning state. IOC is in reset state.
668 */
669static void
670bfa_iocpf_sm_reset(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
671{
672 struct bfa_ioc_s *ioc = iocpf->ioc;
673
674 bfa_trc(ioc, event);
675
676 switch (event) {
677 case IOCPF_E_ENABLE:
678 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fwcheck);
7725ccfd
JH		 679 break;
680
a36c61f9 681 case IOCPF_E_STOP:
7725ccfd
JH		 682 break;
683
684 default:
685 bfa_sm_fault(ioc, event);
686 }
687}
688
5fbe25c7 689/*
a36c61f9 690 * Semaphore should be acquired for version check.
7725ccfd
JH		 691 */
692static void
a36c61f9 693bfa_iocpf_sm_fwcheck_entry(struct bfa_iocpf_s *iocpf)
7725ccfd 694{
5a0adaed 695 struct bfi_ioc_image_hdr_s fwhdr;
8919678e
KG		 696 u32 r32, fwstate, pgnum, pgoff, loff = 0;
697 int i;
698
699 /*
700 * Spin on init semaphore to serialize.
701 */
702 r32 = readl(iocpf->ioc->ioc_regs.ioc_init_sem_reg);
703 while (r32 & 0x1) {
704 udelay(20);
705 r32 = readl(iocpf->ioc->ioc_regs.ioc_init_sem_reg);
706 }
5a0adaed
KG		 707
708 /* h/w sem init */
c679b599 709 fwstate = bfa_ioc_get_cur_ioc_fwstate(iocpf->ioc);
8919678e
KG		 710 if (fwstate == BFI_IOC_UNINIT) {
711 writel(1, iocpf->ioc->ioc_regs.ioc_init_sem_reg);
5a0adaed 712 goto sem_get;
8919678e 713 }
5a0adaed
KG		 714
715 bfa_ioc_fwver_get(iocpf->ioc, &fwhdr);
716
8919678e
KG		 717 if (swab32(fwhdr.exec) == BFI_FWBOOT_TYPE_NORMAL) {
718 writel(1, iocpf->ioc->ioc_regs.ioc_init_sem_reg);
5a0adaed 719 goto sem_get;
8919678e
KG		 720 }
721
722 /*
723 * Clear fwver hdr
724 */
725 pgnum = PSS_SMEM_PGNUM(iocpf->ioc->ioc_regs.smem_pg0, loff);
726 pgoff = PSS_SMEM_PGOFF(loff);
727 writel(pgnum, iocpf->ioc->ioc_regs.host_page_num_fn);
728
729 for (i = 0; i < sizeof(struct bfi_ioc_image_hdr_s) / sizeof(u32); i++) {
730 bfa_mem_write(iocpf->ioc->ioc_regs.smem_page_start, loff, 0);
731 loff += sizeof(u32);
732 }
5a0adaed
KG		 733
734 bfa_trc(iocpf->ioc, fwstate);
8919678e 735 bfa_trc(iocpf->ioc, swab32(fwhdr.exec));
c679b599
VMG		 736 bfa_ioc_set_cur_ioc_fwstate(iocpf->ioc, BFI_IOC_UNINIT);
737 bfa_ioc_set_alt_ioc_fwstate(iocpf->ioc, BFI_IOC_UNINIT);
5a0adaed
KG		 738
739 /*
8919678e 740 * Unlock the hw semaphore. Should be here only once per boot.
5a0adaed 741 */
7ac83b1f 742 bfa_ioc_ownership_reset(iocpf->ioc);
8919678e
KG		 743
744 /*
745 * unlock init semaphore.
746 */
747 writel(1, iocpf->ioc->ioc_regs.ioc_init_sem_reg);
748
5a0adaed 749sem_get:
a36c61f9 750 bfa_ioc_hw_sem_get(iocpf->ioc);
7725ccfd
JH		 751}
752
5fbe25c7 753/*
a36c61f9 754 * Awaiting h/w semaphore to continue with version check.
7725ccfd
JH		 755 */
756static void
a36c61f9 757bfa_iocpf_sm_fwcheck(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
7725ccfd 758{
a36c61f9
KG		 759 struct bfa_ioc_s *ioc = iocpf->ioc;
760
7725ccfd
JH		 761 bfa_trc(ioc, event);
762
763 switch (event) {
a36c61f9
KG		 764 case IOCPF_E_SEMLOCKED:
765 if (bfa_ioc_firmware_lock(ioc)) {
45d7f0cc 766 if (bfa_ioc_sync_start(ioc)) {
f1d584d7
KG		 767 bfa_ioc_sync_join(ioc);
768 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
769 } else {
770 bfa_ioc_firmware_unlock(ioc);
771 writel(1, ioc->ioc_regs.ioc_sem_reg);
772 bfa_sem_timer_start(ioc);
773 }
a36c61f9 774 } else {
f7f73812 775 writel(1, ioc->ioc_regs.ioc_sem_reg);
a36c61f9
KG		 776 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_mismatch);
777 }
7725ccfd
JH		 778 break;
779
5a0adaed
KG		 780 case IOCPF_E_SEM_ERROR:
781 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
782 bfa_fsm_send_event(ioc, IOC_E_HWFAILED);
783 break;
784
a36c61f9 785 case IOCPF_E_DISABLE:
f7f73812 786 bfa_sem_timer_stop(ioc);
a36c61f9 787 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
f7f73812 788 bfa_fsm_send_event(ioc, IOC_E_DISABLED);
a36c61f9
KG		 789 break;
790
791 case IOCPF_E_STOP:
f7f73812 792 bfa_sem_timer_stop(ioc);
a36c61f9 793 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
7725ccfd
JH		 794 break;
795
796 default:
797 bfa_sm_fault(ioc, event);
798 }
799}
800
5fbe25c7 801/*
a36c61f9
KG		 802 * Notify enable completion callback.
803 */
7725ccfd 804static void
a36c61f9 805bfa_iocpf_sm_mismatch_entry(struct bfa_iocpf_s *iocpf)
7725ccfd 806{
a36c61f9
KG		 807 /*
808 * Call only the first time sm enters fwmismatch state.
809 */
775c7742 810 if (iocpf->fw_mismatch_notified == BFA_FALSE)
a36c61f9
KG		 811 bfa_ioc_pf_fwmismatch(iocpf->ioc);
812
775c7742 813 iocpf->fw_mismatch_notified = BFA_TRUE;
a36c61f9 814 bfa_iocpf_timer_start(iocpf->ioc);
7725ccfd
JH		 815}
816
5fbe25c7 817/*
a36c61f9 818 * Awaiting firmware version match.
7725ccfd
JH		 819 */
820static void
a36c61f9 821bfa_iocpf_sm_mismatch(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
7725ccfd 822{
a36c61f9
KG		 823 struct bfa_ioc_s *ioc = iocpf->ioc;
824
7725ccfd
JH		 825 bfa_trc(ioc, event);
826
827 switch (event) {
a36c61f9
KG		 828 case IOCPF_E_TIMEOUT:
829 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fwcheck);
7725ccfd
JH		 830 break;
831
a36c61f9
KG		 832 case IOCPF_E_DISABLE:
833 bfa_iocpf_timer_stop(ioc);
834 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
f7f73812 835 bfa_fsm_send_event(ioc, IOC_E_DISABLED);
a36c61f9 836 break;
7725ccfd 837
a36c61f9
KG		 838 case IOCPF_E_STOP:
839 bfa_iocpf_timer_stop(ioc);
840 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
841 break;
7725ccfd 842
a36c61f9
KG		 843 default:
844 bfa_sm_fault(ioc, event);
845 }
846}
847
5fbe25c7 848/*
a36c61f9
KG		 849 * Request for semaphore.
850 */
851static void
852bfa_iocpf_sm_semwait_entry(struct bfa_iocpf_s *iocpf)
853{
854 bfa_ioc_hw_sem_get(iocpf->ioc);
855}
856
5fbe25c7 857/*
a36c61f9
KG		 858 * Awaiting semaphore for h/w initialzation.
859 */
860static void
861bfa_iocpf_sm_semwait(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
862{
863 struct bfa_ioc_s *ioc = iocpf->ioc;
864
865 bfa_trc(ioc, event);
866
867 switch (event) {
868 case IOCPF_E_SEMLOCKED:
f1d584d7
KG		 869 if (bfa_ioc_sync_complete(ioc)) {
870 bfa_ioc_sync_join(ioc);
871 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
872 } else {
873 writel(1, ioc->ioc_regs.ioc_sem_reg);
874 bfa_sem_timer_start(ioc);
875 }
7725ccfd
JH		 876 break;
877
5a0adaed
KG		 878 case IOCPF_E_SEM_ERROR:
879 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
880 bfa_fsm_send_event(ioc, IOC_E_HWFAILED);
881 break;
882
a36c61f9 883 case IOCPF_E_DISABLE:
f7f73812 884 bfa_sem_timer_stop(ioc);
f1d584d7 885 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
7725ccfd
JH		 886 break;
887
888 default:
889 bfa_sm_fault(ioc, event);
890 }
891}
892
7725ccfd 893static void
a36c61f9 894bfa_iocpf_sm_hwinit_entry(struct bfa_iocpf_s *iocpf)
7725ccfd 895{
775c7742 896 iocpf->poll_time = 0;
f7f73812 897 bfa_ioc_hwinit(iocpf->ioc, BFA_FALSE);
7725ccfd
JH		 898}
899
5fbe25c7 900/*
a36c61f9
KG		 901 * Hardware is being initialized. Interrupts are enabled.
902 * Holding hardware semaphore lock.
7725ccfd
JH		 903 */
904static void
a36c61f9 905bfa_iocpf_sm_hwinit(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
7725ccfd 906{
a36c61f9
KG		 907 struct bfa_ioc_s *ioc = iocpf->ioc;
908
7725ccfd
JH		 909 bfa_trc(ioc, event);
910
911 switch (event) {
a36c61f9 912 case IOCPF_E_FWREADY:
a36c61f9 913 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_enabling);
7725ccfd
JH		 914 break;
915
a36c61f9 916 case IOCPF_E_TIMEOUT:
f7f73812 917 writel(1, ioc->ioc_regs.ioc_sem_reg);
775c7742 918 bfa_fsm_send_event(ioc, IOC_E_PFFAILED);
f1d584d7 919 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
7725ccfd
JH		 920 break;
921
a36c61f9 922 case IOCPF_E_DISABLE:
a36c61f9 923 bfa_iocpf_timer_stop(ioc);
f1d584d7
KG		 924 bfa_ioc_sync_leave(ioc);
925 writel(1, ioc->ioc_regs.ioc_sem_reg);
a36c61f9 926 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
7725ccfd
JH		 927 break;
928
929 default:
930 bfa_sm_fault(ioc, event);
931 }
932}
933
7725ccfd 934static void
a36c61f9 935bfa_iocpf_sm_enabling_entry(struct bfa_iocpf_s *iocpf)
7725ccfd 936{
a36c61f9 937 bfa_iocpf_timer_start(iocpf->ioc);
775c7742
KG		 938 /*
939 * Enable Interrupts before sending fw IOC ENABLE cmd.
940 */
941 iocpf->ioc->cbfn->reset_cbfn(iocpf->ioc->bfa);
a36c61f9 942 bfa_ioc_send_enable(iocpf->ioc);
7725ccfd
JH		 943}
944
5fbe25c7 945/*
a36c61f9
KG		 946 * Host IOC function is being enabled, awaiting response from firmware.
947 * Semaphore is acquired.
7725ccfd
JH		 948 */
949static void
a36c61f9 950bfa_iocpf_sm_enabling(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
7725ccfd 951{
a36c61f9
KG		 952 struct bfa_ioc_s *ioc = iocpf->ioc;
953
7725ccfd
JH		 954 bfa_trc(ioc, event);
955
956 switch (event) {
a36c61f9
KG		 957 case IOCPF_E_FWRSP_ENABLE:
958 bfa_iocpf_timer_stop(ioc);
f7f73812 959 writel(1, ioc->ioc_regs.ioc_sem_reg);
a36c61f9 960 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_ready);
7725ccfd
JH		 961 break;
962
a36c61f9
KG		 963 case IOCPF_E_INITFAIL:
964 bfa_iocpf_timer_stop(ioc);
7725ccfd 965 /*
a36c61f9 966 * !!! fall through !!!
7725ccfd
JH		 967 */
968
a36c61f9 969 case IOCPF_E_TIMEOUT:
f7f73812 970 writel(1, ioc->ioc_regs.ioc_sem_reg);
a36c61f9 971 if (event == IOCPF_E_TIMEOUT)
4e78efef 972 bfa_fsm_send_event(ioc, IOC_E_PFFAILED);
f1d584d7 973 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
7725ccfd
JH		 974 break;
975
a36c61f9
KG		 976 case IOCPF_E_DISABLE:
977 bfa_iocpf_timer_stop(ioc);
f7f73812 978 writel(1, ioc->ioc_regs.ioc_sem_reg);
a36c61f9
KG		 979 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling);
980 break;
981
7725ccfd
JH		 982 default:
983 bfa_sm_fault(ioc, event);
984 }
985}
986
7725ccfd 987static void
a36c61f9 988bfa_iocpf_sm_ready_entry(struct bfa_iocpf_s *iocpf)
7725ccfd 989{
f7f73812 990 bfa_fsm_send_event(iocpf->ioc, IOC_E_ENABLED);
7725ccfd
JH		 991}
992
993static void
a36c61f9 994bfa_iocpf_sm_ready(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
7725ccfd 995{
a36c61f9
KG		 996 struct bfa_ioc_s *ioc = iocpf->ioc;
997
7725ccfd
JH		 998 bfa_trc(ioc, event);
999
1000 switch (event) {
a36c61f9
KG		 1001 case IOCPF_E_DISABLE:
1002 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling);
1003 break;
1004
1005 case IOCPF_E_GETATTRFAIL:
f1d584d7 1006 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
7725ccfd
JH		 1007 break;
1008
a36c61f9 1009 case IOCPF_E_FAIL:
f1d584d7 1010 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail_sync);
7725ccfd
JH		 1011 break;
1012
7725ccfd
JH		 1013 default:
1014 bfa_sm_fault(ioc, event);
1015 }
1016}
1017
7725ccfd 1018static void
a36c61f9 1019bfa_iocpf_sm_disabling_entry(struct bfa_iocpf_s *iocpf)
7725ccfd 1020{
a36c61f9
KG		 1021 bfa_iocpf_timer_start(iocpf->ioc);
1022 bfa_ioc_send_disable(iocpf->ioc);
7725ccfd
JH		 1023}
1024
5fbe25c7 1025/*
7725ccfd
JH		 1026 * IOC is being disabled
1027 */
1028static void
a36c61f9 1029bfa_iocpf_sm_disabling(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
7725ccfd 1030{
a36c61f9
KG		 1031 struct bfa_ioc_s *ioc = iocpf->ioc;
1032
7725ccfd
JH		 1033 bfa_trc(ioc, event);
1034
1035 switch (event) {
a36c61f9 1036 case IOCPF_E_FWRSP_DISABLE:
a36c61f9 1037 bfa_iocpf_timer_stop(ioc);
f1d584d7 1038 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
0a20de44
KG		 1039 break;
1040
a36c61f9
KG		 1041 case IOCPF_E_FAIL:
1042 bfa_iocpf_timer_stop(ioc);
7725ccfd
JH		 1043 /*
1044 * !!! fall through !!!
1045 */
1046
a36c61f9 1047 case IOCPF_E_TIMEOUT:
c679b599 1048 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
f1d584d7 1049 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
a36c61f9
KG		 1050 break;
1051
1052 case IOCPF_E_FWRSP_ENABLE:
7725ccfd
JH		 1053 break;
1054
1055 default:
1056 bfa_sm_fault(ioc, event);
1057 }
1058}
1059
f1d584d7
KG		 1060static void
1061bfa_iocpf_sm_disabling_sync_entry(struct bfa_iocpf_s *iocpf)
1062{
1063 bfa_ioc_hw_sem_get(iocpf->ioc);
1064}
1065
8f4bfadd 1066/*
f1d584d7
KG		 1067 * IOC hb ack request is being removed.
1068 */
1069static void
1070bfa_iocpf_sm_disabling_sync(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
1071{
1072 struct bfa_ioc_s *ioc = iocpf->ioc;
1073
1074 bfa_trc(ioc, event);
1075
1076 switch (event) {
1077 case IOCPF_E_SEMLOCKED:
1078 bfa_ioc_sync_leave(ioc);
1079 writel(1, ioc->ioc_regs.ioc_sem_reg);
1080 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
1081 break;
1082
5a0adaed
KG		 1083 case IOCPF_E_SEM_ERROR:
1084 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
1085 bfa_fsm_send_event(ioc, IOC_E_HWFAILED);
1086 break;
1087
f1d584d7
KG		 1088 case IOCPF_E_FAIL:
1089 break;
1090
1091 default:
1092 bfa_sm_fault(ioc, event);
1093 }
1094}
1095
5fbe25c7 1096/*
7725ccfd
JH		 1097 * IOC disable completion entry.
1098 */
1099static void
a36c61f9 1100bfa_iocpf_sm_disabled_entry(struct bfa_iocpf_s *iocpf)
7725ccfd 1101{
8b070b4a 1102 bfa_ioc_mbox_flush(iocpf->ioc);
f7f73812 1103 bfa_fsm_send_event(iocpf->ioc, IOC_E_DISABLED);
7725ccfd
JH		 1104}
1105
1106static void
a36c61f9 1107bfa_iocpf_sm_disabled(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
7725ccfd 1108{
a36c61f9
KG		 1109 struct bfa_ioc_s *ioc = iocpf->ioc;
1110
7725ccfd
JH		 1111 bfa_trc(ioc, event);
1112
1113 switch (event) {
a36c61f9
KG		 1114 case IOCPF_E_ENABLE:
1115 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_semwait);
7725ccfd
JH		 1116 break;
1117
a36c61f9 1118 case IOCPF_E_STOP:
7725ccfd 1119 bfa_ioc_firmware_unlock(ioc);
a36c61f9 1120 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
7725ccfd
JH		 1121 break;
1122
1123 default:
1124 bfa_sm_fault(ioc, event);
1125 }
1126}
1127
f1d584d7
KG		 1128static void
1129bfa_iocpf_sm_initfail_sync_entry(struct bfa_iocpf_s *iocpf)
1130{
5a0adaed 1131 bfa_ioc_debug_save_ftrc(iocpf->ioc);
f1d584d7
KG		 1132 bfa_ioc_hw_sem_get(iocpf->ioc);
1133}
1134
8f4bfadd 1135/*
f1d584d7
KG		 1136 * Hardware initialization failed.
1137 */
1138static void
1139bfa_iocpf_sm_initfail_sync(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
1140{
1141 struct bfa_ioc_s *ioc = iocpf->ioc;
1142
1143 bfa_trc(ioc, event);
1144
1145 switch (event) {
1146 case IOCPF_E_SEMLOCKED:
1147 bfa_ioc_notify_fail(ioc);
775c7742 1148 bfa_ioc_sync_leave(ioc);
c679b599 1149 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
775c7742
KG		 1150 writel(1, ioc->ioc_regs.ioc_sem_reg);
1151 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail);
f1d584d7
KG		 1152 break;
1153
5a0adaed
KG		 1154 case IOCPF_E_SEM_ERROR:
1155 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
1156 bfa_fsm_send_event(ioc, IOC_E_HWFAILED);
1157 break;
1158
f1d584d7
KG		 1159 case IOCPF_E_DISABLE:
1160 bfa_sem_timer_stop(ioc);
1161 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
1162 break;
1163
1164 case IOCPF_E_STOP:
1165 bfa_sem_timer_stop(ioc);
1166 bfa_ioc_firmware_unlock(ioc);
1167 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
1168 break;
1169
1170 case IOCPF_E_FAIL:
1171 break;
1172
1173 default:
1174 bfa_sm_fault(ioc, event);
1175 }
1176}
1177
7725ccfd 1178static void
a36c61f9 1179bfa_iocpf_sm_initfail_entry(struct bfa_iocpf_s *iocpf)
7725ccfd 1180{
5a0adaed 1181 bfa_trc(iocpf->ioc, 0);
7725ccfd
JH		 1182}
1183
5fbe25c7 1184/*
7725ccfd
JH		 1185 * Hardware initialization failed.
1186 */
1187static void
a36c61f9 1188bfa_iocpf_sm_initfail(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
7725ccfd 1189{
a36c61f9
KG		 1190 struct bfa_ioc_s *ioc = iocpf->ioc;
1191
7725ccfd
JH		 1192 bfa_trc(ioc, event);
1193
1194 switch (event) {
a36c61f9 1195 case IOCPF_E_DISABLE:
a36c61f9 1196 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
7725ccfd
JH		 1197 break;
1198
a36c61f9 1199 case IOCPF_E_STOP:
7725ccfd 1200 bfa_ioc_firmware_unlock(ioc);
a36c61f9 1201 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
7725ccfd
JH		 1202 break;
1203
7725ccfd
JH		 1204 default:
1205 bfa_sm_fault(ioc, event);
1206 }
1207}
1208
7725ccfd 1209static void
f1d584d7 1210bfa_iocpf_sm_fail_sync_entry(struct bfa_iocpf_s *iocpf)
7725ccfd 1211{
8f4bfadd 1212 /*
7725ccfd
JH		 1213 * Mark IOC as failed in hardware and stop firmware.
1214 */
a36c61f9 1215 bfa_ioc_lpu_stop(iocpf->ioc);
7725ccfd 1216
8f4bfadd 1217 /*
7725ccfd
JH		 1218 * Flush any queued up mailbox requests.
1219 */
8b070b4a 1220 bfa_ioc_mbox_flush(iocpf->ioc);
7725ccfd 1221
f1d584d7
KG		 1222 bfa_ioc_hw_sem_get(iocpf->ioc);
1223}
1224
1225static void
1226bfa_iocpf_sm_fail_sync(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
1227{
1228 struct bfa_ioc_s *ioc = iocpf->ioc;
1229
1230 bfa_trc(ioc, event);
1231
1232 switch (event) {
1233 case IOCPF_E_SEMLOCKED:
f1d584d7
KG		 1234 bfa_ioc_sync_ack(ioc);
1235 bfa_ioc_notify_fail(ioc);
1236 if (!iocpf->auto_recover) {
1237 bfa_ioc_sync_leave(ioc);
c679b599 1238 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
f1d584d7
KG		 1239 writel(1, ioc->ioc_regs.ioc_sem_reg);
1240 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
1241 } else {
1242 if (bfa_ioc_sync_complete(ioc))
1243 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
1244 else {
1245 writel(1, ioc->ioc_regs.ioc_sem_reg);
1246 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_semwait);
1247 }
1248 }
1249 break;
1250
5a0adaed
KG		 1251 case IOCPF_E_SEM_ERROR:
1252 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
1253 bfa_fsm_send_event(ioc, IOC_E_HWFAILED);
1254 break;
1255
f1d584d7
KG		 1256 case IOCPF_E_DISABLE:
1257 bfa_sem_timer_stop(ioc);
1258 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
1259 break;
1260
1261 case IOCPF_E_FAIL:
1262 break;
1263
1264 default:
1265 bfa_sm_fault(ioc, event);
1266 }
1267}
1268
1269static void
1270bfa_iocpf_sm_fail_entry(struct bfa_iocpf_s *iocpf)
1271{
5a0adaed 1272 bfa_trc(iocpf->ioc, 0);
7725ccfd
JH		 1273}
1274
5fbe25c7 1275/*
a36c61f9 1276 * IOC is in failed state.
7725ccfd
JH		 1277 */
1278static void
a36c61f9 1279bfa_iocpf_sm_fail(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
7725ccfd 1280{
a36c61f9
KG		 1281 struct bfa_ioc_s *ioc = iocpf->ioc;
1282
7725ccfd
JH		 1283 bfa_trc(ioc, event);
1284
1285 switch (event) {
a36c61f9 1286 case IOCPF_E_DISABLE:
a36c61f9 1287 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
7725ccfd
JH		 1288 break;
1289
7725ccfd
JH		 1290 default:
1291 bfa_sm_fault(ioc, event);
1292 }
1293}
1294
5fbe25c7 1295/*
df0f1933 1296 * BFA IOC private functions
7725ccfd
JH		 1297 */
1298
d37779f8
KG		 1299/*
1300 * Notify common modules registered for notification.
1301 */
7725ccfd 1302static void
d37779f8 1303bfa_ioc_event_notify(struct bfa_ioc_s *ioc, enum bfa_ioc_event_e event)
7725ccfd 1304{
d37779f8
KG		 1305 struct bfa_ioc_notify_s *notify;
1306 struct list_head *qe;
7725ccfd 1307
d37779f8
KG		 1308 list_for_each(qe, &ioc->notify_q) {
1309 notify = (struct bfa_ioc_notify_s *)qe;
1310 notify->cbfn(notify->cbarg, event);
7725ccfd
JH		 1311 }
1312}
1313
d37779f8
KG		 1314static void
1315bfa_ioc_disable_comp(struct bfa_ioc_s *ioc)
1316{
1317 ioc->cbfn->disable_cbfn(ioc->bfa);
1318 bfa_ioc_event_notify(ioc, BFA_IOC_E_DISABLED);
1319}
1320
0a20de44 1321bfa_boolean_t
53440260 1322bfa_ioc_sem_get(void __iomem *sem_reg)
7725ccfd 1323{
0a20de44
KG		 1324 u32 r32;
1325 int cnt = 0;
a36c61f9 1326#define BFA_SEM_SPINCNT 3000
7725ccfd 1327
53440260 1328 r32 = readl(sem_reg);
0a20de44 1329
11189208 1330 while ((r32 & 1) && (cnt < BFA_SEM_SPINCNT)) {
7725ccfd 1331 cnt++;
6a18b167 1332 udelay(2);
53440260 1333 r32 = readl(sem_reg);
0a20de44
KG		 1334 }
1335
11189208 1336 if (!(r32 & 1))
0a20de44
KG		 1337 return BFA_TRUE;
1338
0a20de44 1339 return BFA_FALSE;
7725ccfd
JH		 1340}
1341
7725ccfd
JH		 1342static void
1343bfa_ioc_hw_sem_get(struct bfa_ioc_s *ioc)
1344{
a36c61f9 1345 u32 r32;
7725ccfd 1346
5fbe25c7 1347 /*
7725ccfd 1348 * First read to the semaphore register will return 0, subsequent reads
0a20de44 1349 * will return 1. Semaphore is released by writing 1 to the register
7725ccfd 1350 */
53440260 1351 r32 = readl(ioc->ioc_regs.ioc_sem_reg);
5a0adaed
KG		 1352 if (r32 == ~0) {
1353 WARN_ON(r32 == ~0);
1354 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEM_ERROR);
1355 return;
1356 }
11189208 1357 if (!(r32 & 1)) {
a36c61f9 1358 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEMLOCKED);
7725ccfd
JH		 1359 return;
1360 }
1361
a36c61f9 1362 bfa_sem_timer_start(ioc);
7725ccfd
JH		 1363}
1364
5fbe25c7 1365/*
7725ccfd
JH		 1366 * Initialize LPU local memory (aka secondary memory / SRAM)
1367 */
1368static void
1369bfa_ioc_lmem_init(struct bfa_ioc_s *ioc)
1370{
a36c61f9
KG		 1371 u32 pss_ctl;
1372 int i;
7725ccfd
JH		 1373#define PSS_LMEM_INIT_TIME 10000
1374
53440260 1375 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
7725ccfd
JH		 1376 pss_ctl &= ~__PSS_LMEM_RESET;
1377 pss_ctl |= __PSS_LMEM_INIT_EN;
a36c61f9
KG		 1378
1379 /*
1380 * i2c workaround 12.5khz clock
1381 */
1382 pss_ctl |= __PSS_I2C_CLK_DIV(3UL);
53440260 1383 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
7725ccfd 1384
5fbe25c7 1385 /*
7725ccfd
JH		 1386 * wait for memory initialization to be complete
1387 */
1388 i = 0;
1389 do {
53440260 1390 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
7725ccfd
JH		 1391 i++;
1392 } while (!(pss_ctl & __PSS_LMEM_INIT_DONE) && (i < PSS_LMEM_INIT_TIME));
1393
5fbe25c7 1394 /*
7725ccfd
JH		 1395 * If memory initialization is not successful, IOC timeout will catch
1396 * such failures.
1397 */
d4b671c5 1398 WARN_ON(!(pss_ctl & __PSS_LMEM_INIT_DONE));
7725ccfd
JH		 1399 bfa_trc(ioc, pss_ctl);
1400
1401 pss_ctl &= ~(__PSS_LMEM_INIT_DONE | __PSS_LMEM_INIT_EN);
53440260 1402 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
7725ccfd
JH		 1403}
1404
1405static void
1406bfa_ioc_lpu_start(struct bfa_ioc_s *ioc)
1407{
a36c61f9 1408 u32 pss_ctl;
7725ccfd 1409
5fbe25c7 1410 /*
7725ccfd
JH		 1411 * Take processor out of reset.
1412 */
53440260 1413 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
7725ccfd
JH		 1414 pss_ctl &= ~__PSS_LPU0_RESET;
1415
53440260 1416 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
7725ccfd
JH		 1417}
1418
1419static void
1420bfa_ioc_lpu_stop(struct bfa_ioc_s *ioc)
1421{
a36c61f9 1422 u32 pss_ctl;
7725ccfd 1423
5fbe25c7 1424 /*
7725ccfd
JH		 1425 * Put processors in reset.
1426 */
53440260 1427 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
7725ccfd
JH		 1428 pss_ctl |= (__PSS_LPU0_RESET | __PSS_LPU1_RESET);
1429
53440260 1430 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
7725ccfd
JH		 1431}
1432
5fbe25c7 1433/*
7725ccfd
JH		 1434 * Get driver and firmware versions.
1435 */
0a20de44 1436void
7725ccfd
JH		 1437bfa_ioc_fwver_get(struct bfa_ioc_s *ioc, struct bfi_ioc_image_hdr_s *fwhdr)
1438{
a36c61f9
KG		 1439 u32 pgnum, pgoff;
1440 u32 loff = 0;
1441 int i;
1442 u32 *fwsig = (u32 *) fwhdr;
7725ccfd 1443
f7f73812
MZ		 1444 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, loff);
1445 pgoff = PSS_SMEM_PGOFF(loff);
53440260 1446 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
7725ccfd
JH		 1447
1448 for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr_s) / sizeof(u32));
1449 i++) {
a36c61f9
KG		 1450 fwsig[i] =
1451 bfa_mem_read(ioc->ioc_regs.smem_page_start, loff);
7725ccfd
JH		 1452 loff += sizeof(u32);
1453 }
1454}
1455
5fbe25c7 1456/*
7725ccfd
JH		 1457 * Returns TRUE if same.
1458 */
0a20de44 1459bfa_boolean_t
7725ccfd
JH		 1460bfa_ioc_fwver_cmp(struct bfa_ioc_s *ioc, struct bfi_ioc_image_hdr_s *fwhdr)
1461{
1462 struct bfi_ioc_image_hdr_s *drv_fwhdr;
a36c61f9 1463 int i;
7725ccfd 1464
293f82d5 1465 drv_fwhdr = (struct bfi_ioc_image_hdr_s *)
11189208 1466 bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), 0);
7725ccfd
JH		 1467
1468 for (i = 0; i < BFI_IOC_MD5SUM_SZ; i++) {
881c1b3c 1469 if (fwhdr->md5sum[i] != cpu_to_le32(drv_fwhdr->md5sum[i])) {
7725ccfd
JH		 1470 bfa_trc(ioc, i);
1471 bfa_trc(ioc, fwhdr->md5sum[i]);
1472 bfa_trc(ioc, drv_fwhdr->md5sum[i]);
1473 return BFA_FALSE;
1474 }
1475 }
1476
1477 bfa_trc(ioc, fwhdr->md5sum[0]);
1478 return BFA_TRUE;
1479}
1480
5fbe25c7 1481/*
7725ccfd
JH		 1482 * Return true if current running version is valid. Firmware signature and
1483 * execution context (driver/bios) must match.
1484 */
a36c61f9
KG		 1485static bfa_boolean_t
1486bfa_ioc_fwver_valid(struct bfa_ioc_s *ioc, u32 boot_env)
7725ccfd
JH		 1487{
1488 struct bfi_ioc_image_hdr_s fwhdr, *drv_fwhdr;
1489
7725ccfd 1490 bfa_ioc_fwver_get(ioc, &fwhdr);
293f82d5 1491 drv_fwhdr = (struct bfi_ioc_image_hdr_s *)
11189208 1492 bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), 0);
7725ccfd 1493
881c1b3c 1494 if (fwhdr.signature != cpu_to_le32(drv_fwhdr->signature)) {
7725ccfd
JH		 1495 bfa_trc(ioc, fwhdr.signature);
1496 bfa_trc(ioc, drv_fwhdr->signature);
1497 return BFA_FALSE;
1498 }
1499
11189208
KG		 1500 if (swab32(fwhdr.bootenv) != boot_env) {
1501 bfa_trc(ioc, fwhdr.bootenv);
a36c61f9 1502 bfa_trc(ioc, boot_env);
7725ccfd
JH		 1503 return BFA_FALSE;
1504 }
1505
1506 return bfa_ioc_fwver_cmp(ioc, &fwhdr);
1507}
1508
5fbe25c7 1509/*
7725ccfd
JH		 1510 * Conditionally flush any pending message from firmware at start.
1511 */
1512static void
1513bfa_ioc_msgflush(struct bfa_ioc_s *ioc)
1514{
a36c61f9 1515 u32 r32;
7725ccfd 1516
53440260 1517 r32 = readl(ioc->ioc_regs.lpu_mbox_cmd);
7725ccfd 1518 if (r32)
53440260 1519 writel(1, ioc->ioc_regs.lpu_mbox_cmd);
7725ccfd
JH		 1520}
1521
7725ccfd
JH		 1522static void
1523bfa_ioc_hwinit(struct bfa_ioc_s *ioc, bfa_boolean_t force)
1524{
1525 enum bfi_ioc_state ioc_fwstate;
a36c61f9
KG		 1526 bfa_boolean_t fwvalid;
1527 u32 boot_type;
1528 u32 boot_env;
7725ccfd 1529
c679b599 1530 ioc_fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc);
7725ccfd
JH		 1531
1532 if (force)
1533 ioc_fwstate = BFI_IOC_UNINIT;
1534
1535 bfa_trc(ioc, ioc_fwstate);
1536
11189208
KG		 1537 boot_type = BFI_FWBOOT_TYPE_NORMAL;
1538 boot_env = BFI_FWBOOT_ENV_OS;
a36c61f9 1539
5fbe25c7 1540 /*
7725ccfd
JH		 1541 * check if firmware is valid
1542 */
1543 fwvalid = (ioc_fwstate == BFI_IOC_UNINIT) ?
a36c61f9 1544 BFA_FALSE : bfa_ioc_fwver_valid(ioc, boot_env);
7725ccfd
JH		 1545
1546 if (!fwvalid) {
a36c61f9 1547 bfa_ioc_boot(ioc, boot_type, boot_env);
8b070b4a 1548 bfa_ioc_poll_fwinit(ioc);
7725ccfd
JH		 1549 return;
1550 }
1551
5fbe25c7 1552 /*
7725ccfd
JH		 1553 * If hardware initialization is in progress (initialized by other IOC),
1554 * just wait for an initialization completion interrupt.
1555 */
1556 if (ioc_fwstate == BFI_IOC_INITING) {
775c7742 1557 bfa_ioc_poll_fwinit(ioc);
7725ccfd
JH		 1558 return;
1559 }
1560
5fbe25c7 1561 /*
7725ccfd
JH		 1562 * If IOC function is disabled and firmware version is same,
1563 * just re-enable IOC.
07b28386
JH		 1564 *
1565 * If option rom, IOC must not be in operational state. With
1566 * convergence, IOC will be in operational state when 2nd driver
1567 * is loaded.
7725ccfd 1568 */
8f4bfadd 1569 if (ioc_fwstate == BFI_IOC_DISABLED || ioc_fwstate == BFI_IOC_OP) {
7725ccfd 1570
5fbe25c7 1571 /*
7725ccfd
JH		 1572 * When using MSI-X any pending firmware ready event should
1573 * be flushed. Otherwise MSI-X interrupts are not delivered.
1574 */
1575 bfa_ioc_msgflush(ioc);
a36c61f9 1576 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FWREADY);
7725ccfd
JH		 1577 return;
1578 }
1579
5fbe25c7 1580 /*
7725ccfd
JH		 1581 * Initialize the h/w for any other states.
1582 */
a36c61f9 1583 bfa_ioc_boot(ioc, boot_type, boot_env);
8b070b4a 1584 bfa_ioc_poll_fwinit(ioc);
7725ccfd
JH		 1585}
1586
1587static void
1588bfa_ioc_timeout(void *ioc_arg)
1589{
a36c61f9 1590 struct bfa_ioc_s *ioc = (struct bfa_ioc_s *) ioc_arg;
7725ccfd
JH		 1591
1592 bfa_trc(ioc, 0);
1593 bfa_fsm_send_event(ioc, IOC_E_TIMEOUT);
1594}
1595
1596void
1597bfa_ioc_mbox_send(struct bfa_ioc_s *ioc, void *ioc_msg, int len)
1598{
a36c61f9
KG		 1599 u32 *msgp = (u32 *) ioc_msg;
1600 u32 i;
7725ccfd
JH		 1601
1602 bfa_trc(ioc, msgp[0]);
1603 bfa_trc(ioc, len);
1604
d4b671c5 1605 WARN_ON(len > BFI_IOC_MSGLEN_MAX);
7725ccfd
JH		 1606
1607 /*
1608 * first write msg to mailbox registers
1609 */
1610 for (i = 0; i < len / sizeof(u32); i++)
53440260
JH		 1611 writel(cpu_to_le32(msgp[i]),
1612 ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
7725ccfd
JH		 1613
1614 for (; i < BFI_IOC_MSGLEN_MAX / sizeof(u32); i++)
53440260 1615 writel(0, ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
7725ccfd
JH		 1616
1617 /*
1618 * write 1 to mailbox CMD to trigger LPU event
1619 */
53440260
JH		 1620 writel(1, ioc->ioc_regs.hfn_mbox_cmd);
1621 (void) readl(ioc->ioc_regs.hfn_mbox_cmd);
7725ccfd
JH		 1622}
1623
1624static void
1625bfa_ioc_send_enable(struct bfa_ioc_s *ioc)
1626{
1627 struct bfi_ioc_ctrl_req_s enable_req;
f16a1750 1628 struct timeval tv;
7725ccfd
JH		 1629
1630 bfi_h2i_set(enable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_ENABLE_REQ,
1631 bfa_ioc_portid(ioc));
d37779f8 1632 enable_req.clscode = cpu_to_be16(ioc->clscode);
f16a1750 1633 do_gettimeofday(&tv);
ba816ea8 1634 enable_req.tv_sec = be32_to_cpu(tv.tv_sec);
7725ccfd
JH		 1635 bfa_ioc_mbox_send(ioc, &enable_req, sizeof(struct bfi_ioc_ctrl_req_s));
1636}
1637
1638static void
1639bfa_ioc_send_disable(struct bfa_ioc_s *ioc)
1640{
1641 struct bfi_ioc_ctrl_req_s disable_req;
1642
1643 bfi_h2i_set(disable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_DISABLE_REQ,
1644 bfa_ioc_portid(ioc));
1645 bfa_ioc_mbox_send(ioc, &disable_req, sizeof(struct bfi_ioc_ctrl_req_s));
1646}
1647
1648static void
1649bfa_ioc_send_getattr(struct bfa_ioc_s *ioc)
1650{
a36c61f9 1651 struct bfi_ioc_getattr_req_s attr_req;
7725ccfd
JH		 1652
1653 bfi_h2i_set(attr_req.mh, BFI_MC_IOC, BFI_IOC_H2I_GETATTR_REQ,
1654 bfa_ioc_portid(ioc));
1655 bfa_dma_be_addr_set(attr_req.attr_addr, ioc->attr_dma.pa);
1656 bfa_ioc_mbox_send(ioc, &attr_req, sizeof(attr_req));
1657}
1658
1659static void
1660bfa_ioc_hb_check(void *cbarg)
1661{
0a20de44 1662 struct bfa_ioc_s *ioc = cbarg;
a36c61f9 1663 u32 hb_count;
7725ccfd 1664
53440260 1665 hb_count = readl(ioc->ioc_regs.heartbeat);
7725ccfd 1666 if (ioc->hb_count == hb_count) {
7725ccfd
JH		 1667 bfa_ioc_recover(ioc);
1668 return;
0a20de44
KG		 1669 } else {
1670 ioc->hb_count = hb_count;
7725ccfd
JH		 1671 }
1672
1673 bfa_ioc_mbox_poll(ioc);
a36c61f9 1674 bfa_hb_timer_start(ioc);
7725ccfd
JH		 1675}
1676
1677static void
1678bfa_ioc_hb_monitor(struct bfa_ioc_s *ioc)
1679{
53440260 1680 ioc->hb_count = readl(ioc->ioc_regs.heartbeat);
a36c61f9 1681 bfa_hb_timer_start(ioc);
7725ccfd
JH		 1682}
1683
5fbe25c7 1684/*
a36c61f9 1685 * Initiate a full firmware download.
7725ccfd
JH		 1686 */
1687static void
1688bfa_ioc_download_fw(struct bfa_ioc_s *ioc, u32 boot_type,
a36c61f9 1689 u32 boot_env)
7725ccfd 1690{
a36c61f9
KG		 1691 u32 *fwimg;
1692 u32 pgnum, pgoff;
1693 u32 loff = 0;
1694 u32 chunkno = 0;
1695 u32 i;
11189208 1696 u32 asicmode;
7725ccfd 1697
11189208
KG		 1698 bfa_trc(ioc, bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc)));
1699 fwimg = bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), chunkno);
7725ccfd 1700
f7f73812
MZ		 1701 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, loff);
1702 pgoff = PSS_SMEM_PGOFF(loff);
7725ccfd 1703
53440260 1704 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
7725ccfd 1705
11189208 1706 for (i = 0; i < bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc)); i++) {
7725ccfd 1707
0a20de44
KG		 1708 if (BFA_IOC_FLASH_CHUNK_NO(i) != chunkno) {
1709 chunkno = BFA_IOC_FLASH_CHUNK_NO(i);
11189208 1710 fwimg = bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc),
0a20de44 1711 BFA_IOC_FLASH_CHUNK_ADDR(chunkno));
7725ccfd
JH		 1712 }
1713
5fbe25c7 1714 /*
7725ccfd
JH		 1715 * write smem
1716 */
1717 bfa_mem_write(ioc->ioc_regs.smem_page_start, loff,
881c1b3c 1718 cpu_to_le32(fwimg[BFA_IOC_FLASH_OFFSET_IN_CHUNK(i)]));
7725ccfd
JH		 1719
1720 loff += sizeof(u32);
1721
5fbe25c7 1722 /*
7725ccfd
JH		 1723 * handle page offset wrap around
1724 */
1725 loff = PSS_SMEM_PGOFF(loff);
1726 if (loff == 0) {
1727 pgnum++;
53440260 1728 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
7725ccfd
JH		 1729 }
1730 }
1731
f7f73812
MZ		 1732 writel(PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, 0),
1733 ioc->ioc_regs.host_page_num_fn);
13cc20c5
KG		 1734
1735 /*
11189208
KG		 1736 * Set boot type and device mode at the end.
1737 */
1738 asicmode = BFI_FWBOOT_DEVMODE(ioc->asic_gen, ioc->asic_mode,
1739 ioc->port0_mode, ioc->port1_mode);
1740 bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_FWBOOT_DEVMODE_OFF,
1741 swab32(asicmode));
1742 bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_FWBOOT_TYPE_OFF,
53440260 1743 swab32(boot_type));
11189208 1744 bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_FWBOOT_ENV_OFF,
53440260 1745 swab32(boot_env));
a36c61f9
KG		 1746}
1747
a36c61f9 1748
5fbe25c7 1749/*
a36c61f9
KG		 1750 * Update BFA configuration from firmware configuration.
1751 */
1752static void
1753bfa_ioc_getattr_reply(struct bfa_ioc_s *ioc)
1754{
1755 struct bfi_ioc_attr_s *attr = ioc->attr;
1756
ba816ea8
JH		 1757 attr->adapter_prop = be32_to_cpu(attr->adapter_prop);
1758 attr->card_type = be32_to_cpu(attr->card_type);
1759 attr->maxfrsize = be16_to_cpu(attr->maxfrsize);
5a0adaed 1760 ioc->fcmode = (attr->port_mode == BFI_PORT_MODE_FC);
ea5d7c9e 1761 attr->mfg_year = be16_to_cpu(attr->mfg_year);
a36c61f9
KG		 1762
1763 bfa_fsm_send_event(ioc, IOC_E_FWRSP_GETATTR);
1764}
1765
5fbe25c7 1766/*
a36c61f9
KG		 1767 * Attach time initialization of mbox logic.
1768 */
1769static void
1770bfa_ioc_mbox_attach(struct bfa_ioc_s *ioc)
1771{
1772 struct bfa_ioc_mbox_mod_s *mod = &ioc->mbox_mod;
1773 int mc;
1774
1775 INIT_LIST_HEAD(&mod->cmd_q);
1776 for (mc = 0; mc < BFI_MC_MAX; mc++) {
1777 mod->mbhdlr[mc].cbfn = NULL;
1778 mod->mbhdlr[mc].cbarg = ioc->bfa;
1779 }
1780}
1781
5fbe25c7 1782/*
a36c61f9
KG		 1783 * Mbox poll timer -- restarts any pending mailbox requests.
1784 */
1785static void
1786bfa_ioc_mbox_poll(struct bfa_ioc_s *ioc)
1787{
1788 struct bfa_ioc_mbox_mod_s *mod = &ioc->mbox_mod;
1789 struct bfa_mbox_cmd_s *cmd;
1790 u32 stat;
1791
5fbe25c7 1792 /*
a36c61f9
KG		 1793 * If no command pending, do nothing
1794 */
1795 if (list_empty(&mod->cmd_q))
1796 return;
1797
5fbe25c7 1798 /*
a36c61f9
KG		 1799 * If previous command is not yet fetched by firmware, do nothing
1800 */
53440260 1801 stat = readl(ioc->ioc_regs.hfn_mbox_cmd);
a36c61f9
KG		 1802 if (stat)
1803 return;
1804
5fbe25c7 1805 /*
a36c61f9
KG		 1806 * Enqueue command to firmware.
1807 */
1808 bfa_q_deq(&mod->cmd_q, &cmd);
1809 bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg));
1810}
1811
5fbe25c7 1812/*
a36c61f9
KG		 1813 * Cleanup any pending requests.
1814 */
1815static void
8b070b4a 1816bfa_ioc_mbox_flush(struct bfa_ioc_s *ioc)
a36c61f9
KG		 1817{
1818 struct bfa_ioc_mbox_mod_s *mod = &ioc->mbox_mod;
1819 struct bfa_mbox_cmd_s *cmd;
1820
1821 while (!list_empty(&mod->cmd_q))
1822 bfa_q_deq(&mod->cmd_q, &cmd);
1823}
1824
5fbe25c7 1825/*
a36c61f9
KG		 1826 * Read data from SMEM to host through PCI memmap
1827 *
1828 * @param[in] ioc memory for IOC
1829 * @param[in] tbuf app memory to store data from smem
1830 * @param[in] soff smem offset
1831 * @param[in] sz size of smem in bytes
1832 */
1833static bfa_status_t
1834bfa_ioc_smem_read(struct bfa_ioc_s *ioc, void *tbuf, u32 soff, u32 sz)
1835{
50444a34
M		 1836 u32 pgnum, loff;
1837 __be32 r32;
a36c61f9
KG		 1838 int i, len;
1839 u32 *buf = tbuf;
1840
f7f73812
MZ		 1841 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, soff);
1842 loff = PSS_SMEM_PGOFF(soff);
a36c61f9
KG		 1843 bfa_trc(ioc, pgnum);
1844 bfa_trc(ioc, loff);
1845 bfa_trc(ioc, sz);
1846
1847 /*
1848 * Hold semaphore to serialize pll init and fwtrc.
1849 */
1850 if (BFA_FALSE == bfa_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg)) {
1851 bfa_trc(ioc, 0);
1852 return BFA_STATUS_FAILED;
1853 }
1854
53440260 1855 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
a36c61f9
KG		 1856
1857 len = sz/sizeof(u32);
1858 bfa_trc(ioc, len);
1859 for (i = 0; i < len; i++) {
1860 r32 = bfa_mem_read(ioc->ioc_regs.smem_page_start, loff);
ba134078 1861 buf[i] = swab32(r32);
a36c61f9
KG		 1862 loff += sizeof(u32);
1863
5fbe25c7 1864 /*
a36c61f9
KG		 1865 * handle page offset wrap around
1866 */
1867 loff = PSS_SMEM_PGOFF(loff);
1868 if (loff == 0) {
1869 pgnum++;
53440260 1870 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
a36c61f9
KG		 1871 }
1872 }
f7f73812
MZ		 1873 writel(PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, 0),
1874 ioc->ioc_regs.host_page_num_fn);
a36c61f9
KG		 1875 /*
1876 * release semaphore.
1877 */
5a0adaed 1878 readl(ioc->ioc_regs.ioc_init_sem_reg);
f7f73812 1879 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
a36c61f9
KG		 1880
1881 bfa_trc(ioc, pgnum);
1882 return BFA_STATUS_OK;
1883}
1884
5fbe25c7 1885/*
a36c61f9
KG		 1886 * Clear SMEM data from host through PCI memmap
1887 *
1888 * @param[in] ioc memory for IOC
1889 * @param[in] soff smem offset
1890 * @param[in] sz size of smem in bytes
1891 */
1892static bfa_status_t
1893bfa_ioc_smem_clr(struct bfa_ioc_s *ioc, u32 soff, u32 sz)
1894{
1895 int i, len;
1896 u32 pgnum, loff;
1897
f7f73812
MZ		 1898 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, soff);
1899 loff = PSS_SMEM_PGOFF(soff);
a36c61f9
KG		 1900 bfa_trc(ioc, pgnum);
1901 bfa_trc(ioc, loff);
1902 bfa_trc(ioc, sz);
1903
1904 /*
1905 * Hold semaphore to serialize pll init and fwtrc.
1906 */
1907 if (BFA_FALSE == bfa_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg)) {
1908 bfa_trc(ioc, 0);
1909 return BFA_STATUS_FAILED;
1910 }
1911
53440260 1912 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
a36c61f9
KG		 1913
1914 len = sz/sizeof(u32); /* len in words */
1915 bfa_trc(ioc, len);
1916 for (i = 0; i < len; i++) {
1917 bfa_mem_write(ioc->ioc_regs.smem_page_start, loff, 0);
1918 loff += sizeof(u32);
1919
5fbe25c7 1920 /*
a36c61f9
KG		 1921 * handle page offset wrap around
1922 */
1923 loff = PSS_SMEM_PGOFF(loff);
1924 if (loff == 0) {
1925 pgnum++;
53440260 1926 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
a36c61f9
KG		 1927 }
1928 }
f7f73812
MZ		 1929 writel(PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, 0),
1930 ioc->ioc_regs.host_page_num_fn);
a36c61f9
KG		 1931
1932 /*
1933 * release semaphore.
1934 */
5a0adaed 1935 readl(ioc->ioc_regs.ioc_init_sem_reg);
f7f73812 1936 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
a36c61f9
KG		 1937 bfa_trc(ioc, pgnum);
1938 return BFA_STATUS_OK;
7725ccfd
JH		 1939}
1940
4e78efef
KG		 1941static void
1942bfa_ioc_fail_notify(struct bfa_ioc_s *ioc)
1943{
4e78efef
KG		 1944 struct bfad_s *bfad = (struct bfad_s *)ioc->bfa->bfad;
1945
8f4bfadd 1946 /*
4e78efef
KG		 1947 * Notify driver and common modules registered for notification.
1948 */
1949 ioc->cbfn->hbfail_cbfn(ioc->bfa);
d37779f8 1950 bfa_ioc_event_notify(ioc, BFA_IOC_E_FAILED);
4e78efef
KG		 1951
1952 bfa_ioc_debug_save_ftrc(ioc);
1953
1954 BFA_LOG(KERN_CRIT, bfad, bfa_log_level,
1955 "Heart Beat of IOC has failed\n");
7826f304 1956 bfa_ioc_aen_post(ioc, BFA_IOC_AEN_HBFAIL);
4e78efef
KG		 1957
1958}
1959
7725ccfd 1960static void
a36c61f9 1961bfa_ioc_pf_fwmismatch(struct bfa_ioc_s *ioc)
7725ccfd 1962{
a36c61f9 1963 struct bfad_s *bfad = (struct bfad_s *)ioc->bfa->bfad;
5fbe25c7 1964 /*
a36c61f9 1965 * Provide enable completion callback.
7725ccfd 1966 */
a36c61f9 1967 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
88166242 1968 BFA_LOG(KERN_WARNING, bfad, bfa_log_level,
a36c61f9
KG		 1969 "Running firmware version is incompatible "
1970 "with the driver version\n");
7826f304 1971 bfa_ioc_aen_post(ioc, BFA_IOC_AEN_FWMISMATCH);
a36c61f9 1972}
7725ccfd 1973
a36c61f9
KG		 1974bfa_status_t
1975bfa_ioc_pll_init(struct bfa_ioc_s *ioc)
7725ccfd 1976{
7725ccfd 1977
a36c61f9
KG		 1978 /*
1979 * Hold semaphore so that nobody can access the chip during init.
1980 */
1981 bfa_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg);
7725ccfd 1982
a36c61f9
KG		 1983 bfa_ioc_pll_init_asic(ioc);
1984
1985 ioc->pllinit = BFA_TRUE;
8919678e
KG		 1986
1987 /*
1988 * Initialize LMEM
1989 */
1990 bfa_ioc_lmem_init(ioc);
1991
a36c61f9
KG		 1992 /*
1993 * release semaphore.
1994 */
5a0adaed 1995 readl(ioc->ioc_regs.ioc_init_sem_reg);
f7f73812 1996 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
a36c61f9
KG		 1997
1998 return BFA_STATUS_OK;
1999}
7725ccfd 2000
5fbe25c7 2001/*
7725ccfd
JH		 2002 * Interface used by diag module to do firmware boot with memory test
2003 * as the entry vector.
2004 */
2005void
a36c61f9 2006bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type, u32 boot_env)
7725ccfd 2007{
7725ccfd
JH		 2008 bfa_ioc_stats(ioc, ioc_boots);
2009
2010 if (bfa_ioc_pll_init(ioc) != BFA_STATUS_OK)
2011 return;
2012
5fbe25c7 2013 /*
7725ccfd
JH		 2014 * Initialize IOC state of all functions on a chip reset.
2015 */
11189208 2016 if (boot_type == BFI_FWBOOT_TYPE_MEMTEST) {
c679b599
VMG		 2017 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_MEMTEST);
2018 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_MEMTEST);
7725ccfd 2019 } else {
c679b599
VMG		 2020 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_INITING);
2021 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_INITING);
7725ccfd
JH		 2022 }
2023
07b28386 2024 bfa_ioc_msgflush(ioc);
a36c61f9 2025 bfa_ioc_download_fw(ioc, boot_type, boot_env);
7725ccfd
JH		 2026 bfa_ioc_lpu_start(ioc);
2027}
2028
5fbe25c7 2029/*
7725ccfd
JH		 2030 * Enable/disable IOC failure auto recovery.
2031 */
2032void
2033bfa_ioc_auto_recover(bfa_boolean_t auto_recover)
2034{
2f9b8857 2035 bfa_auto_recover = auto_recover;
7725ccfd
JH		 2036}
2037
2038
a36c61f9 2039
7725ccfd
JH		 2040bfa_boolean_t
2041bfa_ioc_is_operational(struct bfa_ioc_s *ioc)
2042{
2043 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_op);
2044}
2045
a36c61f9
KG		 2046bfa_boolean_t
2047bfa_ioc_is_initialized(struct bfa_ioc_s *ioc)
2048{
c679b599 2049 u32 r32 = bfa_ioc_get_cur_ioc_fwstate(ioc);
a36c61f9
KG		 2050
2051 return ((r32 != BFI_IOC_UNINIT) &&
2052 (r32 != BFI_IOC_INITING) &&
2053 (r32 != BFI_IOC_MEMTEST));
2054}
2055
11189208 2056bfa_boolean_t
7725ccfd
JH		 2057bfa_ioc_msgget(struct bfa_ioc_s *ioc, void *mbmsg)
2058{
50444a34 2059 __be32 *msgp = mbmsg;
a36c61f9
KG		 2060 u32 r32;
2061 int i;
7725ccfd 2062
11189208
KG		 2063 r32 = readl(ioc->ioc_regs.lpu_mbox_cmd);
2064 if ((r32 & 1) == 0)
2065 return BFA_FALSE;
2066
5fbe25c7 2067 /*
7725ccfd
JH		 2068 * read the MBOX msg
2069 */
2070 for (i = 0; i < (sizeof(union bfi_ioc_i2h_msg_u) / sizeof(u32));
2071 i++) {
53440260 2072 r32 = readl(ioc->ioc_regs.lpu_mbox +
7725ccfd 2073 i * sizeof(u32));
ba816ea8 2074 msgp[i] = cpu_to_be32(r32);
7725ccfd
JH		 2075 }
2076
5fbe25c7 2077 /*
7725ccfd
JH		 2078 * turn off mailbox interrupt by clearing mailbox status
2079 */
53440260
JH		 2080 writel(1, ioc->ioc_regs.lpu_mbox_cmd);
2081 readl(ioc->ioc_regs.lpu_mbox_cmd);
11189208
KG		 2082
2083 return BFA_TRUE;
7725ccfd
JH		 2084}
2085
2086void
2087bfa_ioc_isr(struct bfa_ioc_s *ioc, struct bfi_mbmsg_s *m)
2088{
a36c61f9
KG		 2089 union bfi_ioc_i2h_msg_u *msg;
2090 struct bfa_iocpf_s *iocpf = &ioc->iocpf;
7725ccfd 2091
a36c61f9 2092 msg = (union bfi_ioc_i2h_msg_u *) m;
7725ccfd
JH		 2093
2094 bfa_ioc_stats(ioc, ioc_isrs);
2095
2096 switch (msg->mh.msg_id) {
2097 case BFI_IOC_I2H_HBEAT:
2098 break;
2099
7725ccfd 2100 case BFI_IOC_I2H_ENABLE_REPLY:
1a4d8e1b
KG		 2101 ioc->port_mode = ioc->port_mode_cfg =
2102 (enum bfa_mode_s)msg->fw_event.port_mode;
2103 ioc->ad_cap_bm = msg->fw_event.cap_bm;
a36c61f9 2104 bfa_fsm_send_event(iocpf, IOCPF_E_FWRSP_ENABLE);
7725ccfd
JH		 2105 break;
2106
2107 case BFI_IOC_I2H_DISABLE_REPLY:
a36c61f9 2108 bfa_fsm_send_event(iocpf, IOCPF_E_FWRSP_DISABLE);
7725ccfd
JH		 2109 break;
2110
2111 case BFI_IOC_I2H_GETATTR_REPLY:
2112 bfa_ioc_getattr_reply(ioc);
2113 break;
2114
2115 default:
2116 bfa_trc(ioc, msg->mh.msg_id);
d4b671c5 2117 WARN_ON(1);
7725ccfd
JH		 2118 }
2119}
2120
5fbe25c7 2121/*
7725ccfd
JH		 2122 * IOC attach time initialization and setup.
2123 *
2124 * @param[in] ioc memory for IOC
2125 * @param[in] bfa driver instance structure
7725ccfd
JH		 2126 */
2127void
2128bfa_ioc_attach(struct bfa_ioc_s *ioc, void *bfa, struct bfa_ioc_cbfn_s *cbfn,
a36c61f9
KG		 2129 struct bfa_timer_mod_s *timer_mod)
2130{
2131 ioc->bfa = bfa;
2132 ioc->cbfn = cbfn;
2133 ioc->timer_mod = timer_mod;
2134 ioc->fcmode = BFA_FALSE;
2135 ioc->pllinit = BFA_FALSE;
7725ccfd 2136 ioc->dbg_fwsave_once = BFA_TRUE;
a36c61f9 2137 ioc->iocpf.ioc = ioc;
7725ccfd
JH		 2138
2139 bfa_ioc_mbox_attach(ioc);
d37779f8 2140 INIT_LIST_HEAD(&ioc->notify_q);
7725ccfd 2141
a36c61f9
KG		 2142 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
2143 bfa_fsm_send_event(ioc, IOC_E_RESET);
7725ccfd
JH		 2144}
2145
5fbe25c7 2146/*
7725ccfd
JH		 2147 * Driver detach time IOC cleanup.
2148 */
2149void
2150bfa_ioc_detach(struct bfa_ioc_s *ioc)
2151{
2152 bfa_fsm_send_event(ioc, IOC_E_DETACH);
3350d98d 2153 INIT_LIST_HEAD(&ioc->notify_q);
7725ccfd
JH		 2154}
2155
5fbe25c7 2156/*
7725ccfd
JH		 2157 * Setup IOC PCI properties.
2158 *
2159 * @param[in] pcidev PCI device information for this IOC
2160 */
2161void
2162bfa_ioc_pci_init(struct bfa_ioc_s *ioc, struct bfa_pcidev_s *pcidev,
d37779f8 2163 enum bfi_pcifn_class clscode)
7725ccfd 2164{
d37779f8 2165 ioc->clscode = clscode;
a36c61f9 2166 ioc->pcidev = *pcidev;
11189208
KG		 2167
2168 /*
2169 * Initialize IOC and device personality
2170 */
2171 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_FC;
2172 ioc->asic_mode = BFI_ASIC_MODE_FC;
2173
2174 switch (pcidev->device_id) {
2175 case BFA_PCI_DEVICE_ID_FC_8G1P:
2176 case BFA_PCI_DEVICE_ID_FC_8G2P:
2177 ioc->asic_gen = BFI_ASIC_GEN_CB;
1a4d8e1b
KG		 2178 ioc->fcmode = BFA_TRUE;
2179 ioc->port_mode = ioc->port_mode_cfg = BFA_MODE_HBA;
2180 ioc->ad_cap_bm = BFA_CM_HBA;
11189208
KG		 2181 break;
2182
2183 case BFA_PCI_DEVICE_ID_CT:
2184 ioc->asic_gen = BFI_ASIC_GEN_CT;
2185 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_ETH;
2186 ioc->asic_mode = BFI_ASIC_MODE_ETH;
1a4d8e1b
KG		 2187 ioc->port_mode = ioc->port_mode_cfg = BFA_MODE_CNA;
2188 ioc->ad_cap_bm = BFA_CM_CNA;
11189208
KG		 2189 break;
2190
2191 case BFA_PCI_DEVICE_ID_CT_FC:
2192 ioc->asic_gen = BFI_ASIC_GEN_CT;
1a4d8e1b
KG		 2193 ioc->fcmode = BFA_TRUE;
2194 ioc->port_mode = ioc->port_mode_cfg = BFA_MODE_HBA;
2195 ioc->ad_cap_bm = BFA_CM_HBA;
11189208
KG		 2196 break;
2197
2198 case BFA_PCI_DEVICE_ID_CT2:
2199 ioc->asic_gen = BFI_ASIC_GEN_CT2;
1a4d8e1b
KG		 2200 if (clscode == BFI_PCIFN_CLASS_FC &&
2201 pcidev->ssid == BFA_PCI_CT2_SSID_FC) {
11189208 2202 ioc->asic_mode = BFI_ASIC_MODE_FC16;
1a4d8e1b
KG		 2203 ioc->fcmode = BFA_TRUE;
2204 ioc->port_mode = ioc->port_mode_cfg = BFA_MODE_HBA;
2205 ioc->ad_cap_bm = BFA_CM_HBA;
2206 } else {
11189208 2207 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_ETH;
1a4d8e1b
KG		 2208 ioc->asic_mode = BFI_ASIC_MODE_ETH;
2209 if (pcidev->ssid == BFA_PCI_CT2_SSID_FCoE) {
2210 ioc->port_mode =
2211 ioc->port_mode_cfg = BFA_MODE_CNA;
2212 ioc->ad_cap_bm = BFA_CM_CNA;
2213 } else {
2214 ioc->port_mode =
2215 ioc->port_mode_cfg = BFA_MODE_NIC;
2216 ioc->ad_cap_bm = BFA_CM_NIC;
2217 }
11189208
KG		 2218 }
2219 break;
2220
2221 default:
2222 WARN_ON(1);
2223 }
7725ccfd 2224
5fbe25c7 2225 /*
0a20de44
KG		 2226 * Set asic specific interfaces. See bfa_ioc_cb.c and bfa_ioc_ct.c
2227 */
11189208 2228 if (ioc->asic_gen == BFI_ASIC_GEN_CB)
0a20de44 2229 bfa_ioc_set_cb_hwif(ioc);
11189208
KG		 2230 else if (ioc->asic_gen == BFI_ASIC_GEN_CT)
2231 bfa_ioc_set_ct_hwif(ioc);
2232 else {
2233 WARN_ON(ioc->asic_gen != BFI_ASIC_GEN_CT2);
2234 bfa_ioc_set_ct2_hwif(ioc);
2235 bfa_ioc_ct2_poweron(ioc);
2236 }
0a20de44 2237
7725ccfd
JH		 2238 bfa_ioc_map_port(ioc);
2239 bfa_ioc_reg_init(ioc);
2240}
2241
5fbe25c7 2242/*
7725ccfd
JH		 2243 * Initialize IOC dma memory
2244 *
2245 * @param[in] dm_kva kernel virtual address of IOC dma memory
2246 * @param[in] dm_pa physical address of IOC dma memory
2247 */
2248void
a36c61f9 2249bfa_ioc_mem_claim(struct bfa_ioc_s *ioc, u8 *dm_kva, u64 dm_pa)
7725ccfd 2250{
5fbe25c7 2251 /*
7725ccfd
JH		 2252 * dma memory for firmware attribute
2253 */
2254 ioc->attr_dma.kva = dm_kva;
2255 ioc->attr_dma.pa = dm_pa;
a36c61f9 2256 ioc->attr = (struct bfi_ioc_attr_s *) dm_kva;
7725ccfd
JH		 2257}
2258
7725ccfd
JH		 2259void
2260bfa_ioc_enable(struct bfa_ioc_s *ioc)
2261{
2262 bfa_ioc_stats(ioc, ioc_enables);
2263 ioc->dbg_fwsave_once = BFA_TRUE;
2264
2265 bfa_fsm_send_event(ioc, IOC_E_ENABLE);
2266}
2267
2268void
2269bfa_ioc_disable(struct bfa_ioc_s *ioc)
2270{
2271 bfa_ioc_stats(ioc, ioc_disables);
2272 bfa_fsm_send_event(ioc, IOC_E_DISABLE);
2273}
2274
881c1b3c
KG		 2275void
2276bfa_ioc_suspend(struct bfa_ioc_s *ioc)
2277{
2278 ioc->dbg_fwsave_once = BFA_TRUE;
2279 bfa_fsm_send_event(ioc, IOC_E_HWERROR);
2280}
7725ccfd 2281
5fbe25c7 2282/*
7725ccfd
JH		 2283 * Initialize memory for saving firmware trace. Driver must initialize
2284 * trace memory before call bfa_ioc_enable().
2285 */
2286void
2287bfa_ioc_debug_memclaim(struct bfa_ioc_s *ioc, void *dbg_fwsave)
2288{
a36c61f9 2289 ioc->dbg_fwsave = dbg_fwsave;
881c1b3c 2290 ioc->dbg_fwsave_len = BFA_DBG_FWTRC_LEN;
7725ccfd
JH		 2291}
2292
5fbe25c7 2293/*
7725ccfd
JH		 2294 * Register mailbox message handler functions
2295 *
2296 * @param[in] ioc IOC instance
2297 * @param[in] mcfuncs message class handler functions
2298 */
2299void
2300bfa_ioc_mbox_register(struct bfa_ioc_s *ioc, bfa_ioc_mbox_mcfunc_t *mcfuncs)
2301{
a36c61f9
KG		 2302 struct bfa_ioc_mbox_mod_s *mod = &ioc->mbox_mod;
2303 int mc;
7725ccfd
JH		 2304
2305 for (mc = 0; mc < BFI_MC_MAX; mc++)
2306 mod->mbhdlr[mc].cbfn = mcfuncs[mc];
2307}
2308
5fbe25c7 2309/*
7725ccfd
JH		 2310 * Register mailbox message handler function, to be called by common modules
2311 */
2312void
2313bfa_ioc_mbox_regisr(struct bfa_ioc_s *ioc, enum bfi_mclass mc,
2314 bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg)
2315{
a36c61f9 2316 struct bfa_ioc_mbox_mod_s *mod = &ioc->mbox_mod;
7725ccfd 2317
a36c61f9
KG		 2318 mod->mbhdlr[mc].cbfn = cbfn;
2319 mod->mbhdlr[mc].cbarg = cbarg;
7725ccfd
JH		 2320}
2321
5fbe25c7 2322/*
7725ccfd
JH		 2323 * Queue a mailbox command request to firmware. Waits if mailbox is busy.
2324 * Responsibility of caller to serialize
2325 *
2326 * @param[in] ioc IOC instance
2327 * @param[i] cmd Mailbox command
2328 */
2329void
2330bfa_ioc_mbox_queue(struct bfa_ioc_s *ioc, struct bfa_mbox_cmd_s *cmd)
2331{
a36c61f9
KG		 2332 struct bfa_ioc_mbox_mod_s *mod = &ioc->mbox_mod;
2333 u32 stat;
7725ccfd 2334
5fbe25c7 2335 /*
7725ccfd
JH		 2336 * If a previous command is pending, queue new command
2337 */
2338 if (!list_empty(&mod->cmd_q)) {
2339 list_add_tail(&cmd->qe, &mod->cmd_q);
2340 return;
2341 }
2342
5fbe25c7 2343 /*
7725ccfd
JH		 2344 * If mailbox is busy, queue command for poll timer
2345 */
53440260 2346 stat = readl(ioc->ioc_regs.hfn_mbox_cmd);
7725ccfd
JH		 2347 if (stat) {
2348 list_add_tail(&cmd->qe, &mod->cmd_q);
2349 return;
2350 }
2351
5fbe25c7 2352 /*
7725ccfd
JH		 2353 * mailbox is free -- queue command to firmware
2354 */
2355 bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg));
2356}
2357
5fbe25c7 2358/*
7725ccfd
JH		 2359 * Handle mailbox interrupts
2360 */
2361void
2362bfa_ioc_mbox_isr(struct bfa_ioc_s *ioc)
2363{
a36c61f9
KG		 2364 struct bfa_ioc_mbox_mod_s *mod = &ioc->mbox_mod;
2365 struct bfi_mbmsg_s m;
2366 int mc;
7725ccfd 2367
8b070b4a
KG		 2368 if (bfa_ioc_msgget(ioc, &m)) {
2369 /*
2370 * Treat IOC message class as special.
2371 */
2372 mc = m.mh.msg_class;
2373 if (mc == BFI_MC_IOC) {
2374 bfa_ioc_isr(ioc, &m);
2375 return;
2376 }
7725ccfd 2377
fffa6923 2378 if ((mc >= BFI_MC_MAX) || (mod->mbhdlr[mc].cbfn == NULL))
8b070b4a
KG		 2379 return;
2380
2381 mod->mbhdlr[mc].cbfn(mod->mbhdlr[mc].cbarg, &m);
7725ccfd
JH		 2382 }
2383
8b070b4a 2384 bfa_ioc_lpu_read_stat(ioc);
7725ccfd 2385
8b070b4a
KG		 2386 /*
2387 * Try to send pending mailbox commands
2388 */
2389 bfa_ioc_mbox_poll(ioc);
7725ccfd
JH		 2390}
2391
2392void
2393bfa_ioc_error_isr(struct bfa_ioc_s *ioc)
2394{
5a0adaed
KG		 2395 bfa_ioc_stats(ioc, ioc_hbfails);
2396 ioc->stats.hb_count = ioc->hb_count;
7725ccfd
JH		 2397 bfa_fsm_send_event(ioc, IOC_E_HWERROR);
2398}
2399
5fbe25c7 2400/*
7725ccfd
JH		 2401 * return true if IOC is disabled
2402 */
2403bfa_boolean_t
2404bfa_ioc_is_disabled(struct bfa_ioc_s *ioc)
2405{
a36c61f9
KG		 2406 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabling) ||
2407 bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled);
7725ccfd
JH		 2408}
2409
5fbe25c7 2410/*
7725ccfd
JH		 2411 * return true if IOC firmware is different.
2412 */
2413bfa_boolean_t
2414bfa_ioc_fw_mismatch(struct bfa_ioc_s *ioc)
2415{
a36c61f9
KG		 2416 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_reset) ||
2417 bfa_fsm_cmp_state(&ioc->iocpf, bfa_iocpf_sm_fwcheck) ||
2418 bfa_fsm_cmp_state(&ioc->iocpf, bfa_iocpf_sm_mismatch);
7725ccfd
JH		 2419}
2420
2421#define bfa_ioc_state_disabled(__sm) \
2422 (((__sm) == BFI_IOC_UNINIT) || \
2423 ((__sm) == BFI_IOC_INITING) || \
2424 ((__sm) == BFI_IOC_HWINIT) || \
2425 ((__sm) == BFI_IOC_DISABLED) || \
0a20de44 2426 ((__sm) == BFI_IOC_FAIL) || \
7725ccfd
JH		 2427 ((__sm) == BFI_IOC_CFG_DISABLED))
2428
5fbe25c7 2429/*
7725ccfd
JH		 2430 * Check if adapter is disabled -- both IOCs should be in a disabled
2431 * state.
2432 */
2433bfa_boolean_t
2434bfa_ioc_adapter_is_disabled(struct bfa_ioc_s *ioc)
2435{
a36c61f9 2436 u32 ioc_state;
7725ccfd
JH		 2437
2438 if (!bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled))
2439 return BFA_FALSE;
2440
c679b599 2441 ioc_state = bfa_ioc_get_cur_ioc_fwstate(ioc);
7725ccfd
JH		 2442 if (!bfa_ioc_state_disabled(ioc_state))
2443 return BFA_FALSE;
2444
a36c61f9 2445 if (ioc->pcidev.device_id != BFA_PCI_DEVICE_ID_FC_8G1P) {
c679b599 2446 ioc_state = bfa_ioc_get_cur_ioc_fwstate(ioc);
a36c61f9
KG		 2447 if (!bfa_ioc_state_disabled(ioc_state))
2448 return BFA_FALSE;
2449 }
7725ccfd
JH		 2450
2451 return BFA_TRUE;
2452}
2453
8f4bfadd 2454/*
f1d584d7
KG		 2455 * Reset IOC fwstate registers.
2456 */
2457void
2458bfa_ioc_reset_fwstate(struct bfa_ioc_s *ioc)
2459{
c679b599
VMG		 2460 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_UNINIT);
2461 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_UNINIT);
f1d584d7
KG		 2462}
2463
7725ccfd
JH		 2464#define BFA_MFG_NAME "Brocade"
2465void
2466bfa_ioc_get_adapter_attr(struct bfa_ioc_s *ioc,
2467 struct bfa_adapter_attr_s *ad_attr)
2468{
a36c61f9 2469 struct bfi_ioc_attr_s *ioc_attr;
7725ccfd
JH		 2470
2471 ioc_attr = ioc->attr;
0a4b1fc0
KG		 2472
2473 bfa_ioc_get_adapter_serial_num(ioc, ad_attr->serial_num);
2474 bfa_ioc_get_adapter_fw_ver(ioc, ad_attr->fw_ver);
2475 bfa_ioc_get_adapter_optrom_ver(ioc, ad_attr->optrom_ver);
2476 bfa_ioc_get_adapter_manufacturer(ioc, ad_attr->manufacturer);
6a18b167 2477 memcpy(&ad_attr->vpd, &ioc_attr->vpd,
7725ccfd
JH		 2478 sizeof(struct bfa_mfg_vpd_s));
2479
0a4b1fc0
KG		 2480 ad_attr->nports = bfa_ioc_get_nports(ioc);
2481 ad_attr->max_speed = bfa_ioc_speed_sup(ioc);
7725ccfd 2482
0a4b1fc0
KG		 2483 bfa_ioc_get_adapter_model(ioc, ad_attr->model);
2484 /* For now, model descr uses same model string */
2485 bfa_ioc_get_adapter_model(ioc, ad_attr->model_descr);
7725ccfd 2486
ed969324
JH		 2487 ad_attr->card_type = ioc_attr->card_type;
2488 ad_attr->is_mezz = bfa_mfg_is_mezz(ioc_attr->card_type);
2489
7725ccfd
JH		 2490 if (BFI_ADAPTER_IS_SPECIAL(ioc_attr->adapter_prop))
2491 ad_attr->prototype = 1;
2492 else
2493 ad_attr->prototype = 0;
2494
f7f73812 2495 ad_attr->pwwn = ioc->attr->pwwn;
a36c61f9 2496 ad_attr->mac = bfa_ioc_get_mac(ioc);
7725ccfd
JH		 2497
2498 ad_attr->pcie_gen = ioc_attr->pcie_gen;
2499 ad_attr->pcie_lanes = ioc_attr->pcie_lanes;
2500 ad_attr->pcie_lanes_orig = ioc_attr->pcie_lanes_orig;
2501 ad_attr->asic_rev = ioc_attr->asic_rev;
0a4b1fc0
KG		 2502
2503 bfa_ioc_get_pci_chip_rev(ioc, ad_attr->hw_ver);
7725ccfd 2504
11189208
KG		 2505 ad_attr->cna_capable = bfa_ioc_is_cna(ioc);
2506 ad_attr->trunk_capable = (ad_attr->nports > 1) &&
2507 !bfa_ioc_is_cna(ioc) && !ad_attr->is_mezz;
ea5d7c9e
KG		 2508 ad_attr->mfg_day = ioc_attr->mfg_day;
2509 ad_attr->mfg_month = ioc_attr->mfg_month;
2510 ad_attr->mfg_year = ioc_attr->mfg_year;
079bcbc3 2511 memcpy(ad_attr->uuid, ioc_attr->uuid, BFA_ADAPTER_UUID_LEN);
7725ccfd
JH		 2512}
2513
2993cc71
KG		 2514enum bfa_ioc_type_e
2515bfa_ioc_get_type(struct bfa_ioc_s *ioc)
2516{
11189208 2517 if (ioc->clscode == BFI_PCIFN_CLASS_ETH)
2993cc71 2518 return BFA_IOC_TYPE_LL;
11189208
KG		 2519
2520 WARN_ON(ioc->clscode != BFI_PCIFN_CLASS_FC);
2521
5a0adaed 2522 return (ioc->attr->port_mode == BFI_PORT_MODE_FC)
11189208 2523 ? BFA_IOC_TYPE_FC : BFA_IOC_TYPE_FCoE;
2993cc71
KG		 2524}
2525
0a4b1fc0
KG		 2526void
2527bfa_ioc_get_adapter_serial_num(struct bfa_ioc_s *ioc, char *serial_num)
2528{
6a18b167
JH		 2529 memset((void *)serial_num, 0, BFA_ADAPTER_SERIAL_NUM_LEN);
2530 memcpy((void *)serial_num,
0a4b1fc0
KG		 2531 (void *)ioc->attr->brcd_serialnum,
2532 BFA_ADAPTER_SERIAL_NUM_LEN);
2533}
2534
2535void
2536bfa_ioc_get_adapter_fw_ver(struct bfa_ioc_s *ioc, char *fw_ver)
2537{
6a18b167
JH		 2538 memset((void *)fw_ver, 0, BFA_VERSION_LEN);
2539 memcpy(fw_ver, ioc->attr->fw_version, BFA_VERSION_LEN);
0a4b1fc0
KG		 2540}
2541
2542void
2543bfa_ioc_get_pci_chip_rev(struct bfa_ioc_s *ioc, char *chip_rev)
2544{
d4b671c5 2545 WARN_ON(!chip_rev);
0a4b1fc0 2546
6a18b167 2547 memset((void *)chip_rev, 0, BFA_IOC_CHIP_REV_LEN);
0a4b1fc0
KG		 2548
2549 chip_rev[0] = 'R';
2550 chip_rev[1] = 'e';
2551 chip_rev[2] = 'v';
2552 chip_rev[3] = '-';
2553 chip_rev[4] = ioc->attr->asic_rev;
2554 chip_rev[5] = '\0';
2555}
2556
2557void
2558bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc_s *ioc, char *optrom_ver)
2559{
6a18b167
JH		 2560 memset((void *)optrom_ver, 0, BFA_VERSION_LEN);
2561 memcpy(optrom_ver, ioc->attr->optrom_version,
a36c61f9 2562 BFA_VERSION_LEN);
0a4b1fc0
KG		 2563}
2564
2565void
2566bfa_ioc_get_adapter_manufacturer(struct bfa_ioc_s *ioc, char *manufacturer)
2567{
6a18b167
JH		 2568 memset((void *)manufacturer, 0, BFA_ADAPTER_MFG_NAME_LEN);
2569 memcpy(manufacturer, BFA_MFG_NAME, BFA_ADAPTER_MFG_NAME_LEN);
0a4b1fc0
KG		 2570}
2571
2572void
2573bfa_ioc_get_adapter_model(struct bfa_ioc_s *ioc, char *model)
2574{
a36c61f9 2575 struct bfi_ioc_attr_s *ioc_attr;
079bcbc3 2576 u8 nports = bfa_ioc_get_nports(ioc);
0a4b1fc0 2577
d4b671c5 2578 WARN_ON(!model);
6a18b167 2579 memset((void *)model, 0, BFA_ADAPTER_MODEL_NAME_LEN);
0a4b1fc0
KG		 2580
2581 ioc_attr = ioc->attr;
2582
079bcbc3
VMG		 2583 if (bfa_asic_id_ct2(ioc->pcidev.device_id) &&
2584 (!bfa_mfg_is_mezz(ioc_attr->card_type)))
2585 snprintf(model, BFA_ADAPTER_MODEL_NAME_LEN, "%s-%u-%u%s",
2586 BFA_MFG_NAME, ioc_attr->card_type, nports, "p");
2587 else
2588 snprintf(model, BFA_ADAPTER_MODEL_NAME_LEN, "%s-%u",
8b070b4a 2589 BFA_MFG_NAME, ioc_attr->card_type);
0a4b1fc0
KG		 2590}
2591
2592enum bfa_ioc_state
2593bfa_ioc_get_state(struct bfa_ioc_s *ioc)
2594{
a36c61f9
KG		 2595 enum bfa_iocpf_state iocpf_st;
2596 enum bfa_ioc_state ioc_st = bfa_sm_to_state(ioc_sm_table, ioc->fsm);
2597
2598 if (ioc_st == BFA_IOC_ENABLING ||
2599 ioc_st == BFA_IOC_FAIL || ioc_st == BFA_IOC_INITFAIL) {
2600
2601 iocpf_st = bfa_sm_to_state(iocpf_sm_table, ioc->iocpf.fsm);
2602
2603 switch (iocpf_st) {
2604 case BFA_IOCPF_SEMWAIT:
2605 ioc_st = BFA_IOC_SEMWAIT;
2606 break;
2607
2608 case BFA_IOCPF_HWINIT:
2609 ioc_st = BFA_IOC_HWINIT;
2610 break;
2611
2612 case BFA_IOCPF_FWMISMATCH:
2613 ioc_st = BFA_IOC_FWMISMATCH;
2614 break;
2615
2616 case BFA_IOCPF_FAIL:
2617 ioc_st = BFA_IOC_FAIL;
2618 break;
2619
2620 case BFA_IOCPF_INITFAIL:
2621 ioc_st = BFA_IOC_INITFAIL;
2622 break;
2623
2624 default:
2625 break;
2626 }
2627 }
2628
2629 return ioc_st;
0a4b1fc0
KG		 2630}
2631
7725ccfd
JH		 2632void
2633bfa_ioc_get_attr(struct bfa_ioc_s *ioc, struct bfa_ioc_attr_s *ioc_attr)
2634{
6a18b167 2635 memset((void *)ioc_attr, 0, sizeof(struct bfa_ioc_attr_s));
7725ccfd 2636
0a4b1fc0 2637 ioc_attr->state = bfa_ioc_get_state(ioc);
079bcbc3 2638 ioc_attr->port_id = bfa_ioc_portid(ioc);
1a4d8e1b
KG		 2639 ioc_attr->port_mode = ioc->port_mode;
2640 ioc_attr->port_mode_cfg = ioc->port_mode_cfg;
2641 ioc_attr->cap_bm = ioc->ad_cap_bm;
7725ccfd 2642
2993cc71 2643 ioc_attr->ioc_type = bfa_ioc_get_type(ioc);
7725ccfd
JH		 2644
2645 bfa_ioc_get_adapter_attr(ioc, &ioc_attr->adapter_attr);
2646
079bcbc3
VMG		 2647 ioc_attr->pci_attr.device_id = bfa_ioc_devid(ioc);
2648 ioc_attr->pci_attr.pcifn = bfa_ioc_pcifn(ioc);
2649 ioc_attr->def_fn = (bfa_ioc_pcifn(ioc) == bfa_ioc_portid(ioc));
0a4b1fc0 2650 bfa_ioc_get_pci_chip_rev(ioc, ioc_attr->pci_attr.chip_rev);
7725ccfd
JH		 2651}
2652
7725ccfd
JH		 2653mac_t
2654bfa_ioc_get_mac(struct bfa_ioc_s *ioc)
2655{
15b64a83 2656 /*
a36c61f9 2657 * Check the IOC type and return the appropriate MAC
15b64a83
JH		 2658 */
2659 if (bfa_ioc_get_type(ioc) == BFA_IOC_TYPE_FCoE)
a36c61f9 2660 return ioc->attr->fcoe_mac;
15b64a83
JH		 2661 else
2662 return ioc->attr->mac;
2663}
2664
15b64a83
JH		 2665mac_t
2666bfa_ioc_get_mfg_mac(struct bfa_ioc_s *ioc)
2667{
a36c61f9 2668 mac_t m;
7725ccfd 2669
a36c61f9
KG		 2670 m = ioc->attr->mfg_mac;
2671 if (bfa_mfg_is_old_wwn_mac_model(ioc->attr->card_type))
2672 m.mac[MAC_ADDRLEN - 1] += bfa_ioc_pcifn(ioc);
2673 else
2674 bfa_mfg_increment_wwn_mac(&(m.mac[MAC_ADDRLEN-3]),
2675 bfa_ioc_pcifn(ioc));
7725ccfd 2676
a36c61f9 2677 return m;
7725ccfd
JH		 2678}
2679
7826f304
KG		 2680/*
2681 * Send AEN notification
2682 */
2683void
2684bfa_ioc_aen_post(struct bfa_ioc_s *ioc, enum bfa_ioc_aen_event event)
2685{
2686 struct bfad_s *bfad = (struct bfad_s *)ioc->bfa->bfad;
2687 struct bfa_aen_entry_s *aen_entry;
2688 enum bfa_ioc_type_e ioc_type;
2689
2690 bfad_get_aen_entry(bfad, aen_entry);
2691 if (!aen_entry)
2692 return;
2693
2694 ioc_type = bfa_ioc_get_type(ioc);
2695 switch (ioc_type) {
2696 case BFA_IOC_TYPE_FC:
2697 aen_entry->aen_data.ioc.pwwn = ioc->attr->pwwn;
2698 break;
2699 case BFA_IOC_TYPE_FCoE:
2700 aen_entry->aen_data.ioc.pwwn = ioc->attr->pwwn;
2701 aen_entry->aen_data.ioc.mac = bfa_ioc_get_mac(ioc);
2702 break;
2703 case BFA_IOC_TYPE_LL:
2704 aen_entry->aen_data.ioc.mac = bfa_ioc_get_mac(ioc);
2705 break;
2706 default:
2707 WARN_ON(ioc_type != BFA_IOC_TYPE_FC);
2708 break;
2709 }
2710
2711 /* Send the AEN notification */
2712 aen_entry->aen_data.ioc.ioc_type = ioc_type;
2713 bfad_im_post_vendor_event(aen_entry, bfad, ++ioc->ioc_aen_seq,
2714 BFA_AEN_CAT_IOC, event);
2715}
2716
5fbe25c7 2717/*
7725ccfd
JH		 2718 * Retrieve saved firmware trace from a prior IOC failure.
2719 */
2720bfa_status_t
2721bfa_ioc_debug_fwsave(struct bfa_ioc_s *ioc, void *trcdata, int *trclen)
2722{
a36c61f9 2723 int tlen;
7725ccfd
JH		 2724
2725 if (ioc->dbg_fwsave_len == 0)
2726 return BFA_STATUS_ENOFSAVE;
2727
2728 tlen = *trclen;
2729 if (tlen > ioc->dbg_fwsave_len)
2730 tlen = ioc->dbg_fwsave_len;
2731
6a18b167 2732 memcpy(trcdata, ioc->dbg_fwsave, tlen);
7725ccfd
JH		 2733 *trclen = tlen;
2734 return BFA_STATUS_OK;
2735}
2736
738c9e66 2737
5fbe25c7 2738/*
7725ccfd
JH		 2739 * Retrieve saved firmware trace from a prior IOC failure.
2740 */
2741bfa_status_t
2742bfa_ioc_debug_fwtrc(struct bfa_ioc_s *ioc, void *trcdata, int *trclen)
2743{
a36c61f9
KG		 2744 u32 loff = BFA_DBG_FWTRC_OFF(bfa_ioc_portid(ioc));
2745 int tlen;
2746 bfa_status_t status;
7725ccfd
JH		 2747
2748 bfa_trc(ioc, *trclen);
2749
7725ccfd
JH		 2750 tlen = *trclen;
2751 if (tlen > BFA_DBG_FWTRC_LEN)
2752 tlen = BFA_DBG_FWTRC_LEN;
7725ccfd 2753
a36c61f9
KG		 2754 status = bfa_ioc_smem_read(ioc, trcdata, loff, tlen);
2755 *trclen = tlen;
2756 return status;
2757}
7725ccfd 2758
a36c61f9
KG		 2759static void
2760bfa_ioc_send_fwsync(struct bfa_ioc_s *ioc)
2761{
2762 struct bfa_mbox_cmd_s cmd;
2763 struct bfi_ioc_ctrl_req_s *req = (struct bfi_ioc_ctrl_req_s *) cmd.msg;
7725ccfd 2764
a36c61f9
KG		 2765 bfi_h2i_set(req->mh, BFI_MC_IOC, BFI_IOC_H2I_DBG_SYNC,
2766 bfa_ioc_portid(ioc));
d37779f8 2767 req->clscode = cpu_to_be16(ioc->clscode);
a36c61f9
KG		 2768 bfa_ioc_mbox_queue(ioc, &cmd);
2769}
2770
2771static void
2772bfa_ioc_fwsync(struct bfa_ioc_s *ioc)
2773{
2774 u32 fwsync_iter = 1000;
2775
2776 bfa_ioc_send_fwsync(ioc);
2777
5fbe25c7 2778 /*
a36c61f9
KG		 2779 * After sending a fw sync mbox command wait for it to
2780 * take effect. We will not wait for a response because
2781 * 1. fw_sync mbox cmd doesn't have a response.
2782 * 2. Even if we implement that, interrupts might not
2783 * be enabled when we call this function.
2784 * So, just keep checking if any mbox cmd is pending, and
2785 * after waiting for a reasonable amount of time, go ahead.
2786 * It is possible that fw has crashed and the mbox command
2787 * is never acknowledged.
2788 */
2789 while (bfa_ioc_mbox_cmd_pending(ioc) && fwsync_iter > 0)
2790 fwsync_iter--;
2791}
2792
5fbe25c7 2793/*
a36c61f9
KG		 2794 * Dump firmware smem
2795 */
2796bfa_status_t
2797bfa_ioc_debug_fwcore(struct bfa_ioc_s *ioc, void *buf,
2798 u32 *offset, int *buflen)
2799{
2800 u32 loff;
2801 int dlen;
2802 bfa_status_t status;
2803 u32 smem_len = BFA_IOC_FW_SMEM_SIZE(ioc);
2804
2805 if (*offset >= smem_len) {
2806 *offset = *buflen = 0;
2807 return BFA_STATUS_EINVAL;
7725ccfd 2808 }
0a20de44 2809
a36c61f9
KG		 2810 loff = *offset;
2811 dlen = *buflen;
2812
5fbe25c7 2813 /*
a36c61f9
KG		 2814 * First smem read, sync smem before proceeding
2815 * No need to sync before reading every chunk.
0a20de44 2816 */
a36c61f9
KG		 2817 if (loff == 0)
2818 bfa_ioc_fwsync(ioc);
0a20de44 2819
a36c61f9
KG		 2820 if ((loff + dlen) >= smem_len)
2821 dlen = smem_len - loff;
7725ccfd 2822
a36c61f9
KG		 2823 status = bfa_ioc_smem_read(ioc, buf, loff, dlen);
2824
2825 if (status != BFA_STATUS_OK) {
2826 *offset = *buflen = 0;
2827 return status;
2828 }
2829
2830 *offset += dlen;
2831
2832 if (*offset >= smem_len)
2833 *offset = 0;
2834
2835 *buflen = dlen;
2836
2837 return status;
2838}
2839
5fbe25c7 2840/*
a36c61f9
KG		 2841 * Firmware statistics
2842 */
2843bfa_status_t
2844bfa_ioc_fw_stats_get(struct bfa_ioc_s *ioc, void *stats)
2845{
2846 u32 loff = BFI_IOC_FWSTATS_OFF + \
2847 BFI_IOC_FWSTATS_SZ * (bfa_ioc_portid(ioc));
2848 int tlen;
2849 bfa_status_t status;
2850
2851 if (ioc->stats_busy) {
2852 bfa_trc(ioc, ioc->stats_busy);
2853 return BFA_STATUS_DEVBUSY;
2854 }
2855 ioc->stats_busy = BFA_TRUE;
2856
2857 tlen = sizeof(struct bfa_fw_stats_s);
2858 status = bfa_ioc_smem_read(ioc, stats, loff, tlen);
2859
2860 ioc->stats_busy = BFA_FALSE;
2861 return status;
2862}
2863
2864bfa_status_t
2865bfa_ioc_fw_stats_clear(struct bfa_ioc_s *ioc)
2866{
2867 u32 loff = BFI_IOC_FWSTATS_OFF + \
2868 BFI_IOC_FWSTATS_SZ * (bfa_ioc_portid(ioc));
2869 int tlen;
2870 bfa_status_t status;
2871
2872 if (ioc->stats_busy) {
2873 bfa_trc(ioc, ioc->stats_busy);
2874 return BFA_STATUS_DEVBUSY;
2875 }
2876 ioc->stats_busy = BFA_TRUE;
2877
2878 tlen = sizeof(struct bfa_fw_stats_s);
2879 status = bfa_ioc_smem_clr(ioc, loff, tlen);
2880
2881 ioc->stats_busy = BFA_FALSE;
2882 return status;
7725ccfd
JH		 2883}
2884
5fbe25c7 2885/*
7725ccfd
JH		 2886 * Save firmware trace if configured.
2887 */
881c1b3c 2888void
4e78efef 2889bfa_ioc_debug_save_ftrc(struct bfa_ioc_s *ioc)
7725ccfd 2890{
a36c61f9 2891 int tlen;
7725ccfd 2892
4e78efef
KG		 2893 if (ioc->dbg_fwsave_once) {
2894 ioc->dbg_fwsave_once = BFA_FALSE;
2895 if (ioc->dbg_fwsave_len) {
2896 tlen = ioc->dbg_fwsave_len;
2897 bfa_ioc_debug_fwtrc(ioc, ioc->dbg_fwsave, &tlen);
2898 }
7725ccfd
JH		 2899 }
2900}
2901
5fbe25c7 2902/*
7725ccfd
JH		 2903 * Firmware failure detected. Start recovery actions.
2904 */
2905static void
2906bfa_ioc_recover(struct bfa_ioc_s *ioc)
2907{
7725ccfd 2908 bfa_ioc_stats(ioc, ioc_hbfails);
5a0adaed 2909 ioc->stats.hb_count = ioc->hb_count;
7725ccfd
JH		 2910 bfa_fsm_send_event(ioc, IOC_E_HBFAIL);
2911}
2912
5fbe25c7 2913/*
df0f1933 2914 * BFA IOC PF private functions
a36c61f9 2915 */
a36c61f9
KG		 2916static void
2917bfa_iocpf_timeout(void *ioc_arg)
2918{
2919 struct bfa_ioc_s *ioc = (struct bfa_ioc_s *) ioc_arg;
2920
2921 bfa_trc(ioc, 0);
2922 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_TIMEOUT);
2923}
2924
2925static void
2926bfa_iocpf_sem_timeout(void *ioc_arg)
2927{
2928 struct bfa_ioc_s *ioc = (struct bfa_ioc_s *) ioc_arg;
2929
2930 bfa_ioc_hw_sem_get(ioc);
2931}
2932
775c7742
KG		 2933static void
2934bfa_ioc_poll_fwinit(struct bfa_ioc_s *ioc)
2935{
c679b599 2936 u32 fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc);
775c7742
KG		 2937
2938 bfa_trc(ioc, fwstate);
2939
2940 if (fwstate == BFI_IOC_DISABLED) {
2941 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FWREADY);
2942 return;
2943 }
2944
7ac83b1f 2945 if (ioc->iocpf.poll_time >= (3 * BFA_IOC_TOV))
775c7742
KG		 2946 bfa_iocpf_timeout(ioc);
2947 else {
2948 ioc->iocpf.poll_time += BFA_IOC_POLL_TOV;
2949 bfa_iocpf_poll_timer_start(ioc);
2950 }
2951}
2952
2953static void
2954bfa_iocpf_poll_timeout(void *ioc_arg)
2955{
2956 struct bfa_ioc_s *ioc = (struct bfa_ioc_s *) ioc_arg;
2957
2958 bfa_ioc_poll_fwinit(ioc);
2959}
2960
5fbe25c7 2961/*
a36c61f9
KG		 2962 * bfa timer function
2963 */
a36c61f9
KG		 2964void
2965bfa_timer_beat(struct bfa_timer_mod_s *mod)
2966{
2967 struct list_head *qh = &mod->timer_q;
2968 struct list_head *qe, *qe_next;
2969 struct bfa_timer_s *elem;
2970 struct list_head timedout_q;
2971
2972 INIT_LIST_HEAD(&timedout_q);
2973
2974 qe = bfa_q_next(qh);
2975
2976 while (qe != qh) {
2977 qe_next = bfa_q_next(qe);
2978
2979 elem = (struct bfa_timer_s *) qe;
2980 if (elem->timeout <= BFA_TIMER_FREQ) {
2981 elem->timeout = 0;
2982 list_del(&elem->qe);
2983 list_add_tail(&elem->qe, &timedout_q);
2984 } else {
2985 elem->timeout -= BFA_TIMER_FREQ;
2986 }
2987
2988 qe = qe_next; /* go to next elem */
2989 }
2990
2991 /*
2992 * Pop all the timeout entries
2993 */
2994 while (!list_empty(&timedout_q)) {
2995 bfa_q_deq(&timedout_q, &elem);
2996 elem->timercb(elem->arg);
2997 }
2998}
2999
5fbe25c7 3000/*
a36c61f9
KG		 3001 * Should be called with lock protection
3002 */
3003void
3004bfa_timer_begin(struct bfa_timer_mod_s *mod, struct bfa_timer_s *timer,
3005 void (*timercb) (void *), void *arg, unsigned int timeout)
3006{
3007
d4b671c5
JH		 3008 WARN_ON(timercb == NULL);
3009 WARN_ON(bfa_q_is_on_q(&mod->timer_q, timer));
a36c61f9
KG		 3010
3011 timer->timeout = timeout;
3012 timer->timercb = timercb;
3013 timer->arg = arg;
3014
3015 list_add_tail(&timer->qe, &mod->timer_q);
3016}
3017
5fbe25c7 3018/*
a36c61f9
KG		 3019 * Should be called with lock protection
3020 */
3021void
3022bfa_timer_stop(struct bfa_timer_s *timer)
3023{
d4b671c5 3024 WARN_ON(list_empty(&timer->qe));
a36c61f9
KG		 3025
3026 list_del(&timer->qe);
3027}
1a4d8e1b
KG		 3028
3029/*
3030 * ASIC block related
3031 */
3032static void
3033bfa_ablk_config_swap(struct bfa_ablk_cfg_s *cfg)
3034{
3035 struct bfa_ablk_cfg_inst_s *cfg_inst;
3036 int i, j;
3037 u16 be16;
1a4d8e1b
KG		 3038
3039 for (i = 0; i < BFA_ABLK_MAX; i++) {
3040 cfg_inst = &cfg->inst[i];
3041 for (j = 0; j < BFA_ABLK_MAX_PFS; j++) {
3042 be16 = cfg_inst->pf_cfg[j].pers;
3043 cfg_inst->pf_cfg[j].pers = be16_to_cpu(be16);
3044 be16 = cfg_inst->pf_cfg[j].num_qpairs;
3045 cfg_inst->pf_cfg[j].num_qpairs = be16_to_cpu(be16);
3046 be16 = cfg_inst->pf_cfg[j].num_vectors;
3047 cfg_inst->pf_cfg[j].num_vectors = be16_to_cpu(be16);
1a1297c6
KG		 3048 be16 = cfg_inst->pf_cfg[j].bw_min;
3049 cfg_inst->pf_cfg[j].bw_min = be16_to_cpu(be16);
3050 be16 = cfg_inst->pf_cfg[j].bw_max;
3051 cfg_inst->pf_cfg[j].bw_max = be16_to_cpu(be16);
1a4d8e1b
KG		 3052 }
3053 }
3054}
3055
3056static void
3057bfa_ablk_isr(void *cbarg, struct bfi_mbmsg_s *msg)
3058{
3059 struct bfa_ablk_s *ablk = (struct bfa_ablk_s *)cbarg;
3060 struct bfi_ablk_i2h_rsp_s *rsp = (struct bfi_ablk_i2h_rsp_s *)msg;
3061 bfa_ablk_cbfn_t cbfn;
3062
3063 WARN_ON(msg->mh.msg_class != BFI_MC_ABLK);
3064 bfa_trc(ablk->ioc, msg->mh.msg_id);
3065
3066 switch (msg->mh.msg_id) {
3067 case BFI_ABLK_I2H_QUERY:
3068 if (rsp->status == BFA_STATUS_OK) {
3069 memcpy(ablk->cfg, ablk->dma_addr.kva,
3070 sizeof(struct bfa_ablk_cfg_s));
3071 bfa_ablk_config_swap(ablk->cfg);
3072 ablk->cfg = NULL;
3073 }
3074 break;
3075
3076 case BFI_ABLK_I2H_ADPT_CONFIG:
3077 case BFI_ABLK_I2H_PORT_CONFIG:
3078 /* update config port mode */
3079 ablk->ioc->port_mode_cfg = rsp->port_mode;
3080
3081 case BFI_ABLK_I2H_PF_DELETE:
3082 case BFI_ABLK_I2H_PF_UPDATE:
3083 case BFI_ABLK_I2H_OPTROM_ENABLE:
3084 case BFI_ABLK_I2H_OPTROM_DISABLE:
3085 /* No-op */
3086 break;
3087
3088 case BFI_ABLK_I2H_PF_CREATE:
3089 *(ablk->pcifn) = rsp->pcifn;
3090 ablk->pcifn = NULL;
3091 break;
3092
3093 default:
3094 WARN_ON(1);
3095 }
3096
3097 ablk->busy = BFA_FALSE;
3098 if (ablk->cbfn) {
3099 cbfn = ablk->cbfn;
3100 ablk->cbfn = NULL;
3101 cbfn(ablk->cbarg, rsp->status);
3102 }
3103}
3104
3105static void
3106bfa_ablk_notify(void *cbarg, enum bfa_ioc_event_e event)
3107{
3108 struct bfa_ablk_s *ablk = (struct bfa_ablk_s *)cbarg;
3109
3110 bfa_trc(ablk->ioc, event);
3111
3112 switch (event) {
3113 case BFA_IOC_E_ENABLED:
3114 WARN_ON(ablk->busy != BFA_FALSE);
3115 break;
3116
3117 case BFA_IOC_E_DISABLED:
3118 case BFA_IOC_E_FAILED:
3119 /* Fail any pending requests */
3120 ablk->pcifn = NULL;
3121 if (ablk->busy) {
3122 if (ablk->cbfn)
3123 ablk->cbfn(ablk->cbarg, BFA_STATUS_FAILED);
3124 ablk->cbfn = NULL;
3125 ablk->busy = BFA_FALSE;
3126 }
3127 break;
3128
3129 default:
3130 WARN_ON(1);
3131 break;
3132 }
3133}
3134
3135u32
3136bfa_ablk_meminfo(void)
3137{
3138 return BFA_ROUNDUP(sizeof(struct bfa_ablk_cfg_s), BFA_DMA_ALIGN_SZ);
3139}
3140
3141void
3142bfa_ablk_memclaim(struct bfa_ablk_s *ablk, u8 *dma_kva, u64 dma_pa)
3143{
3144 ablk->dma_addr.kva = dma_kva;
3145 ablk->dma_addr.pa = dma_pa;
3146}
3147
3148void
3149bfa_ablk_attach(struct bfa_ablk_s *ablk, struct bfa_ioc_s *ioc)
3150{
3151 ablk->ioc = ioc;
3152
3153 bfa_ioc_mbox_regisr(ablk->ioc, BFI_MC_ABLK, bfa_ablk_isr, ablk);
3350d98d 3154 bfa_q_qe_init(&ablk->ioc_notify);
1a4d8e1b
KG		 3155 bfa_ioc_notify_init(&ablk->ioc_notify, bfa_ablk_notify, ablk);
3156 list_add_tail(&ablk->ioc_notify.qe, &ablk->ioc->notify_q);
3157}
3158
3159bfa_status_t
3160bfa_ablk_query(struct bfa_ablk_s *ablk, struct bfa_ablk_cfg_s *ablk_cfg,
3161 bfa_ablk_cbfn_t cbfn, void *cbarg)
3162{
3163 struct bfi_ablk_h2i_query_s *m;
3164
3165 WARN_ON(!ablk_cfg);
3166
3167 if (!bfa_ioc_is_operational(ablk->ioc)) {
3168 bfa_trc(ablk->ioc, BFA_STATUS_IOC_FAILURE);
3169 return BFA_STATUS_IOC_FAILURE;
3170 }
3171
3172 if (ablk->busy) {
3173 bfa_trc(ablk->ioc, BFA_STATUS_DEVBUSY);
3174 return BFA_STATUS_DEVBUSY;
3175 }
3176
3177 ablk->cfg = ablk_cfg;
3178 ablk->cbfn = cbfn;
3179 ablk->cbarg = cbarg;
3180 ablk->busy = BFA_TRUE;
3181
3182 m = (struct bfi_ablk_h2i_query_s *)ablk->mb.msg;
3183 bfi_h2i_set(m->mh, BFI_MC_ABLK, BFI_ABLK_H2I_QUERY,
3184 bfa_ioc_portid(ablk->ioc));
3185 bfa_dma_be_addr_set(m->addr, ablk->dma_addr.pa);
3186 bfa_ioc_mbox_queue(ablk->ioc, &ablk->mb);
3187
3188 return BFA_STATUS_OK;
3189}
3190
3191bfa_status_t
3192bfa_ablk_pf_create(struct bfa_ablk_s *ablk, u16 *pcifn,
1a1297c6
KG		 3193 u8 port, enum bfi_pcifn_class personality,
3194 u16 bw_min, u16 bw_max,
1a4d8e1b
KG		 3195 bfa_ablk_cbfn_t cbfn, void *cbarg)
3196{
3197 struct bfi_ablk_h2i_pf_req_s *m;
3198
3199 if (!bfa_ioc_is_operational(ablk->ioc)) {
3200 bfa_trc(ablk->ioc, BFA_STATUS_IOC_FAILURE);
3201 return BFA_STATUS_IOC_FAILURE;
3202 }
3203
3204 if (ablk->busy) {
3205 bfa_trc(ablk->ioc, BFA_STATUS_DEVBUSY);
3206 return BFA_STATUS_DEVBUSY;
3207 }
3208
3209 ablk->pcifn = pcifn;
3210 ablk->cbfn = cbfn;
3211 ablk->cbarg = cbarg;
3212 ablk->busy = BFA_TRUE;
3213
3214 m = (struct bfi_ablk_h2i_pf_req_s *)ablk->mb.msg;
3215 bfi_h2i_set(m->mh, BFI_MC_ABLK, BFI_ABLK_H2I_PF_CREATE,
3216 bfa_ioc_portid(ablk->ioc));
3217 m->pers = cpu_to_be16((u16)personality);
1a1297c6
KG		 3218 m->bw_min = cpu_to_be16(bw_min);
3219 m->bw_max = cpu_to_be16(bw_max);
1a4d8e1b
KG		 3220 m->port = port;
3221 bfa_ioc_mbox_queue(ablk->ioc, &ablk->mb);
3222
3223 return BFA_STATUS_OK;
3224}
3225
3226bfa_status_t
3227bfa_ablk_pf_delete(struct bfa_ablk_s *ablk, int pcifn,
3228 bfa_ablk_cbfn_t cbfn, void *cbarg)
3229{
3230 struct bfi_ablk_h2i_pf_req_s *m;
3231
3232 if (!bfa_ioc_is_operational(ablk->ioc)) {
3233 bfa_trc(ablk->ioc, BFA_STATUS_IOC_FAILURE);
3234 return BFA_STATUS_IOC_FAILURE;
3235 }
3236
3237 if (ablk->busy) {
3238 bfa_trc(ablk->ioc, BFA_STATUS_DEVBUSY);
3239 return BFA_STATUS_DEVBUSY;
3240 }
3241
3242 ablk->cbfn = cbfn;
3243 ablk->cbarg = cbarg;
3244 ablk->busy = BFA_TRUE;
3245
3246 m = (struct bfi_ablk_h2i_pf_req_s *)ablk->mb.msg;
3247 bfi_h2i_set(m->mh, BFI_MC_ABLK, BFI_ABLK_H2I_PF_DELETE,
3248 bfa_ioc_portid(ablk->ioc));
3249 m->pcifn = (u8)pcifn;
3250 bfa_ioc_mbox_queue(ablk->ioc, &ablk->mb);
3251
3252 return BFA_STATUS_OK;
3253}
3254
3255bfa_status_t
3256bfa_ablk_adapter_config(struct bfa_ablk_s *ablk, enum bfa_mode_s mode,
3257 int max_pf, int max_vf, bfa_ablk_cbfn_t cbfn, void *cbarg)
3258{
3259 struct bfi_ablk_h2i_cfg_req_s *m;
3260
3261 if (!bfa_ioc_is_operational(ablk->ioc)) {
3262 bfa_trc(ablk->ioc, BFA_STATUS_IOC_FAILURE);
3263 return BFA_STATUS_IOC_FAILURE;
3264 }
3265
3266 if (ablk->busy) {
3267 bfa_trc(ablk->ioc, BFA_STATUS_DEVBUSY);
3268 return BFA_STATUS_DEVBUSY;
3269 }
3270
3271 ablk->cbfn = cbfn;
3272 ablk->cbarg = cbarg;
3273 ablk->busy = BFA_TRUE;
3274
3275 m = (struct bfi_ablk_h2i_cfg_req_s *)ablk->mb.msg;
3276 bfi_h2i_set(m->mh, BFI_MC_ABLK, BFI_ABLK_H2I_ADPT_CONFIG,
3277 bfa_ioc_portid(ablk->ioc));
3278 m->mode = (u8)mode;
3279 m->max_pf = (u8)max_pf;
3280 m->max_vf = (u8)max_vf;
3281 bfa_ioc_mbox_queue(ablk->ioc, &ablk->mb);
3282
3283 return BFA_STATUS_OK;
3284}
3285
3286bfa_status_t
3287bfa_ablk_port_config(struct bfa_ablk_s *ablk, int port, enum bfa_mode_s mode,
3288 int max_pf, int max_vf, bfa_ablk_cbfn_t cbfn, void *cbarg)
3289{
3290 struct bfi_ablk_h2i_cfg_req_s *m;
3291
3292 if (!bfa_ioc_is_operational(ablk->ioc)) {
3293 bfa_trc(ablk->ioc, BFA_STATUS_IOC_FAILURE);
3294 return BFA_STATUS_IOC_FAILURE;
3295 }
3296
3297 if (ablk->busy) {
3298 bfa_trc(ablk->ioc, BFA_STATUS_DEVBUSY);
3299 return BFA_STATUS_DEVBUSY;
3300 }
3301
3302 ablk->cbfn = cbfn;
3303 ablk->cbarg = cbarg;
3304 ablk->busy = BFA_TRUE;
3305
3306 m = (struct bfi_ablk_h2i_cfg_req_s *)ablk->mb.msg;
3307 bfi_h2i_set(m->mh, BFI_MC_ABLK, BFI_ABLK_H2I_PORT_CONFIG,
3308 bfa_ioc_portid(ablk->ioc));
3309 m->port = (u8)port;
3310 m->mode = (u8)mode;
3311 m->max_pf = (u8)max_pf;
3312 m->max_vf = (u8)max_vf;
3313 bfa_ioc_mbox_queue(ablk->ioc, &ablk->mb);
3314
3315 return BFA_STATUS_OK;
3316}
3317
3318bfa_status_t
1a1297c6
KG		 3319bfa_ablk_pf_update(struct bfa_ablk_s *ablk, int pcifn, u16 bw_min,
3320 u16 bw_max, bfa_ablk_cbfn_t cbfn, void *cbarg)
1a4d8e1b
KG		 3321{
3322 struct bfi_ablk_h2i_pf_req_s *m;
3323
3324 if (!bfa_ioc_is_operational(ablk->ioc)) {
3325 bfa_trc(ablk->ioc, BFA_STATUS_IOC_FAILURE);
3326 return BFA_STATUS_IOC_FAILURE;
3327 }
3328
3329 if (ablk->busy) {
3330 bfa_trc(ablk->ioc, BFA_STATUS_DEVBUSY);
3331 return BFA_STATUS_DEVBUSY;
3332 }
3333
3334 ablk->cbfn = cbfn;
3335 ablk->cbarg = cbarg;
3336 ablk->busy = BFA_TRUE;
3337
3338 m = (struct bfi_ablk_h2i_pf_req_s *)ablk->mb.msg;
3339 bfi_h2i_set(m->mh, BFI_MC_ABLK, BFI_ABLK_H2I_PF_UPDATE,
3340 bfa_ioc_portid(ablk->ioc));
3341 m->pcifn = (u8)pcifn;
1a1297c6
KG		 3342 m->bw_min = cpu_to_be16(bw_min);
3343 m->bw_max = cpu_to_be16(bw_max);
1a4d8e1b
KG		 3344 bfa_ioc_mbox_queue(ablk->ioc, &ablk->mb);
3345
3346 return BFA_STATUS_OK;
3347}
3348
3349bfa_status_t
3350bfa_ablk_optrom_en(struct bfa_ablk_s *ablk, bfa_ablk_cbfn_t cbfn, void *cbarg)
3351{
3352 struct bfi_ablk_h2i_optrom_s *m;
3353
3354 if (!bfa_ioc_is_operational(ablk->ioc)) {
3355 bfa_trc(ablk->ioc, BFA_STATUS_IOC_FAILURE);
3356 return BFA_STATUS_IOC_FAILURE;
3357 }
3358
3359 if (ablk->busy) {
3360 bfa_trc(ablk->ioc, BFA_STATUS_DEVBUSY);
3361 return BFA_STATUS_DEVBUSY;
3362 }
3363
3364 ablk->cbfn = cbfn;
3365 ablk->cbarg = cbarg;
3366 ablk->busy = BFA_TRUE;
3367
3368 m = (struct bfi_ablk_h2i_optrom_s *)ablk->mb.msg;
3369 bfi_h2i_set(m->mh, BFI_MC_ABLK, BFI_ABLK_H2I_OPTROM_ENABLE,
3370 bfa_ioc_portid(ablk->ioc));
3371 bfa_ioc_mbox_queue(ablk->ioc, &ablk->mb);
3372
3373 return BFA_STATUS_OK;
3374}
3375
3376bfa_status_t
3377bfa_ablk_optrom_dis(struct bfa_ablk_s *ablk, bfa_ablk_cbfn_t cbfn, void *cbarg)
3378{
3379 struct bfi_ablk_h2i_optrom_s *m;
3380
3381 if (!bfa_ioc_is_operational(ablk->ioc)) {
3382 bfa_trc(ablk->ioc, BFA_STATUS_IOC_FAILURE);
3383 return BFA_STATUS_IOC_FAILURE;
3384 }
3385
3386 if (ablk->busy) {
3387 bfa_trc(ablk->ioc, BFA_STATUS_DEVBUSY);
3388 return BFA_STATUS_DEVBUSY;
3389 }
3390
3391 ablk->cbfn = cbfn;
3392 ablk->cbarg = cbarg;
3393 ablk->busy = BFA_TRUE;
3394
3395 m = (struct bfi_ablk_h2i_optrom_s *)ablk->mb.msg;
3396 bfi_h2i_set(m->mh, BFI_MC_ABLK, BFI_ABLK_H2I_OPTROM_DISABLE,
3397 bfa_ioc_portid(ablk->ioc));
3398 bfa_ioc_mbox_queue(ablk->ioc, &ablk->mb);
3399
3400 return BFA_STATUS_OK;
3401}
51e569aa
KG		 3402
3403/*
3404 * SFP module specific
3405 */
3406
3407/* forward declarations */
3408static void bfa_sfp_getdata_send(struct bfa_sfp_s *sfp);
3409static void bfa_sfp_media_get(struct bfa_sfp_s *sfp);
3410static bfa_status_t bfa_sfp_speed_valid(struct bfa_sfp_s *sfp,
3411 enum bfa_port_speed portspeed);
3412
3413static void
3414bfa_cb_sfp_show(struct bfa_sfp_s *sfp)
3415{
3416 bfa_trc(sfp, sfp->lock);
3417 if (sfp->cbfn)
3418 sfp->cbfn(sfp->cbarg, sfp->status);
3419 sfp->lock = 0;
3420 sfp->cbfn = NULL;
3421}
3422
3423static void
3424bfa_cb_sfp_state_query(struct bfa_sfp_s *sfp)
3425{
3426 bfa_trc(sfp, sfp->portspeed);
3427 if (sfp->media) {
3428 bfa_sfp_media_get(sfp);
3429 if (sfp->state_query_cbfn)
3430 sfp->state_query_cbfn(sfp->state_query_cbarg,
3431 sfp->status);
3432 sfp->media = NULL;
3433 }
3434
3435 if (sfp->portspeed) {
3436 sfp->status = bfa_sfp_speed_valid(sfp, sfp->portspeed);
3437 if (sfp->state_query_cbfn)
3438 sfp->state_query_cbfn(sfp->state_query_cbarg,
3439 sfp->status);
3440 sfp->portspeed = BFA_PORT_SPEED_UNKNOWN;
3441 }
3442
3443 sfp->state_query_lock = 0;
3444 sfp->state_query_cbfn = NULL;
3445}
3446
3447/*
3448 * IOC event handler.
3449 */
3450static void
3451bfa_sfp_notify(void *sfp_arg, enum bfa_ioc_event_e event)
3452{
3453 struct bfa_sfp_s *sfp = sfp_arg;
3454
3455 bfa_trc(sfp, event);
3456 bfa_trc(sfp, sfp->lock);
3457 bfa_trc(sfp, sfp->state_query_lock);
3458
3459 switch (event) {
3460 case BFA_IOC_E_DISABLED:
3461 case BFA_IOC_E_FAILED:
3462 if (sfp->lock) {
3463 sfp->status = BFA_STATUS_IOC_FAILURE;
3464 bfa_cb_sfp_show(sfp);
3465 }
3466
3467 if (sfp->state_query_lock) {
3468 sfp->status = BFA_STATUS_IOC_FAILURE;
3469 bfa_cb_sfp_state_query(sfp);
3470 }
3471 break;
3472
3473 default:
3474 break;
3475 }
3476}
3477
7826f304
KG		 3478/*
3479 * SFP's State Change Notification post to AEN
3480 */
3481static void
3482bfa_sfp_scn_aen_post(struct bfa_sfp_s *sfp, struct bfi_sfp_scn_s *rsp)
3483{
3484 struct bfad_s *bfad = (struct bfad_s *)sfp->ioc->bfa->bfad;
3485 struct bfa_aen_entry_s *aen_entry;
3486 enum bfa_port_aen_event aen_evt = 0;
3487
3488 bfa_trc(sfp, (((u64)rsp->pomlvl) << 16) | (((u64)rsp->sfpid) << 8) |
3489 ((u64)rsp->event));
3490
3491 bfad_get_aen_entry(bfad, aen_entry);
3492 if (!aen_entry)
3493 return;
3494
3495 aen_entry->aen_data.port.ioc_type = bfa_ioc_get_type(sfp->ioc);
3496 aen_entry->aen_data.port.pwwn = sfp->ioc->attr->pwwn;
3497 aen_entry->aen_data.port.mac = bfa_ioc_get_mac(sfp->ioc);
3498
3499 switch (rsp->event) {
3500 case BFA_SFP_SCN_INSERTED:
3501 aen_evt = BFA_PORT_AEN_SFP_INSERT;
3502 break;
3503 case BFA_SFP_SCN_REMOVED:
3504 aen_evt = BFA_PORT_AEN_SFP_REMOVE;
3505 break;
3506 case BFA_SFP_SCN_FAILED:
3507 aen_evt = BFA_PORT_AEN_SFP_ACCESS_ERROR;
3508 break;
3509 case BFA_SFP_SCN_UNSUPPORT:
3510 aen_evt = BFA_PORT_AEN_SFP_UNSUPPORT;
3511 break;
3512 case BFA_SFP_SCN_POM:
3513 aen_evt = BFA_PORT_AEN_SFP_POM;
3514 aen_entry->aen_data.port.level = rsp->pomlvl;
3515 break;
3516 default:
3517 bfa_trc(sfp, rsp->event);
3518 WARN_ON(1);
3519 }
3520
3521 /* Send the AEN notification */
3522 bfad_im_post_vendor_event(aen_entry, bfad, ++sfp->ioc->ioc_aen_seq,
3523 BFA_AEN_CAT_PORT, aen_evt);
3524}
3525
51e569aa
KG		 3526/*
3527 * SFP get data send
3528 */
3529static void
3530bfa_sfp_getdata_send(struct bfa_sfp_s *sfp)
3531{
3532 struct bfi_sfp_req_s *req = (struct bfi_sfp_req_s *)sfp->mbcmd.msg;
3533
3534 bfa_trc(sfp, req->memtype);
3535
3536 /* build host command */
3537 bfi_h2i_set(req->mh, BFI_MC_SFP, BFI_SFP_H2I_SHOW,
3538 bfa_ioc_portid(sfp->ioc));
3539
3540 /* send mbox cmd */
3541 bfa_ioc_mbox_queue(sfp->ioc, &sfp->mbcmd);
3542}
3543
3544/*
3545 * SFP is valid, read sfp data
3546 */
3547static void
3548bfa_sfp_getdata(struct bfa_sfp_s *sfp, enum bfi_sfp_mem_e memtype)
3549{
3550 struct bfi_sfp_req_s *req = (struct bfi_sfp_req_s *)sfp->mbcmd.msg;
3551
3552 WARN_ON(sfp->lock != 0);
3553 bfa_trc(sfp, sfp->state);
3554
3555 sfp->lock = 1;
3556 sfp->memtype = memtype;
3557 req->memtype = memtype;
3558
3559 /* Setup SG list */
3560 bfa_alen_set(&req->alen, sizeof(struct sfp_mem_s), sfp->dbuf_pa);
3561
3562 bfa_sfp_getdata_send(sfp);
3563}
3564
7826f304
KG		 3565/*
3566 * SFP scn handler
3567 */
3568static void
3569bfa_sfp_scn(struct bfa_sfp_s *sfp, struct bfi_mbmsg_s *msg)
3570{
3571 struct bfi_sfp_scn_s *rsp = (struct bfi_sfp_scn_s *) msg;
3572
3573 switch (rsp->event) {
3574 case BFA_SFP_SCN_INSERTED:
3575 sfp->state = BFA_SFP_STATE_INSERTED;
3576 sfp->data_valid = 0;
3577 bfa_sfp_scn_aen_post(sfp, rsp);
3578 break;
3579 case BFA_SFP_SCN_REMOVED:
3580 sfp->state = BFA_SFP_STATE_REMOVED;
3581 sfp->data_valid = 0;
3582 bfa_sfp_scn_aen_post(sfp, rsp);
3583 break;
3584 case BFA_SFP_SCN_FAILED:
3585 sfp->state = BFA_SFP_STATE_FAILED;
3586 sfp->data_valid = 0;
3587 bfa_sfp_scn_aen_post(sfp, rsp);
3588 break;
3589 case BFA_SFP_SCN_UNSUPPORT:
3590 sfp->state = BFA_SFP_STATE_UNSUPPORT;
3591 bfa_sfp_scn_aen_post(sfp, rsp);
3592 if (!sfp->lock)
3593 bfa_sfp_getdata(sfp, BFI_SFP_MEM_ALL);
3594 break;
3595 case BFA_SFP_SCN_POM:
3596 bfa_sfp_scn_aen_post(sfp, rsp);
3597 break;
3598 case BFA_SFP_SCN_VALID:
3599 sfp->state = BFA_SFP_STATE_VALID;
3600 if (!sfp->lock)
3601 bfa_sfp_getdata(sfp, BFI_SFP_MEM_ALL);
3602 break;
3603 default:
3604 bfa_trc(sfp, rsp->event);
3605 WARN_ON(1);
3606 }
3607}
3608
51e569aa
KG		 3609/*
3610 * SFP show complete
3611 */
3612static void
3613bfa_sfp_show_comp(struct bfa_sfp_s *sfp, struct bfi_mbmsg_s *msg)
3614{
3615 struct bfi_sfp_rsp_s *rsp = (struct bfi_sfp_rsp_s *) msg;
3616
3617 if (!sfp->lock) {
3618 /*
3619 * receiving response after ioc failure
3620 */
3621 bfa_trc(sfp, sfp->lock);
3622 return;
3623 }
3624
3625 bfa_trc(sfp, rsp->status);
3626 if (rsp->status == BFA_STATUS_OK) {
3627 sfp->data_valid = 1;
3628 if (sfp->state == BFA_SFP_STATE_VALID)
3629 sfp->status = BFA_STATUS_OK;
3630 else if (sfp->state == BFA_SFP_STATE_UNSUPPORT)
3631 sfp->status = BFA_STATUS_SFP_UNSUPP;
3632 else
3633 bfa_trc(sfp, sfp->state);
3634 } else {
3635 sfp->data_valid = 0;
3636 sfp->status = rsp->status;
3637 /* sfpshow shouldn't change sfp state */
3638 }
3639
3640 bfa_trc(sfp, sfp->memtype);
3641 if (sfp->memtype == BFI_SFP_MEM_DIAGEXT) {
3642 bfa_trc(sfp, sfp->data_valid);
3643 if (sfp->data_valid) {
3644 u32 size = sizeof(struct sfp_mem_s);
3645 u8 *des = (u8 *) &(sfp->sfpmem->srlid_base);
3646 memcpy(des, sfp->dbuf_kva, size);
3647 }
3648 /*
3649 * Queue completion callback.
3650 */
3651 bfa_cb_sfp_show(sfp);
3652 } else
3653 sfp->lock = 0;
3654
3655 bfa_trc(sfp, sfp->state_query_lock);
3656 if (sfp->state_query_lock) {
3657 sfp->state = rsp->state;
3658 /* Complete callback */
3659 bfa_cb_sfp_state_query(sfp);
3660 }
3661}
3662
3663/*
3664 * SFP query fw sfp state
3665 */
3666static void
3667bfa_sfp_state_query(struct bfa_sfp_s *sfp)
3668{
3669 struct bfi_sfp_req_s *req = (struct bfi_sfp_req_s *)sfp->mbcmd.msg;
3670
3671 /* Should not be doing query if not in _INIT state */
3672 WARN_ON(sfp->state != BFA_SFP_STATE_INIT);
3673 WARN_ON(sfp->state_query_lock != 0);
3674 bfa_trc(sfp, sfp->state);
3675
3676 sfp->state_query_lock = 1;
3677 req->memtype = 0;
3678
3679 if (!sfp->lock)
3680 bfa_sfp_getdata(sfp, BFI_SFP_MEM_ALL);
3681}
3682
3683static void
3684bfa_sfp_media_get(struct bfa_sfp_s *sfp)
3685{
3686 enum bfa_defs_sfp_media_e *media = sfp->media;
3687
3688 *media = BFA_SFP_MEDIA_UNKNOWN;
3689
3690 if (sfp->state == BFA_SFP_STATE_UNSUPPORT)
3691 *media = BFA_SFP_MEDIA_UNSUPPORT;
3692 else if (sfp->state == BFA_SFP_STATE_VALID) {
3693 union sfp_xcvr_e10g_code_u e10g;
3694 struct sfp_mem_s *sfpmem = (struct sfp_mem_s *)sfp->dbuf_kva;
3695 u16 xmtr_tech = (sfpmem->srlid_base.xcvr[4] & 0x3) << 7 |
3696 (sfpmem->srlid_base.xcvr[5] >> 1);
3697
3698 e10g.b = sfpmem->srlid_base.xcvr[0];
3699 bfa_trc(sfp, e10g.b);
3700 bfa_trc(sfp, xmtr_tech);
3701 /* check fc transmitter tech */
3702 if ((xmtr_tech & SFP_XMTR_TECH_CU) ||
3703 (xmtr_tech & SFP_XMTR_TECH_CP) ||
3704 (xmtr_tech & SFP_XMTR_TECH_CA))
3705 *media = BFA_SFP_MEDIA_CU;
3706 else if ((xmtr_tech & SFP_XMTR_TECH_EL_INTRA) ||
3707 (xmtr_tech & SFP_XMTR_TECH_EL_INTER))
3708 *media = BFA_SFP_MEDIA_EL;
3709 else if ((xmtr_tech & SFP_XMTR_TECH_LL) ||
3710 (xmtr_tech & SFP_XMTR_TECH_LC))
3711 *media = BFA_SFP_MEDIA_LW;
3712 else if ((xmtr_tech & SFP_XMTR_TECH_SL) ||
3713 (xmtr_tech & SFP_XMTR_TECH_SN) ||
3714 (xmtr_tech & SFP_XMTR_TECH_SA))
3715 *media = BFA_SFP_MEDIA_SW;
3716 /* Check 10G Ethernet Compilance code */
98cdfb43 3717 else if (e10g.r.e10g_sr)
51e569aa 3718 *media = BFA_SFP_MEDIA_SW;
98cdfb43 3719 else if (e10g.r.e10g_lrm && e10g.r.e10g_lr)
51e569aa 3720 *media = BFA_SFP_MEDIA_LW;
98cdfb43 3721 else if (e10g.r.e10g_unall)
51e569aa
KG		 3722 *media = BFA_SFP_MEDIA_UNKNOWN;
3723 else
3724 bfa_trc(sfp, 0);
3725 } else
3726 bfa_trc(sfp, sfp->state);
3727}
3728
3729static bfa_status_t
3730bfa_sfp_speed_valid(struct bfa_sfp_s *sfp, enum bfa_port_speed portspeed)
3731{
3732 struct sfp_mem_s *sfpmem = (struct sfp_mem_s *)sfp->dbuf_kva;
3733 struct sfp_xcvr_s *xcvr = (struct sfp_xcvr_s *) sfpmem->srlid_base.xcvr;
3734 union sfp_xcvr_fc3_code_u fc3 = xcvr->fc3;
3735 union sfp_xcvr_e10g_code_u e10g = xcvr->e10g;
3736
3737 if (portspeed == BFA_PORT_SPEED_10GBPS) {
3738 if (e10g.r.e10g_sr || e10g.r.e10g_lr)
3739 return BFA_STATUS_OK;
3740 else {
3741 bfa_trc(sfp, e10g.b);
3742 return BFA_STATUS_UNSUPP_SPEED;
3743 }
3744 }
3745 if (((portspeed & BFA_PORT_SPEED_16GBPS) && fc3.r.mb1600) ||
3746 ((portspeed & BFA_PORT_SPEED_8GBPS) && fc3.r.mb800) ||
3747 ((portspeed & BFA_PORT_SPEED_4GBPS) && fc3.r.mb400) ||
3748 ((portspeed & BFA_PORT_SPEED_2GBPS) && fc3.r.mb200) ||
3749 ((portspeed & BFA_PORT_SPEED_1GBPS) && fc3.r.mb100))
3750 return BFA_STATUS_OK;
3751 else {
3752 bfa_trc(sfp, portspeed);
3753 bfa_trc(sfp, fc3.b);
3754 bfa_trc(sfp, e10g.b);
3755 return BFA_STATUS_UNSUPP_SPEED;
3756 }
3757}
3758
3759/*
3760 * SFP hmbox handler
3761 */
3762void
3763bfa_sfp_intr(void *sfparg, struct bfi_mbmsg_s *msg)
3764{
3765 struct bfa_sfp_s *sfp = sfparg;
3766
3767 switch (msg->mh.msg_id) {
3768 case BFI_SFP_I2H_SHOW:
3769 bfa_sfp_show_comp(sfp, msg);
3770 break;
3771
3772 case BFI_SFP_I2H_SCN:
7826f304 3773 bfa_sfp_scn(sfp, msg);
51e569aa
KG		 3774 break;
3775
3776 default:
3777 bfa_trc(sfp, msg->mh.msg_id);
3778 WARN_ON(1);
3779 }
3780}
3781
3782/*
3783 * Return DMA memory needed by sfp module.
3784 */
3785u32
3786bfa_sfp_meminfo(void)
3787{
3788 return BFA_ROUNDUP(sizeof(struct sfp_mem_s), BFA_DMA_ALIGN_SZ);
3789}
3790
3791/*
3792 * Attach virtual and physical memory for SFP.
3793 */
3794void
3795bfa_sfp_attach(struct bfa_sfp_s *sfp, struct bfa_ioc_s *ioc, void *dev,
3796 struct bfa_trc_mod_s *trcmod)
3797{
3798 sfp->dev = dev;
3799 sfp->ioc = ioc;
3800 sfp->trcmod = trcmod;
3801
3802 sfp->cbfn = NULL;
3803 sfp->cbarg = NULL;
3804 sfp->sfpmem = NULL;
3805 sfp->lock = 0;
3806 sfp->data_valid = 0;
3807 sfp->state = BFA_SFP_STATE_INIT;
3808 sfp->state_query_lock = 0;
3809 sfp->state_query_cbfn = NULL;
3810 sfp->state_query_cbarg = NULL;
3811 sfp->media = NULL;
3812 sfp->portspeed = BFA_PORT_SPEED_UNKNOWN;
3813 sfp->is_elb = BFA_FALSE;
3814
3815 bfa_ioc_mbox_regisr(sfp->ioc, BFI_MC_SFP, bfa_sfp_intr, sfp);
3816 bfa_q_qe_init(&sfp->ioc_notify);
3817 bfa_ioc_notify_init(&sfp->ioc_notify, bfa_sfp_notify, sfp);
3818 list_add_tail(&sfp->ioc_notify.qe, &sfp->ioc->notify_q);
3819}
3820
3821/*
3822 * Claim Memory for SFP
3823 */
3824void
3825bfa_sfp_memclaim(struct bfa_sfp_s *sfp, u8 *dm_kva, u64 dm_pa)
3826{
3827 sfp->dbuf_kva = dm_kva;
3828 sfp->dbuf_pa = dm_pa;
3829 memset(sfp->dbuf_kva, 0, sizeof(struct sfp_mem_s));
3830
3831 dm_kva += BFA_ROUNDUP(sizeof(struct sfp_mem_s), BFA_DMA_ALIGN_SZ);
3832 dm_pa += BFA_ROUNDUP(sizeof(struct sfp_mem_s), BFA_DMA_ALIGN_SZ);
3833}
3834
3835/*
3836 * Show SFP eeprom content
3837 *
3838 * @param[in] sfp - bfa sfp module
3839 *
3840 * @param[out] sfpmem - sfp eeprom data
3841 *
3842 */
3843bfa_status_t
3844bfa_sfp_show(struct bfa_sfp_s *sfp, struct sfp_mem_s *sfpmem,
3845 bfa_cb_sfp_t cbfn, void *cbarg)
3846{
3847
3848 if (!bfa_ioc_is_operational(sfp->ioc)) {
3849 bfa_trc(sfp, 0);
3850 return BFA_STATUS_IOC_NON_OP;
3851 }
3852
3853 if (sfp->lock) {
3854 bfa_trc(sfp, 0);
3855 return BFA_STATUS_DEVBUSY;
3856 }
3857
3858 sfp->cbfn = cbfn;
3859 sfp->cbarg = cbarg;
3860 sfp->sfpmem = sfpmem;
3861
3862 bfa_sfp_getdata(sfp, BFI_SFP_MEM_DIAGEXT);
3863 return BFA_STATUS_OK;
3864}
3865
3866/*
3867 * Return SFP Media type
3868 *
3869 * @param[in] sfp - bfa sfp module
3870 *
3871 * @param[out] media - port speed from user
3872 *
3873 */
3874bfa_status_t
3875bfa_sfp_media(struct bfa_sfp_s *sfp, enum bfa_defs_sfp_media_e *media,
3876 bfa_cb_sfp_t cbfn, void *cbarg)
3877{
3878 if (!bfa_ioc_is_operational(sfp->ioc)) {
3879 bfa_trc(sfp, 0);
3880 return BFA_STATUS_IOC_NON_OP;
3881 }
3882
3883 sfp->media = media;
3884 if (sfp->state == BFA_SFP_STATE_INIT) {
3885 if (sfp->state_query_lock) {
3886 bfa_trc(sfp, 0);
3887 return BFA_STATUS_DEVBUSY;
3888 } else {
3889 sfp->state_query_cbfn = cbfn;
3890 sfp->state_query_cbarg = cbarg;
3891 bfa_sfp_state_query(sfp);
3892 return BFA_STATUS_SFP_NOT_READY;
3893 }
3894 }
3895
3896 bfa_sfp_media_get(sfp);
3897 return BFA_STATUS_OK;
3898}
3899
3900/*
3901 * Check if user set port speed is allowed by the SFP
3902 *
3903 * @param[in] sfp - bfa sfp module
3904 * @param[in] portspeed - port speed from user
3905 *
3906 */
3907bfa_status_t
3908bfa_sfp_speed(struct bfa_sfp_s *sfp, enum bfa_port_speed portspeed,
3909 bfa_cb_sfp_t cbfn, void *cbarg)
3910{
3911 WARN_ON(portspeed == BFA_PORT_SPEED_UNKNOWN);
3912
3913 if (!bfa_ioc_is_operational(sfp->ioc))
3914 return BFA_STATUS_IOC_NON_OP;
3915
3916 /* For Mezz card, all speed is allowed */
3917 if (bfa_mfg_is_mezz(sfp->ioc->attr->card_type))
3918 return BFA_STATUS_OK;
3919
3920 /* Check SFP state */
3921 sfp->portspeed = portspeed;
3922 if (sfp->state == BFA_SFP_STATE_INIT) {
3923 if (sfp->state_query_lock) {
3924 bfa_trc(sfp, 0);
3925 return BFA_STATUS_DEVBUSY;
3926 } else {
3927 sfp->state_query_cbfn = cbfn;
3928 sfp->state_query_cbarg = cbarg;
3929 bfa_sfp_state_query(sfp);
3930 return BFA_STATUS_SFP_NOT_READY;
3931 }
3932 }
3933
3934 if (sfp->state == BFA_SFP_STATE_REMOVED ||
3935 sfp->state == BFA_SFP_STATE_FAILED) {
3936 bfa_trc(sfp, sfp->state);
3937 return BFA_STATUS_NO_SFP_DEV;
3938 }
3939
3940 if (sfp->state == BFA_SFP_STATE_INSERTED) {
3941 bfa_trc(sfp, sfp->state);
3942 return BFA_STATUS_DEVBUSY; /* sfp is reading data */
3943 }
3944
3945 /* For eloopback, all speed is allowed */
3946 if (sfp->is_elb)
3947 return BFA_STATUS_OK;
3948
3949 return bfa_sfp_speed_valid(sfp, portspeed);
3950}
5a54b1d5
KG		 3951
3952/*
3953 * Flash module specific
3954 */
3955
3956/*
3957 * FLASH DMA buffer should be big enough to hold both MFG block and
3958 * asic block(64k) at the same time and also should be 2k aligned to
3959 * avoid write segement to cross sector boundary.
3960 */
3961#define BFA_FLASH_SEG_SZ 2048
3962#define BFA_FLASH_DMA_BUF_SZ \
3963 BFA_ROUNDUP(0x010000 + sizeof(struct bfa_mfg_block_s), BFA_FLASH_SEG_SZ)
3964
7826f304
KG		 3965static void
3966bfa_flash_aen_audit_post(struct bfa_ioc_s *ioc, enum bfa_audit_aen_event event,
3967 int inst, int type)
3968{
3969 struct bfad_s *bfad = (struct bfad_s *)ioc->bfa->bfad;
3970 struct bfa_aen_entry_s *aen_entry;
3971
3972 bfad_get_aen_entry(bfad, aen_entry);
3973 if (!aen_entry)
3974 return;
3975
3976 aen_entry->aen_data.audit.pwwn = ioc->attr->pwwn;
3977 aen_entry->aen_data.audit.partition_inst = inst;
3978 aen_entry->aen_data.audit.partition_type = type;
3979
3980 /* Send the AEN notification */
3981 bfad_im_post_vendor_event(aen_entry, bfad, ++ioc->ioc_aen_seq,
3982 BFA_AEN_CAT_AUDIT, event);
3983}
3984
5a54b1d5
KG		 3985static void
3986bfa_flash_cb(struct bfa_flash_s *flash)
3987{
3988 flash->op_busy = 0;
3989 if (flash->cbfn)
3990 flash->cbfn(flash->cbarg, flash->status);
3991}
3992
3993static void
3994bfa_flash_notify(void *cbarg, enum bfa_ioc_event_e event)
3995{
3996 struct bfa_flash_s *flash = cbarg;
3997
3998 bfa_trc(flash, event);
3999 switch (event) {
4000 case BFA_IOC_E_DISABLED:
4001 case BFA_IOC_E_FAILED:
4002 if (flash->op_busy) {
4003 flash->status = BFA_STATUS_IOC_FAILURE;
4004 flash->cbfn(flash->cbarg, flash->status);
4005 flash->op_busy = 0;
4006 }
4007 break;
4008
4009 default:
4010 break;
4011 }
4012}
4013
4014/*
4015 * Send flash attribute query request.
4016 *
4017 * @param[in] cbarg - callback argument
4018 */
4019static void
4020bfa_flash_query_send(void *cbarg)
4021{
4022 struct bfa_flash_s *flash = cbarg;
4023 struct bfi_flash_query_req_s *msg =
4024 (struct bfi_flash_query_req_s *) flash->mb.msg;
4025
4026 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_QUERY_REQ,
4027 bfa_ioc_portid(flash->ioc));
4028 bfa_alen_set(&msg->alen, sizeof(struct bfa_flash_attr_s),
4029 flash->dbuf_pa);
4030 bfa_ioc_mbox_queue(flash->ioc, &flash->mb);
4031}
4032
4033/*
4034 * Send flash write request.
4035 *
4036 * @param[in] cbarg - callback argument
4037 */
4038static void
4039bfa_flash_write_send(struct bfa_flash_s *flash)
4040{
4041 struct bfi_flash_write_req_s *msg =
4042 (struct bfi_flash_write_req_s *) flash->mb.msg;
4043 u32 len;
4044
4045 msg->type = be32_to_cpu(flash->type);
4046 msg->instance = flash->instance;
4047 msg->offset = be32_to_cpu(flash->addr_off + flash->offset);
4048 len = (flash->residue < BFA_FLASH_DMA_BUF_SZ) ?
4049 flash->residue : BFA_FLASH_DMA_BUF_SZ;
4050 msg->length = be32_to_cpu(len);
4051
4052 /* indicate if it's the last msg of the whole write operation */
4053 msg->last = (len == flash->residue) ? 1 : 0;
4054
4055 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_WRITE_REQ,
4056 bfa_ioc_portid(flash->ioc));
4057 bfa_alen_set(&msg->alen, len, flash->dbuf_pa);
4058 memcpy(flash->dbuf_kva, flash->ubuf + flash->offset, len);
4059 bfa_ioc_mbox_queue(flash->ioc, &flash->mb);
4060
4061 flash->residue -= len;
4062 flash->offset += len;
4063}
4064
4065/*
4066 * Send flash read request.
4067 *
4068 * @param[in] cbarg - callback argument
4069 */
4070static void
4071bfa_flash_read_send(void *cbarg)
4072{
4073 struct bfa_flash_s *flash = cbarg;
4074 struct bfi_flash_read_req_s *msg =
4075 (struct bfi_flash_read_req_s *) flash->mb.msg;
4076 u32 len;
4077
4078 msg->type = be32_to_cpu(flash->type);
4079 msg->instance = flash->instance;
4080 msg->offset = be32_to_cpu(flash->addr_off + flash->offset);
4081 len = (flash->residue < BFA_FLASH_DMA_BUF_SZ) ?
4082 flash->residue : BFA_FLASH_DMA_BUF_SZ;
4083 msg->length = be32_to_cpu(len);
4084 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_READ_REQ,
4085 bfa_ioc_portid(flash->ioc));
4086 bfa_alen_set(&msg->alen, len, flash->dbuf_pa);
4087 bfa_ioc_mbox_queue(flash->ioc, &flash->mb);
4088}
4089
4090/*
4091 * Send flash erase request.
4092 *
4093 * @param[in] cbarg - callback argument
4094 */
4095static void
4096bfa_flash_erase_send(void *cbarg)
4097{
4098 struct bfa_flash_s *flash = cbarg;
4099 struct bfi_flash_erase_req_s *msg =
4100 (struct bfi_flash_erase_req_s *) flash->mb.msg;
4101
4102 msg->type = be32_to_cpu(flash->type);
4103 msg->instance = flash->instance;
4104 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_ERASE_REQ,
4105 bfa_ioc_portid(flash->ioc));
4106 bfa_ioc_mbox_queue(flash->ioc, &flash->mb);
4107}
4108
4109/*
4110 * Process flash response messages upon receiving interrupts.
4111 *
4112 * @param[in] flasharg - flash structure
4113 * @param[in] msg - message structure
4114 */
4115static void
4116bfa_flash_intr(void *flasharg, struct bfi_mbmsg_s *msg)
4117{
4118 struct bfa_flash_s *flash = flasharg;
4119 u32 status;
4120
4121 union {
4122 struct bfi_flash_query_rsp_s *query;
4123 struct bfi_flash_erase_rsp_s *erase;
4124 struct bfi_flash_write_rsp_s *write;
4125 struct bfi_flash_read_rsp_s *read;
7826f304 4126 struct bfi_flash_event_s *event;
5a54b1d5
KG		 4127 struct bfi_mbmsg_s *msg;
4128 } m;
4129
4130 m.msg = msg;
4131 bfa_trc(flash, msg->mh.msg_id);
4132
4133 if (!flash->op_busy && msg->mh.msg_id != BFI_FLASH_I2H_EVENT) {
4134 /* receiving response after ioc failure */
4135 bfa_trc(flash, 0x9999);
4136 return;
4137 }
4138
4139 switch (msg->mh.msg_id) {
4140 case BFI_FLASH_I2H_QUERY_RSP:
4141 status = be32_to_cpu(m.query->status);
4142 bfa_trc(flash, status);
4143 if (status == BFA_STATUS_OK) {
4144 u32 i;
4145 struct bfa_flash_attr_s *attr, *f;
4146
4147 attr = (struct bfa_flash_attr_s *) flash->ubuf;
4148 f = (struct bfa_flash_attr_s *) flash->dbuf_kva;
4149 attr->status = be32_to_cpu(f->status);
4150 attr->npart = be32_to_cpu(f->npart);
4151 bfa_trc(flash, attr->status);
4152 bfa_trc(flash, attr->npart);
4153 for (i = 0; i < attr->npart; i++) {
4154 attr->part[i].part_type =
4155 be32_to_cpu(f->part[i].part_type);
4156 attr->part[i].part_instance =
4157 be32_to_cpu(f->part[i].part_instance);
4158 attr->part[i].part_off =
4159 be32_to_cpu(f->part[i].part_off);
4160 attr->part[i].part_size =
4161 be32_to_cpu(f->part[i].part_size);
4162 attr->part[i].part_len =
4163 be32_to_cpu(f->part[i].part_len);
4164 attr->part[i].part_status =
4165 be32_to_cpu(f->part[i].part_status);
4166 }
4167 }
4168 flash->status = status;
4169 bfa_flash_cb(flash);
4170 break;
4171 case BFI_FLASH_I2H_ERASE_RSP:
4172 status = be32_to_cpu(m.erase->status);
4173 bfa_trc(flash, status);
4174 flash->status = status;
4175 bfa_flash_cb(flash);
4176 break;
4177 case BFI_FLASH_I2H_WRITE_RSP:
4178 status = be32_to_cpu(m.write->status);
4179 bfa_trc(flash, status);
4180 if (status != BFA_STATUS_OK || flash->residue == 0) {
4181 flash->status = status;
4182 bfa_flash_cb(flash);
4183 } else {
4184 bfa_trc(flash, flash->offset);
4185 bfa_flash_write_send(flash);
4186 }
4187 break;
4188 case BFI_FLASH_I2H_READ_RSP:
4189 status = be32_to_cpu(m.read->status);
4190 bfa_trc(flash, status);
4191 if (status != BFA_STATUS_OK) {
4192 flash->status = status;
4193 bfa_flash_cb(flash);
4194 } else {
4195 u32 len = be32_to_cpu(m.read->length);
4196 bfa_trc(flash, flash->offset);
4197 bfa_trc(flash, len);
4198 memcpy(flash->ubuf + flash->offset,
4199 flash->dbuf_kva, len);
4200 flash->residue -= len;
4201 flash->offset += len;
4202 if (flash->residue == 0) {
4203 flash->status = status;
4204 bfa_flash_cb(flash);
4205 } else
4206 bfa_flash_read_send(flash);
4207 }
4208 break;
4209 case BFI_FLASH_I2H_BOOT_VER_RSP:
7826f304 4210 break;
5a54b1d5 4211 case BFI_FLASH_I2H_EVENT:
7826f304
KG		 4212 status = be32_to_cpu(m.event->status);
4213 bfa_trc(flash, status);
4214 if (status == BFA_STATUS_BAD_FWCFG)
4215 bfa_ioc_aen_post(flash->ioc, BFA_IOC_AEN_FWCFG_ERROR);
4216 else if (status == BFA_STATUS_INVALID_VENDOR) {
4217 u32 param;
4218 param = be32_to_cpu(m.event->param);
4219 bfa_trc(flash, param);
4220 bfa_ioc_aen_post(flash->ioc,
4221 BFA_IOC_AEN_INVALID_VENDOR);
4222 }
5a54b1d5
KG		 4223 break;
4224
4225 default:
4226 WARN_ON(1);
4227 }
4228}
4229
4230/*
4231 * Flash memory info API.
4232 *
4233 * @param[in] mincfg - minimal cfg variable
4234 */
4235u32
4236bfa_flash_meminfo(bfa_boolean_t mincfg)
4237{
4238 /* min driver doesn't need flash */
4239 if (mincfg)
4240 return 0;
4241 return BFA_ROUNDUP(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
4242}
4243
4244/*
4245 * Flash attach API.
4246 *
4247 * @param[in] flash - flash structure
4248 * @param[in] ioc - ioc structure
4249 * @param[in] dev - device structure
4250 * @param[in] trcmod - trace module
4251 * @param[in] logmod - log module
4252 */
4253void
4254bfa_flash_attach(struct bfa_flash_s *flash, struct bfa_ioc_s *ioc, void *dev,
4255 struct bfa_trc_mod_s *trcmod, bfa_boolean_t mincfg)
4256{
4257 flash->ioc = ioc;
4258 flash->trcmod = trcmod;
4259 flash->cbfn = NULL;
4260 flash->cbarg = NULL;
4261 flash->op_busy = 0;
4262
4263 bfa_ioc_mbox_regisr(flash->ioc, BFI_MC_FLASH, bfa_flash_intr, flash);
4264 bfa_q_qe_init(&flash->ioc_notify);
4265 bfa_ioc_notify_init(&flash->ioc_notify, bfa_flash_notify, flash);
4266 list_add_tail(&flash->ioc_notify.qe, &flash->ioc->notify_q);
4267
4268 /* min driver doesn't need flash */
4269 if (mincfg) {
4270 flash->dbuf_kva = NULL;
4271 flash->dbuf_pa = 0;
4272 }
4273}
4274
4275/*
4276 * Claim memory for flash
4277 *
4278 * @param[in] flash - flash structure
4279 * @param[in] dm_kva - pointer to virtual memory address
4280 * @param[in] dm_pa - physical memory address
4281 * @param[in] mincfg - minimal cfg variable
4282 */
4283void
4284bfa_flash_memclaim(struct bfa_flash_s *flash, u8 *dm_kva, u64 dm_pa,
4285 bfa_boolean_t mincfg)
4286{
4287 if (mincfg)
4288 return;
4289
4290 flash->dbuf_kva = dm_kva;
4291 flash->dbuf_pa = dm_pa;
4292 memset(flash->dbuf_kva, 0, BFA_FLASH_DMA_BUF_SZ);
4293 dm_kva += BFA_ROUNDUP(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
4294 dm_pa += BFA_ROUNDUP(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
4295}
4296
4297/*
4298 * Get flash attribute.
4299 *
4300 * @param[in] flash - flash structure
4301 * @param[in] attr - flash attribute structure
4302 * @param[in] cbfn - callback function
4303 * @param[in] cbarg - callback argument
4304 *
4305 * Return status.
4306 */
4307bfa_status_t
4308bfa_flash_get_attr(struct bfa_flash_s *flash, struct bfa_flash_attr_s *attr,
4309 bfa_cb_flash_t cbfn, void *cbarg)
4310{
4311 bfa_trc(flash, BFI_FLASH_H2I_QUERY_REQ);
4312
4313 if (!bfa_ioc_is_operational(flash->ioc))
4314 return BFA_STATUS_IOC_NON_OP;
4315
4316 if (flash->op_busy) {
4317 bfa_trc(flash, flash->op_busy);
4318 return BFA_STATUS_DEVBUSY;
4319 }
4320
4321 flash->op_busy = 1;
4322 flash->cbfn = cbfn;
4323 flash->cbarg = cbarg;
4324 flash->ubuf = (u8 *) attr;
4325 bfa_flash_query_send(flash);
4326
4327 return BFA_STATUS_OK;
4328}
4329
4330/*
4331 * Erase flash partition.
4332 *
4333 * @param[in] flash - flash structure
4334 * @param[in] type - flash partition type
4335 * @param[in] instance - flash partition instance
4336 * @param[in] cbfn - callback function
4337 * @param[in] cbarg - callback argument
4338 *
4339 * Return status.
4340 */
4341bfa_status_t
4342bfa_flash_erase_part(struct bfa_flash_s *flash, enum bfa_flash_part_type type,
4343 u8 instance, bfa_cb_flash_t cbfn, void *cbarg)
4344{
4345 bfa_trc(flash, BFI_FLASH_H2I_ERASE_REQ);
4346 bfa_trc(flash, type);
4347 bfa_trc(flash, instance);
4348
4349 if (!bfa_ioc_is_operational(flash->ioc))
4350 return BFA_STATUS_IOC_NON_OP;
4351
4352 if (flash->op_busy) {
4353 bfa_trc(flash, flash->op_busy);
4354 return BFA_STATUS_DEVBUSY;
4355 }
4356
4357 flash->op_busy = 1;
4358 flash->cbfn = cbfn;
4359 flash->cbarg = cbarg;
4360 flash->type = type;
4361 flash->instance = instance;
4362
4363 bfa_flash_erase_send(flash);
7826f304
KG		 4364 bfa_flash_aen_audit_post(flash->ioc, BFA_AUDIT_AEN_FLASH_ERASE,
4365 instance, type);
5a54b1d5
KG		 4366 return BFA_STATUS_OK;
4367}
4368
4369/*
4370 * Update flash partition.
4371 *
4372 * @param[in] flash - flash structure
4373 * @param[in] type - flash partition type
4374 * @param[in] instance - flash partition instance
4375 * @param[in] buf - update data buffer
4376 * @param[in] len - data buffer length
4377 * @param[in] offset - offset relative to the partition starting address
4378 * @param[in] cbfn - callback function
4379 * @param[in] cbarg - callback argument
4380 *
4381 * Return status.
4382 */
4383bfa_status_t
4384bfa_flash_update_part(struct bfa_flash_s *flash, enum bfa_flash_part_type type,
4385 u8 instance, void *buf, u32 len, u32 offset,
4386 bfa_cb_flash_t cbfn, void *cbarg)
4387{
4388 bfa_trc(flash, BFI_FLASH_H2I_WRITE_REQ);
4389 bfa_trc(flash, type);
4390 bfa_trc(flash, instance);
4391 bfa_trc(flash, len);
4392 bfa_trc(flash, offset);
4393
4394 if (!bfa_ioc_is_operational(flash->ioc))
4395 return BFA_STATUS_IOC_NON_OP;
4396
4397 /*
4398 * 'len' must be in word (4-byte) boundary
4399 * 'offset' must be in sector (16kb) boundary
4400 */
4401 if (!len || (len & 0x03) || (offset & 0x00003FFF))
4402 return BFA_STATUS_FLASH_BAD_LEN;
4403
4404 if (type == BFA_FLASH_PART_MFG)
4405 return BFA_STATUS_EINVAL;
4406
4407 if (flash->op_busy) {
4408 bfa_trc(flash, flash->op_busy);
4409 return BFA_STATUS_DEVBUSY;
4410 }
4411
4412 flash->op_busy = 1;
4413 flash->cbfn = cbfn;
4414 flash->cbarg = cbarg;
4415 flash->type = type;
4416 flash->instance = instance;
4417 flash->residue = len;
4418 flash->offset = 0;
4419 flash->addr_off = offset;
4420 flash->ubuf = buf;
4421
4422 bfa_flash_write_send(flash);
4423 return BFA_STATUS_OK;
4424}
4425
4426/*
4427 * Read flash partition.
4428 *
4429 * @param[in] flash - flash structure
4430 * @param[in] type - flash partition type
4431 * @param[in] instance - flash partition instance
4432 * @param[in] buf - read data buffer
4433 * @param[in] len - data buffer length
4434 * @param[in] offset - offset relative to the partition starting address
4435 * @param[in] cbfn - callback function
4436 * @param[in] cbarg - callback argument
4437 *
4438 * Return status.
4439 */
4440bfa_status_t
4441bfa_flash_read_part(struct bfa_flash_s *flash, enum bfa_flash_part_type type,
4442 u8 instance, void *buf, u32 len, u32 offset,
4443 bfa_cb_flash_t cbfn, void *cbarg)
4444{
4445 bfa_trc(flash, BFI_FLASH_H2I_READ_REQ);
4446 bfa_trc(flash, type);
4447 bfa_trc(flash, instance);
4448 bfa_trc(flash, len);
4449 bfa_trc(flash, offset);
4450
4451 if (!bfa_ioc_is_operational(flash->ioc))
4452 return BFA_STATUS_IOC_NON_OP;
4453
4454 /*
4455 * 'len' must be in word (4-byte) boundary
4456 * 'offset' must be in sector (16kb) boundary
4457 */
4458 if (!len || (len & 0x03) || (offset & 0x00003FFF))
4459 return BFA_STATUS_FLASH_BAD_LEN;
4460
4461 if (flash->op_busy) {
4462 bfa_trc(flash, flash->op_busy);
4463 return BFA_STATUS_DEVBUSY;
4464 }
4465
4466 flash->op_busy = 1;
4467 flash->cbfn = cbfn;
4468 flash->cbarg = cbarg;
4469 flash->type = type;
4470 flash->instance = instance;
4471 flash->residue = len;
4472 flash->offset = 0;
4473 flash->addr_off = offset;
4474 flash->ubuf = buf;
4475 bfa_flash_read_send(flash);
4476
4477 return BFA_STATUS_OK;
4478}
3d7fc66d
KG		 4479
4480/*
4481 * DIAG module specific
4482 */
4483
4484#define BFA_DIAG_MEMTEST_TOV 50000 /* memtest timeout in msec */
bd5a0260 4485#define CT2_BFA_DIAG_MEMTEST_TOV (9*30*1000) /* 4.5 min */
3d7fc66d
KG		 4486
4487/* IOC event handler */
4488static void
4489bfa_diag_notify(void *diag_arg, enum bfa_ioc_event_e event)
4490{
4491 struct bfa_diag_s *diag = diag_arg;
4492
4493 bfa_trc(diag, event);
4494 bfa_trc(diag, diag->block);
4495 bfa_trc(diag, diag->fwping.lock);
4496 bfa_trc(diag, diag->tsensor.lock);
4497
4498 switch (event) {
4499 case BFA_IOC_E_DISABLED:
4500 case BFA_IOC_E_FAILED:
4501 if (diag->fwping.lock) {
4502 diag->fwping.status = BFA_STATUS_IOC_FAILURE;
4503 diag->fwping.cbfn(diag->fwping.cbarg,
4504 diag->fwping.status);
4505 diag->fwping.lock = 0;
4506 }
4507
4508 if (diag->tsensor.lock) {
4509 diag->tsensor.status = BFA_STATUS_IOC_FAILURE;
4510 diag->tsensor.cbfn(diag->tsensor.cbarg,
4511 diag->tsensor.status);
4512 diag->tsensor.lock = 0;
4513 }
4514
4515 if (diag->block) {
4516 if (diag->timer_active) {
4517 bfa_timer_stop(&diag->timer);
4518 diag->timer_active = 0;
4519 }
4520
4521 diag->status = BFA_STATUS_IOC_FAILURE;
4522 diag->cbfn(diag->cbarg, diag->status);
4523 diag->block = 0;
4524 }
4525 break;
4526
4527 default:
4528 break;
4529 }
4530}
4531
4532static void
4533bfa_diag_memtest_done(void *cbarg)
4534{
4535 struct bfa_diag_s *diag = cbarg;
4536 struct bfa_ioc_s *ioc = diag->ioc;
4537 struct bfa_diag_memtest_result *res = diag->result;
4538 u32 loff = BFI_BOOT_MEMTEST_RES_ADDR;
4539 u32 pgnum, pgoff, i;
4540
4541 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, loff);
4542 pgoff = PSS_SMEM_PGOFF(loff);
4543
4544 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
4545
4546 for (i = 0; i < (sizeof(struct bfa_diag_memtest_result) /
4547 sizeof(u32)); i++) {
4548 /* read test result from smem */
4549 *((u32 *) res + i) =
4550 bfa_mem_read(ioc->ioc_regs.smem_page_start, loff);
4551 loff += sizeof(u32);
4552 }
4553
4554 /* Reset IOC fwstates to BFI_IOC_UNINIT */
4555 bfa_ioc_reset_fwstate(ioc);
4556
4557 res->status = swab32(res->status);
4558 bfa_trc(diag, res->status);
4559
4560 if (res->status == BFI_BOOT_MEMTEST_RES_SIG)
4561 diag->status = BFA_STATUS_OK;
4562 else {
4563 diag->status = BFA_STATUS_MEMTEST_FAILED;
4564 res->addr = swab32(res->addr);
4565 res->exp = swab32(res->exp);
4566 res->act = swab32(res->act);
4567 res->err_status = swab32(res->err_status);
4568 res->err_status1 = swab32(res->err_status1);
4569 res->err_addr = swab32(res->err_addr);
4570 bfa_trc(diag, res->addr);
4571 bfa_trc(diag, res->exp);
4572 bfa_trc(diag, res->act);
4573 bfa_trc(diag, res->err_status);
4574 bfa_trc(diag, res->err_status1);
4575 bfa_trc(diag, res->err_addr);
4576 }
4577 diag->timer_active = 0;
4578 diag->cbfn(diag->cbarg, diag->status);
4579 diag->block = 0;
4580}
4581
4582/*
4583 * Firmware ping
4584 */
4585
4586/*
4587 * Perform DMA test directly
4588 */
4589static void
4590diag_fwping_send(struct bfa_diag_s *diag)
4591{
4592 struct bfi_diag_fwping_req_s *fwping_req;
4593 u32 i;
4594
4595 bfa_trc(diag, diag->fwping.dbuf_pa);
4596
4597 /* fill DMA area with pattern */
4598 for (i = 0; i < (BFI_DIAG_DMA_BUF_SZ >> 2); i++)
4599 *((u32 *)diag->fwping.dbuf_kva + i) = diag->fwping.data;
4600
4601 /* Fill mbox msg */
4602 fwping_req = (struct bfi_diag_fwping_req_s *)diag->fwping.mbcmd.msg;
4603
4604 /* Setup SG list */
4605 bfa_alen_set(&fwping_req->alen, BFI_DIAG_DMA_BUF_SZ,
4606 diag->fwping.dbuf_pa);
4607 /* Set up dma count */
4608 fwping_req->count = cpu_to_be32(diag->fwping.count);
4609 /* Set up data pattern */
4610 fwping_req->data = diag->fwping.data;
4611
4612 /* build host command */
4613 bfi_h2i_set(fwping_req->mh, BFI_MC_DIAG, BFI_DIAG_H2I_FWPING,
4614 bfa_ioc_portid(diag->ioc));
4615
4616 /* send mbox cmd */
4617 bfa_ioc_mbox_queue(diag->ioc, &diag->fwping.mbcmd);
4618}
4619
4620static void
4621diag_fwping_comp(struct bfa_diag_s *diag,
4622 struct bfi_diag_fwping_rsp_s *diag_rsp)
4623{
4624 u32 rsp_data = diag_rsp->data;
4625 u8 rsp_dma_status = diag_rsp->dma_status;
4626
4627 bfa_trc(diag, rsp_data);
4628 bfa_trc(diag, rsp_dma_status);
4629
4630 if (rsp_dma_status == BFA_STATUS_OK) {
4631 u32 i, pat;
4632 pat = (diag->fwping.count & 0x1) ? ~(diag->fwping.data) :
4633 diag->fwping.data;
4634 /* Check mbox data */
4635 if (diag->fwping.data != rsp_data) {
4636 bfa_trc(diag, rsp_data);
4637 diag->fwping.result->dmastatus =
4638 BFA_STATUS_DATACORRUPTED;
4639 diag->fwping.status = BFA_STATUS_DATACORRUPTED;
4640 diag->fwping.cbfn(diag->fwping.cbarg,
4641 diag->fwping.status);
4642 diag->fwping.lock = 0;
4643 return;
4644 }
4645 /* Check dma pattern */
4646 for (i = 0; i < (BFI_DIAG_DMA_BUF_SZ >> 2); i++) {
4647 if (*((u32 *)diag->fwping.dbuf_kva + i) != pat) {
4648 bfa_trc(diag, i);
4649 bfa_trc(diag, pat);
4650 bfa_trc(diag,
4651 *((u32 *)diag->fwping.dbuf_kva + i));
4652 diag->fwping.result->dmastatus =
4653 BFA_STATUS_DATACORRUPTED;
4654 diag->fwping.status = BFA_STATUS_DATACORRUPTED;
4655 diag->fwping.cbfn(diag->fwping.cbarg,
4656 diag->fwping.status);
4657 diag->fwping.lock = 0;
4658 return;
4659 }
4660 }
4661 diag->fwping.result->dmastatus = BFA_STATUS_OK;
4662 diag->fwping.status = BFA_STATUS_OK;
4663 diag->fwping.cbfn(diag->fwping.cbarg, diag->fwping.status);
4664 diag->fwping.lock = 0;
4665 } else {
4666 diag->fwping.status = BFA_STATUS_HDMA_FAILED;
4667 diag->fwping.cbfn(diag->fwping.cbarg, diag->fwping.status);
4668 diag->fwping.lock = 0;
4669 }
4670}
4671
4672/*
4673 * Temperature Sensor
4674 */
4675
4676static void
4677diag_tempsensor_send(struct bfa_diag_s *diag)
4678{
4679 struct bfi_diag_ts_req_s *msg;
4680
4681 msg = (struct bfi_diag_ts_req_s *)diag->tsensor.mbcmd.msg;
4682 bfa_trc(diag, msg->temp);
4683 /* build host command */
4684 bfi_h2i_set(msg->mh, BFI_MC_DIAG, BFI_DIAG_H2I_TEMPSENSOR,
4685 bfa_ioc_portid(diag->ioc));
4686 /* send mbox cmd */
4687 bfa_ioc_mbox_queue(diag->ioc, &diag->tsensor.mbcmd);
4688}
4689
4690static void
4691diag_tempsensor_comp(struct bfa_diag_s *diag, bfi_diag_ts_rsp_t *rsp)
4692{
4693 if (!diag->tsensor.lock) {
4694 /* receiving response after ioc failure */
4695 bfa_trc(diag, diag->tsensor.lock);
4696 return;
4697 }
4698
4699 /*
4700 * ASIC junction tempsensor is a reg read operation
4701 * it will always return OK
4702 */
4703 diag->tsensor.temp->temp = be16_to_cpu(rsp->temp);
4704 diag->tsensor.temp->ts_junc = rsp->ts_junc;
4705 diag->tsensor.temp->ts_brd = rsp->ts_brd;
3d7fc66d
KG		 4706
4707 if (rsp->ts_brd) {
4a49b044
KG		 4708 /* tsensor.temp->status is brd_temp status */
4709 diag->tsensor.temp->status = rsp->status;
3d7fc66d
KG		 4710 if (rsp->status == BFA_STATUS_OK) {
4711 diag->tsensor.temp->brd_temp =
4712 be16_to_cpu(rsp->brd_temp);
4a49b044 4713 } else
3d7fc66d 4714 diag->tsensor.temp->brd_temp = 0;
3d7fc66d 4715 }
4a49b044
KG		 4716
4717 bfa_trc(diag, rsp->status);
3d7fc66d
KG		 4718 bfa_trc(diag, rsp->ts_junc);
4719 bfa_trc(diag, rsp->temp);
4720 bfa_trc(diag, rsp->ts_brd);
4721 bfa_trc(diag, rsp->brd_temp);
4a49b044
KG		 4722
4723 /* tsensor status is always good bcos we always have junction temp */
4724 diag->tsensor.status = BFA_STATUS_OK;
3d7fc66d
KG		 4725 diag->tsensor.cbfn(diag->tsensor.cbarg, diag->tsensor.status);
4726 diag->tsensor.lock = 0;
4727}
4728
4729/*
4730 * LED Test command
4731 */
4732static void
4733diag_ledtest_send(struct bfa_diag_s *diag, struct bfa_diag_ledtest_s *ledtest)
4734{
4735 struct bfi_diag_ledtest_req_s *msg;
4736
4737 msg = (struct bfi_diag_ledtest_req_s *)diag->ledtest.mbcmd.msg;
4738 /* build host command */
4739 bfi_h2i_set(msg->mh, BFI_MC_DIAG, BFI_DIAG_H2I_LEDTEST,
4740 bfa_ioc_portid(diag->ioc));
4741
4742 /*
4743 * convert the freq from N blinks per 10 sec to
4744 * crossbow ontime value. We do it here because division is need
4745 */
4746 if (ledtest->freq)
4747 ledtest->freq = 500 / ledtest->freq;
4748
4749 if (ledtest->freq == 0)
4750 ledtest->freq = 1;
4751
4752 bfa_trc(diag, ledtest->freq);
4753 /* mcpy(&ledtest_req->req, ledtest, sizeof(bfa_diag_ledtest_t)); */
4754 msg->cmd = (u8) ledtest->cmd;
4755 msg->color = (u8) ledtest->color;
4756 msg->portid = bfa_ioc_portid(diag->ioc);
4757 msg->led = ledtest->led;
4758 msg->freq = cpu_to_be16(ledtest->freq);
4759
4760 /* send mbox cmd */
4761 bfa_ioc_mbox_queue(diag->ioc, &diag->ledtest.mbcmd);
4762}
4763
4764static void
8919678e 4765diag_ledtest_comp(struct bfa_diag_s *diag, struct bfi_diag_ledtest_rsp_s *msg)
3d7fc66d
KG		 4766{
4767 bfa_trc(diag, diag->ledtest.lock);
4768 diag->ledtest.lock = BFA_FALSE;
4769 /* no bfa_cb_queue is needed because driver is not waiting */
4770}
4771
4772/*
4773 * Port beaconing
4774 */
4775static void
4776diag_portbeacon_send(struct bfa_diag_s *diag, bfa_boolean_t beacon, u32 sec)
4777{
4778 struct bfi_diag_portbeacon_req_s *msg;
4779
4780 msg = (struct bfi_diag_portbeacon_req_s *)diag->beacon.mbcmd.msg;
4781 /* build host command */
4782 bfi_h2i_set(msg->mh, BFI_MC_DIAG, BFI_DIAG_H2I_PORTBEACON,
4783 bfa_ioc_portid(diag->ioc));
4784 msg->beacon = beacon;
4785 msg->period = cpu_to_be32(sec);
4786 /* send mbox cmd */
4787 bfa_ioc_mbox_queue(diag->ioc, &diag->beacon.mbcmd);
4788}
4789
4790static void
4791diag_portbeacon_comp(struct bfa_diag_s *diag)
4792{
4793 bfa_trc(diag, diag->beacon.state);
4794 diag->beacon.state = BFA_FALSE;
4795 if (diag->cbfn_beacon)
4796 diag->cbfn_beacon(diag->dev, BFA_FALSE, diag->beacon.link_e2e);
4797}
4798
4799/*
4800 * Diag hmbox handler
4801 */
4802void
4803bfa_diag_intr(void *diagarg, struct bfi_mbmsg_s *msg)
4804{
4805 struct bfa_diag_s *diag = diagarg;
4806
4807 switch (msg->mh.msg_id) {
4808 case BFI_DIAG_I2H_PORTBEACON:
4809 diag_portbeacon_comp(diag);
4810 break;
4811 case BFI_DIAG_I2H_FWPING:
4812 diag_fwping_comp(diag, (struct bfi_diag_fwping_rsp_s *) msg);
4813 break;
4814 case BFI_DIAG_I2H_TEMPSENSOR:
4815 diag_tempsensor_comp(diag, (bfi_diag_ts_rsp_t *) msg);
4816 break;
4817 case BFI_DIAG_I2H_LEDTEST:
4818 diag_ledtest_comp(diag, (struct bfi_diag_ledtest_rsp_s *) msg);
4819 break;
4820 default:
4821 bfa_trc(diag, msg->mh.msg_id);
4822 WARN_ON(1);
4823 }
4824}
4825
4826/*
4827 * Gen RAM Test
4828 *
4829 * @param[in] *diag - diag data struct
4830 * @param[in] *memtest - mem test params input from upper layer,
4831 * @param[in] pattern - mem test pattern
4832 * @param[in] *result - mem test result
4833 * @param[in] cbfn - mem test callback functioin
4834 * @param[in] cbarg - callback functioin arg
4835 *
4836 * @param[out]
4837 */
4838bfa_status_t
4839bfa_diag_memtest(struct bfa_diag_s *diag, struct bfa_diag_memtest_s *memtest,
4840 u32 pattern, struct bfa_diag_memtest_result *result,
4841 bfa_cb_diag_t cbfn, void *cbarg)
4842{
bd5a0260
KG		 4843 u32 memtest_tov;
4844
3d7fc66d
KG		 4845 bfa_trc(diag, pattern);
4846
4847 if (!bfa_ioc_adapter_is_disabled(diag->ioc))
4848 return BFA_STATUS_ADAPTER_ENABLED;
4849
4850 /* check to see if there is another destructive diag cmd running */
4851 if (diag->block) {
4852 bfa_trc(diag, diag->block);
4853 return BFA_STATUS_DEVBUSY;
4854 } else
4855 diag->block = 1;
4856
4857 diag->result = result;
4858 diag->cbfn = cbfn;
4859 diag->cbarg = cbarg;
4860
4861 /* download memtest code and take LPU0 out of reset */
4862 bfa_ioc_boot(diag->ioc, BFI_FWBOOT_TYPE_MEMTEST, BFI_FWBOOT_ENV_OS);
4863
bd5a0260
KG		 4864 memtest_tov = (bfa_ioc_asic_gen(diag->ioc) == BFI_ASIC_GEN_CT2) ?
4865 CT2_BFA_DIAG_MEMTEST_TOV : BFA_DIAG_MEMTEST_TOV;
3d7fc66d 4866 bfa_timer_begin(diag->ioc->timer_mod, &diag->timer,
bd5a0260 4867 bfa_diag_memtest_done, diag, memtest_tov);
3d7fc66d
KG		 4868 diag->timer_active = 1;
4869 return BFA_STATUS_OK;
4870}
4871
4872/*
4873 * DIAG firmware ping command
4874 *
4875 * @param[in] *diag - diag data struct
4876 * @param[in] cnt - dma loop count for testing PCIE
4877 * @param[in] data - data pattern to pass in fw
4878 * @param[in] *result - pt to bfa_diag_fwping_result_t data struct
4879 * @param[in] cbfn - callback function
4880 * @param[in] *cbarg - callback functioin arg
4881 *
4882 * @param[out]
4883 */
4884bfa_status_t
4885bfa_diag_fwping(struct bfa_diag_s *diag, u32 cnt, u32 data,
4886 struct bfa_diag_results_fwping *result, bfa_cb_diag_t cbfn,
4887 void *cbarg)
4888{
4889 bfa_trc(diag, cnt);
4890 bfa_trc(diag, data);
4891
4892 if (!bfa_ioc_is_operational(diag->ioc))
4893 return BFA_STATUS_IOC_NON_OP;
4894
4895 if (bfa_asic_id_ct2(bfa_ioc_devid((diag->ioc))) &&
4896 ((diag->ioc)->clscode == BFI_PCIFN_CLASS_ETH))
4897 return BFA_STATUS_CMD_NOTSUPP;
4898
4899 /* check to see if there is another destructive diag cmd running */
4900 if (diag->block || diag->fwping.lock) {
4901 bfa_trc(diag, diag->block);
4902 bfa_trc(diag, diag->fwping.lock);
4903 return BFA_STATUS_DEVBUSY;
4904 }
4905
4906 /* Initialization */
4907 diag->fwping.lock = 1;
4908 diag->fwping.cbfn = cbfn;
4909 diag->fwping.cbarg = cbarg;
4910 diag->fwping.result = result;
4911 diag->fwping.data = data;
4912 diag->fwping.count = cnt;
4913
4914 /* Init test results */
4915 diag->fwping.result->data = 0;
4916 diag->fwping.result->status = BFA_STATUS_OK;
4917
4918 /* kick off the first ping */
4919 diag_fwping_send(diag);
4920 return BFA_STATUS_OK;
4921}
4922
4923/*
4924 * Read Temperature Sensor
4925 *
4926 * @param[in] *diag - diag data struct
4927 * @param[in] *result - pt to bfa_diag_temp_t data struct
4928 * @param[in] cbfn - callback function
4929 * @param[in] *cbarg - callback functioin arg
4930 *
4931 * @param[out]
4932 */
4933bfa_status_t
4934bfa_diag_tsensor_query(struct bfa_diag_s *diag,
4935 struct bfa_diag_results_tempsensor_s *result,
4936 bfa_cb_diag_t cbfn, void *cbarg)
4937{
4938 /* check to see if there is a destructive diag cmd running */
4939 if (diag->block || diag->tsensor.lock) {
4940 bfa_trc(diag, diag->block);
4941 bfa_trc(diag, diag->tsensor.lock);
4942 return BFA_STATUS_DEVBUSY;
4943 }
4944
4945 if (!bfa_ioc_is_operational(diag->ioc))
4946 return BFA_STATUS_IOC_NON_OP;
4947
4948 /* Init diag mod params */
4949 diag->tsensor.lock = 1;
4950 diag->tsensor.temp = result;
4951 diag->tsensor.cbfn = cbfn;
4952 diag->tsensor.cbarg = cbarg;
4a49b044 4953 diag->tsensor.status = BFA_STATUS_OK;
3d7fc66d
KG		 4954
4955 /* Send msg to fw */
4956 diag_tempsensor_send(diag);
4957
4958 return BFA_STATUS_OK;
4959}
4960
4961/*
4962 * LED Test command
4963 *
4964 * @param[in] *diag - diag data struct
4965 * @param[in] *ledtest - pt to ledtest data structure
4966 *
4967 * @param[out]
4968 */
4969bfa_status_t
4970bfa_diag_ledtest(struct bfa_diag_s *diag, struct bfa_diag_ledtest_s *ledtest)
4971{
4972 bfa_trc(diag, ledtest->cmd);
4973
4974 if (!bfa_ioc_is_operational(diag->ioc))
4975 return BFA_STATUS_IOC_NON_OP;
4976
4977 if (diag->beacon.state)
4978 return BFA_STATUS_BEACON_ON;
4979
4980 if (diag->ledtest.lock)
4981 return BFA_STATUS_LEDTEST_OP;
4982
4983 /* Send msg to fw */
4984 diag->ledtest.lock = BFA_TRUE;
4985 diag_ledtest_send(diag, ledtest);
4986
4987 return BFA_STATUS_OK;
4988}
4989
4990/*
4991 * Port beaconing command
4992 *
4993 * @param[in] *diag - diag data struct
4994 * @param[in] beacon - port beaconing 1:ON 0:OFF
4995 * @param[in] link_e2e_beacon - link beaconing 1:ON 0:OFF
4996 * @param[in] sec - beaconing duration in seconds
4997 *
4998 * @param[out]
4999 */
5000bfa_status_t
5001bfa_diag_beacon_port(struct bfa_diag_s *diag, bfa_boolean_t beacon,
5002 bfa_boolean_t link_e2e_beacon, uint32_t sec)
5003{
5004 bfa_trc(diag, beacon);
5005 bfa_trc(diag, link_e2e_beacon);
5006 bfa_trc(diag, sec);
5007
5008 if (!bfa_ioc_is_operational(diag->ioc))
5009 return BFA_STATUS_IOC_NON_OP;
5010
5011 if (diag->ledtest.lock)
5012 return BFA_STATUS_LEDTEST_OP;
5013
5014 if (diag->beacon.state && beacon) /* beacon alread on */
5015 return BFA_STATUS_BEACON_ON;
5016
5017 diag->beacon.state = beacon;
5018 diag->beacon.link_e2e = link_e2e_beacon;
5019 if (diag->cbfn_beacon)
5020 diag->cbfn_beacon(diag->dev, beacon, link_e2e_beacon);
5021
5022 /* Send msg to fw */
5023 diag_portbeacon_send(diag, beacon, sec);
5024
5025 return BFA_STATUS_OK;
5026}
5027
5028/*
5029 * Return DMA memory needed by diag module.
5030 */
5031u32
5032bfa_diag_meminfo(void)
5033{
5034 return BFA_ROUNDUP(BFI_DIAG_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
5035}
5036
5037/*
5038 * Attach virtual and physical memory for Diag.
5039 */
5040void
5041bfa_diag_attach(struct bfa_diag_s *diag, struct bfa_ioc_s *ioc, void *dev,
5042 bfa_cb_diag_beacon_t cbfn_beacon, struct bfa_trc_mod_s *trcmod)
5043{
5044 diag->dev = dev;
5045 diag->ioc = ioc;
5046 diag->trcmod = trcmod;
5047
5048 diag->block = 0;
5049 diag->cbfn = NULL;
5050 diag->cbarg = NULL;
5051 diag->result = NULL;
5052 diag->cbfn_beacon = cbfn_beacon;
5053
5054 bfa_ioc_mbox_regisr(diag->ioc, BFI_MC_DIAG, bfa_diag_intr, diag);
5055 bfa_q_qe_init(&diag->ioc_notify);
5056 bfa_ioc_notify_init(&diag->ioc_notify, bfa_diag_notify, diag);
5057 list_add_tail(&diag->ioc_notify.qe, &diag->ioc->notify_q);
5058}
5059
5060void
5061bfa_diag_memclaim(struct bfa_diag_s *diag, u8 *dm_kva, u64 dm_pa)
5062{
5063 diag->fwping.dbuf_kva = dm_kva;
5064 diag->fwping.dbuf_pa = dm_pa;
5065 memset(diag->fwping.dbuf_kva, 0, BFI_DIAG_DMA_BUF_SZ);
5066}
3350d98d
KG		 5067
5068/*
5069 * PHY module specific
5070 */
5071#define BFA_PHY_DMA_BUF_SZ 0x02000 /* 8k dma buffer */
5072#define BFA_PHY_LOCK_STATUS 0x018878 /* phy semaphore status reg */
5073
5074static void
5075bfa_phy_ntoh32(u32 *obuf, u32 *ibuf, int sz)
5076{
5077 int i, m = sz >> 2;
5078
5079 for (i = 0; i < m; i++)
5080 obuf[i] = be32_to_cpu(ibuf[i]);
5081}
5082
5083static bfa_boolean_t
5084bfa_phy_present(struct bfa_phy_s *phy)
5085{
5086 return (phy->ioc->attr->card_type == BFA_MFG_TYPE_LIGHTNING);
5087}
5088
5089static void
5090bfa_phy_notify(void *cbarg, enum bfa_ioc_event_e event)
5091{
5092 struct bfa_phy_s *phy = cbarg;
5093
5094 bfa_trc(phy, event);
5095
5096 switch (event) {
5097 case BFA_IOC_E_DISABLED:
5098 case BFA_IOC_E_FAILED:
5099 if (phy->op_busy) {
5100 phy->status = BFA_STATUS_IOC_FAILURE;
5101 phy->cbfn(phy->cbarg, phy->status);
5102 phy->op_busy = 0;
5103 }
5104 break;
5105
5106 default:
5107 break;
5108 }
5109}
5110
5111/*
5112 * Send phy attribute query request.
5113 *
5114 * @param[in] cbarg - callback argument
5115 */
5116static void
5117bfa_phy_query_send(void *cbarg)
5118{
5119 struct bfa_phy_s *phy = cbarg;
5120 struct bfi_phy_query_req_s *msg =
5121 (struct bfi_phy_query_req_s *) phy->mb.msg;
5122
5123 msg->instance = phy->instance;
5124 bfi_h2i_set(msg->mh, BFI_MC_PHY, BFI_PHY_H2I_QUERY_REQ,
5125 bfa_ioc_portid(phy->ioc));
5126 bfa_alen_set(&msg->alen, sizeof(struct bfa_phy_attr_s), phy->dbuf_pa);
5127 bfa_ioc_mbox_queue(phy->ioc, &phy->mb);
5128}
5129
5130/*
5131 * Send phy write request.
5132 *
5133 * @param[in] cbarg - callback argument
5134 */
5135static void
5136bfa_phy_write_send(void *cbarg)
5137{
5138 struct bfa_phy_s *phy = cbarg;
5139 struct bfi_phy_write_req_s *msg =
5140 (struct bfi_phy_write_req_s *) phy->mb.msg;
5141 u32 len;
5142 u16 *buf, *dbuf;
5143 int i, sz;
5144
5145 msg->instance = phy->instance;
5146 msg->offset = cpu_to_be32(phy->addr_off + phy->offset);
5147 len = (phy->residue < BFA_PHY_DMA_BUF_SZ) ?
5148 phy->residue : BFA_PHY_DMA_BUF_SZ;
5149 msg->length = cpu_to_be32(len);
5150
5151 /* indicate if it's the last msg of the whole write operation */
5152 msg->last = (len == phy->residue) ? 1 : 0;
5153
5154 bfi_h2i_set(msg->mh, BFI_MC_PHY, BFI_PHY_H2I_WRITE_REQ,
5155 bfa_ioc_portid(phy->ioc));
5156 bfa_alen_set(&msg->alen, len, phy->dbuf_pa);
5157
5158 buf = (u16 *) (phy->ubuf + phy->offset);
5159 dbuf = (u16 *)phy->dbuf_kva;
5160 sz = len >> 1;
5161 for (i = 0; i < sz; i++)
5162 buf[i] = cpu_to_be16(dbuf[i]);
5163
5164 bfa_ioc_mbox_queue(phy->ioc, &phy->mb);
5165
5166 phy->residue -= len;
5167 phy->offset += len;
5168}
5169
5170/*
5171 * Send phy read request.
5172 *
5173 * @param[in] cbarg - callback argument
5174 */
5175static void
5176bfa_phy_read_send(void *cbarg)
5177{
5178 struct bfa_phy_s *phy = cbarg;
5179 struct bfi_phy_read_req_s *msg =
5180 (struct bfi_phy_read_req_s *) phy->mb.msg;
5181 u32 len;
5182
5183 msg->instance = phy->instance;
5184 msg->offset = cpu_to_be32(phy->addr_off + phy->offset);
5185 len = (phy->residue < BFA_PHY_DMA_BUF_SZ) ?
5186 phy->residue : BFA_PHY_DMA_BUF_SZ;
5187 msg->length = cpu_to_be32(len);
5188 bfi_h2i_set(msg->mh, BFI_MC_PHY, BFI_PHY_H2I_READ_REQ,
5189 bfa_ioc_portid(phy->ioc));
5190 bfa_alen_set(&msg->alen, len, phy->dbuf_pa);
5191 bfa_ioc_mbox_queue(phy->ioc, &phy->mb);
5192}
5193
5194/*
5195 * Send phy stats request.
5196 *
5197 * @param[in] cbarg - callback argument
5198 */
5199static void
5200bfa_phy_stats_send(void *cbarg)
5201{
5202 struct bfa_phy_s *phy = cbarg;
5203 struct bfi_phy_stats_req_s *msg =
5204 (struct bfi_phy_stats_req_s *) phy->mb.msg;
5205
5206 msg->instance = phy->instance;
5207 bfi_h2i_set(msg->mh, BFI_MC_PHY, BFI_PHY_H2I_STATS_REQ,
5208 bfa_ioc_portid(phy->ioc));
5209 bfa_alen_set(&msg->alen, sizeof(struct bfa_phy_stats_s), phy->dbuf_pa);
5210 bfa_ioc_mbox_queue(phy->ioc, &phy->mb);
5211}
5212
5213/*
5214 * Flash memory info API.
5215 *
5216 * @param[in] mincfg - minimal cfg variable
5217 */
5218u32
5219bfa_phy_meminfo(bfa_boolean_t mincfg)
5220{
5221 /* min driver doesn't need phy */
5222 if (mincfg)
5223 return 0;
5224
5225 return BFA_ROUNDUP(BFA_PHY_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
5226}
5227
5228/*
5229 * Flash attach API.
5230 *
5231 * @param[in] phy - phy structure
5232 * @param[in] ioc - ioc structure
5233 * @param[in] dev - device structure
5234 * @param[in] trcmod - trace module
5235 * @param[in] logmod - log module
5236 */
5237void
5238bfa_phy_attach(struct bfa_phy_s *phy, struct bfa_ioc_s *ioc, void *dev,
5239 struct bfa_trc_mod_s *trcmod, bfa_boolean_t mincfg)
5240{
5241 phy->ioc = ioc;
5242 phy->trcmod = trcmod;
5243 phy->cbfn = NULL;
5244 phy->cbarg = NULL;
5245 phy->op_busy = 0;
5246
5247 bfa_ioc_mbox_regisr(phy->ioc, BFI_MC_PHY, bfa_phy_intr, phy);
5248 bfa_q_qe_init(&phy->ioc_notify);
5249 bfa_ioc_notify_init(&phy->ioc_notify, bfa_phy_notify, phy);
5250 list_add_tail(&phy->ioc_notify.qe, &phy->ioc->notify_q);
5251
5252 /* min driver doesn't need phy */
5253 if (mincfg) {
5254 phy->dbuf_kva = NULL;
5255 phy->dbuf_pa = 0;
5256 }
5257}
5258
5259/*
5260 * Claim memory for phy
5261 *
5262 * @param[in] phy - phy structure
5263 * @param[in] dm_kva - pointer to virtual memory address
5264 * @param[in] dm_pa - physical memory address
5265 * @param[in] mincfg - minimal cfg variable
5266 */
5267void
5268bfa_phy_memclaim(struct bfa_phy_s *phy, u8 *dm_kva, u64 dm_pa,
5269 bfa_boolean_t mincfg)
5270{
5271 if (mincfg)
5272 return;
5273
5274 phy->dbuf_kva = dm_kva;
5275 phy->dbuf_pa = dm_pa;
5276 memset(phy->dbuf_kva, 0, BFA_PHY_DMA_BUF_SZ);
5277 dm_kva += BFA_ROUNDUP(BFA_PHY_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
5278 dm_pa += BFA_ROUNDUP(BFA_PHY_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
5279}
5280
5281bfa_boolean_t
5282bfa_phy_busy(struct bfa_ioc_s *ioc)
5283{
5284 void __iomem *rb;
5285
5286 rb = bfa_ioc_bar0(ioc);
5287 return readl(rb + BFA_PHY_LOCK_STATUS);
5288}
5289
5290/*
5291 * Get phy attribute.
5292 *
5293 * @param[in] phy - phy structure
5294 * @param[in] attr - phy attribute structure
5295 * @param[in] cbfn - callback function
5296 * @param[in] cbarg - callback argument
5297 *
5298 * Return status.
5299 */
5300bfa_status_t
5301bfa_phy_get_attr(struct bfa_phy_s *phy, u8 instance,
5302 struct bfa_phy_attr_s *attr, bfa_cb_phy_t cbfn, void *cbarg)
5303{
5304 bfa_trc(phy, BFI_PHY_H2I_QUERY_REQ);
5305 bfa_trc(phy, instance);
5306
5307 if (!bfa_phy_present(phy))
5308 return BFA_STATUS_PHY_NOT_PRESENT;
5309
5310 if (!bfa_ioc_is_operational(phy->ioc))
5311 return BFA_STATUS_IOC_NON_OP;
5312
5313 if (phy->op_busy || bfa_phy_busy(phy->ioc)) {
5314 bfa_trc(phy, phy->op_busy);
5315 return BFA_STATUS_DEVBUSY;
5316 }
5317
5318 phy->op_busy = 1;
5319 phy->cbfn = cbfn;
5320 phy->cbarg = cbarg;
5321 phy->instance = instance;
5322 phy->ubuf = (uint8_t *) attr;
5323 bfa_phy_query_send(phy);
5324
5325 return BFA_STATUS_OK;
5326}
5327
5328/*
5329 * Get phy stats.
5330 *
5331 * @param[in] phy - phy structure
5332 * @param[in] instance - phy image instance
5333 * @param[in] stats - pointer to phy stats
5334 * @param[in] cbfn - callback function
5335 * @param[in] cbarg - callback argument
5336 *
5337 * Return status.
5338 */
5339bfa_status_t
5340bfa_phy_get_stats(struct bfa_phy_s *phy, u8 instance,
5341 struct bfa_phy_stats_s *stats,
5342 bfa_cb_phy_t cbfn, void *cbarg)
5343{
5344 bfa_trc(phy, BFI_PHY_H2I_STATS_REQ);
5345 bfa_trc(phy, instance);
5346
5347 if (!bfa_phy_present(phy))
5348 return BFA_STATUS_PHY_NOT_PRESENT;
5349
5350 if (!bfa_ioc_is_operational(phy->ioc))
5351 return BFA_STATUS_IOC_NON_OP;
5352
5353 if (phy->op_busy || bfa_phy_busy(phy->ioc)) {
5354 bfa_trc(phy, phy->op_busy);
5355 return BFA_STATUS_DEVBUSY;
5356 }
5357
5358 phy->op_busy = 1;
5359 phy->cbfn = cbfn;
5360 phy->cbarg = cbarg;
5361 phy->instance = instance;
5362 phy->ubuf = (u8 *) stats;
5363 bfa_phy_stats_send(phy);
5364
5365 return BFA_STATUS_OK;
5366}
5367
5368/*
5369 * Update phy image.
5370 *
5371 * @param[in] phy - phy structure
5372 * @param[in] instance - phy image instance
5373 * @param[in] buf - update data buffer
5374 * @param[in] len - data buffer length
5375 * @param[in] offset - offset relative to starting address
5376 * @param[in] cbfn - callback function
5377 * @param[in] cbarg - callback argument
5378 *
5379 * Return status.
5380 */
5381bfa_status_t
5382bfa_phy_update(struct bfa_phy_s *phy, u8 instance,
5383 void *buf, u32 len, u32 offset,
5384 bfa_cb_phy_t cbfn, void *cbarg)
5385{
5386 bfa_trc(phy, BFI_PHY_H2I_WRITE_REQ);
5387 bfa_trc(phy, instance);
5388 bfa_trc(phy, len);
5389 bfa_trc(phy, offset);
5390
5391 if (!bfa_phy_present(phy))
5392 return BFA_STATUS_PHY_NOT_PRESENT;
5393
5394 if (!bfa_ioc_is_operational(phy->ioc))
5395 return BFA_STATUS_IOC_NON_OP;
5396
5397 /* 'len' must be in word (4-byte) boundary */
5398 if (!len || (len & 0x03))
5399 return BFA_STATUS_FAILED;
5400
5401 if (phy->op_busy || bfa_phy_busy(phy->ioc)) {
5402 bfa_trc(phy, phy->op_busy);
5403 return BFA_STATUS_DEVBUSY;
5404 }
5405
5406 phy->op_busy = 1;
5407 phy->cbfn = cbfn;
5408 phy->cbarg = cbarg;
5409 phy->instance = instance;
5410 phy->residue = len;
5411 phy->offset = 0;
5412 phy->addr_off = offset;
5413 phy->ubuf = buf;
5414
5415 bfa_phy_write_send(phy);
5416 return BFA_STATUS_OK;
5417}
5418
5419/*
5420 * Read phy image.
5421 *
5422 * @param[in] phy - phy structure
5423 * @param[in] instance - phy image instance
5424 * @param[in] buf - read data buffer
5425 * @param[in] len - data buffer length
5426 * @param[in] offset - offset relative to starting address
5427 * @param[in] cbfn - callback function
5428 * @param[in] cbarg - callback argument
5429 *
5430 * Return status.
5431 */
5432bfa_status_t
5433bfa_phy_read(struct bfa_phy_s *phy, u8 instance,
5434 void *buf, u32 len, u32 offset,
5435 bfa_cb_phy_t cbfn, void *cbarg)
5436{
5437 bfa_trc(phy, BFI_PHY_H2I_READ_REQ);
5438 bfa_trc(phy, instance);
5439 bfa_trc(phy, len);
5440 bfa_trc(phy, offset);
5441
5442 if (!bfa_phy_present(phy))
5443 return BFA_STATUS_PHY_NOT_PRESENT;
5444
5445 if (!bfa_ioc_is_operational(phy->ioc))
5446 return BFA_STATUS_IOC_NON_OP;
5447
5448 /* 'len' must be in word (4-byte) boundary */
5449 if (!len || (len & 0x03))
5450 return BFA_STATUS_FAILED;
5451
5452 if (phy->op_busy || bfa_phy_busy(phy->ioc)) {
5453 bfa_trc(phy, phy->op_busy);
5454 return BFA_STATUS_DEVBUSY;
5455 }
5456
5457 phy->op_busy = 1;
5458 phy->cbfn = cbfn;
5459 phy->cbarg = cbarg;
5460 phy->instance = instance;
5461 phy->residue = len;
5462 phy->offset = 0;
5463 phy->addr_off = offset;
5464 phy->ubuf = buf;
5465 bfa_phy_read_send(phy);
5466
5467 return BFA_STATUS_OK;
5468}
5469
5470/*
5471 * Process phy response messages upon receiving interrupts.
5472 *
5473 * @param[in] phyarg - phy structure
5474 * @param[in] msg - message structure
5475 */
5476void
5477bfa_phy_intr(void *phyarg, struct bfi_mbmsg_s *msg)
5478{
5479 struct bfa_phy_s *phy = phyarg;
5480 u32 status;
5481
5482 union {
5483 struct bfi_phy_query_rsp_s *query;
5484 struct bfi_phy_stats_rsp_s *stats;
5485 struct bfi_phy_write_rsp_s *write;
5486 struct bfi_phy_read_rsp_s *read;
5487 struct bfi_mbmsg_s *msg;
5488 } m;
5489
5490 m.msg = msg;
5491 bfa_trc(phy, msg->mh.msg_id);
5492
5493 if (!phy->op_busy) {
5494 /* receiving response after ioc failure */
5495 bfa_trc(phy, 0x9999);
5496 return;
5497 }
5498
5499 switch (msg->mh.msg_id) {
5500 case BFI_PHY_I2H_QUERY_RSP:
5501 status = be32_to_cpu(m.query->status);
5502 bfa_trc(phy, status);
5503
5504 if (status == BFA_STATUS_OK) {
5505 struct bfa_phy_attr_s *attr =
5506 (struct bfa_phy_attr_s *) phy->ubuf;
5507 bfa_phy_ntoh32((u32 *)attr, (u32 *)phy->dbuf_kva,
5508 sizeof(struct bfa_phy_attr_s));
5509 bfa_trc(phy, attr->status);
5510 bfa_trc(phy, attr->length);
5511 }
5512
5513 phy->status = status;
5514 phy->op_busy = 0;
5515 if (phy->cbfn)
5516 phy->cbfn(phy->cbarg, phy->status);
5517 break;
5518 case BFI_PHY_I2H_STATS_RSP:
5519 status = be32_to_cpu(m.stats->status);
5520 bfa_trc(phy, status);
5521
5522 if (status == BFA_STATUS_OK) {
5523 struct bfa_phy_stats_s *stats =
5524 (struct bfa_phy_stats_s *) phy->ubuf;
5525 bfa_phy_ntoh32((u32 *)stats, (u32 *)phy->dbuf_kva,
5526 sizeof(struct bfa_phy_stats_s));
5527 bfa_trc(phy, stats->status);
5528 }
5529
5530 phy->status = status;
5531 phy->op_busy = 0;
5532 if (phy->cbfn)
5533 phy->cbfn(phy->cbarg, phy->status);
5534 break;
5535 case BFI_PHY_I2H_WRITE_RSP:
5536 status = be32_to_cpu(m.write->status);
5537 bfa_trc(phy, status);
5538
5539 if (status != BFA_STATUS_OK || phy->residue == 0) {
5540 phy->status = status;
5541 phy->op_busy = 0;
5542 if (phy->cbfn)
5543 phy->cbfn(phy->cbarg, phy->status);
5544 } else {
5545 bfa_trc(phy, phy->offset);
5546 bfa_phy_write_send(phy);
5547 }
5548 break;
5549 case BFI_PHY_I2H_READ_RSP:
5550 status = be32_to_cpu(m.read->status);
5551 bfa_trc(phy, status);
5552
5553 if (status != BFA_STATUS_OK) {
5554 phy->status = status;
5555 phy->op_busy = 0;
5556 if (phy->cbfn)
5557 phy->cbfn(phy->cbarg, phy->status);
5558 } else {
5559 u32 len = be32_to_cpu(m.read->length);
5560 u16 *buf = (u16 *)(phy->ubuf + phy->offset);
5561 u16 *dbuf = (u16 *)phy->dbuf_kva;
5562 int i, sz = len >> 1;
5563
5564 bfa_trc(phy, phy->offset);
5565 bfa_trc(phy, len);
5566
5567 for (i = 0; i < sz; i++)
5568 buf[i] = be16_to_cpu(dbuf[i]);
5569
5570 phy->residue -= len;
5571 phy->offset += len;
5572
5573 if (phy->residue == 0) {
5574 phy->status = status;
5575 phy->op_busy = 0;
5576 if (phy->cbfn)
5577 phy->cbfn(phy->cbarg, phy->status);
5578 } else
5579 bfa_phy_read_send(phy);
5580 }
5581 break;
5582 default:
5583 WARN_ON(1);
5584 }
5585}
45c5dc1d
KG		 5586
5587/*
5588 * DCONF module specific
5589 */
5590
5591BFA_MODULE(dconf);
5592
5593/*
5594 * DCONF state machine events
5595 */
5596enum bfa_dconf_event {
5597 BFA_DCONF_SM_INIT = 1, /* dconf Init */
5598 BFA_DCONF_SM_FLASH_COMP = 2, /* read/write to flash */
5599 BFA_DCONF_SM_WR = 3, /* binding change, map */
5600 BFA_DCONF_SM_TIMEOUT = 4, /* Start timer */
5601 BFA_DCONF_SM_EXIT = 5, /* exit dconf module */
5602 BFA_DCONF_SM_IOCDISABLE = 6, /* IOC disable event */
5603};
5604
5605/* forward declaration of DCONF state machine */
5606static void bfa_dconf_sm_uninit(struct bfa_dconf_mod_s *dconf,
5607 enum bfa_dconf_event event);
5608static void bfa_dconf_sm_flash_read(struct bfa_dconf_mod_s *dconf,
5609 enum bfa_dconf_event event);
5610static void bfa_dconf_sm_ready(struct bfa_dconf_mod_s *dconf,
5611 enum bfa_dconf_event event);
5612static void bfa_dconf_sm_dirty(struct bfa_dconf_mod_s *dconf,
5613 enum bfa_dconf_event event);
5614static void bfa_dconf_sm_sync(struct bfa_dconf_mod_s *dconf,
5615 enum bfa_dconf_event event);
5616static void bfa_dconf_sm_final_sync(struct bfa_dconf_mod_s *dconf,
5617 enum bfa_dconf_event event);
5618static void bfa_dconf_sm_iocdown_dirty(struct bfa_dconf_mod_s *dconf,
5619 enum bfa_dconf_event event);
5620
5621static void bfa_dconf_cbfn(void *dconf, bfa_status_t status);
5622static void bfa_dconf_timer(void *cbarg);
5623static bfa_status_t bfa_dconf_flash_write(struct bfa_dconf_mod_s *dconf);
5624static void bfa_dconf_init_cb(void *arg, bfa_status_t status);
5625
5626/*
4907cb7b 5627 * Beginning state of dconf module. Waiting for an event to start.
45c5dc1d
KG		 5628 */
5629static void
5630bfa_dconf_sm_uninit(struct bfa_dconf_mod_s *dconf, enum bfa_dconf_event event)
5631{
5632 bfa_status_t bfa_status;
5633 bfa_trc(dconf->bfa, event);
5634
5635 switch (event) {
5636 case BFA_DCONF_SM_INIT:
5637 if (dconf->min_cfg) {
5638 bfa_trc(dconf->bfa, dconf->min_cfg);
db9d8a75
KG		 5639 bfa_fsm_send_event(&dconf->bfa->iocfc,
5640 IOCFC_E_DCONF_DONE);
45c5dc1d
KG		 5641 return;
5642 }
5643 bfa_sm_set_state(dconf, bfa_dconf_sm_flash_read);
db9d8a75 5644 bfa_timer_start(dconf->bfa, &dconf->timer,
7ac83b1f 5645 bfa_dconf_timer, dconf, 2 * BFA_DCONF_UPDATE_TOV);
45c5dc1d
KG		 5646 bfa_status = bfa_flash_read_part(BFA_FLASH(dconf->bfa),
5647 BFA_FLASH_PART_DRV, dconf->instance,
5648 dconf->dconf,
5649 sizeof(struct bfa_dconf_s), 0,
5650 bfa_dconf_init_cb, dconf->bfa);
5651 if (bfa_status != BFA_STATUS_OK) {
db9d8a75 5652 bfa_timer_stop(&dconf->timer);
45c5dc1d
KG		 5653 bfa_dconf_init_cb(dconf->bfa, BFA_STATUS_FAILED);
5654 bfa_sm_set_state(dconf, bfa_dconf_sm_uninit);
5655 return;
5656 }
5657 break;
5658 case BFA_DCONF_SM_EXIT:
db9d8a75 5659 bfa_fsm_send_event(&dconf->bfa->iocfc, IOCFC_E_DCONF_DONE);
45c5dc1d
KG		 5660 case BFA_DCONF_SM_IOCDISABLE:
5661 case BFA_DCONF_SM_WR:
5662 case BFA_DCONF_SM_FLASH_COMP:
5663 break;
5664 default:
5665 bfa_sm_fault(dconf->bfa, event);
5666 }
5667}
5668
5669/*
5670 * Read flash for dconf entries and make a call back to the driver once done.
5671 */
5672static void
5673bfa_dconf_sm_flash_read(struct bfa_dconf_mod_s *dconf,
5674 enum bfa_dconf_event event)
5675{
5676 bfa_trc(dconf->bfa, event);
5677
5678 switch (event) {
5679 case BFA_DCONF_SM_FLASH_COMP:
db9d8a75 5680 bfa_timer_stop(&dconf->timer);
45c5dc1d
KG		 5681 bfa_sm_set_state(dconf, bfa_dconf_sm_ready);
5682 break;
5683 case BFA_DCONF_SM_TIMEOUT:
5684 bfa_sm_set_state(dconf, bfa_dconf_sm_ready);
7ac83b1f 5685 bfa_ioc_suspend(&dconf->bfa->ioc);
45c5dc1d
KG		 5686 break;
5687 case BFA_DCONF_SM_EXIT:
db9d8a75
KG		 5688 bfa_timer_stop(&dconf->timer);
5689 bfa_sm_set_state(dconf, bfa_dconf_sm_uninit);
5690 bfa_fsm_send_event(&dconf->bfa->iocfc, IOCFC_E_DCONF_DONE);
5691 break;
45c5dc1d 5692 case BFA_DCONF_SM_IOCDISABLE:
db9d8a75 5693 bfa_timer_stop(&dconf->timer);
45c5dc1d
KG		 5694 bfa_sm_set_state(dconf, bfa_dconf_sm_uninit);
5695 break;
5696 default:
5697 bfa_sm_fault(dconf->bfa, event);
5698 }
5699}
5700
5701/*
5702 * DCONF Module is in ready state. Has completed the initialization.
5703 */
5704static void
5705bfa_dconf_sm_ready(struct bfa_dconf_mod_s *dconf, enum bfa_dconf_event event)
5706{
5707 bfa_trc(dconf->bfa, event);
5708
5709 switch (event) {
5710 case BFA_DCONF_SM_WR:
5711 bfa_timer_start(dconf->bfa, &dconf->timer,
5712 bfa_dconf_timer, dconf, BFA_DCONF_UPDATE_TOV);
5713 bfa_sm_set_state(dconf, bfa_dconf_sm_dirty);
5714 break;
5715 case BFA_DCONF_SM_EXIT:
45c5dc1d 5716 bfa_sm_set_state(dconf, bfa_dconf_sm_uninit);
db9d8a75 5717 bfa_fsm_send_event(&dconf->bfa->iocfc, IOCFC_E_DCONF_DONE);
45c5dc1d
KG		 5718 break;
5719 case BFA_DCONF_SM_INIT:
5720 case BFA_DCONF_SM_IOCDISABLE:
5721 break;
5722 default:
5723 bfa_sm_fault(dconf->bfa, event);
5724 }
5725}
5726
5727/*
5728 * entries are dirty, write back to the flash.
5729 */
5730
5731static void
5732bfa_dconf_sm_dirty(struct bfa_dconf_mod_s *dconf, enum bfa_dconf_event event)
5733{
5734 bfa_trc(dconf->bfa, event);
5735
5736 switch (event) {
5737 case BFA_DCONF_SM_TIMEOUT:
5738 bfa_sm_set_state(dconf, bfa_dconf_sm_sync);
5739 bfa_dconf_flash_write(dconf);
5740 break;
5741 case BFA_DCONF_SM_WR:
5742 bfa_timer_stop(&dconf->timer);
5743 bfa_timer_start(dconf->bfa, &dconf->timer,
5744 bfa_dconf_timer, dconf, BFA_DCONF_UPDATE_TOV);
5745 break;
5746 case BFA_DCONF_SM_EXIT:
5747 bfa_timer_stop(&dconf->timer);
5748 bfa_timer_start(dconf->bfa, &dconf->timer,
5749 bfa_dconf_timer, dconf, BFA_DCONF_UPDATE_TOV);
5750 bfa_sm_set_state(dconf, bfa_dconf_sm_final_sync);
5751 bfa_dconf_flash_write(dconf);
5752 break;
5753 case BFA_DCONF_SM_FLASH_COMP:
5754 break;
5755 case BFA_DCONF_SM_IOCDISABLE:
5756 bfa_timer_stop(&dconf->timer);
5757 bfa_sm_set_state(dconf, bfa_dconf_sm_iocdown_dirty);
5758 break;
5759 default:
5760 bfa_sm_fault(dconf->bfa, event);
5761 }
5762}
5763
5764/*
5765 * Sync the dconf entries to the flash.
5766 */
5767static void
5768bfa_dconf_sm_final_sync(struct bfa_dconf_mod_s *dconf,
5769 enum bfa_dconf_event event)
5770{
5771 bfa_trc(dconf->bfa, event);
5772
5773 switch (event) {
5774 case BFA_DCONF_SM_IOCDISABLE:
5775 case BFA_DCONF_SM_FLASH_COMP:
5776 bfa_timer_stop(&dconf->timer);
5777 case BFA_DCONF_SM_TIMEOUT:
5778 bfa_sm_set_state(dconf, bfa_dconf_sm_uninit);
db9d8a75 5779 bfa_fsm_send_event(&dconf->bfa->iocfc, IOCFC_E_DCONF_DONE);
45c5dc1d
KG		 5780 break;
5781 default:
5782 bfa_sm_fault(dconf->bfa, event);
5783 }
5784}
5785
5786static void
5787bfa_dconf_sm_sync(struct bfa_dconf_mod_s *dconf, enum bfa_dconf_event event)
5788{
5789 bfa_trc(dconf->bfa, event);
5790
5791 switch (event) {
5792 case BFA_DCONF_SM_FLASH_COMP:
5793 bfa_sm_set_state(dconf, bfa_dconf_sm_ready);
5794 break;
5795 case BFA_DCONF_SM_WR:
5796 bfa_timer_start(dconf->bfa, &dconf->timer,
5797 bfa_dconf_timer, dconf, BFA_DCONF_UPDATE_TOV);
5798 bfa_sm_set_state(dconf, bfa_dconf_sm_dirty);
5799 break;
5800 case BFA_DCONF_SM_EXIT:
5801 bfa_timer_start(dconf->bfa, &dconf->timer,
5802 bfa_dconf_timer, dconf, BFA_DCONF_UPDATE_TOV);
5803 bfa_sm_set_state(dconf, bfa_dconf_sm_final_sync);
5804 break;
5805 case BFA_DCONF_SM_IOCDISABLE:
5806 bfa_sm_set_state(dconf, bfa_dconf_sm_iocdown_dirty);
5807 break;
5808 default:
5809 bfa_sm_fault(dconf->bfa, event);
5810 }
5811}
5812
5813static void
5814bfa_dconf_sm_iocdown_dirty(struct bfa_dconf_mod_s *dconf,
5815 enum bfa_dconf_event event)
5816{
5817 bfa_trc(dconf->bfa, event);
5818
5819 switch (event) {
5820 case BFA_DCONF_SM_INIT:
5821 bfa_timer_start(dconf->bfa, &dconf->timer,
5822 bfa_dconf_timer, dconf, BFA_DCONF_UPDATE_TOV);
5823 bfa_sm_set_state(dconf, bfa_dconf_sm_dirty);
5824 break;
5825 case BFA_DCONF_SM_EXIT:
45c5dc1d 5826 bfa_sm_set_state(dconf, bfa_dconf_sm_uninit);
db9d8a75 5827 bfa_fsm_send_event(&dconf->bfa->iocfc, IOCFC_E_DCONF_DONE);
45c5dc1d
KG		 5828 break;
5829 case BFA_DCONF_SM_IOCDISABLE:
5830 break;
5831 default:
5832 bfa_sm_fault(dconf->bfa, event);
5833 }
5834}
5835
5836/*
5837 * Compute and return memory needed by DRV_CFG module.
5838 */
5839static void
5840bfa_dconf_meminfo(struct bfa_iocfc_cfg_s *cfg, struct bfa_meminfo_s *meminfo,
5841 struct bfa_s *bfa)
5842{
5843 struct bfa_mem_kva_s *dconf_kva = BFA_MEM_DCONF_KVA(bfa);
5844
5845 if (cfg->drvcfg.min_cfg)
5846 bfa_mem_kva_setup(meminfo, dconf_kva,
5847 sizeof(struct bfa_dconf_hdr_s));
5848 else
5849 bfa_mem_kva_setup(meminfo, dconf_kva,
5850 sizeof(struct bfa_dconf_s));
5851}
5852
5853static void
5854bfa_dconf_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg,
5855 struct bfa_pcidev_s *pcidev)
5856{
5857 struct bfa_dconf_mod_s *dconf = BFA_DCONF_MOD(bfa);
5858
5859 dconf->bfad = bfad;
5860 dconf->bfa = bfa;
5861 dconf->instance = bfa->ioc.port_id;
5862 bfa_trc(bfa, dconf->instance);
5863
5864 dconf->dconf = (struct bfa_dconf_s *) bfa_mem_kva_curp(dconf);
5865 if (cfg->drvcfg.min_cfg) {
5866 bfa_mem_kva_curp(dconf) += sizeof(struct bfa_dconf_hdr_s);
5867 dconf->min_cfg = BFA_TRUE;
45c5dc1d
KG		 5868 } else {
5869 dconf->min_cfg = BFA_FALSE;
5870 bfa_mem_kva_curp(dconf) += sizeof(struct bfa_dconf_s);
5871 }
5872
5873 bfa_dconf_read_data_valid(bfa) = BFA_FALSE;
5874 bfa_sm_set_state(dconf, bfa_dconf_sm_uninit);
5875}
5876
5877static void
5878bfa_dconf_init_cb(void *arg, bfa_status_t status)
5879{
5880 struct bfa_s *bfa = arg;
5881 struct bfa_dconf_mod_s *dconf = BFA_DCONF_MOD(bfa);
5882
45c5dc1d
KG		 5883 if (status == BFA_STATUS_OK) {
5884 bfa_dconf_read_data_valid(bfa) = BFA_TRUE;
5885 if (dconf->dconf->hdr.signature != BFI_DCONF_SIGNATURE)
5886 dconf->dconf->hdr.signature = BFI_DCONF_SIGNATURE;
5887 if (dconf->dconf->hdr.version != BFI_DCONF_VERSION)
5888 dconf->dconf->hdr.version = BFI_DCONF_VERSION;
5889 }
7ac83b1f 5890 bfa_sm_send_event(dconf, BFA_DCONF_SM_FLASH_COMP);
db9d8a75 5891 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_DCONF_DONE);
45c5dc1d
KG		 5892}
5893
5894void
5895bfa_dconf_modinit(struct bfa_s *bfa)
5896{
5897 struct bfa_dconf_mod_s *dconf = BFA_DCONF_MOD(bfa);
5898 bfa_sm_send_event(dconf, BFA_DCONF_SM_INIT);
5899}
5900static void
5901bfa_dconf_start(struct bfa_s *bfa)
5902{
5903}
5904
5905static void
5906bfa_dconf_stop(struct bfa_s *bfa)
5907{
5908}
5909
5910static void bfa_dconf_timer(void *cbarg)
5911{
5912 struct bfa_dconf_mod_s *dconf = cbarg;
5913 bfa_sm_send_event(dconf, BFA_DCONF_SM_TIMEOUT);
5914}
5915static void
5916bfa_dconf_iocdisable(struct bfa_s *bfa)
5917{
5918 struct bfa_dconf_mod_s *dconf = BFA_DCONF_MOD(bfa);
5919 bfa_sm_send_event(dconf, BFA_DCONF_SM_IOCDISABLE);
5920}
5921
5922static void
5923bfa_dconf_detach(struct bfa_s *bfa)
5924{
5925}
5926
5927static bfa_status_t
5928bfa_dconf_flash_write(struct bfa_dconf_mod_s *dconf)
5929{
5930 bfa_status_t bfa_status;
5931 bfa_trc(dconf->bfa, 0);
5932
5933 bfa_status = bfa_flash_update_part(BFA_FLASH(dconf->bfa),
5934 BFA_FLASH_PART_DRV, dconf->instance,
5935 dconf->dconf, sizeof(struct bfa_dconf_s), 0,
5936 bfa_dconf_cbfn, dconf);
5937 if (bfa_status != BFA_STATUS_OK)
5938 WARN_ON(bfa_status);
5939 bfa_trc(dconf->bfa, bfa_status);
5940
5941 return bfa_status;
5942}
5943
5944bfa_status_t
5945bfa_dconf_update(struct bfa_s *bfa)
5946{
5947 struct bfa_dconf_mod_s *dconf = BFA_DCONF_MOD(bfa);
5948 bfa_trc(dconf->bfa, 0);
5949 if (bfa_sm_cmp_state(dconf, bfa_dconf_sm_iocdown_dirty))
5950 return BFA_STATUS_FAILED;
5951
5952 if (dconf->min_cfg) {
5953 bfa_trc(dconf->bfa, dconf->min_cfg);
5954 return BFA_STATUS_FAILED;
5955 }
5956
5957 bfa_sm_send_event(dconf, BFA_DCONF_SM_WR);
5958 return BFA_STATUS_OK;
5959}
5960
5961static void
5962bfa_dconf_cbfn(void *arg, bfa_status_t status)
5963{
5964 struct bfa_dconf_mod_s *dconf = arg;
5965 WARN_ON(status);
5966 bfa_sm_send_event(dconf, BFA_DCONF_SM_FLASH_COMP);
5967}
5968
5969void
5970bfa_dconf_modexit(struct bfa_s *bfa)
5971{
5972 struct bfa_dconf_mod_s *dconf = BFA_DCONF_MOD(bfa);
45c5dc1d
KG		 5973 bfa_sm_send_event(dconf, BFA_DCONF_SM_EXIT);
5974}
e6826c96
KG		 5975
5976/*
5977 * FRU specific functions
5978 */
5979
5980#define BFA_FRU_DMA_BUF_SZ 0x02000 /* 8k dma buffer */
5981#define BFA_FRU_CHINOOK_MAX_SIZE 0x10000
5982#define BFA_FRU_LIGHTNING_MAX_SIZE 0x200
5983
5984static void
5985bfa_fru_notify(void *cbarg, enum bfa_ioc_event_e event)
5986{
5987 struct bfa_fru_s *fru = cbarg;
5988
5989 bfa_trc(fru, event);
5990
5991 switch (event) {
5992 case BFA_IOC_E_DISABLED:
5993 case BFA_IOC_E_FAILED:
5994 if (fru->op_busy) {
5995 fru->status = BFA_STATUS_IOC_FAILURE;
5996 fru->cbfn(fru->cbarg, fru->status);
5997 fru->op_busy = 0;
5998 }
5999 break;
6000
6001 default:
6002 break;
6003 }
6004}
6005
6006/*
6007 * Send fru write request.
6008 *
6009 * @param[in] cbarg - callback argument
6010 */
6011static void
6012bfa_fru_write_send(void *cbarg, enum bfi_fru_h2i_msgs msg_type)
6013{
6014 struct bfa_fru_s *fru = cbarg;
6015 struct bfi_fru_write_req_s *msg =
6016 (struct bfi_fru_write_req_s *) fru->mb.msg;
6017 u32 len;
6018
6019 msg->offset = cpu_to_be32(fru->addr_off + fru->offset);
6020 len = (fru->residue < BFA_FRU_DMA_BUF_SZ) ?
6021 fru->residue : BFA_FRU_DMA_BUF_SZ;
6022 msg->length = cpu_to_be32(len);
6023
6024 /*
6025 * indicate if it's the last msg of the whole write operation
6026 */
6027 msg->last = (len == fru->residue) ? 1 : 0;
6028
079bcbc3 6029 msg->trfr_cmpl = (len == fru->residue) ? fru->trfr_cmpl : 0;
e6826c96
KG		 6030 bfi_h2i_set(msg->mh, BFI_MC_FRU, msg_type, bfa_ioc_portid(fru->ioc));
6031 bfa_alen_set(&msg->alen, len, fru->dbuf_pa);
6032
6033 memcpy(fru->dbuf_kva, fru->ubuf + fru->offset, len);
6034 bfa_ioc_mbox_queue(fru->ioc, &fru->mb);
6035
6036 fru->residue -= len;
6037 fru->offset += len;
6038}
6039
6040/*
6041 * Send fru read request.
6042 *
6043 * @param[in] cbarg - callback argument
6044 */
6045static void
6046bfa_fru_read_send(void *cbarg, enum bfi_fru_h2i_msgs msg_type)
6047{
6048 struct bfa_fru_s *fru = cbarg;
6049 struct bfi_fru_read_req_s *msg =
6050 (struct bfi_fru_read_req_s *) fru->mb.msg;
6051 u32 len;
6052
6053 msg->offset = cpu_to_be32(fru->addr_off + fru->offset);
6054 len = (fru->residue < BFA_FRU_DMA_BUF_SZ) ?
6055 fru->residue : BFA_FRU_DMA_BUF_SZ;
6056 msg->length = cpu_to_be32(len);
6057 bfi_h2i_set(msg->mh, BFI_MC_FRU, msg_type, bfa_ioc_portid(fru->ioc));
6058 bfa_alen_set(&msg->alen, len, fru->dbuf_pa);
6059 bfa_ioc_mbox_queue(fru->ioc, &fru->mb);
6060}
6061
6062/*
6063 * Flash memory info API.
6064 *
6065 * @param[in] mincfg - minimal cfg variable
6066 */
6067u32
6068bfa_fru_meminfo(bfa_boolean_t mincfg)
6069{
6070 /* min driver doesn't need fru */
6071 if (mincfg)
6072 return 0;
6073
6074 return BFA_ROUNDUP(BFA_FRU_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
6075}
6076
6077/*
6078 * Flash attach API.
6079 *
6080 * @param[in] fru - fru structure
6081 * @param[in] ioc - ioc structure
6082 * @param[in] dev - device structure
6083 * @param[in] trcmod - trace module
6084 * @param[in] logmod - log module
6085 */
6086void
6087bfa_fru_attach(struct bfa_fru_s *fru, struct bfa_ioc_s *ioc, void *dev,
6088 struct bfa_trc_mod_s *trcmod, bfa_boolean_t mincfg)
6089{
6090 fru->ioc = ioc;
6091 fru->trcmod = trcmod;
6092 fru->cbfn = NULL;
6093 fru->cbarg = NULL;
6094 fru->op_busy = 0;
6095
6096 bfa_ioc_mbox_regisr(fru->ioc, BFI_MC_FRU, bfa_fru_intr, fru);
6097 bfa_q_qe_init(&fru->ioc_notify);
6098 bfa_ioc_notify_init(&fru->ioc_notify, bfa_fru_notify, fru);
6099 list_add_tail(&fru->ioc_notify.qe, &fru->ioc->notify_q);
6100
6101 /* min driver doesn't need fru */
6102 if (mincfg) {
6103 fru->dbuf_kva = NULL;
6104 fru->dbuf_pa = 0;
6105 }
6106}
6107
6108/*
6109 * Claim memory for fru
6110 *
6111 * @param[in] fru - fru structure
6112 * @param[in] dm_kva - pointer to virtual memory address
6113 * @param[in] dm_pa - frusical memory address
6114 * @param[in] mincfg - minimal cfg variable
6115 */
6116void
6117bfa_fru_memclaim(struct bfa_fru_s *fru, u8 *dm_kva, u64 dm_pa,
6118 bfa_boolean_t mincfg)
6119{
6120 if (mincfg)
6121 return;
6122
6123 fru->dbuf_kva = dm_kva;
6124 fru->dbuf_pa = dm_pa;
6125 memset(fru->dbuf_kva, 0, BFA_FRU_DMA_BUF_SZ);
6126 dm_kva += BFA_ROUNDUP(BFA_FRU_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
6127 dm_pa += BFA_ROUNDUP(BFA_FRU_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
6128}
6129
6130/*
6131 * Update fru vpd image.
6132 *
6133 * @param[in] fru - fru structure
6134 * @param[in] buf - update data buffer
6135 * @param[in] len - data buffer length
6136 * @param[in] offset - offset relative to starting address
6137 * @param[in] cbfn - callback function
6138 * @param[in] cbarg - callback argument
6139 *
6140 * Return status.
6141 */
6142bfa_status_t
6143bfa_fruvpd_update(struct bfa_fru_s *fru, void *buf, u32 len, u32 offset,
079bcbc3 6144 bfa_cb_fru_t cbfn, void *cbarg, u8 trfr_cmpl)
e6826c96
KG		 6145{
6146 bfa_trc(fru, BFI_FRUVPD_H2I_WRITE_REQ);
6147 bfa_trc(fru, len);
6148 bfa_trc(fru, offset);
6149
079bcbc3
VMG		 6150 if (fru->ioc->asic_gen != BFI_ASIC_GEN_CT2 &&
6151 fru->ioc->attr->card_type != BFA_MFG_TYPE_CHINOOK2)
e6826c96
KG		 6152 return BFA_STATUS_FRU_NOT_PRESENT;
6153
6154 if (fru->ioc->attr->card_type != BFA_MFG_TYPE_CHINOOK)
6155 return BFA_STATUS_CMD_NOTSUPP;
6156
6157 if (!bfa_ioc_is_operational(fru->ioc))
6158 return BFA_STATUS_IOC_NON_OP;
6159
6160 if (fru->op_busy) {
6161 bfa_trc(fru, fru->op_busy);
6162 return BFA_STATUS_DEVBUSY;
6163 }
6164
6165 fru->op_busy = 1;
6166
6167 fru->cbfn = cbfn;
6168 fru->cbarg = cbarg;
6169 fru->residue = len;
6170 fru->offset = 0;
6171 fru->addr_off = offset;
6172 fru->ubuf = buf;
079bcbc3 6173 fru->trfr_cmpl = trfr_cmpl;
e6826c96
KG		 6174
6175 bfa_fru_write_send(fru, BFI_FRUVPD_H2I_WRITE_REQ);
6176
6177 return BFA_STATUS_OK;
6178}
6179
6180/*
6181 * Read fru vpd image.
6182 *
6183 * @param[in] fru - fru structure
6184 * @param[in] buf - read data buffer
6185 * @param[in] len - data buffer length
6186 * @param[in] offset - offset relative to starting address
6187 * @param[in] cbfn - callback function
6188 * @param[in] cbarg - callback argument
6189 *
6190 * Return status.
6191 */
6192bfa_status_t
6193bfa_fruvpd_read(struct bfa_fru_s *fru, void *buf, u32 len, u32 offset,
6194 bfa_cb_fru_t cbfn, void *cbarg)
6195{
6196 bfa_trc(fru, BFI_FRUVPD_H2I_READ_REQ);
6197 bfa_trc(fru, len);
6198 bfa_trc(fru, offset);
6199
6200 if (fru->ioc->asic_gen != BFI_ASIC_GEN_CT2)
6201 return BFA_STATUS_FRU_NOT_PRESENT;
6202
079bcbc3
VMG		 6203 if (fru->ioc->attr->card_type != BFA_MFG_TYPE_CHINOOK &&
6204 fru->ioc->attr->card_type != BFA_MFG_TYPE_CHINOOK2)
e6826c96
KG		 6205 return BFA_STATUS_CMD_NOTSUPP;
6206
6207 if (!bfa_ioc_is_operational(fru->ioc))
6208 return BFA_STATUS_IOC_NON_OP;
6209
6210 if (fru->op_busy) {
6211 bfa_trc(fru, fru->op_busy);
6212 return BFA_STATUS_DEVBUSY;
6213 }
6214
6215 fru->op_busy = 1;
6216
6217 fru->cbfn = cbfn;
6218 fru->cbarg = cbarg;
6219 fru->residue = len;
6220 fru->offset = 0;
6221 fru->addr_off = offset;
6222 fru->ubuf = buf;
6223 bfa_fru_read_send(fru, BFI_FRUVPD_H2I_READ_REQ);
6224
6225 return BFA_STATUS_OK;
6226}
6227
6228/*
6229 * Get maximum size fru vpd image.
6230 *
6231 * @param[in] fru - fru structure
6232 * @param[out] size - maximum size of fru vpd data
6233 *
6234 * Return status.
6235 */
6236bfa_status_t
6237bfa_fruvpd_get_max_size(struct bfa_fru_s *fru, u32 *max_size)
6238{
6239 if (fru->ioc->asic_gen != BFI_ASIC_GEN_CT2)
6240 return BFA_STATUS_FRU_NOT_PRESENT;
6241
6242 if (!bfa_ioc_is_operational(fru->ioc))
6243 return BFA_STATUS_IOC_NON_OP;
6244
079bcbc3
VMG		 6245 if (fru->ioc->attr->card_type == BFA_MFG_TYPE_CHINOOK ||
6246 fru->ioc->attr->card_type == BFA_MFG_TYPE_CHINOOK2)
e6826c96
KG		 6247 *max_size = BFA_FRU_CHINOOK_MAX_SIZE;
6248 else
6249 return BFA_STATUS_CMD_NOTSUPP;
6250 return BFA_STATUS_OK;
6251}
6252/*
6253 * tfru write.
6254 *
6255 * @param[in] fru - fru structure
6256 * @param[in] buf - update data buffer
6257 * @param[in] len - data buffer length
6258 * @param[in] offset - offset relative to starting address
6259 * @param[in] cbfn - callback function
6260 * @param[in] cbarg - callback argument
6261 *
6262 * Return status.
6263 */
6264bfa_status_t
6265bfa_tfru_write(struct bfa_fru_s *fru, void *buf, u32 len, u32 offset,
6266 bfa_cb_fru_t cbfn, void *cbarg)
6267{
6268 bfa_trc(fru, BFI_TFRU_H2I_WRITE_REQ);
6269 bfa_trc(fru, len);
6270 bfa_trc(fru, offset);
6271 bfa_trc(fru, *((u8 *) buf));
6272
6273 if (fru->ioc->asic_gen != BFI_ASIC_GEN_CT2)
6274 return BFA_STATUS_FRU_NOT_PRESENT;
6275
6276 if (!bfa_ioc_is_operational(fru->ioc))
6277 return BFA_STATUS_IOC_NON_OP;
6278
6279 if (fru->op_busy) {
6280 bfa_trc(fru, fru->op_busy);
6281 return BFA_STATUS_DEVBUSY;
6282 }
6283
6284 fru->op_busy = 1;
6285
6286 fru->cbfn = cbfn;
6287 fru->cbarg = cbarg;
6288 fru->residue = len;
6289 fru->offset = 0;
6290 fru->addr_off = offset;
6291 fru->ubuf = buf;
6292
6293 bfa_fru_write_send(fru, BFI_TFRU_H2I_WRITE_REQ);
6294
6295 return BFA_STATUS_OK;
6296}
6297
6298/*
6299 * tfru read.
6300 *
6301 * @param[in] fru - fru structure
6302 * @param[in] buf - read data buffer
6303 * @param[in] len - data buffer length
6304 * @param[in] offset - offset relative to starting address
6305 * @param[in] cbfn - callback function
6306 * @param[in] cbarg - callback argument
6307 *
6308 * Return status.
6309 */
6310bfa_status_t
6311bfa_tfru_read(struct bfa_fru_s *fru, void *buf, u32 len, u32 offset,
6312 bfa_cb_fru_t cbfn, void *cbarg)
6313{
6314 bfa_trc(fru, BFI_TFRU_H2I_READ_REQ);
6315 bfa_trc(fru, len);
6316 bfa_trc(fru, offset);
6317
6318 if (fru->ioc->asic_gen != BFI_ASIC_GEN_CT2)
6319 return BFA_STATUS_FRU_NOT_PRESENT;
6320
6321 if (!bfa_ioc_is_operational(fru->ioc))
6322 return BFA_STATUS_IOC_NON_OP;
6323
6324 if (fru->op_busy) {
6325 bfa_trc(fru, fru->op_busy);
6326 return BFA_STATUS_DEVBUSY;
6327 }
6328
6329 fru->op_busy = 1;
6330
6331 fru->cbfn = cbfn;
6332 fru->cbarg = cbarg;
6333 fru->residue = len;
6334 fru->offset = 0;
6335 fru->addr_off = offset;
6336 fru->ubuf = buf;
6337 bfa_fru_read_send(fru, BFI_TFRU_H2I_READ_REQ);
6338
6339 return BFA_STATUS_OK;
6340}
6341
6342/*
6343 * Process fru response messages upon receiving interrupts.
6344 *
6345 * @param[in] fruarg - fru structure
6346 * @param[in] msg - message structure
6347 */
6348void
6349bfa_fru_intr(void *fruarg, struct bfi_mbmsg_s *msg)
6350{
6351 struct bfa_fru_s *fru = fruarg;
6352 struct bfi_fru_rsp_s *rsp = (struct bfi_fru_rsp_s *)msg;
6353 u32 status;
6354
6355 bfa_trc(fru, msg->mh.msg_id);
6356
6357 if (!fru->op_busy) {
6358 /*
6359 * receiving response after ioc failure
6360 */
6361 bfa_trc(fru, 0x9999);
6362 return;
6363 }
6364
6365 switch (msg->mh.msg_id) {
6366 case BFI_FRUVPD_I2H_WRITE_RSP:
6367 case BFI_TFRU_I2H_WRITE_RSP:
6368 status = be32_to_cpu(rsp->status);
6369 bfa_trc(fru, status);
6370
6371 if (status != BFA_STATUS_OK || fru->residue == 0) {
6372 fru->status = status;
6373 fru->op_busy = 0;
6374 if (fru->cbfn)
6375 fru->cbfn(fru->cbarg, fru->status);
6376 } else {
6377 bfa_trc(fru, fru->offset);
6378 if (msg->mh.msg_id == BFI_FRUVPD_I2H_WRITE_RSP)
6379 bfa_fru_write_send(fru,
6380 BFI_FRUVPD_H2I_WRITE_REQ);
6381 else
6382 bfa_fru_write_send(fru,
6383 BFI_TFRU_H2I_WRITE_REQ);
6384 }
6385 break;
6386 case BFI_FRUVPD_I2H_READ_RSP:
6387 case BFI_TFRU_I2H_READ_RSP:
6388 status = be32_to_cpu(rsp->status);
6389 bfa_trc(fru, status);
6390
6391 if (status != BFA_STATUS_OK) {
6392 fru->status = status;
6393 fru->op_busy = 0;
6394 if (fru->cbfn)
6395 fru->cbfn(fru->cbarg, fru->status);
6396 } else {
6397 u32 len = be32_to_cpu(rsp->length);
6398
6399 bfa_trc(fru, fru->offset);
6400 bfa_trc(fru, len);
6401
6402 memcpy(fru->ubuf + fru->offset, fru->dbuf_kva, len);
6403 fru->residue -= len;
6404 fru->offset += len;
6405
6406 if (fru->residue == 0) {
6407 fru->status = status;
6408 fru->op_busy = 0;
6409 if (fru->cbfn)
6410 fru->cbfn(fru->cbarg, fru->status);
6411 } else {
6412 if (msg->mh.msg_id == BFI_FRUVPD_I2H_READ_RSP)
6413 bfa_fru_read_send(fru,
6414 BFI_FRUVPD_H2I_READ_REQ);
6415 else
6416 bfa_fru_read_send(fru,
6417 BFI_TFRU_H2I_READ_REQ);
6418 }
6419 }
6420 break;
6421 default:
6422 WARN_ON(1);
6423 }
6424}
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