[mirror_ubuntu-artful-kernel.git] / drivers / scsi / bfa / bfi.h

/*
 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
 * All rights reserved
 * www.brocade.com
 *
 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License (GPL) Version 2 as
 * published by the Free Software Foundation
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */

#ifndef __BFI_H__
#define __BFI_H__

#include "bfa_defs.h"
#include "bfa_defs_svc.h"

#pragma pack(1)

/*
 * BFI FW image type
 */
#define	BFI_FLASH_CHUNK_SZ			256	/*  Flash chunk size */
#define	BFI_FLASH_CHUNK_SZ_WORDS	(BFI_FLASH_CHUNK_SZ/sizeof(u32))

/*
 * Msg header common to all msgs
 */
struct bfi_mhdr_s {
	u8		msg_class;	/*  @ref bfi_mclass_t		    */
	u8		msg_id;		/*  msg opcode with in the class   */
	union {
		struct {
			u8	qid;
			u8	lpu_id;	/*  msg destination		    */
		} h2i;
		u16	i2htok;	/*  token in msgs to host	    */
	} mtag;
};

#define bfi_mhdr_2_qid(_mh)	((_mh)->mtag.h2i.qid)

#define bfi_h2i_set(_mh, _mc, _op, _lpuid) do {		\
	(_mh).msg_class		= (_mc);      \
	(_mh).msg_id		= (_op);      \
	(_mh).mtag.h2i.lpu_id	= (_lpuid);      \
} while (0)

#define bfi_i2h_set(_mh, _mc, _op, _i2htok) do {		\
	(_mh).msg_class		= (_mc);      \
	(_mh).msg_id		= (_op);      \
	(_mh).mtag.i2htok	= (_i2htok);      \
} while (0)

/*
 * Message opcodes: 0-127 to firmware, 128-255 to host
 */
#define BFI_I2H_OPCODE_BASE	128
#define BFA_I2HM(_x)		((_x) + BFI_I2H_OPCODE_BASE)

/*
 ****************************************************************************
 *
 * Scatter Gather Element and Page definition
 *
 ****************************************************************************
 */

#define BFI_SGE_INLINE	1
#define BFI_SGE_INLINE_MAX	(BFI_SGE_INLINE + 1)

/*
 * SG Flags
 */
enum {
	BFI_SGE_DATA		= 0,	/*  data address, not last	     */
	BFI_SGE_DATA_CPL	= 1,	/*  data addr, last in current page */
	BFI_SGE_DATA_LAST	= 3,	/*  data address, last		     */
	BFI_SGE_LINK		= 2,	/*  link address		     */
	BFI_SGE_PGDLEN		= 2,	/*  cumulative data length for page */
};

/*
 * DMA addresses
 */
union bfi_addr_u {
	struct {
		__be32	addr_lo;
		__be32	addr_hi;
	} a32;
};

/*
 * Scatter Gather Element used for fast-path IO requests
 */
struct bfi_sge_s {
#ifdef __BIG_ENDIAN
	u32	flags:2,
			rsvd:2,
			sg_len:28;
#else
	u32	sg_len:28,
			rsvd:2,
			flags:2;
#endif
	union bfi_addr_u sga;
};

/**
 * Generic DMA addr-len pair.
 */
struct bfi_alen_s {
	union bfi_addr_u	al_addr;	/* DMA addr of buffer	*/
	u32			al_len;		/* length of buffer	*/
};

/*
 * Scatter Gather Page
 */
#define BFI_SGPG_DATA_SGES		7
#define BFI_SGPG_SGES_MAX		(BFI_SGPG_DATA_SGES + 1)
#define BFI_SGPG_RSVD_WD_LEN	8
struct bfi_sgpg_s {
	struct bfi_sge_s sges[BFI_SGPG_SGES_MAX];
	u32	rsvd[BFI_SGPG_RSVD_WD_LEN];
};

/*
 * Large Message structure - 128 Bytes size Msgs
 */
#define BFI_LMSG_SZ		128
#define BFI_LMSG_PL_WSZ	\
			((BFI_LMSG_SZ - sizeof(struct bfi_mhdr_s)) / 4)

struct bfi_msg_s {
	struct bfi_mhdr_s mhdr;
	u32	pl[BFI_LMSG_PL_WSZ];
};

/*
 * Mailbox message structure
 */
#define BFI_MBMSG_SZ		7
struct bfi_mbmsg_s {
	struct bfi_mhdr_s	mh;
	u32		pl[BFI_MBMSG_SZ];
};

/*
 * Supported PCI function class codes (personality)
 */
enum bfi_pcifn_class {
	BFI_PCIFN_CLASS_FC  = 0x0c04,
	BFI_PCIFN_CLASS_ETH = 0x0200,
};

/*
 * Message Classes
 */
enum bfi_mclass {
	BFI_MC_IOC		= 1,	/*  IO Controller (IOC)	    */
	BFI_MC_FCPORT		= 5,	/*  FC port			    */
	BFI_MC_IOCFC		= 6,	/*  FC - IO Controller (IOC)	    */
	BFI_MC_ABLK		= 7,	/*  ASIC block configuration	    */
	BFI_MC_UF		= 8,	/*  Unsolicited frame receive	    */
	BFI_MC_FCXP		= 9,	/*  FC Transport		    */
	BFI_MC_LPS		= 10,	/*  lport fc login services	    */
	BFI_MC_RPORT		= 11,	/*  Remote port		    */
	BFI_MC_ITN		= 12,	/*  I-T nexus (Initiator mode)	    */
	BFI_MC_IOIM_READ	= 13,	/*  read IO (Initiator mode)	    */
	BFI_MC_IOIM_WRITE	= 14,	/*  write IO (Initiator mode)	    */
	BFI_MC_IOIM_IO		= 15,	/*  IO (Initiator mode)	    */
	BFI_MC_IOIM		= 16,	/*  IO (Initiator mode)	    */
	BFI_MC_IOIM_IOCOM	= 17,	/*  good IO completion		    */
	BFI_MC_TSKIM		= 18,	/*  Initiator Task management	    */
	BFI_MC_PORT		= 21,	/*  Physical port		    */
	BFI_MC_MAX		= 32
};

#define BFI_IOC_MAX_CQS		4
#define BFI_IOC_MAX_CQS_ASIC	8
#define BFI_IOC_MSGLEN_MAX	32	/* 32 bytes */

/*
 *----------------------------------------------------------------------
 *				IOC
 *----------------------------------------------------------------------
 */

/*
 * Different asic generations
 */
enum bfi_asic_gen {
	BFI_ASIC_GEN_CB		= 1,	/* crossbow 8G FC		*/
	BFI_ASIC_GEN_CT		= 2,	/* catapult 8G FC or 10G CNA	*/
	BFI_ASIC_GEN_CT2	= 3,	/* catapult-2 16G FC or 10G CNA	*/
};

enum bfi_asic_mode {
	BFI_ASIC_MODE_FC	= 1,	/* FC upto 8G speed		*/
	BFI_ASIC_MODE_FC16	= 2,	/* FC upto 16G speed		*/
	BFI_ASIC_MODE_ETH	= 3,	/* Ethernet ports		*/
	BFI_ASIC_MODE_COMBO	= 4,	/* FC 16G and Ethernet 10G port	*/
};

enum bfi_ioc_h2i_msgs {
	BFI_IOC_H2I_ENABLE_REQ		= 1,
	BFI_IOC_H2I_DISABLE_REQ		= 2,
	BFI_IOC_H2I_GETATTR_REQ		= 3,
	BFI_IOC_H2I_DBG_SYNC		= 4,
	BFI_IOC_H2I_DBG_DUMP		= 5,
};

enum bfi_ioc_i2h_msgs {
	BFI_IOC_I2H_ENABLE_REPLY	= BFA_I2HM(1),
	BFI_IOC_I2H_DISABLE_REPLY	= BFA_I2HM(2),
	BFI_IOC_I2H_GETATTR_REPLY	= BFA_I2HM(3),
	BFI_IOC_I2H_HBEAT		= BFA_I2HM(4),
	BFI_IOC_I2H_ACQ_ADDR_REPLY	= BFA_I2HM(5),
};

/*
 * BFI_IOC_H2I_GETATTR_REQ message
 */
struct bfi_ioc_getattr_req_s {
	struct bfi_mhdr_s	mh;
	union bfi_addr_u	attr_addr;
};

struct bfi_ioc_attr_s {
	wwn_t		mfg_pwwn;	/*  Mfg port wwn	   */
	wwn_t		mfg_nwwn;	/*  Mfg node wwn	   */
	mac_t		mfg_mac;	/*  Mfg mac		   */
	u8		port_mode;	/* bfi_port_mode	   */
	u8		rsvd_a;
	wwn_t		pwwn;
	wwn_t		nwwn;
	mac_t		mac;		/*  PBC or Mfg mac	   */
	u16	rsvd_b;
	mac_t		fcoe_mac;
	u16	rsvd_c;
	char		brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
	u8		pcie_gen;
	u8		pcie_lanes_orig;
	u8		pcie_lanes;
	u8		rx_bbcredit;	/*  receive buffer credits */
	u32	adapter_prop;	/*  adapter properties     */
	u16	maxfrsize;	/*  max receive frame size */
	char		asic_rev;
	u8		rsvd_d;
	char		fw_version[BFA_VERSION_LEN];
	char		optrom_version[BFA_VERSION_LEN];
	struct		bfa_mfg_vpd_s	vpd;
	u32	card_type;	/*  card type			*/
};

/*
 * BFI_IOC_I2H_GETATTR_REPLY message
 */
struct bfi_ioc_getattr_reply_s {
	struct	bfi_mhdr_s	mh;	/*  Common msg header		*/
	u8			status;	/*  cfg reply status		*/
	u8			rsvd[3];
};

/*
 * Firmware memory page offsets
 */
#define BFI_IOC_SMEM_PG0_CB	(0x40)
#define BFI_IOC_SMEM_PG0_CT	(0x180)

/*
 * Firmware statistic offset
 */
#define BFI_IOC_FWSTATS_OFF	(0x6B40)
#define BFI_IOC_FWSTATS_SZ	(4096)

/*
 * Firmware trace offset
 */
#define BFI_IOC_TRC_OFF		(0x4b00)
#define BFI_IOC_TRC_ENTS	256

#define BFI_IOC_FW_SIGNATURE	(0xbfadbfad)
#define BFI_IOC_MD5SUM_SZ	4
struct bfi_ioc_image_hdr_s {
	u32	signature;	/* constant signature		*/
	u8	asic_gen;	/* asic generation		*/
	u8	asic_mode;
	u8	port0_mode;	/* device mode for port 0	*/
	u8	port1_mode;	/* device mode for port 1	*/
	u32	exec;		/* exec vector			*/
	u32	bootenv;	/* fimware boot env		*/
	u32	rsvd_b[4];
	u32	md5sum[BFI_IOC_MD5SUM_SZ];
};

#define BFI_FWBOOT_DEVMODE_OFF		4
#define BFI_FWBOOT_TYPE_OFF		8
#define BFI_FWBOOT_ENV_OFF		12
#define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \
	(((u32)(__asic_gen)) << 24 |		\
	 ((u32)(__asic_mode)) << 16 |		\
	 ((u32)(__p0_mode)) << 8 |		\
	 ((u32)(__p1_mode)))

#define BFI_FWBOOT_TYPE_NORMAL	0
#define BFI_FWBOOT_TYPE_MEMTEST	1
#define BFI_FWBOOT_ENV_OS       0

enum bfi_port_mode {
	BFI_PORT_MODE_FC	= 1,
	BFI_PORT_MODE_ETH	= 2,
};

struct bfi_ioc_hbeat_s {
	struct bfi_mhdr_s  mh;		/*  common msg header		*/
	u32	   hb_count;	/*  current heart beat count	*/
};

/*
 * IOC hardware/firmware state
 */
enum bfi_ioc_state {
	BFI_IOC_UNINIT		= 0,	/*  not initialized		     */
	BFI_IOC_INITING		= 1,	/*  h/w is being initialized	     */
	BFI_IOC_HWINIT		= 2,	/*  h/w is initialized		     */
	BFI_IOC_CFG		= 3,	/*  IOC configuration in progress   */
	BFI_IOC_OP		= 4,	/*  IOC is operational		     */
	BFI_IOC_DISABLING	= 5,	/*  IOC is being disabled	     */
	BFI_IOC_DISABLED	= 6,	/*  IOC is disabled		     */
	BFI_IOC_CFG_DISABLED	= 7,	/*  IOC is being disabled;transient */
	BFI_IOC_FAIL		= 8,	/*  IOC heart-beat failure	     */
	BFI_IOC_MEMTEST		= 9,	/*  IOC is doing memtest	     */
};

#define BFI_IOC_ENDIAN_SIG  0x12345678

enum {
	BFI_ADAPTER_TYPE_FC	= 0x01,		/*  FC adapters	   */
	BFI_ADAPTER_TYPE_MK	= 0x0f0000,	/*  adapter type mask     */
	BFI_ADAPTER_TYPE_SH	= 16,	        /*  adapter type shift    */
	BFI_ADAPTER_NPORTS_MK	= 0xff00,	/*  number of ports mask  */
	BFI_ADAPTER_NPORTS_SH	= 8,	        /*  number of ports shift */
	BFI_ADAPTER_SPEED_MK	= 0xff,		/*  adapter speed mask    */
	BFI_ADAPTER_SPEED_SH	= 0,	        /*  adapter speed shift   */
	BFI_ADAPTER_PROTO	= 0x100000,	/*  prototype adapaters   */
	BFI_ADAPTER_TTV		= 0x200000,	/*  TTV debug capable     */
	BFI_ADAPTER_UNSUPP	= 0x400000,	/*  unknown adapter type  */
};

#define BFI_ADAPTER_GETP(__prop, __adap_prop)			\
	(((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >>	\
		BFI_ADAPTER_ ## __prop ## _SH)
#define BFI_ADAPTER_SETP(__prop, __val)				\
	((__val) << BFI_ADAPTER_ ## __prop ## _SH)
#define BFI_ADAPTER_IS_PROTO(__adap_type)			\
	((__adap_type) & BFI_ADAPTER_PROTO)
#define BFI_ADAPTER_IS_TTV(__adap_type)				\
	((__adap_type) & BFI_ADAPTER_TTV)
#define BFI_ADAPTER_IS_UNSUPP(__adap_type)			\
	((__adap_type) & BFI_ADAPTER_UNSUPP)
#define BFI_ADAPTER_IS_SPECIAL(__adap_type)			\
	((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO |	\
			BFI_ADAPTER_UNSUPP))

/*
 * BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages
 */
struct bfi_ioc_ctrl_req_s {
	struct bfi_mhdr_s	mh;
	u16			clscode;
	u16			rsvd;
	u32		tv_sec;
};
#define bfi_ioc_enable_req_t struct bfi_ioc_ctrl_req_s;
#define bfi_ioc_disable_req_t struct bfi_ioc_ctrl_req_s;

/*
 * BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages
 */
struct bfi_ioc_ctrl_reply_s {
	struct bfi_mhdr_s	mh;		/*  Common msg header     */
	u8			status;		/*  enable/disable status */
	u8			port_mode;	/*  bfa_mode_s	*/
	u8			cap_bm;		/*  capability bit mask */
	u8			rsvd;
};
#define bfi_ioc_enable_reply_t struct bfi_ioc_ctrl_reply_s;
#define bfi_ioc_disable_reply_t struct bfi_ioc_ctrl_reply_s;

#define BFI_IOC_MSGSZ   8
/*
 * H2I Messages
 */
union bfi_ioc_h2i_msg_u {
	struct bfi_mhdr_s		mh;
	struct bfi_ioc_ctrl_req_s	enable_req;
	struct bfi_ioc_ctrl_req_s	disable_req;
	struct bfi_ioc_getattr_req_s	getattr_req;
	u32			mboxmsg[BFI_IOC_MSGSZ];
};

/*
 * I2H Messages
 */
union bfi_ioc_i2h_msg_u {
	struct bfi_mhdr_s		mh;
	struct bfi_ioc_ctrl_reply_s	fw_event;
	u32			mboxmsg[BFI_IOC_MSGSZ];
};


/*
 *----------------------------------------------------------------------
 *				PBC
 *----------------------------------------------------------------------
 */

#define BFI_PBC_MAX_BLUNS	8
#define BFI_PBC_MAX_VPORTS	16
#define BFI_PBC_PORT_DISABLED	2

/*
 * PBC boot lun configuration
 */
struct bfi_pbc_blun_s {
	wwn_t		tgt_pwwn;
	struct scsi_lun	tgt_lun;
};

/*
 * PBC virtual port configuration
 */
struct bfi_pbc_vport_s {
	wwn_t		vp_pwwn;
	wwn_t		vp_nwwn;
};

/*
 * BFI pre-boot configuration information
 */
struct bfi_pbc_s {
	u8		port_enabled;
	u8		boot_enabled;
	u8		nbluns;
	u8		nvports;
	u8		port_speed;
	u8		rsvd_a;
	u16	hss;
	wwn_t		pbc_pwwn;
	wwn_t		pbc_nwwn;
	struct bfi_pbc_blun_s blun[BFI_PBC_MAX_BLUNS];
	struct bfi_pbc_vport_s vport[BFI_PBC_MAX_VPORTS];
};

/*
 *----------------------------------------------------------------------
 *				MSGQ
 *----------------------------------------------------------------------
 */
#define BFI_MSGQ_FULL(_q)	(((_q->pi + 1) % _q->q_depth) == _q->ci)
#define BFI_MSGQ_EMPTY(_q)	(_q->pi == _q->ci)
#define BFI_MSGQ_UPDATE_CI(_q)	(_q->ci = (_q->ci + 1) % _q->q_depth)
#define BFI_MSGQ_UPDATE_PI(_q)	(_q->pi = (_q->pi + 1) % _q->q_depth)

/* q_depth must be power of 2 */
#define BFI_MSGQ_FREE_CNT(_q)	((_q->ci - _q->pi - 1) & (_q->q_depth - 1))

enum bfi_msgq_h2i_msgs_e {
	BFI_MSGQ_H2I_INIT_REQ	= 1,
	BFI_MSGQ_H2I_DOORBELL	= 2,
	BFI_MSGQ_H2I_SHUTDOWN	= 3,
};

enum bfi_msgq_i2h_msgs_e {
	BFI_MSGQ_I2H_INIT_RSP	= 1,
	BFI_MSGQ_I2H_DOORBELL	= 2,
};


/* Messages(commands/responsed/AENS will have the following header */
struct bfi_msgq_mhdr_s {
	u8		msg_class;
	u8		msg_id;
	u16	msg_token;
	u16	num_entries;
	u8		enet_id;
	u8		rsvd[1];
};

#define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do {        \
	(_mh).msg_class		= (_mc);      \
	(_mh).msg_id		= (_mid);      \
	(_mh).msg_token		= (_tok);      \
	(_mh).enet_id		= (_enet_id);      \
} while (0)

/*
 * Mailbox  for messaging interface
 *
*/
#define BFI_MSGQ_CMD_ENTRY_SIZE		(64)    /* TBD */
#define BFI_MSGQ_RSP_ENTRY_SIZE		(64)    /* TBD */
#define BFI_MSGQ_MSG_SIZE_MAX		(2048)  /* TBD */

struct bfi_msgq_s {
	union bfi_addr_u addr;
	u16 q_depth;     /* Total num of entries in the queue */
	u8 rsvd[2];
};

/* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */
struct bfi_msgq_cfg_req_s {
	struct bfi_mhdr_s mh;
	struct bfi_msgq_s cmdq;
	struct bfi_msgq_s rspq;
};

/* BFI_ENET_MSGQ_CFG_RSP */
struct bfi_msgq_cfg_rsp_s {
	struct bfi_mhdr_s mh;
	u8 cmd_status;
	u8 rsvd[3];
};


/* BFI_MSGQ_H2I_DOORBELL */
struct bfi_msgq_h2i_db_s {
	struct bfi_mhdr_s mh;
	u16 cmdq_pi;
	u16 rspq_ci;
};

/* BFI_MSGQ_I2H_DOORBELL */
struct bfi_msgq_i2h_db_s {
	struct bfi_mhdr_s mh;
	u16 rspq_pi;
	u16 cmdq_ci;
};

#pragma pack()

/* BFI port specific */
#pragma pack(1)

enum bfi_port_h2i {
	BFI_PORT_H2I_ENABLE_REQ         = (1),
	BFI_PORT_H2I_DISABLE_REQ        = (2),
	BFI_PORT_H2I_GET_STATS_REQ      = (3),
	BFI_PORT_H2I_CLEAR_STATS_REQ    = (4),
};

enum bfi_port_i2h {
	BFI_PORT_I2H_ENABLE_RSP         = BFA_I2HM(1),
	BFI_PORT_I2H_DISABLE_RSP        = BFA_I2HM(2),
	BFI_PORT_I2H_GET_STATS_RSP      = BFA_I2HM(3),
	BFI_PORT_I2H_CLEAR_STATS_RSP    = BFA_I2HM(4),
};

/*
 * Generic REQ type
 */
struct bfi_port_generic_req_s {
	struct bfi_mhdr_s  mh;          /*  msg header		*/
	u32     msgtag;         /*  msgtag for reply                */
	u32     rsvd;
};

/*
 * Generic RSP type
 */
struct bfi_port_generic_rsp_s {
	struct bfi_mhdr_s  mh;          /*  common msg header               */
	u8              status;         /*  port enable status              */
	u8              rsvd[3];
	u32     msgtag;         /*  msgtag for reply                */
};

/*
 * BFI_PORT_H2I_GET_STATS_REQ
 */
struct bfi_port_get_stats_req_s {
	struct bfi_mhdr_s  mh;          /*  common msg header               */
	union bfi_addr_u   dma_addr;
};

union bfi_port_h2i_msg_u {
	struct bfi_mhdr_s               mh;
	struct bfi_port_generic_req_s   enable_req;
	struct bfi_port_generic_req_s   disable_req;
	struct bfi_port_get_stats_req_s getstats_req;
	struct bfi_port_generic_req_s   clearstats_req;
};

union bfi_port_i2h_msg_u {
	struct bfi_mhdr_s               mh;
	struct bfi_port_generic_rsp_s   enable_rsp;
	struct bfi_port_generic_rsp_s   disable_rsp;
	struct bfi_port_generic_rsp_s   getstats_rsp;
	struct bfi_port_generic_rsp_s   clearstats_rsp;
};

/*
 *----------------------------------------------------------------------
 *				ABLK
 *----------------------------------------------------------------------
 */
enum bfi_ablk_h2i_msgs_e {
	BFI_ABLK_H2I_QUERY		= 1,
	BFI_ABLK_H2I_ADPT_CONFIG	= 2,
	BFI_ABLK_H2I_PORT_CONFIG	= 3,
	BFI_ABLK_H2I_PF_CREATE		= 4,
	BFI_ABLK_H2I_PF_DELETE		= 5,
	BFI_ABLK_H2I_PF_UPDATE		= 6,
	BFI_ABLK_H2I_OPTROM_ENABLE	= 7,
	BFI_ABLK_H2I_OPTROM_DISABLE	= 8,
};

enum bfi_ablk_i2h_msgs_e {
	BFI_ABLK_I2H_QUERY		= BFA_I2HM(BFI_ABLK_H2I_QUERY),
	BFI_ABLK_I2H_ADPT_CONFIG	= BFA_I2HM(BFI_ABLK_H2I_ADPT_CONFIG),
	BFI_ABLK_I2H_PORT_CONFIG	= BFA_I2HM(BFI_ABLK_H2I_PORT_CONFIG),
	BFI_ABLK_I2H_PF_CREATE		= BFA_I2HM(BFI_ABLK_H2I_PF_CREATE),
	BFI_ABLK_I2H_PF_DELETE		= BFA_I2HM(BFI_ABLK_H2I_PF_DELETE),
	BFI_ABLK_I2H_PF_UPDATE		= BFA_I2HM(BFI_ABLK_H2I_PF_UPDATE),
	BFI_ABLK_I2H_OPTROM_ENABLE	= BFA_I2HM(BFI_ABLK_H2I_OPTROM_ENABLE),
	BFI_ABLK_I2H_OPTROM_DISABLE	= BFA_I2HM(BFI_ABLK_H2I_OPTROM_DISABLE),
};

/* BFI_ABLK_H2I_QUERY */
struct bfi_ablk_h2i_query_s {
	struct bfi_mhdr_s	mh;
	union bfi_addr_u	addr;
};

/* BFI_ABL_H2I_ADPT_CONFIG, BFI_ABLK_H2I_PORT_CONFIG */
struct bfi_ablk_h2i_cfg_req_s {
	struct bfi_mhdr_s	mh;
	u8			mode;
	u8			port;
	u8			max_pf;
	u8			max_vf;
};

/*
 * BFI_ABLK_H2I_PF_CREATE, BFI_ABLK_H2I_PF_DELETE,
 */
struct bfi_ablk_h2i_pf_req_s {
	struct bfi_mhdr_s	mh;
	u8			pcifn;
	u8			port;
	u16			pers;
	u32			bw;
};

/* BFI_ABLK_H2I_OPTROM_ENABLE, BFI_ABLK_H2I_OPTROM_DISABLE */
struct bfi_ablk_h2i_optrom_s {
	struct bfi_mhdr_s	mh;
};

/*
 * BFI_ABLK_I2H_QUERY
 * BFI_ABLK_I2H_PORT_CONFIG
 * BFI_ABLK_I2H_PF_CREATE
 * BFI_ABLK_I2H_PF_DELETE
 * BFI_ABLK_I2H_PF_UPDATE
 * BFI_ABLK_I2H_OPTROM_ENABLE
 * BFI_ABLK_I2H_OPTROM_DISABLE
 */
struct bfi_ablk_i2h_rsp_s {
	struct bfi_mhdr_s	mh;
	u8			status;
	u8			pcifn;
	u8			port_mode;
};

#pragma pack()

#endif /* __BFI_H__ */
Commit	Line	Data
a36c61f9 KG	1	/*
	2	* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
	3	* All rights reserved
	4	* www.brocade.com
	5	*
	6	* Linux driver for Brocade Fibre Channel Host Bus Adapter.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License (GPL) Version 2 as
	10	* published by the Free Software Foundation
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*/
	17
	18	#ifndef __BFI_H__
	19	#define __BFI_H__
	20
	21	#include "bfa_defs.h"
	22	#include "bfa_defs_svc.h"
	23
	24	#pragma pack(1)
	25
acdc79a6	26	/*
a36c61f9 KG	27	* BFI FW image type
	28	*/
	29	#define BFI_FLASH_CHUNK_SZ 256 /* Flash chunk size */
	30	#define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32))
a36c61f9	31
acdc79a6	32	/*
a36c61f9 KG	33	* Msg header common to all msgs
	34	*/
	35	struct bfi_mhdr_s {
	36	u8 msg_class; /* @ref bfi_mclass_t */
	37	u8 msg_id; /* msg opcode with in the class */
	38	union {
	39	struct {
d37779f8	40	u8 qid;
a36c61f9 KG	41	u8 lpu_id; /* msg destination */
	42	} h2i;
	43	u16 i2htok; /* token in msgs to host */
	44	} mtag;
	45	};
	46
43ffdf4d	47	#define bfi_mhdr_2_qid(_mh) ((_mh)->mtag.h2i.qid)
d37779f8	48
a36c61f9 KG	49	#define bfi_h2i_set(_mh, _mc, _op, _lpuid) do { \
	50	(_mh).msg_class = (_mc); \
	51	(_mh).msg_id = (_op); \
	52	(_mh).mtag.h2i.lpu_id = (_lpuid); \
	53	} while (0)
	54
	55	#define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \
	56	(_mh).msg_class = (_mc); \
	57	(_mh).msg_id = (_op); \
	58	(_mh).mtag.i2htok = (_i2htok); \
	59	} while (0)
	60
	61	/*
	62	* Message opcodes: 0-127 to firmware, 128-255 to host
	63	*/
	64	#define BFI_I2H_OPCODE_BASE 128
	65	#define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE)
	66
acdc79a6	67	/*
a36c61f9 KG	68	****************************************************************************
	69	*
	70	* Scatter Gather Element and Page definition
	71	*
	72	****************************************************************************
	73	*/
	74
	75	#define BFI_SGE_INLINE 1
	76	#define BFI_SGE_INLINE_MAX (BFI_SGE_INLINE + 1)
	77
acdc79a6	78	/*
a36c61f9 KG	79	* SG Flags
	80	*/
	81	enum {
	82	BFI_SGE_DATA = 0, /* data address, not last */
	83	BFI_SGE_DATA_CPL = 1, /* data addr, last in current page */
	84	BFI_SGE_DATA_LAST = 3, /* data address, last */
	85	BFI_SGE_LINK = 2, /* link address */
	86	BFI_SGE_PGDLEN = 2, /* cumulative data length for page */
	87	};
	88
acdc79a6	89	/*
a36c61f9 KG	90	* DMA addresses
	91	*/
	92	union bfi_addr_u {
	93	struct {
50444a34 M	94	__be32 addr_lo;
50444a34 M	95	__be32 addr_hi;
a36c61f9 KG	96	} a32;
	97	};
	98
acdc79a6	99	/*
85ce928d	100	* Scatter Gather Element used for fast-path IO requests
a36c61f9 KG	101	*/
a36c61f9 KG	102	struct bfi_sge_s {
f16a1750	103	#ifdef __BIG_ENDIAN
a36c61f9 KG	104	u32 flags:2,
	105	rsvd:2,
	106	sg_len:28;
	107	#else
	108	u32 sg_len:28,
	109	rsvd:2,
	110	flags:2;
	111	#endif
	112	union bfi_addr_u sga;
	113	};
	114
85ce928d KG	115	/**
	116	* Generic DMA addr-len pair.
	117	*/
	118	struct bfi_alen_s {
	119	union bfi_addr_u al_addr; /* DMA addr of buffer */
	120	u32 al_len; /* length of buffer */
	121	};
	122
acdc79a6	123	/*
a36c61f9 KG	124	* Scatter Gather Page
	125	*/
	126	#define BFI_SGPG_DATA_SGES 7
	127	#define BFI_SGPG_SGES_MAX (BFI_SGPG_DATA_SGES + 1)
	128	#define BFI_SGPG_RSVD_WD_LEN 8
	129	struct bfi_sgpg_s {
	130	struct bfi_sge_s sges[BFI_SGPG_SGES_MAX];
	131	u32 rsvd[BFI_SGPG_RSVD_WD_LEN];
	132	};
	133
	134	/*
	135	* Large Message structure - 128 Bytes size Msgs
	136	*/
	137	#define BFI_LMSG_SZ 128
	138	#define BFI_LMSG_PL_WSZ \
	139	((BFI_LMSG_SZ - sizeof(struct bfi_mhdr_s)) / 4)
	140
	141	struct bfi_msg_s {
	142	struct bfi_mhdr_s mhdr;
	143	u32 pl[BFI_LMSG_PL_WSZ];
	144	};
	145
acdc79a6	146	/*
a36c61f9 KG	147	* Mailbox message structure
	148	*/
	149	#define BFI_MBMSG_SZ 7
	150	struct bfi_mbmsg_s {
	151	struct bfi_mhdr_s mh;
	152	u32 pl[BFI_MBMSG_SZ];
	153	};
	154
d37779f8 KG	155	/*
	156	* Supported PCI function class codes (personality)
	157	*/
	158	enum bfi_pcifn_class {
	159	BFI_PCIFN_CLASS_FC = 0x0c04,
	160	BFI_PCIFN_CLASS_ETH = 0x0200,
	161	};
	162
acdc79a6	163	/*
a36c61f9 KG	164	* Message Classes
	165	*/
	166	enum bfi_mclass {
	167	BFI_MC_IOC = 1, /* IO Controller (IOC) */
	168	BFI_MC_FCPORT = 5, /* FC port */
	169	BFI_MC_IOCFC = 6, /* FC - IO Controller (IOC) */
1a4d8e1b	170	BFI_MC_ABLK = 7, /* ASIC block configuration */
a36c61f9 KG	171	BFI_MC_UF = 8, /* Unsolicited frame receive */
	172	BFI_MC_FCXP = 9, /* FC Transport */
	173	BFI_MC_LPS = 10, /* lport fc login services */
	174	BFI_MC_RPORT = 11, /* Remote port */
dd5aaf45	175	BFI_MC_ITN = 12, /* I-T nexus (Initiator mode) */
a36c61f9 KG	176	BFI_MC_IOIM_READ = 13, /* read IO (Initiator mode) */
	177	BFI_MC_IOIM_WRITE = 14, /* write IO (Initiator mode) */
	178	BFI_MC_IOIM_IO = 15, /* IO (Initiator mode) */
	179	BFI_MC_IOIM = 16, /* IO (Initiator mode) */
	180	BFI_MC_IOIM_IOCOM = 17, /* good IO completion */
	181	BFI_MC_TSKIM = 18, /* Initiator Task management */
	182	BFI_MC_PORT = 21, /* Physical port */
	183	BFI_MC_MAX = 32
	184	};
	185
	186	#define BFI_IOC_MAX_CQS 4
	187	#define BFI_IOC_MAX_CQS_ASIC 8
	188	#define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */
	189
acdc79a6	190	/*
a36c61f9 KG	191	*----------------------------------------------------------------------
	192	* IOC
	193	*----------------------------------------------------------------------
	194	*/
	195
11189208 KG	196	/*
	197	* Different asic generations
	198	*/
	199	enum bfi_asic_gen {
	200	BFI_ASIC_GEN_CB = 1, /* crossbow 8G FC */
	201	BFI_ASIC_GEN_CT = 2, /* catapult 8G FC or 10G CNA */
	202	BFI_ASIC_GEN_CT2 = 3, /* catapult-2 16G FC or 10G CNA */
	203	};
	204
	205	enum bfi_asic_mode {
	206	BFI_ASIC_MODE_FC = 1, /* FC upto 8G speed */
	207	BFI_ASIC_MODE_FC16 = 2, /* FC upto 16G speed */
	208	BFI_ASIC_MODE_ETH = 3, /* Ethernet ports */
	209	BFI_ASIC_MODE_COMBO = 4, /* FC 16G and Ethernet 10G port */
	210	};
	211
a36c61f9 KG	212	enum bfi_ioc_h2i_msgs {
	213	BFI_IOC_H2I_ENABLE_REQ = 1,
	214	BFI_IOC_H2I_DISABLE_REQ = 2,
	215	BFI_IOC_H2I_GETATTR_REQ = 3,
	216	BFI_IOC_H2I_DBG_SYNC = 4,
	217	BFI_IOC_H2I_DBG_DUMP = 5,
	218	};
	219
	220	enum bfi_ioc_i2h_msgs {
	221	BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1),
	222	BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2),
	223	BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3),
775c7742	224	BFI_IOC_I2H_HBEAT = BFA_I2HM(4),
a714134a	225	BFI_IOC_I2H_ACQ_ADDR_REPLY = BFA_I2HM(5),
a36c61f9 KG	226	};
a36c61f9 KG	227
acdc79a6	228	/*
a36c61f9 KG	229	* BFI_IOC_H2I_GETATTR_REQ message
	230	*/
	231	struct bfi_ioc_getattr_req_s {
	232	struct bfi_mhdr_s mh;
	233	union bfi_addr_u attr_addr;
	234	};
	235
	236	struct bfi_ioc_attr_s {
	237	wwn_t mfg_pwwn; /* Mfg port wwn */
	238	wwn_t mfg_nwwn; /* Mfg node wwn */
	239	mac_t mfg_mac; /* Mfg mac */
5a0adaed KG	240	u8 port_mode; /* bfi_port_mode */
5a0adaed KG	241	u8 rsvd_a;
a36c61f9 KG	242	wwn_t pwwn;
	243	wwn_t nwwn;
	244	mac_t mac; /* PBC or Mfg mac */
	245	u16 rsvd_b;
	246	mac_t fcoe_mac;
	247	u16 rsvd_c;
	248	char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
	249	u8 pcie_gen;
	250	u8 pcie_lanes_orig;
	251	u8 pcie_lanes;
	252	u8 rx_bbcredit; /* receive buffer credits */
	253	u32 adapter_prop; /* adapter properties */
	254	u16 maxfrsize; /* max receive frame size */
	255	char asic_rev;
10a07379	256	u8 rsvd_d;
a36c61f9 KG	257	char fw_version[BFA_VERSION_LEN];
	258	char optrom_version[BFA_VERSION_LEN];
	259	struct bfa_mfg_vpd_s vpd;
	260	u32 card_type; /* card type */
	261	};
	262
acdc79a6	263	/*
a36c61f9 KG	264	* BFI_IOC_I2H_GETATTR_REPLY message
	265	*/
	266	struct bfi_ioc_getattr_reply_s {
	267	struct bfi_mhdr_s mh; /* Common msg header */
	268	u8 status; /* cfg reply status */
	269	u8 rsvd[3];
	270	};
	271
acdc79a6	272	/*
a36c61f9 KG	273	* Firmware memory page offsets
	274	*/
	275	#define BFI_IOC_SMEM_PG0_CB (0x40)
	276	#define BFI_IOC_SMEM_PG0_CT (0x180)
	277
acdc79a6	278	/*
a36c61f9 KG	279	* Firmware statistic offset
	280	*/
	281	#define BFI_IOC_FWSTATS_OFF (0x6B40)
	282	#define BFI_IOC_FWSTATS_SZ (4096)
	283
acdc79a6	284	/*
a36c61f9 KG	285	* Firmware trace offset
	286	*/
	287	#define BFI_IOC_TRC_OFF (0x4b00)
	288	#define BFI_IOC_TRC_ENTS 256
	289
	290	#define BFI_IOC_FW_SIGNATURE (0xbfadbfad)
	291	#define BFI_IOC_MD5SUM_SZ 4
	292	struct bfi_ioc_image_hdr_s {
11189208 KG	293	u32 signature; /* constant signature */
	294	u8 asic_gen; /* asic generation */
	295	u8 asic_mode;
	296	u8 port0_mode; /* device mode for port 0 */
	297	u8 port1_mode; /* device mode for port 1 */
	298	u32 exec; /* exec vector */
	299	u32 bootenv; /* fimware boot env */
a36c61f9 KG	300	u32 rsvd_b[4];
	301	u32 md5sum[BFI_IOC_MD5SUM_SZ];
	302	};
	303
11189208 KG	304	#define BFI_FWBOOT_DEVMODE_OFF 4
	305	#define BFI_FWBOOT_TYPE_OFF 8
	306	#define BFI_FWBOOT_ENV_OFF 12
	307	#define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \
	308	(((u32)(__asic_gen)) << 24 \| \
	309	((u32)(__asic_mode)) << 16 \| \
	310	((u32)(__p0_mode)) << 8 \| \
	311	((u32)(__p1_mode)))
	312
	313	#define BFI_FWBOOT_TYPE_NORMAL 0
	314	#define BFI_FWBOOT_TYPE_MEMTEST 1
	315	#define BFI_FWBOOT_ENV_OS 0
	316
	317	enum bfi_port_mode {
	318	BFI_PORT_MODE_FC = 1,
	319	BFI_PORT_MODE_ETH = 2,
	320	};
	321
a36c61f9 KG	322	struct bfi_ioc_hbeat_s {
	323	struct bfi_mhdr_s mh; /* common msg header */
	324	u32 hb_count; /* current heart beat count */
	325	};
	326
acdc79a6	327	/*
a36c61f9 KG	328	* IOC hardware/firmware state
	329	*/
	330	enum bfi_ioc_state {
	331	BFI_IOC_UNINIT = 0, /* not initialized */
	332	BFI_IOC_INITING = 1, /* h/w is being initialized */
	333	BFI_IOC_HWINIT = 2, /* h/w is initialized */
	334	BFI_IOC_CFG = 3, /* IOC configuration in progress */
	335	BFI_IOC_OP = 4, /* IOC is operational */
	336	BFI_IOC_DISABLING = 5, /* IOC is being disabled */
	337	BFI_IOC_DISABLED = 6, /* IOC is disabled */
	338	BFI_IOC_CFG_DISABLED = 7, /* IOC is being disabled;transient */
	339	BFI_IOC_FAIL = 8, /* IOC heart-beat failure */
	340	BFI_IOC_MEMTEST = 9, /* IOC is doing memtest */
	341	};
	342
	343	#define BFI_IOC_ENDIAN_SIG 0x12345678
	344
	345	enum {
	346	BFI_ADAPTER_TYPE_FC = 0x01, /* FC adapters */
	347	BFI_ADAPTER_TYPE_MK = 0x0f0000, /* adapter type mask */
	348	BFI_ADAPTER_TYPE_SH = 16, /* adapter type shift */
	349	BFI_ADAPTER_NPORTS_MK = 0xff00, /* number of ports mask */
	350	BFI_ADAPTER_NPORTS_SH = 8, /* number of ports shift */
	351	BFI_ADAPTER_SPEED_MK = 0xff, /* adapter speed mask */
	352	BFI_ADAPTER_SPEED_SH = 0, /* adapter speed shift */
	353	BFI_ADAPTER_PROTO = 0x100000, /* prototype adapaters */
	354	BFI_ADAPTER_TTV = 0x200000, /* TTV debug capable */
	355	BFI_ADAPTER_UNSUPP = 0x400000, /* unknown adapter type */
	356	};
	357
	358	#define BFI_ADAPTER_GETP(__prop, __adap_prop) \
	359	(((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >> \
	360	BFI_ADAPTER_ ## __prop ## _SH)
	361	#define BFI_ADAPTER_SETP(__prop, __val) \
	362	((__val) << BFI_ADAPTER_ ## __prop ## _SH)
	363	#define BFI_ADAPTER_IS_PROTO(__adap_type) \
	364	((__adap_type) & BFI_ADAPTER_PROTO)
	365	#define BFI_ADAPTER_IS_TTV(__adap_type) \
	366	((__adap_type) & BFI_ADAPTER_TTV)
	367	#define BFI_ADAPTER_IS_UNSUPP(__adap_type) \
	368	((__adap_type) & BFI_ADAPTER_UNSUPP)
	369	#define BFI_ADAPTER_IS_SPECIAL(__adap_type) \
	370	((__adap_type) & (BFI_ADAPTER_TTV \| BFI_ADAPTER_PROTO \| \
	371	BFI_ADAPTER_UNSUPP))
	372
acdc79a6	373	/*
a36c61f9 KG	374	* BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages
	375	*/
	376	struct bfi_ioc_ctrl_req_s {
	377	struct bfi_mhdr_s mh;
d37779f8 KG	378	u16 clscode;
d37779f8 KG	379	u16 rsvd;
a36c61f9 KG	380	u32 tv_sec;
	381	};
	382	#define bfi_ioc_enable_req_t struct bfi_ioc_ctrl_req_s;
	383	#define bfi_ioc_disable_req_t struct bfi_ioc_ctrl_req_s;
	384
acdc79a6	385	/*
a36c61f9 KG	386	* BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages
	387	*/
	388	struct bfi_ioc_ctrl_reply_s {
	389	struct bfi_mhdr_s mh; /* Common msg header */
	390	u8 status; /* enable/disable status */
1a4d8e1b KG	391	u8 port_mode; /* bfa_mode_s */
	392	u8 cap_bm; /* capability bit mask */
	393	u8 rsvd;
a36c61f9 KG	394	};
	395	#define bfi_ioc_enable_reply_t struct bfi_ioc_ctrl_reply_s;
	396	#define bfi_ioc_disable_reply_t struct bfi_ioc_ctrl_reply_s;
	397
	398	#define BFI_IOC_MSGSZ 8
acdc79a6	399	/*
a36c61f9 KG	400	* H2I Messages
	401	*/
	402	union bfi_ioc_h2i_msg_u {
	403	struct bfi_mhdr_s mh;
	404	struct bfi_ioc_ctrl_req_s enable_req;
	405	struct bfi_ioc_ctrl_req_s disable_req;
	406	struct bfi_ioc_getattr_req_s getattr_req;
	407	u32 mboxmsg[BFI_IOC_MSGSZ];
	408	};
	409
acdc79a6	410	/*
a36c61f9 KG	411	* I2H Messages
	412	*/
	413	union bfi_ioc_i2h_msg_u {
	414	struct bfi_mhdr_s mh;
1a4d8e1b	415	struct bfi_ioc_ctrl_reply_s fw_event;
a36c61f9 KG	416	u32 mboxmsg[BFI_IOC_MSGSZ];
	417	};
	418
	419
acdc79a6	420	/*
a36c61f9 KG	421	*----------------------------------------------------------------------
	422	* PBC
	423	*----------------------------------------------------------------------
	424	*/
	425
	426	#define BFI_PBC_MAX_BLUNS 8
	427	#define BFI_PBC_MAX_VPORTS 16
43ffdf4d	428	#define BFI_PBC_PORT_DISABLED 2
a36c61f9	429
acdc79a6	430	/*
a36c61f9 KG	431	* PBC boot lun configuration
	432	*/
	433	struct bfi_pbc_blun_s {
	434	wwn_t tgt_pwwn;
f314878a	435	struct scsi_lun tgt_lun;
a36c61f9 KG	436	};
a36c61f9 KG	437
acdc79a6	438	/*
a36c61f9 KG	439	* PBC virtual port configuration
	440	*/
	441	struct bfi_pbc_vport_s {
	442	wwn_t vp_pwwn;
	443	wwn_t vp_nwwn;
	444	};
	445
acdc79a6	446	/*
a36c61f9 KG	447	* BFI pre-boot configuration information
	448	*/
	449	struct bfi_pbc_s {
	450	u8 port_enabled;
	451	u8 boot_enabled;
	452	u8 nbluns;
	453	u8 nvports;
	454	u8 port_speed;
	455	u8 rsvd_a;
	456	u16 hss;
	457	wwn_t pbc_pwwn;
	458	wwn_t pbc_nwwn;
	459	struct bfi_pbc_blun_s blun[BFI_PBC_MAX_BLUNS];
	460	struct bfi_pbc_vport_s vport[BFI_PBC_MAX_VPORTS];
	461	};
	462
acdc79a6	463	/*
a36c61f9 KG	464	*----------------------------------------------------------------------
	465	* MSGQ
	466	*----------------------------------------------------------------------
	467	*/
	468	#define BFI_MSGQ_FULL(_q) (((_q->pi + 1) % _q->q_depth) == _q->ci)
	469	#define BFI_MSGQ_EMPTY(_q) (_q->pi == _q->ci)
	470	#define BFI_MSGQ_UPDATE_CI(_q) (_q->ci = (_q->ci + 1) % _q->q_depth)
	471	#define BFI_MSGQ_UPDATE_PI(_q) (_q->pi = (_q->pi + 1) % _q->q_depth)
	472
	473	/* q_depth must be power of 2 */
	474	#define BFI_MSGQ_FREE_CNT(_q) ((_q->ci - _q->pi - 1) & (_q->q_depth - 1))
	475
	476	enum bfi_msgq_h2i_msgs_e {
	477	BFI_MSGQ_H2I_INIT_REQ = 1,
	478	BFI_MSGQ_H2I_DOORBELL = 2,
	479	BFI_MSGQ_H2I_SHUTDOWN = 3,
	480	};
	481
	482	enum bfi_msgq_i2h_msgs_e {
	483	BFI_MSGQ_I2H_INIT_RSP = 1,
	484	BFI_MSGQ_I2H_DOORBELL = 2,
	485	};
	486
	487
	488	/* Messages(commands/responsed/AENS will have the following header */
	489	struct bfi_msgq_mhdr_s {
	490	u8 msg_class;
	491	u8 msg_id;
	492	u16 msg_token;
	493	u16 num_entries;
	494	u8 enet_id;
	495	u8 rsvd[1];
	496	};
	497
	498	#define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do { \
	499	(_mh).msg_class = (_mc); \
	500	(_mh).msg_id = (_mid); \
	501	(_mh).msg_token = (_tok); \
	502	(_mh).enet_id = (_enet_id); \
	503	} while (0)
	504
	505	/*
	506	* Mailbox for messaging interface
	507	*
	508	*/
	509	#define BFI_MSGQ_CMD_ENTRY_SIZE (64) /* TBD */
	510	#define BFI_MSGQ_RSP_ENTRY_SIZE (64) /* TBD */
	511	#define BFI_MSGQ_MSG_SIZE_MAX (2048) /* TBD */
	512
	513	struct bfi_msgq_s {
	514	union bfi_addr_u addr;
	515	u16 q_depth; /* Total num of entries in the queue */
	516	u8 rsvd[2];
	517	};
	518
	519	/* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */
	520	struct bfi_msgq_cfg_req_s {
	521	struct bfi_mhdr_s mh;
	522	struct bfi_msgq_s cmdq;
	523	struct bfi_msgq_s rspq;
	524	};
	525
	526	/* BFI_ENET_MSGQ_CFG_RSP */
	527	struct bfi_msgq_cfg_rsp_s {
528	struct bfi_mhdr_s mh;
529	u8 cmd_status;
530	u8 rsvd[3];
531	};
532
533
534	/* BFI_MSGQ_H2I_DOORBELL */
535	struct bfi_msgq_h2i_db_s {
536	struct bfi_mhdr_s mh;
537	u16 cmdq_pi;
538	u16 rspq_ci;
539	};
540
541	/* BFI_MSGQ_I2H_DOORBELL */
542	struct bfi_msgq_i2h_db_s {
543	struct bfi_mhdr_s mh;
544	u16 rspq_pi;
545	u16 cmdq_ci;
546	};
547
548	#pragma pack()
549
550	/* BFI port specific */
551	#pragma pack(1)
552
553	enum bfi_port_h2i {
554	BFI_PORT_H2I_ENABLE_REQ = (1),
555	BFI_PORT_H2I_DISABLE_REQ = (2),
556	BFI_PORT_H2I_GET_STATS_REQ = (3),
557	BFI_PORT_H2I_CLEAR_STATS_REQ = (4),
558	};
559
560	enum bfi_port_i2h {
561	BFI_PORT_I2H_ENABLE_RSP = BFA_I2HM(1),
562	BFI_PORT_I2H_DISABLE_RSP = BFA_I2HM(2),
563	BFI_PORT_I2H_GET_STATS_RSP = BFA_I2HM(3),
564	BFI_PORT_I2H_CLEAR_STATS_RSP = BFA_I2HM(4),
565	};
566
acdc79a6	567	/*
a36c61f9 KG	568	* Generic REQ type
	569	*/
	570	struct bfi_port_generic_req_s {
	571	struct bfi_mhdr_s mh; /* msg header */
	572	u32 msgtag; /* msgtag for reply */
	573	u32 rsvd;
	574	};
	575
acdc79a6	576	/*
a36c61f9 KG	577	* Generic RSP type
	578	*/
	579	struct bfi_port_generic_rsp_s {
	580	struct bfi_mhdr_s mh; /* common msg header */
	581	u8 status; /* port enable status */
	582	u8 rsvd[3];
	583	u32 msgtag; /* msgtag for reply */
	584	};
	585
acdc79a6	586	/*
a36c61f9 KG	587	* BFI_PORT_H2I_GET_STATS_REQ
	588	*/
	589	struct bfi_port_get_stats_req_s {
	590	struct bfi_mhdr_s mh; /* common msg header */
	591	union bfi_addr_u dma_addr;
	592	};
	593
	594	union bfi_port_h2i_msg_u {
	595	struct bfi_mhdr_s mh;
	596	struct bfi_port_generic_req_s enable_req;
	597	struct bfi_port_generic_req_s disable_req;
	598	struct bfi_port_get_stats_req_s getstats_req;
	599	struct bfi_port_generic_req_s clearstats_req;
	600	};
	601
	602	union bfi_port_i2h_msg_u {
	603	struct bfi_mhdr_s mh;
	604	struct bfi_port_generic_rsp_s enable_rsp;
	605	struct bfi_port_generic_rsp_s disable_rsp;
	606	struct bfi_port_generic_rsp_s getstats_rsp;
	607	struct bfi_port_generic_rsp_s clearstats_rsp;
	608	};
	609
1a4d8e1b KG	610	/*
	611	*----------------------------------------------------------------------
	612	* ABLK
	613	*----------------------------------------------------------------------
	614	*/
	615	enum bfi_ablk_h2i_msgs_e {
	616	BFI_ABLK_H2I_QUERY = 1,
	617	BFI_ABLK_H2I_ADPT_CONFIG = 2,
	618	BFI_ABLK_H2I_PORT_CONFIG = 3,
	619	BFI_ABLK_H2I_PF_CREATE = 4,
	620	BFI_ABLK_H2I_PF_DELETE = 5,
	621	BFI_ABLK_H2I_PF_UPDATE = 6,
	622	BFI_ABLK_H2I_OPTROM_ENABLE = 7,
	623	BFI_ABLK_H2I_OPTROM_DISABLE = 8,
	624	};
	625
	626	enum bfi_ablk_i2h_msgs_e {
	627	BFI_ABLK_I2H_QUERY = BFA_I2HM(BFI_ABLK_H2I_QUERY),
	628	BFI_ABLK_I2H_ADPT_CONFIG = BFA_I2HM(BFI_ABLK_H2I_ADPT_CONFIG),
	629	BFI_ABLK_I2H_PORT_CONFIG = BFA_I2HM(BFI_ABLK_H2I_PORT_CONFIG),
	630	BFI_ABLK_I2H_PF_CREATE = BFA_I2HM(BFI_ABLK_H2I_PF_CREATE),
	631	BFI_ABLK_I2H_PF_DELETE = BFA_I2HM(BFI_ABLK_H2I_PF_DELETE),
	632	BFI_ABLK_I2H_PF_UPDATE = BFA_I2HM(BFI_ABLK_H2I_PF_UPDATE),
	633	BFI_ABLK_I2H_OPTROM_ENABLE = BFA_I2HM(BFI_ABLK_H2I_OPTROM_ENABLE),
	634	BFI_ABLK_I2H_OPTROM_DISABLE = BFA_I2HM(BFI_ABLK_H2I_OPTROM_DISABLE),
	635	};
	636
	637	/* BFI_ABLK_H2I_QUERY */
	638	struct bfi_ablk_h2i_query_s {
	639	struct bfi_mhdr_s mh;
	640	union bfi_addr_u addr;
	641	};
	642
	643	/* BFI_ABL_H2I_ADPT_CONFIG, BFI_ABLK_H2I_PORT_CONFIG */
	644	struct bfi_ablk_h2i_cfg_req_s {
	645	struct bfi_mhdr_s mh;
	646	u8 mode;
	647	u8 port;
	648	u8 max_pf;
	649	u8 max_vf;
	650	};
	651
	652	/*
	653	* BFI_ABLK_H2I_PF_CREATE, BFI_ABLK_H2I_PF_DELETE,
	654	*/
	655	struct bfi_ablk_h2i_pf_req_s {
	656	struct bfi_mhdr_s mh;
	657	u8 pcifn;
	658	u8 port;
	659	u16 pers;
	660	u32 bw;
	661	};
	662
	663	/* BFI_ABLK_H2I_OPTROM_ENABLE, BFI_ABLK_H2I_OPTROM_DISABLE */
	664	struct bfi_ablk_h2i_optrom_s {
	665	struct bfi_mhdr_s mh;
	666	};
	667
	668	/*
	669	* BFI_ABLK_I2H_QUERY
	670	* BFI_ABLK_I2H_PORT_CONFIG
	671	* BFI_ABLK_I2H_PF_CREATE
	672	* BFI_ABLK_I2H_PF_DELETE
	673	* BFI_ABLK_I2H_PF_UPDATE
674	* BFI_ABLK_I2H_OPTROM_ENABLE
675	* BFI_ABLK_I2H_OPTROM_DISABLE
676	*/
677	struct bfi_ablk_i2h_rsp_s {
678	struct bfi_mhdr_s mh;
679	u8 status;
680	u8 pcifn;
681	u8 port_mode;
682	};
683
a36c61f9 KG	684	#pragma pack()
	685
	686	#endif /* __BFI_H__ */