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1da177e4 LT |
1 | /* blz1230.c: Driver for Blizzard 1230 SCSI IV Controller. |
2 | * | |
3 | * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk) | |
4 | * | |
5 | * This driver is based on the CyberStorm driver, hence the occasional | |
6 | * reference to CyberStorm. | |
7 | */ | |
8 | ||
9 | /* TODO: | |
10 | * | |
11 | * 1) Figure out how to make a cleaner merge with the sparc driver with regard | |
12 | * to the caches and the Sparc MMU mapping. | |
13 | * 2) Make as few routines required outside the generic driver. A lot of the | |
14 | * routines in this file used to be inline! | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/blkdev.h> | |
26 | #include <linux/proc_fs.h> | |
27 | #include <linux/stat.h> | |
28 | #include <linux/interrupt.h> | |
29 | ||
30 | #include "scsi.h" | |
31 | #include <scsi/scsi_host.h> | |
32 | #include "NCR53C9x.h" | |
33 | ||
34 | #include <linux/zorro.h> | |
35 | #include <asm/irq.h> | |
36 | #include <asm/amigaints.h> | |
37 | #include <asm/amigahw.h> | |
38 | ||
39 | #include <asm/pgtable.h> | |
40 | ||
41 | #define MKIV 1 | |
42 | ||
43 | /* The controller registers can be found in the Z2 config area at these | |
44 | * offsets: | |
45 | */ | |
46 | #define BLZ1230_ESP_ADDR 0x8000 | |
47 | #define BLZ1230_DMA_ADDR 0x10000 | |
48 | #define BLZ1230II_ESP_ADDR 0x10000 | |
49 | #define BLZ1230II_DMA_ADDR 0x10021 | |
50 | ||
51 | ||
52 | /* The Blizzard 1230 DMA interface | |
53 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
54 | * Only two things can be programmed in the Blizzard DMA: | |
55 | * 1) The data direction is controlled by the status of bit 31 (1 = write) | |
56 | * 2) The source/dest address (word aligned, shifted one right) in bits 30-0 | |
57 | * | |
58 | * Program DMA by first latching the highest byte of the address/direction | |
59 | * (i.e. bits 31-24 of the long word constructed as described in steps 1+2 | |
60 | * above). Then write each byte of the address/direction (starting with the | |
61 | * top byte, working down) to the DMA address register. | |
62 | * | |
63 | * Figure out interrupt status by reading the ESP status byte. | |
64 | */ | |
65 | struct blz1230_dma_registers { | |
66 | volatile unsigned char dma_addr; /* DMA address [0x0000] */ | |
67 | unsigned char dmapad2[0x7fff]; | |
68 | volatile unsigned char dma_latch; /* DMA latch [0x8000] */ | |
69 | }; | |
70 | ||
71 | struct blz1230II_dma_registers { | |
72 | volatile unsigned char dma_addr; /* DMA address [0x0000] */ | |
73 | unsigned char dmapad2[0xf]; | |
74 | volatile unsigned char dma_latch; /* DMA latch [0x0010] */ | |
75 | }; | |
76 | ||
77 | #define BLZ1230_DMA_WRITE 0x80000000 | |
78 | ||
79 | static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count); | |
80 | static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp); | |
81 | static void dma_dump_state(struct NCR_ESP *esp); | |
82 | static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length); | |
83 | static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length); | |
84 | static void dma_ints_off(struct NCR_ESP *esp); | |
85 | static void dma_ints_on(struct NCR_ESP *esp); | |
86 | static int dma_irq_p(struct NCR_ESP *esp); | |
87 | static int dma_ports_p(struct NCR_ESP *esp); | |
88 | static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write); | |
89 | ||
90 | static volatile unsigned char cmd_buffer[16]; | |
91 | /* This is where all commands are put | |
92 | * before they are transferred to the ESP chip | |
93 | * via PIO. | |
94 | */ | |
95 | ||
96 | /***************************************************************** Detection */ | |
d0be4a7d | 97 | int __init blz1230_esp_detect(struct scsi_host_template *tpnt) |
1da177e4 LT |
98 | { |
99 | struct NCR_ESP *esp; | |
100 | struct zorro_dev *z = NULL; | |
101 | unsigned long address; | |
102 | struct ESP_regs *eregs; | |
103 | unsigned long board; | |
104 | ||
105 | #if MKIV | |
106 | #define REAL_BLZ1230_ID ZORRO_PROD_PHASE5_BLIZZARD_1230_IV_1260 | |
107 | #define REAL_BLZ1230_ESP_ADDR BLZ1230_ESP_ADDR | |
108 | #define REAL_BLZ1230_DMA_ADDR BLZ1230_DMA_ADDR | |
109 | #else | |
110 | #define REAL_BLZ1230_ID ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060 | |
111 | #define REAL_BLZ1230_ESP_ADDR BLZ1230II_ESP_ADDR | |
112 | #define REAL_BLZ1230_DMA_ADDR BLZ1230II_DMA_ADDR | |
113 | #endif | |
114 | ||
115 | if ((z = zorro_find_device(REAL_BLZ1230_ID, z))) { | |
116 | board = z->resource.start; | |
117 | if (request_mem_region(board+REAL_BLZ1230_ESP_ADDR, | |
118 | sizeof(struct ESP_regs), "NCR53C9x")) { | |
119 | /* Do some magic to figure out if the blizzard is | |
120 | * equipped with a SCSI controller | |
121 | */ | |
122 | address = ZTWO_VADDR(board); | |
123 | eregs = (struct ESP_regs *)(address + REAL_BLZ1230_ESP_ADDR); | |
4df4db5c MR |
124 | esp = esp_allocate(tpnt, (void *)board + REAL_BLZ1230_ESP_ADDR, |
125 | 0); | |
1da177e4 LT |
126 | |
127 | esp_write(eregs->esp_cfg1, (ESP_CONFIG1_PENABLE | 7)); | |
128 | udelay(5); | |
129 | if(esp_read(eregs->esp_cfg1) != (ESP_CONFIG1_PENABLE | 7)) | |
130 | goto err_out; | |
131 | ||
132 | /* Do command transfer with programmed I/O */ | |
133 | esp->do_pio_cmds = 1; | |
134 | ||
135 | /* Required functions */ | |
136 | esp->dma_bytes_sent = &dma_bytes_sent; | |
137 | esp->dma_can_transfer = &dma_can_transfer; | |
138 | esp->dma_dump_state = &dma_dump_state; | |
139 | esp->dma_init_read = &dma_init_read; | |
140 | esp->dma_init_write = &dma_init_write; | |
141 | esp->dma_ints_off = &dma_ints_off; | |
142 | esp->dma_ints_on = &dma_ints_on; | |
143 | esp->dma_irq_p = &dma_irq_p; | |
144 | esp->dma_ports_p = &dma_ports_p; | |
145 | esp->dma_setup = &dma_setup; | |
146 | ||
147 | /* Optional functions */ | |
148 | esp->dma_barrier = 0; | |
149 | esp->dma_drain = 0; | |
150 | esp->dma_invalidate = 0; | |
151 | esp->dma_irq_entry = 0; | |
152 | esp->dma_irq_exit = 0; | |
153 | esp->dma_led_on = 0; | |
154 | esp->dma_led_off = 0; | |
155 | esp->dma_poll = 0; | |
156 | esp->dma_reset = 0; | |
157 | ||
158 | /* SCSI chip speed */ | |
159 | esp->cfreq = 40000000; | |
160 | ||
161 | /* The DMA registers on the Blizzard are mapped | |
162 | * relative to the device (i.e. in the same Zorro | |
163 | * I/O block). | |
164 | */ | |
165 | esp->dregs = (void *)(address + REAL_BLZ1230_DMA_ADDR); | |
166 | ||
167 | /* ESP register base */ | |
168 | esp->eregs = eregs; | |
169 | ||
170 | /* Set the command buffer */ | |
171 | esp->esp_command = cmd_buffer; | |
172 | esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer); | |
173 | ||
174 | esp->irq = IRQ_AMIGA_PORTS; | |
175 | esp->slot = board+REAL_BLZ1230_ESP_ADDR; | |
1d6f359a | 176 | if (request_irq(IRQ_AMIGA_PORTS, esp_intr, IRQF_SHARED, |
1da177e4 LT |
177 | "Blizzard 1230 SCSI IV", esp->ehost)) |
178 | goto err_out; | |
179 | ||
180 | /* Figure out our scsi ID on the bus */ | |
181 | esp->scsi_id = 7; | |
182 | ||
183 | /* We don't have a differential SCSI-bus. */ | |
184 | esp->diff = 0; | |
185 | ||
186 | esp_initialize(esp); | |
187 | ||
188 | printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use); | |
189 | esps_running = esps_in_use; | |
190 | return esps_in_use; | |
191 | } | |
192 | } | |
193 | return 0; | |
194 | ||
195 | err_out: | |
196 | scsi_unregister(esp->ehost); | |
197 | esp_deallocate(esp); | |
198 | release_mem_region(board+REAL_BLZ1230_ESP_ADDR, | |
199 | sizeof(struct ESP_regs)); | |
200 | return 0; | |
201 | } | |
202 | ||
203 | /************************************************************* DMA Functions */ | |
204 | static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count) | |
205 | { | |
206 | /* Since the Blizzard DMA is fully dedicated to the ESP chip, | |
207 | * the number of bytes sent (to the ESP chip) equals the number | |
208 | * of bytes in the FIFO - there is no buffering in the DMA controller. | |
209 | * XXXX Do I read this right? It is from host to ESP, right? | |
210 | */ | |
211 | return fifo_count; | |
212 | } | |
213 | ||
214 | static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp) | |
215 | { | |
216 | /* I don't think there's any limit on the Blizzard DMA. So we use what | |
217 | * the ESP chip can handle (24 bit). | |
218 | */ | |
219 | unsigned long sz = sp->SCp.this_residual; | |
220 | if(sz > 0x1000000) | |
221 | sz = 0x1000000; | |
222 | return sz; | |
223 | } | |
224 | ||
225 | static void dma_dump_state(struct NCR_ESP *esp) | |
226 | { | |
227 | ESPLOG(("intreq:<%04x>, intena:<%04x>\n", | |
b4290a23 | 228 | amiga_custom.intreqr, amiga_custom.intenar)); |
1da177e4 LT |
229 | } |
230 | ||
231 | void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length) | |
232 | { | |
233 | #if MKIV | |
234 | struct blz1230_dma_registers *dregs = | |
235 | (struct blz1230_dma_registers *) (esp->dregs); | |
236 | #else | |
237 | struct blz1230II_dma_registers *dregs = | |
238 | (struct blz1230II_dma_registers *) (esp->dregs); | |
239 | #endif | |
240 | ||
241 | cache_clear(addr, length); | |
242 | ||
243 | addr >>= 1; | |
244 | addr &= ~(BLZ1230_DMA_WRITE); | |
245 | ||
246 | /* First set latch */ | |
247 | dregs->dma_latch = (addr >> 24) & 0xff; | |
248 | ||
249 | /* Then pump the address to the DMA address register */ | |
250 | #if MKIV | |
251 | dregs->dma_addr = (addr >> 24) & 0xff; | |
252 | #endif | |
253 | dregs->dma_addr = (addr >> 16) & 0xff; | |
254 | dregs->dma_addr = (addr >> 8) & 0xff; | |
255 | dregs->dma_addr = (addr ) & 0xff; | |
256 | } | |
257 | ||
258 | void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length) | |
259 | { | |
260 | #if MKIV | |
261 | struct blz1230_dma_registers *dregs = | |
262 | (struct blz1230_dma_registers *) (esp->dregs); | |
263 | #else | |
264 | struct blz1230II_dma_registers *dregs = | |
265 | (struct blz1230II_dma_registers *) (esp->dregs); | |
266 | #endif | |
267 | ||
268 | cache_push(addr, length); | |
269 | ||
270 | addr >>= 1; | |
271 | addr |= BLZ1230_DMA_WRITE; | |
272 | ||
273 | /* First set latch */ | |
274 | dregs->dma_latch = (addr >> 24) & 0xff; | |
275 | ||
276 | /* Then pump the address to the DMA address register */ | |
277 | #if MKIV | |
278 | dregs->dma_addr = (addr >> 24) & 0xff; | |
279 | #endif | |
280 | dregs->dma_addr = (addr >> 16) & 0xff; | |
281 | dregs->dma_addr = (addr >> 8) & 0xff; | |
282 | dregs->dma_addr = (addr ) & 0xff; | |
283 | } | |
284 | ||
285 | static void dma_ints_off(struct NCR_ESP *esp) | |
286 | { | |
287 | disable_irq(esp->irq); | |
288 | } | |
289 | ||
290 | static void dma_ints_on(struct NCR_ESP *esp) | |
291 | { | |
292 | enable_irq(esp->irq); | |
293 | } | |
294 | ||
295 | static int dma_irq_p(struct NCR_ESP *esp) | |
296 | { | |
297 | return (esp_read(esp->eregs->esp_status) & ESP_STAT_INTR); | |
298 | } | |
299 | ||
300 | static int dma_ports_p(struct NCR_ESP *esp) | |
301 | { | |
b4290a23 | 302 | return ((amiga_custom.intenar) & IF_PORTS); |
1da177e4 LT |
303 | } |
304 | ||
305 | static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write) | |
306 | { | |
307 | /* On the Sparc, DMA_ST_WRITE means "move data from device to memory" | |
308 | * so when (write) is true, it actually means READ! | |
309 | */ | |
310 | if(write){ | |
311 | dma_init_read(esp, addr, count); | |
312 | } else { | |
313 | dma_init_write(esp, addr, count); | |
314 | } | |
315 | } | |
316 | ||
317 | #define HOSTS_C | |
318 | ||
319 | int blz1230_esp_release(struct Scsi_Host *instance) | |
320 | { | |
321 | #ifdef MODULE | |
322 | unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev; | |
323 | esp_deallocate((struct NCR_ESP *)instance->hostdata); | |
324 | esp_release(); | |
325 | release_mem_region(address, sizeof(struct ESP_regs)); | |
326 | free_irq(IRQ_AMIGA_PORTS, esp_intr); | |
327 | #endif | |
328 | return 1; | |
329 | } | |
330 | ||
331 | ||
d0be4a7d | 332 | static struct scsi_host_template driver_template = { |
1da177e4 LT |
333 | .proc_name = "esp-blz1230", |
334 | .proc_info = esp_proc_info, | |
335 | .name = "Blizzard1230 SCSI IV", | |
336 | .detect = blz1230_esp_detect, | |
337 | .slave_alloc = esp_slave_alloc, | |
338 | .slave_destroy = esp_slave_destroy, | |
339 | .release = blz1230_esp_release, | |
340 | .queuecommand = esp_queue, | |
341 | .eh_abort_handler = esp_abort, | |
342 | .eh_bus_reset_handler = esp_reset, | |
343 | .can_queue = 7, | |
344 | .this_id = 7, | |
345 | .sg_tablesize = SG_ALL, | |
346 | .cmd_per_lun = 1, | |
347 | .use_clustering = ENABLE_CLUSTERING | |
348 | }; | |
349 | ||
350 | ||
351 | #include "scsi_module.c" | |
352 | ||
353 | MODULE_LICENSE("GPL"); |