[mirror_ubuntu-hirsute-kernel.git] / drivers / scsi / cpqfcTSchip.h

/* Copyright(c) 2000, Compaq Computer Corporation 
 * Fibre Channel Host Bus Adapter 
 * 64-bit, 66MHz PCI 
 * Originally developed and tested on:
 * (front): [chip] Tachyon TS HPFC-5166A/1.2  L2C1090 ...
 *          SP# P225CXCBFIEL6T, Rev XC
 *          SP# 161290-001, Rev XD
 * (back): Board No. 010008-001 A/W Rev X5, FAB REV X5
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2, or (at your option) any
 * later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 * Written by Don Zimmerman
*/
#ifndef CPQFCTSCHIP_H
#define CPQFCTSCHIP_H
#ifndef TACHYON_CHIP_INC

// FC-PH (Physical) specification levels for Login payloads
// NOTE: These are NOT strictly complied with by any FC vendors

#define FC_PH42			0x08
#define FC_PH43			0x09
#define FC_PH3			0x20

#define TACHLITE_TS_RX_SIZE     1024  // max inbound frame size
// "I" prefix is for Include

#define IVENDID    0x00  // word
#define IDEVID     0x02
#define ITLCFGCMD 0x04
#define IMEMBASE   0x18    // Tachyon
#define ITLMEMBASE   0x1C  // Tachlite
#define IIOBASEL   0x10    // Tachyon I/O base address, lower 256 bytes
#define IIOBASEU   0x14    // Tachyon I/O base address, upper 256 bytes
#define ITLIOBASEL   0x14  // TachLite I/O base address, lower 256 bytes
#define ITLIOBASEU   0x18  // TachLite I/O base address, upper 256 bytes
#define ITLRAMBASE   0x20  // TL on-board RAM start
#define ISROMBASE  0x24
#define IROMBASE   0x30

#define ICFGCMD    0x04    // PCI config - PCI config access (word)
#define ICFGSTAT   0x06    // PCI status (R - word)
#define IRCTR_WCTR 0x1F2   // ROM control / pre-fetch wait counter
#define IPCIMCTR   0x1F3   // PCI master control register
#define IINTPEND   0x1FD   // Interrupt pending (I/O Upper - Tachyon & TL)
#define IINTEN     0x1FE   // Interrupt enable  (I/O Upper - Tachyon & TL)
#define IINTSTAT   0x1FF   // Interrupt status  (I/O Upper - Tachyon & TL)

#define IMQ_BASE            0x80
#define IMQ_LENGTH          0x84
#define IMQ_CONSUMER_INDEX  0x88
#define IMQ_PRODUCER_INDEX  0x8C   // Tach copies its INDX to bits 0-7 of value

/*
// IOBASE UPPER
#define SFSBQ_BASE            0x00   // single-frame sequences
#define SFSBQ_LENGTH          0x04
#define SFSBQ_PRODUCER_INDEX  0x08
#define SFSBQ_CONSUMER_INDEX  0x0C   // (R)
#define SFS_BUFFER_LENGTH     0X10
                              // SCSI-FCP hardware assists
#define SEST_BASE             0x40   // SSCI Exchange State Table
#define SEST_LENGTH           0x44
#define SCSI_BUFFER_LENGTH    0x48
#define SEST_LINKED_LIST      0x4C

#define TACHYON_My_ID         0x6C
#define TACHYON_CONFIGURATION 0x84   // (R/W) reset val 2
#define TACHYON_CONTROL       0x88
#define TACHYON_STATUS        0x8C   // (R)
#define TACHYON_FLUSH_SEST    0x90   // (R/W)
#define TACHYON_EE_CREDIT_TMR 0x94   // (R)
#define TACHYON_BB_CREDIT_TMR 0x98   // (R)
#define TACHYON_RCV_FRAME_ERR 0x9C   // (R)
#define FRAME_MANAGER_CONFIG  0xC0   // (R/W)
#define FRAME_MANAGER_CONTROL 0xC4
#define FRAME_MANAGER_STATUS  0xC8   // (R)
#define FRAME_MANAGER_ED_TOV  0xCC
#define FRAME_MANAGER_LINK_ERR1 0xD0   // (R)
#define FRAME_MANAGER_LINK_ERR2 0xD4   // (R)
#define FRAME_MANAGER_TIMEOUT2  0xD8   // (W)
#define FRAME_MANAGER_BB_CREDIT 0xDC   // (R)
#define FRAME_MANAGER_WWN_HI    0xE0   // (R/W)
#define FRAME_MANAGER_WWN_LO    0xE4   // (R/W)
#define FRAME_MANAGER_RCV_AL_PA 0xE8   // (R)
#define FRAME_MANAGER_PRIMITIVE 0xEC   // {K28.5} byte1 byte2 byte3
*/
		    
#define TL_MEM_ERQ_BASE                    0x0 //ERQ Base
#define TL_IO_ERQ_BASE                     0x0 //ERQ base

#define TL_MEM_ERQ_LENGTH                  0x4 //ERQ Length
#define TL_IO_ERQ_LENGTH                   0x4 //ERQ Length

#define TL_MEM_ERQ_PRODUCER_INDEX          0x8 //ERQ Producer Index  register
#define TL_IO_ERQ_PRODUCER_INDEX           0x8 //ERQ Producer Index  register

#define TL_MEM_ERQ_CONSUMER_INDEX_ADR 0xC //ERQ Consumer Index address register
#define TL_IO_ERQ_CONSUMER_INDEX_ADR  0xC //ERQ Consumer Index address register

#define TL_MEM_ERQ_CONSUMER_INDEX     0xC //ERQ Consumer Index 
#define TL_IO_ERQ_CONSUMER_INDEX      0xC //ERQ Consumer Index 

#define TL_MEM_SFQ_BASE               0x50 //SFQ Base
#define TL_IO_SFQ_BASE                0x50 //SFQ base

#define TL_MEM_SFQ_LENGTH             0x54 //SFQ Length
#define TL_IO_SFQ_LENGTH              0x54 //SFQ Length

#define TL_MEM_SFQ_CONSUMER_INDEX     0x58 //SFQ Consumer Index
#define TL_IO_SFQ_CONSUMER_INDEX      0x58 //SFQ Consumer Index

#define TL_MEM_IMQ_BASE               0x80 //IMQ Base
#define TL_IO_IMQ_BASE                0x80 //IMQ base

#define TL_MEM_IMQ_LENGTH             0x84 //IMQ Length
#define TL_IO_IMQ_LENGTH              0x84 //IMQ Length

#define TL_MEM_IMQ_CONSUMER_INDEX     0x88 //IMQ Consumer Index
#define TL_IO_IMQ_CONSUMER_INDEX      0x88 //IMQ Consumer Index

#define TL_MEM_IMQ_PRODUCER_INDEX_ADR 0x8C //IMQ Producer Index address register
#define TL_IO_IMQ_PRODUCER_INDEX_ADR  0x8C //IMQ Producer Index address register

#define TL_MEM_SEST_BASE              0x140 //SFQ Base
#define TL_IO_SEST_BASE               0x40 //SFQ base

#define TL_MEM_SEST_LENGTH            0x144 //SFQ Length
#define TL_IO_SEST_LENGTH             0x44 //SFQ Length

#define TL_MEM_SEST_LINKED_LIST       0x14C

#define TL_MEM_SEST_SG_PAGE           0x168  // Extended Scatter/Gather page size

#define TL_MEM_TACH_My_ID             0x16C
#define TL_IO_TACH_My_ID              0x6C //My AL_PA ID

#define TL_MEM_TACH_CONFIG            0x184 //Tachlite Configuration register
#define TL_IO_CONFIG                  0x84 //Tachlite Configuration register

#define TL_MEM_TACH_CONTROL           0x188 //Tachlite Control register
#define TL_IO_CTR                     0x88 //Tachlite Control register

#define TL_MEM_TACH_STATUS            0x18C //Tachlite Status register
#define TL_IO_STAT                    0x8C //Tachlite Status register

#define TL_MEM_FM_CONFIG        0x1C0 //Frame Manager Configuration register
#define TL_IO_FM_CONFIG         0xC0 //Frame Manager Configuration register

#define TL_MEM_FM_CONTROL       0x1C4 //Frame Manager Control
#define TL_IO_FM_CTL            0xC4 //Frame Manager Control

#define TL_MEM_FM_STATUS        0x1C8 //Frame Manager Status
#define TL_IO_FM_STAT           0xC8 //Frame Manager Status

#define TL_MEM_FM_LINK_STAT1    0x1D0 //Frame Manager Link Status 1
#define TL_IO_FM_LINK_STAT1     0xD0 //Frame Manager Link Status 1

#define TL_MEM_FM_LINK_STAT2    0x1D4 //Frame Manager Link Status 2
#define TL_IO_FM_LINK_STAT2     0xD4 //Frame Manager Link Status 2

#define TL_MEM_FM_TIMEOUT2      0x1D8   // (W)

#define TL_MEM_FM_BB_CREDIT0    0x1DC

#define TL_MEM_FM_WWN_HI        0x1E0 //Frame Manager World Wide Name High
#define TL_IO_FM_WWN_HI         0xE0 //Frame Manager World Wide Name High

#define TL_MEM_FM_WWN_LO        0x1E4 //Frame Manager World Wide Name LOW
#define TL_IO_FM_WWN_LO         0xE4 //Frame Manager World Wide Name Low

#define TL_MEM_FM_RCV_AL_PA     0x1E8 //Frame Manager AL_PA Received register
#define TL_IO_FM_ALPA           0xE8 //Frame Manager AL_PA Received register

#define TL_MEM_FM_ED_TOV           0x1CC

#define TL_IO_ROMCTR            0xFA //TL PCI ROM Control Register
#define TL_IO_PCIMCTR           0xFB //TL PCI Master Control Register
#define TL_IO_SOFTRST           0xFC //Tachlite Configuration register
#define TL_MEM_SOFTRST          0x1FC //Tachlite Configuration register

// completion message types (bit 8 set means Interrupt generated)
// CM_Type
#define OUTBOUND_COMPLETION        0
#define ERROR_IDLE_COMPLETION   0x01
#define OUT_HI_PRI_COMPLETION   0x01
#define INBOUND_MFS_COMPLETION  0x02
#define INBOUND_000_COMPLETION  0x03
#define INBOUND_SFS_COMPLETION  0x04  // Tachyon & TachLite
#define ERQ_FROZEN_COMPLETION   0x06  // TachLite
#define INBOUND_C1_TIMEOUT      0x05
#define INBOUND_BUSIED_FRAME    0x06
#define SFS_BUF_WARN            0x07
#define FCP_FROZEN_COMPLETION   0x07  // TachLite
#define MFS_BUF_WARN            0x08
#define IMQ_BUF_WARN            0x09
#define FRAME_MGR_INTERRUPT     0x0A
#define READ_STATUS             0x0B
#define INBOUND_SCSI_DATA_COMPLETION  0x0C
#define INBOUND_FCP_XCHG_COMPLETION   0x0C  // TachLite
#define INBOUND_SCSI_DATA_COMMAND     0x0D
#define BAD_SCSI_FRAME                0x0E
#define INB_SCSI_STATUS_COMPLETION    0x0F
#define BUFFER_PROCESSED_COMPLETION   0x11

// FC-AL (Tachyon) Loop Port State Machine defs
// (loop "Up" states)
#define MONITORING 0x0
#define ARBITRATING 0x1
#define ARBITRAT_WON 0x2
#define OPEN 0x3
#define OPENED 0x4
#define XMITTD_CLOSE 0x5
#define RCVD_CLOSE 0x6
#define TRANSFER 0x7

// (loop "Down" states)
#define INITIALIZING 0x8
#define O_I_INIT 0x9
#define O_I_PROTOCOL 0xa
#define O_I_LIP_RCVD 0xb
#define HOST_CONTROL 0xc
#define LOOP_FAIL 0xd
// (no 0xe)
#define OLD_PORT 0xf


#define TACHYON_CHIP_INC
#endif
#endif /* CPQFCTSCHIP_H */
Commit	Line	Data
1da177e4 LT	1	/* Copyright(c) 2000, Compaq Computer Corporation
	2	* Fibre Channel Host Bus Adapter
	3	* 64-bit, 66MHz PCI
	4	* Originally developed and tested on:
	5	* (front): [chip] Tachyon TS HPFC-5166A/1.2 L2C1090 ...
	6	* SP# P225CXCBFIEL6T, Rev XC
	7	* SP# 161290-001, Rev XD
	8	* (back): Board No. 010008-001 A/W Rev X5, FAB REV X5
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2, or (at your option) any
	13	* later version.
	14	*
	15	* This program is distributed in the hope that it will be useful, but
	16	* WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	* Written by Don Zimmerman
	20	*/
	21	#ifndef CPQFCTSCHIP_H
	22	#define CPQFCTSCHIP_H
	23	#ifndef TACHYON_CHIP_INC
	24
	25	// FC-PH (Physical) specification levels for Login payloads
	26	// NOTE: These are NOT strictly complied with by any FC vendors
	27
	28	#define FC_PH42 0x08
	29	#define FC_PH43 0x09
	30	#define FC_PH3 0x20
	31
	32	#define TACHLITE_TS_RX_SIZE 1024 // max inbound frame size
	33	// "I" prefix is for Include
	34
	35	#define IVENDID 0x00 // word
	36	#define IDEVID 0x02
	37	#define ITLCFGCMD 0x04
	38	#define IMEMBASE 0x18 // Tachyon
	39	#define ITLMEMBASE 0x1C // Tachlite
	40	#define IIOBASEL 0x10 // Tachyon I/O base address, lower 256 bytes
	41	#define IIOBASEU 0x14 // Tachyon I/O base address, upper 256 bytes
	42	#define ITLIOBASEL 0x14 // TachLite I/O base address, lower 256 bytes
	43	#define ITLIOBASEU 0x18 // TachLite I/O base address, upper 256 bytes
	44	#define ITLRAMBASE 0x20 // TL on-board RAM start
	45	#define ISROMBASE 0x24
	46	#define IROMBASE 0x30
	47
	48	#define ICFGCMD 0x04 // PCI config - PCI config access (word)
	49	#define ICFGSTAT 0x06 // PCI status (R - word)
	50	#define IRCTR_WCTR 0x1F2 // ROM control / pre-fetch wait counter
	51	#define IPCIMCTR 0x1F3 // PCI master control register
	52	#define IINTPEND 0x1FD // Interrupt pending (I/O Upper - Tachyon & TL)
	53	#define IINTEN 0x1FE // Interrupt enable (I/O Upper - Tachyon & TL)
	54	#define IINTSTAT 0x1FF // Interrupt status (I/O Upper - Tachyon & TL)
	55
	56	#define IMQ_BASE 0x80
	57	#define IMQ_LENGTH 0x84
	58	#define IMQ_CONSUMER_INDEX 0x88
	59	#define IMQ_PRODUCER_INDEX 0x8C // Tach copies its INDX to bits 0-7 of value
	60
	61	/*
	62	// IOBASE UPPER
	63	#define SFSBQ_BASE 0x00 // single-frame sequences
	64	#define SFSBQ_LENGTH 0x04
65	#define SFSBQ_PRODUCER_INDEX 0x08
66	#define SFSBQ_CONSUMER_INDEX 0x0C // (R)
67	#define SFS_BUFFER_LENGTH 0X10
68	// SCSI-FCP hardware assists
69	#define SEST_BASE 0x40 // SSCI Exchange State Table
70	#define SEST_LENGTH 0x44
71	#define SCSI_BUFFER_LENGTH 0x48
72	#define SEST_LINKED_LIST 0x4C
73
74	#define TACHYON_My_ID 0x6C
75	#define TACHYON_CONFIGURATION 0x84 // (R/W) reset val 2
76	#define TACHYON_CONTROL 0x88
77	#define TACHYON_STATUS 0x8C // (R)
78	#define TACHYON_FLUSH_SEST 0x90 // (R/W)
79	#define TACHYON_EE_CREDIT_TMR 0x94 // (R)
80	#define TACHYON_BB_CREDIT_TMR 0x98 // (R)
81	#define TACHYON_RCV_FRAME_ERR 0x9C // (R)
82	#define FRAME_MANAGER_CONFIG 0xC0 // (R/W)
83	#define FRAME_MANAGER_CONTROL 0xC4
84	#define FRAME_MANAGER_STATUS 0xC8 // (R)
85	#define FRAME_MANAGER_ED_TOV 0xCC
86	#define FRAME_MANAGER_LINK_ERR1 0xD0 // (R)
87	#define FRAME_MANAGER_LINK_ERR2 0xD4 // (R)
88	#define FRAME_MANAGER_TIMEOUT2 0xD8 // (W)
89	#define FRAME_MANAGER_BB_CREDIT 0xDC // (R)
90	#define FRAME_MANAGER_WWN_HI 0xE0 // (R/W)
91	#define FRAME_MANAGER_WWN_LO 0xE4 // (R/W)
92	#define FRAME_MANAGER_RCV_AL_PA 0xE8 // (R)
93	#define FRAME_MANAGER_PRIMITIVE 0xEC // {K28.5} byte1 byte2 byte3
94	*/
95
96	#define TL_MEM_ERQ_BASE 0x0 //ERQ Base
97	#define TL_IO_ERQ_BASE 0x0 //ERQ base
98
99	#define TL_MEM_ERQ_LENGTH 0x4 //ERQ Length
100	#define TL_IO_ERQ_LENGTH 0x4 //ERQ Length
101
102	#define TL_MEM_ERQ_PRODUCER_INDEX 0x8 //ERQ Producer Index register
103	#define TL_IO_ERQ_PRODUCER_INDEX 0x8 //ERQ Producer Index register
104
105	#define TL_MEM_ERQ_CONSUMER_INDEX_ADR 0xC //ERQ Consumer Index address register
106	#define TL_IO_ERQ_CONSUMER_INDEX_ADR 0xC //ERQ Consumer Index address register
107
108	#define TL_MEM_ERQ_CONSUMER_INDEX 0xC //ERQ Consumer Index
109	#define TL_IO_ERQ_CONSUMER_INDEX 0xC //ERQ Consumer Index
110
111	#define TL_MEM_SFQ_BASE 0x50 //SFQ Base
112	#define TL_IO_SFQ_BASE 0x50 //SFQ base
113
114	#define TL_MEM_SFQ_LENGTH 0x54 //SFQ Length
115	#define TL_IO_SFQ_LENGTH 0x54 //SFQ Length
116
117	#define TL_MEM_SFQ_CONSUMER_INDEX 0x58 //SFQ Consumer Index
118	#define TL_IO_SFQ_CONSUMER_INDEX 0x58 //SFQ Consumer Index
119
120	#define TL_MEM_IMQ_BASE 0x80 //IMQ Base
121	#define TL_IO_IMQ_BASE 0x80 //IMQ base
122
123	#define TL_MEM_IMQ_LENGTH 0x84 //IMQ Length
124	#define TL_IO_IMQ_LENGTH 0x84 //IMQ Length
125
126	#define TL_MEM_IMQ_CONSUMER_INDEX 0x88 //IMQ Consumer Index
127	#define TL_IO_IMQ_CONSUMER_INDEX 0x88 //IMQ Consumer Index
128
129	#define TL_MEM_IMQ_PRODUCER_INDEX_ADR 0x8C //IMQ Producer Index address register
130	#define TL_IO_IMQ_PRODUCER_INDEX_ADR 0x8C //IMQ Producer Index address register
131
132	#define TL_MEM_SEST_BASE 0x140 //SFQ Base
133	#define TL_IO_SEST_BASE 0x40 //SFQ base
134
135	#define TL_MEM_SEST_LENGTH 0x144 //SFQ Length
136	#define TL_IO_SEST_LENGTH 0x44 //SFQ Length
137
138	#define TL_MEM_SEST_LINKED_LIST 0x14C
139
140	#define TL_MEM_SEST_SG_PAGE 0x168 // Extended Scatter/Gather page size
141
142	#define TL_MEM_TACH_My_ID 0x16C
143	#define TL_IO_TACH_My_ID 0x6C //My AL_PA ID
144
145	#define TL_MEM_TACH_CONFIG 0x184 //Tachlite Configuration register
146	#define TL_IO_CONFIG 0x84 //Tachlite Configuration register
147
148	#define TL_MEM_TACH_CONTROL 0x188 //Tachlite Control register
149	#define TL_IO_CTR 0x88 //Tachlite Control register
150
151	#define TL_MEM_TACH_STATUS 0x18C //Tachlite Status register
152	#define TL_IO_STAT 0x8C //Tachlite Status register
153
154	#define TL_MEM_FM_CONFIG 0x1C0 //Frame Manager Configuration register
155	#define TL_IO_FM_CONFIG 0xC0 //Frame Manager Configuration register
156
157	#define TL_MEM_FM_CONTROL 0x1C4 //Frame Manager Control
158	#define TL_IO_FM_CTL 0xC4 //Frame Manager Control
159
160	#define TL_MEM_FM_STATUS 0x1C8 //Frame Manager Status
161	#define TL_IO_FM_STAT 0xC8 //Frame Manager Status
162
163	#define TL_MEM_FM_LINK_STAT1 0x1D0 //Frame Manager Link Status 1
164	#define TL_IO_FM_LINK_STAT1 0xD0 //Frame Manager Link Status 1
165
166	#define TL_MEM_FM_LINK_STAT2 0x1D4 //Frame Manager Link Status 2
167	#define TL_IO_FM_LINK_STAT2 0xD4 //Frame Manager Link Status 2
168
169	#define TL_MEM_FM_TIMEOUT2 0x1D8 // (W)
170
171	#define TL_MEM_FM_BB_CREDIT0 0x1DC
172
173	#define TL_MEM_FM_WWN_HI 0x1E0 //Frame Manager World Wide Name High
174	#define TL_IO_FM_WWN_HI 0xE0 //Frame Manager World Wide Name High
175
176	#define TL_MEM_FM_WWN_LO 0x1E4 //Frame Manager World Wide Name LOW
177	#define TL_IO_FM_WWN_LO 0xE4 //Frame Manager World Wide Name Low
178
179	#define TL_MEM_FM_RCV_AL_PA 0x1E8 //Frame Manager AL_PA Received register
180	#define TL_IO_FM_ALPA 0xE8 //Frame Manager AL_PA Received register
181
182	#define TL_MEM_FM_ED_TOV 0x1CC
183
184	#define TL_IO_ROMCTR 0xFA //TL PCI ROM Control Register
185	#define TL_IO_PCIMCTR 0xFB //TL PCI Master Control Register
186	#define TL_IO_SOFTRST 0xFC //Tachlite Configuration register
187	#define TL_MEM_SOFTRST 0x1FC //Tachlite Configuration register
188
189	// completion message types (bit 8 set means Interrupt generated)
190	// CM_Type
191	#define OUTBOUND_COMPLETION 0
192	#define ERROR_IDLE_COMPLETION 0x01
193	#define OUT_HI_PRI_COMPLETION 0x01
194	#define INBOUND_MFS_COMPLETION 0x02
195	#define INBOUND_000_COMPLETION 0x03
196	#define INBOUND_SFS_COMPLETION 0x04 // Tachyon & TachLite
197	#define ERQ_FROZEN_COMPLETION 0x06 // TachLite
198	#define INBOUND_C1_TIMEOUT 0x05
199	#define INBOUND_BUSIED_FRAME 0x06
200	#define SFS_BUF_WARN 0x07
201	#define FCP_FROZEN_COMPLETION 0x07 // TachLite
202	#define MFS_BUF_WARN 0x08
203	#define IMQ_BUF_WARN 0x09
204	#define FRAME_MGR_INTERRUPT 0x0A
205	#define READ_STATUS 0x0B
206	#define INBOUND_SCSI_DATA_COMPLETION 0x0C
207	#define INBOUND_FCP_XCHG_COMPLETION 0x0C // TachLite
208	#define INBOUND_SCSI_DATA_COMMAND 0x0D
209	#define BAD_SCSI_FRAME 0x0E
210	#define INB_SCSI_STATUS_COMPLETION 0x0F
211	#define BUFFER_PROCESSED_COMPLETION 0x11
212
213	// FC-AL (Tachyon) Loop Port State Machine defs
214	// (loop "Up" states)
215	#define MONITORING 0x0
216	#define ARBITRATING 0x1
217	#define ARBITRAT_WON 0x2
218	#define OPEN 0x3
219	#define OPENED 0x4
220	#define XMITTD_CLOSE 0x5
221	#define RCVD_CLOSE 0x6
222	#define TRANSFER 0x7
223
224	// (loop "Down" states)
225	#define INITIALIZING 0x8
226	#define O_I_INIT 0x9
227	#define O_I_PROTOCOL 0xa
228	#define O_I_LIP_RCVD 0xb
229	#define HOST_CONTROL 0xc
230	#define LOOP_FAIL 0xd
231	// (no 0xe)
232	#define OLD_PORT 0xf
233
234
235
236	#define TACHYON_CHIP_INC
237	#endif
238	#endif /* CPQFCTSCHIP_H */