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a3667aae NKI |
1 | /* |
2 | * This file is part of the Chelsio FCoE driver for Linux. | |
3 | * | |
4 | * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved. | |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #include <linux/pci.h> | |
36 | #include <linux/pci_regs.h> | |
37 | #include <linux/firmware.h> | |
38 | #include <linux/stddef.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/string.h> | |
41 | #include <linux/compiler.h> | |
42 | #include <linux/jiffies.h> | |
43 | #include <linux/kernel.h> | |
44 | #include <linux/log2.h> | |
45 | ||
46 | #include "csio_hw.h" | |
47 | #include "csio_lnode.h" | |
48 | #include "csio_rnode.h" | |
49 | ||
a3667aae NKI |
50 | int csio_dbg_level = 0xFEFF; |
51 | unsigned int csio_port_mask = 0xf; | |
52 | ||
53 | /* Default FW event queue entries. */ | |
54 | static uint32_t csio_evtq_sz = CSIO_EVTQ_SIZE; | |
55 | ||
56 | /* Default MSI param level */ | |
57 | int csio_msi = 2; | |
58 | ||
59 | /* FCoE function instances */ | |
60 | static int dev_num; | |
61 | ||
62 | /* FCoE Adapter types & its description */ | |
7cc16380 AB |
63 | static const struct csio_adap_desc csio_t5_fcoe_adapters[] = { |
64 | {"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"}, | |
65 | {"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"}, | |
3fb4c22e | 66 | {"T522-CR 10G/1G", "Chelsio T522-CR 10G/1G [FCoE]"}, |
7cc16380 AB |
67 | {"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"}, |
68 | {"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"}, | |
69 | {"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"}, | |
70 | {"T540-CH 10G", "Chelsio T540-CH 10G [FCoE]"}, | |
71 | {"T520-SO 10G", "Chelsio T520-SO 10G [FCoE]"}, | |
72 | {"T520-CX4 10G", "Chelsio T520-CX4 10G [FCoE]"}, | |
73 | {"T520-BT 10G", "Chelsio T520-BT 10G [FCoE]"}, | |
74 | {"T504-BT 1G", "Chelsio T504-BT 1G [FCoE]"}, | |
75 | {"B520-SR 10G", "Chelsio B520-SR 10G [FCoE]"}, | |
76 | {"B504-BT 1G", "Chelsio B504-BT 1G [FCoE]"}, | |
77 | {"T580-CR 10G", "Chelsio T580-CR 10G [FCoE]"}, | |
78 | {"T540-LP-CR 10G", "Chelsio T540-LP-CR 10G [FCoE]"}, | |
79 | {"AMSTERDAM 10G", "Chelsio AMSTERDAM 10G [FCoE]"}, | |
80 | {"T580-LP-CR 40G", "Chelsio T580-LP-CR 40G [FCoE]"}, | |
81 | {"T520-LL-CR 10G", "Chelsio T520-LL-CR 10G [FCoE]"}, | |
82 | {"T560-CR 40G", "Chelsio T560-CR 40G [FCoE]"}, | |
3fb4c22e PM |
83 | {"T580-CR 40G", "Chelsio T580-CR 40G [FCoE]"}, |
84 | {"T580-SO 40G", "Chelsio T580-SO 40G [FCoE]"}, | |
85 | {"T502-BT 1G", "Chelsio T502-BT 1G [FCoE]"} | |
a3667aae NKI |
86 | }; |
87 | ||
88 | static void csio_mgmtm_cleanup(struct csio_mgmtm *); | |
89 | static void csio_hw_mbm_cleanup(struct csio_hw *); | |
90 | ||
91 | /* State machine forward declarations */ | |
92 | static void csio_hws_uninit(struct csio_hw *, enum csio_hw_ev); | |
93 | static void csio_hws_configuring(struct csio_hw *, enum csio_hw_ev); | |
94 | static void csio_hws_initializing(struct csio_hw *, enum csio_hw_ev); | |
95 | static void csio_hws_ready(struct csio_hw *, enum csio_hw_ev); | |
96 | static void csio_hws_quiescing(struct csio_hw *, enum csio_hw_ev); | |
97 | static void csio_hws_quiesced(struct csio_hw *, enum csio_hw_ev); | |
98 | static void csio_hws_resetting(struct csio_hw *, enum csio_hw_ev); | |
99 | static void csio_hws_removing(struct csio_hw *, enum csio_hw_ev); | |
100 | static void csio_hws_pcierr(struct csio_hw *, enum csio_hw_ev); | |
101 | ||
102 | static void csio_hw_initialize(struct csio_hw *hw); | |
103 | static void csio_evtq_stop(struct csio_hw *hw); | |
104 | static void csio_evtq_start(struct csio_hw *hw); | |
105 | ||
106 | int csio_is_hw_ready(struct csio_hw *hw) | |
107 | { | |
108 | return csio_match_state(hw, csio_hws_ready); | |
109 | } | |
110 | ||
111 | int csio_is_hw_removing(struct csio_hw *hw) | |
112 | { | |
113 | return csio_match_state(hw, csio_hws_removing); | |
114 | } | |
115 | ||
116 | ||
117 | /* | |
118 | * csio_hw_wait_op_done_val - wait until an operation is completed | |
119 | * @hw: the HW module | |
120 | * @reg: the register to check for completion | |
121 | * @mask: a single-bit field within @reg that indicates completion | |
122 | * @polarity: the value of the field when the operation is completed | |
123 | * @attempts: number of check iterations | |
124 | * @delay: delay in usecs between iterations | |
125 | * @valp: where to store the value of the register at completion time | |
126 | * | |
127 | * Wait until an operation is completed by checking a bit in a register | |
128 | * up to @attempts times. If @valp is not NULL the value of the register | |
129 | * at the time it indicated completion is stored there. Returns 0 if the | |
130 | * operation completes and -EAGAIN otherwise. | |
131 | */ | |
7cc16380 | 132 | int |
a3667aae NKI |
133 | csio_hw_wait_op_done_val(struct csio_hw *hw, int reg, uint32_t mask, |
134 | int polarity, int attempts, int delay, uint32_t *valp) | |
135 | { | |
136 | uint32_t val; | |
137 | while (1) { | |
138 | val = csio_rd_reg32(hw, reg); | |
139 | ||
140 | if (!!(val & mask) == polarity) { | |
141 | if (valp) | |
142 | *valp = val; | |
143 | return 0; | |
144 | } | |
145 | ||
146 | if (--attempts == 0) | |
147 | return -EAGAIN; | |
148 | if (delay) | |
149 | udelay(delay); | |
150 | } | |
151 | } | |
152 | ||
7cc16380 AB |
153 | /* |
154 | * csio_hw_tp_wr_bits_indirect - set/clear bits in an indirect TP register | |
155 | * @hw: the adapter | |
156 | * @addr: the indirect TP register address | |
157 | * @mask: specifies the field within the register to modify | |
158 | * @val: new value for the field | |
159 | * | |
160 | * Sets a field of an indirect TP register to the given value. | |
161 | */ | |
162 | void | |
163 | csio_hw_tp_wr_bits_indirect(struct csio_hw *hw, unsigned int addr, | |
164 | unsigned int mask, unsigned int val) | |
165 | { | |
837e4a42 HS |
166 | csio_wr_reg32(hw, addr, TP_PIO_ADDR_A); |
167 | val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask; | |
168 | csio_wr_reg32(hw, val, TP_PIO_DATA_A); | |
7cc16380 AB |
169 | } |
170 | ||
a3667aae NKI |
171 | void |
172 | csio_set_reg_field(struct csio_hw *hw, uint32_t reg, uint32_t mask, | |
173 | uint32_t value) | |
174 | { | |
175 | uint32_t val = csio_rd_reg32(hw, reg) & ~mask; | |
176 | ||
177 | csio_wr_reg32(hw, val | value, reg); | |
178 | /* Flush */ | |
179 | csio_rd_reg32(hw, reg); | |
180 | ||
181 | } | |
182 | ||
a3667aae | 183 | static int |
5036f0a0 | 184 | csio_memory_write(struct csio_hw *hw, int mtype, u32 addr, u32 len, u32 *buf) |
a3667aae | 185 | { |
7cc16380 AB |
186 | return hw->chip_ops->chip_memory_rw(hw, MEMWIN_CSIOSTOR, mtype, |
187 | addr, len, buf, 0); | |
a3667aae NKI |
188 | } |
189 | ||
190 | /* | |
191 | * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. | |
192 | */ | |
7cc16380 AB |
193 | #define EEPROM_MAX_RD_POLL 40 |
194 | #define EEPROM_MAX_WR_POLL 6 | |
195 | #define EEPROM_STAT_ADDR 0x7bfc | |
196 | #define VPD_BASE 0x400 | |
197 | #define VPD_BASE_OLD 0 | |
198 | #define VPD_LEN 1024 | |
a3667aae NKI |
199 | #define VPD_INFO_FLD_HDR_SIZE 3 |
200 | ||
201 | /* | |
202 | * csio_hw_seeprom_read - read a serial EEPROM location | |
203 | * @hw: hw to read | |
204 | * @addr: EEPROM virtual address | |
205 | * @data: where to store the read data | |
206 | * | |
207 | * Read a 32-bit word from a location in serial EEPROM using the card's PCI | |
208 | * VPD capability. Note that this function must be called with a virtual | |
209 | * address. | |
210 | */ | |
211 | static int | |
212 | csio_hw_seeprom_read(struct csio_hw *hw, uint32_t addr, uint32_t *data) | |
213 | { | |
214 | uint16_t val = 0; | |
215 | int attempts = EEPROM_MAX_RD_POLL; | |
216 | uint32_t base = hw->params.pci.vpd_cap_addr; | |
217 | ||
218 | if (addr >= EEPROMVSIZE || (addr & 3)) | |
219 | return -EINVAL; | |
220 | ||
221 | pci_write_config_word(hw->pdev, base + PCI_VPD_ADDR, (uint16_t)addr); | |
222 | ||
223 | do { | |
224 | udelay(10); | |
225 | pci_read_config_word(hw->pdev, base + PCI_VPD_ADDR, &val); | |
226 | } while (!(val & PCI_VPD_ADDR_F) && --attempts); | |
227 | ||
228 | if (!(val & PCI_VPD_ADDR_F)) { | |
229 | csio_err(hw, "reading EEPROM address 0x%x failed\n", addr); | |
230 | return -EINVAL; | |
231 | } | |
232 | ||
233 | pci_read_config_dword(hw->pdev, base + PCI_VPD_DATA, data); | |
78890ed7 | 234 | *data = le32_to_cpu(*(__le32 *)data); |
5036f0a0 | 235 | |
a3667aae NKI |
236 | return 0; |
237 | } | |
238 | ||
239 | /* | |
240 | * Partial EEPROM Vital Product Data structure. Includes only the ID and | |
241 | * VPD-R sections. | |
242 | */ | |
243 | struct t4_vpd_hdr { | |
244 | u8 id_tag; | |
245 | u8 id_len[2]; | |
246 | u8 id_data[ID_LEN]; | |
247 | u8 vpdr_tag; | |
248 | u8 vpdr_len[2]; | |
249 | }; | |
250 | ||
251 | /* | |
252 | * csio_hw_get_vpd_keyword_val - Locates an information field keyword in | |
253 | * the VPD | |
254 | * @v: Pointer to buffered vpd data structure | |
255 | * @kw: The keyword to search for | |
256 | * | |
257 | * Returns the value of the information field keyword or | |
258 | * -EINVAL otherwise. | |
259 | */ | |
260 | static int | |
261 | csio_hw_get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw) | |
262 | { | |
263 | int32_t i; | |
264 | int32_t offset , len; | |
265 | const uint8_t *buf = &v->id_tag; | |
266 | const uint8_t *vpdr_len = &v->vpdr_tag; | |
267 | offset = sizeof(struct t4_vpd_hdr); | |
268 | len = (uint16_t)vpdr_len[1] + ((uint16_t)vpdr_len[2] << 8); | |
269 | ||
270 | if (len + sizeof(struct t4_vpd_hdr) > VPD_LEN) | |
271 | return -EINVAL; | |
272 | ||
273 | for (i = offset; (i + VPD_INFO_FLD_HDR_SIZE) <= (offset + len);) { | |
274 | if (memcmp(buf + i , kw, 2) == 0) { | |
275 | i += VPD_INFO_FLD_HDR_SIZE; | |
276 | return i; | |
277 | } | |
278 | ||
279 | i += VPD_INFO_FLD_HDR_SIZE + buf[i+2]; | |
280 | } | |
281 | ||
282 | return -EINVAL; | |
283 | } | |
284 | ||
285 | static int | |
286 | csio_pci_capability(struct pci_dev *pdev, int cap, int *pos) | |
287 | { | |
288 | *pos = pci_find_capability(pdev, cap); | |
289 | if (*pos) | |
290 | return 0; | |
291 | ||
292 | return -1; | |
293 | } | |
294 | ||
295 | /* | |
296 | * csio_hw_get_vpd_params - read VPD parameters from VPD EEPROM | |
297 | * @hw: HW module | |
298 | * @p: where to store the parameters | |
299 | * | |
300 | * Reads card parameters stored in VPD EEPROM. | |
301 | */ | |
302 | static int | |
303 | csio_hw_get_vpd_params(struct csio_hw *hw, struct csio_vpd *p) | |
304 | { | |
305 | int i, ret, ec, sn, addr; | |
306 | uint8_t *vpd, csum; | |
307 | const struct t4_vpd_hdr *v; | |
308 | /* To get around compilation warning from strstrip */ | |
309 | char *s; | |
310 | ||
311 | if (csio_is_valid_vpd(hw)) | |
312 | return 0; | |
313 | ||
314 | ret = csio_pci_capability(hw->pdev, PCI_CAP_ID_VPD, | |
315 | &hw->params.pci.vpd_cap_addr); | |
316 | if (ret) | |
317 | return -EINVAL; | |
318 | ||
319 | vpd = kzalloc(VPD_LEN, GFP_ATOMIC); | |
320 | if (vpd == NULL) | |
321 | return -ENOMEM; | |
322 | ||
323 | /* | |
324 | * Card information normally starts at VPD_BASE but early cards had | |
325 | * it at 0. | |
326 | */ | |
327 | ret = csio_hw_seeprom_read(hw, VPD_BASE, (uint32_t *)(vpd)); | |
328 | addr = *vpd == 0x82 ? VPD_BASE : VPD_BASE_OLD; | |
329 | ||
330 | for (i = 0; i < VPD_LEN; i += 4) { | |
331 | ret = csio_hw_seeprom_read(hw, addr + i, (uint32_t *)(vpd + i)); | |
332 | if (ret) { | |
333 | kfree(vpd); | |
334 | return ret; | |
335 | } | |
336 | } | |
337 | ||
338 | /* Reset the VPD flag! */ | |
339 | hw->flags &= (~CSIO_HWF_VPD_VALID); | |
340 | ||
341 | v = (const struct t4_vpd_hdr *)vpd; | |
342 | ||
343 | #define FIND_VPD_KW(var, name) do { \ | |
344 | var = csio_hw_get_vpd_keyword_val(v, name); \ | |
345 | if (var < 0) { \ | |
346 | csio_err(hw, "missing VPD keyword " name "\n"); \ | |
347 | kfree(vpd); \ | |
348 | return -EINVAL; \ | |
349 | } \ | |
350 | } while (0) | |
351 | ||
352 | FIND_VPD_KW(i, "RV"); | |
353 | for (csum = 0; i >= 0; i--) | |
354 | csum += vpd[i]; | |
355 | ||
356 | if (csum) { | |
357 | csio_err(hw, "corrupted VPD EEPROM, actual csum %u\n", csum); | |
358 | kfree(vpd); | |
359 | return -EINVAL; | |
360 | } | |
361 | FIND_VPD_KW(ec, "EC"); | |
362 | FIND_VPD_KW(sn, "SN"); | |
363 | #undef FIND_VPD_KW | |
364 | ||
365 | memcpy(p->id, v->id_data, ID_LEN); | |
366 | s = strstrip(p->id); | |
367 | memcpy(p->ec, vpd + ec, EC_LEN); | |
368 | s = strstrip(p->ec); | |
369 | i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; | |
370 | memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); | |
371 | s = strstrip(p->sn); | |
372 | ||
373 | csio_valid_vpd_copied(hw); | |
374 | ||
375 | kfree(vpd); | |
376 | return 0; | |
377 | } | |
378 | ||
379 | /* | |
380 | * csio_hw_sf1_read - read data from the serial flash | |
381 | * @hw: the HW module | |
382 | * @byte_cnt: number of bytes to read | |
383 | * @cont: whether another operation will be chained | |
384 | * @lock: whether to lock SF for PL access only | |
385 | * @valp: where to store the read data | |
386 | * | |
387 | * Reads up to 4 bytes of data from the serial flash. The location of | |
388 | * the read needs to be specified prior to calling this by issuing the | |
389 | * appropriate commands to the serial flash. | |
390 | */ | |
391 | static int | |
392 | csio_hw_sf1_read(struct csio_hw *hw, uint32_t byte_cnt, int32_t cont, | |
393 | int32_t lock, uint32_t *valp) | |
394 | { | |
395 | int ret; | |
396 | ||
397 | if (!byte_cnt || byte_cnt > 4) | |
398 | return -EINVAL; | |
0d804338 | 399 | if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F) |
a3667aae NKI |
400 | return -EBUSY; |
401 | ||
0d804338 HS |
402 | csio_wr_reg32(hw, SF_LOCK_V(lock) | SF_CONT_V(cont) | |
403 | BYTECNT_V(byte_cnt - 1), SF_OP_A); | |
404 | ret = csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, | |
405 | 10, NULL); | |
a3667aae | 406 | if (!ret) |
0d804338 | 407 | *valp = csio_rd_reg32(hw, SF_DATA_A); |
a3667aae NKI |
408 | return ret; |
409 | } | |
410 | ||
411 | /* | |
412 | * csio_hw_sf1_write - write data to the serial flash | |
413 | * @hw: the HW module | |
414 | * @byte_cnt: number of bytes to write | |
415 | * @cont: whether another operation will be chained | |
416 | * @lock: whether to lock SF for PL access only | |
417 | * @val: value to write | |
418 | * | |
419 | * Writes up to 4 bytes of data to the serial flash. The location of | |
420 | * the write needs to be specified prior to calling this by issuing the | |
421 | * appropriate commands to the serial flash. | |
422 | */ | |
423 | static int | |
424 | csio_hw_sf1_write(struct csio_hw *hw, uint32_t byte_cnt, uint32_t cont, | |
425 | int32_t lock, uint32_t val) | |
426 | { | |
427 | if (!byte_cnt || byte_cnt > 4) | |
428 | return -EINVAL; | |
0d804338 | 429 | if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F) |
a3667aae NKI |
430 | return -EBUSY; |
431 | ||
0d804338 HS |
432 | csio_wr_reg32(hw, val, SF_DATA_A); |
433 | csio_wr_reg32(hw, SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | | |
434 | OP_V(1) | SF_LOCK_V(lock), SF_OP_A); | |
a3667aae | 435 | |
0d804338 | 436 | return csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, |
a3667aae NKI |
437 | 10, NULL); |
438 | } | |
439 | ||
440 | /* | |
441 | * csio_hw_flash_wait_op - wait for a flash operation to complete | |
442 | * @hw: the HW module | |
443 | * @attempts: max number of polls of the status register | |
444 | * @delay: delay between polls in ms | |
445 | * | |
446 | * Wait for a flash operation to complete by polling the status register. | |
447 | */ | |
448 | static int | |
449 | csio_hw_flash_wait_op(struct csio_hw *hw, int32_t attempts, int32_t delay) | |
450 | { | |
451 | int ret; | |
452 | uint32_t status; | |
453 | ||
454 | while (1) { | |
455 | ret = csio_hw_sf1_write(hw, 1, 1, 1, SF_RD_STATUS); | |
456 | if (ret != 0) | |
457 | return ret; | |
458 | ||
459 | ret = csio_hw_sf1_read(hw, 1, 0, 1, &status); | |
460 | if (ret != 0) | |
461 | return ret; | |
462 | ||
463 | if (!(status & 1)) | |
464 | return 0; | |
465 | if (--attempts == 0) | |
466 | return -EAGAIN; | |
467 | if (delay) | |
468 | msleep(delay); | |
469 | } | |
470 | } | |
471 | ||
472 | /* | |
473 | * csio_hw_read_flash - read words from serial flash | |
474 | * @hw: the HW module | |
475 | * @addr: the start address for the read | |
476 | * @nwords: how many 32-bit words to read | |
477 | * @data: where to store the read data | |
478 | * @byte_oriented: whether to store data as bytes or as words | |
479 | * | |
480 | * Read the specified number of 32-bit words from the serial flash. | |
481 | * If @byte_oriented is set the read data is stored as a byte array | |
482 | * (i.e., big-endian), otherwise as 32-bit words in the platform's | |
483 | * natural endianess. | |
484 | */ | |
485 | static int | |
486 | csio_hw_read_flash(struct csio_hw *hw, uint32_t addr, uint32_t nwords, | |
487 | uint32_t *data, int32_t byte_oriented) | |
488 | { | |
489 | int ret; | |
490 | ||
491 | if (addr + nwords * sizeof(uint32_t) > hw->params.sf_size || (addr & 3)) | |
492 | return -EINVAL; | |
493 | ||
494 | addr = swab32(addr) | SF_RD_DATA_FAST; | |
495 | ||
496 | ret = csio_hw_sf1_write(hw, 4, 1, 0, addr); | |
497 | if (ret != 0) | |
498 | return ret; | |
499 | ||
500 | ret = csio_hw_sf1_read(hw, 1, 1, 0, data); | |
501 | if (ret != 0) | |
502 | return ret; | |
503 | ||
504 | for ( ; nwords; nwords--, data++) { | |
505 | ret = csio_hw_sf1_read(hw, 4, nwords > 1, nwords == 1, data); | |
506 | if (nwords == 1) | |
0d804338 | 507 | csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */ |
a3667aae NKI |
508 | if (ret) |
509 | return ret; | |
510 | if (byte_oriented) | |
78890ed7 | 511 | *data = (__force __u32) htonl(*data); |
a3667aae NKI |
512 | } |
513 | return 0; | |
514 | } | |
515 | ||
516 | /* | |
517 | * csio_hw_write_flash - write up to a page of data to the serial flash | |
518 | * @hw: the hw | |
519 | * @addr: the start address to write | |
520 | * @n: length of data to write in bytes | |
521 | * @data: the data to write | |
522 | * | |
523 | * Writes up to a page of data (256 bytes) to the serial flash starting | |
524 | * at the given address. All the data must be written to the same page. | |
525 | */ | |
526 | static int | |
527 | csio_hw_write_flash(struct csio_hw *hw, uint32_t addr, | |
528 | uint32_t n, const uint8_t *data) | |
529 | { | |
530 | int ret = -EINVAL; | |
531 | uint32_t buf[64]; | |
532 | uint32_t i, c, left, val, offset = addr & 0xff; | |
533 | ||
534 | if (addr >= hw->params.sf_size || offset + n > SF_PAGE_SIZE) | |
535 | return -EINVAL; | |
536 | ||
537 | val = swab32(addr) | SF_PROG_PAGE; | |
538 | ||
539 | ret = csio_hw_sf1_write(hw, 1, 0, 1, SF_WR_ENABLE); | |
540 | if (ret != 0) | |
541 | goto unlock; | |
542 | ||
543 | ret = csio_hw_sf1_write(hw, 4, 1, 1, val); | |
544 | if (ret != 0) | |
545 | goto unlock; | |
546 | ||
547 | for (left = n; left; left -= c) { | |
548 | c = min(left, 4U); | |
549 | for (val = 0, i = 0; i < c; ++i) | |
550 | val = (val << 8) + *data++; | |
551 | ||
552 | ret = csio_hw_sf1_write(hw, c, c != left, 1, val); | |
553 | if (ret) | |
554 | goto unlock; | |
555 | } | |
556 | ret = csio_hw_flash_wait_op(hw, 8, 1); | |
557 | if (ret) | |
558 | goto unlock; | |
559 | ||
0d804338 | 560 | csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */ |
a3667aae NKI |
561 | |
562 | /* Read the page to verify the write succeeded */ | |
563 | ret = csio_hw_read_flash(hw, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); | |
564 | if (ret) | |
565 | return ret; | |
566 | ||
567 | if (memcmp(data - n, (uint8_t *)buf + offset, n)) { | |
568 | csio_err(hw, | |
569 | "failed to correctly write the flash page at %#x\n", | |
570 | addr); | |
571 | return -EINVAL; | |
572 | } | |
573 | ||
574 | return 0; | |
575 | ||
576 | unlock: | |
0d804338 | 577 | csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */ |
a3667aae NKI |
578 | return ret; |
579 | } | |
580 | ||
581 | /* | |
582 | * csio_hw_flash_erase_sectors - erase a range of flash sectors | |
583 | * @hw: the HW module | |
584 | * @start: the first sector to erase | |
585 | * @end: the last sector to erase | |
586 | * | |
587 | * Erases the sectors in the given inclusive range. | |
588 | */ | |
589 | static int | |
590 | csio_hw_flash_erase_sectors(struct csio_hw *hw, int32_t start, int32_t end) | |
591 | { | |
592 | int ret = 0; | |
593 | ||
594 | while (start <= end) { | |
595 | ||
596 | ret = csio_hw_sf1_write(hw, 1, 0, 1, SF_WR_ENABLE); | |
597 | if (ret != 0) | |
598 | goto out; | |
599 | ||
600 | ret = csio_hw_sf1_write(hw, 4, 0, 1, | |
601 | SF_ERASE_SECTOR | (start << 8)); | |
602 | if (ret != 0) | |
603 | goto out; | |
604 | ||
605 | ret = csio_hw_flash_wait_op(hw, 14, 500); | |
606 | if (ret != 0) | |
607 | goto out; | |
608 | ||
609 | start++; | |
610 | } | |
611 | out: | |
612 | if (ret) | |
613 | csio_err(hw, "erase of flash sector %d failed, error %d\n", | |
614 | start, ret); | |
0d804338 | 615 | csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */ |
a3667aae NKI |
616 | return 0; |
617 | } | |
618 | ||
a3667aae NKI |
619 | static void |
620 | csio_hw_print_fw_version(struct csio_hw *hw, char *str) | |
621 | { | |
622 | csio_info(hw, "%s: %u.%u.%u.%u\n", str, | |
b2e1a3f0 HS |
623 | FW_HDR_FW_VER_MAJOR_G(hw->fwrev), |
624 | FW_HDR_FW_VER_MINOR_G(hw->fwrev), | |
625 | FW_HDR_FW_VER_MICRO_G(hw->fwrev), | |
626 | FW_HDR_FW_VER_BUILD_G(hw->fwrev)); | |
a3667aae NKI |
627 | } |
628 | ||
629 | /* | |
630 | * csio_hw_get_fw_version - read the firmware version | |
631 | * @hw: HW module | |
632 | * @vers: where to place the version | |
633 | * | |
634 | * Reads the FW version from flash. | |
635 | */ | |
636 | static int | |
637 | csio_hw_get_fw_version(struct csio_hw *hw, uint32_t *vers) | |
638 | { | |
216ce69c | 639 | return csio_hw_read_flash(hw, FLASH_FW_START + |
a3667aae NKI |
640 | offsetof(struct fw_hdr, fw_ver), 1, |
641 | vers, 0); | |
642 | } | |
643 | ||
644 | /* | |
645 | * csio_hw_get_tp_version - read the TP microcode version | |
646 | * @hw: HW module | |
647 | * @vers: where to place the version | |
648 | * | |
649 | * Reads the TP microcode version from flash. | |
650 | */ | |
651 | static int | |
652 | csio_hw_get_tp_version(struct csio_hw *hw, u32 *vers) | |
653 | { | |
654 | return csio_hw_read_flash(hw, FLASH_FW_START + | |
655 | offsetof(struct fw_hdr, tp_microcode_ver), 1, | |
656 | vers, 0); | |
657 | } | |
658 | ||
a3667aae NKI |
659 | /* |
660 | * csio_hw_fw_dload - download firmware. | |
661 | * @hw: HW module | |
662 | * @fw_data: firmware image to write. | |
663 | * @size: image size | |
664 | * | |
665 | * Write the supplied firmware image to the card's serial flash. | |
666 | */ | |
667 | static int | |
668 | csio_hw_fw_dload(struct csio_hw *hw, uint8_t *fw_data, uint32_t size) | |
669 | { | |
670 | uint32_t csum; | |
671 | int32_t addr; | |
672 | int ret; | |
673 | uint32_t i; | |
674 | uint8_t first_page[SF_PAGE_SIZE]; | |
5036f0a0 | 675 | const __be32 *p = (const __be32 *)fw_data; |
a3667aae NKI |
676 | struct fw_hdr *hdr = (struct fw_hdr *)fw_data; |
677 | uint32_t sf_sec_size; | |
678 | ||
679 | if ((!hw->params.sf_size) || (!hw->params.sf_nsec)) { | |
680 | csio_err(hw, "Serial Flash data invalid\n"); | |
681 | return -EINVAL; | |
682 | } | |
683 | ||
684 | if (!size) { | |
685 | csio_err(hw, "FW image has no data\n"); | |
686 | return -EINVAL; | |
687 | } | |
688 | ||
689 | if (size & 511) { | |
690 | csio_err(hw, "FW image size not multiple of 512 bytes\n"); | |
691 | return -EINVAL; | |
692 | } | |
693 | ||
694 | if (ntohs(hdr->len512) * 512 != size) { | |
695 | csio_err(hw, "FW image size differs from size in FW header\n"); | |
696 | return -EINVAL; | |
697 | } | |
698 | ||
216ce69c | 699 | if (size > FLASH_FW_MAX_SIZE) { |
a3667aae | 700 | csio_err(hw, "FW image too large, max is %u bytes\n", |
216ce69c | 701 | FLASH_FW_MAX_SIZE); |
a3667aae NKI |
702 | return -EINVAL; |
703 | } | |
704 | ||
705 | for (csum = 0, i = 0; i < size / sizeof(csum); i++) | |
706 | csum += ntohl(p[i]); | |
707 | ||
708 | if (csum != 0xffffffff) { | |
709 | csio_err(hw, "corrupted firmware image, checksum %#x\n", csum); | |
710 | return -EINVAL; | |
711 | } | |
712 | ||
713 | sf_sec_size = hw->params.sf_size / hw->params.sf_nsec; | |
714 | i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ | |
715 | ||
716 | csio_dbg(hw, "Erasing sectors... start:%d end:%d\n", | |
216ce69c | 717 | FLASH_FW_START_SEC, FLASH_FW_START_SEC + i - 1); |
a3667aae | 718 | |
216ce69c PM |
719 | ret = csio_hw_flash_erase_sectors(hw, FLASH_FW_START_SEC, |
720 | FLASH_FW_START_SEC + i - 1); | |
a3667aae NKI |
721 | if (ret) { |
722 | csio_err(hw, "Flash Erase failed\n"); | |
723 | goto out; | |
724 | } | |
725 | ||
726 | /* | |
727 | * We write the correct version at the end so the driver can see a bad | |
728 | * version if the FW write fails. Start by writing a copy of the | |
729 | * first page with a bad version. | |
730 | */ | |
731 | memcpy(first_page, fw_data, SF_PAGE_SIZE); | |
732 | ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff); | |
216ce69c | 733 | ret = csio_hw_write_flash(hw, FLASH_FW_START, SF_PAGE_SIZE, first_page); |
a3667aae NKI |
734 | if (ret) |
735 | goto out; | |
736 | ||
737 | csio_dbg(hw, "Writing Flash .. start:%d end:%d\n", | |
738 | FW_IMG_START, FW_IMG_START + size); | |
739 | ||
216ce69c | 740 | addr = FLASH_FW_START; |
a3667aae NKI |
741 | for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { |
742 | addr += SF_PAGE_SIZE; | |
743 | fw_data += SF_PAGE_SIZE; | |
744 | ret = csio_hw_write_flash(hw, addr, SF_PAGE_SIZE, fw_data); | |
745 | if (ret) | |
746 | goto out; | |
747 | } | |
748 | ||
749 | ret = csio_hw_write_flash(hw, | |
216ce69c | 750 | FLASH_FW_START + |
a3667aae NKI |
751 | offsetof(struct fw_hdr, fw_ver), |
752 | sizeof(hdr->fw_ver), | |
753 | (const uint8_t *)&hdr->fw_ver); | |
754 | ||
755 | out: | |
756 | if (ret) | |
757 | csio_err(hw, "firmware download failed, error %d\n", ret); | |
758 | return ret; | |
759 | } | |
760 | ||
761 | static int | |
762 | csio_hw_get_flash_params(struct csio_hw *hw) | |
763 | { | |
764 | int ret; | |
765 | uint32_t info = 0; | |
766 | ||
767 | ret = csio_hw_sf1_write(hw, 1, 1, 0, SF_RD_ID); | |
768 | if (!ret) | |
769 | ret = csio_hw_sf1_read(hw, 3, 0, 1, &info); | |
0d804338 | 770 | csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */ |
a3667aae NKI |
771 | if (ret != 0) |
772 | return ret; | |
773 | ||
774 | if ((info & 0xff) != 0x20) /* not a Numonix flash */ | |
775 | return -EINVAL; | |
776 | info >>= 16; /* log2 of size */ | |
777 | if (info >= 0x14 && info < 0x18) | |
778 | hw->params.sf_nsec = 1 << (info - 16); | |
779 | else if (info == 0x18) | |
780 | hw->params.sf_nsec = 64; | |
781 | else | |
782 | return -EINVAL; | |
783 | hw->params.sf_size = 1 << info; | |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
a3667aae NKI |
788 | /*****************************************************************************/ |
789 | /* HW State machine assists */ | |
790 | /*****************************************************************************/ | |
791 | ||
792 | static int | |
793 | csio_hw_dev_ready(struct csio_hw *hw) | |
794 | { | |
795 | uint32_t reg; | |
796 | int cnt = 6; | |
4bbd458e | 797 | int src_pf; |
a3667aae | 798 | |
0d804338 HS |
799 | while (((reg = csio_rd_reg32(hw, PL_WHOAMI_A)) == 0xFFFFFFFF) && |
800 | (--cnt != 0)) | |
a3667aae NKI |
801 | mdelay(100); |
802 | ||
4bbd458e VP |
803 | if (csio_is_t5(hw->pdev->device & CSIO_HW_CHIP_MASK)) |
804 | src_pf = SOURCEPF_G(reg); | |
805 | else | |
806 | src_pf = T6_SOURCEPF_G(reg); | |
807 | ||
808 | if ((cnt == 0) && (((int32_t)(src_pf) < 0) || | |
809 | (src_pf >= CSIO_MAX_PFN))) { | |
a3667aae NKI |
810 | csio_err(hw, "PL_WHOAMI returned 0x%x, cnt:%d\n", reg, cnt); |
811 | return -EIO; | |
812 | } | |
813 | ||
4bbd458e | 814 | hw->pfn = src_pf; |
a3667aae NKI |
815 | |
816 | return 0; | |
817 | } | |
818 | ||
819 | /* | |
820 | * csio_do_hello - Perform the HELLO FW Mailbox command and process response. | |
821 | * @hw: HW module | |
822 | * @state: Device state | |
823 | * | |
824 | * FW_HELLO_CMD has to be polled for completion. | |
825 | */ | |
826 | static int | |
827 | csio_do_hello(struct csio_hw *hw, enum csio_dev_state *state) | |
828 | { | |
829 | struct csio_mb *mbp; | |
830 | int rv = 0; | |
a3667aae NKI |
831 | enum fw_retval retval; |
832 | uint8_t mpfn; | |
833 | char state_str[16]; | |
834 | int retries = FW_CMD_HELLO_RETRIES; | |
835 | ||
836 | memset(state_str, 0, sizeof(state_str)); | |
837 | ||
838 | mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); | |
839 | if (!mbp) { | |
840 | rv = -ENOMEM; | |
841 | CSIO_INC_STATS(hw, n_err_nomem); | |
842 | goto out; | |
843 | } | |
844 | ||
a3667aae NKI |
845 | retry: |
846 | csio_mb_hello(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, | |
666224d4 | 847 | hw->pfn, CSIO_MASTER_MAY, NULL); |
a3667aae NKI |
848 | |
849 | rv = csio_mb_issue(hw, mbp); | |
850 | if (rv) { | |
851 | csio_err(hw, "failed to issue HELLO cmd. ret:%d.\n", rv); | |
852 | goto out_free_mb; | |
853 | } | |
854 | ||
855 | csio_mb_process_hello_rsp(hw, mbp, &retval, state, &mpfn); | |
856 | if (retval != FW_SUCCESS) { | |
857 | csio_err(hw, "HELLO cmd failed with ret: %d\n", retval); | |
858 | rv = -EINVAL; | |
859 | goto out_free_mb; | |
860 | } | |
861 | ||
862 | /* Firmware has designated us to be master */ | |
863 | if (hw->pfn == mpfn) { | |
864 | hw->flags |= CSIO_HWF_MASTER; | |
865 | } else if (*state == CSIO_DEV_STATE_UNINIT) { | |
866 | /* | |
867 | * If we're not the Master PF then we need to wait around for | |
868 | * the Master PF Driver to finish setting up the adapter. | |
869 | * | |
870 | * Note that we also do this wait if we're a non-Master-capable | |
871 | * PF and there is no current Master PF; a Master PF may show up | |
872 | * momentarily and we wouldn't want to fail pointlessly. (This | |
873 | * can happen when an OS loads lots of different drivers rapidly | |
874 | * at the same time). In this case, the Master PF returned by | |
875 | * the firmware will be PCIE_FW_MASTER_MASK so the test below | |
876 | * will work ... | |
877 | */ | |
878 | ||
879 | int waiting = FW_CMD_HELLO_TIMEOUT; | |
880 | ||
881 | /* | |
882 | * Wait for the firmware to either indicate an error or | |
883 | * initialized state. If we see either of these we bail out | |
884 | * and report the issue to the caller. If we exhaust the | |
885 | * "hello timeout" and we haven't exhausted our retries, try | |
886 | * again. Otherwise bail with a timeout error. | |
887 | */ | |
888 | for (;;) { | |
889 | uint32_t pcie_fw; | |
890 | ||
7cc16380 | 891 | spin_unlock_irq(&hw->lock); |
a3667aae | 892 | msleep(50); |
7cc16380 | 893 | spin_lock_irq(&hw->lock); |
a3667aae NKI |
894 | waiting -= 50; |
895 | ||
896 | /* | |
897 | * If neither Error nor Initialialized are indicated | |
898 | * by the firmware keep waiting till we exaust our | |
899 | * timeout ... and then retry if we haven't exhausted | |
900 | * our retries ... | |
901 | */ | |
f061de42 HS |
902 | pcie_fw = csio_rd_reg32(hw, PCIE_FW_A); |
903 | if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) { | |
a3667aae NKI |
904 | if (waiting <= 0) { |
905 | if (retries-- > 0) | |
906 | goto retry; | |
907 | ||
908 | rv = -ETIMEDOUT; | |
909 | break; | |
910 | } | |
911 | continue; | |
912 | } | |
913 | ||
914 | /* | |
915 | * We either have an Error or Initialized condition | |
916 | * report errors preferentially. | |
917 | */ | |
918 | if (state) { | |
f061de42 | 919 | if (pcie_fw & PCIE_FW_ERR_F) { |
a3667aae NKI |
920 | *state = CSIO_DEV_STATE_ERR; |
921 | rv = -ETIMEDOUT; | |
f061de42 | 922 | } else if (pcie_fw & PCIE_FW_INIT_F) |
a3667aae NKI |
923 | *state = CSIO_DEV_STATE_INIT; |
924 | } | |
925 | ||
926 | /* | |
927 | * If we arrived before a Master PF was selected and | |
928 | * there's not a valid Master PF, grab its identity | |
929 | * for our caller. | |
930 | */ | |
f061de42 HS |
931 | if (mpfn == PCIE_FW_MASTER_M && |
932 | (pcie_fw & PCIE_FW_MASTER_VLD_F)) | |
933 | mpfn = PCIE_FW_MASTER_G(pcie_fw); | |
a3667aae NKI |
934 | break; |
935 | } | |
936 | hw->flags &= ~CSIO_HWF_MASTER; | |
937 | } | |
938 | ||
939 | switch (*state) { | |
940 | case CSIO_DEV_STATE_UNINIT: | |
941 | strcpy(state_str, "Initializing"); | |
942 | break; | |
943 | case CSIO_DEV_STATE_INIT: | |
944 | strcpy(state_str, "Initialized"); | |
945 | break; | |
946 | case CSIO_DEV_STATE_ERR: | |
947 | strcpy(state_str, "Error"); | |
948 | break; | |
949 | default: | |
950 | strcpy(state_str, "Unknown"); | |
951 | break; | |
952 | } | |
953 | ||
954 | if (hw->pfn == mpfn) | |
955 | csio_info(hw, "PF: %d, Coming up as MASTER, HW state: %s\n", | |
956 | hw->pfn, state_str); | |
957 | else | |
958 | csio_info(hw, | |
959 | "PF: %d, Coming up as SLAVE, Master PF: %d, HW state: %s\n", | |
960 | hw->pfn, mpfn, state_str); | |
961 | ||
962 | out_free_mb: | |
963 | mempool_free(mbp, hw->mb_mempool); | |
964 | out: | |
965 | return rv; | |
966 | } | |
967 | ||
968 | /* | |
969 | * csio_do_bye - Perform the BYE FW Mailbox command and process response. | |
970 | * @hw: HW module | |
971 | * | |
972 | */ | |
973 | static int | |
974 | csio_do_bye(struct csio_hw *hw) | |
975 | { | |
976 | struct csio_mb *mbp; | |
977 | enum fw_retval retval; | |
978 | ||
979 | mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); | |
980 | if (!mbp) { | |
981 | CSIO_INC_STATS(hw, n_err_nomem); | |
982 | return -ENOMEM; | |
983 | } | |
984 | ||
985 | csio_mb_bye(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL); | |
986 | ||
987 | if (csio_mb_issue(hw, mbp)) { | |
988 | csio_err(hw, "Issue of BYE command failed\n"); | |
989 | mempool_free(mbp, hw->mb_mempool); | |
990 | return -EINVAL; | |
991 | } | |
992 | ||
993 | retval = csio_mb_fw_retval(mbp); | |
994 | if (retval != FW_SUCCESS) { | |
995 | mempool_free(mbp, hw->mb_mempool); | |
996 | return -EINVAL; | |
997 | } | |
998 | ||
999 | mempool_free(mbp, hw->mb_mempool); | |
1000 | ||
1001 | return 0; | |
1002 | } | |
1003 | ||
1004 | /* | |
1005 | * csio_do_reset- Perform the device reset. | |
1006 | * @hw: HW module | |
1007 | * @fw_rst: FW reset | |
1008 | * | |
1009 | * If fw_rst is set, issues FW reset mbox cmd otherwise | |
1010 | * does PIO reset. | |
1011 | * Performs reset of the function. | |
1012 | */ | |
1013 | static int | |
1014 | csio_do_reset(struct csio_hw *hw, bool fw_rst) | |
1015 | { | |
1016 | struct csio_mb *mbp; | |
1017 | enum fw_retval retval; | |
1018 | ||
1019 | if (!fw_rst) { | |
1020 | /* PIO reset */ | |
0d804338 | 1021 | csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A); |
a3667aae NKI |
1022 | mdelay(2000); |
1023 | return 0; | |
1024 | } | |
1025 | ||
1026 | mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); | |
1027 | if (!mbp) { | |
1028 | CSIO_INC_STATS(hw, n_err_nomem); | |
1029 | return -ENOMEM; | |
1030 | } | |
1031 | ||
1032 | csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO, | |
0d804338 | 1033 | PIORSTMODE_F | PIORST_F, 0, NULL); |
a3667aae NKI |
1034 | |
1035 | if (csio_mb_issue(hw, mbp)) { | |
1036 | csio_err(hw, "Issue of RESET command failed.n"); | |
1037 | mempool_free(mbp, hw->mb_mempool); | |
1038 | return -EINVAL; | |
1039 | } | |
1040 | ||
1041 | retval = csio_mb_fw_retval(mbp); | |
1042 | if (retval != FW_SUCCESS) { | |
1043 | csio_err(hw, "RESET cmd failed with ret:0x%x.\n", retval); | |
1044 | mempool_free(mbp, hw->mb_mempool); | |
1045 | return -EINVAL; | |
1046 | } | |
1047 | ||
1048 | mempool_free(mbp, hw->mb_mempool); | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
1053 | static int | |
1054 | csio_hw_validate_caps(struct csio_hw *hw, struct csio_mb *mbp) | |
1055 | { | |
1056 | struct fw_caps_config_cmd *rsp = (struct fw_caps_config_cmd *)mbp->mb; | |
1057 | uint16_t caps; | |
1058 | ||
1059 | caps = ntohs(rsp->fcoecaps); | |
1060 | ||
1061 | if (!(caps & FW_CAPS_CONFIG_FCOE_INITIATOR)) { | |
1062 | csio_err(hw, "No FCoE Initiator capability in the firmware.\n"); | |
1063 | return -EINVAL; | |
1064 | } | |
1065 | ||
1066 | if (!(caps & FW_CAPS_CONFIG_FCOE_CTRL_OFLD)) { | |
1067 | csio_err(hw, "No FCoE Control Offload capability\n"); | |
1068 | return -EINVAL; | |
1069 | } | |
1070 | ||
1071 | return 0; | |
1072 | } | |
1073 | ||
1074 | /* | |
1075 | * csio_hw_fw_halt - issue a reset/halt to FW and put uP into RESET | |
1076 | * @hw: the HW module | |
1077 | * @mbox: mailbox to use for the FW RESET command (if desired) | |
1078 | * @force: force uP into RESET even if FW RESET command fails | |
1079 | * | |
1080 | * Issues a RESET command to firmware (if desired) with a HALT indication | |
1081 | * and then puts the microprocessor into RESET state. The RESET command | |
1082 | * will only be issued if a legitimate mailbox is provided (mbox <= | |
1083 | * PCIE_FW_MASTER_MASK). | |
1084 | * | |
1085 | * This is generally used in order for the host to safely manipulate the | |
1086 | * adapter without fear of conflicting with whatever the firmware might | |
1087 | * be doing. The only way out of this state is to RESTART the firmware | |
1088 | * ... | |
1089 | */ | |
1090 | static int | |
1091 | csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force) | |
1092 | { | |
1093 | enum fw_retval retval = 0; | |
1094 | ||
1095 | /* | |
1096 | * If a legitimate mailbox is provided, issue a RESET command | |
1097 | * with a HALT indication. | |
1098 | */ | |
f061de42 | 1099 | if (mbox <= PCIE_FW_MASTER_M) { |
a3667aae NKI |
1100 | struct csio_mb *mbp; |
1101 | ||
1102 | mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); | |
1103 | if (!mbp) { | |
1104 | CSIO_INC_STATS(hw, n_err_nomem); | |
1105 | return -ENOMEM; | |
1106 | } | |
1107 | ||
1108 | csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO, | |
0d804338 | 1109 | PIORSTMODE_F | PIORST_F, FW_RESET_CMD_HALT_F, |
a3667aae NKI |
1110 | NULL); |
1111 | ||
1112 | if (csio_mb_issue(hw, mbp)) { | |
1113 | csio_err(hw, "Issue of RESET command failed!\n"); | |
1114 | mempool_free(mbp, hw->mb_mempool); | |
1115 | return -EINVAL; | |
1116 | } | |
1117 | ||
1118 | retval = csio_mb_fw_retval(mbp); | |
1119 | mempool_free(mbp, hw->mb_mempool); | |
1120 | } | |
1121 | ||
1122 | /* | |
1123 | * Normally we won't complete the operation if the firmware RESET | |
1124 | * command fails but if our caller insists we'll go ahead and put the | |
1125 | * uP into RESET. This can be useful if the firmware is hung or even | |
1126 | * missing ... We'll have to take the risk of putting the uP into | |
1127 | * RESET without the cooperation of firmware in that case. | |
1128 | * | |
1129 | * We also force the firmware's HALT flag to be on in case we bypassed | |
1130 | * the firmware RESET command above or we're dealing with old firmware | |
1131 | * which doesn't have the HALT capability. This will serve as a flag | |
1132 | * for the incoming firmware to know that it's coming out of a HALT | |
1133 | * rather than a RESET ... if it's new enough to understand that ... | |
1134 | */ | |
1135 | if (retval == 0 || force) { | |
89c3a86c | 1136 | csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F); |
f061de42 HS |
1137 | csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F, |
1138 | PCIE_FW_HALT_F); | |
a3667aae NKI |
1139 | } |
1140 | ||
1141 | /* | |
1142 | * And we always return the result of the firmware RESET command | |
1143 | * even when we force the uP into RESET ... | |
1144 | */ | |
1145 | return retval ? -EINVAL : 0; | |
1146 | } | |
1147 | ||
1148 | /* | |
1149 | * csio_hw_fw_restart - restart the firmware by taking the uP out of RESET | |
1150 | * @hw: the HW module | |
1151 | * @reset: if we want to do a RESET to restart things | |
1152 | * | |
1153 | * Restart firmware previously halted by csio_hw_fw_halt(). On successful | |
1154 | * return the previous PF Master remains as the new PF Master and there | |
1155 | * is no need to issue a new HELLO command, etc. | |
1156 | * | |
1157 | * We do this in two ways: | |
1158 | * | |
1159 | * 1. If we're dealing with newer firmware we'll simply want to take | |
1160 | * the chip's microprocessor out of RESET. This will cause the | |
1161 | * firmware to start up from its start vector. And then we'll loop | |
1162 | * until the firmware indicates it's started again (PCIE_FW.HALT | |
1163 | * reset to 0) or we timeout. | |
1164 | * | |
1165 | * 2. If we're dealing with older firmware then we'll need to RESET | |
1166 | * the chip since older firmware won't recognize the PCIE_FW.HALT | |
1167 | * flag and automatically RESET itself on startup. | |
1168 | */ | |
1169 | static int | |
1170 | csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset) | |
1171 | { | |
1172 | if (reset) { | |
1173 | /* | |
1174 | * Since we're directing the RESET instead of the firmware | |
1175 | * doing it automatically, we need to clear the PCIE_FW.HALT | |
1176 | * bit. | |
1177 | */ | |
f061de42 | 1178 | csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F, 0); |
a3667aae NKI |
1179 | |
1180 | /* | |
1181 | * If we've been given a valid mailbox, first try to get the | |
1182 | * firmware to do the RESET. If that works, great and we can | |
1183 | * return success. Otherwise, if we haven't been given a | |
1184 | * valid mailbox or the RESET command failed, fall back to | |
1185 | * hitting the chip with a hammer. | |
1186 | */ | |
f061de42 | 1187 | if (mbox <= PCIE_FW_MASTER_M) { |
89c3a86c | 1188 | csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0); |
a3667aae NKI |
1189 | msleep(100); |
1190 | if (csio_do_reset(hw, true) == 0) | |
1191 | return 0; | |
1192 | } | |
1193 | ||
0d804338 | 1194 | csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A); |
a3667aae NKI |
1195 | msleep(2000); |
1196 | } else { | |
1197 | int ms; | |
1198 | ||
89c3a86c | 1199 | csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0); |
a3667aae | 1200 | for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { |
f061de42 | 1201 | if (!(csio_rd_reg32(hw, PCIE_FW_A) & PCIE_FW_HALT_F)) |
a3667aae NKI |
1202 | return 0; |
1203 | msleep(100); | |
1204 | ms += 100; | |
1205 | } | |
1206 | return -ETIMEDOUT; | |
1207 | } | |
1208 | return 0; | |
1209 | } | |
1210 | ||
1211 | /* | |
1212 | * csio_hw_fw_upgrade - perform all of the steps necessary to upgrade FW | |
1213 | * @hw: the HW module | |
1214 | * @mbox: mailbox to use for the FW RESET command (if desired) | |
1215 | * @fw_data: the firmware image to write | |
1216 | * @size: image size | |
1217 | * @force: force upgrade even if firmware doesn't cooperate | |
1218 | * | |
1219 | * Perform all of the steps necessary for upgrading an adapter's | |
1220 | * firmware image. Normally this requires the cooperation of the | |
1221 | * existing firmware in order to halt all existing activities | |
1222 | * but if an invalid mailbox token is passed in we skip that step | |
1223 | * (though we'll still put the adapter microprocessor into RESET in | |
1224 | * that case). | |
1225 | * | |
1226 | * On successful return the new firmware will have been loaded and | |
1227 | * the adapter will have been fully RESET losing all previous setup | |
1228 | * state. On unsuccessful return the adapter may be completely hosed ... | |
1229 | * positive errno indicates that the adapter is ~probably~ intact, a | |
1230 | * negative errno indicates that things are looking bad ... | |
1231 | */ | |
1232 | static int | |
1233 | csio_hw_fw_upgrade(struct csio_hw *hw, uint32_t mbox, | |
1234 | const u8 *fw_data, uint32_t size, int32_t force) | |
1235 | { | |
1236 | const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; | |
1237 | int reset, ret; | |
1238 | ||
1239 | ret = csio_hw_fw_halt(hw, mbox, force); | |
1240 | if (ret != 0 && !force) | |
1241 | return ret; | |
1242 | ||
1243 | ret = csio_hw_fw_dload(hw, (uint8_t *) fw_data, size); | |
1244 | if (ret != 0) | |
1245 | return ret; | |
1246 | ||
1247 | /* | |
1248 | * Older versions of the firmware don't understand the new | |
1249 | * PCIE_FW.HALT flag and so won't know to perform a RESET when they | |
1250 | * restart. So for newly loaded older firmware we'll have to do the | |
1251 | * RESET for it so it starts up on a clean slate. We can tell if | |
1252 | * the newly loaded firmware will handle this right by checking | |
1253 | * its header flags to see if it advertises the capability. | |
1254 | */ | |
1255 | reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); | |
1256 | return csio_hw_fw_restart(hw, mbox, reset); | |
1257 | } | |
1258 | ||
a3667aae NKI |
1259 | /* |
1260 | * csio_get_device_params - Get device parameters. | |
1261 | * @hw: HW module | |
1262 | * | |
1263 | */ | |
1264 | static int | |
1265 | csio_get_device_params(struct csio_hw *hw) | |
1266 | { | |
1267 | struct csio_wrm *wrm = csio_hw_to_wrm(hw); | |
1268 | struct csio_mb *mbp; | |
1269 | enum fw_retval retval; | |
1270 | u32 param[6]; | |
1271 | int i, j = 0; | |
1272 | ||
1273 | /* Initialize portids to -1 */ | |
1274 | for (i = 0; i < CSIO_MAX_PPORTS; i++) | |
1275 | hw->pport[i].portid = -1; | |
1276 | ||
1277 | mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); | |
1278 | if (!mbp) { | |
1279 | CSIO_INC_STATS(hw, n_err_nomem); | |
1280 | return -ENOMEM; | |
1281 | } | |
1282 | ||
1283 | /* Get port vec information. */ | |
1284 | param[0] = FW_PARAM_DEV(PORTVEC); | |
1285 | ||
1286 | /* Get Core clock. */ | |
1287 | param[1] = FW_PARAM_DEV(CCLK); | |
1288 | ||
1289 | /* Get EQ id start and end. */ | |
1290 | param[2] = FW_PARAM_PFVF(EQ_START); | |
1291 | param[3] = FW_PARAM_PFVF(EQ_END); | |
1292 | ||
1293 | /* Get IQ id start and end. */ | |
1294 | param[4] = FW_PARAM_PFVF(IQFLINT_START); | |
1295 | param[5] = FW_PARAM_PFVF(IQFLINT_END); | |
1296 | ||
1297 | csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0, | |
1298 | ARRAY_SIZE(param), param, NULL, false, NULL); | |
1299 | if (csio_mb_issue(hw, mbp)) { | |
1300 | csio_err(hw, "Issue of FW_PARAMS_CMD(read) failed!\n"); | |
1301 | mempool_free(mbp, hw->mb_mempool); | |
1302 | return -EINVAL; | |
1303 | } | |
1304 | ||
1305 | csio_mb_process_read_params_rsp(hw, mbp, &retval, | |
1306 | ARRAY_SIZE(param), param); | |
1307 | if (retval != FW_SUCCESS) { | |
1308 | csio_err(hw, "FW_PARAMS_CMD(read) failed with ret:0x%x!\n", | |
1309 | retval); | |
1310 | mempool_free(mbp, hw->mb_mempool); | |
1311 | return -EINVAL; | |
1312 | } | |
1313 | ||
1314 | /* cache the information. */ | |
1315 | hw->port_vec = param[0]; | |
1316 | hw->vpd.cclk = param[1]; | |
1317 | wrm->fw_eq_start = param[2]; | |
1318 | wrm->fw_iq_start = param[4]; | |
1319 | ||
1320 | /* Using FW configured max iqs & eqs */ | |
1321 | if ((hw->flags & CSIO_HWF_USING_SOFT_PARAMS) || | |
1322 | !csio_is_hw_master(hw)) { | |
1323 | hw->cfg_niq = param[5] - param[4] + 1; | |
1324 | hw->cfg_neq = param[3] - param[2] + 1; | |
1325 | csio_dbg(hw, "Using fwconfig max niqs %d neqs %d\n", | |
1326 | hw->cfg_niq, hw->cfg_neq); | |
1327 | } | |
1328 | ||
1329 | hw->port_vec &= csio_port_mask; | |
1330 | ||
1331 | hw->num_pports = hweight32(hw->port_vec); | |
1332 | ||
1333 | csio_dbg(hw, "Port vector: 0x%x, #ports: %d\n", | |
1334 | hw->port_vec, hw->num_pports); | |
1335 | ||
1336 | for (i = 0; i < hw->num_pports; i++) { | |
1337 | while ((hw->port_vec & (1 << j)) == 0) | |
1338 | j++; | |
1339 | hw->pport[i].portid = j++; | |
1340 | csio_dbg(hw, "Found Port:%d\n", hw->pport[i].portid); | |
1341 | } | |
1342 | mempool_free(mbp, hw->mb_mempool); | |
1343 | ||
1344 | return 0; | |
1345 | } | |
1346 | ||
1347 | ||
1348 | /* | |
1349 | * csio_config_device_caps - Get and set device capabilities. | |
1350 | * @hw: HW module | |
1351 | * | |
1352 | */ | |
1353 | static int | |
1354 | csio_config_device_caps(struct csio_hw *hw) | |
1355 | { | |
1356 | struct csio_mb *mbp; | |
1357 | enum fw_retval retval; | |
1358 | int rv = -EINVAL; | |
1359 | ||
1360 | mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); | |
1361 | if (!mbp) { | |
1362 | CSIO_INC_STATS(hw, n_err_nomem); | |
1363 | return -ENOMEM; | |
1364 | } | |
1365 | ||
1366 | /* Get device capabilities */ | |
1367 | csio_mb_caps_config(hw, mbp, CSIO_MB_DEFAULT_TMO, 0, 0, 0, 0, NULL); | |
1368 | ||
1369 | if (csio_mb_issue(hw, mbp)) { | |
1370 | csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD(r) failed!\n"); | |
1371 | goto out; | |
1372 | } | |
1373 | ||
1374 | retval = csio_mb_fw_retval(mbp); | |
1375 | if (retval != FW_SUCCESS) { | |
1376 | csio_err(hw, "FW_CAPS_CONFIG_CMD(r) returned %d!\n", retval); | |
1377 | goto out; | |
1378 | } | |
1379 | ||
1380 | /* Validate device capabilities */ | |
541c571f PM |
1381 | rv = csio_hw_validate_caps(hw, mbp); |
1382 | if (rv != 0) | |
a3667aae NKI |
1383 | goto out; |
1384 | ||
1385 | /* Don't config device capabilities if already configured */ | |
1386 | if (hw->fw_state == CSIO_DEV_STATE_INIT) { | |
1387 | rv = 0; | |
1388 | goto out; | |
1389 | } | |
1390 | ||
1391 | /* Write back desired device capabilities */ | |
1392 | csio_mb_caps_config(hw, mbp, CSIO_MB_DEFAULT_TMO, true, true, | |
1393 | false, true, NULL); | |
1394 | ||
1395 | if (csio_mb_issue(hw, mbp)) { | |
1396 | csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD(w) failed!\n"); | |
1397 | goto out; | |
1398 | } | |
1399 | ||
1400 | retval = csio_mb_fw_retval(mbp); | |
1401 | if (retval != FW_SUCCESS) { | |
1402 | csio_err(hw, "FW_CAPS_CONFIG_CMD(w) returned %d!\n", retval); | |
1403 | goto out; | |
1404 | } | |
1405 | ||
1406 | rv = 0; | |
1407 | out: | |
1408 | mempool_free(mbp, hw->mb_mempool); | |
1409 | return rv; | |
1410 | } | |
1411 | ||
a3667aae NKI |
1412 | /* |
1413 | * csio_enable_ports - Bring up all available ports. | |
1414 | * @hw: HW module. | |
1415 | * | |
1416 | */ | |
1417 | static int | |
1418 | csio_enable_ports(struct csio_hw *hw) | |
1419 | { | |
1420 | struct csio_mb *mbp; | |
1421 | enum fw_retval retval; | |
1422 | uint8_t portid; | |
1423 | int i; | |
1424 | ||
1425 | mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); | |
1426 | if (!mbp) { | |
1427 | CSIO_INC_STATS(hw, n_err_nomem); | |
1428 | return -ENOMEM; | |
1429 | } | |
1430 | ||
1431 | for (i = 0; i < hw->num_pports; i++) { | |
1432 | portid = hw->pport[i].portid; | |
1433 | ||
1434 | /* Read PORT information */ | |
1435 | csio_mb_port(hw, mbp, CSIO_MB_DEFAULT_TMO, portid, | |
1436 | false, 0, 0, NULL); | |
1437 | ||
1438 | if (csio_mb_issue(hw, mbp)) { | |
1439 | csio_err(hw, "failed to issue FW_PORT_CMD(r) port:%d\n", | |
1440 | portid); | |
1441 | mempool_free(mbp, hw->mb_mempool); | |
1442 | return -EINVAL; | |
1443 | } | |
1444 | ||
1445 | csio_mb_process_read_port_rsp(hw, mbp, &retval, | |
1446 | &hw->pport[i].pcap); | |
1447 | if (retval != FW_SUCCESS) { | |
1448 | csio_err(hw, "FW_PORT_CMD(r) port:%d failed: 0x%x\n", | |
1449 | portid, retval); | |
1450 | mempool_free(mbp, hw->mb_mempool); | |
1451 | return -EINVAL; | |
1452 | } | |
1453 | ||
1454 | /* Write back PORT information */ | |
1455 | csio_mb_port(hw, mbp, CSIO_MB_DEFAULT_TMO, portid, true, | |
1456 | (PAUSE_RX | PAUSE_TX), hw->pport[i].pcap, NULL); | |
1457 | ||
1458 | if (csio_mb_issue(hw, mbp)) { | |
1459 | csio_err(hw, "failed to issue FW_PORT_CMD(w) port:%d\n", | |
1460 | portid); | |
1461 | mempool_free(mbp, hw->mb_mempool); | |
1462 | return -EINVAL; | |
1463 | } | |
1464 | ||
1465 | retval = csio_mb_fw_retval(mbp); | |
1466 | if (retval != FW_SUCCESS) { | |
1467 | csio_err(hw, "FW_PORT_CMD(w) port:%d failed :0x%x\n", | |
1468 | portid, retval); | |
1469 | mempool_free(mbp, hw->mb_mempool); | |
1470 | return -EINVAL; | |
1471 | } | |
1472 | ||
1473 | } /* For all ports */ | |
1474 | ||
1475 | mempool_free(mbp, hw->mb_mempool); | |
1476 | ||
1477 | return 0; | |
1478 | } | |
1479 | ||
1480 | /* | |
1481 | * csio_get_fcoe_resinfo - Read fcoe fw resource info. | |
1482 | * @hw: HW module | |
1483 | * Issued with lock held. | |
1484 | */ | |
1485 | static int | |
1486 | csio_get_fcoe_resinfo(struct csio_hw *hw) | |
1487 | { | |
1488 | struct csio_fcoe_res_info *res_info = &hw->fres_info; | |
1489 | struct fw_fcoe_res_info_cmd *rsp; | |
1490 | struct csio_mb *mbp; | |
1491 | enum fw_retval retval; | |
1492 | ||
1493 | mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); | |
1494 | if (!mbp) { | |
1495 | CSIO_INC_STATS(hw, n_err_nomem); | |
1496 | return -ENOMEM; | |
1497 | } | |
1498 | ||
1499 | /* Get FCoE FW resource information */ | |
1500 | csio_fcoe_read_res_info_init_mb(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL); | |
1501 | ||
1502 | if (csio_mb_issue(hw, mbp)) { | |
1503 | csio_err(hw, "failed to issue FW_FCOE_RES_INFO_CMD\n"); | |
1504 | mempool_free(mbp, hw->mb_mempool); | |
1505 | return -EINVAL; | |
1506 | } | |
1507 | ||
1508 | rsp = (struct fw_fcoe_res_info_cmd *)(mbp->mb); | |
e2ac9628 | 1509 | retval = FW_CMD_RETVAL_G(ntohl(rsp->retval_len16)); |
a3667aae NKI |
1510 | if (retval != FW_SUCCESS) { |
1511 | csio_err(hw, "FW_FCOE_RES_INFO_CMD failed with ret x%x\n", | |
1512 | retval); | |
1513 | mempool_free(mbp, hw->mb_mempool); | |
1514 | return -EINVAL; | |
1515 | } | |
1516 | ||
1517 | res_info->e_d_tov = ntohs(rsp->e_d_tov); | |
1518 | res_info->r_a_tov_seq = ntohs(rsp->r_a_tov_seq); | |
1519 | res_info->r_a_tov_els = ntohs(rsp->r_a_tov_els); | |
1520 | res_info->r_r_tov = ntohs(rsp->r_r_tov); | |
1521 | res_info->max_xchgs = ntohl(rsp->max_xchgs); | |
1522 | res_info->max_ssns = ntohl(rsp->max_ssns); | |
1523 | res_info->used_xchgs = ntohl(rsp->used_xchgs); | |
1524 | res_info->used_ssns = ntohl(rsp->used_ssns); | |
1525 | res_info->max_fcfs = ntohl(rsp->max_fcfs); | |
1526 | res_info->max_vnps = ntohl(rsp->max_vnps); | |
1527 | res_info->used_fcfs = ntohl(rsp->used_fcfs); | |
1528 | res_info->used_vnps = ntohl(rsp->used_vnps); | |
1529 | ||
1530 | csio_dbg(hw, "max ssns:%d max xchgs:%d\n", res_info->max_ssns, | |
1531 | res_info->max_xchgs); | |
1532 | mempool_free(mbp, hw->mb_mempool); | |
1533 | ||
1534 | return 0; | |
1535 | } | |
1536 | ||
1537 | static int | |
1538 | csio_hw_check_fwconfig(struct csio_hw *hw, u32 *param) | |
1539 | { | |
1540 | struct csio_mb *mbp; | |
1541 | enum fw_retval retval; | |
1542 | u32 _param[1]; | |
1543 | ||
1544 | mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); | |
1545 | if (!mbp) { | |
1546 | CSIO_INC_STATS(hw, n_err_nomem); | |
1547 | return -ENOMEM; | |
1548 | } | |
1549 | ||
1550 | /* | |
1551 | * Find out whether we're dealing with a version of | |
1552 | * the firmware which has configuration file support. | |
1553 | */ | |
5167865a HS |
1554 | _param[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
1555 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); | |
a3667aae NKI |
1556 | |
1557 | csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0, | |
1558 | ARRAY_SIZE(_param), _param, NULL, false, NULL); | |
1559 | if (csio_mb_issue(hw, mbp)) { | |
1560 | csio_err(hw, "Issue of FW_PARAMS_CMD(read) failed!\n"); | |
1561 | mempool_free(mbp, hw->mb_mempool); | |
1562 | return -EINVAL; | |
1563 | } | |
1564 | ||
1565 | csio_mb_process_read_params_rsp(hw, mbp, &retval, | |
1566 | ARRAY_SIZE(_param), _param); | |
1567 | if (retval != FW_SUCCESS) { | |
1568 | csio_err(hw, "FW_PARAMS_CMD(read) failed with ret:0x%x!\n", | |
1569 | retval); | |
1570 | mempool_free(mbp, hw->mb_mempool); | |
1571 | return -EINVAL; | |
1572 | } | |
1573 | ||
1574 | mempool_free(mbp, hw->mb_mempool); | |
1575 | *param = _param[0]; | |
1576 | ||
1577 | return 0; | |
1578 | } | |
1579 | ||
1580 | static int | |
1581 | csio_hw_flash_config(struct csio_hw *hw, u32 *fw_cfg_param, char *path) | |
1582 | { | |
1583 | int ret = 0; | |
1584 | const struct firmware *cf; | |
1585 | struct pci_dev *pci_dev = hw->pdev; | |
1586 | struct device *dev = &pci_dev->dev; | |
a3667aae NKI |
1587 | unsigned int mtype = 0, maddr = 0; |
1588 | uint32_t *cfg_data; | |
1589 | int value_to_add = 0; | |
4bbd458e VP |
1590 | const char *fw_cfg_file; |
1591 | ||
1592 | if (csio_is_t5(pci_dev->device & CSIO_HW_CHIP_MASK)) | |
1593 | fw_cfg_file = FW_CFG_NAME_T5; | |
1594 | else | |
1595 | fw_cfg_file = FW_CFG_NAME_T6; | |
a3667aae | 1596 | |
4bbd458e | 1597 | if (request_firmware(&cf, fw_cfg_file, dev) < 0) { |
7cc16380 | 1598 | csio_err(hw, "could not find config file %s, err: %d\n", |
4bbd458e | 1599 | fw_cfg_file, ret); |
a3667aae NKI |
1600 | return -ENOENT; |
1601 | } | |
1602 | ||
1603 | if (cf->size%4 != 0) | |
1604 | value_to_add = 4 - (cf->size % 4); | |
1605 | ||
1606 | cfg_data = kzalloc(cf->size+value_to_add, GFP_KERNEL); | |
02db3db5 JJ |
1607 | if (cfg_data == NULL) { |
1608 | ret = -ENOMEM; | |
1609 | goto leave; | |
1610 | } | |
a3667aae NKI |
1611 | |
1612 | memcpy((void *)cfg_data, (const void *)cf->data, cf->size); | |
02db3db5 JJ |
1613 | if (csio_hw_check_fwconfig(hw, fw_cfg_param) != 0) { |
1614 | ret = -EINVAL; | |
1615 | goto leave; | |
1616 | } | |
a3667aae | 1617 | |
5167865a HS |
1618 | mtype = FW_PARAMS_PARAM_Y_G(*fw_cfg_param); |
1619 | maddr = FW_PARAMS_PARAM_Z_G(*fw_cfg_param) << 16; | |
a3667aae NKI |
1620 | |
1621 | ret = csio_memory_write(hw, mtype, maddr, | |
1622 | cf->size + value_to_add, cfg_data); | |
7cc16380 AB |
1623 | |
1624 | if ((ret == 0) && (value_to_add != 0)) { | |
1625 | union { | |
1626 | u32 word; | |
1627 | char buf[4]; | |
1628 | } last; | |
1629 | size_t size = cf->size & ~0x3; | |
1630 | int i; | |
1631 | ||
1632 | last.word = cfg_data[size >> 2]; | |
1633 | for (i = value_to_add; i < 4; i++) | |
1634 | last.buf[i] = 0; | |
1635 | ret = csio_memory_write(hw, mtype, maddr + size, 4, &last.word); | |
1636 | } | |
a3667aae | 1637 | if (ret == 0) { |
4bbd458e VP |
1638 | csio_info(hw, "config file upgraded to %s\n", fw_cfg_file); |
1639 | snprintf(path, 64, "%s%s", "/lib/firmware/", fw_cfg_file); | |
a3667aae NKI |
1640 | } |
1641 | ||
02db3db5 | 1642 | leave: |
a3667aae NKI |
1643 | kfree(cfg_data); |
1644 | release_firmware(cf); | |
a3667aae NKI |
1645 | return ret; |
1646 | } | |
1647 | ||
1648 | /* | |
1649 | * HW initialization: contact FW, obtain config, perform basic init. | |
1650 | * | |
1651 | * If the firmware we're dealing with has Configuration File support, then | |
1652 | * we use that to perform all configuration -- either using the configuration | |
1653 | * file stored in flash on the adapter or using a filesystem-local file | |
1654 | * if available. | |
1655 | * | |
1656 | * If we don't have configuration file support in the firmware, then we'll | |
1657 | * have to set things up the old fashioned way with hard-coded register | |
1658 | * writes and firmware commands ... | |
1659 | */ | |
1660 | ||
1661 | /* | |
1662 | * Attempt to initialize the HW via a Firmware Configuration File. | |
1663 | */ | |
1664 | static int | |
1665 | csio_hw_use_fwconfig(struct csio_hw *hw, int reset, u32 *fw_cfg_param) | |
1666 | { | |
216ce69c PM |
1667 | struct csio_mb *mbp = NULL; |
1668 | struct fw_caps_config_cmd *caps_cmd; | |
a3667aae | 1669 | unsigned int mtype, maddr; |
216ce69c | 1670 | int rv = -EINVAL; |
7cc16380 | 1671 | uint32_t finiver = 0, finicsum = 0, cfcsum = 0; |
a3667aae | 1672 | char path[64]; |
216ce69c | 1673 | char *config_name = NULL; |
a3667aae NKI |
1674 | |
1675 | /* | |
1676 | * Reset device if necessary | |
1677 | */ | |
1678 | if (reset) { | |
1679 | rv = csio_do_reset(hw, true); | |
1680 | if (rv != 0) | |
1681 | goto bye; | |
1682 | } | |
1683 | ||
1684 | /* | |
1685 | * If we have a configuration file in host , | |
1686 | * then use that. Otherwise, use the configuration file stored | |
1687 | * in the HW flash ... | |
1688 | */ | |
1689 | spin_unlock_irq(&hw->lock); | |
1690 | rv = csio_hw_flash_config(hw, fw_cfg_param, path); | |
1691 | spin_lock_irq(&hw->lock); | |
1692 | if (rv != 0) { | |
216ce69c PM |
1693 | /* |
1694 | * config file was not found. Use default | |
1695 | * config file from flash. | |
1696 | */ | |
1697 | config_name = "On FLASH"; | |
1698 | mtype = FW_MEMTYPE_CF_FLASH; | |
1699 | maddr = hw->chip_ops->chip_flash_cfg_addr(hw); | |
a3667aae | 1700 | } else { |
216ce69c | 1701 | config_name = path; |
5167865a HS |
1702 | mtype = FW_PARAMS_PARAM_Y_G(*fw_cfg_param); |
1703 | maddr = FW_PARAMS_PARAM_Z_G(*fw_cfg_param) << 16; | |
a3667aae NKI |
1704 | } |
1705 | ||
216ce69c PM |
1706 | mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); |
1707 | if (!mbp) { | |
1708 | CSIO_INC_STATS(hw, n_err_nomem); | |
1709 | return -ENOMEM; | |
1710 | } | |
1711 | /* | |
1712 | * Tell the firmware to process the indicated Configuration File. | |
1713 | * If there are no errors and the caller has provided return value | |
1714 | * pointers for the [fini] section version, checksum and computed | |
1715 | * checksum, pass those back to the caller. | |
1716 | */ | |
1717 | caps_cmd = (struct fw_caps_config_cmd *)(mbp->mb); | |
1718 | CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1); | |
1719 | caps_cmd->op_to_write = | |
1720 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | | |
1721 | FW_CMD_REQUEST_F | | |
1722 | FW_CMD_READ_F); | |
1723 | caps_cmd->cfvalid_to_len16 = | |
1724 | htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | | |
1725 | FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | | |
1726 | FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | | |
1727 | FW_LEN16(*caps_cmd)); | |
1728 | ||
1729 | if (csio_mb_issue(hw, mbp)) { | |
1730 | rv = -EINVAL; | |
1731 | goto bye; | |
1732 | } | |
1733 | ||
1734 | rv = csio_mb_fw_retval(mbp); | |
1735 | /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware | |
1736 | * Configuration File in FLASH), our last gasp effort is to use the | |
1737 | * Firmware Configuration File which is embedded in the | |
1738 | * firmware. A very few early versions of the firmware didn't | |
1739 | * have one embedded but we can ignore those. | |
1740 | */ | |
1741 | if (rv == ENOENT) { | |
1742 | CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1); | |
1743 | caps_cmd->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | | |
1744 | FW_CMD_REQUEST_F | | |
1745 | FW_CMD_READ_F); | |
1746 | caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd)); | |
1747 | ||
1748 | if (csio_mb_issue(hw, mbp)) { | |
1749 | rv = -EINVAL; | |
1750 | goto bye; | |
1751 | } | |
1752 | ||
1753 | rv = csio_mb_fw_retval(mbp); | |
1754 | config_name = "Firmware Default"; | |
1755 | } | |
1756 | if (rv != FW_SUCCESS) | |
1757 | goto bye; | |
1758 | ||
1759 | finiver = ntohl(caps_cmd->finiver); | |
1760 | finicsum = ntohl(caps_cmd->finicsum); | |
1761 | cfcsum = ntohl(caps_cmd->cfcsum); | |
a3667aae NKI |
1762 | |
1763 | /* | |
216ce69c | 1764 | * And now tell the firmware to use the configuration we just loaded. |
a3667aae | 1765 | */ |
216ce69c PM |
1766 | caps_cmd->op_to_write = |
1767 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | | |
1768 | FW_CMD_REQUEST_F | | |
1769 | FW_CMD_WRITE_F); | |
1770 | caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd)); | |
1771 | ||
1772 | if (csio_mb_issue(hw, mbp)) { | |
1773 | rv = -EINVAL; | |
a3667aae | 1774 | goto bye; |
216ce69c | 1775 | } |
a3667aae | 1776 | |
216ce69c PM |
1777 | rv = csio_mb_fw_retval(mbp); |
1778 | if (rv != FW_SUCCESS) { | |
1779 | csio_dbg(hw, "FW_CAPS_CONFIG_CMD returned %d!\n", rv); | |
1780 | goto bye; | |
1781 | } | |
a3667aae NKI |
1782 | |
1783 | if (finicsum != cfcsum) { | |
1784 | csio_warn(hw, | |
1785 | "Config File checksum mismatch: csum=%#x, computed=%#x\n", | |
1786 | finicsum, cfcsum); | |
a3667aae NKI |
1787 | } |
1788 | ||
216ce69c | 1789 | /* Validate device capabilities */ |
541c571f PM |
1790 | rv = csio_hw_validate_caps(hw, mbp); |
1791 | if (rv != 0) | |
216ce69c | 1792 | goto bye; |
a351e40b VP |
1793 | |
1794 | mempool_free(mbp, hw->mb_mempool); | |
1795 | mbp = NULL; | |
1796 | ||
a3667aae NKI |
1797 | /* |
1798 | * Note that we're operating with parameters | |
1799 | * not supplied by the driver, rather than from hard-wired | |
1800 | * initialization constants buried in the driver. | |
1801 | */ | |
1802 | hw->flags |= CSIO_HWF_USING_SOFT_PARAMS; | |
1803 | ||
1804 | /* device parameters */ | |
1805 | rv = csio_get_device_params(hw); | |
1806 | if (rv != 0) | |
1807 | goto bye; | |
1808 | ||
1809 | /* Configure SGE */ | |
1810 | csio_wr_sge_init(hw); | |
1811 | ||
1812 | /* | |
1813 | * And finally tell the firmware to initialize itself using the | |
1814 | * parameters from the Configuration File. | |
1815 | */ | |
1816 | /* Post event to notify completion of configuration */ | |
1817 | csio_post_event(&hw->sm, CSIO_HWE_INIT); | |
1818 | ||
216ce69c PM |
1819 | csio_info(hw, "Successfully configure using Firmware " |
1820 | "Configuration File %s, version %#x, computed checksum %#x\n", | |
1821 | config_name, finiver, cfcsum); | |
a3667aae NKI |
1822 | return 0; |
1823 | ||
1824 | /* | |
1825 | * Something bad happened. Return the error ... | |
1826 | */ | |
1827 | bye: | |
216ce69c PM |
1828 | if (mbp) |
1829 | mempool_free(mbp, hw->mb_mempool); | |
a3667aae | 1830 | hw->flags &= ~CSIO_HWF_USING_SOFT_PARAMS; |
216ce69c | 1831 | csio_warn(hw, "Configuration file error %d\n", rv); |
a3667aae NKI |
1832 | return rv; |
1833 | } | |
1834 | ||
f40e74ff PM |
1835 | /* Is the given firmware API compatible with the one the driver was compiled |
1836 | * with? | |
1837 | */ | |
1838 | static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) | |
1839 | { | |
1840 | ||
1841 | /* short circuit if it's the exact same firmware version */ | |
1842 | if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) | |
1843 | return 1; | |
1844 | ||
1845 | #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) | |
1846 | if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && | |
1847 | SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe)) | |
1848 | return 1; | |
1849 | #undef SAME_INTF | |
1850 | ||
1851 | return 0; | |
1852 | } | |
1853 | ||
1854 | /* The firmware in the filesystem is usable, but should it be installed? | |
1855 | * This routine explains itself in detail if it indicates the filesystem | |
1856 | * firmware should be installed. | |
1857 | */ | |
1858 | static int csio_should_install_fs_fw(struct csio_hw *hw, int card_fw_usable, | |
1859 | int k, int c) | |
1860 | { | |
1861 | const char *reason; | |
1862 | ||
1863 | if (!card_fw_usable) { | |
1864 | reason = "incompatible or unusable"; | |
1865 | goto install; | |
1866 | } | |
1867 | ||
1868 | if (k > c) { | |
1869 | reason = "older than the version supported with this driver"; | |
1870 | goto install; | |
1871 | } | |
1872 | ||
1873 | return 0; | |
1874 | ||
1875 | install: | |
1876 | csio_err(hw, "firmware on card (%u.%u.%u.%u) is %s, " | |
1877 | "installing firmware %u.%u.%u.%u on card.\n", | |
1878 | FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c), | |
1879 | FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason, | |
1880 | FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), | |
1881 | FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); | |
1882 | ||
1883 | return 1; | |
1884 | } | |
1885 | ||
1886 | static struct fw_info fw_info_array[] = { | |
1887 | { | |
1888 | .chip = CHELSIO_T5, | |
1889 | .fs_name = FW_CFG_NAME_T5, | |
1890 | .fw_mod_name = FW_FNAME_T5, | |
1891 | .fw_hdr = { | |
1892 | .chip = FW_HDR_CHIP_T5, | |
1893 | .fw_ver = __cpu_to_be32(FW_VERSION(T5)), | |
1894 | .intfver_nic = FW_INTFVER(T5, NIC), | |
1895 | .intfver_vnic = FW_INTFVER(T5, VNIC), | |
1896 | .intfver_ri = FW_INTFVER(T5, RI), | |
1897 | .intfver_iscsi = FW_INTFVER(T5, ISCSI), | |
1898 | .intfver_fcoe = FW_INTFVER(T5, FCOE), | |
1899 | }, | |
4bbd458e VP |
1900 | }, { |
1901 | .chip = CHELSIO_T6, | |
1902 | .fs_name = FW_CFG_NAME_T6, | |
1903 | .fw_mod_name = FW_FNAME_T6, | |
1904 | .fw_hdr = { | |
1905 | .chip = FW_HDR_CHIP_T6, | |
1906 | .fw_ver = __cpu_to_be32(FW_VERSION(T6)), | |
1907 | .intfver_nic = FW_INTFVER(T6, NIC), | |
1908 | .intfver_vnic = FW_INTFVER(T6, VNIC), | |
1909 | .intfver_ri = FW_INTFVER(T6, RI), | |
1910 | .intfver_iscsi = FW_INTFVER(T6, ISCSI), | |
1911 | .intfver_fcoe = FW_INTFVER(T6, FCOE), | |
1912 | }, | |
f40e74ff PM |
1913 | } |
1914 | }; | |
1915 | ||
1916 | static struct fw_info *find_fw_info(int chip) | |
1917 | { | |
1918 | int i; | |
1919 | ||
1920 | for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { | |
1921 | if (fw_info_array[i].chip == chip) | |
1922 | return &fw_info_array[i]; | |
1923 | } | |
1924 | return NULL; | |
1925 | } | |
1926 | ||
78890ed7 | 1927 | static int csio_hw_prep_fw(struct csio_hw *hw, struct fw_info *fw_info, |
f40e74ff PM |
1928 | const u8 *fw_data, unsigned int fw_size, |
1929 | struct fw_hdr *card_fw, enum csio_dev_state state, | |
1930 | int *reset) | |
1931 | { | |
1932 | int ret, card_fw_usable, fs_fw_usable; | |
1933 | const struct fw_hdr *fs_fw; | |
1934 | const struct fw_hdr *drv_fw; | |
1935 | ||
1936 | drv_fw = &fw_info->fw_hdr; | |
1937 | ||
1938 | /* Read the header of the firmware on the card */ | |
1939 | ret = csio_hw_read_flash(hw, FLASH_FW_START, | |
1940 | sizeof(*card_fw) / sizeof(uint32_t), | |
1941 | (uint32_t *)card_fw, 1); | |
1942 | if (ret == 0) { | |
1943 | card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw); | |
1944 | } else { | |
1945 | csio_err(hw, | |
1946 | "Unable to read card's firmware header: %d\n", ret); | |
1947 | card_fw_usable = 0; | |
1948 | } | |
1949 | ||
1950 | if (fw_data != NULL) { | |
1951 | fs_fw = (const void *)fw_data; | |
1952 | fs_fw_usable = fw_compatible(drv_fw, fs_fw); | |
1953 | } else { | |
1954 | fs_fw = NULL; | |
1955 | fs_fw_usable = 0; | |
1956 | } | |
1957 | ||
1958 | if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && | |
1959 | (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) { | |
1960 | /* Common case: the firmware on the card is an exact match and | |
1961 | * the filesystem one is an exact match too, or the filesystem | |
1962 | * one is absent/incompatible. | |
1963 | */ | |
1964 | } else if (fs_fw_usable && state == CSIO_DEV_STATE_UNINIT && | |
1965 | csio_should_install_fs_fw(hw, card_fw_usable, | |
1966 | be32_to_cpu(fs_fw->fw_ver), | |
1967 | be32_to_cpu(card_fw->fw_ver))) { | |
1968 | ret = csio_hw_fw_upgrade(hw, hw->pfn, fw_data, | |
1969 | fw_size, 0); | |
1970 | if (ret != 0) { | |
1971 | csio_err(hw, | |
1972 | "failed to install firmware: %d\n", ret); | |
1973 | goto bye; | |
1974 | } | |
1975 | ||
1976 | /* Installed successfully, update the cached header too. */ | |
1977 | memcpy(card_fw, fs_fw, sizeof(*card_fw)); | |
1978 | card_fw_usable = 1; | |
1979 | *reset = 0; /* already reset as part of load_fw */ | |
1980 | } | |
1981 | ||
1982 | if (!card_fw_usable) { | |
1983 | uint32_t d, c, k; | |
1984 | ||
1985 | d = be32_to_cpu(drv_fw->fw_ver); | |
1986 | c = be32_to_cpu(card_fw->fw_ver); | |
1987 | k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0; | |
1988 | ||
1989 | csio_err(hw, "Cannot find a usable firmware: " | |
1990 | "chip state %d, " | |
1991 | "driver compiled with %d.%d.%d.%d, " | |
1992 | "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n", | |
1993 | state, | |
1994 | FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d), | |
1995 | FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d), | |
1996 | FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c), | |
1997 | FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), | |
1998 | FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), | |
1999 | FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); | |
2000 | ret = EINVAL; | |
2001 | goto bye; | |
2002 | } | |
2003 | ||
2004 | /* We're using whatever's on the card and it's known to be good. */ | |
2005 | hw->fwrev = be32_to_cpu(card_fw->fw_ver); | |
2006 | hw->tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); | |
2007 | ||
2008 | bye: | |
2009 | return ret; | |
2010 | } | |
2011 | ||
a3667aae NKI |
2012 | /* |
2013 | * Returns -EINVAL if attempts to flash the firmware failed | |
2014 | * else returns 0, | |
2015 | * if flashing was not attempted because the card had the | |
2016 | * latest firmware ECANCELED is returned | |
2017 | */ | |
2018 | static int | |
f40e74ff | 2019 | csio_hw_flash_fw(struct csio_hw *hw, int *reset) |
a3667aae NKI |
2020 | { |
2021 | int ret = -ECANCELED; | |
2022 | const struct firmware *fw; | |
f40e74ff PM |
2023 | struct fw_info *fw_info; |
2024 | struct fw_hdr *card_fw; | |
a3667aae NKI |
2025 | struct pci_dev *pci_dev = hw->pdev; |
2026 | struct device *dev = &pci_dev->dev ; | |
f40e74ff PM |
2027 | const u8 *fw_data = NULL; |
2028 | unsigned int fw_size = 0; | |
4bbd458e | 2029 | const char *fw_bin_file; |
f40e74ff PM |
2030 | |
2031 | /* This is the firmware whose headers the driver was compiled | |
2032 | * against | |
2033 | */ | |
2034 | fw_info = find_fw_info(CHELSIO_CHIP_VERSION(hw->chip_id)); | |
2035 | if (fw_info == NULL) { | |
2036 | csio_err(hw, | |
2037 | "unable to get firmware info for chip %d.\n", | |
2038 | CHELSIO_CHIP_VERSION(hw->chip_id)); | |
2039 | return -EINVAL; | |
2040 | } | |
a3667aae | 2041 | |
4bbd458e VP |
2042 | if (csio_is_t5(pci_dev->device & CSIO_HW_CHIP_MASK)) |
2043 | fw_bin_file = FW_FNAME_T5; | |
2044 | else | |
2045 | fw_bin_file = FW_FNAME_T6; | |
2046 | ||
2047 | if (request_firmware(&fw, fw_bin_file, dev) < 0) { | |
7cc16380 | 2048 | csio_err(hw, "could not find firmware image %s, err: %d\n", |
4bbd458e | 2049 | fw_bin_file, ret); |
216ce69c PM |
2050 | } else { |
2051 | fw_data = fw->data; | |
2052 | fw_size = fw->size; | |
a3667aae NKI |
2053 | } |
2054 | ||
f40e74ff PM |
2055 | /* allocate memory to read the header of the firmware on the |
2056 | * card | |
a3667aae | 2057 | */ |
f40e74ff PM |
2058 | card_fw = kmalloc(sizeof(*card_fw), GFP_KERNEL); |
2059 | ||
f40e74ff PM |
2060 | /* upgrade FW logic */ |
2061 | ret = csio_hw_prep_fw(hw, fw_info, fw_data, fw_size, card_fw, | |
2062 | hw->fw_state, reset); | |
a3667aae | 2063 | |
f40e74ff PM |
2064 | /* Cleaning up */ |
2065 | if (fw != NULL) | |
2066 | release_firmware(fw); | |
2067 | kfree(card_fw); | |
a3667aae NKI |
2068 | return ret; |
2069 | } | |
2070 | ||
96e6c633 VP |
2071 | static int csio_hw_check_fwver(struct csio_hw *hw) |
2072 | { | |
2073 | if (csio_is_t6(hw->pdev->device & CSIO_HW_CHIP_MASK) && | |
2074 | (hw->fwrev < CSIO_MIN_T6_FW)) { | |
2075 | csio_hw_print_fw_version(hw, "T6 unsupported fw"); | |
2076 | return -1; | |
2077 | } | |
2078 | ||
2079 | return 0; | |
2080 | } | |
2081 | ||
a3667aae NKI |
2082 | /* |
2083 | * csio_hw_configure - Configure HW | |
2084 | * @hw - HW module | |
2085 | * | |
2086 | */ | |
2087 | static void | |
2088 | csio_hw_configure(struct csio_hw *hw) | |
2089 | { | |
2090 | int reset = 1; | |
2091 | int rv; | |
2092 | u32 param[1]; | |
2093 | ||
2094 | rv = csio_hw_dev_ready(hw); | |
2095 | if (rv != 0) { | |
2096 | CSIO_INC_STATS(hw, n_err_fatal); | |
2097 | csio_post_event(&hw->sm, CSIO_HWE_FATAL); | |
2098 | goto out; | |
2099 | } | |
2100 | ||
2101 | /* HW version */ | |
0d804338 | 2102 | hw->chip_ver = (char)csio_rd_reg32(hw, PL_REV_A); |
a3667aae NKI |
2103 | |
2104 | /* Needed for FW download */ | |
2105 | rv = csio_hw_get_flash_params(hw); | |
2106 | if (rv != 0) { | |
2107 | csio_err(hw, "Failed to get serial flash params rv:%d\n", rv); | |
2108 | csio_post_event(&hw->sm, CSIO_HWE_FATAL); | |
2109 | goto out; | |
2110 | } | |
2111 | ||
ad4d35f8 YW |
2112 | /* Set PCIe completion timeout to 4 seconds */ |
2113 | if (pci_is_pcie(hw->pdev)) | |
2114 | pcie_capability_clear_and_set_word(hw->pdev, PCI_EXP_DEVCTL2, | |
2115 | PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd); | |
a3667aae | 2116 | |
7cc16380 | 2117 | hw->chip_ops->chip_set_mem_win(hw, MEMWIN_CSIOSTOR); |
a3667aae NKI |
2118 | |
2119 | rv = csio_hw_get_fw_version(hw, &hw->fwrev); | |
2120 | if (rv != 0) | |
2121 | goto out; | |
2122 | ||
2123 | csio_hw_print_fw_version(hw, "Firmware revision"); | |
2124 | ||
2125 | rv = csio_do_hello(hw, &hw->fw_state); | |
2126 | if (rv != 0) { | |
2127 | CSIO_INC_STATS(hw, n_err_fatal); | |
2128 | csio_post_event(&hw->sm, CSIO_HWE_FATAL); | |
2129 | goto out; | |
2130 | } | |
2131 | ||
2132 | /* Read vpd */ | |
2133 | rv = csio_hw_get_vpd_params(hw, &hw->vpd); | |
2134 | if (rv != 0) | |
2135 | goto out; | |
2136 | ||
f40e74ff PM |
2137 | csio_hw_get_fw_version(hw, &hw->fwrev); |
2138 | csio_hw_get_tp_version(hw, &hw->tp_vers); | |
a3667aae | 2139 | if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) { |
a3667aae NKI |
2140 | |
2141 | /* Do firmware update */ | |
f40e74ff PM |
2142 | spin_unlock_irq(&hw->lock); |
2143 | rv = csio_hw_flash_fw(hw, &reset); | |
2144 | spin_lock_irq(&hw->lock); | |
2145 | ||
2146 | if (rv != 0) | |
2147 | goto out; | |
a3667aae | 2148 | |
96e6c633 VP |
2149 | rv = csio_hw_check_fwver(hw); |
2150 | if (rv < 0) | |
2151 | goto out; | |
2152 | ||
216ce69c PM |
2153 | /* If the firmware doesn't support Configuration Files, |
2154 | * return an error. | |
a3667aae | 2155 | */ |
216ce69c PM |
2156 | rv = csio_hw_check_fwconfig(hw, param); |
2157 | if (rv != 0) { | |
2158 | csio_info(hw, "Firmware doesn't support " | |
2159 | "Firmware Configuration files\n"); | |
2160 | goto out; | |
a3667aae NKI |
2161 | } |
2162 | ||
216ce69c PM |
2163 | /* The firmware provides us with a memory buffer where we can |
2164 | * load a Configuration File from the host if we want to | |
2165 | * override the Configuration File in flash. | |
2166 | */ | |
2167 | rv = csio_hw_use_fwconfig(hw, reset, param); | |
2168 | if (rv == -ENOENT) { | |
2169 | csio_info(hw, "Could not initialize " | |
2170 | "adapter, error%d\n", rv); | |
a3667aae | 2171 | goto out; |
216ce69c PM |
2172 | } |
2173 | if (rv != 0) { | |
2174 | csio_info(hw, "Could not initialize " | |
2175 | "adapter, error%d\n", rv); | |
2176 | goto out; | |
2177 | } | |
a3667aae NKI |
2178 | |
2179 | } else { | |
96e6c633 VP |
2180 | rv = csio_hw_check_fwver(hw); |
2181 | if (rv < 0) | |
2182 | goto out; | |
2183 | ||
a3667aae NKI |
2184 | if (hw->fw_state == CSIO_DEV_STATE_INIT) { |
2185 | ||
7cc16380 AB |
2186 | hw->flags |= CSIO_HWF_USING_SOFT_PARAMS; |
2187 | ||
a3667aae NKI |
2188 | /* device parameters */ |
2189 | rv = csio_get_device_params(hw); | |
2190 | if (rv != 0) | |
2191 | goto out; | |
2192 | ||
2193 | /* Get device capabilities */ | |
2194 | rv = csio_config_device_caps(hw); | |
2195 | if (rv != 0) | |
2196 | goto out; | |
2197 | ||
2198 | /* Configure SGE */ | |
2199 | csio_wr_sge_init(hw); | |
2200 | ||
2201 | /* Post event to notify completion of configuration */ | |
2202 | csio_post_event(&hw->sm, CSIO_HWE_INIT); | |
2203 | goto out; | |
2204 | } | |
2205 | } /* if not master */ | |
2206 | ||
2207 | out: | |
2208 | return; | |
2209 | } | |
2210 | ||
2211 | /* | |
2212 | * csio_hw_initialize - Initialize HW | |
2213 | * @hw - HW module | |
2214 | * | |
2215 | */ | |
2216 | static void | |
2217 | csio_hw_initialize(struct csio_hw *hw) | |
2218 | { | |
2219 | struct csio_mb *mbp; | |
2220 | enum fw_retval retval; | |
2221 | int rv; | |
2222 | int i; | |
2223 | ||
2224 | if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) { | |
2225 | mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); | |
2226 | if (!mbp) | |
2227 | goto out; | |
2228 | ||
2229 | csio_mb_initialize(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL); | |
2230 | ||
2231 | if (csio_mb_issue(hw, mbp)) { | |
2232 | csio_err(hw, "Issue of FW_INITIALIZE_CMD failed!\n"); | |
2233 | goto free_and_out; | |
2234 | } | |
2235 | ||
2236 | retval = csio_mb_fw_retval(mbp); | |
2237 | if (retval != FW_SUCCESS) { | |
2238 | csio_err(hw, "FW_INITIALIZE_CMD returned 0x%x!\n", | |
2239 | retval); | |
2240 | goto free_and_out; | |
2241 | } | |
2242 | ||
2243 | mempool_free(mbp, hw->mb_mempool); | |
2244 | } | |
2245 | ||
2246 | rv = csio_get_fcoe_resinfo(hw); | |
2247 | if (rv != 0) { | |
2248 | csio_err(hw, "Failed to read fcoe resource info: %d\n", rv); | |
2249 | goto out; | |
2250 | } | |
2251 | ||
2252 | spin_unlock_irq(&hw->lock); | |
2253 | rv = csio_config_queues(hw); | |
2254 | spin_lock_irq(&hw->lock); | |
2255 | ||
2256 | if (rv != 0) { | |
2257 | csio_err(hw, "Config of queues failed!: %d\n", rv); | |
2258 | goto out; | |
2259 | } | |
2260 | ||
2261 | for (i = 0; i < hw->num_pports; i++) | |
2262 | hw->pport[i].mod_type = FW_PORT_MOD_TYPE_NA; | |
2263 | ||
2264 | if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) { | |
2265 | rv = csio_enable_ports(hw); | |
2266 | if (rv != 0) { | |
2267 | csio_err(hw, "Failed to enable ports: %d\n", rv); | |
2268 | goto out; | |
2269 | } | |
2270 | } | |
2271 | ||
2272 | csio_post_event(&hw->sm, CSIO_HWE_INIT_DONE); | |
2273 | return; | |
2274 | ||
2275 | free_and_out: | |
2276 | mempool_free(mbp, hw->mb_mempool); | |
2277 | out: | |
2278 | return; | |
2279 | } | |
2280 | ||
0d804338 | 2281 | #define PF_INTR_MASK (PFSW_F | PFCIM_F) |
a3667aae NKI |
2282 | |
2283 | /* | |
2284 | * csio_hw_intr_enable - Enable HW interrupts | |
2285 | * @hw: Pointer to HW module. | |
2286 | * | |
2287 | * Enable interrupts in HW registers. | |
2288 | */ | |
2289 | static void | |
2290 | csio_hw_intr_enable(struct csio_hw *hw) | |
2291 | { | |
2292 | uint16_t vec = (uint16_t)csio_get_mb_intr_idx(csio_hw_to_mbm(hw)); | |
4bbd458e | 2293 | u32 pf = 0; |
0d804338 | 2294 | uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE_A); |
a3667aae | 2295 | |
4bbd458e VP |
2296 | if (csio_is_t5(hw->pdev->device & CSIO_HW_CHIP_MASK)) |
2297 | pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A)); | |
2298 | else | |
2299 | pf = T6_SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A)); | |
2300 | ||
a3667aae NKI |
2301 | /* |
2302 | * Set aivec for MSI/MSIX. PCIE_PF_CFG.INTXType is set up | |
2303 | * by FW, so do nothing for INTX. | |
2304 | */ | |
2305 | if (hw->intr_mode == CSIO_IM_MSIX) | |
f061de42 HS |
2306 | csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A), |
2307 | AIVEC_V(AIVEC_M), vec); | |
a3667aae | 2308 | else if (hw->intr_mode == CSIO_IM_MSI) |
f061de42 HS |
2309 | csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A), |
2310 | AIVEC_V(AIVEC_M), 0); | |
a3667aae | 2311 | |
0d804338 | 2312 | csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE_A)); |
a3667aae NKI |
2313 | |
2314 | /* Turn on MB interrupts - this will internally flush PIO as well */ | |
2315 | csio_mb_intr_enable(hw); | |
2316 | ||
2317 | /* These are common registers - only a master can modify them */ | |
2318 | if (csio_is_hw_master(hw)) { | |
2319 | /* | |
2320 | * Disable the Serial FLASH interrupt, if enabled! | |
2321 | */ | |
0d804338 HS |
2322 | pl &= (~SF_F); |
2323 | csio_wr_reg32(hw, pl, PL_INT_ENABLE_A); | |
a3667aae | 2324 | |
f612b815 HS |
2325 | csio_wr_reg32(hw, ERR_CPL_EXCEED_IQE_SIZE_F | |
2326 | EGRESS_SIZE_ERR_F | ERR_INVALID_CIDX_INC_F | | |
2327 | ERR_CPL_OPCODE_0_F | ERR_DROPPED_DB_F | | |
2328 | ERR_DATA_CPL_ON_HIGH_QID1_F | | |
2329 | ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F | | |
2330 | ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F | | |
2331 | ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F | | |
2332 | ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F, | |
2333 | SGE_INT_ENABLE3_A); | |
0d804338 | 2334 | csio_set_reg_field(hw, PL_INT_MAP0_A, 0, 1 << pf); |
a3667aae NKI |
2335 | } |
2336 | ||
2337 | hw->flags |= CSIO_HWF_HW_INTR_ENABLED; | |
2338 | ||
2339 | } | |
2340 | ||
2341 | /* | |
2342 | * csio_hw_intr_disable - Disable HW interrupts | |
2343 | * @hw: Pointer to HW module. | |
2344 | * | |
2345 | * Turn off Mailbox and PCI_PF_CFG interrupts. | |
2346 | */ | |
2347 | void | |
2348 | csio_hw_intr_disable(struct csio_hw *hw) | |
2349 | { | |
4bbd458e VP |
2350 | u32 pf = 0; |
2351 | ||
2352 | if (csio_is_t5(hw->pdev->device & CSIO_HW_CHIP_MASK)) | |
2353 | pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A)); | |
2354 | else | |
2355 | pf = T6_SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A)); | |
a3667aae NKI |
2356 | |
2357 | if (!(hw->flags & CSIO_HWF_HW_INTR_ENABLED)) | |
2358 | return; | |
2359 | ||
2360 | hw->flags &= ~CSIO_HWF_HW_INTR_ENABLED; | |
2361 | ||
0d804338 | 2362 | csio_wr_reg32(hw, 0, MYPF_REG(PL_PF_INT_ENABLE_A)); |
a3667aae | 2363 | if (csio_is_hw_master(hw)) |
0d804338 | 2364 | csio_set_reg_field(hw, PL_INT_MAP0_A, 1 << pf, 0); |
a3667aae NKI |
2365 | |
2366 | /* Turn off MB interrupts */ | |
2367 | csio_mb_intr_disable(hw); | |
2368 | ||
2369 | } | |
2370 | ||
7cc16380 | 2371 | void |
a3667aae NKI |
2372 | csio_hw_fatal_err(struct csio_hw *hw) |
2373 | { | |
f612b815 | 2374 | csio_set_reg_field(hw, SGE_CONTROL_A, GLOBALENABLE_F, 0); |
a3667aae NKI |
2375 | csio_hw_intr_disable(hw); |
2376 | ||
2377 | /* Do not reset HW, we may need FW state for debugging */ | |
2378 | csio_fatal(hw, "HW Fatal error encountered!\n"); | |
2379 | } | |
2380 | ||
2381 | /*****************************************************************************/ | |
2382 | /* START: HW SM */ | |
2383 | /*****************************************************************************/ | |
2384 | /* | |
2385 | * csio_hws_uninit - Uninit state | |
2386 | * @hw - HW module | |
2387 | * @evt - Event | |
2388 | * | |
2389 | */ | |
2390 | static void | |
2391 | csio_hws_uninit(struct csio_hw *hw, enum csio_hw_ev evt) | |
2392 | { | |
2393 | hw->prev_evt = hw->cur_evt; | |
2394 | hw->cur_evt = evt; | |
2395 | CSIO_INC_STATS(hw, n_evt_sm[evt]); | |
2396 | ||
2397 | switch (evt) { | |
2398 | case CSIO_HWE_CFG: | |
2399 | csio_set_state(&hw->sm, csio_hws_configuring); | |
2400 | csio_hw_configure(hw); | |
2401 | break; | |
2402 | ||
2403 | default: | |
2404 | CSIO_INC_STATS(hw, n_evt_unexp); | |
2405 | break; | |
2406 | } | |
2407 | } | |
2408 | ||
2409 | /* | |
2410 | * csio_hws_configuring - Configuring state | |
2411 | * @hw - HW module | |
2412 | * @evt - Event | |
2413 | * | |
2414 | */ | |
2415 | static void | |
2416 | csio_hws_configuring(struct csio_hw *hw, enum csio_hw_ev evt) | |
2417 | { | |
2418 | hw->prev_evt = hw->cur_evt; | |
2419 | hw->cur_evt = evt; | |
2420 | CSIO_INC_STATS(hw, n_evt_sm[evt]); | |
2421 | ||
2422 | switch (evt) { | |
2423 | case CSIO_HWE_INIT: | |
2424 | csio_set_state(&hw->sm, csio_hws_initializing); | |
2425 | csio_hw_initialize(hw); | |
2426 | break; | |
2427 | ||
2428 | case CSIO_HWE_INIT_DONE: | |
2429 | csio_set_state(&hw->sm, csio_hws_ready); | |
2430 | /* Fan out event to all lnode SMs */ | |
2431 | csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREADY); | |
2432 | break; | |
2433 | ||
2434 | case CSIO_HWE_FATAL: | |
2435 | csio_set_state(&hw->sm, csio_hws_uninit); | |
2436 | break; | |
2437 | ||
2438 | case CSIO_HWE_PCI_REMOVE: | |
2439 | csio_do_bye(hw); | |
2440 | break; | |
2441 | default: | |
2442 | CSIO_INC_STATS(hw, n_evt_unexp); | |
2443 | break; | |
2444 | } | |
2445 | } | |
2446 | ||
2447 | /* | |
2448 | * csio_hws_initializing - Initialiazing state | |
2449 | * @hw - HW module | |
2450 | * @evt - Event | |
2451 | * | |
2452 | */ | |
2453 | static void | |
2454 | csio_hws_initializing(struct csio_hw *hw, enum csio_hw_ev evt) | |
2455 | { | |
2456 | hw->prev_evt = hw->cur_evt; | |
2457 | hw->cur_evt = evt; | |
2458 | CSIO_INC_STATS(hw, n_evt_sm[evt]); | |
2459 | ||
2460 | switch (evt) { | |
2461 | case CSIO_HWE_INIT_DONE: | |
2462 | csio_set_state(&hw->sm, csio_hws_ready); | |
2463 | ||
2464 | /* Fan out event to all lnode SMs */ | |
2465 | csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREADY); | |
2466 | ||
2467 | /* Enable interrupts */ | |
2468 | csio_hw_intr_enable(hw); | |
2469 | break; | |
2470 | ||
2471 | case CSIO_HWE_FATAL: | |
2472 | csio_set_state(&hw->sm, csio_hws_uninit); | |
2473 | break; | |
2474 | ||
2475 | case CSIO_HWE_PCI_REMOVE: | |
2476 | csio_do_bye(hw); | |
2477 | break; | |
2478 | ||
2479 | default: | |
2480 | CSIO_INC_STATS(hw, n_evt_unexp); | |
2481 | break; | |
2482 | } | |
2483 | } | |
2484 | ||
2485 | /* | |
2486 | * csio_hws_ready - Ready state | |
2487 | * @hw - HW module | |
2488 | * @evt - Event | |
2489 | * | |
2490 | */ | |
2491 | static void | |
2492 | csio_hws_ready(struct csio_hw *hw, enum csio_hw_ev evt) | |
2493 | { | |
2494 | /* Remember the event */ | |
2495 | hw->evtflag = evt; | |
2496 | ||
2497 | hw->prev_evt = hw->cur_evt; | |
2498 | hw->cur_evt = evt; | |
2499 | CSIO_INC_STATS(hw, n_evt_sm[evt]); | |
2500 | ||
2501 | switch (evt) { | |
2502 | case CSIO_HWE_HBA_RESET: | |
2503 | case CSIO_HWE_FW_DLOAD: | |
2504 | case CSIO_HWE_SUSPEND: | |
2505 | case CSIO_HWE_PCI_REMOVE: | |
2506 | case CSIO_HWE_PCIERR_DETECTED: | |
2507 | csio_set_state(&hw->sm, csio_hws_quiescing); | |
2508 | /* cleanup all outstanding cmds */ | |
2509 | if (evt == CSIO_HWE_HBA_RESET || | |
2510 | evt == CSIO_HWE_PCIERR_DETECTED) | |
2511 | csio_scsim_cleanup_io(csio_hw_to_scsim(hw), false); | |
2512 | else | |
2513 | csio_scsim_cleanup_io(csio_hw_to_scsim(hw), true); | |
2514 | ||
2515 | csio_hw_intr_disable(hw); | |
2516 | csio_hw_mbm_cleanup(hw); | |
2517 | csio_evtq_stop(hw); | |
2518 | csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWSTOP); | |
2519 | csio_evtq_flush(hw); | |
2520 | csio_mgmtm_cleanup(csio_hw_to_mgmtm(hw)); | |
2521 | csio_post_event(&hw->sm, CSIO_HWE_QUIESCED); | |
2522 | break; | |
2523 | ||
2524 | case CSIO_HWE_FATAL: | |
2525 | csio_set_state(&hw->sm, csio_hws_uninit); | |
2526 | break; | |
2527 | ||
2528 | default: | |
2529 | CSIO_INC_STATS(hw, n_evt_unexp); | |
2530 | break; | |
2531 | } | |
2532 | } | |
2533 | ||
2534 | /* | |
2535 | * csio_hws_quiescing - Quiescing state | |
2536 | * @hw - HW module | |
2537 | * @evt - Event | |
2538 | * | |
2539 | */ | |
2540 | static void | |
2541 | csio_hws_quiescing(struct csio_hw *hw, enum csio_hw_ev evt) | |
2542 | { | |
2543 | hw->prev_evt = hw->cur_evt; | |
2544 | hw->cur_evt = evt; | |
2545 | CSIO_INC_STATS(hw, n_evt_sm[evt]); | |
2546 | ||
2547 | switch (evt) { | |
2548 | case CSIO_HWE_QUIESCED: | |
2549 | switch (hw->evtflag) { | |
2550 | case CSIO_HWE_FW_DLOAD: | |
2551 | csio_set_state(&hw->sm, csio_hws_resetting); | |
2552 | /* Download firmware */ | |
2553 | /* Fall through */ | |
2554 | ||
2555 | case CSIO_HWE_HBA_RESET: | |
2556 | csio_set_state(&hw->sm, csio_hws_resetting); | |
2557 | /* Start reset of the HBA */ | |
2558 | csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWRESET); | |
2559 | csio_wr_destroy_queues(hw, false); | |
2560 | csio_do_reset(hw, false); | |
2561 | csio_post_event(&hw->sm, CSIO_HWE_HBA_RESET_DONE); | |
2562 | break; | |
2563 | ||
2564 | case CSIO_HWE_PCI_REMOVE: | |
2565 | csio_set_state(&hw->sm, csio_hws_removing); | |
2566 | csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREMOVE); | |
2567 | csio_wr_destroy_queues(hw, true); | |
2568 | /* Now send the bye command */ | |
2569 | csio_do_bye(hw); | |
2570 | break; | |
2571 | ||
2572 | case CSIO_HWE_SUSPEND: | |
2573 | csio_set_state(&hw->sm, csio_hws_quiesced); | |
2574 | break; | |
2575 | ||
2576 | case CSIO_HWE_PCIERR_DETECTED: | |
2577 | csio_set_state(&hw->sm, csio_hws_pcierr); | |
2578 | csio_wr_destroy_queues(hw, false); | |
2579 | break; | |
2580 | ||
2581 | default: | |
2582 | CSIO_INC_STATS(hw, n_evt_unexp); | |
2583 | break; | |
2584 | ||
2585 | } | |
2586 | break; | |
2587 | ||
2588 | default: | |
2589 | CSIO_INC_STATS(hw, n_evt_unexp); | |
2590 | break; | |
2591 | } | |
2592 | } | |
2593 | ||
2594 | /* | |
2595 | * csio_hws_quiesced - Quiesced state | |
2596 | * @hw - HW module | |
2597 | * @evt - Event | |
2598 | * | |
2599 | */ | |
2600 | static void | |
2601 | csio_hws_quiesced(struct csio_hw *hw, enum csio_hw_ev evt) | |
2602 | { | |
2603 | hw->prev_evt = hw->cur_evt; | |
2604 | hw->cur_evt = evt; | |
2605 | CSIO_INC_STATS(hw, n_evt_sm[evt]); | |
2606 | ||
2607 | switch (evt) { | |
2608 | case CSIO_HWE_RESUME: | |
2609 | csio_set_state(&hw->sm, csio_hws_configuring); | |
2610 | csio_hw_configure(hw); | |
2611 | break; | |
2612 | ||
2613 | default: | |
2614 | CSIO_INC_STATS(hw, n_evt_unexp); | |
2615 | break; | |
2616 | } | |
2617 | } | |
2618 | ||
2619 | /* | |
2620 | * csio_hws_resetting - HW Resetting state | |
2621 | * @hw - HW module | |
2622 | * @evt - Event | |
2623 | * | |
2624 | */ | |
2625 | static void | |
2626 | csio_hws_resetting(struct csio_hw *hw, enum csio_hw_ev evt) | |
2627 | { | |
2628 | hw->prev_evt = hw->cur_evt; | |
2629 | hw->cur_evt = evt; | |
2630 | CSIO_INC_STATS(hw, n_evt_sm[evt]); | |
2631 | ||
2632 | switch (evt) { | |
2633 | case CSIO_HWE_HBA_RESET_DONE: | |
2634 | csio_evtq_start(hw); | |
2635 | csio_set_state(&hw->sm, csio_hws_configuring); | |
2636 | csio_hw_configure(hw); | |
2637 | break; | |
2638 | ||
2639 | default: | |
2640 | CSIO_INC_STATS(hw, n_evt_unexp); | |
2641 | break; | |
2642 | } | |
2643 | } | |
2644 | ||
2645 | /* | |
2646 | * csio_hws_removing - PCI Hotplug removing state | |
2647 | * @hw - HW module | |
2648 | * @evt - Event | |
2649 | * | |
2650 | */ | |
2651 | static void | |
2652 | csio_hws_removing(struct csio_hw *hw, enum csio_hw_ev evt) | |
2653 | { | |
2654 | hw->prev_evt = hw->cur_evt; | |
2655 | hw->cur_evt = evt; | |
2656 | CSIO_INC_STATS(hw, n_evt_sm[evt]); | |
2657 | ||
2658 | switch (evt) { | |
2659 | case CSIO_HWE_HBA_RESET: | |
2660 | if (!csio_is_hw_master(hw)) | |
2661 | break; | |
2662 | /* | |
2663 | * The BYE should have alerady been issued, so we cant | |
2664 | * use the mailbox interface. Hence we use the PL_RST | |
2665 | * register directly. | |
2666 | */ | |
2667 | csio_err(hw, "Resetting HW and waiting 2 seconds...\n"); | |
0d804338 | 2668 | csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A); |
a3667aae NKI |
2669 | mdelay(2000); |
2670 | break; | |
2671 | ||
2672 | /* Should never receive any new events */ | |
2673 | default: | |
2674 | CSIO_INC_STATS(hw, n_evt_unexp); | |
2675 | break; | |
2676 | ||
2677 | } | |
2678 | } | |
2679 | ||
2680 | /* | |
2681 | * csio_hws_pcierr - PCI Error state | |
2682 | * @hw - HW module | |
2683 | * @evt - Event | |
2684 | * | |
2685 | */ | |
2686 | static void | |
2687 | csio_hws_pcierr(struct csio_hw *hw, enum csio_hw_ev evt) | |
2688 | { | |
2689 | hw->prev_evt = hw->cur_evt; | |
2690 | hw->cur_evt = evt; | |
2691 | CSIO_INC_STATS(hw, n_evt_sm[evt]); | |
2692 | ||
2693 | switch (evt) { | |
2694 | case CSIO_HWE_PCIERR_SLOT_RESET: | |
2695 | csio_evtq_start(hw); | |
2696 | csio_set_state(&hw->sm, csio_hws_configuring); | |
2697 | csio_hw_configure(hw); | |
2698 | break; | |
2699 | ||
2700 | default: | |
2701 | CSIO_INC_STATS(hw, n_evt_unexp); | |
2702 | break; | |
2703 | } | |
2704 | } | |
2705 | ||
2706 | /*****************************************************************************/ | |
2707 | /* END: HW SM */ | |
2708 | /*****************************************************************************/ | |
2709 | ||
a3667aae NKI |
2710 | /* |
2711 | * csio_handle_intr_status - table driven interrupt handler | |
2712 | * @hw: HW instance | |
2713 | * @reg: the interrupt status register to process | |
2714 | * @acts: table of interrupt actions | |
2715 | * | |
2716 | * A table driven interrupt handler that applies a set of masks to an | |
2717 | * interrupt status word and performs the corresponding actions if the | |
2718 | * interrupts described by the mask have occured. The actions include | |
2719 | * optionally emitting a warning or alert message. The table is terminated | |
2720 | * by an entry specifying mask 0. Returns the number of fatal interrupt | |
2721 | * conditions. | |
2722 | */ | |
7cc16380 | 2723 | int |
a3667aae NKI |
2724 | csio_handle_intr_status(struct csio_hw *hw, unsigned int reg, |
2725 | const struct intr_info *acts) | |
2726 | { | |
2727 | int fatal = 0; | |
2728 | unsigned int mask = 0; | |
2729 | unsigned int status = csio_rd_reg32(hw, reg); | |
2730 | ||
2731 | for ( ; acts->mask; ++acts) { | |
2732 | if (!(status & acts->mask)) | |
2733 | continue; | |
2734 | if (acts->fatal) { | |
2735 | fatal++; | |
2736 | csio_fatal(hw, "Fatal %s (0x%x)\n", | |
2737 | acts->msg, status & acts->mask); | |
2738 | } else if (acts->msg) | |
2739 | csio_info(hw, "%s (0x%x)\n", | |
2740 | acts->msg, status & acts->mask); | |
2741 | mask |= acts->mask; | |
2742 | } | |
2743 | status &= mask; | |
2744 | if (status) /* clear processed interrupts */ | |
2745 | csio_wr_reg32(hw, status, reg); | |
2746 | return fatal; | |
2747 | } | |
2748 | ||
a3667aae NKI |
2749 | /* |
2750 | * TP interrupt handler. | |
2751 | */ | |
2752 | static void csio_tp_intr_handler(struct csio_hw *hw) | |
2753 | { | |
2754 | static struct intr_info tp_intr_info[] = { | |
2755 | { 0x3fffffff, "TP parity error", -1, 1 }, | |
837e4a42 | 2756 | { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 }, |
a3667aae NKI |
2757 | { 0, NULL, 0, 0 } |
2758 | }; | |
2759 | ||
837e4a42 | 2760 | if (csio_handle_intr_status(hw, TP_INT_CAUSE_A, tp_intr_info)) |
a3667aae NKI |
2761 | csio_hw_fatal_err(hw); |
2762 | } | |
2763 | ||
2764 | /* | |
2765 | * SGE interrupt handler. | |
2766 | */ | |
2767 | static void csio_sge_intr_handler(struct csio_hw *hw) | |
2768 | { | |
2769 | uint64_t v; | |
2770 | ||
2771 | static struct intr_info sge_intr_info[] = { | |
f612b815 | 2772 | { ERR_CPL_EXCEED_IQE_SIZE_F, |
a3667aae | 2773 | "SGE received CPL exceeding IQE size", -1, 1 }, |
f612b815 | 2774 | { ERR_INVALID_CIDX_INC_F, |
a3667aae | 2775 | "SGE GTS CIDX increment too large", -1, 0 }, |
f612b815 HS |
2776 | { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 }, |
2777 | { ERR_DROPPED_DB_F, "SGE doorbell dropped", -1, 0 }, | |
2778 | { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F, | |
a3667aae | 2779 | "SGE IQID > 1023 received CPL for FL", -1, 0 }, |
f612b815 | 2780 | { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1, |
a3667aae | 2781 | 0 }, |
f612b815 | 2782 | { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1, |
a3667aae | 2783 | 0 }, |
f612b815 | 2784 | { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1, |
a3667aae | 2785 | 0 }, |
f612b815 | 2786 | { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1, |
a3667aae | 2787 | 0 }, |
f612b815 | 2788 | { ERR_ING_CTXT_PRIO_F, |
a3667aae | 2789 | "SGE too many priority ingress contexts", -1, 0 }, |
f612b815 | 2790 | { ERR_EGR_CTXT_PRIO_F, |
a3667aae | 2791 | "SGE too many priority egress contexts", -1, 0 }, |
f612b815 HS |
2792 | { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 }, |
2793 | { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 }, | |
a3667aae NKI |
2794 | { 0, NULL, 0, 0 } |
2795 | }; | |
2796 | ||
f612b815 HS |
2797 | v = (uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE1_A) | |
2798 | ((uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE2_A) << 32); | |
a3667aae NKI |
2799 | if (v) { |
2800 | csio_fatal(hw, "SGE parity error (%#llx)\n", | |
2801 | (unsigned long long)v); | |
2802 | csio_wr_reg32(hw, (uint32_t)(v & 0xFFFFFFFF), | |
f612b815 HS |
2803 | SGE_INT_CAUSE1_A); |
2804 | csio_wr_reg32(hw, (uint32_t)(v >> 32), SGE_INT_CAUSE2_A); | |
a3667aae NKI |
2805 | } |
2806 | ||
f612b815 | 2807 | v |= csio_handle_intr_status(hw, SGE_INT_CAUSE3_A, sge_intr_info); |
a3667aae | 2808 | |
f612b815 | 2809 | if (csio_handle_intr_status(hw, SGE_INT_CAUSE3_A, sge_intr_info) || |
a3667aae NKI |
2810 | v != 0) |
2811 | csio_hw_fatal_err(hw); | |
2812 | } | |
2813 | ||
89c3a86c HS |
2814 | #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\ |
2815 | OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F) | |
2816 | #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\ | |
2817 | IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F) | |
a3667aae NKI |
2818 | |
2819 | /* | |
2820 | * CIM interrupt handler. | |
2821 | */ | |
2822 | static void csio_cim_intr_handler(struct csio_hw *hw) | |
2823 | { | |
2824 | static struct intr_info cim_intr_info[] = { | |
89c3a86c | 2825 | { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 }, |
a3667aae NKI |
2826 | { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, |
2827 | { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, | |
89c3a86c HS |
2828 | { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 }, |
2829 | { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 }, | |
2830 | { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 }, | |
2831 | { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 }, | |
a3667aae NKI |
2832 | { 0, NULL, 0, 0 } |
2833 | }; | |
2834 | static struct intr_info cim_upintr_info[] = { | |
89c3a86c HS |
2835 | { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 }, |
2836 | { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 }, | |
2837 | { ILLWRINT_F, "CIM illegal write", -1, 1 }, | |
2838 | { ILLRDINT_F, "CIM illegal read", -1, 1 }, | |
2839 | { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 }, | |
2840 | { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 }, | |
2841 | { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 }, | |
2842 | { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 }, | |
2843 | { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 }, | |
2844 | { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 }, | |
2845 | { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 }, | |
2846 | { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 }, | |
2847 | { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 }, | |
2848 | { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 }, | |
2849 | { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 }, | |
2850 | { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 }, | |
2851 | { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 }, | |
2852 | { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 }, | |
2853 | { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 }, | |
2854 | { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 }, | |
2855 | { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 }, | |
2856 | { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 }, | |
2857 | { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 }, | |
2858 | { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 }, | |
2859 | { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 }, | |
2860 | { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 }, | |
2861 | { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 }, | |
2862 | { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 }, | |
a3667aae NKI |
2863 | { 0, NULL, 0, 0 } |
2864 | }; | |
2865 | ||
2866 | int fat; | |
2867 | ||
89c3a86c HS |
2868 | fat = csio_handle_intr_status(hw, CIM_HOST_INT_CAUSE_A, |
2869 | cim_intr_info) + | |
2870 | csio_handle_intr_status(hw, CIM_HOST_UPACC_INT_CAUSE_A, | |
2871 | cim_upintr_info); | |
a3667aae NKI |
2872 | if (fat) |
2873 | csio_hw_fatal_err(hw); | |
2874 | } | |
2875 | ||
2876 | /* | |
2877 | * ULP RX interrupt handler. | |
2878 | */ | |
2879 | static void csio_ulprx_intr_handler(struct csio_hw *hw) | |
2880 | { | |
2881 | static struct intr_info ulprx_intr_info[] = { | |
2882 | { 0x1800000, "ULPRX context error", -1, 1 }, | |
2883 | { 0x7fffff, "ULPRX parity error", -1, 1 }, | |
2884 | { 0, NULL, 0, 0 } | |
2885 | }; | |
2886 | ||
0d804338 | 2887 | if (csio_handle_intr_status(hw, ULP_RX_INT_CAUSE_A, ulprx_intr_info)) |
a3667aae NKI |
2888 | csio_hw_fatal_err(hw); |
2889 | } | |
2890 | ||
2891 | /* | |
2892 | * ULP TX interrupt handler. | |
2893 | */ | |
2894 | static void csio_ulptx_intr_handler(struct csio_hw *hw) | |
2895 | { | |
2896 | static struct intr_info ulptx_intr_info[] = { | |
837e4a42 | 2897 | { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1, |
a3667aae | 2898 | 0 }, |
837e4a42 | 2899 | { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1, |
a3667aae | 2900 | 0 }, |
837e4a42 | 2901 | { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1, |
a3667aae | 2902 | 0 }, |
837e4a42 | 2903 | { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1, |
a3667aae NKI |
2904 | 0 }, |
2905 | { 0xfffffff, "ULPTX parity error", -1, 1 }, | |
2906 | { 0, NULL, 0, 0 } | |
2907 | }; | |
2908 | ||
837e4a42 | 2909 | if (csio_handle_intr_status(hw, ULP_TX_INT_CAUSE_A, ulptx_intr_info)) |
a3667aae NKI |
2910 | csio_hw_fatal_err(hw); |
2911 | } | |
2912 | ||
2913 | /* | |
2914 | * PM TX interrupt handler. | |
2915 | */ | |
2916 | static void csio_pmtx_intr_handler(struct csio_hw *hw) | |
2917 | { | |
2918 | static struct intr_info pmtx_intr_info[] = { | |
837e4a42 HS |
2919 | { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 }, |
2920 | { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 }, | |
2921 | { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 }, | |
2922 | { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 }, | |
a3667aae | 2923 | { 0xffffff0, "PMTX framing error", -1, 1 }, |
837e4a42 HS |
2924 | { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 }, |
2925 | { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error", -1, | |
a3667aae | 2926 | 1 }, |
837e4a42 HS |
2927 | { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 }, |
2928 | { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1}, | |
a3667aae NKI |
2929 | { 0, NULL, 0, 0 } |
2930 | }; | |
2931 | ||
837e4a42 | 2932 | if (csio_handle_intr_status(hw, PM_TX_INT_CAUSE_A, pmtx_intr_info)) |
a3667aae NKI |
2933 | csio_hw_fatal_err(hw); |
2934 | } | |
2935 | ||
2936 | /* | |
2937 | * PM RX interrupt handler. | |
2938 | */ | |
2939 | static void csio_pmrx_intr_handler(struct csio_hw *hw) | |
2940 | { | |
2941 | static struct intr_info pmrx_intr_info[] = { | |
837e4a42 | 2942 | { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 }, |
a3667aae | 2943 | { 0x3ffff0, "PMRX framing error", -1, 1 }, |
837e4a42 HS |
2944 | { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 }, |
2945 | { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error", -1, | |
a3667aae | 2946 | 1 }, |
837e4a42 HS |
2947 | { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 }, |
2948 | { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1}, | |
a3667aae NKI |
2949 | { 0, NULL, 0, 0 } |
2950 | }; | |
2951 | ||
837e4a42 | 2952 | if (csio_handle_intr_status(hw, PM_RX_INT_CAUSE_A, pmrx_intr_info)) |
a3667aae NKI |
2953 | csio_hw_fatal_err(hw); |
2954 | } | |
2955 | ||
2956 | /* | |
2957 | * CPL switch interrupt handler. | |
2958 | */ | |
2959 | static void csio_cplsw_intr_handler(struct csio_hw *hw) | |
2960 | { | |
2961 | static struct intr_info cplsw_intr_info[] = { | |
0d804338 HS |
2962 | { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 }, |
2963 | { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 }, | |
2964 | { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 }, | |
2965 | { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 }, | |
2966 | { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 }, | |
2967 | { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 }, | |
a3667aae NKI |
2968 | { 0, NULL, 0, 0 } |
2969 | }; | |
2970 | ||
0d804338 | 2971 | if (csio_handle_intr_status(hw, CPL_INTR_CAUSE_A, cplsw_intr_info)) |
a3667aae NKI |
2972 | csio_hw_fatal_err(hw); |
2973 | } | |
2974 | ||
2975 | /* | |
2976 | * LE interrupt handler. | |
2977 | */ | |
2978 | static void csio_le_intr_handler(struct csio_hw *hw) | |
2979 | { | |
4bbd458e VP |
2980 | enum chip_type chip = CHELSIO_CHIP_VERSION(hw->chip_id); |
2981 | ||
a3667aae | 2982 | static struct intr_info le_intr_info[] = { |
0d804338 HS |
2983 | { LIPMISS_F, "LE LIP miss", -1, 0 }, |
2984 | { LIP0_F, "LE 0 LIP error", -1, 0 }, | |
2985 | { PARITYERR_F, "LE parity error", -1, 1 }, | |
2986 | { UNKNOWNCMD_F, "LE unknown command", -1, 1 }, | |
2987 | { REQQPARERR_F, "LE request queue parity error", -1, 1 }, | |
a3667aae NKI |
2988 | { 0, NULL, 0, 0 } |
2989 | }; | |
2990 | ||
4bbd458e VP |
2991 | static struct intr_info t6_le_intr_info[] = { |
2992 | { T6_LIPMISS_F, "LE LIP miss", -1, 0 }, | |
2993 | { T6_LIP0_F, "LE 0 LIP error", -1, 0 }, | |
2994 | { TCAMINTPERR_F, "LE parity error", -1, 1 }, | |
2995 | { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 }, | |
2996 | { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 }, | |
2997 | { 0, NULL, 0, 0 } | |
2998 | }; | |
2999 | ||
3000 | if (csio_handle_intr_status(hw, LE_DB_INT_CAUSE_A, | |
3001 | (chip == CHELSIO_T5) ? | |
3002 | le_intr_info : t6_le_intr_info)) | |
a3667aae NKI |
3003 | csio_hw_fatal_err(hw); |
3004 | } | |
3005 | ||
3006 | /* | |
3007 | * MPS interrupt handler. | |
3008 | */ | |
3009 | static void csio_mps_intr_handler(struct csio_hw *hw) | |
3010 | { | |
3011 | static struct intr_info mps_rx_intr_info[] = { | |
3012 | { 0xffffff, "MPS Rx parity error", -1, 1 }, | |
3013 | { 0, NULL, 0, 0 } | |
3014 | }; | |
3015 | static struct intr_info mps_tx_intr_info[] = { | |
837e4a42 HS |
3016 | { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 }, |
3017 | { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 }, | |
3018 | { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error", | |
3019 | -1, 1 }, | |
3020 | { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error", | |
3021 | -1, 1 }, | |
3022 | { BUBBLE_F, "MPS Tx underflow", -1, 1 }, | |
3023 | { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 }, | |
3024 | { FRMERR_F, "MPS Tx framing error", -1, 1 }, | |
a3667aae NKI |
3025 | { 0, NULL, 0, 0 } |
3026 | }; | |
3027 | static struct intr_info mps_trc_intr_info[] = { | |
837e4a42 HS |
3028 | { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 }, |
3029 | { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error", | |
3030 | -1, 1 }, | |
3031 | { MISCPERR_F, "MPS TRC misc parity error", -1, 1 }, | |
a3667aae NKI |
3032 | { 0, NULL, 0, 0 } |
3033 | }; | |
3034 | static struct intr_info mps_stat_sram_intr_info[] = { | |
3035 | { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, | |
3036 | { 0, NULL, 0, 0 } | |
3037 | }; | |
3038 | static struct intr_info mps_stat_tx_intr_info[] = { | |
3039 | { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, | |
3040 | { 0, NULL, 0, 0 } | |
3041 | }; | |
3042 | static struct intr_info mps_stat_rx_intr_info[] = { | |
3043 | { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, | |
3044 | { 0, NULL, 0, 0 } | |
3045 | }; | |
3046 | static struct intr_info mps_cls_intr_info[] = { | |
837e4a42 HS |
3047 | { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 }, |
3048 | { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 }, | |
3049 | { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 }, | |
a3667aae NKI |
3050 | { 0, NULL, 0, 0 } |
3051 | }; | |
3052 | ||
3053 | int fat; | |
3054 | ||
837e4a42 HS |
3055 | fat = csio_handle_intr_status(hw, MPS_RX_PERR_INT_CAUSE_A, |
3056 | mps_rx_intr_info) + | |
3057 | csio_handle_intr_status(hw, MPS_TX_INT_CAUSE_A, | |
3058 | mps_tx_intr_info) + | |
3059 | csio_handle_intr_status(hw, MPS_TRC_INT_CAUSE_A, | |
3060 | mps_trc_intr_info) + | |
3061 | csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_SRAM_A, | |
3062 | mps_stat_sram_intr_info) + | |
3063 | csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A, | |
3064 | mps_stat_tx_intr_info) + | |
3065 | csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A, | |
3066 | mps_stat_rx_intr_info) + | |
3067 | csio_handle_intr_status(hw, MPS_CLS_INT_CAUSE_A, | |
3068 | mps_cls_intr_info); | |
3069 | ||
3070 | csio_wr_reg32(hw, 0, MPS_INT_CAUSE_A); | |
3071 | csio_rd_reg32(hw, MPS_INT_CAUSE_A); /* flush */ | |
a3667aae NKI |
3072 | if (fat) |
3073 | csio_hw_fatal_err(hw); | |
3074 | } | |
3075 | ||
89c3a86c HS |
3076 | #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \ |
3077 | ECC_UE_INT_CAUSE_F) | |
a3667aae NKI |
3078 | |
3079 | /* | |
3080 | * EDC/MC interrupt handler. | |
3081 | */ | |
3082 | static void csio_mem_intr_handler(struct csio_hw *hw, int idx) | |
3083 | { | |
3084 | static const char name[3][5] = { "EDC0", "EDC1", "MC" }; | |
3085 | ||
3086 | unsigned int addr, cnt_addr, v; | |
3087 | ||
3088 | if (idx <= MEM_EDC1) { | |
89c3a86c HS |
3089 | addr = EDC_REG(EDC_INT_CAUSE_A, idx); |
3090 | cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx); | |
a3667aae | 3091 | } else { |
89c3a86c HS |
3092 | addr = MC_INT_CAUSE_A; |
3093 | cnt_addr = MC_ECC_STATUS_A; | |
a3667aae NKI |
3094 | } |
3095 | ||
3096 | v = csio_rd_reg32(hw, addr) & MEM_INT_MASK; | |
89c3a86c | 3097 | if (v & PERR_INT_CAUSE_F) |
a3667aae | 3098 | csio_fatal(hw, "%s FIFO parity error\n", name[idx]); |
89c3a86c HS |
3099 | if (v & ECC_CE_INT_CAUSE_F) { |
3100 | uint32_t cnt = ECC_CECNT_G(csio_rd_reg32(hw, cnt_addr)); | |
a3667aae | 3101 | |
89c3a86c | 3102 | csio_wr_reg32(hw, ECC_CECNT_V(ECC_CECNT_M), cnt_addr); |
a3667aae NKI |
3103 | csio_warn(hw, "%u %s correctable ECC data error%s\n", |
3104 | cnt, name[idx], cnt > 1 ? "s" : ""); | |
3105 | } | |
89c3a86c | 3106 | if (v & ECC_UE_INT_CAUSE_F) |
a3667aae NKI |
3107 | csio_fatal(hw, "%s uncorrectable ECC data error\n", name[idx]); |
3108 | ||
3109 | csio_wr_reg32(hw, v, addr); | |
89c3a86c | 3110 | if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F)) |
a3667aae NKI |
3111 | csio_hw_fatal_err(hw); |
3112 | } | |
3113 | ||
3114 | /* | |
3115 | * MA interrupt handler. | |
3116 | */ | |
3117 | static void csio_ma_intr_handler(struct csio_hw *hw) | |
3118 | { | |
89c3a86c | 3119 | uint32_t v, status = csio_rd_reg32(hw, MA_INT_CAUSE_A); |
a3667aae | 3120 | |
89c3a86c | 3121 | if (status & MEM_PERR_INT_CAUSE_F) |
a3667aae | 3122 | csio_fatal(hw, "MA parity error, parity status %#x\n", |
89c3a86c HS |
3123 | csio_rd_reg32(hw, MA_PARITY_ERROR_STATUS_A)); |
3124 | if (status & MEM_WRAP_INT_CAUSE_F) { | |
3125 | v = csio_rd_reg32(hw, MA_INT_WRAP_STATUS_A); | |
a3667aae NKI |
3126 | csio_fatal(hw, |
3127 | "MA address wrap-around error by client %u to address %#x\n", | |
89c3a86c | 3128 | MEM_WRAP_CLIENT_NUM_G(v), MEM_WRAP_ADDRESS_G(v) << 4); |
a3667aae | 3129 | } |
89c3a86c | 3130 | csio_wr_reg32(hw, status, MA_INT_CAUSE_A); |
a3667aae NKI |
3131 | csio_hw_fatal_err(hw); |
3132 | } | |
3133 | ||
3134 | /* | |
3135 | * SMB interrupt handler. | |
3136 | */ | |
3137 | static void csio_smb_intr_handler(struct csio_hw *hw) | |
3138 | { | |
3139 | static struct intr_info smb_intr_info[] = { | |
0d804338 HS |
3140 | { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 }, |
3141 | { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 }, | |
3142 | { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 }, | |
a3667aae NKI |
3143 | { 0, NULL, 0, 0 } |
3144 | }; | |
3145 | ||
0d804338 | 3146 | if (csio_handle_intr_status(hw, SMB_INT_CAUSE_A, smb_intr_info)) |
a3667aae NKI |
3147 | csio_hw_fatal_err(hw); |
3148 | } | |
3149 | ||
3150 | /* | |
3151 | * NC-SI interrupt handler. | |
3152 | */ | |
3153 | static void csio_ncsi_intr_handler(struct csio_hw *hw) | |
3154 | { | |
3155 | static struct intr_info ncsi_intr_info[] = { | |
0d804338 HS |
3156 | { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 }, |
3157 | { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 }, | |
3158 | { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 }, | |
3159 | { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 }, | |
a3667aae NKI |
3160 | { 0, NULL, 0, 0 } |
3161 | }; | |
3162 | ||
0d804338 | 3163 | if (csio_handle_intr_status(hw, NCSI_INT_CAUSE_A, ncsi_intr_info)) |
a3667aae NKI |
3164 | csio_hw_fatal_err(hw); |
3165 | } | |
3166 | ||
3167 | /* | |
3168 | * XGMAC interrupt handler. | |
3169 | */ | |
3170 | static void csio_xgmac_intr_handler(struct csio_hw *hw, int port) | |
3171 | { | |
3fb4c22e | 3172 | uint32_t v = csio_rd_reg32(hw, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A)); |
a3667aae | 3173 | |
0d804338 | 3174 | v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F; |
a3667aae NKI |
3175 | if (!v) |
3176 | return; | |
3177 | ||
0d804338 | 3178 | if (v & TXFIFO_PRTY_ERR_F) |
a3667aae | 3179 | csio_fatal(hw, "XGMAC %d Tx FIFO parity error\n", port); |
0d804338 | 3180 | if (v & RXFIFO_PRTY_ERR_F) |
a3667aae | 3181 | csio_fatal(hw, "XGMAC %d Rx FIFO parity error\n", port); |
3fb4c22e | 3182 | csio_wr_reg32(hw, v, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A)); |
a3667aae NKI |
3183 | csio_hw_fatal_err(hw); |
3184 | } | |
3185 | ||
3186 | /* | |
3187 | * PL interrupt handler. | |
3188 | */ | |
3189 | static void csio_pl_intr_handler(struct csio_hw *hw) | |
3190 | { | |
3191 | static struct intr_info pl_intr_info[] = { | |
0d804338 HS |
3192 | { FATALPERR_F, "T4 fatal parity error", -1, 1 }, |
3193 | { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 }, | |
a3667aae NKI |
3194 | { 0, NULL, 0, 0 } |
3195 | }; | |
3196 | ||
0d804338 | 3197 | if (csio_handle_intr_status(hw, PL_PL_INT_CAUSE_A, pl_intr_info)) |
a3667aae NKI |
3198 | csio_hw_fatal_err(hw); |
3199 | } | |
3200 | ||
3201 | /* | |
3202 | * csio_hw_slow_intr_handler - control path interrupt handler | |
3203 | * @hw: HW module | |
3204 | * | |
3205 | * Interrupt handler for non-data global interrupt events, e.g., errors. | |
3206 | * The designation 'slow' is because it involves register reads, while | |
3207 | * data interrupts typically don't involve any MMIOs. | |
3208 | */ | |
3209 | int | |
3210 | csio_hw_slow_intr_handler(struct csio_hw *hw) | |
3211 | { | |
0d804338 | 3212 | uint32_t cause = csio_rd_reg32(hw, PL_INT_CAUSE_A); |
a3667aae NKI |
3213 | |
3214 | if (!(cause & CSIO_GLBL_INTR_MASK)) { | |
3215 | CSIO_INC_STATS(hw, n_plint_unexp); | |
3216 | return 0; | |
3217 | } | |
3218 | ||
3219 | csio_dbg(hw, "Slow interrupt! cause: 0x%x\n", cause); | |
3220 | ||
3221 | CSIO_INC_STATS(hw, n_plint_cnt); | |
3222 | ||
0d804338 | 3223 | if (cause & CIM_F) |
a3667aae NKI |
3224 | csio_cim_intr_handler(hw); |
3225 | ||
0d804338 | 3226 | if (cause & MPS_F) |
a3667aae NKI |
3227 | csio_mps_intr_handler(hw); |
3228 | ||
0d804338 | 3229 | if (cause & NCSI_F) |
a3667aae NKI |
3230 | csio_ncsi_intr_handler(hw); |
3231 | ||
0d804338 | 3232 | if (cause & PL_F) |
a3667aae NKI |
3233 | csio_pl_intr_handler(hw); |
3234 | ||
0d804338 | 3235 | if (cause & SMB_F) |
a3667aae NKI |
3236 | csio_smb_intr_handler(hw); |
3237 | ||
0d804338 | 3238 | if (cause & XGMAC0_F) |
a3667aae NKI |
3239 | csio_xgmac_intr_handler(hw, 0); |
3240 | ||
0d804338 | 3241 | if (cause & XGMAC1_F) |
a3667aae NKI |
3242 | csio_xgmac_intr_handler(hw, 1); |
3243 | ||
0d804338 | 3244 | if (cause & XGMAC_KR0_F) |
a3667aae NKI |
3245 | csio_xgmac_intr_handler(hw, 2); |
3246 | ||
0d804338 | 3247 | if (cause & XGMAC_KR1_F) |
a3667aae NKI |
3248 | csio_xgmac_intr_handler(hw, 3); |
3249 | ||
0d804338 | 3250 | if (cause & PCIE_F) |
7cc16380 | 3251 | hw->chip_ops->chip_pcie_intr_handler(hw); |
a3667aae | 3252 | |
0d804338 | 3253 | if (cause & MC_F) |
a3667aae NKI |
3254 | csio_mem_intr_handler(hw, MEM_MC); |
3255 | ||
0d804338 | 3256 | if (cause & EDC0_F) |
a3667aae NKI |
3257 | csio_mem_intr_handler(hw, MEM_EDC0); |
3258 | ||
0d804338 | 3259 | if (cause & EDC1_F) |
a3667aae NKI |
3260 | csio_mem_intr_handler(hw, MEM_EDC1); |
3261 | ||
0d804338 | 3262 | if (cause & LE_F) |
a3667aae NKI |
3263 | csio_le_intr_handler(hw); |
3264 | ||
0d804338 | 3265 | if (cause & TP_F) |
a3667aae NKI |
3266 | csio_tp_intr_handler(hw); |
3267 | ||
0d804338 | 3268 | if (cause & MA_F) |
a3667aae NKI |
3269 | csio_ma_intr_handler(hw); |
3270 | ||
0d804338 | 3271 | if (cause & PM_TX_F) |
a3667aae NKI |
3272 | csio_pmtx_intr_handler(hw); |
3273 | ||
0d804338 | 3274 | if (cause & PM_RX_F) |
a3667aae NKI |
3275 | csio_pmrx_intr_handler(hw); |
3276 | ||
0d804338 | 3277 | if (cause & ULP_RX_F) |
a3667aae NKI |
3278 | csio_ulprx_intr_handler(hw); |
3279 | ||
0d804338 | 3280 | if (cause & CPL_SWITCH_F) |
a3667aae NKI |
3281 | csio_cplsw_intr_handler(hw); |
3282 | ||
0d804338 | 3283 | if (cause & SGE_F) |
a3667aae NKI |
3284 | csio_sge_intr_handler(hw); |
3285 | ||
0d804338 | 3286 | if (cause & ULP_TX_F) |
a3667aae NKI |
3287 | csio_ulptx_intr_handler(hw); |
3288 | ||
3289 | /* Clear the interrupts just processed for which we are the master. */ | |
0d804338 HS |
3290 | csio_wr_reg32(hw, cause & CSIO_GLBL_INTR_MASK, PL_INT_CAUSE_A); |
3291 | csio_rd_reg32(hw, PL_INT_CAUSE_A); /* flush */ | |
a3667aae NKI |
3292 | |
3293 | return 1; | |
3294 | } | |
3295 | ||
3296 | /***************************************************************************** | |
3297 | * HW <--> mailbox interfacing routines. | |
3298 | ****************************************************************************/ | |
3299 | /* | |
3300 | * csio_mberr_worker - Worker thread (dpc) for mailbox/error completions | |
3301 | * | |
3302 | * @data: Private data pointer. | |
3303 | * | |
3304 | * Called from worker thread context. | |
3305 | */ | |
3306 | static void | |
3307 | csio_mberr_worker(void *data) | |
3308 | { | |
3309 | struct csio_hw *hw = (struct csio_hw *)data; | |
3310 | struct csio_mbm *mbm = &hw->mbm; | |
3311 | LIST_HEAD(cbfn_q); | |
3312 | struct csio_mb *mbp_next; | |
3313 | int rv; | |
3314 | ||
3315 | del_timer_sync(&mbm->timer); | |
3316 | ||
3317 | spin_lock_irq(&hw->lock); | |
3318 | if (list_empty(&mbm->cbfn_q)) { | |
3319 | spin_unlock_irq(&hw->lock); | |
3320 | return; | |
3321 | } | |
3322 | ||
3323 | list_splice_tail_init(&mbm->cbfn_q, &cbfn_q); | |
3324 | mbm->stats.n_cbfnq = 0; | |
3325 | ||
3326 | /* Try to start waiting mailboxes */ | |
3327 | if (!list_empty(&mbm->req_q)) { | |
3328 | mbp_next = list_first_entry(&mbm->req_q, struct csio_mb, list); | |
3329 | list_del_init(&mbp_next->list); | |
3330 | ||
3331 | rv = csio_mb_issue(hw, mbp_next); | |
3332 | if (rv != 0) | |
3333 | list_add_tail(&mbp_next->list, &mbm->req_q); | |
3334 | else | |
3335 | CSIO_DEC_STATS(mbm, n_activeq); | |
3336 | } | |
3337 | spin_unlock_irq(&hw->lock); | |
3338 | ||
3339 | /* Now callback completions */ | |
3340 | csio_mb_completions(hw, &cbfn_q); | |
3341 | } | |
3342 | ||
3343 | /* | |
3344 | * csio_hw_mb_timer - Top-level Mailbox timeout handler. | |
3345 | * | |
3346 | * @data: private data pointer | |
3347 | * | |
3348 | **/ | |
3349 | static void | |
3350 | csio_hw_mb_timer(uintptr_t data) | |
3351 | { | |
3352 | struct csio_hw *hw = (struct csio_hw *)data; | |
3353 | struct csio_mb *mbp = NULL; | |
3354 | ||
3355 | spin_lock_irq(&hw->lock); | |
3356 | mbp = csio_mb_tmo_handler(hw); | |
3357 | spin_unlock_irq(&hw->lock); | |
3358 | ||
3359 | /* Call back the function for the timed-out Mailbox */ | |
3360 | if (mbp) | |
3361 | mbp->mb_cbfn(hw, mbp); | |
3362 | ||
3363 | } | |
3364 | ||
3365 | /* | |
3366 | * csio_hw_mbm_cleanup - Cleanup Mailbox module. | |
3367 | * @hw: HW module | |
3368 | * | |
3369 | * Called with lock held, should exit with lock held. | |
3370 | * Cancels outstanding mailboxes (waiting, in-flight) and gathers them | |
3371 | * into a local queue. Drops lock and calls the completions. Holds | |
3372 | * lock and returns. | |
3373 | */ | |
3374 | static void | |
3375 | csio_hw_mbm_cleanup(struct csio_hw *hw) | |
3376 | { | |
3377 | LIST_HEAD(cbfn_q); | |
3378 | ||
3379 | csio_mb_cancel_all(hw, &cbfn_q); | |
3380 | ||
3381 | spin_unlock_irq(&hw->lock); | |
3382 | csio_mb_completions(hw, &cbfn_q); | |
3383 | spin_lock_irq(&hw->lock); | |
3384 | } | |
3385 | ||
3386 | /***************************************************************************** | |
3387 | * Event handling | |
3388 | ****************************************************************************/ | |
3389 | int | |
3390 | csio_enqueue_evt(struct csio_hw *hw, enum csio_evt type, void *evt_msg, | |
3391 | uint16_t len) | |
3392 | { | |
3393 | struct csio_evt_msg *evt_entry = NULL; | |
3394 | ||
3395 | if (type >= CSIO_EVT_MAX) | |
3396 | return -EINVAL; | |
3397 | ||
3398 | if (len > CSIO_EVT_MSG_SIZE) | |
3399 | return -EINVAL; | |
3400 | ||
3401 | if (hw->flags & CSIO_HWF_FWEVT_STOP) | |
3402 | return -EINVAL; | |
3403 | ||
3404 | if (list_empty(&hw->evt_free_q)) { | |
3405 | csio_err(hw, "Failed to alloc evt entry, msg type %d len %d\n", | |
3406 | type, len); | |
3407 | return -ENOMEM; | |
3408 | } | |
3409 | ||
3410 | evt_entry = list_first_entry(&hw->evt_free_q, | |
3411 | struct csio_evt_msg, list); | |
3412 | list_del_init(&evt_entry->list); | |
3413 | ||
3414 | /* copy event msg and queue the event */ | |
3415 | evt_entry->type = type; | |
3416 | memcpy((void *)evt_entry->data, evt_msg, len); | |
3417 | list_add_tail(&evt_entry->list, &hw->evt_active_q); | |
3418 | ||
3419 | CSIO_DEC_STATS(hw, n_evt_freeq); | |
3420 | CSIO_INC_STATS(hw, n_evt_activeq); | |
3421 | ||
3422 | return 0; | |
3423 | } | |
3424 | ||
3425 | static int | |
3426 | csio_enqueue_evt_lock(struct csio_hw *hw, enum csio_evt type, void *evt_msg, | |
3427 | uint16_t len, bool msg_sg) | |
3428 | { | |
3429 | struct csio_evt_msg *evt_entry = NULL; | |
3430 | struct csio_fl_dma_buf *fl_sg; | |
3431 | uint32_t off = 0; | |
3432 | unsigned long flags; | |
3433 | int n, ret = 0; | |
3434 | ||
3435 | if (type >= CSIO_EVT_MAX) | |
3436 | return -EINVAL; | |
3437 | ||
3438 | if (len > CSIO_EVT_MSG_SIZE) | |
3439 | return -EINVAL; | |
3440 | ||
3441 | spin_lock_irqsave(&hw->lock, flags); | |
3442 | if (hw->flags & CSIO_HWF_FWEVT_STOP) { | |
3443 | ret = -EINVAL; | |
3444 | goto out; | |
3445 | } | |
3446 | ||
3447 | if (list_empty(&hw->evt_free_q)) { | |
3448 | csio_err(hw, "Failed to alloc evt entry, msg type %d len %d\n", | |
3449 | type, len); | |
3450 | ret = -ENOMEM; | |
3451 | goto out; | |
3452 | } | |
3453 | ||
3454 | evt_entry = list_first_entry(&hw->evt_free_q, | |
3455 | struct csio_evt_msg, list); | |
3456 | list_del_init(&evt_entry->list); | |
3457 | ||
3458 | /* copy event msg and queue the event */ | |
3459 | evt_entry->type = type; | |
3460 | ||
3461 | /* If Payload in SG list*/ | |
3462 | if (msg_sg) { | |
3463 | fl_sg = (struct csio_fl_dma_buf *) evt_msg; | |
3464 | for (n = 0; (n < CSIO_MAX_FLBUF_PER_IQWR && off < len); n++) { | |
3465 | memcpy((void *)((uintptr_t)evt_entry->data + off), | |
3466 | fl_sg->flbufs[n].vaddr, | |
3467 | fl_sg->flbufs[n].len); | |
3468 | off += fl_sg->flbufs[n].len; | |
3469 | } | |
3470 | } else | |
3471 | memcpy((void *)evt_entry->data, evt_msg, len); | |
3472 | ||
3473 | list_add_tail(&evt_entry->list, &hw->evt_active_q); | |
3474 | CSIO_DEC_STATS(hw, n_evt_freeq); | |
3475 | CSIO_INC_STATS(hw, n_evt_activeq); | |
3476 | out: | |
3477 | spin_unlock_irqrestore(&hw->lock, flags); | |
3478 | return ret; | |
3479 | } | |
3480 | ||
3481 | static void | |
3482 | csio_free_evt(struct csio_hw *hw, struct csio_evt_msg *evt_entry) | |
3483 | { | |
3484 | if (evt_entry) { | |
3485 | spin_lock_irq(&hw->lock); | |
3486 | list_del_init(&evt_entry->list); | |
3487 | list_add_tail(&evt_entry->list, &hw->evt_free_q); | |
3488 | CSIO_DEC_STATS(hw, n_evt_activeq); | |
3489 | CSIO_INC_STATS(hw, n_evt_freeq); | |
3490 | spin_unlock_irq(&hw->lock); | |
3491 | } | |
3492 | } | |
3493 | ||
3494 | void | |
3495 | csio_evtq_flush(struct csio_hw *hw) | |
3496 | { | |
3497 | uint32_t count; | |
3498 | count = 30; | |
3499 | while (hw->flags & CSIO_HWF_FWEVT_PENDING && count--) { | |
3500 | spin_unlock_irq(&hw->lock); | |
3501 | msleep(2000); | |
3502 | spin_lock_irq(&hw->lock); | |
3503 | } | |
3504 | ||
3505 | CSIO_DB_ASSERT(!(hw->flags & CSIO_HWF_FWEVT_PENDING)); | |
3506 | } | |
3507 | ||
3508 | static void | |
3509 | csio_evtq_stop(struct csio_hw *hw) | |
3510 | { | |
3511 | hw->flags |= CSIO_HWF_FWEVT_STOP; | |
3512 | } | |
3513 | ||
3514 | static void | |
3515 | csio_evtq_start(struct csio_hw *hw) | |
3516 | { | |
3517 | hw->flags &= ~CSIO_HWF_FWEVT_STOP; | |
3518 | } | |
3519 | ||
3520 | static void | |
3521 | csio_evtq_cleanup(struct csio_hw *hw) | |
3522 | { | |
3523 | struct list_head *evt_entry, *next_entry; | |
3524 | ||
3525 | /* Release outstanding events from activeq to freeq*/ | |
3526 | if (!list_empty(&hw->evt_active_q)) | |
3527 | list_splice_tail_init(&hw->evt_active_q, &hw->evt_free_q); | |
3528 | ||
3529 | hw->stats.n_evt_activeq = 0; | |
3530 | hw->flags &= ~CSIO_HWF_FWEVT_PENDING; | |
3531 | ||
3532 | /* Freeup event entry */ | |
3533 | list_for_each_safe(evt_entry, next_entry, &hw->evt_free_q) { | |
3534 | kfree(evt_entry); | |
3535 | CSIO_DEC_STATS(hw, n_evt_freeq); | |
3536 | } | |
3537 | ||
3538 | hw->stats.n_evt_freeq = 0; | |
3539 | } | |
3540 | ||
3541 | ||
3542 | static void | |
3543 | csio_process_fwevtq_entry(struct csio_hw *hw, void *wr, uint32_t len, | |
3544 | struct csio_fl_dma_buf *flb, void *priv) | |
3545 | { | |
3546 | __u8 op; | |
a3667aae NKI |
3547 | void *msg = NULL; |
3548 | uint32_t msg_len = 0; | |
3549 | bool msg_sg = 0; | |
3550 | ||
3551 | op = ((struct rss_header *) wr)->opcode; | |
3552 | if (op == CPL_FW6_PLD) { | |
3553 | CSIO_INC_STATS(hw, n_cpl_fw6_pld); | |
3554 | if (!flb || !flb->totlen) { | |
3555 | CSIO_INC_STATS(hw, n_cpl_unexp); | |
3556 | return; | |
3557 | } | |
3558 | ||
3559 | msg = (void *) flb; | |
3560 | msg_len = flb->totlen; | |
3561 | msg_sg = 1; | |
a3667aae NKI |
3562 | } else if (op == CPL_FW6_MSG || op == CPL_FW4_MSG) { |
3563 | ||
3564 | CSIO_INC_STATS(hw, n_cpl_fw6_msg); | |
3565 | /* skip RSS header */ | |
3566 | msg = (void *)((uintptr_t)wr + sizeof(__be64)); | |
3567 | msg_len = (op == CPL_FW6_MSG) ? sizeof(struct cpl_fw6_msg) : | |
3568 | sizeof(struct cpl_fw4_msg); | |
a3667aae NKI |
3569 | } else { |
3570 | csio_warn(hw, "unexpected CPL %#x on FW event queue\n", op); | |
3571 | CSIO_INC_STATS(hw, n_cpl_unexp); | |
3572 | return; | |
3573 | } | |
3574 | ||
3575 | /* | |
3576 | * Enqueue event to EventQ. Events processing happens | |
3577 | * in Event worker thread context | |
3578 | */ | |
3579 | if (csio_enqueue_evt_lock(hw, CSIO_EVT_FW, msg, | |
3580 | (uint16_t)msg_len, msg_sg)) | |
3581 | CSIO_INC_STATS(hw, n_evt_drop); | |
3582 | } | |
3583 | ||
3584 | void | |
3585 | csio_evtq_worker(struct work_struct *work) | |
3586 | { | |
3587 | struct csio_hw *hw = container_of(work, struct csio_hw, evtq_work); | |
3588 | struct list_head *evt_entry, *next_entry; | |
3589 | LIST_HEAD(evt_q); | |
3590 | struct csio_evt_msg *evt_msg; | |
3591 | struct cpl_fw6_msg *msg; | |
3592 | struct csio_rnode *rn; | |
3593 | int rv = 0; | |
3594 | uint8_t evtq_stop = 0; | |
3595 | ||
3596 | csio_dbg(hw, "event worker thread active evts#%d\n", | |
3597 | hw->stats.n_evt_activeq); | |
3598 | ||
3599 | spin_lock_irq(&hw->lock); | |
3600 | while (!list_empty(&hw->evt_active_q)) { | |
3601 | list_splice_tail_init(&hw->evt_active_q, &evt_q); | |
3602 | spin_unlock_irq(&hw->lock); | |
3603 | ||
3604 | list_for_each_safe(evt_entry, next_entry, &evt_q) { | |
3605 | evt_msg = (struct csio_evt_msg *) evt_entry; | |
3606 | ||
3607 | /* Drop events if queue is STOPPED */ | |
3608 | spin_lock_irq(&hw->lock); | |
3609 | if (hw->flags & CSIO_HWF_FWEVT_STOP) | |
3610 | evtq_stop = 1; | |
3611 | spin_unlock_irq(&hw->lock); | |
3612 | if (evtq_stop) { | |
3613 | CSIO_INC_STATS(hw, n_evt_drop); | |
3614 | goto free_evt; | |
3615 | } | |
3616 | ||
3617 | switch (evt_msg->type) { | |
3618 | case CSIO_EVT_FW: | |
3619 | msg = (struct cpl_fw6_msg *)(evt_msg->data); | |
3620 | ||
3621 | if ((msg->opcode == CPL_FW6_MSG || | |
3622 | msg->opcode == CPL_FW4_MSG) && | |
3623 | !msg->type) { | |
3624 | rv = csio_mb_fwevt_handler(hw, | |
3625 | msg->data); | |
3626 | if (!rv) | |
3627 | break; | |
3628 | /* Handle any remaining fw events */ | |
3629 | csio_fcoe_fwevt_handler(hw, | |
3630 | msg->opcode, msg->data); | |
3631 | } else if (msg->opcode == CPL_FW6_PLD) { | |
3632 | ||
3633 | csio_fcoe_fwevt_handler(hw, | |
3634 | msg->opcode, msg->data); | |
3635 | } else { | |
3636 | csio_warn(hw, | |
3637 | "Unhandled FW msg op %x type %x\n", | |
3638 | msg->opcode, msg->type); | |
3639 | CSIO_INC_STATS(hw, n_evt_drop); | |
3640 | } | |
3641 | break; | |
3642 | ||
3643 | case CSIO_EVT_MBX: | |
3644 | csio_mberr_worker(hw); | |
3645 | break; | |
3646 | ||
3647 | case CSIO_EVT_DEV_LOSS: | |
3648 | memcpy(&rn, evt_msg->data, sizeof(rn)); | |
3649 | csio_rnode_devloss_handler(rn); | |
3650 | break; | |
3651 | ||
3652 | default: | |
3653 | csio_warn(hw, "Unhandled event %x on evtq\n", | |
3654 | evt_msg->type); | |
3655 | CSIO_INC_STATS(hw, n_evt_unexp); | |
3656 | break; | |
3657 | } | |
3658 | free_evt: | |
3659 | csio_free_evt(hw, evt_msg); | |
3660 | } | |
3661 | ||
3662 | spin_lock_irq(&hw->lock); | |
3663 | } | |
3664 | hw->flags &= ~CSIO_HWF_FWEVT_PENDING; | |
3665 | spin_unlock_irq(&hw->lock); | |
3666 | } | |
3667 | ||
3668 | int | |
3669 | csio_fwevtq_handler(struct csio_hw *hw) | |
3670 | { | |
3671 | int rv; | |
3672 | ||
3673 | if (csio_q_iqid(hw, hw->fwevt_iq_idx) == CSIO_MAX_QID) { | |
3674 | CSIO_INC_STATS(hw, n_int_stray); | |
3675 | return -EINVAL; | |
3676 | } | |
3677 | ||
3678 | rv = csio_wr_process_iq_idx(hw, hw->fwevt_iq_idx, | |
3679 | csio_process_fwevtq_entry, NULL); | |
3680 | return rv; | |
3681 | } | |
3682 | ||
3683 | /**************************************************************************** | |
3684 | * Entry points | |
3685 | ****************************************************************************/ | |
3686 | ||
3687 | /* Management module */ | |
3688 | /* | |
3689 | * csio_mgmt_req_lookup - Lookup the given IO req exist in Active Q. | |
3690 | * mgmt - mgmt module | |
3691 | * @io_req - io request | |
3692 | * | |
3693 | * Return - 0:if given IO Req exists in active Q. | |
3694 | * -EINVAL :if lookup fails. | |
3695 | */ | |
3696 | int | |
3697 | csio_mgmt_req_lookup(struct csio_mgmtm *mgmtm, struct csio_ioreq *io_req) | |
3698 | { | |
3699 | struct list_head *tmp; | |
3700 | ||
3701 | /* Lookup ioreq in the ACTIVEQ */ | |
3702 | list_for_each(tmp, &mgmtm->active_q) { | |
3703 | if (io_req == (struct csio_ioreq *)tmp) | |
3704 | return 0; | |
3705 | } | |
3706 | return -EINVAL; | |
3707 | } | |
3708 | ||
3709 | #define ECM_MIN_TMO 1000 /* Minimum timeout value for req */ | |
3710 | ||
3711 | /* | |
3712 | * csio_mgmts_tmo_handler - MGMT IO Timeout handler. | |
3713 | * @data - Event data. | |
3714 | * | |
3715 | * Return - none. | |
3716 | */ | |
3717 | static void | |
3718 | csio_mgmt_tmo_handler(uintptr_t data) | |
3719 | { | |
3720 | struct csio_mgmtm *mgmtm = (struct csio_mgmtm *) data; | |
3721 | struct list_head *tmp; | |
3722 | struct csio_ioreq *io_req; | |
3723 | ||
3724 | csio_dbg(mgmtm->hw, "Mgmt timer invoked!\n"); | |
3725 | ||
3726 | spin_lock_irq(&mgmtm->hw->lock); | |
3727 | ||
3728 | list_for_each(tmp, &mgmtm->active_q) { | |
3729 | io_req = (struct csio_ioreq *) tmp; | |
3730 | io_req->tmo -= min_t(uint32_t, io_req->tmo, ECM_MIN_TMO); | |
3731 | ||
3732 | if (!io_req->tmo) { | |
3733 | /* Dequeue the request from retry Q. */ | |
3734 | tmp = csio_list_prev(tmp); | |
3735 | list_del_init(&io_req->sm.sm_list); | |
3736 | if (io_req->io_cbfn) { | |
3737 | /* io_req will be freed by completion handler */ | |
3738 | io_req->wr_status = -ETIMEDOUT; | |
3739 | io_req->io_cbfn(mgmtm->hw, io_req); | |
3740 | } else { | |
3741 | CSIO_DB_ASSERT(0); | |
3742 | } | |
3743 | } | |
3744 | } | |
3745 | ||
3746 | /* If retry queue is not empty, re-arm timer */ | |
3747 | if (!list_empty(&mgmtm->active_q)) | |
3748 | mod_timer(&mgmtm->mgmt_timer, | |
3749 | jiffies + msecs_to_jiffies(ECM_MIN_TMO)); | |
3750 | spin_unlock_irq(&mgmtm->hw->lock); | |
3751 | } | |
3752 | ||
3753 | static void | |
3754 | csio_mgmtm_cleanup(struct csio_mgmtm *mgmtm) | |
3755 | { | |
3756 | struct csio_hw *hw = mgmtm->hw; | |
3757 | struct csio_ioreq *io_req; | |
3758 | struct list_head *tmp; | |
3759 | uint32_t count; | |
3760 | ||
3761 | count = 30; | |
3762 | /* Wait for all outstanding req to complete gracefully */ | |
3763 | while ((!list_empty(&mgmtm->active_q)) && count--) { | |
3764 | spin_unlock_irq(&hw->lock); | |
3765 | msleep(2000); | |
3766 | spin_lock_irq(&hw->lock); | |
3767 | } | |
3768 | ||
3769 | /* release outstanding req from ACTIVEQ */ | |
3770 | list_for_each(tmp, &mgmtm->active_q) { | |
3771 | io_req = (struct csio_ioreq *) tmp; | |
3772 | tmp = csio_list_prev(tmp); | |
3773 | list_del_init(&io_req->sm.sm_list); | |
3774 | mgmtm->stats.n_active--; | |
3775 | if (io_req->io_cbfn) { | |
3776 | /* io_req will be freed by completion handler */ | |
3777 | io_req->wr_status = -ETIMEDOUT; | |
3778 | io_req->io_cbfn(mgmtm->hw, io_req); | |
3779 | } | |
3780 | } | |
3781 | } | |
3782 | ||
3783 | /* | |
3784 | * csio_mgmt_init - Mgmt module init entry point | |
3785 | * @mgmtsm - mgmt module | |
3786 | * @hw - HW module | |
3787 | * | |
3788 | * Initialize mgmt timer, resource wait queue, active queue, | |
3789 | * completion q. Allocate Egress and Ingress | |
3790 | * WR queues and save off the queue index returned by the WR | |
3791 | * module for future use. Allocate and save off mgmt reqs in the | |
3792 | * mgmt_req_freelist for future use. Make sure their SM is initialized | |
3793 | * to uninit state. | |
3794 | * Returns: 0 - on success | |
3795 | * -ENOMEM - on error. | |
3796 | */ | |
3797 | static int | |
3798 | csio_mgmtm_init(struct csio_mgmtm *mgmtm, struct csio_hw *hw) | |
3799 | { | |
3800 | struct timer_list *timer = &mgmtm->mgmt_timer; | |
3801 | ||
3802 | init_timer(timer); | |
3803 | timer->function = csio_mgmt_tmo_handler; | |
3804 | timer->data = (unsigned long)mgmtm; | |
3805 | ||
3806 | INIT_LIST_HEAD(&mgmtm->active_q); | |
3807 | INIT_LIST_HEAD(&mgmtm->cbfn_q); | |
3808 | ||
3809 | mgmtm->hw = hw; | |
3810 | /*mgmtm->iq_idx = hw->fwevt_iq_idx;*/ | |
3811 | ||
3812 | return 0; | |
3813 | } | |
3814 | ||
3815 | /* | |
3816 | * csio_mgmtm_exit - MGMT module exit entry point | |
3817 | * @mgmtsm - mgmt module | |
3818 | * | |
3819 | * This function called during MGMT module uninit. | |
3820 | * Stop timers, free ioreqs allocated. | |
3821 | * Returns: None | |
3822 | * | |
3823 | */ | |
3824 | static void | |
3825 | csio_mgmtm_exit(struct csio_mgmtm *mgmtm) | |
3826 | { | |
3827 | del_timer_sync(&mgmtm->mgmt_timer); | |
3828 | } | |
3829 | ||
3830 | ||
3831 | /** | |
3832 | * csio_hw_start - Kicks off the HW State machine | |
3833 | * @hw: Pointer to HW module. | |
3834 | * | |
3835 | * It is assumed that the initialization is a synchronous operation. | |
3836 | * So when we return afer posting the event, the HW SM should be in | |
3837 | * the ready state, if there were no errors during init. | |
3838 | */ | |
3839 | int | |
3840 | csio_hw_start(struct csio_hw *hw) | |
3841 | { | |
3842 | spin_lock_irq(&hw->lock); | |
3843 | csio_post_event(&hw->sm, CSIO_HWE_CFG); | |
3844 | spin_unlock_irq(&hw->lock); | |
3845 | ||
3846 | if (csio_is_hw_ready(hw)) | |
3847 | return 0; | |
3848 | else | |
3849 | return -EINVAL; | |
3850 | } | |
3851 | ||
3852 | int | |
3853 | csio_hw_stop(struct csio_hw *hw) | |
3854 | { | |
3855 | csio_post_event(&hw->sm, CSIO_HWE_PCI_REMOVE); | |
3856 | ||
3857 | if (csio_is_hw_removing(hw)) | |
3858 | return 0; | |
3859 | else | |
3860 | return -EINVAL; | |
3861 | } | |
3862 | ||
3863 | /* Max reset retries */ | |
3864 | #define CSIO_MAX_RESET_RETRIES 3 | |
3865 | ||
3866 | /** | |
3867 | * csio_hw_reset - Reset the hardware | |
3868 | * @hw: HW module. | |
3869 | * | |
3870 | * Caller should hold lock across this function. | |
3871 | */ | |
3872 | int | |
3873 | csio_hw_reset(struct csio_hw *hw) | |
3874 | { | |
3875 | if (!csio_is_hw_master(hw)) | |
3876 | return -EPERM; | |
3877 | ||
3878 | if (hw->rst_retries >= CSIO_MAX_RESET_RETRIES) { | |
3879 | csio_dbg(hw, "Max hw reset attempts reached.."); | |
3880 | return -EINVAL; | |
3881 | } | |
3882 | ||
3883 | hw->rst_retries++; | |
3884 | csio_post_event(&hw->sm, CSIO_HWE_HBA_RESET); | |
3885 | ||
3886 | if (csio_is_hw_ready(hw)) { | |
3887 | hw->rst_retries = 0; | |
3888 | hw->stats.n_reset_start = jiffies_to_msecs(jiffies); | |
3889 | return 0; | |
3890 | } else | |
3891 | return -EINVAL; | |
3892 | } | |
3893 | ||
3894 | /* | |
3895 | * csio_hw_get_device_id - Caches the Adapter's vendor & device id. | |
3896 | * @hw: HW module. | |
3897 | */ | |
3898 | static void | |
3899 | csio_hw_get_device_id(struct csio_hw *hw) | |
3900 | { | |
3901 | /* Is the adapter device id cached already ?*/ | |
3902 | if (csio_is_dev_id_cached(hw)) | |
3903 | return; | |
3904 | ||
3905 | /* Get the PCI vendor & device id */ | |
3906 | pci_read_config_word(hw->pdev, PCI_VENDOR_ID, | |
3907 | &hw->params.pci.vendor_id); | |
3908 | pci_read_config_word(hw->pdev, PCI_DEVICE_ID, | |
3909 | &hw->params.pci.device_id); | |
3910 | ||
3911 | csio_dev_id_cached(hw); | |
7cc16380 | 3912 | hw->chip_id = (hw->params.pci.device_id & CSIO_HW_CHIP_MASK); |
a3667aae NKI |
3913 | |
3914 | } /* csio_hw_get_device_id */ | |
3915 | ||
3916 | /* | |
3917 | * csio_hw_set_description - Set the model, description of the hw. | |
3918 | * @hw: HW module. | |
3919 | * @ven_id: PCI Vendor ID | |
3920 | * @dev_id: PCI Device ID | |
3921 | */ | |
3922 | static void | |
3923 | csio_hw_set_description(struct csio_hw *hw, uint16_t ven_id, uint16_t dev_id) | |
3924 | { | |
3925 | uint32_t adap_type, prot_type; | |
3926 | ||
3927 | if (ven_id == CSIO_VENDOR_ID) { | |
3928 | prot_type = (dev_id & CSIO_ASIC_DEVID_PROTO_MASK); | |
3929 | adap_type = (dev_id & CSIO_ASIC_DEVID_TYPE_MASK); | |
3930 | ||
3fb4c22e | 3931 | if (prot_type == CSIO_T5_FCOE_ASIC) { |
a3667aae | 3932 | memcpy(hw->hw_ver, |
7cc16380 | 3933 | csio_t5_fcoe_adapters[adap_type].model_no, 16); |
a3667aae | 3934 | memcpy(hw->model_desc, |
7cc16380 AB |
3935 | csio_t5_fcoe_adapters[adap_type].description, |
3936 | 32); | |
a3667aae NKI |
3937 | } else { |
3938 | char tempName[32] = "Chelsio FCoE Controller"; | |
3939 | memcpy(hw->model_desc, tempName, 32); | |
a3667aae NKI |
3940 | } |
3941 | } | |
3942 | } /* csio_hw_set_description */ | |
3943 | ||
3944 | /** | |
3945 | * csio_hw_init - Initialize HW module. | |
3946 | * @hw: Pointer to HW module. | |
3947 | * | |
3948 | * Initialize the members of the HW module. | |
3949 | */ | |
3950 | int | |
3951 | csio_hw_init(struct csio_hw *hw) | |
3952 | { | |
3953 | int rv = -EINVAL; | |
3954 | uint32_t i; | |
3955 | uint16_t ven_id, dev_id; | |
3956 | struct csio_evt_msg *evt_entry; | |
3957 | ||
3958 | INIT_LIST_HEAD(&hw->sm.sm_list); | |
3959 | csio_init_state(&hw->sm, csio_hws_uninit); | |
3960 | spin_lock_init(&hw->lock); | |
3961 | INIT_LIST_HEAD(&hw->sln_head); | |
3962 | ||
3963 | /* Get the PCI vendor & device id */ | |
3964 | csio_hw_get_device_id(hw); | |
3965 | ||
3966 | strcpy(hw->name, CSIO_HW_NAME); | |
3967 | ||
3fb4c22e PM |
3968 | /* Initialize the HW chip ops T5 specific ops */ |
3969 | hw->chip_ops = &t5_ops; | |
7cc16380 | 3970 | |
a3667aae NKI |
3971 | /* Set the model & its description */ |
3972 | ||
3973 | ven_id = hw->params.pci.vendor_id; | |
3974 | dev_id = hw->params.pci.device_id; | |
3975 | ||
3976 | csio_hw_set_description(hw, ven_id, dev_id); | |
3977 | ||
3978 | /* Initialize default log level */ | |
3979 | hw->params.log_level = (uint32_t) csio_dbg_level; | |
3980 | ||
3981 | csio_set_fwevt_intr_idx(hw, -1); | |
3982 | csio_set_nondata_intr_idx(hw, -1); | |
3983 | ||
3984 | /* Init all the modules: Mailbox, WorkRequest and Transport */ | |
3985 | if (csio_mbm_init(csio_hw_to_mbm(hw), hw, csio_hw_mb_timer)) | |
3986 | goto err; | |
3987 | ||
3988 | rv = csio_wrm_init(csio_hw_to_wrm(hw), hw); | |
3989 | if (rv) | |
3990 | goto err_mbm_exit; | |
3991 | ||
3992 | rv = csio_scsim_init(csio_hw_to_scsim(hw), hw); | |
3993 | if (rv) | |
3994 | goto err_wrm_exit; | |
3995 | ||
3996 | rv = csio_mgmtm_init(csio_hw_to_mgmtm(hw), hw); | |
3997 | if (rv) | |
3998 | goto err_scsim_exit; | |
3999 | /* Pre-allocate evtq and initialize them */ | |
4000 | INIT_LIST_HEAD(&hw->evt_active_q); | |
4001 | INIT_LIST_HEAD(&hw->evt_free_q); | |
4002 | for (i = 0; i < csio_evtq_sz; i++) { | |
4003 | ||
4004 | evt_entry = kzalloc(sizeof(struct csio_evt_msg), GFP_KERNEL); | |
4005 | if (!evt_entry) { | |
ea47ebf1 | 4006 | rv = -ENOMEM; |
a3667aae NKI |
4007 | csio_err(hw, "Failed to initialize eventq"); |
4008 | goto err_evtq_cleanup; | |
4009 | } | |
4010 | ||
4011 | list_add_tail(&evt_entry->list, &hw->evt_free_q); | |
4012 | CSIO_INC_STATS(hw, n_evt_freeq); | |
4013 | } | |
4014 | ||
4015 | hw->dev_num = dev_num; | |
4016 | dev_num++; | |
4017 | ||
4018 | return 0; | |
4019 | ||
4020 | err_evtq_cleanup: | |
4021 | csio_evtq_cleanup(hw); | |
4022 | csio_mgmtm_exit(csio_hw_to_mgmtm(hw)); | |
4023 | err_scsim_exit: | |
4024 | csio_scsim_exit(csio_hw_to_scsim(hw)); | |
4025 | err_wrm_exit: | |
4026 | csio_wrm_exit(csio_hw_to_wrm(hw), hw); | |
4027 | err_mbm_exit: | |
4028 | csio_mbm_exit(csio_hw_to_mbm(hw)); | |
4029 | err: | |
4030 | return rv; | |
4031 | } | |
4032 | ||
4033 | /** | |
4034 | * csio_hw_exit - Un-initialize HW module. | |
4035 | * @hw: Pointer to HW module. | |
4036 | * | |
4037 | */ | |
4038 | void | |
4039 | csio_hw_exit(struct csio_hw *hw) | |
4040 | { | |
4041 | csio_evtq_cleanup(hw); | |
4042 | csio_mgmtm_exit(csio_hw_to_mgmtm(hw)); | |
4043 | csio_scsim_exit(csio_hw_to_scsim(hw)); | |
4044 | csio_wrm_exit(csio_hw_to_wrm(hw), hw); | |
4045 | csio_mbm_exit(csio_hw_to_mbm(hw)); | |
4046 | } |