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d69630e8 AB |
1 | /* |
2 | * This file is part of the Chelsio FCoE driver for Linux. | |
3 | * | |
4 | * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved. | |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #ifndef __CSIO_HW_CHIP_H__ | |
35 | #define __CSIO_HW_CHIP_H__ | |
36 | ||
37 | #include "csio_defs.h" | |
38 | ||
d69630e8 AB |
39 | /* Define MACRO values */ |
40 | #define CSIO_HW_T4 0x4000 | |
41 | #define CSIO_T4_FCOE_ASIC 0x4600 | |
42 | #define CSIO_HW_T5 0x5000 | |
43 | #define CSIO_T5_FCOE_ASIC 0x5600 | |
44 | #define CSIO_HW_CHIP_MASK 0xF000 | |
3fedeab1 | 45 | |
d69630e8 AB |
46 | #define T4_REGMAP_SIZE (160 * 1024) |
47 | #define T5_REGMAP_SIZE (332 * 1024) | |
48 | #define FW_FNAME_T4 "cxgb4/t4fw.bin" | |
49 | #define FW_FNAME_T5 "cxgb4/t5fw.bin" | |
50 | #define FW_CFG_NAME_T4 "cxgb4/t4-config.txt" | |
51 | #define FW_CFG_NAME_T5 "cxgb4/t5-config.txt" | |
52 | ||
53 | /* Define static functions */ | |
54 | static inline int csio_is_t4(uint16_t chip) | |
55 | { | |
56 | return (chip == CSIO_HW_T4); | |
57 | } | |
58 | ||
59 | static inline int csio_is_t5(uint16_t chip) | |
60 | { | |
61 | return (chip == CSIO_HW_T5); | |
62 | } | |
63 | ||
64 | /* Define MACRO DEFINITIONS */ | |
65 | #define CSIO_DEVICE(devid, idx) \ | |
66 | { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) } | |
67 | ||
68 | #define CSIO_HW_PIDX(hw, index) \ | |
f612b815 HS |
69 | (csio_is_t4(hw->chip_id) ? (PIDX_V(index)) : \ |
70 | (PIDX_T5_G(index) | DBTYPE_F)) | |
d69630e8 AB |
71 | |
72 | #define CSIO_HW_LP_INT_THRESH(hw, val) \ | |
f612b815 | 73 | (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_V(val)) : \ |
f061de42 | 74 | (LP_INT_THRESH_T5_V(val))) |
d69630e8 AB |
75 | |
76 | #define CSIO_HW_M_LP_INT_THRESH(hw) \ | |
f061de42 | 77 | (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_M) : (LP_INT_THRESH_T5_M)) |
d69630e8 AB |
78 | |
79 | #define CSIO_MAC_INT_CAUSE_REG(hw, port) \ | |
0d804338 HS |
80 | (csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE_A)) : \ |
81 | (T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A))) | |
d69630e8 AB |
82 | |
83 | #define FW_VERSION_MAJOR(hw) (csio_is_t4(hw->chip_id) ? 1 : 0) | |
84 | #define FW_VERSION_MINOR(hw) (csio_is_t4(hw->chip_id) ? 2 : 0) | |
85 | #define FW_VERSION_MICRO(hw) (csio_is_t4(hw->chip_id) ? 8 : 0) | |
86 | ||
87 | #define CSIO_FW_FNAME(hw) \ | |
88 | (csio_is_t4(hw->chip_id) ? FW_FNAME_T4 : FW_FNAME_T5) | |
89 | ||
90 | #define CSIO_CF_FNAME(hw) \ | |
91 | (csio_is_t4(hw->chip_id) ? FW_CFG_NAME_T4 : FW_CFG_NAME_T5) | |
92 | ||
93 | /* Declare ENUMS */ | |
94 | enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; | |
95 | ||
96 | enum { | |
97 | MEMWIN_APERTURE = 2048, | |
98 | MEMWIN_BASE = 0x1b800, | |
99 | MEMWIN_CSIOSTOR = 6, /* PCI-e Memory Window access */ | |
100 | }; | |
101 | ||
102 | /* Slow path handlers */ | |
103 | struct intr_info { | |
104 | unsigned int mask; /* bits to check in interrupt status */ | |
105 | const char *msg; /* message to print or NULL */ | |
106 | short stat_idx; /* stat counter to increment or -1 */ | |
107 | unsigned short fatal; /* whether the condition reported is fatal */ | |
108 | }; | |
109 | ||
110 | /* T4/T5 Chip specific ops */ | |
111 | struct csio_hw; | |
112 | struct csio_hw_chip_ops { | |
113 | int (*chip_set_mem_win)(struct csio_hw *, uint32_t); | |
114 | void (*chip_pcie_intr_handler)(struct csio_hw *); | |
115 | uint32_t (*chip_flash_cfg_addr)(struct csio_hw *); | |
116 | int (*chip_mc_read)(struct csio_hw *, int, uint32_t, | |
117 | __be32 *, uint64_t *); | |
118 | int (*chip_edc_read)(struct csio_hw *, int, uint32_t, | |
119 | __be32 *, uint64_t *); | |
120 | int (*chip_memory_rw)(struct csio_hw *, u32, int, u32, | |
121 | u32, uint32_t *, int); | |
122 | void (*chip_dfs_create_ext_mem)(struct csio_hw *); | |
123 | }; | |
124 | ||
125 | extern struct csio_hw_chip_ops t4_ops; | |
126 | extern struct csio_hw_chip_ops t5_ops; | |
127 | ||
128 | #endif /* #ifndef __CSIO_HW_CHIP_H__ */ |