[mirror_ubuntu-artful-kernel.git] / drivers / scsi / csiostor / csio_hw_chip.h

/*
 * This file is part of the Chelsio FCoE driver for Linux.
 *
 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __CSIO_HW_CHIP_H__
#define __CSIO_HW_CHIP_H__

#include "csio_defs.h"

/* Define MACRO values */
#define CSIO_HW_T5				0x5000
#define CSIO_T5_FCOE_ASIC			0x5600
#define CSIO_HW_CHIP_MASK			0xF000

#define T5_REGMAP_SIZE				(332 * 1024)
#define FW_FNAME_T5				"cxgb4/t5fw.bin"
#define FW_CFG_NAME_T5				"cxgb4/t5-config.txt"

#define T5FW_VERSION_MAJOR 0x01
#define T5FW_VERSION_MINOR 0x0B
#define T5FW_VERSION_MICRO 0x1B
#define T5FW_VERSION_BUILD 0x00

#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
#define CHELSIO_CHIP_FPGA          0x100
#define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf)
#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)

#define CHELSIO_T5		0x5

enum chip_type {
	T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
	T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
	T5_FIRST_REV	= T5_A0,
	T5_LAST_REV	= T5_A1,
};

static inline int csio_is_t5(uint16_t chip)
{
	return (chip == CSIO_HW_T5);
}

/* Define MACRO DEFINITIONS */
#define CSIO_DEVICE(devid, idx)						\
	{ PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }

#include "t4fw_api.h"

#define FW_VERSION(chip) ( \
		FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
		FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
		FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
		FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)

struct fw_info {
	u8 chip;
	char *fs_name;
	char *fw_mod_name;
	struct fw_hdr fw_hdr;
};

/* Declare ENUMS */
enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };

enum {
	MEMWIN_APERTURE = 2048,
	MEMWIN_BASE     = 0x1b800,
};

/* Slow path handlers */
struct intr_info {
	unsigned int mask;       /* bits to check in interrupt status */
	const char *msg;         /* message to print or NULL */
	short stat_idx;          /* stat counter to increment or -1 */
	unsigned short fatal;    /* whether the condition reported is fatal */
};

/* T4/T5 Chip specific ops */
struct csio_hw;
struct csio_hw_chip_ops {
	int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
	void (*chip_pcie_intr_handler)(struct csio_hw *);
	uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
	int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
					__be32 *, uint64_t *);
	int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
					__be32 *, uint64_t *);
	int (*chip_memory_rw)(struct csio_hw *, u32, int, u32,
					u32, uint32_t *, int);
	void (*chip_dfs_create_ext_mem)(struct csio_hw *);
};

extern struct csio_hw_chip_ops t5_ops;

#endif /* #ifndef __CSIO_HW_CHIP_H__ */
Commit	Line	Data
d69630e8 AB	1	/*
	2	* This file is part of the Chelsio FCoE driver for Linux.
	3	*
	4	* Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
	5	*
	6	* This software is available to you under a choice of one of two
	7	* licenses. You may choose to be licensed under the terms of the GNU
	8	* General Public License (GPL) Version 2, available from the file
	9	* OpenIB.org BSD license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or
	12	* without modification, are permitted provided that the following
	13	* conditions are met:
	14	*
	15	* - Redistributions of source code must retain the above
	16	* copyright notice, this list of conditions and the following
	17	* disclaimer.
	18	*
	19	* - Redistributions in binary form must reproduce the above
	20	* copyright notice, this list of conditions and the following
	21	* disclaimer in the documentation and/or other materials
	22	* provided with the distribution.
	23	*
	24	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	25	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	26	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	27	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	28	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	29	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	30	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	31	* SOFTWARE.
	32	*/
	33
	34	#ifndef __CSIO_HW_CHIP_H__
	35	#define __CSIO_HW_CHIP_H__
	36
	37	#include "csio_defs.h"
	38
d69630e8	39	/* Define MACRO values */
d69630e8 AB	40	#define CSIO_HW_T5 0x5000
	41	#define CSIO_T5_FCOE_ASIC 0x5600
	42	#define CSIO_HW_CHIP_MASK 0xF000
3fedeab1	43
d69630e8	44	#define T5_REGMAP_SIZE (332 * 1024)
d69630e8	45	#define FW_FNAME_T5 "cxgb4/t5fw.bin"
d69630e8 AB	46	#define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
d69630e8 AB	47
f40e74ff PM	48	#define T5FW_VERSION_MAJOR 0x01
	49	#define T5FW_VERSION_MINOR 0x0B
	50	#define T5FW_VERSION_MICRO 0x1B
	51	#define T5FW_VERSION_BUILD 0x00
	52
	53	#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) \| (revision))
	54	#define CHELSIO_CHIP_FPGA 0x100
	55	#define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf)
	56	#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
	57
f40e74ff PM	58	#define CHELSIO_T5 0x5
	59
	60	enum chip_type {
f40e74ff PM	61	T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
	62	T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
	63	T5_FIRST_REV = T5_A0,
	64	T5_LAST_REV = T5_A1,
	65	};
	66
d69630e8 AB	67	static inline int csio_is_t5(uint16_t chip)
	68	{
	69	return (chip == CSIO_HW_T5);
	70	}
	71
	72	/* Define MACRO DEFINITIONS */
	73	#define CSIO_DEVICE(devid, idx) \
	74	{ PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
	75
f40e74ff PM	76	#include "t4fw_api.h"
	77
	78	#define FW_VERSION(chip) ( \
	79	FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) \| \
	80	FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) \| \
	81	FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) \| \
	82	FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
	83	#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
	84
	85	struct fw_info {
	86	u8 chip;
	87	char *fs_name;
	88	char *fw_mod_name;
	89	struct fw_hdr fw_hdr;
	90	};
d69630e8 AB	91
	92	/* Declare ENUMS */
	93	enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
	94
	95	enum {
	96	MEMWIN_APERTURE = 2048,
	97	MEMWIN_BASE = 0x1b800,
d69630e8 AB	98	};
	99
	100	/* Slow path handlers */
	101	struct intr_info {
	102	unsigned int mask; /* bits to check in interrupt status */
	103	const char msg; / message to print or NULL */
	104	short stat_idx; /* stat counter to increment or -1 */
	105	unsigned short fatal; /* whether the condition reported is fatal */
	106	};
	107
	108	/* T4/T5 Chip specific ops */
	109	struct csio_hw;
	110	struct csio_hw_chip_ops {
	111	int (chip_set_mem_win)(struct csio_hw , uint32_t);
	112	void (chip_pcie_intr_handler)(struct csio_hw );
	113	uint32_t (chip_flash_cfg_addr)(struct csio_hw );
	114	int (chip_mc_read)(struct csio_hw , int, uint32_t,
	115	__be32 , uint64_t );
	116	int (chip_edc_read)(struct csio_hw , int, uint32_t,
	117	__be32 , uint64_t );
	118	int (chip_memory_rw)(struct csio_hw , u32, int, u32,
	119	u32, uint32_t *, int);
	120	void (chip_dfs_create_ext_mem)(struct csio_hw );
	121	};
	122
d69630e8 AB	123	extern struct csio_hw_chip_ops t5_ops;
	124
	125	#endif /* #ifndef __CSIO_HW_CHIP_H__ */