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esp_scsi: read status registers
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / esp_scsi.c
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cd9ad58d
DM		 1/* esp_scsi.c: ESP SCSI driver.
2 *
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/kernel.h>
7#include <linux/types.h>
8#include <linux/slab.h>
9#include <linux/delay.h>
10#include <linux/list.h>
11#include <linux/completion.h>
12#include <linux/kallsyms.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
e1f2a094 16#include <linux/irqreturn.h>
cd9ad58d
DM		 17
18#include <asm/irq.h>
19#include <asm/io.h>
20#include <asm/dma.h>
21
22#include <scsi/scsi.h>
23#include <scsi/scsi_host.h>
24#include <scsi/scsi_cmnd.h>
25#include <scsi/scsi_device.h>
26#include <scsi/scsi_tcq.h>
27#include <scsi/scsi_dbg.h>
28#include <scsi/scsi_transport_spi.h>
29
30#include "esp_scsi.h"
31
32#define DRV_MODULE_NAME "esp"
33#define PFX DRV_MODULE_NAME ": "
34#define DRV_VERSION "2.000"
35#define DRV_MODULE_RELDATE "April 19, 2007"
36
37/* SCSI bus reset settle time in seconds. */
38static int esp_bus_reset_settle = 3;
39
40static u32 esp_debug;
41#define ESP_DEBUG_INTR 0x00000001
42#define ESP_DEBUG_SCSICMD 0x00000002
43#define ESP_DEBUG_RESET 0x00000004
44#define ESP_DEBUG_MSGIN 0x00000008
45#define ESP_DEBUG_MSGOUT 0x00000010
46#define ESP_DEBUG_CMDDONE 0x00000020
47#define ESP_DEBUG_DISCONNECT 0x00000040
48#define ESP_DEBUG_DATASTART 0x00000080
49#define ESP_DEBUG_DATADONE 0x00000100
50#define ESP_DEBUG_RECONNECT 0x00000200
51#define ESP_DEBUG_AUTOSENSE 0x00000400
1af6f603
HR		 52#define ESP_DEBUG_EVENT 0x00000800
53#define ESP_DEBUG_COMMAND 0x00001000
cd9ad58d
DM		 54
55#define esp_log_intr(f, a...) \
56do { if (esp_debug & ESP_DEBUG_INTR) \
a1a75b35 57 shost_printk(KERN_DEBUG, esp->host, f, ## a); \
cd9ad58d
DM		 58} while (0)
59
60#define esp_log_reset(f, a...) \
61do { if (esp_debug & ESP_DEBUG_RESET) \
a1a75b35 62 shost_printk(KERN_DEBUG, esp->host, f, ## a); \
cd9ad58d
DM		 63} while (0)
64
65#define esp_log_msgin(f, a...) \
66do { if (esp_debug & ESP_DEBUG_MSGIN) \
a1a75b35 67 shost_printk(KERN_DEBUG, esp->host, f, ## a); \
cd9ad58d
DM		 68} while (0)
69
70#define esp_log_msgout(f, a...) \
71do { if (esp_debug & ESP_DEBUG_MSGOUT) \
a1a75b35 72 shost_printk(KERN_DEBUG, esp->host, f, ## a); \
cd9ad58d
DM		 73} while (0)
74
75#define esp_log_cmddone(f, a...) \
76do { if (esp_debug & ESP_DEBUG_CMDDONE) \
a1a75b35 77 shost_printk(KERN_DEBUG, esp->host, f, ## a); \
cd9ad58d
DM		 78} while (0)
79
80#define esp_log_disconnect(f, a...) \
81do { if (esp_debug & ESP_DEBUG_DISCONNECT) \
a1a75b35 82 shost_printk(KERN_DEBUG, esp->host, f, ## a); \
cd9ad58d
DM		 83} while (0)
84
85#define esp_log_datastart(f, a...) \
86do { if (esp_debug & ESP_DEBUG_DATASTART) \
a1a75b35 87 shost_printk(KERN_DEBUG, esp->host, f, ## a); \
cd9ad58d
DM		 88} while (0)
89
90#define esp_log_datadone(f, a...) \
91do { if (esp_debug & ESP_DEBUG_DATADONE) \
a1a75b35 92 shost_printk(KERN_DEBUG, esp->host, f, ## a); \
cd9ad58d
DM		 93} while (0)
94
95#define esp_log_reconnect(f, a...) \
96do { if (esp_debug & ESP_DEBUG_RECONNECT) \
a1a75b35 97 shost_printk(KERN_DEBUG, esp->host, f, ## a); \
cd9ad58d
DM		 98} while (0)
99
100#define esp_log_autosense(f, a...) \
101do { if (esp_debug & ESP_DEBUG_AUTOSENSE) \
a1a75b35 102 shost_printk(KERN_DEBUG, esp->host, f, ## a); \
cd9ad58d
DM		 103} while (0)
104
1af6f603
HR		 105#define esp_log_event(f, a...) \
106do { if (esp_debug & ESP_DEBUG_EVENT) \
107 shost_printk(KERN_DEBUG, esp->host, f, ## a); \
108} while (0)
109
110#define esp_log_command(f, a...) \
111do { if (esp_debug & ESP_DEBUG_COMMAND) \
112 shost_printk(KERN_DEBUG, esp->host, f, ## a); \
113} while (0)
114
cd9ad58d
DM		 115#define esp_read8(REG) esp->ops->esp_read8(esp, REG)
116#define esp_write8(VAL,REG) esp->ops->esp_write8(esp, VAL, REG)
117
118static void esp_log_fill_regs(struct esp *esp,
119 struct esp_event_ent *p)
120{
121 p->sreg = esp->sreg;
122 p->seqreg = esp->seqreg;
123 p->sreg2 = esp->sreg2;
124 p->ireg = esp->ireg;
125 p->select_state = esp->select_state;
126 p->event = esp->event;
127}
128
129void scsi_esp_cmd(struct esp *esp, u8 val)
130{
131 struct esp_event_ent *p;
132 int idx = esp->esp_event_cur;
133
134 p = &esp->esp_event_log[idx];
135 p->type = ESP_EVENT_TYPE_CMD;
136 p->val = val;
137 esp_log_fill_regs(esp, p);
138
139 esp->esp_event_cur = (idx + 1) & (ESP_EVENT_LOG_SZ - 1);
140
1af6f603 141 esp_log_command("cmd[%02x]\n", val);
cd9ad58d
DM		 142 esp_write8(val, ESP_CMD);
143}
144EXPORT_SYMBOL(scsi_esp_cmd);
145
146static void esp_event(struct esp *esp, u8 val)
147{
148 struct esp_event_ent *p;
149 int idx = esp->esp_event_cur;
150
151 p = &esp->esp_event_log[idx];
152 p->type = ESP_EVENT_TYPE_EVENT;
153 p->val = val;
154 esp_log_fill_regs(esp, p);
155
156 esp->esp_event_cur = (idx + 1) & (ESP_EVENT_LOG_SZ - 1);
157
158 esp->event = val;
159}
160
161static void esp_dump_cmd_log(struct esp *esp)
162{
163 int idx = esp->esp_event_cur;
164 int stop = idx;
165
a1a75b35 166 shost_printk(KERN_INFO, esp->host, "Dumping command log\n");
cd9ad58d
DM		 167 do {
168 struct esp_event_ent *p = &esp->esp_event_log[idx];
169
a1a75b35
HR		 170 shost_printk(KERN_INFO, esp->host,
171 "ent[%d] %s val[%02x] sreg[%02x] seqreg[%02x] "
172 "sreg2[%02x] ireg[%02x] ss[%02x] event[%02x]\n",
173 idx,
174 p->type == ESP_EVENT_TYPE_CMD ? "CMD" : "EVENT",
175 p->val, p->sreg, p->seqreg,
176 p->sreg2, p->ireg, p->select_state, p->event);
cd9ad58d
DM		 177
178 idx = (idx + 1) & (ESP_EVENT_LOG_SZ - 1);
179 } while (idx != stop);
180}
181
182static void esp_flush_fifo(struct esp *esp)
183{
184 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
185 if (esp->rev == ESP236) {
186 int lim = 1000;
187
188 while (esp_read8(ESP_FFLAGS) & ESP_FF_FBYTES) {
189 if (--lim == 0) {
a1a75b35
HR		 190 shost_printk(KERN_ALERT, esp->host,
191 "ESP_FF_BYTES will not clear!\n");
cd9ad58d
DM		 192 break;
193 }
194 udelay(1);
195 }
196 }
197}
198
199static void hme_read_fifo(struct esp *esp)
200{
201 int fcnt = esp_read8(ESP_FFLAGS) & ESP_FF_FBYTES;
202 int idx = 0;
203
204 while (fcnt--) {
205 esp->fifo[idx++] = esp_read8(ESP_FDATA);
206 esp->fifo[idx++] = esp_read8(ESP_FDATA);
207 }
208 if (esp->sreg2 & ESP_STAT2_F1BYTE) {
209 esp_write8(0, ESP_FDATA);
210 esp->fifo[idx++] = esp_read8(ESP_FDATA);
211 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
212 }
213 esp->fifo_cnt = idx;
214}
215
216static void esp_set_all_config3(struct esp *esp, u8 val)
217{
218 int i;
219
220 for (i = 0; i < ESP_MAX_TARGET; i++)
221 esp->target[i].esp_config3 = val;
222}
223
224/* Reset the ESP chip, _not_ the SCSI bus. */
225static void esp_reset_esp(struct esp *esp)
226{
227 u8 family_code, version;
228
229 /* Now reset the ESP chip */
230 scsi_esp_cmd(esp, ESP_CMD_RC);
231 scsi_esp_cmd(esp, ESP_CMD_NULL | ESP_CMD_DMA);
a793804f
DM		 232 if (esp->rev == FAST)
233 esp_write8(ESP_CONFIG2_FENAB, ESP_CFG2);
cd9ad58d
DM		 234 scsi_esp_cmd(esp, ESP_CMD_NULL | ESP_CMD_DMA);
235
cd9ad58d
DM		 236 /* This is the only point at which it is reliable to read
237 * the ID-code for a fast ESP chip variants.
238 */
239 esp->max_period = ((35 * esp->ccycle) / 1000);
240 if (esp->rev == FAST) {
241 version = esp_read8(ESP_UID);
242 family_code = (version & 0xf8) >> 3;
243 if (family_code == 0x02)
244 esp->rev = FAS236;
245 else if (family_code == 0x0a)
246 esp->rev = FASHME; /* Version is usually '5'. */
247 else
248 esp->rev = FAS100A;
249 esp->min_period = ((4 * esp->ccycle) / 1000);
250 } else {
251 esp->min_period = ((5 * esp->ccycle) / 1000);
252 }
253 esp->max_period = (esp->max_period + 3)>>2;
254 esp->min_period = (esp->min_period + 3)>>2;
255
256 esp_write8(esp->config1, ESP_CFG1);
257 switch (esp->rev) {
258 case ESP100:
259 /* nothing to do */
260 break;
261
262 case ESP100A:
263 esp_write8(esp->config2, ESP_CFG2);
264 break;
265
266 case ESP236:
267 /* Slow 236 */
268 esp_write8(esp->config2, ESP_CFG2);
269 esp->prev_cfg3 = esp->target[0].esp_config3;
270 esp_write8(esp->prev_cfg3, ESP_CFG3);
271 break;
272
273 case FASHME:
274 esp->config2 |= (ESP_CONFIG2_HME32 | ESP_CONFIG2_HMEFENAB);
275 /* fallthrough... */
276
277 case FAS236:
278 /* Fast 236 or HME */
279 esp_write8(esp->config2, ESP_CFG2);
280 if (esp->rev == FASHME) {
281 u8 cfg3 = esp->target[0].esp_config3;
282
283 cfg3 |= ESP_CONFIG3_FCLOCK | ESP_CONFIG3_OBPUSH;
284 if (esp->scsi_id >= 8)
285 cfg3 |= ESP_CONFIG3_IDBIT3;
286 esp_set_all_config3(esp, cfg3);
287 } else {
288 u32 cfg3 = esp->target[0].esp_config3;
289
290 cfg3 |= ESP_CONFIG3_FCLK;
291 esp_set_all_config3(esp, cfg3);
292 }
293 esp->prev_cfg3 = esp->target[0].esp_config3;
294 esp_write8(esp->prev_cfg3, ESP_CFG3);
295 if (esp->rev == FASHME) {
296 esp->radelay = 80;
297 } else {
298 if (esp->flags & ESP_FLAG_DIFFERENTIAL)
299 esp->radelay = 0;
300 else
301 esp->radelay = 96;
302 }
303 break;
304
305 case FAS100A:
306 /* Fast 100a */
307 esp_write8(esp->config2, ESP_CFG2);
308 esp_set_all_config3(esp,
309 (esp->target[0].esp_config3 |
310 ESP_CONFIG3_FCLOCK));
311 esp->prev_cfg3 = esp->target[0].esp_config3;
312 esp_write8(esp->prev_cfg3, ESP_CFG3);
313 esp->radelay = 32;
314 break;
315
316 default:
317 break;
318 }
319
a793804f
DM		 320 /* Reload the configuration registers */
321 esp_write8(esp->cfact, ESP_CFACT);
322
323 esp->prev_stp = 0;
324 esp_write8(esp->prev_stp, ESP_STP);
325
326 esp->prev_soff = 0;
327 esp_write8(esp->prev_soff, ESP_SOFF);
328
329 esp_write8(esp->neg_defp, ESP_TIMEO);
330
cd9ad58d
DM		 331 /* Eat any bitrot in the chip */
332 esp_read8(ESP_INTRPT);
333 udelay(100);
334}
335
336static void esp_map_dma(struct esp *esp, struct scsi_cmnd *cmd)
337{
338 struct esp_cmd_priv *spriv = ESP_CMD_PRIV(cmd);
4c2baaaf 339 struct scatterlist *sg = scsi_sglist(cmd);
cd9ad58d
DM		 340 int dir = cmd->sc_data_direction;
341 int total, i;
342
343 if (dir == DMA_NONE)
344 return;
345
4c2baaaf 346 spriv->u.num_sg = esp->ops->map_sg(esp, sg, scsi_sg_count(cmd), dir);
cd9ad58d
DM		 347 spriv->cur_residue = sg_dma_len(sg);
348 spriv->cur_sg = sg;
349
350 total = 0;
351 for (i = 0; i < spriv->u.num_sg; i++)
352 total += sg_dma_len(&sg[i]);
353 spriv->tot_residue = total;
354}
355
356static dma_addr_t esp_cur_dma_addr(struct esp_cmd_entry *ent,
357 struct scsi_cmnd *cmd)
358{
359 struct esp_cmd_priv *p = ESP_CMD_PRIV(cmd);
360
361 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
362 return ent->sense_dma +
363 (ent->sense_ptr - cmd->sense_buffer);
364 }
365
366 return sg_dma_address(p->cur_sg) +
367 (sg_dma_len(p->cur_sg) -
368 p->cur_residue);
369}
370
371static unsigned int esp_cur_dma_len(struct esp_cmd_entry *ent,
372 struct scsi_cmnd *cmd)
373{
374 struct esp_cmd_priv *p = ESP_CMD_PRIV(cmd);
375
376 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
377 return SCSI_SENSE_BUFFERSIZE -
378 (ent->sense_ptr - cmd->sense_buffer);
379 }
380 return p->cur_residue;
381}
382
383static void esp_advance_dma(struct esp *esp, struct esp_cmd_entry *ent,
384 struct scsi_cmnd *cmd, unsigned int len)
385{
386 struct esp_cmd_priv *p = ESP_CMD_PRIV(cmd);
387
388 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
389 ent->sense_ptr += len;
390 return;
391 }
392
393 p->cur_residue -= len;
394 p->tot_residue -= len;
395 if (p->cur_residue < 0 || p->tot_residue < 0) {
a1a75b35
HR		 396 shost_printk(KERN_ERR, esp->host,
397 "Data transfer overflow.\n");
398 shost_printk(KERN_ERR, esp->host,
399 "cur_residue[%d] tot_residue[%d] len[%u]\n",
400 p->cur_residue, p->tot_residue, len);
cd9ad58d
DM		 401 p->cur_residue = 0;
402 p->tot_residue = 0;
403 }
404 if (!p->cur_residue && p->tot_residue) {
405 p->cur_sg++;
406 p->cur_residue = sg_dma_len(p->cur_sg);
407 }
408}
409
410static void esp_unmap_dma(struct esp *esp, struct scsi_cmnd *cmd)
411{
412 struct esp_cmd_priv *spriv = ESP_CMD_PRIV(cmd);
413 int dir = cmd->sc_data_direction;
414
415 if (dir == DMA_NONE)
416 return;
417
4c2baaaf 418 esp->ops->unmap_sg(esp, scsi_sglist(cmd), spriv->u.num_sg, dir);
cd9ad58d
DM		 419}
420
421static void esp_save_pointers(struct esp *esp, struct esp_cmd_entry *ent)
422{
423 struct scsi_cmnd *cmd = ent->cmd;
424 struct esp_cmd_priv *spriv = ESP_CMD_PRIV(cmd);
425
426 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
427 ent->saved_sense_ptr = ent->sense_ptr;
428 return;
429 }
430 ent->saved_cur_residue = spriv->cur_residue;
431 ent->saved_cur_sg = spriv->cur_sg;
432 ent->saved_tot_residue = spriv->tot_residue;
433}
434
435static void esp_restore_pointers(struct esp *esp, struct esp_cmd_entry *ent)
436{
437 struct scsi_cmnd *cmd = ent->cmd;
438 struct esp_cmd_priv *spriv = ESP_CMD_PRIV(cmd);
439
440 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
441 ent->sense_ptr = ent->saved_sense_ptr;
442 return;
443 }
444 spriv->cur_residue = ent->saved_cur_residue;
445 spriv->cur_sg = ent->saved_cur_sg;
446 spriv->tot_residue = ent->saved_tot_residue;
447}
448
449static void esp_check_command_len(struct esp *esp, struct scsi_cmnd *cmd)
450{
451 if (cmd->cmd_len == 6 ||
452 cmd->cmd_len == 10 ||
453 cmd->cmd_len == 12) {
454 esp->flags &= ~ESP_FLAG_DOING_SLOWCMD;
455 } else {
456 esp->flags |= ESP_FLAG_DOING_SLOWCMD;
457 }
458}
459
460static void esp_write_tgt_config3(struct esp *esp, int tgt)
461{
462 if (esp->rev > ESP100A) {
463 u8 val = esp->target[tgt].esp_config3;
464
465 if (val != esp->prev_cfg3) {
466 esp->prev_cfg3 = val;
467 esp_write8(val, ESP_CFG3);
468 }
469 }
470}
471
472static void esp_write_tgt_sync(struct esp *esp, int tgt)
473{
474 u8 off = esp->target[tgt].esp_offset;
475 u8 per = esp->target[tgt].esp_period;
476
477 if (off != esp->prev_soff) {
478 esp->prev_soff = off;
479 esp_write8(off, ESP_SOFF);
480 }
481 if (per != esp->prev_stp) {
482 esp->prev_stp = per;
483 esp_write8(per, ESP_STP);
484 }
485}
486
487static u32 esp_dma_length_limit(struct esp *esp, u32 dma_addr, u32 dma_len)
488{
489 if (esp->rev == FASHME) {
490 /* Arbitrary segment boundaries, 24-bit counts. */
491 if (dma_len > (1U << 24))
492 dma_len = (1U << 24);
493 } else {
494 u32 base, end;
495
496 /* ESP chip limits other variants by 16-bits of transfer
497 * count. Actually on FAS100A and FAS236 we could get
498 * 24-bits of transfer count by enabling ESP_CONFIG2_FENAB
499 * in the ESP_CFG2 register but that causes other unwanted
500 * changes so we don't use it currently.
501 */
502 if (dma_len > (1U << 16))
503 dma_len = (1U << 16);
504
505 /* All of the DMA variants hooked up to these chips
506 * cannot handle crossing a 24-bit address boundary.
507 */
508 base = dma_addr & ((1U << 24) - 1U);
509 end = base + dma_len;
510 if (end > (1U << 24))
511 end = (1U <<24);
512 dma_len = end - base;
513 }
514 return dma_len;
515}
516
517static int esp_need_to_nego_wide(struct esp_target_data *tp)
518{
519 struct scsi_target *target = tp->starget;
520
521 return spi_width(target) != tp->nego_goal_width;
522}
523
524static int esp_need_to_nego_sync(struct esp_target_data *tp)
525{
526 struct scsi_target *target = tp->starget;
527
528 /* When offset is zero, period is "don't care". */
529 if (!spi_offset(target) && !tp->nego_goal_offset)
530 return 0;
531
532 if (spi_offset(target) == tp->nego_goal_offset &&
533 spi_period(target) == tp->nego_goal_period)
534 return 0;
535
536 return 1;
537}
538
539static int esp_alloc_lun_tag(struct esp_cmd_entry *ent,
540 struct esp_lun_data *lp)
541{
21af8107 542 if (!ent->orig_tag[0]) {
cd9ad58d
DM		 543 /* Non-tagged, slot already taken? */
544 if (lp->non_tagged_cmd)
545 return -EBUSY;
546
547 if (lp->hold) {
548 /* We are being held by active tagged
549 * commands.
550 */
551 if (lp->num_tagged)
552 return -EBUSY;
553
554 /* Tagged commands completed, we can unplug
555 * the queue and run this untagged command.
556 */
557 lp->hold = 0;
558 } else if (lp->num_tagged) {
559 /* Plug the queue until num_tagged decreases
560 * to zero in esp_free_lun_tag.
561 */
562 lp->hold = 1;
563 return -EBUSY;
564 }
565
566 lp->non_tagged_cmd = ent;
567 return 0;
568 } else {
569 /* Tagged command, see if blocked by a
570 * non-tagged one.
571 */
572 if (lp->non_tagged_cmd || lp->hold)
573 return -EBUSY;
574 }
575
21af8107 576 BUG_ON(lp->tagged_cmds[ent->orig_tag[1]]);
cd9ad58d 577
21af8107 578 lp->tagged_cmds[ent->orig_tag[1]] = ent;
cd9ad58d
DM		 579 lp->num_tagged++;
580
581 return 0;
582}
583
584static void esp_free_lun_tag(struct esp_cmd_entry *ent,
585 struct esp_lun_data *lp)
586{
21af8107
DM		 587 if (ent->orig_tag[0]) {
588 BUG_ON(lp->tagged_cmds[ent->orig_tag[1]] != ent);
589 lp->tagged_cmds[ent->orig_tag[1]] = NULL;
cd9ad58d
DM		 590 lp->num_tagged--;
591 } else {
592 BUG_ON(lp->non_tagged_cmd != ent);
593 lp->non_tagged_cmd = NULL;
594 }
595}
596
597/* When a contingent allegiance conditon is created, we force feed a
598 * REQUEST_SENSE command to the device to fetch the sense data. I
599 * tried many other schemes, relying on the scsi error handling layer
600 * to send out the REQUEST_SENSE automatically, but this was difficult
601 * to get right especially in the presence of applications like smartd
602 * which use SG_IO to send out their own REQUEST_SENSE commands.
603 */
604static void esp_autosense(struct esp *esp, struct esp_cmd_entry *ent)
605{
606 struct scsi_cmnd *cmd = ent->cmd;
607 struct scsi_device *dev = cmd->device;
608 int tgt, lun;
609 u8 *p, val;
610
611 tgt = dev->id;
612 lun = dev->lun;
613
614
615 if (!ent->sense_ptr) {
a1a75b35
HR		 616 esp_log_autosense("Doing auto-sense for tgt[%d] lun[%d]\n",
617 tgt, lun);
cd9ad58d
DM		 618
619 ent->sense_ptr = cmd->sense_buffer;
620 ent->sense_dma = esp->ops->map_single(esp,
621 ent->sense_ptr,
622 SCSI_SENSE_BUFFERSIZE,
623 DMA_FROM_DEVICE);
624 }
625 ent->saved_sense_ptr = ent->sense_ptr;
626
627 esp->active_cmd = ent;
628
629 p = esp->command_block;
630 esp->msg_out_len = 0;
631
632 *p++ = IDENTIFY(0, lun);
633 *p++ = REQUEST_SENSE;
634 *p++ = ((dev->scsi_level <= SCSI_2) ?
635 (lun << 5) : 0);
636 *p++ = 0;
637 *p++ = 0;
638 *p++ = SCSI_SENSE_BUFFERSIZE;
639 *p++ = 0;
640
641 esp->select_state = ESP_SELECT_BASIC;
642
643 val = tgt;
644 if (esp->rev == FASHME)
645 val |= ESP_BUSID_RESELID | ESP_BUSID_CTR32BIT;
646 esp_write8(val, ESP_BUSID);
647
648 esp_write_tgt_sync(esp, tgt);
649 esp_write_tgt_config3(esp, tgt);
650
651 val = (p - esp->command_block);
652
653 if (esp->rev == FASHME)
654 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
655 esp->ops->send_dma_cmd(esp, esp->command_block_dma,
656 val, 16, 0, ESP_CMD_DMA | ESP_CMD_SELA);
657}
658
659static struct esp_cmd_entry *find_and_prep_issuable_command(struct esp *esp)
660{
661 struct esp_cmd_entry *ent;
662
663 list_for_each_entry(ent, &esp->queued_cmds, list) {
664 struct scsi_cmnd *cmd = ent->cmd;
665 struct scsi_device *dev = cmd->device;
666 struct esp_lun_data *lp = dev->hostdata;
667
668 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
669 ent->tag[0] = 0;
670 ent->tag[1] = 0;
671 return ent;
672 }
673
50668633 674 if (!spi_populate_tag_msg(&ent->tag[0], cmd)) {
cd9ad58d
DM		 675 ent->tag[0] = 0;
676 ent->tag[1] = 0;
677 }
21af8107
DM		 678 ent->orig_tag[0] = ent->tag[0];
679 ent->orig_tag[1] = ent->tag[1];
cd9ad58d
DM		 680
681 if (esp_alloc_lun_tag(ent, lp) < 0)
682 continue;
683
684 return ent;
685 }
686
687 return NULL;
688}
689
690static void esp_maybe_execute_command(struct esp *esp)
691{
692 struct esp_target_data *tp;
693 struct esp_lun_data *lp;
694 struct scsi_device *dev;
695 struct scsi_cmnd *cmd;
696 struct esp_cmd_entry *ent;
697 int tgt, lun, i;
698 u32 val, start_cmd;
699 u8 *p;
700
701 if (esp->active_cmd ||
702 (esp->flags & ESP_FLAG_RESETTING))
703 return;
704
705 ent = find_and_prep_issuable_command(esp);
706 if (!ent)
707 return;
708
709 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
710 esp_autosense(esp, ent);
711 return;
712 }
713
714 cmd = ent->cmd;
715 dev = cmd->device;
716 tgt = dev->id;
717 lun = dev->lun;
718 tp = &esp->target[tgt];
719 lp = dev->hostdata;
720
63ce2499 721 list_move(&ent->list, &esp->active_cmds);
cd9ad58d
DM		 722
723 esp->active_cmd = ent;
724
725 esp_map_dma(esp, cmd);
726 esp_save_pointers(esp, ent);
727
728 esp_check_command_len(esp, cmd);
729
730 p = esp->command_block;
731
732 esp->msg_out_len = 0;
733 if (tp->flags & ESP_TGT_CHECK_NEGO) {
734 /* Need to negotiate. If the target is broken
735 * go for synchronous transfers and non-wide.
736 */
737 if (tp->flags & ESP_TGT_BROKEN) {
738 tp->flags &= ~ESP_TGT_DISCONNECT;
739 tp->nego_goal_period = 0;
740 tp->nego_goal_offset = 0;
741 tp->nego_goal_width = 0;
742 tp->nego_goal_tags = 0;
743 }
744
745 /* If the settings are not changing, skip this. */
746 if (spi_width(tp->starget) == tp->nego_goal_width &&
747 spi_period(tp->starget) == tp->nego_goal_period &&
748 spi_offset(tp->starget) == tp->nego_goal_offset) {
749 tp->flags &= ~ESP_TGT_CHECK_NEGO;
750 goto build_identify;
751 }
752
753 if (esp->rev == FASHME && esp_need_to_nego_wide(tp)) {
754 esp->msg_out_len =
755 spi_populate_width_msg(&esp->msg_out[0],
756 (tp->nego_goal_width ?
757 1 : 0));
758 tp->flags |= ESP_TGT_NEGO_WIDE;
759 } else if (esp_need_to_nego_sync(tp)) {
760 esp->msg_out_len =
761 spi_populate_sync_msg(&esp->msg_out[0],
762 tp->nego_goal_period,
763 tp->nego_goal_offset);
764 tp->flags |= ESP_TGT_NEGO_SYNC;
765 } else {
766 tp->flags &= ~ESP_TGT_CHECK_NEGO;
767 }
768
769 /* Process it like a slow command. */
770 if (tp->flags & (ESP_TGT_NEGO_WIDE | ESP_TGT_NEGO_SYNC))
771 esp->flags |= ESP_FLAG_DOING_SLOWCMD;
772 }
773
774build_identify:
775 /* If we don't have a lun-data struct yet, we're probing
776 * so do not disconnect. Also, do not disconnect unless
777 * we have a tag on this command.
778 */
779 if (lp && (tp->flags & ESP_TGT_DISCONNECT) && ent->tag[0])
780 *p++ = IDENTIFY(1, lun);
781 else
782 *p++ = IDENTIFY(0, lun);
783
784 if (ent->tag[0] && esp->rev == ESP100) {
785 /* ESP100 lacks select w/atn3 command, use select
786 * and stop instead.
787 */
788 esp->flags |= ESP_FLAG_DOING_SLOWCMD;
789 }
790
791 if (!(esp->flags & ESP_FLAG_DOING_SLOWCMD)) {
792 start_cmd = ESP_CMD_DMA | ESP_CMD_SELA;
793 if (ent->tag[0]) {
794 *p++ = ent->tag[0];
795 *p++ = ent->tag[1];
796
797 start_cmd = ESP_CMD_DMA | ESP_CMD_SA3;
798 }
799
800 for (i = 0; i < cmd->cmd_len; i++)
801 *p++ = cmd->cmnd[i];
802
803 esp->select_state = ESP_SELECT_BASIC;
804 } else {
805 esp->cmd_bytes_left = cmd->cmd_len;
806 esp->cmd_bytes_ptr = &cmd->cmnd[0];
807
808 if (ent->tag[0]) {
809 for (i = esp->msg_out_len - 1;
810 i >= 0; i--)
811 esp->msg_out[i + 2] = esp->msg_out[i];
812 esp->msg_out[0] = ent->tag[0];
813 esp->msg_out[1] = ent->tag[1];
814 esp->msg_out_len += 2;
815 }
816
817 start_cmd = ESP_CMD_DMA | ESP_CMD_SELAS;
818 esp->select_state = ESP_SELECT_MSGOUT;
819 }
820 val = tgt;
821 if (esp->rev == FASHME)
822 val |= ESP_BUSID_RESELID | ESP_BUSID_CTR32BIT;
823 esp_write8(val, ESP_BUSID);
824
825 esp_write_tgt_sync(esp, tgt);
826 esp_write_tgt_config3(esp, tgt);
827
828 val = (p - esp->command_block);
829
830 if (esp_debug & ESP_DEBUG_SCSICMD) {
831 printk("ESP: tgt[%d] lun[%d] scsi_cmd [ ", tgt, lun);
832 for (i = 0; i < cmd->cmd_len; i++)
833 printk("%02x ", cmd->cmnd[i]);
834 printk("]\n");
835 }
836
837 if (esp->rev == FASHME)
838 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
839 esp->ops->send_dma_cmd(esp, esp->command_block_dma,
840 val, 16, 0, start_cmd);
841}
842
843static struct esp_cmd_entry *esp_get_ent(struct esp *esp)
844{
845 struct list_head *head = &esp->esp_cmd_pool;
846 struct esp_cmd_entry *ret;
847
848 if (list_empty(head)) {
849 ret = kzalloc(sizeof(struct esp_cmd_entry), GFP_ATOMIC);
850 } else {
851 ret = list_entry(head->next, struct esp_cmd_entry, list);
852 list_del(&ret->list);
853 memset(ret, 0, sizeof(*ret));
854 }
855 return ret;
856}
857
858static void esp_put_ent(struct esp *esp, struct esp_cmd_entry *ent)
859{
860 list_add(&ent->list, &esp->esp_cmd_pool);
861}
862
863static void esp_cmd_is_done(struct esp *esp, struct esp_cmd_entry *ent,
864 struct scsi_cmnd *cmd, unsigned int result)
865{
866 struct scsi_device *dev = cmd->device;
867 int tgt = dev->id;
868 int lun = dev->lun;
869
870 esp->active_cmd = NULL;
871 esp_unmap_dma(esp, cmd);
872 esp_free_lun_tag(ent, dev->hostdata);
873 cmd->result = result;
874
875 if (ent->eh_done) {
876 complete(ent->eh_done);
877 ent->eh_done = NULL;
878 }
879
880 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
881 esp->ops->unmap_single(esp, ent->sense_dma,
882 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
883 ent->sense_ptr = NULL;
884
885 /* Restore the message/status bytes to what we actually
886 * saw originally. Also, report that we are providing
887 * the sense data.
888 */
889 cmd->result = ((DRIVER_SENSE << 24) |
890 (DID_OK << 16) |
891 (COMMAND_COMPLETE << 8) |
892 (SAM_STAT_CHECK_CONDITION << 0));
893
894 ent->flags &= ~ESP_CMD_FLAG_AUTOSENSE;
895 if (esp_debug & ESP_DEBUG_AUTOSENSE) {
896 int i;
897
898 printk("esp%d: tgt[%d] lun[%d] AUTO SENSE[ ",
899 esp->host->unique_id, tgt, lun);
900 for (i = 0; i < 18; i++)
901 printk("%02x ", cmd->sense_buffer[i]);
902 printk("]\n");
903 }
904 }
905
906 cmd->scsi_done(cmd);
907
908 list_del(&ent->list);
909 esp_put_ent(esp, ent);
910
911 esp_maybe_execute_command(esp);
912}
913
914static unsigned int compose_result(unsigned int status, unsigned int message,
915 unsigned int driver_code)
916{
917 return (status | (message << 8) | (driver_code << 16));
918}
919
920static void esp_event_queue_full(struct esp *esp, struct esp_cmd_entry *ent)
921{
922 struct scsi_device *dev = ent->cmd->device;
923 struct esp_lun_data *lp = dev->hostdata;
924
925 scsi_track_queue_full(dev, lp->num_tagged - 1);
926}
927
f281233d 928static int esp_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
cd9ad58d
DM		 929{
930 struct scsi_device *dev = cmd->device;
2b14ec78 931 struct esp *esp = shost_priv(dev->host);
cd9ad58d
DM		 932 struct esp_cmd_priv *spriv;
933 struct esp_cmd_entry *ent;
934
935 ent = esp_get_ent(esp);
936 if (!ent)
937 return SCSI_MLQUEUE_HOST_BUSY;
938
939 ent->cmd = cmd;
940
941 cmd->scsi_done = done;
942
943 spriv = ESP_CMD_PRIV(cmd);
944 spriv->u.dma_addr = ~(dma_addr_t)0x0;
945
946 list_add_tail(&ent->list, &esp->queued_cmds);
947
948 esp_maybe_execute_command(esp);
949
950 return 0;
951}
952
f281233d
JG		 953static DEF_SCSI_QCMD(esp_queuecommand)
954
cd9ad58d
DM		 955static int esp_check_gross_error(struct esp *esp)
956{
957 if (esp->sreg & ESP_STAT_SPAM) {
958 /* Gross Error, could be one of:
959 * - top of fifo overwritten
960 * - top of command register overwritten
961 * - DMA programmed with wrong direction
962 * - improper phase change
963 */
a1a75b35
HR		 964 shost_printk(KERN_ERR, esp->host,
965 "Gross error sreg[%02x]\n", esp->sreg);
cd9ad58d
DM		 966 /* XXX Reset the chip. XXX */
967 return 1;
968 }
969 return 0;
970}
971
972static int esp_check_spur_intr(struct esp *esp)
973{
974 switch (esp->rev) {
975 case ESP100:
976 case ESP100A:
977 /* The interrupt pending bit of the status register cannot
978 * be trusted on these revisions.
979 */
980 esp->sreg &= ~ESP_STAT_INTR;
981 break;
982
983 default:
984 if (!(esp->sreg & ESP_STAT_INTR)) {
cd9ad58d
DM		 985 if (esp->ireg & ESP_INTR_SR)
986 return 1;
987
988 /* If the DMA is indicating interrupt pending and the
989 * ESP is not, the only possibility is a DMA error.
990 */
991 if (!esp->ops->dma_error(esp)) {
a1a75b35
HR		 992 shost_printk(KERN_ERR, esp->host,
993 "Spurious irq, sreg=%02x.\n",
994 esp->sreg);
cd9ad58d
DM		 995 return -1;
996 }
997
a1a75b35 998 shost_printk(KERN_ERR, esp->host, "DMA error\n");
cd9ad58d
DM		 999
1000 /* XXX Reset the chip. XXX */
1001 return -1;
1002 }
1003 break;
1004 }
1005
1006 return 0;
1007}
1008
1009static void esp_schedule_reset(struct esp *esp)
1010{
a1a75b35 1011 esp_log_reset("esp_schedule_reset() from %pf\n",
cd9ad58d
DM		 1012 __builtin_return_address(0));
1013 esp->flags |= ESP_FLAG_RESETTING;
1014 esp_event(esp, ESP_EVENT_RESET);
1015}
1016
1017/* In order to avoid having to add a special half-reconnected state
1018 * into the driver we just sit here and poll through the rest of
1019 * the reselection process to get the tag message bytes.
1020 */
1021static struct esp_cmd_entry *esp_reconnect_with_tag(struct esp *esp,
1022 struct esp_lun_data *lp)
1023{
1024 struct esp_cmd_entry *ent;
1025 int i;
1026
1027 if (!lp->num_tagged) {
a1a75b35
HR		 1028 shost_printk(KERN_ERR, esp->host,
1029 "Reconnect w/num_tagged==0\n");
cd9ad58d
DM		 1030 return NULL;
1031 }
1032
a1a75b35 1033 esp_log_reconnect("reconnect tag, ");
cd9ad58d
DM		 1034
1035 for (i = 0; i < ESP_QUICKIRQ_LIMIT; i++) {
1036 if (esp->ops->irq_pending(esp))
1037 break;
1038 }
1039 if (i == ESP_QUICKIRQ_LIMIT) {
a1a75b35
HR		 1040 shost_printk(KERN_ERR, esp->host,
1041 "Reconnect IRQ1 timeout\n");
cd9ad58d
DM		 1042 return NULL;
1043 }
1044
1045 esp->sreg = esp_read8(ESP_STATUS);
1046 esp->ireg = esp_read8(ESP_INTRPT);
1047
1048 esp_log_reconnect("IRQ(%d:%x:%x), ",
1049 i, esp->ireg, esp->sreg);
1050
1051 if (esp->ireg & ESP_INTR_DC) {
a1a75b35
HR		 1052 shost_printk(KERN_ERR, esp->host,
1053 "Reconnect, got disconnect.\n");
cd9ad58d
DM		 1054 return NULL;
1055 }
1056
1057 if ((esp->sreg & ESP_STAT_PMASK) != ESP_MIP) {
a1a75b35
HR		 1058 shost_printk(KERN_ERR, esp->host,
1059 "Reconnect, not MIP sreg[%02x].\n", esp->sreg);
cd9ad58d
DM		 1060 return NULL;
1061 }
1062
1063 /* DMA in the tag bytes... */
1064 esp->command_block[0] = 0xff;
1065 esp->command_block[1] = 0xff;
1066 esp->ops->send_dma_cmd(esp, esp->command_block_dma,
1067 2, 2, 1, ESP_CMD_DMA | ESP_CMD_TI);
1068
70f23fd6 1069 /* ACK the message. */
cd9ad58d
DM		 1070 scsi_esp_cmd(esp, ESP_CMD_MOK);
1071
1072 for (i = 0; i < ESP_RESELECT_TAG_LIMIT; i++) {
1073 if (esp->ops->irq_pending(esp)) {
1074 esp->sreg = esp_read8(ESP_STATUS);
1075 esp->ireg = esp_read8(ESP_INTRPT);
1076 if (esp->ireg & ESP_INTR_FDONE)
1077 break;
1078 }
1079 udelay(1);
1080 }
1081 if (i == ESP_RESELECT_TAG_LIMIT) {
a1a75b35 1082 shost_printk(KERN_ERR, esp->host, "Reconnect IRQ2 timeout\n");
cd9ad58d
DM		 1083 return NULL;
1084 }
1085 esp->ops->dma_drain(esp);
1086 esp->ops->dma_invalidate(esp);
1087
1088 esp_log_reconnect("IRQ2(%d:%x:%x) tag[%x:%x]\n",
1089 i, esp->ireg, esp->sreg,
1090 esp->command_block[0],
1091 esp->command_block[1]);
1092
1093 if (esp->command_block[0] < SIMPLE_QUEUE_TAG ||
1094 esp->command_block[0] > ORDERED_QUEUE_TAG) {
a1a75b35
HR		 1095 shost_printk(KERN_ERR, esp->host,
1096 "Reconnect, bad tag type %02x.\n",
1097 esp->command_block[0]);
cd9ad58d
DM		 1098 return NULL;
1099 }
1100
1101 ent = lp->tagged_cmds[esp->command_block[1]];
1102 if (!ent) {
a1a75b35
HR		 1103 shost_printk(KERN_ERR, esp->host,
1104 "Reconnect, no entry for tag %02x.\n",
1105 esp->command_block[1]);
cd9ad58d
DM		 1106 return NULL;
1107 }
1108
1109 return ent;
1110}
1111
1112static int esp_reconnect(struct esp *esp)
1113{
1114 struct esp_cmd_entry *ent;
1115 struct esp_target_data *tp;
1116 struct esp_lun_data *lp;
1117 struct scsi_device *dev;
1118 int target, lun;
1119
1120 BUG_ON(esp->active_cmd);
1121 if (esp->rev == FASHME) {
1122 /* FASHME puts the target and lun numbers directly
1123 * into the fifo.
1124 */
1125 target = esp->fifo[0];
1126 lun = esp->fifo[1] & 0x7;
1127 } else {
1128 u8 bits = esp_read8(ESP_FDATA);
1129
1130 /* Older chips put the lun directly into the fifo, but
1131 * the target is given as a sample of the arbitration
1132 * lines on the bus at reselection time. So we should
1133 * see the ID of the ESP and the one reconnecting target
1134 * set in the bitmap.
1135 */
1136 if (!(bits & esp->scsi_id_mask))
1137 goto do_reset;
1138 bits &= ~esp->scsi_id_mask;
1139 if (!bits || (bits & (bits - 1)))
1140 goto do_reset;
1141
1142 target = ffs(bits) - 1;
1143 lun = (esp_read8(ESP_FDATA) & 0x7);
1144
1145 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1146 if (esp->rev == ESP100) {
1147 u8 ireg = esp_read8(ESP_INTRPT);
1148 /* This chip has a bug during reselection that can
1149 * cause a spurious illegal-command interrupt, which
1150 * we simply ACK here. Another possibility is a bus
1151 * reset so we must check for that.
1152 */
1153 if (ireg & ESP_INTR_SR)
1154 goto do_reset;
1155 }
1156 scsi_esp_cmd(esp, ESP_CMD_NULL);
1157 }
1158
1159 esp_write_tgt_sync(esp, target);
1160 esp_write_tgt_config3(esp, target);
1161
1162 scsi_esp_cmd(esp, ESP_CMD_MOK);
1163
1164 if (esp->rev == FASHME)
1165 esp_write8(target | ESP_BUSID_RESELID | ESP_BUSID_CTR32BIT,
1166 ESP_BUSID);
1167
1168 tp = &esp->target[target];
1169 dev = __scsi_device_lookup_by_target(tp->starget, lun);
1170 if (!dev) {
a1a75b35
HR		 1171 shost_printk(KERN_ERR, esp->host,
1172 "Reconnect, no lp tgt[%u] lun[%u]\n",
1173 target, lun);
cd9ad58d
DM		 1174 goto do_reset;
1175 }
1176 lp = dev->hostdata;
1177
1178 ent = lp->non_tagged_cmd;
1179 if (!ent) {
1180 ent = esp_reconnect_with_tag(esp, lp);
1181 if (!ent)
1182 goto do_reset;
1183 }
1184
1185 esp->active_cmd = ent;
1186
1187 if (ent->flags & ESP_CMD_FLAG_ABORT) {
1188 esp->msg_out[0] = ABORT_TASK_SET;
1189 esp->msg_out_len = 1;
1190 scsi_esp_cmd(esp, ESP_CMD_SATN);
1191 }
1192
1193 esp_event(esp, ESP_EVENT_CHECK_PHASE);
1194 esp_restore_pointers(esp, ent);
1195 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1196 return 1;
1197
1198do_reset:
1199 esp_schedule_reset(esp);
1200 return 0;
1201}
1202
1203static int esp_finish_select(struct esp *esp)
1204{
1205 struct esp_cmd_entry *ent;
1206 struct scsi_cmnd *cmd;
1207 u8 orig_select_state;
1208
1209 orig_select_state = esp->select_state;
1210
1211 /* No longer selecting. */
1212 esp->select_state = ESP_SELECT_NONE;
1213
1214 esp->seqreg = esp_read8(ESP_SSTEP) & ESP_STEP_VBITS;
1215 ent = esp->active_cmd;
1216 cmd = ent->cmd;
1217
1218 if (esp->ops->dma_error(esp)) {
1219 /* If we see a DMA error during or as a result of selection,
1220 * all bets are off.
1221 */
1222 esp_schedule_reset(esp);
1223 esp_cmd_is_done(esp, ent, cmd, (DID_ERROR << 16));
1224 return 0;
1225 }
1226
1227 esp->ops->dma_invalidate(esp);
1228
1229 if (esp->ireg == (ESP_INTR_RSEL | ESP_INTR_FDONE)) {
1230 struct esp_target_data *tp = &esp->target[cmd->device->id];
1231
1232 /* Carefully back out of the selection attempt. Release
1233 * resources (such as DMA mapping & TAG) and reset state (such
1234 * as message out and command delivery variables).
1235 */
1236 if (!(ent->flags & ESP_CMD_FLAG_AUTOSENSE)) {
1237 esp_unmap_dma(esp, cmd);
1238 esp_free_lun_tag(ent, cmd->device->hostdata);
1239 tp->flags &= ~(ESP_TGT_NEGO_SYNC | ESP_TGT_NEGO_WIDE);
1240 esp->flags &= ~ESP_FLAG_DOING_SLOWCMD;
1241 esp->cmd_bytes_ptr = NULL;
1242 esp->cmd_bytes_left = 0;
1243 } else {
1244 esp->ops->unmap_single(esp, ent->sense_dma,
1245 SCSI_SENSE_BUFFERSIZE,
1246 DMA_FROM_DEVICE);
1247 ent->sense_ptr = NULL;
1248 }
1249
1250 /* Now that the state is unwound properly, put back onto
1251 * the issue queue. This command is no longer active.
1252 */
63ce2499 1253 list_move(&ent->list, &esp->queued_cmds);
cd9ad58d
DM		 1254 esp->active_cmd = NULL;
1255
1256 /* Return value ignored by caller, it directly invokes
1257 * esp_reconnect().
1258 */
1259 return 0;
1260 }
1261
1262 if (esp->ireg == ESP_INTR_DC) {
1263 struct scsi_device *dev = cmd->device;
1264
1265 /* Disconnect. Make sure we re-negotiate sync and
1266 * wide parameters if this target starts responding
1267 * again in the future.
1268 */
1269 esp->target[dev->id].flags |= ESP_TGT_CHECK_NEGO;
1270
1271 scsi_esp_cmd(esp, ESP_CMD_ESEL);
1272 esp_cmd_is_done(esp, ent, cmd, (DID_BAD_TARGET << 16));
1273 return 1;
1274 }
1275
1276 if (esp->ireg == (ESP_INTR_FDONE | ESP_INTR_BSERV)) {
1277 /* Selection successful. On pre-FAST chips we have
1278 * to do a NOP and possibly clean out the FIFO.
1279 */
1280 if (esp->rev <= ESP236) {
1281 int fcnt = esp_read8(ESP_FFLAGS) & ESP_FF_FBYTES;
1282
1283 scsi_esp_cmd(esp, ESP_CMD_NULL);
1284
1285 if (!fcnt &&
1286 (!esp->prev_soff ||
1287 ((esp->sreg & ESP_STAT_PMASK) != ESP_DIP)))
1288 esp_flush_fifo(esp);
1289 }
1290
1291 /* If we are doing a slow command, negotiation, etc.
1292 * we'll do the right thing as we transition to the
1293 * next phase.
1294 */
1295 esp_event(esp, ESP_EVENT_CHECK_PHASE);
1296 return 0;
1297 }
1298
a1a75b35
HR		 1299 shost_printk(KERN_INFO, esp->host,
1300 "Unexpected selection completion ireg[%x]\n", esp->ireg);
cd9ad58d
DM		 1301 esp_schedule_reset(esp);
1302 return 0;
1303}
1304
1305static int esp_data_bytes_sent(struct esp *esp, struct esp_cmd_entry *ent,
1306 struct scsi_cmnd *cmd)
1307{
1308 int fifo_cnt, ecount, bytes_sent, flush_fifo;
1309
1310 fifo_cnt = esp_read8(ESP_FFLAGS) & ESP_FF_FBYTES;
1311 if (esp->prev_cfg3 & ESP_CONFIG3_EWIDE)
1312 fifo_cnt <<= 1;
1313
1314 ecount = 0;
1315 if (!(esp->sreg & ESP_STAT_TCNT)) {
1316 ecount = ((unsigned int)esp_read8(ESP_TCLOW) |
1317 (((unsigned int)esp_read8(ESP_TCMED)) << 8));
1318 if (esp->rev == FASHME)
1319 ecount |= ((unsigned int)esp_read8(FAS_RLO)) << 16;
1320 }
1321
1322 bytes_sent = esp->data_dma_len;
1323 bytes_sent -= ecount;
1324
1325 if (!(ent->flags & ESP_CMD_FLAG_WRITE))
1326 bytes_sent -= fifo_cnt;
1327
1328 flush_fifo = 0;
1329 if (!esp->prev_soff) {
1330 /* Synchronous data transfer, always flush fifo. */
1331 flush_fifo = 1;
1332 } else {
1333 if (esp->rev == ESP100) {
1334 u32 fflags, phase;
1335
1336 /* ESP100 has a chip bug where in the synchronous data
1337 * phase it can mistake a final long REQ pulse from the
1338 * target as an extra data byte. Fun.
1339 *
1340 * To detect this case we resample the status register
1341 * and fifo flags. If we're still in a data phase and
1342 * we see spurious chunks in the fifo, we return error
1343 * to the caller which should reset and set things up
1344 * such that we only try future transfers to this
1345 * target in synchronous mode.
1346 */
1347 esp->sreg = esp_read8(ESP_STATUS);
1348 phase = esp->sreg & ESP_STAT_PMASK;
1349 fflags = esp_read8(ESP_FFLAGS);
1350
1351 if ((phase == ESP_DOP &&
1352 (fflags & ESP_FF_ONOTZERO)) ||
1353 (phase == ESP_DIP &&
1354 (fflags & ESP_FF_FBYTES)))
1355 return -1;
1356 }
1357 if (!(ent->flags & ESP_CMD_FLAG_WRITE))
1358 flush_fifo = 1;
1359 }
1360
1361 if (flush_fifo)
1362 esp_flush_fifo(esp);
1363
1364 return bytes_sent;
1365}
1366
1367static void esp_setsync(struct esp *esp, struct esp_target_data *tp,
1368 u8 scsi_period, u8 scsi_offset,
1369 u8 esp_stp, u8 esp_soff)
1370{
1371 spi_period(tp->starget) = scsi_period;
1372 spi_offset(tp->starget) = scsi_offset;
1373 spi_width(tp->starget) = (tp->flags & ESP_TGT_WIDE) ? 1 : 0;
1374
1375 if (esp_soff) {
1376 esp_stp &= 0x1f;
1377 esp_soff |= esp->radelay;
1378 if (esp->rev >= FAS236) {
1379 u8 bit = ESP_CONFIG3_FSCSI;
1380 if (esp->rev >= FAS100A)
1381 bit = ESP_CONFIG3_FAST;
1382
1383 if (scsi_period < 50) {
1384 if (esp->rev == FASHME)
1385 esp_soff &= ~esp->radelay;
1386 tp->esp_config3 |= bit;
1387 } else {
1388 tp->esp_config3 &= ~bit;
1389 }
1390 esp->prev_cfg3 = tp->esp_config3;
1391 esp_write8(esp->prev_cfg3, ESP_CFG3);
1392 }
1393 }
1394
1395 tp->esp_period = esp->prev_stp = esp_stp;
1396 tp->esp_offset = esp->prev_soff = esp_soff;
1397
1398 esp_write8(esp_soff, ESP_SOFF);
1399 esp_write8(esp_stp, ESP_STP);
1400
1401 tp->flags &= ~(ESP_TGT_NEGO_SYNC | ESP_TGT_CHECK_NEGO);
1402
1403 spi_display_xfer_agreement(tp->starget);
1404}
1405
1406static void esp_msgin_reject(struct esp *esp)
1407{
1408 struct esp_cmd_entry *ent = esp->active_cmd;
1409 struct scsi_cmnd *cmd = ent->cmd;
1410 struct esp_target_data *tp;
1411 int tgt;
1412
1413 tgt = cmd->device->id;
1414 tp = &esp->target[tgt];
1415
1416 if (tp->flags & ESP_TGT_NEGO_WIDE) {
1417 tp->flags &= ~(ESP_TGT_NEGO_WIDE | ESP_TGT_WIDE);
1418
1419 if (!esp_need_to_nego_sync(tp)) {
1420 tp->flags &= ~ESP_TGT_CHECK_NEGO;
1421 scsi_esp_cmd(esp, ESP_CMD_RATN);
1422 } else {
1423 esp->msg_out_len =
1424 spi_populate_sync_msg(&esp->msg_out[0],
1425 tp->nego_goal_period,
1426 tp->nego_goal_offset);
1427 tp->flags |= ESP_TGT_NEGO_SYNC;
1428 scsi_esp_cmd(esp, ESP_CMD_SATN);
1429 }
1430 return;
1431 }
1432
1433 if (tp->flags & ESP_TGT_NEGO_SYNC) {
1434 tp->flags &= ~(ESP_TGT_NEGO_SYNC | ESP_TGT_CHECK_NEGO);
1435 tp->esp_period = 0;
1436 tp->esp_offset = 0;
1437 esp_setsync(esp, tp, 0, 0, 0, 0);
1438 scsi_esp_cmd(esp, ESP_CMD_RATN);
1439 return;
1440 }
1441
1442 esp->msg_out[0] = ABORT_TASK_SET;
1443 esp->msg_out_len = 1;
1444 scsi_esp_cmd(esp, ESP_CMD_SATN);
1445}
1446
1447static void esp_msgin_sdtr(struct esp *esp, struct esp_target_data *tp)
1448{
1449 u8 period = esp->msg_in[3];
1450 u8 offset = esp->msg_in[4];
1451 u8 stp;
1452
1453 if (!(tp->flags & ESP_TGT_NEGO_SYNC))
1454 goto do_reject;
1455
1456 if (offset > 15)
1457 goto do_reject;
1458
1459 if (offset) {
237abac6 1460 int one_clock;
cd9ad58d
DM		 1461
1462 if (period > esp->max_period) {
1463 period = offset = 0;
1464 goto do_sdtr;
1465 }
1466 if (period < esp->min_period)
1467 goto do_reject;
1468
1469 one_clock = esp->ccycle / 1000;
237abac6 1470 stp = DIV_ROUND_UP(period << 2, one_clock);
cd9ad58d
DM		 1471 if (stp && esp->rev >= FAS236) {
1472 if (stp >= 50)
1473 stp--;
1474 }
1475 } else {
1476 stp = 0;
1477 }
1478
1479 esp_setsync(esp, tp, period, offset, stp, offset);
1480 return;
1481
1482do_reject:
1483 esp->msg_out[0] = MESSAGE_REJECT;
1484 esp->msg_out_len = 1;
1485 scsi_esp_cmd(esp, ESP_CMD_SATN);
1486 return;
1487
1488do_sdtr:
1489 tp->nego_goal_period = period;
1490 tp->nego_goal_offset = offset;
1491 esp->msg_out_len =
1492 spi_populate_sync_msg(&esp->msg_out[0],
1493 tp->nego_goal_period,
1494 tp->nego_goal_offset);
1495 scsi_esp_cmd(esp, ESP_CMD_SATN);
1496}
1497
1498static void esp_msgin_wdtr(struct esp *esp, struct esp_target_data *tp)
1499{
1500 int size = 8 << esp->msg_in[3];
1501 u8 cfg3;
1502
1503 if (esp->rev != FASHME)
1504 goto do_reject;
1505
1506 if (size != 8 && size != 16)
1507 goto do_reject;
1508
1509 if (!(tp->flags & ESP_TGT_NEGO_WIDE))
1510 goto do_reject;
1511
1512 cfg3 = tp->esp_config3;
1513 if (size == 16) {
1514 tp->flags |= ESP_TGT_WIDE;
1515 cfg3 |= ESP_CONFIG3_EWIDE;
1516 } else {
1517 tp->flags &= ~ESP_TGT_WIDE;
1518 cfg3 &= ~ESP_CONFIG3_EWIDE;
1519 }
1520 tp->esp_config3 = cfg3;
1521 esp->prev_cfg3 = cfg3;
1522 esp_write8(cfg3, ESP_CFG3);
1523
1524 tp->flags &= ~ESP_TGT_NEGO_WIDE;
1525
1526 spi_period(tp->starget) = 0;
1527 spi_offset(tp->starget) = 0;
1528 if (!esp_need_to_nego_sync(tp)) {
1529 tp->flags &= ~ESP_TGT_CHECK_NEGO;
1530 scsi_esp_cmd(esp, ESP_CMD_RATN);
1531 } else {
1532 esp->msg_out_len =
1533 spi_populate_sync_msg(&esp->msg_out[0],
1534 tp->nego_goal_period,
1535 tp->nego_goal_offset);
1536 tp->flags |= ESP_TGT_NEGO_SYNC;
1537 scsi_esp_cmd(esp, ESP_CMD_SATN);
1538 }
1539 return;
1540
1541do_reject:
1542 esp->msg_out[0] = MESSAGE_REJECT;
1543 esp->msg_out_len = 1;
1544 scsi_esp_cmd(esp, ESP_CMD_SATN);
1545}
1546
1547static void esp_msgin_extended(struct esp *esp)
1548{
1549 struct esp_cmd_entry *ent = esp->active_cmd;
1550 struct scsi_cmnd *cmd = ent->cmd;
1551 struct esp_target_data *tp;
1552 int tgt = cmd->device->id;
1553
1554 tp = &esp->target[tgt];
1555 if (esp->msg_in[2] == EXTENDED_SDTR) {
1556 esp_msgin_sdtr(esp, tp);
1557 return;
1558 }
1559 if (esp->msg_in[2] == EXTENDED_WDTR) {
1560 esp_msgin_wdtr(esp, tp);
1561 return;
1562 }
1563
a1a75b35
HR		 1564 shost_printk(KERN_INFO, esp->host,
1565 "Unexpected extended msg type %x\n", esp->msg_in[2]);
cd9ad58d
DM		 1566
1567 esp->msg_out[0] = ABORT_TASK_SET;
1568 esp->msg_out_len = 1;
1569 scsi_esp_cmd(esp, ESP_CMD_SATN);
1570}
1571
1572/* Analyze msgin bytes received from target so far. Return non-zero
1573 * if there are more bytes needed to complete the message.
1574 */
1575static int esp_msgin_process(struct esp *esp)
1576{
1577 u8 msg0 = esp->msg_in[0];
1578 int len = esp->msg_in_len;
1579
1580 if (msg0 & 0x80) {
1581 /* Identify */
a1a75b35
HR		 1582 shost_printk(KERN_INFO, esp->host,
1583 "Unexpected msgin identify\n");
cd9ad58d
DM		 1584 return 0;
1585 }
1586
1587 switch (msg0) {
1588 case EXTENDED_MESSAGE:
1589 if (len == 1)
1590 return 1;
1591 if (len < esp->msg_in[1] + 2)
1592 return 1;
1593 esp_msgin_extended(esp);
1594 return 0;
1595
1596 case IGNORE_WIDE_RESIDUE: {
1597 struct esp_cmd_entry *ent;
1598 struct esp_cmd_priv *spriv;
1599 if (len == 1)
1600 return 1;
1601
1602 if (esp->msg_in[1] != 1)
1603 goto do_reject;
1604
1605 ent = esp->active_cmd;
1606 spriv = ESP_CMD_PRIV(ent->cmd);
1607
1608 if (spriv->cur_residue == sg_dma_len(spriv->cur_sg)) {
1609 spriv->cur_sg--;
1610 spriv->cur_residue = 1;
1611 } else
1612 spriv->cur_residue++;
1613 spriv->tot_residue++;
1614 return 0;
1615 }
1616 case NOP:
1617 return 0;
1618 case RESTORE_POINTERS:
1619 esp_restore_pointers(esp, esp->active_cmd);
1620 return 0;
1621 case SAVE_POINTERS:
1622 esp_save_pointers(esp, esp->active_cmd);
1623 return 0;
1624
1625 case COMMAND_COMPLETE:
1626 case DISCONNECT: {
1627 struct esp_cmd_entry *ent = esp->active_cmd;
1628
1629 ent->message = msg0;
1630 esp_event(esp, ESP_EVENT_FREE_BUS);
1631 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1632 return 0;
1633 }
1634 case MESSAGE_REJECT:
1635 esp_msgin_reject(esp);
1636 return 0;
1637
1638 default:
1639 do_reject:
1640 esp->msg_out[0] = MESSAGE_REJECT;
1641 esp->msg_out_len = 1;
1642 scsi_esp_cmd(esp, ESP_CMD_SATN);
1643 return 0;
1644 }
1645}
1646
1647static int esp_process_event(struct esp *esp)
1648{
1649 int write;
1650
1651again:
1652 write = 0;
1af6f603
HR		 1653 esp_log_event("process event %d phase %x\n",
1654 esp->event, esp->sreg & ESP_STAT_PMASK);
cd9ad58d
DM		 1655 switch (esp->event) {
1656 case ESP_EVENT_CHECK_PHASE:
1657 switch (esp->sreg & ESP_STAT_PMASK) {
1658 case ESP_DOP:
1659 esp_event(esp, ESP_EVENT_DATA_OUT);
1660 break;
1661 case ESP_DIP:
1662 esp_event(esp, ESP_EVENT_DATA_IN);
1663 break;
1664 case ESP_STATP:
1665 esp_flush_fifo(esp);
1666 scsi_esp_cmd(esp, ESP_CMD_ICCSEQ);
1667 esp_event(esp, ESP_EVENT_STATUS);
1668 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1669 return 1;
1670
1671 case ESP_MOP:
1672 esp_event(esp, ESP_EVENT_MSGOUT);
1673 break;
1674
1675 case ESP_MIP:
1676 esp_event(esp, ESP_EVENT_MSGIN);
1677 break;
1678
1679 case ESP_CMDP:
1680 esp_event(esp, ESP_EVENT_CMD_START);
1681 break;
1682
1683 default:
a1a75b35
HR		 1684 shost_printk(KERN_INFO, esp->host,
1685 "Unexpected phase, sreg=%02x\n",
1686 esp->sreg);
cd9ad58d
DM		 1687 esp_schedule_reset(esp);
1688 return 0;
1689 }
1690 goto again;
1691 break;
1692
1693 case ESP_EVENT_DATA_IN:
1694 write = 1;
1695 /* fallthru */
1696
1697 case ESP_EVENT_DATA_OUT: {
1698 struct esp_cmd_entry *ent = esp->active_cmd;
1699 struct scsi_cmnd *cmd = ent->cmd;
1700 dma_addr_t dma_addr = esp_cur_dma_addr(ent, cmd);
1701 unsigned int dma_len = esp_cur_dma_len(ent, cmd);
1702
1703 if (esp->rev == ESP100)
1704 scsi_esp_cmd(esp, ESP_CMD_NULL);
1705
1706 if (write)
1707 ent->flags |= ESP_CMD_FLAG_WRITE;
1708 else
1709 ent->flags &= ~ESP_CMD_FLAG_WRITE;
1710
6fe07aaf
FT		 1711 if (esp->ops->dma_length_limit)
1712 dma_len = esp->ops->dma_length_limit(esp, dma_addr,
1713 dma_len);
1714 else
1715 dma_len = esp_dma_length_limit(esp, dma_addr, dma_len);
1716
cd9ad58d
DM		 1717 esp->data_dma_len = dma_len;
1718
1719 if (!dma_len) {
a1a75b35
HR		 1720 shost_printk(KERN_ERR, esp->host,
1721 "DMA length is zero!\n");
1722 shost_printk(KERN_ERR, esp->host,
1723 "cur adr[%08llx] len[%08x]\n",
1724 (unsigned long long)esp_cur_dma_addr(ent, cmd),
1725 esp_cur_dma_len(ent, cmd));
cd9ad58d
DM		 1726 esp_schedule_reset(esp);
1727 return 0;
1728 }
1729
a1a75b35 1730 esp_log_datastart("start data addr[%08llx] len[%u] write(%d)\n",
e1f2a094 1731 (unsigned long long)dma_addr, dma_len, write);
cd9ad58d
DM		 1732
1733 esp->ops->send_dma_cmd(esp, dma_addr, dma_len, dma_len,
1734 write, ESP_CMD_DMA | ESP_CMD_TI);
1735 esp_event(esp, ESP_EVENT_DATA_DONE);
1736 break;
1737 }
1738 case ESP_EVENT_DATA_DONE: {
1739 struct esp_cmd_entry *ent = esp->active_cmd;
1740 struct scsi_cmnd *cmd = ent->cmd;
1741 int bytes_sent;
1742
1743 if (esp->ops->dma_error(esp)) {
a1a75b35
HR		 1744 shost_printk(KERN_INFO, esp->host,
1745 "data done, DMA error, resetting\n");
cd9ad58d
DM		 1746 esp_schedule_reset(esp);
1747 return 0;
1748 }
1749
1750 if (ent->flags & ESP_CMD_FLAG_WRITE) {
1751 /* XXX parity errors, etc. XXX */
1752
1753 esp->ops->dma_drain(esp);
1754 }
1755 esp->ops->dma_invalidate(esp);
1756
1757 if (esp->ireg != ESP_INTR_BSERV) {
1758 /* We should always see exactly a bus-service
1759 * interrupt at the end of a successful transfer.
1760 */
a1a75b35
HR		 1761 shost_printk(KERN_INFO, esp->host,
1762 "data done, not BSERV, resetting\n");
cd9ad58d
DM		 1763 esp_schedule_reset(esp);
1764 return 0;
1765 }
1766
1767 bytes_sent = esp_data_bytes_sent(esp, ent, cmd);
1768
a1a75b35 1769 esp_log_datadone("data done flgs[%x] sent[%d]\n",
cd9ad58d
DM		 1770 ent->flags, bytes_sent);
1771
1772 if (bytes_sent < 0) {
1773 /* XXX force sync mode for this target XXX */
1774 esp_schedule_reset(esp);
1775 return 0;
1776 }
1777
1778 esp_advance_dma(esp, ent, cmd, bytes_sent);
1779 esp_event(esp, ESP_EVENT_CHECK_PHASE);
1780 goto again;
cd9ad58d
DM		 1781 }
1782
1783 case ESP_EVENT_STATUS: {
1784 struct esp_cmd_entry *ent = esp->active_cmd;
1785
1786 if (esp->ireg & ESP_INTR_FDONE) {
1787 ent->status = esp_read8(ESP_FDATA);
1788 ent->message = esp_read8(ESP_FDATA);
1789 scsi_esp_cmd(esp, ESP_CMD_MOK);
1790 } else if (esp->ireg == ESP_INTR_BSERV) {
1791 ent->status = esp_read8(ESP_FDATA);
1792 ent->message = 0xff;
1793 esp_event(esp, ESP_EVENT_MSGIN);
1794 return 0;
1795 }
1796
1797 if (ent->message != COMMAND_COMPLETE) {
a1a75b35
HR		 1798 shost_printk(KERN_INFO, esp->host,
1799 "Unexpected message %x in status\n",
1800 ent->message);
cd9ad58d
DM		 1801 esp_schedule_reset(esp);
1802 return 0;
1803 }
1804
1805 esp_event(esp, ESP_EVENT_FREE_BUS);
1806 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1807 break;
1808 }
1809 case ESP_EVENT_FREE_BUS: {
1810 struct esp_cmd_entry *ent = esp->active_cmd;
1811 struct scsi_cmnd *cmd = ent->cmd;
1812
1813 if (ent->message == COMMAND_COMPLETE ||
1814 ent->message == DISCONNECT)
1815 scsi_esp_cmd(esp, ESP_CMD_ESEL);
1816
1817 if (ent->message == COMMAND_COMPLETE) {
a1a75b35 1818 esp_log_cmddone("Command done status[%x] message[%x]\n",
cd9ad58d
DM		 1819 ent->status, ent->message);
1820 if (ent->status == SAM_STAT_TASK_SET_FULL)
1821 esp_event_queue_full(esp, ent);
1822
1823 if (ent->status == SAM_STAT_CHECK_CONDITION &&
1824 !(ent->flags & ESP_CMD_FLAG_AUTOSENSE)) {
1825 ent->flags |= ESP_CMD_FLAG_AUTOSENSE;
1826 esp_autosense(esp, ent);
1827 } else {
1828 esp_cmd_is_done(esp, ent, cmd,
1829 compose_result(ent->status,
1830 ent->message,
1831 DID_OK));
1832 }
1833 } else if (ent->message == DISCONNECT) {
a1a75b35 1834 esp_log_disconnect("Disconnecting tgt[%d] tag[%x:%x]\n",
cd9ad58d
DM		 1835 cmd->device->id,
1836 ent->tag[0], ent->tag[1]);
1837
1838 esp->active_cmd = NULL;
1839 esp_maybe_execute_command(esp);
1840 } else {
a1a75b35
HR		 1841 shost_printk(KERN_INFO, esp->host,
1842 "Unexpected message %x in freebus\n",
1843 ent->message);
cd9ad58d
DM		 1844 esp_schedule_reset(esp);
1845 return 0;
1846 }
1847 if (esp->active_cmd)
1848 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1849 break;
1850 }
1851 case ESP_EVENT_MSGOUT: {
1852 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1853
1854 if (esp_debug & ESP_DEBUG_MSGOUT) {
1855 int i;
1856 printk("ESP: Sending message [ ");
1857 for (i = 0; i < esp->msg_out_len; i++)
1858 printk("%02x ", esp->msg_out[i]);
1859 printk("]\n");
1860 }
1861
1862 if (esp->rev == FASHME) {
1863 int i;
1864
1865 /* Always use the fifo. */
1866 for (i = 0; i < esp->msg_out_len; i++) {
1867 esp_write8(esp->msg_out[i], ESP_FDATA);
1868 esp_write8(0, ESP_FDATA);
1869 }
1870 scsi_esp_cmd(esp, ESP_CMD_TI);
1871 } else {
1872 if (esp->msg_out_len == 1) {
1873 esp_write8(esp->msg_out[0], ESP_FDATA);
1874 scsi_esp_cmd(esp, ESP_CMD_TI);
1875 } else {
1876 /* Use DMA. */
1877 memcpy(esp->command_block,
1878 esp->msg_out,
1879 esp->msg_out_len);
1880
1881 esp->ops->send_dma_cmd(esp,
1882 esp->command_block_dma,
1883 esp->msg_out_len,
1884 esp->msg_out_len,
1885 0,
1886 ESP_CMD_DMA|ESP_CMD_TI);
1887 }
1888 }
1889 esp_event(esp, ESP_EVENT_MSGOUT_DONE);
1890 break;
1891 }
1892 case ESP_EVENT_MSGOUT_DONE:
1893 if (esp->rev == FASHME) {
1894 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1895 } else {
1896 if (esp->msg_out_len > 1)
1897 esp->ops->dma_invalidate(esp);
1898 }
1899
1900 if (!(esp->ireg & ESP_INTR_DC)) {
1901 if (esp->rev != FASHME)
1902 scsi_esp_cmd(esp, ESP_CMD_NULL);
1903 }
1904 esp_event(esp, ESP_EVENT_CHECK_PHASE);
1905 goto again;
1906 case ESP_EVENT_MSGIN:
1907 if (esp->ireg & ESP_INTR_BSERV) {
1908 if (esp->rev == FASHME) {
1909 if (!(esp_read8(ESP_STATUS2) &
1910 ESP_STAT2_FEMPTY))
1911 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1912 } else {
1913 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1914 if (esp->rev == ESP100)
1915 scsi_esp_cmd(esp, ESP_CMD_NULL);
1916 }
1917 scsi_esp_cmd(esp, ESP_CMD_TI);
1918 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1919 return 1;
1920 }
1921 if (esp->ireg & ESP_INTR_FDONE) {
1922 u8 val;
1923
1924 if (esp->rev == FASHME)
1925 val = esp->fifo[0];
1926 else
1927 val = esp_read8(ESP_FDATA);
1928 esp->msg_in[esp->msg_in_len++] = val;
1929
a1a75b35 1930 esp_log_msgin("Got msgin byte %x\n", val);
cd9ad58d
DM		 1931
1932 if (!esp_msgin_process(esp))
1933 esp->msg_in_len = 0;
1934
1935 if (esp->rev == FASHME)
1936 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1937
1938 scsi_esp_cmd(esp, ESP_CMD_MOK);
1939
1940 if (esp->event != ESP_EVENT_FREE_BUS)
1941 esp_event(esp, ESP_EVENT_CHECK_PHASE);
1942 } else {
a1a75b35
HR		 1943 shost_printk(KERN_INFO, esp->host,
1944 "MSGIN neither BSERV not FDON, resetting");
cd9ad58d
DM		 1945 esp_schedule_reset(esp);
1946 return 0;
1947 }
1948 break;
1949 case ESP_EVENT_CMD_START:
1950 memcpy(esp->command_block, esp->cmd_bytes_ptr,
1951 esp->cmd_bytes_left);
1952 if (esp->rev == FASHME)
1953 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1954 esp->ops->send_dma_cmd(esp, esp->command_block_dma,
1955 esp->cmd_bytes_left, 16, 0,
1956 ESP_CMD_DMA | ESP_CMD_TI);
1957 esp_event(esp, ESP_EVENT_CMD_DONE);
1958 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1959 break;
1960 case ESP_EVENT_CMD_DONE:
1961 esp->ops->dma_invalidate(esp);
1962 if (esp->ireg & ESP_INTR_BSERV) {
1963 esp_event(esp, ESP_EVENT_CHECK_PHASE);
1964 goto again;
1965 }
1966 esp_schedule_reset(esp);
1967 return 0;
1968 break;
1969
1970 case ESP_EVENT_RESET:
1971 scsi_esp_cmd(esp, ESP_CMD_RS);
1972 break;
1973
1974 default:
a1a75b35
HR		 1975 shost_printk(KERN_INFO, esp->host,
1976 "Unexpected event %x, resetting\n", esp->event);
cd9ad58d
DM		 1977 esp_schedule_reset(esp);
1978 return 0;
1979 break;
1980 }
1981 return 1;
1982}
1983
1984static void esp_reset_cleanup_one(struct esp *esp, struct esp_cmd_entry *ent)
1985{
1986 struct scsi_cmnd *cmd = ent->cmd;
1987
1988 esp_unmap_dma(esp, cmd);
1989 esp_free_lun_tag(ent, cmd->device->hostdata);
1990 cmd->result = DID_RESET << 16;
1991
1992 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
1993 esp->ops->unmap_single(esp, ent->sense_dma,
1994 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
1995 ent->sense_ptr = NULL;
1996 }
1997
1998 cmd->scsi_done(cmd);
1999 list_del(&ent->list);
2000 esp_put_ent(esp, ent);
2001}
2002
2003static void esp_clear_hold(struct scsi_device *dev, void *data)
2004{
2005 struct esp_lun_data *lp = dev->hostdata;
2006
2007 BUG_ON(lp->num_tagged);
2008 lp->hold = 0;
2009}
2010
2011static void esp_reset_cleanup(struct esp *esp)
2012{
2013 struct esp_cmd_entry *ent, *tmp;
2014 int i;
2015
2016 list_for_each_entry_safe(ent, tmp, &esp->queued_cmds, list) {
2017 struct scsi_cmnd *cmd = ent->cmd;
2018
2019 list_del(&ent->list);
2020 cmd->result = DID_RESET << 16;
2021 cmd->scsi_done(cmd);
2022 esp_put_ent(esp, ent);
2023 }
2024
2025 list_for_each_entry_safe(ent, tmp, &esp->active_cmds, list) {
2026 if (ent == esp->active_cmd)
2027 esp->active_cmd = NULL;
2028 esp_reset_cleanup_one(esp, ent);
2029 }
2030
2031 BUG_ON(esp->active_cmd != NULL);
2032
2033 /* Force renegotiation of sync/wide transfers. */
2034 for (i = 0; i < ESP_MAX_TARGET; i++) {
2035 struct esp_target_data *tp = &esp->target[i];
2036
2037 tp->esp_period = 0;
2038 tp->esp_offset = 0;
2039 tp->esp_config3 &= ~(ESP_CONFIG3_EWIDE |
2040 ESP_CONFIG3_FSCSI |
2041 ESP_CONFIG3_FAST);
2042 tp->flags &= ~ESP_TGT_WIDE;
2043 tp->flags |= ESP_TGT_CHECK_NEGO;
2044
2045 if (tp->starget)
522939d4
MR		 2046 __starget_for_each_device(tp->starget, NULL,
2047 esp_clear_hold);
cd9ad58d 2048 }
204abf28 2049 esp->flags &= ~ESP_FLAG_RESETTING;
cd9ad58d
DM		 2050}
2051
2052/* Runs under host->lock */
2053static void __esp_interrupt(struct esp *esp)
2054{
2055 int finish_reset, intr_done;
2056 u8 phase;
2057
9535fff3
HR		 2058 /*
2059 * Once INTRPT is read STATUS and SSTEP are cleared.
2060 */
cd9ad58d 2061 esp->sreg = esp_read8(ESP_STATUS);
9535fff3
HR		 2062 esp->seqreg = esp_read8(ESP_SSTEP);
2063 esp->ireg = esp_read8(ESP_INTRPT);
cd9ad58d
DM		 2064
2065 if (esp->flags & ESP_FLAG_RESETTING) {
2066 finish_reset = 1;
2067 } else {
2068 if (esp_check_gross_error(esp))
2069 return;
2070
2071 finish_reset = esp_check_spur_intr(esp);
2072 if (finish_reset < 0)
2073 return;
2074 }
2075
cd9ad58d
DM		 2076 if (esp->ireg & ESP_INTR_SR)
2077 finish_reset = 1;
2078
2079 if (finish_reset) {
2080 esp_reset_cleanup(esp);
2081 if (esp->eh_reset) {
2082 complete(esp->eh_reset);
2083 esp->eh_reset = NULL;
2084 }
2085 return;
2086 }
2087
2088 phase = (esp->sreg & ESP_STAT_PMASK);
2089 if (esp->rev == FASHME) {
2090 if (((phase != ESP_DIP && phase != ESP_DOP) &&
2091 esp->select_state == ESP_SELECT_NONE &&
2092 esp->event != ESP_EVENT_STATUS &&
2093 esp->event != ESP_EVENT_DATA_DONE) ||
2094 (esp->ireg & ESP_INTR_RSEL)) {
2095 esp->sreg2 = esp_read8(ESP_STATUS2);
2096 if (!(esp->sreg2 & ESP_STAT2_FEMPTY) ||
2097 (esp->sreg2 & ESP_STAT2_F1BYTE))
2098 hme_read_fifo(esp);
2099 }
2100 }
2101
a1a75b35 2102 esp_log_intr("intr sreg[%02x] seqreg[%02x] "
cd9ad58d
DM		 2103 "sreg2[%02x] ireg[%02x]\n",
2104 esp->sreg, esp->seqreg, esp->sreg2, esp->ireg);
2105
2106 intr_done = 0;
2107
2108 if (esp->ireg & (ESP_INTR_S | ESP_INTR_SATN | ESP_INTR_IC)) {
a1a75b35
HR		 2109 shost_printk(KERN_INFO, esp->host,
2110 "unexpected IREG %02x\n", esp->ireg);
cd9ad58d
DM		 2111 if (esp->ireg & ESP_INTR_IC)
2112 esp_dump_cmd_log(esp);
2113
2114 esp_schedule_reset(esp);
2115 } else {
2116 if (!(esp->ireg & ESP_INTR_RSEL)) {
2117 /* Some combination of FDONE, BSERV, DC. */
2118 if (esp->select_state != ESP_SELECT_NONE)
2119 intr_done = esp_finish_select(esp);
2120 } else if (esp->ireg & ESP_INTR_RSEL) {
2121 if (esp->active_cmd)
2122 (void) esp_finish_select(esp);
2123 intr_done = esp_reconnect(esp);
2124 }
2125 }
2126 while (!intr_done)
2127 intr_done = esp_process_event(esp);
2128}
2129
2130irqreturn_t scsi_esp_intr(int irq, void *dev_id)
2131{
2132 struct esp *esp = dev_id;
2133 unsigned long flags;
2134 irqreturn_t ret;
2135
2136 spin_lock_irqsave(esp->host->host_lock, flags);
2137 ret = IRQ_NONE;
2138 if (esp->ops->irq_pending(esp)) {
2139 ret = IRQ_HANDLED;
2140 for (;;) {
2141 int i;
2142
2143 __esp_interrupt(esp);
2144 if (!(esp->flags & ESP_FLAG_QUICKIRQ_CHECK))
2145 break;
2146 esp->flags &= ~ESP_FLAG_QUICKIRQ_CHECK;
2147
2148 for (i = 0; i < ESP_QUICKIRQ_LIMIT; i++) {
2149 if (esp->ops->irq_pending(esp))
2150 break;
2151 }
2152 if (i == ESP_QUICKIRQ_LIMIT)
2153 break;
2154 }
2155 }
2156 spin_unlock_irqrestore(esp->host->host_lock, flags);
2157
2158 return ret;
2159}
2160EXPORT_SYMBOL(scsi_esp_intr);
2161
76246808 2162static void esp_get_revision(struct esp *esp)
cd9ad58d
DM		 2163{
2164 u8 val;
2165
2166 esp->config1 = (ESP_CONFIG1_PENABLE | (esp->scsi_id & 7));
2167 esp->config2 = (ESP_CONFIG2_SCSI2ENAB | ESP_CONFIG2_REGPARITY);
2168 esp_write8(esp->config2, ESP_CFG2);
2169
2170 val = esp_read8(ESP_CFG2);
2171 val &= ~ESP_CONFIG2_MAGIC;
2172 if (val != (ESP_CONFIG2_SCSI2ENAB | ESP_CONFIG2_REGPARITY)) {
2173 /* If what we write to cfg2 does not come back, cfg2 is not
2174 * implemented, therefore this must be a plain esp100.
2175 */
2176 esp->rev = ESP100;
2177 } else {
2178 esp->config2 = 0;
2179 esp_set_all_config3(esp, 5);
2180 esp->prev_cfg3 = 5;
2181 esp_write8(esp->config2, ESP_CFG2);
2182 esp_write8(0, ESP_CFG3);
2183 esp_write8(esp->prev_cfg3, ESP_CFG3);
2184
2185 val = esp_read8(ESP_CFG3);
2186 if (val != 5) {
2187 /* The cfg2 register is implemented, however
2188 * cfg3 is not, must be esp100a.
2189 */
2190 esp->rev = ESP100A;
2191 } else {
2192 esp_set_all_config3(esp, 0);
2193 esp->prev_cfg3 = 0;
2194 esp_write8(esp->prev_cfg3, ESP_CFG3);
2195
2196 /* All of cfg{1,2,3} implemented, must be one of
2197 * the fas variants, figure out which one.
2198 */
2199 if (esp->cfact == 0 || esp->cfact > ESP_CCF_F5) {
2200 esp->rev = FAST;
2201 esp->sync_defp = SYNC_DEFP_FAST;
2202 } else {
2203 esp->rev = ESP236;
2204 }
2205 esp->config2 = 0;
2206 esp_write8(esp->config2, ESP_CFG2);
2207 }
2208 }
2209}
2210
76246808 2211static void esp_init_swstate(struct esp *esp)
cd9ad58d
DM		 2212{
2213 int i;
2214
2215 INIT_LIST_HEAD(&esp->queued_cmds);
2216 INIT_LIST_HEAD(&esp->active_cmds);
2217 INIT_LIST_HEAD(&esp->esp_cmd_pool);
2218
2219 /* Start with a clear state, domain validation (via ->slave_configure,
2220 * spi_dv_device()) will attempt to enable SYNC, WIDE, and tagged
2221 * commands.
2222 */
2223 for (i = 0 ; i < ESP_MAX_TARGET; i++) {
2224 esp->target[i].flags = 0;
2225 esp->target[i].nego_goal_period = 0;
2226 esp->target[i].nego_goal_offset = 0;
2227 esp->target[i].nego_goal_width = 0;
2228 esp->target[i].nego_goal_tags = 0;
2229 }
2230}
2231
2232/* This places the ESP into a known state at boot time. */
d679f805 2233static void esp_bootup_reset(struct esp *esp)
cd9ad58d
DM		 2234{
2235 u8 val;
2236
2237 /* Reset the DMA */
2238 esp->ops->reset_dma(esp);
2239
2240 /* Reset the ESP */
2241 esp_reset_esp(esp);
2242
2243 /* Reset the SCSI bus, but tell ESP not to generate an irq */
2244 val = esp_read8(ESP_CFG1);
2245 val |= ESP_CONFIG1_SRRDISAB;
2246 esp_write8(val, ESP_CFG1);
2247
2248 scsi_esp_cmd(esp, ESP_CMD_RS);
2249 udelay(400);
2250
2251 esp_write8(esp->config1, ESP_CFG1);
2252
2253 /* Eat any bitrot in the chip and we are done... */
2254 esp_read8(ESP_INTRPT);
2255}
2256
76246808 2257static void esp_set_clock_params(struct esp *esp)
cd9ad58d 2258{
6fe07aaf 2259 int fhz;
cd9ad58d
DM		 2260 u8 ccf;
2261
2262 /* This is getting messy but it has to be done correctly or else
2263 * you get weird behavior all over the place. We are trying to
2264 * basically figure out three pieces of information.
2265 *
2266 * a) Clock Conversion Factor
2267 *
2268 * This is a representation of the input crystal clock frequency
2269 * going into the ESP on this machine. Any operation whose timing
2270 * is longer than 400ns depends on this value being correct. For
2271 * example, you'll get blips for arbitration/selection during high
2272 * load or with multiple targets if this is not set correctly.
2273 *
2274 * b) Selection Time-Out
2275 *
2276 * The ESP isn't very bright and will arbitrate for the bus and try
2277 * to select a target forever if you let it. This value tells the
2278 * ESP when it has taken too long to negotiate and that it should
2279 * interrupt the CPU so we can see what happened. The value is
2280 * computed as follows (from NCR/Symbios chip docs).
2281 *
2282 * (Time Out Period) * (Input Clock)
2283 * STO = ----------------------------------
2284 * (8192) * (Clock Conversion Factor)
2285 *
2286 * We use a time out period of 250ms (ESP_BUS_TIMEOUT).
2287 *
2288 * c) Imperical constants for synchronous offset and transfer period
2289 * register values
2290 *
2291 * This entails the smallest and largest sync period we could ever
2292 * handle on this ESP.
2293 */
6fe07aaf 2294 fhz = esp->cfreq;
cd9ad58d 2295
6fe07aaf 2296 ccf = ((fhz / 1000000) + 4) / 5;
cd9ad58d
DM		 2297 if (ccf == 1)
2298 ccf = 2;
2299
2300 /* If we can't find anything reasonable, just assume 20MHZ.
2301 * This is the clock frequency of the older sun4c's where I've
2302 * been unable to find the clock-frequency PROM property. All
2303 * other machines provide useful values it seems.
2304 */
6fe07aaf
FT		 2305 if (fhz <= 5000000 || ccf < 1 || ccf > 8) {
2306 fhz = 20000000;
cd9ad58d
DM		 2307 ccf = 4;
2308 }
2309
2310 esp->cfact = (ccf == 8 ? 0 : ccf);
6fe07aaf
FT		 2311 esp->cfreq = fhz;
2312 esp->ccycle = ESP_HZ_TO_CYCLE(fhz);
cd9ad58d 2313 esp->ctick = ESP_TICK(ccf, esp->ccycle);
6fe07aaf 2314 esp->neg_defp = ESP_NEG_DEFP(fhz, ccf);
cd9ad58d
DM		 2315 esp->sync_defp = SYNC_DEFP_SLOW;
2316}
2317
2318static const char *esp_chip_names[] = {
2319 "ESP100",
2320 "ESP100A",
2321 "ESP236",
2322 "FAS236",
2323 "FAS100A",
2324 "FAST",
2325 "FASHME",
2326};
2327
2328static struct scsi_transport_template *esp_transport_template;
2329
76246808 2330int scsi_esp_register(struct esp *esp, struct device *dev)
cd9ad58d
DM		 2331{
2332 static int instance;
2333 int err;
2334
3707a186
HR		 2335 if (!esp->num_tags)
2336 esp->num_tags = ESP_DEFAULT_TAGS;
2337 else if (esp->num_tags >= ESP_MAX_TAG)
2338 esp->num_tags = ESP_MAX_TAG - 1;
cd9ad58d
DM		 2339 esp->host->transportt = esp_transport_template;
2340 esp->host->max_lun = ESP_MAX_LUN;
2341 esp->host->cmd_per_lun = 2;
ff4abd6c 2342 esp->host->unique_id = instance;
cd9ad58d
DM		 2343
2344 esp_set_clock_params(esp);
2345
2346 esp_get_revision(esp);
2347
2348 esp_init_swstate(esp);
2349
2350 esp_bootup_reset(esp);
2351
a1a75b35
HR		 2352 dev_printk(KERN_INFO, dev, "esp%u: regs[%1p:%1p] irq[%u]\n",
2353 esp->host->unique_id, esp->regs, esp->dma_regs,
2354 esp->host->irq);
2355 dev_printk(KERN_INFO, dev,
2356 "esp%u: is a %s, %u MHz (ccf=%u), SCSI ID %u\n",
2357 esp->host->unique_id, esp_chip_names[esp->rev],
2358 esp->cfreq / 1000000, esp->cfact, esp->scsi_id);
cd9ad58d
DM		 2359
2360 /* Let the SCSI bus reset settle. */
2361 ssleep(esp_bus_reset_settle);
2362
2363 err = scsi_add_host(esp->host, dev);
2364 if (err)
2365 return err;
2366
ff4abd6c 2367 instance++;
cd9ad58d
DM		 2368
2369 scsi_scan_host(esp->host);
2370
2371 return 0;
2372}
2373EXPORT_SYMBOL(scsi_esp_register);
2374
76246808 2375void scsi_esp_unregister(struct esp *esp)
cd9ad58d
DM		 2376{
2377 scsi_remove_host(esp->host);
2378}
2379EXPORT_SYMBOL(scsi_esp_unregister);
2380
ec5e69f6
JB		 2381static int esp_target_alloc(struct scsi_target *starget)
2382{
2383 struct esp *esp = shost_priv(dev_to_shost(&starget->dev));
2384 struct esp_target_data *tp = &esp->target[starget->id];
2385
2386 tp->starget = starget;
2387
2388 return 0;
2389}
2390
2391static void esp_target_destroy(struct scsi_target *starget)
2392{
2393 struct esp *esp = shost_priv(dev_to_shost(&starget->dev));
2394 struct esp_target_data *tp = &esp->target[starget->id];
2395
2396 tp->starget = NULL;
2397}
2398
cd9ad58d
DM		 2399static int esp_slave_alloc(struct scsi_device *dev)
2400{
2b14ec78 2401 struct esp *esp = shost_priv(dev->host);
cd9ad58d
DM		 2402 struct esp_target_data *tp = &esp->target[dev->id];
2403 struct esp_lun_data *lp;
2404
2405 lp = kzalloc(sizeof(*lp), GFP_KERNEL);
2406 if (!lp)
2407 return -ENOMEM;
2408 dev->hostdata = lp;
2409
cd9ad58d
DM		 2410 spi_min_period(tp->starget) = esp->min_period;
2411 spi_max_offset(tp->starget) = 15;
2412
2413 if (esp->flags & ESP_FLAG_WIDE_CAPABLE)
2414 spi_max_width(tp->starget) = 1;
2415 else
2416 spi_max_width(tp->starget) = 0;
2417
2418 return 0;
2419}
2420
2421static int esp_slave_configure(struct scsi_device *dev)
2422{
2b14ec78 2423 struct esp *esp = shost_priv(dev->host);
cd9ad58d 2424 struct esp_target_data *tp = &esp->target[dev->id];
cd9ad58d 2425
3707a186
HR		 2426 if (dev->tagged_supported)
2427 scsi_change_queue_depth(dev, esp->num_tags);
cd9ad58d 2428
cd9ad58d
DM		 2429 tp->flags |= ESP_TGT_DISCONNECT;
2430
2431 if (!spi_initial_dv(dev->sdev_target))
2432 spi_dv_device(dev);
2433
2434 return 0;
2435}
2436
2437static void esp_slave_destroy(struct scsi_device *dev)
2438{
2439 struct esp_lun_data *lp = dev->hostdata;
2440
2441 kfree(lp);
2442 dev->hostdata = NULL;
2443}
2444
2445static int esp_eh_abort_handler(struct scsi_cmnd *cmd)
2446{
2b14ec78 2447 struct esp *esp = shost_priv(cmd->device->host);
cd9ad58d
DM		 2448 struct esp_cmd_entry *ent, *tmp;
2449 struct completion eh_done;
2450 unsigned long flags;
2451
2452 /* XXX This helps a lot with debugging but might be a bit
2453 * XXX much for the final driver.
2454 */
2455 spin_lock_irqsave(esp->host->host_lock, flags);
a1a75b35
HR		 2456 shost_printk(KERN_ERR, esp->host, "Aborting command [%p:%02x]\n",
2457 cmd, cmd->cmnd[0]);
cd9ad58d
DM		 2458 ent = esp->active_cmd;
2459 if (ent)
a1a75b35
HR		 2460 shost_printk(KERN_ERR, esp->host,
2461 "Current command [%p:%02x]\n",
2462 ent->cmd, ent->cmd->cmnd[0]);
cd9ad58d 2463 list_for_each_entry(ent, &esp->queued_cmds, list) {
a1a75b35
HR		 2464 shost_printk(KERN_ERR, esp->host, "Queued command [%p:%02x]\n",
2465 ent->cmd, ent->cmd->cmnd[0]);
cd9ad58d
DM		 2466 }
2467 list_for_each_entry(ent, &esp->active_cmds, list) {
a1a75b35
HR		 2468 shost_printk(KERN_ERR, esp->host, " Active command [%p:%02x]\n",
2469 ent->cmd, ent->cmd->cmnd[0]);
cd9ad58d
DM		 2470 }
2471 esp_dump_cmd_log(esp);
2472 spin_unlock_irqrestore(esp->host->host_lock, flags);
2473
2474 spin_lock_irqsave(esp->host->host_lock, flags);
2475
2476 ent = NULL;
2477 list_for_each_entry(tmp, &esp->queued_cmds, list) {
2478 if (tmp->cmd == cmd) {
2479 ent = tmp;
2480 break;
2481 }
2482 }
2483
2484 if (ent) {
2485 /* Easiest case, we didn't even issue the command
2486 * yet so it is trivial to abort.
2487 */
2488 list_del(&ent->list);
2489
2490 cmd->result = DID_ABORT << 16;
2491 cmd->scsi_done(cmd);
2492
2493 esp_put_ent(esp, ent);
2494
2495 goto out_success;
2496 }
2497
2498 init_completion(&eh_done);
2499
2500 ent = esp->active_cmd;
2501 if (ent && ent->cmd == cmd) {
2502 /* Command is the currently active command on
2503 * the bus. If we already have an output message
2504 * pending, no dice.
2505 */
2506 if (esp->msg_out_len)
2507 goto out_failure;
2508
2509 /* Send out an abort, encouraging the target to
2510 * go to MSGOUT phase by asserting ATN.
2511 */
2512 esp->msg_out[0] = ABORT_TASK_SET;
2513 esp->msg_out_len = 1;
2514 ent->eh_done = &eh_done;
2515
2516 scsi_esp_cmd(esp, ESP_CMD_SATN);
2517 } else {
2518 /* The command is disconnected. This is not easy to
2519 * abort. For now we fail and let the scsi error
2520 * handling layer go try a scsi bus reset or host
2521 * reset.
2522 *
2523 * What we could do is put together a scsi command
2524 * solely for the purpose of sending an abort message
2525 * to the target. Coming up with all the code to
2526 * cook up scsi commands, special case them everywhere,
2527 * etc. is for questionable gain and it would be better
2528 * if the generic scsi error handling layer could do at
2529 * least some of that for us.
2530 *
2531 * Anyways this is an area for potential future improvement
2532 * in this driver.
2533 */
2534 goto out_failure;
2535 }
2536
2537 spin_unlock_irqrestore(esp->host->host_lock, flags);
2538
2539 if (!wait_for_completion_timeout(&eh_done, 5 * HZ)) {
2540 spin_lock_irqsave(esp->host->host_lock, flags);
2541 ent->eh_done = NULL;
2542 spin_unlock_irqrestore(esp->host->host_lock, flags);
2543
2544 return FAILED;
2545 }
2546
2547 return SUCCESS;
2548
2549out_success:
2550 spin_unlock_irqrestore(esp->host->host_lock, flags);
2551 return SUCCESS;
2552
2553out_failure:
2554 /* XXX This might be a good location to set ESP_TGT_BROKEN
2555 * XXX since we know which target/lun in particular is
2556 * XXX causing trouble.
2557 */
2558 spin_unlock_irqrestore(esp->host->host_lock, flags);
2559 return FAILED;
2560}
2561
2562static int esp_eh_bus_reset_handler(struct scsi_cmnd *cmd)
2563{
2b14ec78 2564 struct esp *esp = shost_priv(cmd->device->host);
cd9ad58d
DM		 2565 struct completion eh_reset;
2566 unsigned long flags;
2567
2568 init_completion(&eh_reset);
2569
2570 spin_lock_irqsave(esp->host->host_lock, flags);
2571
2572 esp->eh_reset = &eh_reset;
2573
2574 /* XXX This is too simple... We should add lots of
2575 * XXX checks here so that if we find that the chip is
2576 * XXX very wedged we return failure immediately so
2577 * XXX that we can perform a full chip reset.
2578 */
2579 esp->flags |= ESP_FLAG_RESETTING;
2580 scsi_esp_cmd(esp, ESP_CMD_RS);
2581
2582 spin_unlock_irqrestore(esp->host->host_lock, flags);
2583
2584 ssleep(esp_bus_reset_settle);
2585
2586 if (!wait_for_completion_timeout(&eh_reset, 5 * HZ)) {
2587 spin_lock_irqsave(esp->host->host_lock, flags);
2588 esp->eh_reset = NULL;
2589 spin_unlock_irqrestore(esp->host->host_lock, flags);
2590
2591 return FAILED;
2592 }
2593
2594 return SUCCESS;
2595}
2596
2597/* All bets are off, reset the entire device. */
2598static int esp_eh_host_reset_handler(struct scsi_cmnd *cmd)
2599{
2b14ec78 2600 struct esp *esp = shost_priv(cmd->device->host);
cd9ad58d
DM		 2601 unsigned long flags;
2602
2603 spin_lock_irqsave(esp->host->host_lock, flags);
2604 esp_bootup_reset(esp);
2605 esp_reset_cleanup(esp);
2606 spin_unlock_irqrestore(esp->host->host_lock, flags);
2607
2608 ssleep(esp_bus_reset_settle);
2609
2610 return SUCCESS;
2611}
2612
2613static const char *esp_info(struct Scsi_Host *host)
2614{
2615 return "esp";
2616}
2617
2618struct scsi_host_template scsi_esp_template = {
2619 .module = THIS_MODULE,
2620 .name = "esp",
2621 .info = esp_info,
2622 .queuecommand = esp_queuecommand,
ec5e69f6
JB		 2623 .target_alloc = esp_target_alloc,
2624 .target_destroy = esp_target_destroy,
cd9ad58d
DM		 2625 .slave_alloc = esp_slave_alloc,
2626 .slave_configure = esp_slave_configure,
2627 .slave_destroy = esp_slave_destroy,
2628 .eh_abort_handler = esp_eh_abort_handler,
2629 .eh_bus_reset_handler = esp_eh_bus_reset_handler,
2630 .eh_host_reset_handler = esp_eh_host_reset_handler,
2631 .can_queue = 7,
2632 .this_id = 7,
2633 .sg_tablesize = SG_ALL,
2634 .use_clustering = ENABLE_CLUSTERING,
2635 .max_sectors = 0xffff,
2636 .skip_settle_delay = 1,
2ecb204d 2637 .use_blk_tags = 1,
cd9ad58d
DM		 2638};
2639EXPORT_SYMBOL(scsi_esp_template);
2640
2641static void esp_get_signalling(struct Scsi_Host *host)
2642{
2b14ec78 2643 struct esp *esp = shost_priv(host);
cd9ad58d
DM		 2644 enum spi_signal_type type;
2645
2646 if (esp->flags & ESP_FLAG_DIFFERENTIAL)
2647 type = SPI_SIGNAL_HVD;
2648 else
2649 type = SPI_SIGNAL_SE;
2650
2651 spi_signalling(host) = type;
2652}
2653
2654static void esp_set_offset(struct scsi_target *target, int offset)
2655{
2656 struct Scsi_Host *host = dev_to_shost(target->dev.parent);
2b14ec78 2657 struct esp *esp = shost_priv(host);
cd9ad58d
DM		 2658 struct esp_target_data *tp = &esp->target[target->id];
2659
02507a80
FT		 2660 if (esp->flags & ESP_FLAG_DISABLE_SYNC)
2661 tp->nego_goal_offset = 0;
2662 else
2663 tp->nego_goal_offset = offset;
cd9ad58d
DM		 2664 tp->flags |= ESP_TGT_CHECK_NEGO;
2665}
2666
2667static void esp_set_period(struct scsi_target *target, int period)
2668{
2669 struct Scsi_Host *host = dev_to_shost(target->dev.parent);
2b14ec78 2670 struct esp *esp = shost_priv(host);
cd9ad58d
DM		 2671 struct esp_target_data *tp = &esp->target[target->id];
2672
2673 tp->nego_goal_period = period;
2674 tp->flags |= ESP_TGT_CHECK_NEGO;
2675}
2676
2677static void esp_set_width(struct scsi_target *target, int width)
2678{
2679 struct Scsi_Host *host = dev_to_shost(target->dev.parent);
2b14ec78 2680 struct esp *esp = shost_priv(host);
cd9ad58d
DM		 2681 struct esp_target_data *tp = &esp->target[target->id];
2682
2683 tp->nego_goal_width = (width ? 1 : 0);
2684 tp->flags |= ESP_TGT_CHECK_NEGO;
2685}
2686
2687static struct spi_function_template esp_transport_ops = {
2688 .set_offset = esp_set_offset,
2689 .show_offset = 1,
2690 .set_period = esp_set_period,
2691 .show_period = 1,
2692 .set_width = esp_set_width,
2693 .show_width = 1,
2694 .get_signalling = esp_get_signalling,
2695};
2696
2697static int __init esp_init(void)
2698{
2699 BUILD_BUG_ON(sizeof(struct scsi_pointer) <
2700 sizeof(struct esp_cmd_priv));
2701
2702 esp_transport_template = spi_attach_transport(&esp_transport_ops);
2703 if (!esp_transport_template)
2704 return -ENODEV;
2705
2706 return 0;
2707}
2708
2709static void __exit esp_exit(void)
2710{
2711 spi_release_transport(esp_transport_template);
2712}
2713
2714MODULE_DESCRIPTION("ESP SCSI driver core");
2715MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
2716MODULE_LICENSE("GPL");
2717MODULE_VERSION(DRV_VERSION);
2718
2719module_param(esp_bus_reset_settle, int, 0);
2720MODULE_PARM_DESC(esp_bus_reset_settle,
2721 "ESP scsi bus reset delay in seconds");
2722
2723module_param(esp_debug, int, 0);
2724MODULE_PARM_DESC(esp_debug,
2725"ESP bitmapped debugging message enable value:\n"
2726" 0x00000001 Log interrupt events\n"
2727" 0x00000002 Log scsi commands\n"
2728" 0x00000004 Log resets\n"
2729" 0x00000008 Log message in events\n"
2730" 0x00000010 Log message out events\n"
2731" 0x00000020 Log command completion\n"
2732" 0x00000040 Log disconnects\n"
2733" 0x00000080 Log data start\n"
2734" 0x00000100 Log data done\n"
2735" 0x00000200 Log reconnects\n"
2736" 0x00000400 Log auto-sense data\n"
2737);
2738
2739module_init(esp_init);
2740module_exit(esp_exit);
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