]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Generic Generic NCR5380 driver | |
3 | * | |
4 | * Copyright 1993, Drew Eckhardt | |
5 | * Visionary Computing | |
6 | * (Unix and Linux consulting and custom programming) | |
7 | * drew@colorado.edu | |
8 | * +1 (303) 440-4894 | |
9 | * | |
10 | * NCR53C400 extensions (c) 1994,1995,1996, Kevin Lentin | |
11 | * K.Lentin@cs.monash.edu.au | |
12 | * | |
13 | * NCR53C400A extensions (c) 1996, Ingmar Baumgart | |
14 | * ingmar@gonzo.schwaben.de | |
15 | * | |
16 | * DTC3181E extensions (c) 1997, Ronald van Cuijlenborg | |
17 | * ronald.van.cuijlenborg@tip.nl or nutty@dds.nl | |
18 | * | |
19 | * Added ISAPNP support for DTC436 adapters, | |
20 | * Thomas Sailer, sailer@ife.ee.ethz.ch | |
1da177e4 | 21 | * |
9c41ab27 | 22 | * See Documentation/scsi/g_NCR5380.txt for more info. |
1da177e4 LT |
23 | */ |
24 | ||
1da177e4 | 25 | #include <asm/io.h> |
1da177e4 | 26 | #include <linux/blkdev.h> |
161c0059 | 27 | #include <linux/module.h> |
1da177e4 LT |
28 | #include <scsi/scsi_host.h> |
29 | #include "g_NCR5380.h" | |
30 | #include "NCR5380.h" | |
1da177e4 LT |
31 | #include <linux/init.h> |
32 | #include <linux/ioport.h> | |
a8cfbcae OZ |
33 | #include <linux/isa.h> |
34 | #include <linux/pnp.h> | |
1da177e4 LT |
35 | #include <linux/interrupt.h> |
36 | ||
a8cfbcae OZ |
37 | #define MAX_CARDS 8 |
38 | ||
39 | /* old-style parameters for compatibility */ | |
c0965e63 | 40 | static int ncr_irq; |
c0965e63 FT |
41 | static int ncr_addr; |
42 | static int ncr_5380; | |
43 | static int ncr_53c400; | |
44 | static int ncr_53c400a; | |
45 | static int dtc_3181e; | |
c6084cbc | 46 | static int hp_c2502; |
a8cfbcae OZ |
47 | module_param(ncr_irq, int, 0); |
48 | module_param(ncr_addr, int, 0); | |
49 | module_param(ncr_5380, int, 0); | |
50 | module_param(ncr_53c400, int, 0); | |
51 | module_param(ncr_53c400a, int, 0); | |
52 | module_param(dtc_3181e, int, 0); | |
53 | module_param(hp_c2502, int, 0); | |
54 | ||
55 | static int irq[] = { 0, 0, 0, 0, 0, 0, 0, 0 }; | |
56 | module_param_array(irq, int, NULL, 0); | |
57 | MODULE_PARM_DESC(irq, "IRQ number(s)"); | |
1da177e4 | 58 | |
a8cfbcae OZ |
59 | static int base[] = { 0, 0, 0, 0, 0, 0, 0, 0 }; |
60 | module_param_array(base, int, NULL, 0); | |
61 | MODULE_PARM_DESC(base, "base address(es)"); | |
62 | ||
63 | static int card[] = { -1, -1, -1, -1, -1, -1, -1, -1 }; | |
64 | module_param_array(card, int, NULL, 0); | |
65 | MODULE_PARM_DESC(card, "card type (0=NCR5380, 1=NCR53C400, 2=NCR53C400A, 3=DTC3181E, 4=HP C2502)"); | |
66 | ||
67 | MODULE_LICENSE("GPL"); | |
1da177e4 | 68 | |
c6084cbc OZ |
69 | #ifndef SCSI_G_NCR5380_MEM |
70 | /* | |
71 | * Configure I/O address of 53C400A or DTC436 by writing magic numbers | |
72 | * to ports 0x779 and 0x379. | |
73 | */ | |
74 | static void magic_configure(int idx, u8 irq, u8 magic[]) | |
75 | { | |
76 | u8 cfg = 0; | |
77 | ||
78 | outb(magic[0], 0x779); | |
79 | outb(magic[1], 0x379); | |
80 | outb(magic[2], 0x379); | |
81 | outb(magic[3], 0x379); | |
82 | outb(magic[4], 0x379); | |
83 | ||
84 | /* allowed IRQs for HP C2502 */ | |
85 | if (irq != 2 && irq != 3 && irq != 4 && irq != 5 && irq != 7) | |
86 | irq = 0; | |
87 | if (idx >= 0 && idx <= 7) | |
88 | cfg = 0x80 | idx | (irq << 4); | |
89 | outb(cfg, 0x379); | |
90 | } | |
91 | #endif | |
92 | ||
a8cfbcae OZ |
93 | static int generic_NCR5380_init_one(struct scsi_host_template *tpnt, |
94 | struct device *pdev, int base, int irq, int board) | |
1da177e4 | 95 | { |
1da177e4 | 96 | unsigned int *ports; |
c6084cbc | 97 | u8 *magic = NULL; |
702a98c6 OZ |
98 | #ifndef SCSI_G_NCR5380_MEM |
99 | int i; | |
c6084cbc | 100 | int port_idx = -1; |
9d376402 | 101 | unsigned long region_size; |
702a98c6 | 102 | #endif |
a8cfbcae | 103 | static unsigned int ncr_53c400a_ports[] = { |
1da177e4 LT |
104 | 0x280, 0x290, 0x300, 0x310, 0x330, 0x340, 0x348, 0x350, 0 |
105 | }; | |
a8cfbcae | 106 | static unsigned int dtc_3181e_ports[] = { |
1da177e4 LT |
107 | 0x220, 0x240, 0x280, 0x2a0, 0x2c0, 0x300, 0x320, 0x340, 0 |
108 | }; | |
a8cfbcae | 109 | static u8 ncr_53c400a_magic[] = { /* 53C400A & DTC436 */ |
c6084cbc OZ |
110 | 0x59, 0xb9, 0xc5, 0xae, 0xa6 |
111 | }; | |
a8cfbcae | 112 | static u8 hp_c2502_magic[] = { /* HP C2502 */ |
c6084cbc OZ |
113 | 0x0f, 0x22, 0xf0, 0x20, 0x80 |
114 | }; | |
a8cfbcae | 115 | int flags, ret; |
1da177e4 | 116 | struct Scsi_Host *instance; |
12150797 | 117 | struct NCR5380_hostdata *hostdata; |
702a98c6 | 118 | #ifdef SCSI_G_NCR5380_MEM |
c818cb64 | 119 | void __iomem *iomem; |
9d376402 | 120 | resource_size_t iomem_size; |
c818cb64 | 121 | #endif |
1da177e4 | 122 | |
d91f5afe OZ |
123 | ports = NULL; |
124 | flags = 0; | |
a8cfbcae | 125 | switch (board) { |
d91f5afe OZ |
126 | case BOARD_NCR5380: |
127 | flags = FLAG_NO_PSEUDO_DMA | FLAG_DMA_FIXUP; | |
128 | break; | |
129 | case BOARD_NCR53C400A: | |
130 | ports = ncr_53c400a_ports; | |
131 | magic = ncr_53c400a_magic; | |
132 | break; | |
133 | case BOARD_HP_C2502: | |
134 | ports = ncr_53c400a_ports; | |
135 | magic = hp_c2502_magic; | |
136 | break; | |
137 | case BOARD_DTC3181E: | |
138 | ports = dtc_3181e_ports; | |
139 | magic = ncr_53c400a_magic; | |
140 | break; | |
141 | } | |
1da177e4 | 142 | |
702a98c6 | 143 | #ifndef SCSI_G_NCR5380_MEM |
d91f5afe OZ |
144 | if (ports && magic) { |
145 | /* wakeup sequence for the NCR53C400A and DTC3181E */ | |
1da177e4 | 146 | |
d91f5afe OZ |
147 | /* Disable the adapter and look for a free io port */ |
148 | magic_configure(-1, 0, magic); | |
1da177e4 | 149 | |
d91f5afe | 150 | region_size = 16; |
a8cfbcae | 151 | if (base) |
d91f5afe | 152 | for (i = 0; ports[i]; i++) { |
a8cfbcae OZ |
153 | if (base == ports[i]) { /* index found */ |
154 | if (!request_region(ports[i], | |
155 | region_size, | |
156 | "ncr53c80")) | |
157 | return -EBUSY; | |
d91f5afe | 158 | break; |
a8cfbcae OZ |
159 | } |
160 | } | |
161 | else | |
d91f5afe | 162 | for (i = 0; ports[i]; i++) { |
a8cfbcae OZ |
163 | if (!request_region(ports[i], region_size, |
164 | "ncr53c80")) | |
d91f5afe OZ |
165 | continue; |
166 | if (inb(ports[i]) == 0xff) | |
167 | break; | |
168 | release_region(ports[i], region_size); | |
169 | } | |
170 | if (ports[i]) { | |
171 | /* At this point we have our region reserved */ | |
172 | magic_configure(i, 0, magic); /* no IRQ yet */ | |
173 | outb(0xc0, ports[i] + 9); | |
a8cfbcae OZ |
174 | if (inb(ports[i] + 9) != 0x80) { |
175 | ret = -ENODEV; | |
176 | goto out_release; | |
177 | } | |
178 | base = ports[i]; | |
d91f5afe OZ |
179 | port_idx = i; |
180 | } else | |
a8cfbcae | 181 | return -EINVAL; |
d91f5afe OZ |
182 | } |
183 | else | |
184 | { | |
a8cfbcae | 185 | /* NCR5380 - no configuration, just grab */ |
d91f5afe | 186 | region_size = 8; |
a8cfbcae OZ |
187 | if (!base || !request_region(base, region_size, "ncr5380")) |
188 | return -EBUSY; | |
d91f5afe | 189 | } |
1da177e4 | 190 | #else |
d91f5afe OZ |
191 | iomem_size = NCR53C400_region_size; |
192 | if (!request_mem_region(base, iomem_size, "ncr5380")) | |
a8cfbcae | 193 | return -EBUSY; |
d91f5afe OZ |
194 | iomem = ioremap(base, iomem_size); |
195 | if (!iomem) { | |
196 | release_mem_region(base, iomem_size); | |
a8cfbcae | 197 | return -ENOMEM; |
d91f5afe | 198 | } |
1da177e4 | 199 | #endif |
a8cfbcae OZ |
200 | instance = scsi_host_alloc(tpnt, sizeof(struct NCR5380_hostdata)); |
201 | if (instance == NULL) { | |
202 | ret = -ENOMEM; | |
d91f5afe | 203 | goto out_release; |
a8cfbcae | 204 | } |
d91f5afe | 205 | hostdata = shost_priv(instance); |
1da177e4 | 206 | |
702a98c6 | 207 | #ifndef SCSI_G_NCR5380_MEM |
a8cfbcae | 208 | instance->io_port = base; |
d91f5afe OZ |
209 | instance->n_io_port = region_size; |
210 | hostdata->io_width = 1; /* 8-bit PDMA by default */ | |
4d8c08c7 | 211 | |
d91f5afe OZ |
212 | /* |
213 | * On NCR53C400 boards, NCR5380 registers are mapped 8 past | |
214 | * the base address. | |
215 | */ | |
a8cfbcae | 216 | switch (board) { |
d91f5afe OZ |
217 | case BOARD_NCR53C400: |
218 | instance->io_port += 8; | |
219 | hostdata->c400_ctl_status = 0; | |
220 | hostdata->c400_blk_cnt = 1; | |
221 | hostdata->c400_host_buf = 4; | |
222 | break; | |
223 | case BOARD_DTC3181E: | |
224 | hostdata->io_width = 2; /* 16-bit PDMA */ | |
225 | /* fall through */ | |
226 | case BOARD_NCR53C400A: | |
227 | case BOARD_HP_C2502: | |
228 | hostdata->c400_ctl_status = 9; | |
229 | hostdata->c400_blk_cnt = 10; | |
230 | hostdata->c400_host_buf = 8; | |
231 | break; | |
232 | } | |
c818cb64 | 233 | #else |
a8cfbcae | 234 | instance->base = base; |
d91f5afe OZ |
235 | hostdata->iomem = iomem; |
236 | hostdata->iomem_size = iomem_size; | |
a8cfbcae | 237 | switch (board) { |
d91f5afe OZ |
238 | case BOARD_NCR53C400: |
239 | hostdata->c400_ctl_status = 0x100; | |
240 | hostdata->c400_blk_cnt = 0x101; | |
241 | hostdata->c400_host_buf = 0x104; | |
242 | break; | |
243 | case BOARD_DTC3181E: | |
244 | case BOARD_NCR53C400A: | |
245 | case BOARD_HP_C2502: | |
246 | pr_err(DRV_MODULE_NAME ": unknown register offsets\n"); | |
a8cfbcae | 247 | ret = -EINVAL; |
d91f5afe OZ |
248 | goto out_unregister; |
249 | } | |
1da177e4 LT |
250 | #endif |
251 | ||
a8cfbcae OZ |
252 | ret = NCR5380_init(instance, flags | FLAG_LATE_DMA_SETUP); |
253 | if (ret) | |
d91f5afe | 254 | goto out_unregister; |
1da177e4 | 255 | |
a8cfbcae | 256 | switch (board) { |
d91f5afe OZ |
257 | case BOARD_NCR53C400: |
258 | case BOARD_DTC3181E: | |
259 | case BOARD_NCR53C400A: | |
260 | case BOARD_HP_C2502: | |
261 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); | |
262 | } | |
4d8c08c7 | 263 | |
d91f5afe | 264 | NCR5380_maybe_reset_bus(instance); |
b6488f97 | 265 | |
a8cfbcae OZ |
266 | if (irq != IRQ_AUTO) |
267 | instance->irq = irq; | |
d91f5afe OZ |
268 | else |
269 | instance->irq = NCR5380_probe_irq(instance, 0xffff); | |
1da177e4 | 270 | |
d91f5afe OZ |
271 | /* Compatibility with documented NCR5380 kernel parameters */ |
272 | if (instance->irq == 255) | |
273 | instance->irq = NO_IRQ; | |
22f5f10d | 274 | |
d91f5afe | 275 | if (instance->irq != NO_IRQ) { |
c6084cbc | 276 | #ifndef SCSI_G_NCR5380_MEM |
d91f5afe | 277 | /* set IRQ for HP C2502 */ |
a8cfbcae | 278 | if (board == BOARD_HP_C2502) |
d91f5afe | 279 | magic_configure(port_idx, instance->irq, magic); |
c6084cbc | 280 | #endif |
d91f5afe OZ |
281 | if (request_irq(instance->irq, generic_NCR5380_intr, |
282 | 0, "NCR5380", instance)) { | |
283 | printk(KERN_WARNING "scsi%d : IRQ%d not free, interrupts disabled\n", instance->host_no, instance->irq); | |
284 | instance->irq = NO_IRQ; | |
1da177e4 | 285 | } |
d91f5afe | 286 | } |
1da177e4 | 287 | |
d91f5afe OZ |
288 | if (instance->irq == NO_IRQ) { |
289 | printk(KERN_INFO "scsi%d : interrupts not enabled. for better interactive performance,\n", instance->host_no); | |
290 | printk(KERN_INFO "scsi%d : please jumper the board for a free IRQ.\n", instance->host_no); | |
1da177e4 | 291 | } |
d91f5afe | 292 | |
a8cfbcae OZ |
293 | ret = scsi_add_host(instance, pdev); |
294 | if (ret) | |
295 | goto out_free_irq; | |
296 | scsi_scan_host(instance); | |
297 | dev_set_drvdata(pdev, instance); | |
298 | return 0; | |
0ad0eff9 | 299 | |
a8cfbcae OZ |
300 | out_free_irq: |
301 | if (instance->irq != NO_IRQ) | |
302 | free_irq(instance->irq, instance); | |
303 | NCR5380_exit(instance); | |
0ad0eff9 | 304 | out_unregister: |
a8cfbcae | 305 | scsi_host_put(instance); |
0ad0eff9 FT |
306 | out_release: |
307 | #ifndef SCSI_G_NCR5380_MEM | |
a8cfbcae | 308 | release_region(base, region_size); |
0ad0eff9 FT |
309 | #else |
310 | iounmap(iomem); | |
9d376402 | 311 | release_mem_region(base, iomem_size); |
0ad0eff9 | 312 | #endif |
a8cfbcae | 313 | return ret; |
1da177e4 LT |
314 | } |
315 | ||
a8cfbcae | 316 | static void generic_NCR5380_release_resources(struct Scsi_Host *instance) |
1da177e4 | 317 | { |
a8cfbcae | 318 | scsi_remove_host(instance); |
22f5f10d | 319 | if (instance->irq != NO_IRQ) |
1e641664 | 320 | free_irq(instance->irq, instance); |
1da177e4 | 321 | NCR5380_exit(instance); |
702a98c6 | 322 | #ifndef SCSI_G_NCR5380_MEM |
b01ec348 | 323 | release_region(instance->io_port, instance->n_io_port); |
1da177e4 | 324 | #else |
9d376402 FT |
325 | { |
326 | struct NCR5380_hostdata *hostdata = shost_priv(instance); | |
1da177e4 | 327 | |
9d376402 FT |
328 | iounmap(hostdata->iomem); |
329 | release_mem_region(instance->base, hostdata->iomem_size); | |
330 | } | |
331 | #endif | |
a8cfbcae | 332 | scsi_host_put(instance); |
1da177e4 | 333 | } |
1da177e4 LT |
334 | |
335 | /** | |
6c4b88ca | 336 | * generic_NCR5380_pread - pseudo DMA read |
1da177e4 LT |
337 | * @instance: adapter to read from |
338 | * @dst: buffer to read into | |
339 | * @len: buffer length | |
340 | * | |
25985edc | 341 | * Perform a pseudo DMA mode read from an NCR53C400 or equivalent |
1da177e4 LT |
342 | * controller |
343 | */ | |
344 | ||
6c4b88ca FT |
345 | static inline int generic_NCR5380_pread(struct Scsi_Host *instance, |
346 | unsigned char *dst, int len) | |
1da177e4 | 347 | { |
54d8fe44 | 348 | struct NCR5380_hostdata *hostdata = shost_priv(instance); |
1da177e4 LT |
349 | int blocks = len / 128; |
350 | int start = 0; | |
1da177e4 | 351 | |
12150797 OZ |
352 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE | CSR_TRANS_DIR); |
353 | NCR5380_write(hostdata->c400_blk_cnt, blocks); | |
1da177e4 | 354 | while (1) { |
12150797 | 355 | if (NCR5380_read(hostdata->c400_blk_cnt) == 0) |
1da177e4 | 356 | break; |
12150797 | 357 | if (NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ) { |
1da177e4 LT |
358 | printk(KERN_ERR "53C400r: Got 53C80_IRQ start=%d, blocks=%d\n", start, blocks); |
359 | return -1; | |
360 | } | |
12150797 OZ |
361 | while (NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY) |
362 | ; /* FIXME - no timeout */ | |
1da177e4 | 363 | |
702a98c6 | 364 | #ifndef SCSI_G_NCR5380_MEM |
aeb51152 OZ |
365 | if (hostdata->io_width == 2) |
366 | insw(instance->io_port + hostdata->c400_host_buf, | |
367 | dst + start, 64); | |
368 | else | |
369 | insb(instance->io_port + hostdata->c400_host_buf, | |
12150797 | 370 | dst + start, 128); |
1da177e4 | 371 | #else |
702a98c6 | 372 | /* implies SCSI_G_NCR5380_MEM */ |
54d8fe44 FT |
373 | memcpy_fromio(dst + start, |
374 | hostdata->iomem + NCR53C400_host_buffer, 128); | |
1da177e4 LT |
375 | #endif |
376 | start += 128; | |
377 | blocks--; | |
378 | } | |
379 | ||
380 | if (blocks) { | |
12150797 OZ |
381 | while (NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY) |
382 | ; /* FIXME - no timeout */ | |
1da177e4 | 383 | |
702a98c6 | 384 | #ifndef SCSI_G_NCR5380_MEM |
aeb51152 OZ |
385 | if (hostdata->io_width == 2) |
386 | insw(instance->io_port + hostdata->c400_host_buf, | |
387 | dst + start, 64); | |
388 | else | |
389 | insb(instance->io_port + hostdata->c400_host_buf, | |
12150797 | 390 | dst + start, 128); |
1da177e4 | 391 | #else |
702a98c6 | 392 | /* implies SCSI_G_NCR5380_MEM */ |
54d8fe44 FT |
393 | memcpy_fromio(dst + start, |
394 | hostdata->iomem + NCR53C400_host_buffer, 128); | |
1da177e4 LT |
395 | #endif |
396 | start += 128; | |
397 | blocks--; | |
398 | } | |
399 | ||
12150797 | 400 | if (!(NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ)) |
1da177e4 LT |
401 | printk("53C400r: no 53C80 gated irq after transfer"); |
402 | ||
42fc6370 OZ |
403 | /* wait for 53C80 registers to be available */ |
404 | while (!(NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG)) | |
1da177e4 | 405 | ; |
42fc6370 | 406 | |
1da177e4 LT |
407 | if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) |
408 | printk(KERN_ERR "53C400r: no end dma signal\n"); | |
409 | ||
1da177e4 LT |
410 | return 0; |
411 | } | |
412 | ||
413 | /** | |
6c4b88ca | 414 | * generic_NCR5380_pwrite - pseudo DMA write |
1da177e4 LT |
415 | * @instance: adapter to read from |
416 | * @dst: buffer to read into | |
417 | * @len: buffer length | |
418 | * | |
25985edc | 419 | * Perform a pseudo DMA mode read from an NCR53C400 or equivalent |
1da177e4 LT |
420 | * controller |
421 | */ | |
422 | ||
6c4b88ca FT |
423 | static inline int generic_NCR5380_pwrite(struct Scsi_Host *instance, |
424 | unsigned char *src, int len) | |
1da177e4 | 425 | { |
54d8fe44 | 426 | struct NCR5380_hostdata *hostdata = shost_priv(instance); |
1da177e4 LT |
427 | int blocks = len / 128; |
428 | int start = 0; | |
1da177e4 | 429 | |
12150797 OZ |
430 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); |
431 | NCR5380_write(hostdata->c400_blk_cnt, blocks); | |
1da177e4 | 432 | while (1) { |
12150797 | 433 | if (NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ) { |
1da177e4 LT |
434 | printk(KERN_ERR "53C400w: Got 53C80_IRQ start=%d, blocks=%d\n", start, blocks); |
435 | return -1; | |
436 | } | |
437 | ||
12150797 | 438 | if (NCR5380_read(hostdata->c400_blk_cnt) == 0) |
1da177e4 | 439 | break; |
12150797 | 440 | while (NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY) |
1da177e4 | 441 | ; // FIXME - timeout |
702a98c6 | 442 | #ifndef SCSI_G_NCR5380_MEM |
aeb51152 OZ |
443 | if (hostdata->io_width == 2) |
444 | outsw(instance->io_port + hostdata->c400_host_buf, | |
445 | src + start, 64); | |
446 | else | |
447 | outsb(instance->io_port + hostdata->c400_host_buf, | |
12150797 | 448 | src + start, 128); |
1da177e4 | 449 | #else |
702a98c6 | 450 | /* implies SCSI_G_NCR5380_MEM */ |
54d8fe44 FT |
451 | memcpy_toio(hostdata->iomem + NCR53C400_host_buffer, |
452 | src + start, 128); | |
1da177e4 LT |
453 | #endif |
454 | start += 128; | |
455 | blocks--; | |
456 | } | |
457 | if (blocks) { | |
12150797 | 458 | while (NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY) |
1da177e4 LT |
459 | ; // FIXME - no timeout |
460 | ||
702a98c6 | 461 | #ifndef SCSI_G_NCR5380_MEM |
aeb51152 OZ |
462 | if (hostdata->io_width == 2) |
463 | outsw(instance->io_port + hostdata->c400_host_buf, | |
464 | src + start, 64); | |
465 | else | |
466 | outsb(instance->io_port + hostdata->c400_host_buf, | |
12150797 | 467 | src + start, 128); |
1da177e4 | 468 | #else |
702a98c6 | 469 | /* implies SCSI_G_NCR5380_MEM */ |
54d8fe44 FT |
470 | memcpy_toio(hostdata->iomem + NCR53C400_host_buffer, |
471 | src + start, 128); | |
1da177e4 LT |
472 | #endif |
473 | start += 128; | |
474 | blocks--; | |
475 | } | |
476 | ||
42fc6370 OZ |
477 | /* wait for 53C80 registers to be available */ |
478 | while (!(NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG)) { | |
aeb51152 OZ |
479 | udelay(4); /* DTC436 chip hangs without this */ |
480 | /* FIXME - no timeout */ | |
481 | } | |
1da177e4 | 482 | |
1da177e4 LT |
483 | if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) { |
484 | printk(KERN_ERR "53C400w: no end dma signal\n"); | |
485 | } | |
42fc6370 | 486 | |
1da177e4 LT |
487 | while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)) |
488 | ; // TIMEOUT | |
489 | return 0; | |
490 | } | |
ff3d4578 | 491 | |
7e9ec8d9 FT |
492 | static int generic_NCR5380_dma_xfer_len(struct Scsi_Host *instance, |
493 | struct scsi_cmnd *cmd) | |
ff3d4578 | 494 | { |
7e9ec8d9 | 495 | struct NCR5380_hostdata *hostdata = shost_priv(instance); |
ff3d4578 FT |
496 | int transfersize = cmd->transfersize; |
497 | ||
7e9ec8d9 FT |
498 | if (hostdata->flags & FLAG_NO_PSEUDO_DMA) |
499 | return 0; | |
500 | ||
ff3d4578 FT |
501 | /* Limit transfers to 32K, for xx400 & xx406 |
502 | * pseudoDMA that transfers in 128 bytes blocks. | |
503 | */ | |
504 | if (transfersize > 32 * 1024 && cmd->SCp.this_residual && | |
505 | !(cmd->SCp.this_residual % transfersize)) | |
506 | transfersize = 32 * 1024; | |
507 | ||
f0394621 OZ |
508 | /* 53C400 datasheet: non-modulo-128-byte transfers should use PIO */ |
509 | if (transfersize % 128) | |
510 | transfersize = 0; | |
511 | ||
ff3d4578 FT |
512 | return transfersize; |
513 | } | |
514 | ||
1da177e4 LT |
515 | /* |
516 | * Include the NCR5380 core code that we build our driver around | |
517 | */ | |
518 | ||
519 | #include "NCR5380.c" | |
520 | ||
d0be4a7d | 521 | static struct scsi_host_template driver_template = { |
a8cfbcae | 522 | .module = THIS_MODULE, |
aa2e2cb1 | 523 | .proc_name = DRV_MODULE_NAME, |
aa2e2cb1 | 524 | .name = "Generic NCR5380/NCR53C400 SCSI", |
aa2e2cb1 FT |
525 | .info = generic_NCR5380_info, |
526 | .queuecommand = generic_NCR5380_queue_command, | |
1da177e4 LT |
527 | .eh_abort_handler = generic_NCR5380_abort, |
528 | .eh_bus_reset_handler = generic_NCR5380_bus_reset, | |
aa2e2cb1 FT |
529 | .can_queue = 16, |
530 | .this_id = 7, | |
531 | .sg_tablesize = SG_ALL, | |
532 | .cmd_per_lun = 2, | |
533 | .use_clustering = DISABLE_CLUSTERING, | |
32b26a10 | 534 | .cmd_size = NCR5380_CMD_SIZE, |
0a4e3612 | 535 | .max_sectors = 128, |
1da177e4 | 536 | }; |
161c0059 | 537 | |
1da177e4 | 538 | |
a8cfbcae OZ |
539 | static int generic_NCR5380_isa_match(struct device *pdev, unsigned int ndev) |
540 | { | |
541 | int ret = generic_NCR5380_init_one(&driver_template, pdev, base[ndev], | |
542 | irq[ndev], card[ndev]); | |
543 | if (ret) { | |
544 | if (base[ndev]) | |
545 | printk(KERN_WARNING "Card not found at address 0x%03x\n", | |
546 | base[ndev]); | |
547 | return 0; | |
548 | } | |
1da177e4 | 549 | |
a8cfbcae OZ |
550 | return 1; |
551 | } | |
552 | ||
553 | static int generic_NCR5380_isa_remove(struct device *pdev, | |
554 | unsigned int ndev) | |
555 | { | |
556 | generic_NCR5380_release_resources(dev_get_drvdata(pdev)); | |
557 | dev_set_drvdata(pdev, NULL); | |
558 | return 0; | |
559 | } | |
560 | ||
561 | static struct isa_driver generic_NCR5380_isa_driver = { | |
562 | .match = generic_NCR5380_isa_match, | |
563 | .remove = generic_NCR5380_isa_remove, | |
564 | .driver = { | |
565 | .name = DRV_MODULE_NAME | |
566 | }, | |
567 | }; | |
568 | ||
569 | #if !defined(SCSI_G_NCR5380_MEM) && defined(CONFIG_PNP) | |
570 | static struct pnp_device_id generic_NCR5380_pnp_ids[] = { | |
571 | { .id = "DTC436e", .driver_data = BOARD_DTC3181E }, | |
572 | { .id = "" } | |
573 | }; | |
574 | MODULE_DEVICE_TABLE(pnp, generic_NCR5380_pnp_ids); | |
575 | ||
576 | static int generic_NCR5380_pnp_probe(struct pnp_dev *pdev, | |
577 | const struct pnp_device_id *id) | |
578 | { | |
579 | int base, irq; | |
580 | ||
581 | if (pnp_activate_dev(pdev) < 0) | |
582 | return -EBUSY; | |
583 | ||
584 | base = pnp_port_start(pdev, 0); | |
585 | irq = pnp_irq(pdev, 0); | |
586 | ||
587 | return generic_NCR5380_init_one(&driver_template, &pdev->dev, base, irq, | |
588 | id->driver_data); | |
589 | } | |
590 | ||
591 | static void generic_NCR5380_pnp_remove(struct pnp_dev *pdev) | |
592 | { | |
593 | generic_NCR5380_release_resources(pnp_get_drvdata(pdev)); | |
594 | pnp_set_drvdata(pdev, NULL); | |
595 | } | |
596 | ||
597 | static struct pnp_driver generic_NCR5380_pnp_driver = { | |
598 | .name = DRV_MODULE_NAME, | |
599 | .id_table = generic_NCR5380_pnp_ids, | |
600 | .probe = generic_NCR5380_pnp_probe, | |
601 | .remove = generic_NCR5380_pnp_remove, | |
1da177e4 | 602 | }; |
a8cfbcae | 603 | #endif /* !defined(SCSI_G_NCR5380_MEM) && defined(CONFIG_PNP) */ |
1da177e4 | 604 | |
a8cfbcae OZ |
605 | static int pnp_registered, isa_registered; |
606 | ||
607 | static int __init generic_NCR5380_init(void) | |
608 | { | |
609 | int ret = 0; | |
610 | ||
611 | /* compatibility with old-style parameters */ | |
612 | if (irq[0] == 0 && base[0] == 0 && card[0] == -1) { | |
613 | irq[0] = ncr_irq; | |
614 | base[0] = ncr_addr; | |
615 | if (ncr_5380) | |
616 | card[0] = BOARD_NCR5380; | |
617 | if (ncr_53c400) | |
618 | card[0] = BOARD_NCR53C400; | |
619 | if (ncr_53c400a) | |
620 | card[0] = BOARD_NCR53C400A; | |
621 | if (dtc_3181e) | |
622 | card[0] = BOARD_DTC3181E; | |
623 | if (hp_c2502) | |
624 | card[0] = BOARD_HP_C2502; | |
625 | } | |
626 | ||
627 | #if !defined(SCSI_G_NCR5380_MEM) && defined(CONFIG_PNP) | |
628 | if (!pnp_register_driver(&generic_NCR5380_pnp_driver)) | |
629 | pnp_registered = 1; | |
702a98c6 | 630 | #endif |
a8cfbcae OZ |
631 | ret = isa_register_driver(&generic_NCR5380_isa_driver, MAX_CARDS); |
632 | if (!ret) | |
633 | isa_registered = 1; | |
634 | ||
635 | return (pnp_registered || isa_registered) ? 0 : ret; | |
636 | } | |
637 | ||
638 | static void __exit generic_NCR5380_exit(void) | |
639 | { | |
640 | #if !defined(SCSI_G_NCR5380_MEM) && defined(CONFIG_PNP) | |
641 | if (pnp_registered) | |
642 | pnp_unregister_driver(&generic_NCR5380_pnp_driver); | |
643 | #endif | |
644 | if (isa_registered) | |
645 | isa_unregister_driver(&generic_NCR5380_isa_driver); | |
646 | } | |
647 | ||
648 | module_init(generic_NCR5380_init); | |
649 | module_exit(generic_NCR5380_exit); |