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1da177e4 LT |
1 | /************************************************************************ |
2 | * Linux driver for * | |
3 | * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers * | |
4 | * Intel Corporation: Storage RAID Controllers * | |
5 | * * | |
6 | * gdth.c * | |
cbd5f69b | 7 | * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner * |
1da177e4 | 8 | * Copyright (C) 2002-04 Intel Corporation * |
cbd5f69b | 9 | * Copyright (C) 2003-06 Adaptec Inc. * |
1da177e4 LT |
10 | * <achim_leubner@adaptec.com> * |
11 | * * | |
12 | * Additions/Fixes: * | |
13 | * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> * | |
14 | * Johannes Dinner <johannes_dinner@adaptec.com> * | |
15 | * * | |
16 | * This program is free software; you can redistribute it and/or modify * | |
17 | * it under the terms of the GNU General Public License as published * | |
18 | * by the Free Software Foundation; either version 2 of the License, * | |
19 | * or (at your option) any later version. * | |
20 | * * | |
21 | * This program is distributed in the hope that it will be useful, * | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
24 | * GNU General Public License for more details. * | |
25 | * * | |
26 | * You should have received a copy of the GNU General Public License * | |
27 | * along with this kernel; if not, write to the Free Software * | |
28 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * | |
29 | * * | |
cbd5f69b | 30 | * Linux kernel 2.4.x, 2.6.x supported * |
1da177e4 LT |
31 | * * |
32 | * $Log: gdth.c,v $ | |
cbd5f69b LA |
33 | * Revision 1.74 2006/04/10 13:44:47 achim |
34 | * Community changes for 2.6.x | |
35 | * Kernel 2.2.x no longer supported | |
36 | * scsi_request interface removed, thanks to Christoph Hellwig | |
37 | * | |
1da177e4 LT |
38 | * Revision 1.73 2004/03/31 13:33:03 achim |
39 | * Special command 0xfd implemented to detect 64-bit DMA support | |
40 | * | |
41 | * Revision 1.72 2004/03/17 08:56:04 achim | |
42 | * 64-bit DMA only enabled if FW >= x.43 | |
43 | * | |
44 | * Revision 1.71 2004/03/05 15:51:29 achim | |
45 | * Screen service: separate message buffer, bugfixes | |
46 | * | |
47 | * Revision 1.70 2004/02/27 12:19:07 achim | |
48 | * Bugfix: Reset bit in config (0xfe) call removed | |
49 | * | |
50 | * Revision 1.69 2004/02/20 09:50:24 achim | |
51 | * Compatibility changes for kernels < 2.4.20 | |
52 | * Bugfix screen service command size | |
53 | * pci_set_dma_mask() error handling added | |
54 | * | |
55 | * Revision 1.68 2004/02/19 15:46:54 achim | |
56 | * 64-bit DMA bugfixes | |
57 | * Drive size bugfix for drives > 1TB | |
58 | * | |
59 | * Revision 1.67 2004/01/14 13:11:57 achim | |
60 | * Tool access over /proc no longer supported | |
61 | * Bugfixes IOCTLs | |
62 | * | |
63 | * Revision 1.66 2003/12/19 15:04:06 achim | |
64 | * Bugfixes support for drives > 2TB | |
65 | * | |
66 | * Revision 1.65 2003/12/15 11:21:56 achim | |
67 | * 64-bit DMA support added | |
68 | * Support for drives > 2 TB implemented | |
69 | * Kernels 2.2.x, 2.4.x, 2.6.x supported | |
70 | * | |
71 | * Revision 1.64 2003/09/17 08:30:26 achim | |
72 | * EISA/ISA controller scan disabled | |
73 | * Command line switch probe_eisa_isa added | |
74 | * | |
75 | * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it> | |
76 | * Minor cleanups in gdth_ioctl. | |
77 | * | |
78 | * Revision 1.62 2003/02/27 15:01:59 achim | |
79 | * Dynamic DMA mapping implemented | |
80 | * New (character device) IOCTL interface added | |
81 | * Other controller related changes made | |
82 | * | |
83 | * Revision 1.61 2002/11/08 13:09:52 boji | |
84 | * Added support for XSCALE based RAID Controllers | |
85 | * Fixed SCREENSERVICE initialization in SMP cases | |
86 | * Added checks for gdth_polling before GDTH_HA_LOCK | |
87 | * | |
88 | * Revision 1.60 2002/02/05 09:35:22 achim | |
89 | * MODULE_LICENSE only if kernel >= 2.4.11 | |
90 | * | |
91 | * Revision 1.59 2002/01/30 09:46:33 achim | |
92 | * Small changes | |
93 | * | |
94 | * Revision 1.58 2002/01/29 15:30:02 achim | |
95 | * Set default value of shared_access to Y | |
96 | * New status S_CACHE_RESERV for clustering added | |
97 | * | |
98 | * Revision 1.57 2001/08/21 11:16:35 achim | |
99 | * Bugfix free_irq() | |
100 | * | |
101 | * Revision 1.56 2001/08/09 11:19:39 achim | |
cbd5f69b | 102 | * Scsi_Host_Template changes |
1da177e4 LT |
103 | * |
104 | * Revision 1.55 2001/08/09 10:11:28 achim | |
105 | * Command HOST_UNFREEZE_IO before cache service init. | |
106 | * | |
107 | * Revision 1.54 2001/07/20 13:48:12 achim | |
108 | * Expand: gdth_analyse_hdrive() removed | |
109 | * | |
110 | * Revision 1.53 2001/07/17 09:52:49 achim | |
111 | * Small OEM related change | |
112 | * | |
113 | * Revision 1.52 2001/06/19 15:06:20 achim | |
114 | * New host command GDT_UNFREEZE_IO added | |
115 | * | |
116 | * Revision 1.51 2001/05/22 06:42:37 achim | |
117 | * PCI: Subdevice ID added | |
118 | * | |
119 | * Revision 1.50 2001/05/17 13:42:16 achim | |
120 | * Support for Intel Storage RAID Controllers added | |
121 | * | |
122 | * Revision 1.50 2001/05/17 12:12:34 achim | |
123 | * Support for Intel Storage RAID Controllers added | |
124 | * | |
125 | * Revision 1.49 2001/03/15 15:07:17 achim | |
126 | * New __setup interface for boot command line options added | |
127 | * | |
128 | * Revision 1.48 2001/02/06 12:36:28 achim | |
129 | * Bugfix Cluster protocol | |
130 | * | |
131 | * Revision 1.47 2001/01/10 14:42:06 achim | |
132 | * New switch shared_access added | |
133 | * | |
134 | * Revision 1.46 2001/01/09 08:11:35 achim | |
135 | * gdth_command() removed | |
136 | * meaning of Scsi_Pointer members changed | |
137 | * | |
138 | * Revision 1.45 2000/11/16 12:02:24 achim | |
139 | * Changes for kernel 2.4 | |
140 | * | |
141 | * Revision 1.44 2000/10/11 08:44:10 achim | |
142 | * Clustering changes: New flag media_changed added | |
143 | * | |
144 | * Revision 1.43 2000/09/20 12:59:01 achim | |
145 | * DPMEM remap functions for all PCI controller types implemented | |
146 | * Small changes for ia64 platform | |
147 | * | |
148 | * Revision 1.42 2000/07/20 09:04:50 achim | |
149 | * Small changes for kernel 2.4 | |
150 | * | |
151 | * Revision 1.41 2000/07/04 14:11:11 achim | |
152 | * gdth_analyse_hdrive() added to rescan drives after online expansion | |
153 | * | |
154 | * Revision 1.40 2000/06/27 11:24:16 achim | |
155 | * Changes Clustering, Screenservice | |
156 | * | |
157 | * Revision 1.39 2000/06/15 13:09:04 achim | |
158 | * Changes for gdth_do_cmd() | |
159 | * | |
160 | * Revision 1.38 2000/06/15 12:08:43 achim | |
161 | * Bugfix gdth_sync_event(), service SCREENSERVICE | |
162 | * Data direction for command 0xc2 changed to DOU | |
163 | * | |
164 | * Revision 1.37 2000/05/25 13:50:10 achim | |
165 | * New driver parameter virt_ctr added | |
166 | * | |
167 | * Revision 1.36 2000/05/04 08:50:46 achim | |
168 | * Event buffer now in gdth_ha_str | |
169 | * | |
170 | * Revision 1.35 2000/03/03 10:44:08 achim | |
171 | * New event_string only valid for the RP controller family | |
172 | * | |
173 | * Revision 1.34 2000/03/02 14:55:29 achim | |
174 | * New mechanism for async. event handling implemented | |
175 | * | |
176 | * Revision 1.33 2000/02/21 15:37:37 achim | |
177 | * Bugfix Alpha platform + DPMEM above 4GB | |
178 | * | |
179 | * Revision 1.32 2000/02/14 16:17:37 achim | |
180 | * Bugfix sense_buffer[] + raw devices | |
181 | * | |
182 | * Revision 1.31 2000/02/10 10:29:00 achim | |
183 | * Delete sense_buffer[0], if command OK | |
184 | * | |
185 | * Revision 1.30 1999/11/02 13:42:39 achim | |
186 | * ARRAY_DRV_LIST2 implemented | |
187 | * Now 255 log. and 100 host drives supported | |
188 | * | |
189 | * Revision 1.29 1999/10/05 13:28:47 achim | |
190 | * GDT_CLUST_RESET added | |
191 | * | |
192 | * Revision 1.28 1999/08/12 13:44:54 achim | |
193 | * MOUNTALL removed | |
194 | * Cluster drives -> removeable drives | |
195 | * | |
196 | * Revision 1.27 1999/06/22 07:22:38 achim | |
197 | * Small changes | |
198 | * | |
199 | * Revision 1.26 1999/06/10 16:09:12 achim | |
200 | * Cluster Host Drive support: Bugfixes | |
201 | * | |
202 | * Revision 1.25 1999/06/01 16:03:56 achim | |
203 | * gdth_init_pci(): Manipulate config. space to start RP controller | |
204 | * | |
205 | * Revision 1.24 1999/05/26 11:53:06 achim | |
206 | * Cluster Host Drive support added | |
207 | * | |
208 | * Revision 1.23 1999/03/26 09:12:31 achim | |
209 | * Default value for hdr_channel set to 0 | |
210 | * | |
211 | * Revision 1.22 1999/03/22 16:27:16 achim | |
212 | * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA() | |
213 | * | |
214 | * Revision 1.21 1999/03/16 13:40:34 achim | |
215 | * Problems with reserved drives solved | |
216 | * gdth_eh_bus_reset() implemented | |
217 | * | |
218 | * Revision 1.20 1999/03/10 09:08:13 achim | |
219 | * Bugfix: Corrections in gdth_direction_tab[] made | |
220 | * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq() | |
221 | * | |
222 | * Revision 1.19 1999/03/05 14:38:16 achim | |
223 | * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong | |
224 | * -> gdth_eval_mapping() implemented, changes in gdth_bios_param() | |
225 | * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers | |
226 | * with BIOS disabled and memory test set to Intensive | |
227 | * Enhanced /proc support | |
228 | * | |
229 | * Revision 1.18 1999/02/24 09:54:33 achim | |
230 | * Command line parameter hdr_channel implemented | |
231 | * Bugfix for EISA controllers + Linux 2.2.x | |
232 | * | |
233 | * Revision 1.17 1998/12/17 15:58:11 achim | |
234 | * Command line parameters implemented | |
235 | * Changes for Alpha platforms | |
236 | * PCI controller scan changed | |
237 | * SMP support improved (spin_lock_irqsave(),...) | |
238 | * New async. events, new scan/reserve commands included | |
239 | * | |
240 | * Revision 1.16 1998/09/28 16:08:46 achim | |
241 | * GDT_PCIMPR: DPMEM remapping, if required | |
242 | * mdelay() added | |
243 | * | |
244 | * Revision 1.15 1998/06/03 14:54:06 achim | |
245 | * gdth_delay(), gdth_flush() implemented | |
246 | * Bugfix: gdth_release() changed | |
247 | * | |
248 | * Revision 1.14 1998/05/22 10:01:17 achim | |
249 | * mj: pcibios_strerror() removed | |
250 | * Improved SMP support (if version >= 2.1.95) | |
251 | * gdth_halt(): halt_called flag added (if version < 2.1) | |
252 | * | |
253 | * Revision 1.13 1998/04/16 09:14:57 achim | |
254 | * Reserve drives (for raw service) implemented | |
255 | * New error handling code enabled | |
256 | * Get controller name from board_info() IOCTL | |
257 | * Final round of PCI device driver patches by Martin Mares | |
258 | * | |
259 | * Revision 1.12 1998/03/03 09:32:37 achim | |
260 | * Fibre channel controller support added | |
261 | * | |
262 | * Revision 1.11 1998/01/27 16:19:14 achim | |
263 | * SA_SHIRQ added | |
264 | * add_timer()/del_timer() instead of GDTH_TIMER | |
265 | * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER | |
266 | * New error handling included | |
267 | * | |
268 | * Revision 1.10 1997/10/31 12:29:57 achim | |
269 | * Read heads/sectors from host drive | |
270 | * | |
271 | * Revision 1.9 1997/09/04 10:07:25 achim | |
272 | * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ... | |
273 | * register_reboot_notifier() to get a notify on shutown used | |
274 | * | |
275 | * Revision 1.8 1997/04/02 12:14:30 achim | |
276 | * Version 1.00 (see gdth.h), tested with kernel 2.0.29 | |
277 | * | |
278 | * Revision 1.7 1997/03/12 13:33:37 achim | |
279 | * gdth_reset() changed, new async. events | |
280 | * | |
281 | * Revision 1.6 1997/03/04 14:01:11 achim | |
282 | * Shutdown routine gdth_halt() implemented | |
283 | * | |
284 | * Revision 1.5 1997/02/21 09:08:36 achim | |
285 | * New controller included (RP, RP1, RP2 series) | |
286 | * IOCTL interface implemented | |
287 | * | |
288 | * Revision 1.4 1996/07/05 12:48:55 achim | |
289 | * Function gdth_bios_param() implemented | |
290 | * New constant GDTH_MAXC_P_L inserted | |
291 | * GDT_WRITE_THR, GDT_EXT_INFO implemented | |
292 | * Function gdth_reset() changed | |
293 | * | |
294 | * Revision 1.3 1996/05/10 09:04:41 achim | |
295 | * Small changes for Linux 1.2.13 | |
296 | * | |
297 | * Revision 1.2 1996/05/09 12:45:27 achim | |
298 | * Loadable module support implemented | |
299 | * /proc support corrections made | |
300 | * | |
301 | * Revision 1.1 1996/04/11 07:35:57 achim | |
302 | * Initial revision | |
303 | * | |
304 | ************************************************************************/ | |
305 | ||
306 | /* All GDT Disk Array Controllers are fully supported by this driver. | |
307 | * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the | |
308 | * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete | |
309 | * list of all controller types. | |
310 | * | |
311 | * If you have one or more GDT3000/3020 EISA controllers with | |
312 | * controller BIOS disabled, you have to set the IRQ values with the | |
313 | * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are | |
314 | * the IRQ values for the EISA controllers. | |
315 | * | |
316 | * After the optional list of IRQ values, other possible | |
317 | * command line options are: | |
318 | * disable:Y disable driver | |
319 | * disable:N enable driver | |
320 | * reserve_mode:0 reserve no drives for the raw service | |
321 | * reserve_mode:1 reserve all not init., removable drives | |
322 | * reserve_mode:2 reserve all not init. drives | |
323 | * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with | |
324 | * h- controller no., b- channel no., | |
325 | * t- target ID, l- LUN | |
326 | * reverse_scan:Y reverse scan order for PCI controllers | |
327 | * reverse_scan:N scan PCI controllers like BIOS | |
328 | * max_ids:x x - target ID count per channel (1..MAXID) | |
329 | * rescan:Y rescan all channels/IDs | |
330 | * rescan:N use all devices found until now | |
331 | * virt_ctr:Y map every channel to a virtual controller | |
332 | * virt_ctr:N use multi channel support | |
333 | * hdr_channel:x x - number of virtual bus for host drives | |
334 | * shared_access:Y disable driver reserve/release protocol to | |
335 | * access a shared resource from several nodes, | |
575c9687 | 336 | * appropriate controller firmware required |
1da177e4 LT |
337 | * shared_access:N enable driver reserve/release protocol |
338 | * probe_eisa_isa:Y scan for EISA/ISA controllers | |
339 | * probe_eisa_isa:N do not scan for EISA/ISA controllers | |
340 | * force_dma32:Y use only 32 bit DMA mode | |
341 | * force_dma32:N use 64 bit DMA mode, if supported | |
342 | * | |
343 | * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N, | |
344 | * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0, | |
345 | * shared_access:Y,probe_eisa_isa:N,force_dma32:N". | |
346 | * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y". | |
347 | * | |
348 | * When loading the gdth driver as a module, the same options are available. | |
349 | * You can set the IRQs with "IRQ=...". However, the syntax to specify the | |
350 | * options changes slightly. You must replace all ',' between options | |
351 | * with ' ' and all ':' with '=' and you must use | |
352 | * '1' in place of 'Y' and '0' in place of 'N'. | |
353 | * | |
354 | * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0 | |
355 | * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0 | |
356 | * probe_eisa_isa=0 force_dma32=0" | |
357 | * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1". | |
358 | */ | |
359 | ||
360 | /* The meaning of the Scsi_Pointer members in this driver is as follows: | |
361 | * ptr: Chaining | |
362 | * this_residual: Command priority | |
363 | * buffer: phys. DMA sense buffer | |
364 | * dma_handle: phys. DMA buffer (kernel >= 2.4.0) | |
365 | * buffers_residual: Timeout value | |
366 | * Status: Command status (gdth_do_cmd()), DMA mem. mappings | |
367 | * Message: Additional info (gdth_do_cmd()), DMA direction | |
368 | * have_data_in: Flag for gdth_wait_completion() | |
369 | * sent_command: Opcode special command | |
370 | * phase: Service/parameter/return code special command | |
371 | */ | |
372 | ||
373 | ||
374 | /* interrupt coalescing */ | |
375 | /* #define INT_COAL */ | |
376 | ||
377 | /* statistics */ | |
378 | #define GDTH_STATISTICS | |
379 | ||
380 | #include <linux/module.h> | |
381 | ||
382 | #include <linux/version.h> | |
383 | #include <linux/kernel.h> | |
384 | #include <linux/types.h> | |
385 | #include <linux/pci.h> | |
386 | #include <linux/string.h> | |
387 | #include <linux/ctype.h> | |
388 | #include <linux/ioport.h> | |
389 | #include <linux/delay.h> | |
1da177e4 LT |
390 | #include <linux/interrupt.h> |
391 | #include <linux/in.h> | |
392 | #include <linux/proc_fs.h> | |
393 | #include <linux/time.h> | |
394 | #include <linux/timer.h> | |
cbd5f69b | 395 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,6) |
910638ae | 396 | #include <linux/dma-mapping.h> |
cbd5f69b LA |
397 | #else |
398 | #define DMA_32BIT_MASK 0x00000000ffffffffULL | |
399 | #define DMA_64BIT_MASK 0xffffffffffffffffULL | |
400 | #endif | |
401 | ||
1da177e4 LT |
402 | #ifdef GDTH_RTC |
403 | #include <linux/mc146818rtc.h> | |
404 | #endif | |
405 | #include <linux/reboot.h> | |
406 | ||
407 | #include <asm/dma.h> | |
408 | #include <asm/system.h> | |
409 | #include <asm/io.h> | |
410 | #include <asm/uaccess.h> | |
411 | #include <linux/spinlock.h> | |
412 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) | |
413 | #include <linux/blkdev.h> | |
414 | #else | |
415 | #include <linux/blk.h> | |
416 | #include "sd.h" | |
417 | #endif | |
418 | ||
419 | #include "scsi.h" | |
420 | #include <scsi/scsi_host.h> | |
1da177e4 | 421 | #include "gdth_kcompat.h" |
cbd5f69b | 422 | #include "gdth.h" |
1da177e4 LT |
423 | |
424 | static void gdth_delay(int milliseconds); | |
425 | static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs); | |
7d12e780 | 426 | static irqreturn_t gdth_interrupt(int irq, void *dev_id); |
1da177e4 LT |
427 | static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp); |
428 | static int gdth_async_event(int hanum); | |
429 | static void gdth_log_event(gdth_evt_data *dvr, char *buffer); | |
430 | ||
431 | static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority); | |
432 | static void gdth_next(int hanum); | |
433 | static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b); | |
434 | static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp); | |
435 | static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source, | |
436 | ushort idx, gdth_evt_data *evt); | |
437 | static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr); | |
438 | static void gdth_readapp_event(gdth_ha_str *ha, unchar application, | |
439 | gdth_evt_str *estr); | |
440 | static void gdth_clear_events(void); | |
441 | ||
442 | static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp, | |
443 | char *buffer,ushort count); | |
444 | static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp); | |
445 | static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive); | |
446 | ||
1da177e4 LT |
447 | static int gdth_search_pci(gdth_pci_str *pcistr); |
448 | static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt, | |
449 | ushort vendor, ushort dev); | |
450 | static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt); | |
1da177e4 LT |
451 | static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha); |
452 | ||
453 | static void gdth_enable_int(int hanum); | |
454 | static int gdth_get_status(unchar *pIStatus,int irq); | |
455 | static int gdth_test_busy(int hanum); | |
456 | static int gdth_get_cmd_index(int hanum); | |
457 | static void gdth_release_event(int hanum); | |
458 | static int gdth_wait(int hanum,int index,ulong32 time); | |
459 | static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1, | |
460 | ulong64 p2,ulong64 p3); | |
461 | static int gdth_search_drives(int hanum); | |
462 | static int gdth_analyse_hdrive(int hanum, ushort hdrive); | |
463 | ||
464 | static const char *gdth_ctr_name(int hanum); | |
465 | ||
466 | static int gdth_open(struct inode *inode, struct file *filep); | |
467 | static int gdth_close(struct inode *inode, struct file *filep); | |
468 | static int gdth_ioctl(struct inode *inode, struct file *filep, | |
469 | unsigned int cmd, unsigned long arg); | |
470 | ||
471 | static void gdth_flush(int hanum); | |
472 | static int gdth_halt(struct notifier_block *nb, ulong event, void *buf); | |
cbd5f69b LA |
473 | static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *)); |
474 | static void gdth_scsi_done(struct scsi_cmnd *scp); | |
aed91cb5 CH |
475 | #ifdef CONFIG_ISA |
476 | static int gdth_isa_probe_one(struct scsi_host_template *, ulong32); | |
477 | #endif | |
706a5d45 CH |
478 | #ifdef CONFIG_EISA |
479 | static int gdth_eisa_probe_one(struct scsi_host_template *, ushort); | |
480 | #endif | |
1da177e4 LT |
481 | |
482 | #ifdef DEBUG_GDTH | |
483 | static unchar DebugState = DEBUG_GDTH; | |
484 | ||
485 | #ifdef __SERIAL__ | |
486 | #define MAX_SERBUF 160 | |
487 | static void ser_init(void); | |
488 | static void ser_puts(char *str); | |
489 | static void ser_putc(char c); | |
490 | static int ser_printk(const char *fmt, ...); | |
491 | static char strbuf[MAX_SERBUF+1]; | |
492 | #ifdef __COM2__ | |
493 | #define COM_BASE 0x2f8 | |
494 | #else | |
495 | #define COM_BASE 0x3f8 | |
496 | #endif | |
497 | static void ser_init() | |
498 | { | |
499 | unsigned port=COM_BASE; | |
500 | ||
501 | outb(0x80,port+3); | |
502 | outb(0,port+1); | |
503 | /* 19200 Baud, if 9600: outb(12,port) */ | |
504 | outb(6, port); | |
505 | outb(3,port+3); | |
506 | outb(0,port+1); | |
507 | /* | |
508 | ser_putc('I'); | |
509 | ser_putc(' '); | |
510 | */ | |
511 | } | |
512 | ||
513 | static void ser_puts(char *str) | |
514 | { | |
515 | char *ptr; | |
516 | ||
517 | ser_init(); | |
518 | for (ptr=str;*ptr;++ptr) | |
519 | ser_putc(*ptr); | |
520 | } | |
521 | ||
522 | static void ser_putc(char c) | |
523 | { | |
524 | unsigned port=COM_BASE; | |
525 | ||
526 | while ((inb(port+5) & 0x20)==0); | |
527 | outb(c,port); | |
528 | if (c==0x0a) | |
529 | { | |
530 | while ((inb(port+5) & 0x20)==0); | |
531 | outb(0x0d,port); | |
532 | } | |
533 | } | |
534 | ||
535 | static int ser_printk(const char *fmt, ...) | |
536 | { | |
537 | va_list args; | |
538 | int i; | |
539 | ||
540 | va_start(args,fmt); | |
541 | i = vsprintf(strbuf,fmt,args); | |
542 | ser_puts(strbuf); | |
543 | va_end(args); | |
544 | return i; | |
545 | } | |
546 | ||
547 | #define TRACE(a) {if (DebugState==1) {ser_printk a;}} | |
548 | #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}} | |
549 | #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}} | |
550 | ||
551 | #else /* !__SERIAL__ */ | |
552 | #define TRACE(a) {if (DebugState==1) {printk a;}} | |
553 | #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}} | |
554 | #define TRACE3(a) {if (DebugState!=0) {printk a;}} | |
555 | #endif | |
556 | ||
557 | #else /* !DEBUG */ | |
558 | #define TRACE(a) | |
559 | #define TRACE2(a) | |
560 | #define TRACE3(a) | |
561 | #endif | |
562 | ||
563 | #ifdef GDTH_STATISTICS | |
564 | static ulong32 max_rq=0, max_index=0, max_sg=0; | |
565 | #ifdef INT_COAL | |
566 | static ulong32 max_int_coal=0; | |
567 | #endif | |
568 | static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0; | |
569 | static struct timer_list gdth_timer; | |
570 | #endif | |
571 | ||
572 | #define PTR2USHORT(a) (ushort)(ulong)(a) | |
6391a113 TK |
573 | #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b) |
574 | #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t)) | |
1da177e4 LT |
575 | |
576 | #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata)) | |
577 | #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext) | |
578 | #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext) | |
579 | ||
580 | #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b)) | |
581 | ||
582 | #define gdth_readb(addr) readb(addr) | |
583 | #define gdth_readw(addr) readw(addr) | |
584 | #define gdth_readl(addr) readl(addr) | |
585 | #define gdth_writeb(b,addr) writeb((b),(addr)) | |
586 | #define gdth_writew(b,addr) writew((b),(addr)) | |
587 | #define gdth_writel(b,addr) writel((b),(addr)) | |
588 | ||
aed91cb5 | 589 | #ifdef CONFIG_ISA |
1da177e4 | 590 | static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */ |
aed91cb5 | 591 | #endif |
706a5d45 | 592 | #ifdef CONFIG_EISA |
1da177e4 | 593 | static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */ |
706a5d45 | 594 | #endif |
1da177e4 LT |
595 | static unchar gdth_polling; /* polling if TRUE */ |
596 | static unchar gdth_from_wait = FALSE; /* gdth_wait() */ | |
597 | static int wait_index,wait_hanum; /* gdth_wait() */ | |
598 | static int gdth_ctr_count = 0; /* controller count */ | |
599 | static int gdth_ctr_vcount = 0; /* virt. ctr. count */ | |
600 | static int gdth_ctr_released = 0; /* gdth_release() */ | |
601 | static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */ | |
602 | static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */ | |
603 | static unchar gdth_write_through = FALSE; /* write through */ | |
604 | static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */ | |
605 | static int elastidx; | |
606 | static int eoldidx; | |
607 | static int major; | |
608 | ||
609 | #define DIN 1 /* IN data direction */ | |
610 | #define DOU 2 /* OUT data direction */ | |
611 | #define DNO DIN /* no data transfer */ | |
612 | #define DUN DIN /* unknown data direction */ | |
613 | static unchar gdth_direction_tab[0x100] = { | |
614 | DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN, | |
615 | DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN, | |
616 | DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU, | |
617 | DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU, | |
618 | DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN, | |
619 | DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN, | |
620 | DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN, | |
621 | DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN, | |
622 | DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN, | |
623 | DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN, | |
624 | DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU, | |
625 | DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN, | |
626 | DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN, | |
627 | DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN, | |
628 | DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN, | |
629 | DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN | |
630 | }; | |
631 | ||
632 | /* LILO and modprobe/insmod parameters */ | |
633 | /* IRQ list for GDT3000/3020 EISA controllers */ | |
634 | static int irq[MAXHA] __initdata = | |
635 | {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, | |
636 | 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}; | |
637 | /* disable driver flag */ | |
638 | static int disable __initdata = 0; | |
639 | /* reserve flag */ | |
640 | static int reserve_mode = 1; | |
641 | /* reserve list */ | |
642 | static int reserve_list[MAX_RES_ARGS] = | |
643 | {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, | |
644 | 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, | |
645 | 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}; | |
646 | /* scan order for PCI controllers */ | |
647 | static int reverse_scan = 0; | |
648 | /* virtual channel for the host drives */ | |
649 | static int hdr_channel = 0; | |
650 | /* max. IDs per channel */ | |
651 | static int max_ids = MAXID; | |
652 | /* rescan all IDs */ | |
653 | static int rescan = 0; | |
654 | /* map channels to virtual controllers */ | |
655 | static int virt_ctr = 0; | |
656 | /* shared access */ | |
657 | static int shared_access = 1; | |
658 | /* enable support for EISA and ISA controllers */ | |
659 | static int probe_eisa_isa = 0; | |
660 | /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */ | |
661 | static int force_dma32 = 0; | |
662 | ||
663 | /* parameters for modprobe/insmod */ | |
cbd5f69b | 664 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11) |
1da177e4 LT |
665 | module_param_array(irq, int, NULL, 0); |
666 | module_param(disable, int, 0); | |
667 | module_param(reserve_mode, int, 0); | |
668 | module_param_array(reserve_list, int, NULL, 0); | |
669 | module_param(reverse_scan, int, 0); | |
670 | module_param(hdr_channel, int, 0); | |
671 | module_param(max_ids, int, 0); | |
672 | module_param(rescan, int, 0); | |
673 | module_param(virt_ctr, int, 0); | |
674 | module_param(shared_access, int, 0); | |
675 | module_param(probe_eisa_isa, int, 0); | |
676 | module_param(force_dma32, int, 0); | |
cbd5f69b LA |
677 | #else |
678 | MODULE_PARM(irq, "i"); | |
679 | MODULE_PARM(disable, "i"); | |
680 | MODULE_PARM(reserve_mode, "i"); | |
681 | MODULE_PARM(reserve_list, "4-" __MODULE_STRING(MAX_RES_ARGS) "i"); | |
682 | MODULE_PARM(reverse_scan, "i"); | |
683 | MODULE_PARM(hdr_channel, "i"); | |
684 | MODULE_PARM(max_ids, "i"); | |
685 | MODULE_PARM(rescan, "i"); | |
686 | MODULE_PARM(virt_ctr, "i"); | |
687 | MODULE_PARM(shared_access, "i"); | |
688 | MODULE_PARM(probe_eisa_isa, "i"); | |
689 | MODULE_PARM(force_dma32, "i"); | |
690 | #endif | |
1da177e4 LT |
691 | MODULE_AUTHOR("Achim Leubner"); |
692 | MODULE_LICENSE("GPL"); | |
693 | ||
694 | /* ioctl interface */ | |
00977a59 | 695 | static const struct file_operations gdth_fops = { |
1da177e4 LT |
696 | .ioctl = gdth_ioctl, |
697 | .open = gdth_open, | |
698 | .release = gdth_close, | |
699 | }; | |
700 | ||
687d2bc4 MW |
701 | #define GDTH_MAGIC 0xc2e7c389 /* I got it from /dev/urandom */ |
702 | #define IS_GDTH_INTERNAL_CMD(scp) (scp->underflow == GDTH_MAGIC) | |
703 | ||
1da177e4 LT |
704 | #include "gdth_proc.h" |
705 | #include "gdth_proc.c" | |
706 | ||
707 | /* notifier block to get a notify on system shutdown/halt/reboot */ | |
708 | static struct notifier_block gdth_notifier = { | |
709 | gdth_halt, NULL, 0 | |
710 | }; | |
e041c683 | 711 | static int notifier_disabled = 0; |
1da177e4 LT |
712 | |
713 | static void gdth_delay(int milliseconds) | |
714 | { | |
715 | if (milliseconds == 0) { | |
716 | udelay(1); | |
717 | } else { | |
718 | mdelay(milliseconds); | |
719 | } | |
720 | } | |
721 | ||
cbd5f69b LA |
722 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) |
723 | static void gdth_scsi_done(struct scsi_cmnd *scp) | |
724 | { | |
b8bff2ae | 725 | TRACE2(("gdth_scsi_done()\n")); |
cbd5f69b | 726 | |
b8bff2ae MW |
727 | if (IS_GDTH_INTERNAL_CMD(scp)) |
728 | complete((struct completion *)scp->request); | |
729 | else | |
730 | scp->scsi_done(scp); | |
cbd5f69b LA |
731 | } |
732 | ||
733 | int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd, | |
734 | int timeout, u32 *info) | |
735 | { | |
736 | Scsi_Cmnd *scp; | |
6e9a4738 | 737 | DECLARE_COMPLETION_ONSTACK(wait); |
cbd5f69b LA |
738 | int rval; |
739 | ||
bbfbbbc1 | 740 | scp = kzalloc(sizeof(*scp), GFP_KERNEL); |
cbd5f69b LA |
741 | if (!scp) |
742 | return -ENOMEM; | |
bbfbbbc1 | 743 | |
cbd5f69b | 744 | scp->device = sdev; |
beb40487 CH |
745 | /* use request field to save the ptr. to completion struct. */ |
746 | scp->request = (struct request *)&wait; | |
cbd5f69b LA |
747 | scp->timeout_per_command = timeout*HZ; |
748 | scp->request_buffer = gdtcmd; | |
749 | scp->cmd_len = 12; | |
750 | memcpy(scp->cmnd, cmnd, 12); | |
751 | scp->SCp.this_residual = IOCTL_PRI; /* priority */ | |
687d2bc4 | 752 | scp->underflow = GDTH_MAGIC; |
b8bff2ae | 753 | gdth_queuecommand(scp, NULL); |
cbd5f69b LA |
754 | wait_for_completion(&wait); |
755 | ||
756 | rval = scp->SCp.Status; | |
757 | if (info) | |
758 | *info = scp->SCp.Message; | |
759 | kfree(scp); | |
760 | return rval; | |
761 | } | |
762 | #else | |
763 | static void gdth_scsi_done(Scsi_Cmnd *scp) | |
764 | { | |
765 | TRACE2(("gdth_scsi_done()\n")); | |
766 | ||
767 | scp->request.rq_status = RQ_SCSI_DONE; | |
768 | if (scp->request.waiting) | |
769 | complete(scp->request.waiting); | |
770 | } | |
771 | ||
772 | int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd, | |
773 | int timeout, u32 *info) | |
774 | { | |
775 | Scsi_Cmnd *scp = scsi_allocate_device(sdev, 1, FALSE); | |
776 | unsigned bufflen = gdtcmd ? sizeof(gdth_cmd_str) : 0; | |
6e9a4738 | 777 | DECLARE_COMPLETION_ONSTACK(wait); |
cbd5f69b LA |
778 | int rval; |
779 | ||
780 | if (!scp) | |
781 | return -ENOMEM; | |
782 | scp->cmd_len = 12; | |
783 | scp->use_sg = 0; | |
784 | scp->SCp.this_residual = IOCTL_PRI; /* priority */ | |
785 | scp->request.rq_status = RQ_SCSI_BUSY; | |
786 | scp->request.waiting = &wait; | |
787 | scsi_do_cmd(scp, cmnd, gdtcmd, bufflen, gdth_scsi_done, timeout*HZ, 1); | |
788 | wait_for_completion(&wait); | |
789 | ||
790 | rval = scp->SCp.Status; | |
791 | if (info) | |
792 | *info = scp->SCp.Message; | |
793 | ||
794 | scsi_release_command(scp); | |
795 | return rval; | |
796 | } | |
797 | #endif | |
798 | ||
799 | int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd, | |
800 | int timeout, u32 *info) | |
801 | { | |
802 | struct scsi_device *sdev = scsi_get_host_dev(shost); | |
803 | int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info); | |
804 | ||
805 | scsi_free_host_dev(sdev); | |
806 | return rval; | |
807 | } | |
808 | ||
1da177e4 LT |
809 | static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs) |
810 | { | |
811 | *cyls = size /HEADS/SECS; | |
812 | if (*cyls <= MAXCYLS) { | |
813 | *heads = HEADS; | |
814 | *secs = SECS; | |
815 | } else { /* too high for 64*32 */ | |
816 | *cyls = size /MEDHEADS/MEDSECS; | |
817 | if (*cyls <= MAXCYLS) { | |
818 | *heads = MEDHEADS; | |
819 | *secs = MEDSECS; | |
820 | } else { /* too high for 127*63 */ | |
821 | *cyls = size /BIGHEADS/BIGSECS; | |
822 | *heads = BIGHEADS; | |
823 | *secs = BIGSECS; | |
824 | } | |
825 | } | |
826 | } | |
827 | ||
828 | /* controller search and initialization functions */ | |
706a5d45 | 829 | #ifdef CONFIG_EISA |
1da177e4 LT |
830 | static int __init gdth_search_eisa(ushort eisa_adr) |
831 | { | |
832 | ulong32 id; | |
833 | ||
834 | TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr)); | |
835 | id = inl(eisa_adr+ID0REG); | |
836 | if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */ | |
837 | if ((inb(eisa_adr+EISAREG) & 8) == 0) | |
838 | return 0; /* not EISA configured */ | |
839 | return 1; | |
840 | } | |
841 | if (id == GDT3_ID) /* GDT3000 */ | |
842 | return 1; | |
843 | ||
844 | return 0; | |
845 | } | |
706a5d45 | 846 | #endif /* CONFIG_EISA */ |
1da177e4 | 847 | |
aed91cb5 | 848 | #ifdef CONFIG_ISA |
1da177e4 LT |
849 | static int __init gdth_search_isa(ulong32 bios_adr) |
850 | { | |
851 | void __iomem *addr; | |
852 | ulong32 id; | |
853 | ||
854 | TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr)); | |
855 | if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) { | |
856 | id = gdth_readl(addr); | |
857 | iounmap(addr); | |
858 | if (id == GDT2_ID) /* GDT2000 */ | |
859 | return 1; | |
860 | } | |
861 | return 0; | |
862 | } | |
aed91cb5 | 863 | #endif /* CONFIG_ISA */ |
1da177e4 LT |
864 | |
865 | static int __init gdth_search_pci(gdth_pci_str *pcistr) | |
866 | { | |
867 | ushort device, cnt; | |
868 | ||
869 | TRACE(("gdth_search_pci()\n")); | |
870 | ||
871 | cnt = 0; | |
872 | for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device) | |
873 | gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device); | |
874 | for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP; | |
875 | device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device) | |
876 | gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device); | |
877 | gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, | |
878 | PCI_DEVICE_ID_VORTEX_GDTNEWRX); | |
879 | gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, | |
880 | PCI_DEVICE_ID_VORTEX_GDTNEWRX2); | |
881 | gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL, | |
882 | PCI_DEVICE_ID_INTEL_SRC); | |
883 | gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL, | |
884 | PCI_DEVICE_ID_INTEL_SRC_XSCALE); | |
885 | return cnt; | |
886 | } | |
887 | ||
888 | /* Vortex only makes RAID controllers. | |
889 | * We do not really want to specify all 550 ids here, so wildcard match. | |
890 | */ | |
6c4b7e4f | 891 | static struct pci_device_id gdthtable[] __maybe_unused = { |
1da177e4 LT |
892 | {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID}, |
893 | {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID}, | |
894 | {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID}, | |
895 | {0} | |
896 | }; | |
897 | MODULE_DEVICE_TABLE(pci,gdthtable); | |
898 | ||
899 | static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt, | |
cbd5f69b | 900 | ushort vendor, ushort device) |
1da177e4 LT |
901 | { |
902 | ulong base0, base1, base2; | |
903 | struct pci_dev *pdev; | |
904 | ||
905 | TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n", | |
906 | *cnt, vendor, device)); | |
907 | ||
908 | pdev = NULL; | |
909 | while ((pdev = pci_find_device(vendor, device, pdev)) | |
910 | != NULL) { | |
911 | if (pci_enable_device(pdev)) | |
912 | continue; | |
913 | if (*cnt >= MAXHA) | |
914 | return; | |
915 | /* GDT PCI controller found, resources are already in pdev */ | |
916 | pcistr[*cnt].pdev = pdev; | |
1da177e4 LT |
917 | pcistr[*cnt].irq = pdev->irq; |
918 | base0 = pci_resource_flags(pdev, 0); | |
919 | base1 = pci_resource_flags(pdev, 1); | |
920 | base2 = pci_resource_flags(pdev, 2); | |
921 | if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */ | |
922 | device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */ | |
923 | if (!(base0 & IORESOURCE_MEM)) | |
924 | continue; | |
925 | pcistr[*cnt].dpmem = pci_resource_start(pdev, 0); | |
926 | } else { /* GDT6110, GDT6120, .. */ | |
927 | if (!(base0 & IORESOURCE_MEM) || | |
928 | !(base2 & IORESOURCE_MEM) || | |
929 | !(base1 & IORESOURCE_IO)) | |
930 | continue; | |
931 | pcistr[*cnt].dpmem = pci_resource_start(pdev, 2); | |
932 | pcistr[*cnt].io_mm = pci_resource_start(pdev, 0); | |
933 | pcistr[*cnt].io = pci_resource_start(pdev, 1); | |
934 | } | |
935 | TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n", | |
8e9a8a0d JG |
936 | pcistr[*cnt].pdev->bus->number, |
937 | PCI_SLOT(pcistr[*cnt].pdev->devfn), | |
1da177e4 LT |
938 | pcistr[*cnt].irq, pcistr[*cnt].dpmem)); |
939 | (*cnt)++; | |
940 | } | |
941 | } | |
942 | ||
943 | ||
944 | static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt) | |
945 | { | |
946 | gdth_pci_str temp; | |
947 | int i, changed; | |
948 | ||
949 | TRACE(("gdth_sort_pci() cnt %d\n",cnt)); | |
950 | if (cnt == 0) | |
951 | return; | |
952 | ||
953 | do { | |
954 | changed = FALSE; | |
955 | for (i = 0; i < cnt-1; ++i) { | |
956 | if (!reverse_scan) { | |
8e9a8a0d JG |
957 | if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) || |
958 | (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number && | |
959 | PCI_SLOT(pcistr[i].pdev->devfn) > | |
960 | PCI_SLOT(pcistr[i+1].pdev->devfn))) { | |
1da177e4 LT |
961 | temp = pcistr[i]; |
962 | pcistr[i] = pcistr[i+1]; | |
963 | pcistr[i+1] = temp; | |
964 | changed = TRUE; | |
965 | } | |
966 | } else { | |
8e9a8a0d JG |
967 | if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) || |
968 | (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number && | |
969 | PCI_SLOT(pcistr[i].pdev->devfn) < | |
970 | PCI_SLOT(pcistr[i+1].pdev->devfn))) { | |
1da177e4 LT |
971 | temp = pcistr[i]; |
972 | pcistr[i] = pcistr[i+1]; | |
973 | pcistr[i+1] = temp; | |
974 | changed = TRUE; | |
975 | } | |
976 | } | |
977 | } | |
978 | } while (changed); | |
979 | } | |
980 | ||
706a5d45 | 981 | #ifdef CONFIG_EISA |
1da177e4 LT |
982 | static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha) |
983 | { | |
984 | ulong32 retries,id; | |
985 | unchar prot_ver,eisacf,i,irq_found; | |
986 | ||
987 | TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr)); | |
988 | ||
989 | /* disable board interrupts, deinitialize services */ | |
990 | outb(0xff,eisa_adr+EDOORREG); | |
991 | outb(0x00,eisa_adr+EDENABREG); | |
992 | outb(0x00,eisa_adr+EINTENABREG); | |
993 | ||
994 | outb(0xff,eisa_adr+LDOORREG); | |
995 | retries = INIT_RETRIES; | |
996 | gdth_delay(20); | |
997 | while (inb(eisa_adr+EDOORREG) != 0xff) { | |
998 | if (--retries == 0) { | |
999 | printk("GDT-EISA: Initialization error (DEINIT failed)\n"); | |
1000 | return 0; | |
1001 | } | |
1002 | gdth_delay(1); | |
1003 | TRACE2(("wait for DEINIT: retries=%d\n",retries)); | |
1004 | } | |
1005 | prot_ver = inb(eisa_adr+MAILBOXREG); | |
1006 | outb(0xff,eisa_adr+EDOORREG); | |
1007 | if (prot_ver != PROTOCOL_VERSION) { | |
1008 | printk("GDT-EISA: Illegal protocol version\n"); | |
1009 | return 0; | |
1010 | } | |
1011 | ha->bmic = eisa_adr; | |
1012 | ha->brd_phys = (ulong32)eisa_adr >> 12; | |
1013 | ||
1014 | outl(0,eisa_adr+MAILBOXREG); | |
1015 | outl(0,eisa_adr+MAILBOXREG+4); | |
1016 | outl(0,eisa_adr+MAILBOXREG+8); | |
1017 | outl(0,eisa_adr+MAILBOXREG+12); | |
1018 | ||
1019 | /* detect IRQ */ | |
1020 | if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) { | |
1021 | ha->oem_id = OEM_ID_ICP; | |
1022 | ha->type = GDT_EISA; | |
1023 | ha->stype = id; | |
1024 | outl(1,eisa_adr+MAILBOXREG+8); | |
1025 | outb(0xfe,eisa_adr+LDOORREG); | |
1026 | retries = INIT_RETRIES; | |
1027 | gdth_delay(20); | |
1028 | while (inb(eisa_adr+EDOORREG) != 0xfe) { | |
1029 | if (--retries == 0) { | |
1030 | printk("GDT-EISA: Initialization error (get IRQ failed)\n"); | |
1031 | return 0; | |
1032 | } | |
1033 | gdth_delay(1); | |
1034 | } | |
1035 | ha->irq = inb(eisa_adr+MAILBOXREG); | |
1036 | outb(0xff,eisa_adr+EDOORREG); | |
1037 | TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq)); | |
1038 | /* check the result */ | |
1039 | if (ha->irq == 0) { | |
1040 | TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n")); | |
1041 | for (i = 0, irq_found = FALSE; | |
1042 | i < MAXHA && irq[i] != 0xff; ++i) { | |
1043 | if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) { | |
1044 | irq_found = TRUE; | |
1045 | break; | |
1046 | } | |
1047 | } | |
1048 | if (irq_found) { | |
1049 | ha->irq = irq[i]; | |
1050 | irq[i] = 0; | |
1051 | printk("GDT-EISA: Can not detect controller IRQ,\n"); | |
1052 | printk("Use IRQ setting from command line (IRQ = %d)\n", | |
1053 | ha->irq); | |
1054 | } else { | |
1055 | printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n"); | |
1056 | printk("the controller BIOS or use command line parameters\n"); | |
1057 | return 0; | |
1058 | } | |
1059 | } | |
1060 | } else { | |
1061 | eisacf = inb(eisa_adr+EISAREG) & 7; | |
1062 | if (eisacf > 4) /* level triggered */ | |
1063 | eisacf -= 4; | |
1064 | ha->irq = gdth_irq_tab[eisacf]; | |
1065 | ha->oem_id = OEM_ID_ICP; | |
1066 | ha->type = GDT_EISA; | |
1067 | ha->stype = id; | |
1068 | } | |
1069 | ||
1070 | ha->dma64_support = 0; | |
1071 | return 1; | |
1072 | } | |
706a5d45 | 1073 | #endif /* CONFIG_EISA */ |
1da177e4 | 1074 | |
aed91cb5 | 1075 | #ifdef CONFIG_ISA |
1da177e4 LT |
1076 | static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha) |
1077 | { | |
1078 | register gdt2_dpram_str __iomem *dp2_ptr; | |
1079 | int i; | |
1080 | unchar irq_drq,prot_ver; | |
1081 | ulong32 retries; | |
1082 | ||
1083 | TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr)); | |
1084 | ||
1085 | ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str)); | |
1086 | if (ha->brd == NULL) { | |
1087 | printk("GDT-ISA: Initialization error (DPMEM remap error)\n"); | |
1088 | return 0; | |
1089 | } | |
1090 | dp2_ptr = ha->brd; | |
1091 | gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */ | |
1092 | /* reset interface area */ | |
1093 | memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u)); | |
1094 | if (gdth_readl(&dp2_ptr->u) != 0) { | |
1095 | printk("GDT-ISA: Initialization error (DPMEM write error)\n"); | |
1096 | iounmap(ha->brd); | |
1097 | return 0; | |
1098 | } | |
1099 | ||
1100 | /* disable board interrupts, read DRQ and IRQ */ | |
1101 | gdth_writeb(0xff, &dp2_ptr->io.irqdel); | |
1102 | gdth_writeb(0x00, &dp2_ptr->io.irqen); | |
1103 | gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status); | |
1104 | gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index); | |
1105 | ||
1106 | irq_drq = gdth_readb(&dp2_ptr->io.rq); | |
1107 | for (i=0; i<3; ++i) { | |
1108 | if ((irq_drq & 1)==0) | |
1109 | break; | |
1110 | irq_drq >>= 1; | |
1111 | } | |
1112 | ha->drq = gdth_drq_tab[i]; | |
1113 | ||
1114 | irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3; | |
1115 | for (i=1; i<5; ++i) { | |
1116 | if ((irq_drq & 1)==0) | |
1117 | break; | |
1118 | irq_drq >>= 1; | |
1119 | } | |
1120 | ha->irq = gdth_irq_tab[i]; | |
1121 | ||
1122 | /* deinitialize services */ | |
1123 | gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]); | |
1124 | gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx); | |
1125 | gdth_writeb(0, &dp2_ptr->io.event); | |
1126 | retries = INIT_RETRIES; | |
1127 | gdth_delay(20); | |
1128 | while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) { | |
1129 | if (--retries == 0) { | |
1130 | printk("GDT-ISA: Initialization error (DEINIT failed)\n"); | |
1131 | iounmap(ha->brd); | |
1132 | return 0; | |
1133 | } | |
1134 | gdth_delay(1); | |
1135 | } | |
1136 | prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]); | |
1137 | gdth_writeb(0, &dp2_ptr->u.ic.Status); | |
1138 | gdth_writeb(0xff, &dp2_ptr->io.irqdel); | |
1139 | if (prot_ver != PROTOCOL_VERSION) { | |
1140 | printk("GDT-ISA: Illegal protocol version\n"); | |
1141 | iounmap(ha->brd); | |
1142 | return 0; | |
1143 | } | |
1144 | ||
1145 | ha->oem_id = OEM_ID_ICP; | |
1146 | ha->type = GDT_ISA; | |
1147 | ha->ic_all_size = sizeof(dp2_ptr->u); | |
1148 | ha->stype= GDT2_ID; | |
1149 | ha->brd_phys = bios_adr >> 4; | |
1150 | ||
1151 | /* special request to controller BIOS */ | |
1152 | gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]); | |
1153 | gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]); | |
1154 | gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]); | |
1155 | gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]); | |
1156 | gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx); | |
1157 | gdth_writeb(0, &dp2_ptr->io.event); | |
1158 | retries = INIT_RETRIES; | |
1159 | gdth_delay(20); | |
1160 | while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) { | |
1161 | if (--retries == 0) { | |
1162 | printk("GDT-ISA: Initialization error\n"); | |
1163 | iounmap(ha->brd); | |
1164 | return 0; | |
1165 | } | |
1166 | gdth_delay(1); | |
1167 | } | |
1168 | gdth_writeb(0, &dp2_ptr->u.ic.Status); | |
1169 | gdth_writeb(0xff, &dp2_ptr->io.irqdel); | |
1170 | ||
1171 | ha->dma64_support = 0; | |
1172 | return 1; | |
1173 | } | |
aed91cb5 | 1174 | #endif /* CONFIG_ISA */ |
1da177e4 LT |
1175 | |
1176 | static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha) | |
1177 | { | |
1178 | register gdt6_dpram_str __iomem *dp6_ptr; | |
1179 | register gdt6c_dpram_str __iomem *dp6c_ptr; | |
1180 | register gdt6m_dpram_str __iomem *dp6m_ptr; | |
1181 | ulong32 retries; | |
1182 | unchar prot_ver; | |
1183 | ushort command; | |
1184 | int i, found = FALSE; | |
1185 | ||
1186 | TRACE(("gdth_init_pci()\n")); | |
1187 | ||
8e9a8a0d | 1188 | if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL) |
1da177e4 LT |
1189 | ha->oem_id = OEM_ID_INTEL; |
1190 | else | |
1191 | ha->oem_id = OEM_ID_ICP; | |
8e9a8a0d JG |
1192 | ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8); |
1193 | ha->stype = (ulong32)pcistr->pdev->device; | |
1da177e4 LT |
1194 | ha->irq = pcistr->irq; |
1195 | ha->pdev = pcistr->pdev; | |
1196 | ||
8e9a8a0d | 1197 | if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */ |
1da177e4 LT |
1198 | TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq)); |
1199 | ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str)); | |
1200 | if (ha->brd == NULL) { | |
1201 | printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); | |
1202 | return 0; | |
1203 | } | |
1204 | /* check and reset interface area */ | |
1205 | dp6_ptr = ha->brd; | |
1206 | gdth_writel(DPMEM_MAGIC, &dp6_ptr->u); | |
1207 | if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) { | |
1208 | printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n", | |
1209 | pcistr->dpmem); | |
1210 | found = FALSE; | |
1211 | for (i = 0xC8000; i < 0xE8000; i += 0x4000) { | |
1212 | iounmap(ha->brd); | |
1213 | ha->brd = ioremap(i, sizeof(ushort)); | |
1214 | if (ha->brd == NULL) { | |
1215 | printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); | |
1216 | return 0; | |
1217 | } | |
1218 | if (gdth_readw(ha->brd) != 0xffff) { | |
1219 | TRACE2(("init_pci_old() address 0x%x busy\n", i)); | |
1220 | continue; | |
1221 | } | |
1222 | iounmap(ha->brd); | |
1223 | pci_write_config_dword(pcistr->pdev, | |
1224 | PCI_BASE_ADDRESS_0, i); | |
1225 | ha->brd = ioremap(i, sizeof(gdt6_dpram_str)); | |
1226 | if (ha->brd == NULL) { | |
1227 | printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); | |
1228 | return 0; | |
1229 | } | |
1230 | dp6_ptr = ha->brd; | |
1231 | gdth_writel(DPMEM_MAGIC, &dp6_ptr->u); | |
1232 | if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) { | |
1233 | printk("GDT-PCI: Use free address at 0x%x\n", i); | |
1234 | found = TRUE; | |
1235 | break; | |
1236 | } | |
1237 | } | |
1238 | if (!found) { | |
1239 | printk("GDT-PCI: No free address found!\n"); | |
1240 | iounmap(ha->brd); | |
1241 | return 0; | |
1242 | } | |
1243 | } | |
1244 | memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u)); | |
1245 | if (gdth_readl(&dp6_ptr->u) != 0) { | |
1246 | printk("GDT-PCI: Initialization error (DPMEM write error)\n"); | |
1247 | iounmap(ha->brd); | |
1248 | return 0; | |
1249 | } | |
1250 | ||
1251 | /* disable board interrupts, deinit services */ | |
1252 | gdth_writeb(0xff, &dp6_ptr->io.irqdel); | |
1253 | gdth_writeb(0x00, &dp6_ptr->io.irqen); | |
1254 | gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status); | |
1255 | gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index); | |
1256 | ||
1257 | gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]); | |
1258 | gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx); | |
1259 | gdth_writeb(0, &dp6_ptr->io.event); | |
1260 | retries = INIT_RETRIES; | |
1261 | gdth_delay(20); | |
1262 | while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) { | |
1263 | if (--retries == 0) { | |
1264 | printk("GDT-PCI: Initialization error (DEINIT failed)\n"); | |
1265 | iounmap(ha->brd); | |
1266 | return 0; | |
1267 | } | |
1268 | gdth_delay(1); | |
1269 | } | |
1270 | prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]); | |
1271 | gdth_writeb(0, &dp6_ptr->u.ic.S_Status); | |
1272 | gdth_writeb(0xff, &dp6_ptr->io.irqdel); | |
1273 | if (prot_ver != PROTOCOL_VERSION) { | |
1274 | printk("GDT-PCI: Illegal protocol version\n"); | |
1275 | iounmap(ha->brd); | |
1276 | return 0; | |
1277 | } | |
1278 | ||
1279 | ha->type = GDT_PCI; | |
1280 | ha->ic_all_size = sizeof(dp6_ptr->u); | |
1281 | ||
1282 | /* special command to controller BIOS */ | |
1283 | gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]); | |
1284 | gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]); | |
1285 | gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]); | |
1286 | gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]); | |
1287 | gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx); | |
1288 | gdth_writeb(0, &dp6_ptr->io.event); | |
1289 | retries = INIT_RETRIES; | |
1290 | gdth_delay(20); | |
1291 | while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) { | |
1292 | if (--retries == 0) { | |
1293 | printk("GDT-PCI: Initialization error\n"); | |
1294 | iounmap(ha->brd); | |
1295 | return 0; | |
1296 | } | |
1297 | gdth_delay(1); | |
1298 | } | |
1299 | gdth_writeb(0, &dp6_ptr->u.ic.S_Status); | |
1300 | gdth_writeb(0xff, &dp6_ptr->io.irqdel); | |
1301 | ||
1302 | ha->dma64_support = 0; | |
1303 | ||
8e9a8a0d | 1304 | } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */ |
1da177e4 LT |
1305 | ha->plx = (gdt6c_plx_regs *)pcistr->io; |
1306 | TRACE2(("init_pci_new() dpmem %lx irq %d\n", | |
1307 | pcistr->dpmem,ha->irq)); | |
1308 | ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str)); | |
1309 | if (ha->brd == NULL) { | |
1310 | printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); | |
1311 | iounmap(ha->brd); | |
1312 | return 0; | |
1313 | } | |
1314 | /* check and reset interface area */ | |
1315 | dp6c_ptr = ha->brd; | |
1316 | gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u); | |
1317 | if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) { | |
1318 | printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n", | |
1319 | pcistr->dpmem); | |
1320 | found = FALSE; | |
1321 | for (i = 0xC8000; i < 0xE8000; i += 0x4000) { | |
1322 | iounmap(ha->brd); | |
1323 | ha->brd = ioremap(i, sizeof(ushort)); | |
1324 | if (ha->brd == NULL) { | |
1325 | printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); | |
1326 | return 0; | |
1327 | } | |
1328 | if (gdth_readw(ha->brd) != 0xffff) { | |
1329 | TRACE2(("init_pci_plx() address 0x%x busy\n", i)); | |
1330 | continue; | |
1331 | } | |
1332 | iounmap(ha->brd); | |
1333 | pci_write_config_dword(pcistr->pdev, | |
1334 | PCI_BASE_ADDRESS_2, i); | |
1335 | ha->brd = ioremap(i, sizeof(gdt6c_dpram_str)); | |
1336 | if (ha->brd == NULL) { | |
1337 | printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); | |
1338 | return 0; | |
1339 | } | |
1340 | dp6c_ptr = ha->brd; | |
1341 | gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u); | |
1342 | if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) { | |
1343 | printk("GDT-PCI: Use free address at 0x%x\n", i); | |
1344 | found = TRUE; | |
1345 | break; | |
1346 | } | |
1347 | } | |
1348 | if (!found) { | |
1349 | printk("GDT-PCI: No free address found!\n"); | |
1350 | iounmap(ha->brd); | |
1351 | return 0; | |
1352 | } | |
1353 | } | |
1354 | memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u)); | |
1355 | if (gdth_readl(&dp6c_ptr->u) != 0) { | |
1356 | printk("GDT-PCI: Initialization error (DPMEM write error)\n"); | |
1357 | iounmap(ha->brd); | |
1358 | return 0; | |
1359 | } | |
1360 | ||
1361 | /* disable board interrupts, deinit services */ | |
1362 | outb(0x00,PTR2USHORT(&ha->plx->control1)); | |
1363 | outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); | |
1364 | ||
1365 | gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status); | |
1366 | gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index); | |
1367 | ||
1368 | gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]); | |
1369 | gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx); | |
1370 | ||
1371 | outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); | |
1372 | ||
1373 | retries = INIT_RETRIES; | |
1374 | gdth_delay(20); | |
1375 | while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) { | |
1376 | if (--retries == 0) { | |
1377 | printk("GDT-PCI: Initialization error (DEINIT failed)\n"); | |
1378 | iounmap(ha->brd); | |
1379 | return 0; | |
1380 | } | |
1381 | gdth_delay(1); | |
1382 | } | |
1383 | prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]); | |
1384 | gdth_writeb(0, &dp6c_ptr->u.ic.Status); | |
1385 | if (prot_ver != PROTOCOL_VERSION) { | |
1386 | printk("GDT-PCI: Illegal protocol version\n"); | |
1387 | iounmap(ha->brd); | |
1388 | return 0; | |
1389 | } | |
1390 | ||
1391 | ha->type = GDT_PCINEW; | |
1392 | ha->ic_all_size = sizeof(dp6c_ptr->u); | |
1393 | ||
1394 | /* special command to controller BIOS */ | |
1395 | gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]); | |
1396 | gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]); | |
1397 | gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]); | |
1398 | gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]); | |
1399 | gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx); | |
1400 | ||
1401 | outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); | |
1402 | ||
1403 | retries = INIT_RETRIES; | |
1404 | gdth_delay(20); | |
1405 | while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) { | |
1406 | if (--retries == 0) { | |
1407 | printk("GDT-PCI: Initialization error\n"); | |
1408 | iounmap(ha->brd); | |
1409 | return 0; | |
1410 | } | |
1411 | gdth_delay(1); | |
1412 | } | |
1413 | gdth_writeb(0, &dp6c_ptr->u.ic.S_Status); | |
1414 | ||
1415 | ha->dma64_support = 0; | |
1416 | ||
1417 | } else { /* MPR */ | |
1418 | TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq)); | |
1419 | ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str)); | |
1420 | if (ha->brd == NULL) { | |
1421 | printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); | |
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | /* manipulate config. space to enable DPMEM, start RP controller */ | |
1426 | pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command); | |
1427 | command |= 6; | |
1428 | pci_write_config_word(pcistr->pdev, PCI_COMMAND, command); | |
1429 | if (pci_resource_start(pcistr->pdev, 8) == 1UL) | |
1430 | pci_resource_start(pcistr->pdev, 8) = 0UL; | |
1431 | i = 0xFEFF0001UL; | |
1432 | pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i); | |
1433 | gdth_delay(1); | |
1434 | pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, | |
1435 | pci_resource_start(pcistr->pdev, 8)); | |
1436 | ||
1437 | dp6m_ptr = ha->brd; | |
1438 | ||
1439 | /* Ensure that it is safe to access the non HW portions of DPMEM. | |
1440 | * Aditional check needed for Xscale based RAID controllers */ | |
1441 | while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 ) | |
1442 | gdth_delay(1); | |
1443 | ||
1444 | /* check and reset interface area */ | |
1445 | gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u); | |
1446 | if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) { | |
1447 | printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n", | |
1448 | pcistr->dpmem); | |
1449 | found = FALSE; | |
1450 | for (i = 0xC8000; i < 0xE8000; i += 0x4000) { | |
1451 | iounmap(ha->brd); | |
1452 | ha->brd = ioremap(i, sizeof(ushort)); | |
1453 | if (ha->brd == NULL) { | |
1454 | printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); | |
1455 | return 0; | |
1456 | } | |
1457 | if (gdth_readw(ha->brd) != 0xffff) { | |
1458 | TRACE2(("init_pci_mpr() address 0x%x busy\n", i)); | |
1459 | continue; | |
1460 | } | |
1461 | iounmap(ha->brd); | |
1462 | pci_write_config_dword(pcistr->pdev, | |
1463 | PCI_BASE_ADDRESS_0, i); | |
1464 | ha->brd = ioremap(i, sizeof(gdt6m_dpram_str)); | |
1465 | if (ha->brd == NULL) { | |
1466 | printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); | |
1467 | return 0; | |
1468 | } | |
1469 | dp6m_ptr = ha->brd; | |
1470 | gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u); | |
1471 | if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) { | |
1472 | printk("GDT-PCI: Use free address at 0x%x\n", i); | |
1473 | found = TRUE; | |
1474 | break; | |
1475 | } | |
1476 | } | |
1477 | if (!found) { | |
1478 | printk("GDT-PCI: No free address found!\n"); | |
1479 | iounmap(ha->brd); | |
1480 | return 0; | |
1481 | } | |
1482 | } | |
1483 | memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u)); | |
1484 | ||
1485 | /* disable board interrupts, deinit services */ | |
1486 | gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4, | |
1487 | &dp6m_ptr->i960r.edoor_en_reg); | |
1488 | gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg); | |
1489 | gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status); | |
1490 | gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index); | |
1491 | ||
1492 | gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]); | |
1493 | gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx); | |
1494 | gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg); | |
1495 | retries = INIT_RETRIES; | |
1496 | gdth_delay(20); | |
1497 | while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) { | |
1498 | if (--retries == 0) { | |
1499 | printk("GDT-PCI: Initialization error (DEINIT failed)\n"); | |
1500 | iounmap(ha->brd); | |
1501 | return 0; | |
1502 | } | |
1503 | gdth_delay(1); | |
1504 | } | |
1505 | prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]); | |
1506 | gdth_writeb(0, &dp6m_ptr->u.ic.S_Status); | |
1507 | if (prot_ver != PROTOCOL_VERSION) { | |
1508 | printk("GDT-PCI: Illegal protocol version\n"); | |
1509 | iounmap(ha->brd); | |
1510 | return 0; | |
1511 | } | |
1512 | ||
1513 | ha->type = GDT_PCIMPR; | |
1514 | ha->ic_all_size = sizeof(dp6m_ptr->u); | |
1515 | ||
1516 | /* special command to controller BIOS */ | |
1517 | gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]); | |
1518 | gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]); | |
1519 | gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]); | |
1520 | gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]); | |
1521 | gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx); | |
1522 | gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg); | |
1523 | retries = INIT_RETRIES; | |
1524 | gdth_delay(20); | |
1525 | while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) { | |
1526 | if (--retries == 0) { | |
1527 | printk("GDT-PCI: Initialization error\n"); | |
1528 | iounmap(ha->brd); | |
1529 | return 0; | |
1530 | } | |
1531 | gdth_delay(1); | |
1532 | } | |
1533 | gdth_writeb(0, &dp6m_ptr->u.ic.S_Status); | |
1534 | ||
1535 | /* read FW version to detect 64-bit DMA support */ | |
1536 | gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx); | |
1537 | gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg); | |
1538 | retries = INIT_RETRIES; | |
1539 | gdth_delay(20); | |
1540 | while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) { | |
1541 | if (--retries == 0) { | |
1542 | printk("GDT-PCI: Initialization error (DEINIT failed)\n"); | |
1543 | iounmap(ha->brd); | |
1544 | return 0; | |
1545 | } | |
1546 | gdth_delay(1); | |
1547 | } | |
1548 | prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16); | |
1549 | gdth_writeb(0, &dp6m_ptr->u.ic.S_Status); | |
1550 | if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */ | |
1551 | ha->dma64_support = 0; | |
1552 | else | |
1553 | ha->dma64_support = 1; | |
1554 | } | |
1555 | ||
1556 | return 1; | |
1557 | } | |
1558 | ||
1559 | ||
1560 | /* controller protocol functions */ | |
1561 | ||
1562 | static void __init gdth_enable_int(int hanum) | |
1563 | { | |
1564 | gdth_ha_str *ha; | |
1565 | ulong flags; | |
1566 | gdt2_dpram_str __iomem *dp2_ptr; | |
1567 | gdt6_dpram_str __iomem *dp6_ptr; | |
1568 | gdt6m_dpram_str __iomem *dp6m_ptr; | |
1569 | ||
1570 | TRACE(("gdth_enable_int() hanum %d\n",hanum)); | |
1571 | ha = HADATA(gdth_ctr_tab[hanum]); | |
1572 | spin_lock_irqsave(&ha->smp_lock, flags); | |
1573 | ||
1574 | if (ha->type == GDT_EISA) { | |
1575 | outb(0xff, ha->bmic + EDOORREG); | |
1576 | outb(0xff, ha->bmic + EDENABREG); | |
1577 | outb(0x01, ha->bmic + EINTENABREG); | |
1578 | } else if (ha->type == GDT_ISA) { | |
1579 | dp2_ptr = ha->brd; | |
1580 | gdth_writeb(1, &dp2_ptr->io.irqdel); | |
1581 | gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index); | |
1582 | gdth_writeb(1, &dp2_ptr->io.irqen); | |
1583 | } else if (ha->type == GDT_PCI) { | |
1584 | dp6_ptr = ha->brd; | |
1585 | gdth_writeb(1, &dp6_ptr->io.irqdel); | |
1586 | gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index); | |
1587 | gdth_writeb(1, &dp6_ptr->io.irqen); | |
1588 | } else if (ha->type == GDT_PCINEW) { | |
1589 | outb(0xff, PTR2USHORT(&ha->plx->edoor_reg)); | |
1590 | outb(0x03, PTR2USHORT(&ha->plx->control1)); | |
1591 | } else if (ha->type == GDT_PCIMPR) { | |
1592 | dp6m_ptr = ha->brd; | |
1593 | gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg); | |
1594 | gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4, | |
1595 | &dp6m_ptr->i960r.edoor_en_reg); | |
1596 | } | |
1597 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
1598 | } | |
1599 | ||
1600 | ||
1601 | static int gdth_get_status(unchar *pIStatus,int irq) | |
1602 | { | |
1603 | register gdth_ha_str *ha; | |
1604 | int i; | |
1605 | ||
1606 | TRACE(("gdth_get_status() irq %d ctr_count %d\n", | |
1607 | irq,gdth_ctr_count)); | |
1608 | ||
1609 | *pIStatus = 0; | |
1610 | for (i=0; i<gdth_ctr_count; ++i) { | |
1611 | ha = HADATA(gdth_ctr_tab[i]); | |
1612 | if (ha->irq != (unchar)irq) /* check IRQ */ | |
1613 | continue; | |
1614 | if (ha->type == GDT_EISA) | |
1615 | *pIStatus = inb((ushort)ha->bmic + EDOORREG); | |
1616 | else if (ha->type == GDT_ISA) | |
1617 | *pIStatus = | |
1618 | gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index); | |
1619 | else if (ha->type == GDT_PCI) | |
1620 | *pIStatus = | |
1621 | gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index); | |
1622 | else if (ha->type == GDT_PCINEW) | |
1623 | *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg)); | |
1624 | else if (ha->type == GDT_PCIMPR) | |
1625 | *pIStatus = | |
1626 | gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg); | |
1627 | ||
1628 | if (*pIStatus) | |
1629 | return i; /* board found */ | |
1630 | } | |
1631 | return -1; | |
1632 | } | |
1633 | ||
1634 | ||
1635 | static int gdth_test_busy(int hanum) | |
1636 | { | |
1637 | register gdth_ha_str *ha; | |
1638 | register int gdtsema0 = 0; | |
1639 | ||
1640 | TRACE(("gdth_test_busy() hanum %d\n",hanum)); | |
1641 | ||
1642 | ha = HADATA(gdth_ctr_tab[hanum]); | |
1643 | if (ha->type == GDT_EISA) | |
1644 | gdtsema0 = (int)inb(ha->bmic + SEMA0REG); | |
1645 | else if (ha->type == GDT_ISA) | |
1646 | gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0); | |
1647 | else if (ha->type == GDT_PCI) | |
1648 | gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0); | |
1649 | else if (ha->type == GDT_PCINEW) | |
1650 | gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg)); | |
1651 | else if (ha->type == GDT_PCIMPR) | |
1652 | gdtsema0 = | |
1653 | (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg); | |
1654 | ||
1655 | return (gdtsema0 & 1); | |
1656 | } | |
1657 | ||
1658 | ||
1659 | static int gdth_get_cmd_index(int hanum) | |
1660 | { | |
1661 | register gdth_ha_str *ha; | |
1662 | int i; | |
1663 | ||
1664 | TRACE(("gdth_get_cmd_index() hanum %d\n",hanum)); | |
1665 | ||
1666 | ha = HADATA(gdth_ctr_tab[hanum]); | |
1667 | for (i=0; i<GDTH_MAXCMDS; ++i) { | |
1668 | if (ha->cmd_tab[i].cmnd == UNUSED_CMND) { | |
1669 | ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer; | |
1670 | ha->cmd_tab[i].service = ha->pccb->Service; | |
1671 | ha->pccb->CommandIndex = (ulong32)i+2; | |
1672 | return (i+2); | |
1673 | } | |
1674 | } | |
1675 | return 0; | |
1676 | } | |
1677 | ||
1678 | ||
1679 | static void gdth_set_sema0(int hanum) | |
1680 | { | |
1681 | register gdth_ha_str *ha; | |
1682 | ||
1683 | TRACE(("gdth_set_sema0() hanum %d\n",hanum)); | |
1684 | ||
1685 | ha = HADATA(gdth_ctr_tab[hanum]); | |
1686 | if (ha->type == GDT_EISA) { | |
1687 | outb(1, ha->bmic + SEMA0REG); | |
1688 | } else if (ha->type == GDT_ISA) { | |
1689 | gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0); | |
1690 | } else if (ha->type == GDT_PCI) { | |
1691 | gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0); | |
1692 | } else if (ha->type == GDT_PCINEW) { | |
1693 | outb(1, PTR2USHORT(&ha->plx->sema0_reg)); | |
1694 | } else if (ha->type == GDT_PCIMPR) { | |
1695 | gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg); | |
1696 | } | |
1697 | } | |
1698 | ||
1699 | ||
1700 | static void gdth_copy_command(int hanum) | |
1701 | { | |
1702 | register gdth_ha_str *ha; | |
1703 | register gdth_cmd_str *cmd_ptr; | |
1704 | register gdt6m_dpram_str __iomem *dp6m_ptr; | |
1705 | register gdt6c_dpram_str __iomem *dp6c_ptr; | |
1706 | gdt6_dpram_str __iomem *dp6_ptr; | |
1707 | gdt2_dpram_str __iomem *dp2_ptr; | |
1708 | ushort cp_count,dp_offset,cmd_no; | |
1709 | ||
1710 | TRACE(("gdth_copy_command() hanum %d\n",hanum)); | |
1711 | ||
1712 | ha = HADATA(gdth_ctr_tab[hanum]); | |
1713 | cp_count = ha->cmd_len; | |
1714 | dp_offset= ha->cmd_offs_dpmem; | |
1715 | cmd_no = ha->cmd_cnt; | |
1716 | cmd_ptr = ha->pccb; | |
1717 | ||
1718 | ++ha->cmd_cnt; | |
1719 | if (ha->type == GDT_EISA) | |
1720 | return; /* no DPMEM, no copy */ | |
1721 | ||
1722 | /* set cpcount dword aligned */ | |
1723 | if (cp_count & 3) | |
1724 | cp_count += (4 - (cp_count & 3)); | |
1725 | ||
1726 | ha->cmd_offs_dpmem += cp_count; | |
1727 | ||
1728 | /* set offset and service, copy command to DPMEM */ | |
1729 | if (ha->type == GDT_ISA) { | |
1730 | dp2_ptr = ha->brd; | |
1731 | gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET, | |
1732 | &dp2_ptr->u.ic.comm_queue[cmd_no].offset); | |
1733 | gdth_writew((ushort)cmd_ptr->Service, | |
1734 | &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id); | |
1735 | memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count); | |
1736 | } else if (ha->type == GDT_PCI) { | |
1737 | dp6_ptr = ha->brd; | |
1738 | gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET, | |
1739 | &dp6_ptr->u.ic.comm_queue[cmd_no].offset); | |
1740 | gdth_writew((ushort)cmd_ptr->Service, | |
1741 | &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id); | |
1742 | memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count); | |
1743 | } else if (ha->type == GDT_PCINEW) { | |
1744 | dp6c_ptr = ha->brd; | |
1745 | gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET, | |
1746 | &dp6c_ptr->u.ic.comm_queue[cmd_no].offset); | |
1747 | gdth_writew((ushort)cmd_ptr->Service, | |
1748 | &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id); | |
1749 | memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count); | |
1750 | } else if (ha->type == GDT_PCIMPR) { | |
1751 | dp6m_ptr = ha->brd; | |
1752 | gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET, | |
1753 | &dp6m_ptr->u.ic.comm_queue[cmd_no].offset); | |
1754 | gdth_writew((ushort)cmd_ptr->Service, | |
1755 | &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id); | |
1756 | memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count); | |
1757 | } | |
1758 | } | |
1759 | ||
1760 | ||
1761 | static void gdth_release_event(int hanum) | |
1762 | { | |
1763 | register gdth_ha_str *ha; | |
1764 | ||
1765 | TRACE(("gdth_release_event() hanum %d\n",hanum)); | |
1766 | ha = HADATA(gdth_ctr_tab[hanum]); | |
1767 | ||
1768 | #ifdef GDTH_STATISTICS | |
1769 | { | |
1770 | ulong32 i,j; | |
1771 | for (i=0,j=0; j<GDTH_MAXCMDS; ++j) { | |
1772 | if (ha->cmd_tab[j].cmnd != UNUSED_CMND) | |
1773 | ++i; | |
1774 | } | |
1775 | if (max_index < i) { | |
1776 | max_index = i; | |
1777 | TRACE3(("GDT: max_index = %d\n",(ushort)i)); | |
1778 | } | |
1779 | } | |
1780 | #endif | |
1781 | ||
1782 | if (ha->pccb->OpCode == GDT_INIT) | |
1783 | ha->pccb->Service |= 0x80; | |
1784 | ||
1785 | if (ha->type == GDT_EISA) { | |
1786 | if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */ | |
1787 | outl(ha->ccb_phys, ha->bmic + MAILBOXREG); | |
1788 | outb(ha->pccb->Service, ha->bmic + LDOORREG); | |
1789 | } else if (ha->type == GDT_ISA) { | |
1790 | gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event); | |
1791 | } else if (ha->type == GDT_PCI) { | |
1792 | gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event); | |
1793 | } else if (ha->type == GDT_PCINEW) { | |
1794 | outb(1, PTR2USHORT(&ha->plx->ldoor_reg)); | |
1795 | } else if (ha->type == GDT_PCIMPR) { | |
1796 | gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg); | |
1797 | } | |
1798 | } | |
1799 | ||
1800 | ||
1801 | static int gdth_wait(int hanum,int index,ulong32 time) | |
1802 | { | |
1803 | gdth_ha_str *ha; | |
1804 | int answer_found = FALSE; | |
1805 | ||
1806 | TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time)); | |
1807 | ||
1808 | ha = HADATA(gdth_ctr_tab[hanum]); | |
1809 | if (index == 0) | |
1810 | return 1; /* no wait required */ | |
1811 | ||
1812 | gdth_from_wait = TRUE; | |
1813 | do { | |
7d12e780 | 1814 | gdth_interrupt((int)ha->irq,ha); |
1da177e4 LT |
1815 | if (wait_hanum==hanum && wait_index==index) { |
1816 | answer_found = TRUE; | |
1817 | break; | |
1818 | } | |
1819 | gdth_delay(1); | |
1820 | } while (--time); | |
1821 | gdth_from_wait = FALSE; | |
1822 | ||
1823 | while (gdth_test_busy(hanum)) | |
1824 | gdth_delay(0); | |
1825 | ||
1826 | return (answer_found); | |
1827 | } | |
1828 | ||
1829 | ||
1830 | static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1, | |
1831 | ulong64 p2,ulong64 p3) | |
1832 | { | |
1833 | register gdth_ha_str *ha; | |
1834 | register gdth_cmd_str *cmd_ptr; | |
1835 | int retries,index; | |
1836 | ||
1837 | TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode)); | |
1838 | ||
1839 | ha = HADATA(gdth_ctr_tab[hanum]); | |
1840 | cmd_ptr = ha->pccb; | |
1841 | memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str)); | |
1842 | ||
1843 | /* make command */ | |
1844 | for (retries = INIT_RETRIES;;) { | |
1845 | cmd_ptr->Service = service; | |
1846 | cmd_ptr->RequestBuffer = INTERNAL_CMND; | |
1847 | if (!(index=gdth_get_cmd_index(hanum))) { | |
1848 | TRACE(("GDT: No free command index found\n")); | |
1849 | return 0; | |
1850 | } | |
1851 | gdth_set_sema0(hanum); | |
1852 | cmd_ptr->OpCode = opcode; | |
1853 | cmd_ptr->BoardNode = LOCALBOARD; | |
1854 | if (service == CACHESERVICE) { | |
1855 | if (opcode == GDT_IOCTL) { | |
1856 | cmd_ptr->u.ioctl.subfunc = p1; | |
1857 | cmd_ptr->u.ioctl.channel = (ulong32)p2; | |
1858 | cmd_ptr->u.ioctl.param_size = (ushort)p3; | |
1859 | cmd_ptr->u.ioctl.p_param = ha->scratch_phys; | |
1860 | } else { | |
1861 | if (ha->cache_feat & GDT_64BIT) { | |
1862 | cmd_ptr->u.cache64.DeviceNo = (ushort)p1; | |
1863 | cmd_ptr->u.cache64.BlockNo = p2; | |
1864 | } else { | |
1865 | cmd_ptr->u.cache.DeviceNo = (ushort)p1; | |
1866 | cmd_ptr->u.cache.BlockNo = (ulong32)p2; | |
1867 | } | |
1868 | } | |
1869 | } else if (service == SCSIRAWSERVICE) { | |
1870 | if (ha->raw_feat & GDT_64BIT) { | |
1871 | cmd_ptr->u.raw64.direction = p1; | |
1872 | cmd_ptr->u.raw64.bus = (unchar)p2; | |
1873 | cmd_ptr->u.raw64.target = (unchar)p3; | |
1874 | cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8); | |
1875 | } else { | |
1876 | cmd_ptr->u.raw.direction = p1; | |
1877 | cmd_ptr->u.raw.bus = (unchar)p2; | |
1878 | cmd_ptr->u.raw.target = (unchar)p3; | |
1879 | cmd_ptr->u.raw.lun = (unchar)(p3 >> 8); | |
1880 | } | |
1881 | } else if (service == SCREENSERVICE) { | |
1882 | if (opcode == GDT_REALTIME) { | |
1883 | *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1; | |
1884 | *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2; | |
1885 | *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3; | |
1886 | } | |
1887 | } | |
1888 | ha->cmd_len = sizeof(gdth_cmd_str); | |
1889 | ha->cmd_offs_dpmem = 0; | |
1890 | ha->cmd_cnt = 0; | |
1891 | gdth_copy_command(hanum); | |
1892 | gdth_release_event(hanum); | |
1893 | gdth_delay(20); | |
1894 | if (!gdth_wait(hanum,index,INIT_TIMEOUT)) { | |
1895 | printk("GDT: Initialization error (timeout service %d)\n",service); | |
1896 | return 0; | |
1897 | } | |
1898 | if (ha->status != S_BSY || --retries == 0) | |
1899 | break; | |
1900 | gdth_delay(1); | |
1901 | } | |
1902 | ||
1903 | return (ha->status != S_OK ? 0:1); | |
1904 | } | |
1905 | ||
1906 | ||
1907 | /* search for devices */ | |
1908 | ||
1909 | static int __init gdth_search_drives(int hanum) | |
1910 | { | |
1911 | register gdth_ha_str *ha; | |
1912 | ushort cdev_cnt, i; | |
1913 | int ok; | |
1914 | ulong32 bus_no, drv_cnt, drv_no, j; | |
1915 | gdth_getch_str *chn; | |
1916 | gdth_drlist_str *drl; | |
1917 | gdth_iochan_str *ioc; | |
1918 | gdth_raw_iochan_str *iocr; | |
1919 | gdth_arcdl_str *alst; | |
1920 | gdth_alist_str *alst2; | |
1921 | gdth_oem_str_ioctl *oemstr; | |
1922 | #ifdef INT_COAL | |
1923 | gdth_perf_modes *pmod; | |
1924 | #endif | |
1925 | ||
1926 | #ifdef GDTH_RTC | |
1927 | unchar rtc[12]; | |
1928 | ulong flags; | |
1929 | #endif | |
1930 | ||
1931 | TRACE(("gdth_search_drives() hanum %d\n",hanum)); | |
1932 | ha = HADATA(gdth_ctr_tab[hanum]); | |
1933 | ok = 0; | |
1934 | ||
1935 | /* initialize controller services, at first: screen service */ | |
1936 | ha->screen_feat = 0; | |
1937 | if (!force_dma32) { | |
1938 | ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0); | |
1939 | if (ok) | |
1940 | ha->screen_feat = GDT_64BIT; | |
1941 | } | |
1942 | if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC)) | |
1943 | ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0); | |
1944 | if (!ok) { | |
1945 | printk("GDT-HA %d: Initialization error screen service (code %d)\n", | |
1946 | hanum, ha->status); | |
1947 | return 0; | |
1948 | } | |
1949 | TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n")); | |
1950 | ||
1951 | #ifdef GDTH_RTC | |
1952 | /* read realtime clock info, send to controller */ | |
1953 | /* 1. wait for the falling edge of update flag */ | |
1954 | spin_lock_irqsave(&rtc_lock, flags); | |
1955 | for (j = 0; j < 1000000; ++j) | |
1956 | if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) | |
1957 | break; | |
1958 | for (j = 0; j < 1000000; ++j) | |
1959 | if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)) | |
1960 | break; | |
1961 | /* 2. read info */ | |
1962 | do { | |
1963 | for (j = 0; j < 12; ++j) | |
1964 | rtc[j] = CMOS_READ(j); | |
1965 | } while (rtc[0] != CMOS_READ(0)); | |
7a960b76 | 1966 | spin_unlock_irqrestore(&rtc_lock, flags); |
1da177e4 LT |
1967 | TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0], |
1968 | *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8])); | |
1969 | /* 3. send to controller firmware */ | |
1970 | gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0], | |
1971 | *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]); | |
1972 | #endif | |
1973 | ||
1974 | /* unfreeze all IOs */ | |
1975 | gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0); | |
1976 | ||
1977 | /* initialize cache service */ | |
1978 | ha->cache_feat = 0; | |
1979 | if (!force_dma32) { | |
1980 | ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0); | |
1981 | if (ok) | |
1982 | ha->cache_feat = GDT_64BIT; | |
1983 | } | |
1984 | if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC)) | |
1985 | ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0); | |
1986 | if (!ok) { | |
1987 | printk("GDT-HA %d: Initialization error cache service (code %d)\n", | |
1988 | hanum, ha->status); | |
1989 | return 0; | |
1990 | } | |
1991 | TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n")); | |
1992 | cdev_cnt = (ushort)ha->info; | |
1993 | ha->fw_vers = ha->service; | |
1994 | ||
1995 | #ifdef INT_COAL | |
1996 | if (ha->type == GDT_PCIMPR) { | |
1997 | /* set perf. modes */ | |
1998 | pmod = (gdth_perf_modes *)ha->pscratch; | |
1999 | pmod->version = 1; | |
2000 | pmod->st_mode = 1; /* enable one status buffer */ | |
2001 | *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys; | |
2002 | pmod->st_buff_indx1 = COALINDEX; | |
2003 | pmod->st_buff_addr2 = 0; | |
2004 | pmod->st_buff_u_addr2 = 0; | |
2005 | pmod->st_buff_indx2 = 0; | |
2006 | pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS; | |
2007 | pmod->cmd_mode = 0; // disable all cmd buffers | |
2008 | pmod->cmd_buff_addr1 = 0; | |
2009 | pmod->cmd_buff_u_addr1 = 0; | |
2010 | pmod->cmd_buff_indx1 = 0; | |
2011 | pmod->cmd_buff_addr2 = 0; | |
2012 | pmod->cmd_buff_u_addr2 = 0; | |
2013 | pmod->cmd_buff_indx2 = 0; | |
2014 | pmod->cmd_buff_size = 0; | |
2015 | pmod->reserved1 = 0; | |
2016 | pmod->reserved2 = 0; | |
2017 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES, | |
2018 | INVALID_CHANNEL,sizeof(gdth_perf_modes))) { | |
2019 | printk("GDT-HA %d: Interrupt coalescing activated\n", hanum); | |
2020 | } | |
2021 | } | |
2022 | #endif | |
2023 | ||
2024 | /* detect number of buses - try new IOCTL */ | |
2025 | iocr = (gdth_raw_iochan_str *)ha->pscratch; | |
2026 | iocr->hdr.version = 0xffffffff; | |
2027 | iocr->hdr.list_entries = MAXBUS; | |
2028 | iocr->hdr.first_chan = 0; | |
2029 | iocr->hdr.last_chan = MAXBUS-1; | |
2030 | iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]); | |
2031 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC, | |
2032 | INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) { | |
2033 | TRACE2(("IOCHAN_RAW_DESC supported!\n")); | |
2034 | ha->bus_cnt = iocr->hdr.chan_count; | |
2035 | for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) { | |
2036 | if (iocr->list[bus_no].proc_id < MAXID) | |
2037 | ha->bus_id[bus_no] = iocr->list[bus_no].proc_id; | |
2038 | else | |
2039 | ha->bus_id[bus_no] = 0xff; | |
2040 | } | |
2041 | } else { | |
2042 | /* old method */ | |
2043 | chn = (gdth_getch_str *)ha->pscratch; | |
2044 | for (bus_no = 0; bus_no < MAXBUS; ++bus_no) { | |
2045 | chn->channel_no = bus_no; | |
2046 | if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL, | |
2047 | SCSI_CHAN_CNT | L_CTRL_PATTERN, | |
2048 | IO_CHANNEL | INVALID_CHANNEL, | |
2049 | sizeof(gdth_getch_str))) { | |
2050 | if (bus_no == 0) { | |
2051 | printk("GDT-HA %d: Error detecting channel count (0x%x)\n", | |
2052 | hanum, ha->status); | |
2053 | return 0; | |
2054 | } | |
2055 | break; | |
2056 | } | |
2057 | if (chn->siop_id < MAXID) | |
2058 | ha->bus_id[bus_no] = chn->siop_id; | |
2059 | else | |
2060 | ha->bus_id[bus_no] = 0xff; | |
2061 | } | |
2062 | ha->bus_cnt = (unchar)bus_no; | |
2063 | } | |
2064 | TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt)); | |
2065 | ||
2066 | /* read cache configuration */ | |
2067 | if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO, | |
2068 | INVALID_CHANNEL,sizeof(gdth_cinfo_str))) { | |
2069 | printk("GDT-HA %d: Initialization error cache service (code %d)\n", | |
2070 | hanum, ha->status); | |
2071 | return 0; | |
2072 | } | |
2073 | ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar; | |
2074 | TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n", | |
2075 | ha->cpar.version,ha->cpar.state,ha->cpar.strategy, | |
2076 | ha->cpar.write_back,ha->cpar.block_size)); | |
2077 | ||
2078 | /* read board info and features */ | |
2079 | ha->more_proc = FALSE; | |
2080 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO, | |
2081 | INVALID_CHANNEL,sizeof(gdth_binfo_str))) { | |
2082 | memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch, | |
2083 | sizeof(gdth_binfo_str)); | |
2084 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES, | |
2085 | INVALID_CHANNEL,sizeof(gdth_bfeat_str))) { | |
2086 | TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n")); | |
2087 | ha->bfeat = *(gdth_bfeat_str *)ha->pscratch; | |
2088 | ha->more_proc = TRUE; | |
2089 | } | |
2090 | } else { | |
2091 | TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n")); | |
2092 | strcpy(ha->binfo.type_string, gdth_ctr_name(hanum)); | |
2093 | } | |
2094 | TRACE2(("Controller name: %s\n",ha->binfo.type_string)); | |
2095 | ||
2096 | /* read more informations */ | |
2097 | if (ha->more_proc) { | |
2098 | /* physical drives, channel addresses */ | |
2099 | ioc = (gdth_iochan_str *)ha->pscratch; | |
2100 | ioc->hdr.version = 0xffffffff; | |
2101 | ioc->hdr.list_entries = MAXBUS; | |
2102 | ioc->hdr.first_chan = 0; | |
2103 | ioc->hdr.last_chan = MAXBUS-1; | |
2104 | ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]); | |
2105 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC, | |
2106 | INVALID_CHANNEL,sizeof(gdth_iochan_str))) { | |
2107 | for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) { | |
2108 | ha->raw[bus_no].address = ioc->list[bus_no].address; | |
2109 | ha->raw[bus_no].local_no = ioc->list[bus_no].local_no; | |
2110 | } | |
2111 | } else { | |
2112 | for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) { | |
2113 | ha->raw[bus_no].address = IO_CHANNEL; | |
2114 | ha->raw[bus_no].local_no = bus_no; | |
2115 | } | |
2116 | } | |
2117 | for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) { | |
2118 | chn = (gdth_getch_str *)ha->pscratch; | |
2119 | chn->channel_no = ha->raw[bus_no].local_no; | |
2120 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL, | |
2121 | SCSI_CHAN_CNT | L_CTRL_PATTERN, | |
2122 | ha->raw[bus_no].address | INVALID_CHANNEL, | |
2123 | sizeof(gdth_getch_str))) { | |
2124 | ha->raw[bus_no].pdev_cnt = chn->drive_cnt; | |
2125 | TRACE2(("Channel %d: %d phys. drives\n", | |
2126 | bus_no,chn->drive_cnt)); | |
2127 | } | |
2128 | if (ha->raw[bus_no].pdev_cnt > 0) { | |
2129 | drl = (gdth_drlist_str *)ha->pscratch; | |
2130 | drl->sc_no = ha->raw[bus_no].local_no; | |
2131 | drl->sc_cnt = ha->raw[bus_no].pdev_cnt; | |
2132 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL, | |
2133 | SCSI_DR_LIST | L_CTRL_PATTERN, | |
2134 | ha->raw[bus_no].address | INVALID_CHANNEL, | |
2135 | sizeof(gdth_drlist_str))) { | |
2136 | for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j) | |
2137 | ha->raw[bus_no].id_list[j] = drl->sc_list[j]; | |
2138 | } else { | |
2139 | ha->raw[bus_no].pdev_cnt = 0; | |
2140 | } | |
2141 | } | |
2142 | } | |
2143 | ||
2144 | /* logical drives */ | |
2145 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT, | |
2146 | INVALID_CHANNEL,sizeof(ulong32))) { | |
2147 | drv_cnt = *(ulong32 *)ha->pscratch; | |
2148 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST, | |
2149 | INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) { | |
2150 | for (j = 0; j < drv_cnt; ++j) { | |
2151 | drv_no = ((ulong32 *)ha->pscratch)[j]; | |
2152 | if (drv_no < MAX_LDRIVES) { | |
2153 | ha->hdr[drv_no].is_logdrv = TRUE; | |
2154 | TRACE2(("Drive %d is log. drive\n",drv_no)); | |
2155 | } | |
2156 | } | |
2157 | } | |
2158 | alst = (gdth_arcdl_str *)ha->pscratch; | |
2159 | alst->entries_avail = MAX_LDRIVES; | |
2160 | alst->first_entry = 0; | |
2161 | alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]); | |
2162 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL, | |
2163 | ARRAY_DRV_LIST2 | LA_CTRL_PATTERN, | |
2164 | INVALID_CHANNEL, sizeof(gdth_arcdl_str) + | |
2165 | (alst->entries_avail-1) * sizeof(gdth_alist_str))) { | |
2166 | for (j = 0; j < alst->entries_init; ++j) { | |
2167 | ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd; | |
2168 | ha->hdr[j].is_master = alst->list[j].is_master; | |
2169 | ha->hdr[j].is_parity = alst->list[j].is_parity; | |
2170 | ha->hdr[j].is_hotfix = alst->list[j].is_hotfix; | |
2171 | ha->hdr[j].master_no = alst->list[j].cd_handle; | |
2172 | } | |
2173 | } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL, | |
2174 | ARRAY_DRV_LIST | LA_CTRL_PATTERN, | |
2175 | 0, 35 * sizeof(gdth_alist_str))) { | |
2176 | for (j = 0; j < 35; ++j) { | |
2177 | alst2 = &((gdth_alist_str *)ha->pscratch)[j]; | |
2178 | ha->hdr[j].is_arraydrv = alst2->is_arrayd; | |
2179 | ha->hdr[j].is_master = alst2->is_master; | |
2180 | ha->hdr[j].is_parity = alst2->is_parity; | |
2181 | ha->hdr[j].is_hotfix = alst2->is_hotfix; | |
2182 | ha->hdr[j].master_no = alst2->cd_handle; | |
2183 | } | |
2184 | } | |
2185 | } | |
2186 | } | |
2187 | ||
2188 | /* initialize raw service */ | |
2189 | ha->raw_feat = 0; | |
2190 | if (!force_dma32) { | |
2191 | ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0); | |
2192 | if (ok) | |
2193 | ha->raw_feat = GDT_64BIT; | |
2194 | } | |
2195 | if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC)) | |
2196 | ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0); | |
2197 | if (!ok) { | |
2198 | printk("GDT-HA %d: Initialization error raw service (code %d)\n", | |
2199 | hanum, ha->status); | |
2200 | return 0; | |
2201 | } | |
2202 | TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n")); | |
2203 | ||
2204 | /* set/get features raw service (scatter/gather) */ | |
2205 | if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER, | |
2206 | 0,0)) { | |
2207 | TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n")); | |
2208 | if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) { | |
2209 | TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n", | |
2210 | ha->info)); | |
2211 | ha->raw_feat |= (ushort)ha->info; | |
2212 | } | |
2213 | } | |
2214 | ||
2215 | /* set/get features cache service (equal to raw service) */ | |
2216 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0, | |
2217 | SCATTER_GATHER,0)) { | |
2218 | TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n")); | |
2219 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) { | |
2220 | TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n", | |
2221 | ha->info)); | |
2222 | ha->cache_feat |= (ushort)ha->info; | |
2223 | } | |
2224 | } | |
2225 | ||
2226 | /* reserve drives for raw service */ | |
2227 | if (reserve_mode != 0) { | |
2228 | gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL, | |
2229 | reserve_mode == 1 ? 1 : 3, 0, 0); | |
2230 | TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n", | |
2231 | ha->status)); | |
2232 | } | |
2233 | for (i = 0; i < MAX_RES_ARGS; i += 4) { | |
2234 | if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt && | |
2235 | reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) { | |
2236 | TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n", | |
2237 | reserve_list[i], reserve_list[i+1], | |
2238 | reserve_list[i+2], reserve_list[i+3])); | |
2239 | if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0, | |
2240 | reserve_list[i+1], reserve_list[i+2] | | |
2241 | (reserve_list[i+3] << 8))) { | |
2242 | printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n", | |
2243 | hanum, ha->status); | |
2244 | } | |
2245 | } | |
2246 | } | |
2247 | ||
2248 | /* Determine OEM string using IOCTL */ | |
2249 | oemstr = (gdth_oem_str_ioctl *)ha->pscratch; | |
2250 | oemstr->params.ctl_version = 0x01; | |
2251 | oemstr->params.buffer_size = sizeof(oemstr->text); | |
2252 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL, | |
2253 | CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL, | |
2254 | sizeof(gdth_oem_str_ioctl))) { | |
2255 | TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n")); | |
2256 | printk("GDT-HA %d: Vendor: %s Name: %s\n", | |
2257 | hanum,oemstr->text.oem_company_name,ha->binfo.type_string); | |
2258 | /* Save the Host Drive inquiry data */ | |
2259 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) | |
2260 | strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id, | |
2261 | sizeof(ha->oem_name)); | |
2262 | #else | |
2263 | strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7); | |
2264 | ha->oem_name[7] = '\0'; | |
2265 | #endif | |
2266 | } else { | |
2267 | /* Old method, based on PCI ID */ | |
2268 | TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n")); | |
2269 | printk("GDT-HA %d: Name: %s\n", | |
2270 | hanum,ha->binfo.type_string); | |
2271 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) | |
2272 | if (ha->oem_id == OEM_ID_INTEL) | |
2273 | strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name)); | |
2274 | else | |
2275 | strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name)); | |
2276 | #else | |
2277 | if (ha->oem_id == OEM_ID_INTEL) | |
2278 | strcpy(ha->oem_name,"Intel "); | |
2279 | else | |
2280 | strcpy(ha->oem_name,"ICP "); | |
2281 | #endif | |
2282 | } | |
2283 | ||
2284 | /* scanning for host drives */ | |
2285 | for (i = 0; i < cdev_cnt; ++i) | |
2286 | gdth_analyse_hdrive(hanum,i); | |
2287 | ||
2288 | TRACE(("gdth_search_drives() OK\n")); | |
2289 | return 1; | |
2290 | } | |
2291 | ||
2292 | static int gdth_analyse_hdrive(int hanum,ushort hdrive) | |
2293 | { | |
2294 | register gdth_ha_str *ha; | |
2295 | ulong32 drv_cyls; | |
2296 | int drv_hds, drv_secs; | |
2297 | ||
2298 | TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive)); | |
2299 | if (hdrive >= MAX_HDRIVES) | |
2300 | return 0; | |
2301 | ha = HADATA(gdth_ctr_tab[hanum]); | |
2302 | ||
2303 | if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0)) | |
2304 | return 0; | |
2305 | ha->hdr[hdrive].present = TRUE; | |
2306 | ha->hdr[hdrive].size = ha->info; | |
2307 | ||
2308 | /* evaluate mapping (sectors per head, heads per cylinder) */ | |
2309 | ha->hdr[hdrive].size &= ~SECS32; | |
2310 | if (ha->info2 == 0) { | |
2311 | gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs); | |
2312 | } else { | |
2313 | drv_hds = ha->info2 & 0xff; | |
2314 | drv_secs = (ha->info2 >> 8) & 0xff; | |
2315 | drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs; | |
2316 | } | |
2317 | ha->hdr[hdrive].heads = (unchar)drv_hds; | |
2318 | ha->hdr[hdrive].secs = (unchar)drv_secs; | |
2319 | /* round size */ | |
2320 | ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs; | |
2321 | ||
2322 | if (ha->cache_feat & GDT_64BIT) { | |
2323 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0) | |
2324 | && ha->info2 != 0) { | |
2325 | ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info; | |
2326 | } | |
2327 | } | |
2328 | TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n", | |
2329 | hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs)); | |
2330 | ||
2331 | /* get informations about device */ | |
2332 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) { | |
2333 | TRACE2(("gdth_search_dr() cache drive %d devtype %d\n", | |
2334 | hdrive,ha->info)); | |
2335 | ha->hdr[hdrive].devtype = (ushort)ha->info; | |
2336 | } | |
2337 | ||
2338 | /* cluster info */ | |
2339 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) { | |
2340 | TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n", | |
2341 | hdrive,ha->info)); | |
2342 | if (!shared_access) | |
2343 | ha->hdr[hdrive].cluster_type = (unchar)ha->info; | |
2344 | } | |
2345 | ||
2346 | /* R/W attributes */ | |
2347 | if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) { | |
2348 | TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n", | |
2349 | hdrive,ha->info)); | |
2350 | ha->hdr[hdrive].rw_attribs = (unchar)ha->info; | |
2351 | } | |
2352 | ||
2353 | return 1; | |
2354 | } | |
2355 | ||
2356 | ||
2357 | /* command queueing/sending functions */ | |
2358 | ||
2359 | static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority) | |
2360 | { | |
2361 | register gdth_ha_str *ha; | |
2362 | register Scsi_Cmnd *pscp; | |
2363 | register Scsi_Cmnd *nscp; | |
2364 | ulong flags; | |
2365 | unchar b, t; | |
2366 | ||
2367 | TRACE(("gdth_putq() priority %d\n",priority)); | |
2368 | ha = HADATA(gdth_ctr_tab[hanum]); | |
2369 | spin_lock_irqsave(&ha->smp_lock, flags); | |
2370 | ||
687d2bc4 | 2371 | if (!IS_GDTH_INTERNAL_CMD(scp)) { |
cbd5f69b LA |
2372 | scp->SCp.this_residual = (int)priority; |
2373 | b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel; | |
2374 | t = scp->device->id; | |
2375 | if (priority >= DEFAULT_PRI) { | |
2376 | if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) || | |
2377 | (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) { | |
2378 | TRACE2(("gdth_putq(): locked IO ->update_timeout()\n")); | |
2379 | scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0); | |
2380 | } | |
1da177e4 LT |
2381 | } |
2382 | } | |
2383 | ||
2384 | if (ha->req_first==NULL) { | |
2385 | ha->req_first = scp; /* queue was empty */ | |
2386 | scp->SCp.ptr = NULL; | |
2387 | } else { /* queue not empty */ | |
2388 | pscp = ha->req_first; | |
2389 | nscp = (Scsi_Cmnd *)pscp->SCp.ptr; | |
2390 | /* priority: 0-highest,..,0xff-lowest */ | |
2391 | while (nscp && (unchar)nscp->SCp.this_residual <= priority) { | |
2392 | pscp = nscp; | |
2393 | nscp = (Scsi_Cmnd *)pscp->SCp.ptr; | |
2394 | } | |
2395 | pscp->SCp.ptr = (char *)scp; | |
2396 | scp->SCp.ptr = (char *)nscp; | |
2397 | } | |
2398 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
2399 | ||
2400 | #ifdef GDTH_STATISTICS | |
2401 | flags = 0; | |
2402 | for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr) | |
2403 | ++flags; | |
2404 | if (max_rq < flags) { | |
2405 | max_rq = flags; | |
2406 | TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq)); | |
2407 | } | |
2408 | #endif | |
2409 | } | |
2410 | ||
2411 | static void gdth_next(int hanum) | |
2412 | { | |
2413 | register gdth_ha_str *ha; | |
2414 | register Scsi_Cmnd *pscp; | |
2415 | register Scsi_Cmnd *nscp; | |
2416 | unchar b, t, l, firsttime; | |
2417 | unchar this_cmd, next_cmd; | |
2418 | ulong flags = 0; | |
2419 | int cmd_index; | |
2420 | ||
2421 | TRACE(("gdth_next() hanum %d\n",hanum)); | |
2422 | ha = HADATA(gdth_ctr_tab[hanum]); | |
2423 | if (!gdth_polling) | |
2424 | spin_lock_irqsave(&ha->smp_lock, flags); | |
2425 | ||
2426 | ha->cmd_cnt = ha->cmd_offs_dpmem = 0; | |
2427 | this_cmd = firsttime = TRUE; | |
2428 | next_cmd = gdth_polling ? FALSE:TRUE; | |
2429 | cmd_index = 0; | |
2430 | ||
2431 | for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) { | |
2432 | if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr) | |
2433 | pscp = (Scsi_Cmnd *)pscp->SCp.ptr; | |
687d2bc4 | 2434 | if (!IS_GDTH_INTERNAL_CMD(nscp)) { |
cbd5f69b LA |
2435 | b = virt_ctr ? |
2436 | NUMDATA(nscp->device->host)->busnum : nscp->device->channel; | |
2437 | t = nscp->device->id; | |
2438 | l = nscp->device->lun; | |
2439 | if (nscp->SCp.this_residual >= DEFAULT_PRI) { | |
2440 | if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) || | |
2441 | (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock)) | |
2442 | continue; | |
2443 | } | |
2444 | } else | |
2445 | b = t = l = 0; | |
1da177e4 LT |
2446 | |
2447 | if (firsttime) { | |
2448 | if (gdth_test_busy(hanum)) { /* controller busy ? */ | |
2449 | TRACE(("gdth_next() controller %d busy !\n",hanum)); | |
2450 | if (!gdth_polling) { | |
2451 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
2452 | return; | |
2453 | } | |
2454 | while (gdth_test_busy(hanum)) | |
2455 | gdth_delay(1); | |
2456 | } | |
2457 | firsttime = FALSE; | |
2458 | } | |
2459 | ||
687d2bc4 | 2460 | if (!IS_GDTH_INTERNAL_CMD(nscp)) { |
1da177e4 LT |
2461 | if (nscp->SCp.phase == -1) { |
2462 | nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */ | |
2463 | if (nscp->cmnd[0] == TEST_UNIT_READY) { | |
2464 | TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n", | |
2465 | b, t, l)); | |
2466 | /* TEST_UNIT_READY -> set scan mode */ | |
2467 | if ((ha->scan_mode & 0x0f) == 0) { | |
2468 | if (b == 0 && t == 0 && l == 0) { | |
2469 | ha->scan_mode |= 1; | |
2470 | TRACE2(("Scan mode: 0x%x\n", ha->scan_mode)); | |
2471 | } | |
2472 | } else if ((ha->scan_mode & 0x0f) == 1) { | |
2473 | if (b == 0 && ((t == 0 && l == 1) || | |
2474 | (t == 1 && l == 0))) { | |
2475 | nscp->SCp.sent_command = GDT_SCAN_START; | |
2476 | nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8) | |
2477 | | SCSIRAWSERVICE; | |
2478 | ha->scan_mode = 0x12; | |
2479 | TRACE2(("Scan mode: 0x%x (SCAN_START)\n", | |
2480 | ha->scan_mode)); | |
2481 | } else { | |
2482 | ha->scan_mode &= 0x10; | |
2483 | TRACE2(("Scan mode: 0x%x\n", ha->scan_mode)); | |
2484 | } | |
2485 | } else if (ha->scan_mode == 0x12) { | |
2486 | if (b == ha->bus_cnt && t == ha->tid_cnt-1) { | |
2487 | nscp->SCp.phase = SCSIRAWSERVICE; | |
2488 | nscp->SCp.sent_command = GDT_SCAN_END; | |
2489 | ha->scan_mode &= 0x10; | |
2490 | TRACE2(("Scan mode: 0x%x (SCAN_END)\n", | |
2491 | ha->scan_mode)); | |
2492 | } | |
2493 | } | |
2494 | } | |
2495 | if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY && | |
2496 | nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE && | |
2497 | (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) { | |
2498 | /* always GDT_CLUST_INFO! */ | |
2499 | nscp->SCp.sent_command = GDT_CLUST_INFO; | |
2500 | } | |
2501 | } | |
2502 | } | |
2503 | ||
2504 | if (nscp->SCp.sent_command != -1) { | |
2505 | if ((nscp->SCp.phase & 0xff) == CACHESERVICE) { | |
2506 | if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t))) | |
2507 | this_cmd = FALSE; | |
2508 | next_cmd = FALSE; | |
2509 | } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) { | |
2510 | if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b)))) | |
2511 | this_cmd = FALSE; | |
2512 | next_cmd = FALSE; | |
2513 | } else { | |
2514 | memset((char*)nscp->sense_buffer,0,16); | |
2515 | nscp->sense_buffer[0] = 0x70; | |
2516 | nscp->sense_buffer[2] = NOT_READY; | |
2517 | nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1); | |
2518 | if (!nscp->SCp.have_data_in) | |
2519 | nscp->SCp.have_data_in++; | |
2520 | else | |
b8bff2ae | 2521 | gdth_scsi_done(nscp); |
1da177e4 | 2522 | } |
687d2bc4 | 2523 | } else if (IS_GDTH_INTERNAL_CMD(nscp)) { |
1da177e4 LT |
2524 | if (!(cmd_index=gdth_special_cmd(hanum,nscp))) |
2525 | this_cmd = FALSE; | |
2526 | next_cmd = FALSE; | |
2527 | } else if (b != ha->virt_bus) { | |
2528 | if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW || | |
2529 | !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b)))) | |
2530 | this_cmd = FALSE; | |
2531 | else | |
2532 | ha->raw[BUS_L2P(ha,b)].io_cnt[t]++; | |
2533 | } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) { | |
2534 | TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n", | |
2535 | nscp->cmnd[0], b, t, l)); | |
2536 | nscp->result = DID_BAD_TARGET << 16; | |
2537 | if (!nscp->SCp.have_data_in) | |
2538 | nscp->SCp.have_data_in++; | |
2539 | else | |
b8bff2ae | 2540 | gdth_scsi_done(nscp); |
1da177e4 LT |
2541 | } else { |
2542 | switch (nscp->cmnd[0]) { | |
2543 | case TEST_UNIT_READY: | |
2544 | case INQUIRY: | |
2545 | case REQUEST_SENSE: | |
2546 | case READ_CAPACITY: | |
2547 | case VERIFY: | |
2548 | case START_STOP: | |
2549 | case MODE_SENSE: | |
2550 | case SERVICE_ACTION_IN: | |
2551 | TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0], | |
2552 | nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3], | |
2553 | nscp->cmnd[4],nscp->cmnd[5])); | |
2554 | if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) { | |
2555 | /* return UNIT_ATTENTION */ | |
2556 | TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n", | |
2557 | nscp->cmnd[0], t)); | |
2558 | ha->hdr[t].media_changed = FALSE; | |
2559 | memset((char*)nscp->sense_buffer,0,16); | |
2560 | nscp->sense_buffer[0] = 0x70; | |
2561 | nscp->sense_buffer[2] = UNIT_ATTENTION; | |
2562 | nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1); | |
2563 | if (!nscp->SCp.have_data_in) | |
2564 | nscp->SCp.have_data_in++; | |
2565 | else | |
b8bff2ae MW |
2566 | gdth_scsi_done(nscp); |
2567 | } else if (gdth_internal_cache_cmd(hanum, nscp)) | |
2568 | gdth_scsi_done(nscp); | |
1da177e4 LT |
2569 | break; |
2570 | ||
2571 | case ALLOW_MEDIUM_REMOVAL: | |
2572 | TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0], | |
2573 | nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3], | |
2574 | nscp->cmnd[4],nscp->cmnd[5])); | |
2575 | if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) { | |
2576 | TRACE(("Prevent r. nonremov. drive->do nothing\n")); | |
2577 | nscp->result = DID_OK << 16; | |
2578 | nscp->sense_buffer[0] = 0; | |
2579 | if (!nscp->SCp.have_data_in) | |
2580 | nscp->SCp.have_data_in++; | |
2581 | else | |
b8bff2ae | 2582 | gdth_scsi_done(nscp); |
1da177e4 LT |
2583 | } else { |
2584 | nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0; | |
2585 | TRACE(("Prevent/allow r. %d rem. drive %d\n", | |
2586 | nscp->cmnd[4],nscp->cmnd[3])); | |
2587 | if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t))) | |
2588 | this_cmd = FALSE; | |
2589 | } | |
2590 | break; | |
2591 | ||
2592 | case RESERVE: | |
2593 | case RELEASE: | |
2594 | TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ? | |
2595 | "RESERVE" : "RELEASE")); | |
2596 | if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t))) | |
2597 | this_cmd = FALSE; | |
2598 | break; | |
2599 | ||
2600 | case READ_6: | |
2601 | case WRITE_6: | |
2602 | case READ_10: | |
2603 | case WRITE_10: | |
2604 | case READ_16: | |
2605 | case WRITE_16: | |
2606 | if (ha->hdr[t].media_changed) { | |
2607 | /* return UNIT_ATTENTION */ | |
2608 | TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n", | |
2609 | nscp->cmnd[0], t)); | |
2610 | ha->hdr[t].media_changed = FALSE; | |
2611 | memset((char*)nscp->sense_buffer,0,16); | |
2612 | nscp->sense_buffer[0] = 0x70; | |
2613 | nscp->sense_buffer[2] = UNIT_ATTENTION; | |
2614 | nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1); | |
2615 | if (!nscp->SCp.have_data_in) | |
2616 | nscp->SCp.have_data_in++; | |
2617 | else | |
b8bff2ae MW |
2618 | gdth_scsi_done(nscp); |
2619 | } else if (!(cmd_index=gdth_fill_cache_cmd(hanum, nscp, t))) | |
1da177e4 LT |
2620 | this_cmd = FALSE; |
2621 | break; | |
2622 | ||
2623 | default: | |
2624 | TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0], | |
2625 | nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3], | |
2626 | nscp->cmnd[4],nscp->cmnd[5])); | |
2627 | printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n", | |
2628 | hanum, nscp->cmnd[0]); | |
2629 | nscp->result = DID_ABORT << 16; | |
2630 | if (!nscp->SCp.have_data_in) | |
2631 | nscp->SCp.have_data_in++; | |
2632 | else | |
b8bff2ae | 2633 | gdth_scsi_done(nscp); |
1da177e4 LT |
2634 | break; |
2635 | } | |
2636 | } | |
2637 | ||
2638 | if (!this_cmd) | |
2639 | break; | |
2640 | if (nscp == ha->req_first) | |
2641 | ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr; | |
2642 | else | |
2643 | pscp->SCp.ptr = nscp->SCp.ptr; | |
2644 | if (!next_cmd) | |
2645 | break; | |
2646 | } | |
2647 | ||
2648 | if (ha->cmd_cnt > 0) { | |
2649 | gdth_release_event(hanum); | |
2650 | } | |
2651 | ||
2652 | if (!gdth_polling) | |
2653 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
2654 | ||
2655 | if (gdth_polling && ha->cmd_cnt > 0) { | |
2656 | if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT)) | |
2657 | printk("GDT-HA %d: Command %d timed out !\n", | |
2658 | hanum,cmd_index); | |
2659 | } | |
2660 | } | |
2661 | ||
2662 | static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp, | |
2663 | char *buffer,ushort count) | |
2664 | { | |
2665 | ushort cpcount,i; | |
2666 | ushort cpsum,cpnow; | |
2667 | struct scatterlist *sl; | |
2668 | gdth_ha_str *ha; | |
2669 | char *address; | |
2670 | ||
5d5ff44f | 2671 | cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen; |
1da177e4 LT |
2672 | ha = HADATA(gdth_ctr_tab[hanum]); |
2673 | ||
2674 | if (scp->use_sg) { | |
2675 | sl = (struct scatterlist *)scp->request_buffer; | |
2676 | for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) { | |
cbd5f69b | 2677 | unsigned long flags; |
1da177e4 LT |
2678 | cpnow = (ushort)sl->length; |
2679 | TRACE(("copy_internal() now %d sum %d count %d %d\n", | |
2680 | cpnow,cpsum,cpcount,(ushort)scp->bufflen)); | |
2681 | if (cpsum+cpnow > cpcount) | |
2682 | cpnow = cpcount - cpsum; | |
2683 | cpsum += cpnow; | |
2684 | if (!sl->page) { | |
2685 | printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n", | |
2686 | hanum); | |
2687 | return; | |
2688 | } | |
cbd5f69b LA |
2689 | local_irq_save(flags); |
2690 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) | |
2691 | address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset; | |
2692 | memcpy(address,buffer,cpnow); | |
2693 | flush_dcache_page(sl->page); | |
2694 | kunmap_atomic(address, KM_BIO_SRC_IRQ); | |
2695 | #else | |
2696 | address = kmap_atomic(sl->page, KM_BH_IRQ) + sl->offset; | |
1da177e4 | 2697 | memcpy(address,buffer,cpnow); |
cbd5f69b LA |
2698 | flush_dcache_page(sl->page); |
2699 | kunmap_atomic(address, KM_BH_IRQ); | |
2700 | #endif | |
2701 | local_irq_restore(flags); | |
1da177e4 LT |
2702 | if (cpsum == cpcount) |
2703 | break; | |
2704 | buffer += cpnow; | |
2705 | } | |
2706 | } else { | |
2707 | TRACE(("copy_internal() count %d\n",cpcount)); | |
2708 | memcpy((char*)scp->request_buffer,buffer,cpcount); | |
2709 | } | |
2710 | } | |
2711 | ||
2712 | static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp) | |
2713 | { | |
2714 | register gdth_ha_str *ha; | |
2715 | unchar t; | |
2716 | gdth_inq_data inq; | |
2717 | gdth_rdcap_data rdc; | |
2718 | gdth_sense_data sd; | |
2719 | gdth_modep_data mpd; | |
2720 | ||
2721 | ha = HADATA(gdth_ctr_tab[hanum]); | |
2722 | t = scp->device->id; | |
2723 | TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n", | |
2724 | scp->cmnd[0],t)); | |
2725 | ||
2726 | scp->result = DID_OK << 16; | |
2727 | scp->sense_buffer[0] = 0; | |
2728 | ||
2729 | switch (scp->cmnd[0]) { | |
2730 | case TEST_UNIT_READY: | |
2731 | case VERIFY: | |
2732 | case START_STOP: | |
2733 | TRACE2(("Test/Verify/Start hdrive %d\n",t)); | |
2734 | break; | |
2735 | ||
2736 | case INQUIRY: | |
2737 | TRACE2(("Inquiry hdrive %d devtype %d\n", | |
2738 | t,ha->hdr[t].devtype)); | |
2739 | inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK; | |
2740 | /* you can here set all disks to removable, if you want to do | |
2741 | a flush using the ALLOW_MEDIUM_REMOVAL command */ | |
2742 | inq.modif_rmb = 0x00; | |
2743 | if ((ha->hdr[t].devtype & 1) || | |
2744 | (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) | |
2745 | inq.modif_rmb = 0x80; | |
2746 | inq.version = 2; | |
2747 | inq.resp_aenc = 2; | |
2748 | inq.add_length= 32; | |
2749 | strcpy(inq.vendor,ha->oem_name); | |
2750 | sprintf(inq.product,"Host Drive #%02d",t); | |
2751 | strcpy(inq.revision," "); | |
2752 | gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data)); | |
2753 | break; | |
2754 | ||
2755 | case REQUEST_SENSE: | |
2756 | TRACE2(("Request sense hdrive %d\n",t)); | |
2757 | sd.errorcode = 0x70; | |
2758 | sd.segno = 0x00; | |
2759 | sd.key = NO_SENSE; | |
2760 | sd.info = 0; | |
2761 | sd.add_length= 0; | |
2762 | gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data)); | |
2763 | break; | |
2764 | ||
2765 | case MODE_SENSE: | |
2766 | TRACE2(("Mode sense hdrive %d\n",t)); | |
2767 | memset((char*)&mpd,0,sizeof(gdth_modep_data)); | |
2768 | mpd.hd.data_length = sizeof(gdth_modep_data); | |
2769 | mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0; | |
2770 | mpd.hd.bd_length = sizeof(mpd.bd); | |
2771 | mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16; | |
2772 | mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8; | |
2773 | mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff); | |
2774 | gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data)); | |
2775 | break; | |
2776 | ||
2777 | case READ_CAPACITY: | |
2778 | TRACE2(("Read capacity hdrive %d\n",t)); | |
2779 | if (ha->hdr[t].size > (ulong64)0xffffffff) | |
2780 | rdc.last_block_no = 0xffffffff; | |
2781 | else | |
2782 | rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1); | |
2783 | rdc.block_length = cpu_to_be32(SECTOR_SIZE); | |
2784 | gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data)); | |
2785 | break; | |
2786 | ||
2787 | case SERVICE_ACTION_IN: | |
2788 | if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 && | |
2789 | (ha->cache_feat & GDT_64BIT)) { | |
2790 | gdth_rdcap16_data rdc16; | |
2791 | ||
2792 | TRACE2(("Read capacity (16) hdrive %d\n",t)); | |
2793 | rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1); | |
2794 | rdc16.block_length = cpu_to_be32(SECTOR_SIZE); | |
2795 | gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data)); | |
2796 | } else { | |
2797 | scp->result = DID_ABORT << 16; | |
2798 | } | |
2799 | break; | |
2800 | ||
2801 | default: | |
2802 | TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0])); | |
2803 | break; | |
2804 | } | |
2805 | ||
2806 | if (!scp->SCp.have_data_in) | |
2807 | scp->SCp.have_data_in++; | |
2808 | else | |
2809 | return 1; | |
2810 | ||
2811 | return 0; | |
2812 | } | |
2813 | ||
2814 | static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive) | |
2815 | { | |
2816 | register gdth_ha_str *ha; | |
2817 | register gdth_cmd_str *cmdp; | |
2818 | struct scatterlist *sl; | |
2819 | ulong32 cnt, blockcnt; | |
2820 | ulong64 no, blockno; | |
2821 | dma_addr_t phys_addr; | |
2822 | int i, cmd_index, read_write, sgcnt, mode64; | |
2823 | struct page *page; | |
2824 | ulong offset; | |
2825 | ||
2826 | ha = HADATA(gdth_ctr_tab[hanum]); | |
2827 | cmdp = ha->pccb; | |
2828 | TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n", | |
2829 | scp->cmnd[0],scp->cmd_len,hdrive)); | |
2830 | ||
2831 | if (ha->type==GDT_EISA && ha->cmd_cnt>0) | |
2832 | return 0; | |
2833 | ||
2834 | mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE; | |
2835 | /* test for READ_16, WRITE_16 if !mode64 ? --- | |
2836 | not required, should not occur due to error return on | |
2837 | READ_CAPACITY_16 */ | |
2838 | ||
2839 | cmdp->Service = CACHESERVICE; | |
2840 | cmdp->RequestBuffer = scp; | |
2841 | /* search free command index */ | |
2842 | if (!(cmd_index=gdth_get_cmd_index(hanum))) { | |
2843 | TRACE(("GDT: No free command index found\n")); | |
2844 | return 0; | |
2845 | } | |
2846 | /* if it's the first command, set command semaphore */ | |
2847 | if (ha->cmd_cnt == 0) | |
2848 | gdth_set_sema0(hanum); | |
2849 | ||
2850 | /* fill command */ | |
2851 | read_write = 0; | |
2852 | if (scp->SCp.sent_command != -1) | |
2853 | cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */ | |
2854 | else if (scp->cmnd[0] == RESERVE) | |
2855 | cmdp->OpCode = GDT_RESERVE_DRV; | |
2856 | else if (scp->cmnd[0] == RELEASE) | |
2857 | cmdp->OpCode = GDT_RELEASE_DRV; | |
2858 | else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) { | |
2859 | if (scp->cmnd[4] & 1) /* prevent ? */ | |
2860 | cmdp->OpCode = GDT_MOUNT; | |
2861 | else if (scp->cmnd[3] & 1) /* removable drive ? */ | |
2862 | cmdp->OpCode = GDT_UNMOUNT; | |
2863 | else | |
2864 | cmdp->OpCode = GDT_FLUSH; | |
2865 | } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 || | |
2866 | scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16 | |
2867 | ) { | |
2868 | read_write = 1; | |
2869 | if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) && | |
2870 | (ha->cache_feat & GDT_WR_THROUGH))) | |
2871 | cmdp->OpCode = GDT_WRITE_THR; | |
2872 | else | |
2873 | cmdp->OpCode = GDT_WRITE; | |
2874 | } else { | |
2875 | read_write = 2; | |
2876 | cmdp->OpCode = GDT_READ; | |
2877 | } | |
2878 | ||
2879 | cmdp->BoardNode = LOCALBOARD; | |
2880 | if (mode64) { | |
2881 | cmdp->u.cache64.DeviceNo = hdrive; | |
2882 | cmdp->u.cache64.BlockNo = 1; | |
2883 | cmdp->u.cache64.sg_canz = 0; | |
2884 | } else { | |
2885 | cmdp->u.cache.DeviceNo = hdrive; | |
2886 | cmdp->u.cache.BlockNo = 1; | |
2887 | cmdp->u.cache.sg_canz = 0; | |
2888 | } | |
2889 | ||
2890 | if (read_write) { | |
2891 | if (scp->cmd_len == 16) { | |
2892 | memcpy(&no, &scp->cmnd[2], sizeof(ulong64)); | |
2893 | blockno = be64_to_cpu(no); | |
2894 | memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32)); | |
2895 | blockcnt = be32_to_cpu(cnt); | |
2896 | } else if (scp->cmd_len == 10) { | |
2897 | memcpy(&no, &scp->cmnd[2], sizeof(ulong32)); | |
2898 | blockno = be32_to_cpu(no); | |
2899 | memcpy(&cnt, &scp->cmnd[7], sizeof(ushort)); | |
2900 | blockcnt = be16_to_cpu(cnt); | |
2901 | } else { | |
2902 | memcpy(&no, &scp->cmnd[0], sizeof(ulong32)); | |
2903 | blockno = be32_to_cpu(no) & 0x001fffffUL; | |
2904 | blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4]; | |
2905 | } | |
2906 | if (mode64) { | |
2907 | cmdp->u.cache64.BlockNo = blockno; | |
2908 | cmdp->u.cache64.BlockCnt = blockcnt; | |
2909 | } else { | |
2910 | cmdp->u.cache.BlockNo = (ulong32)blockno; | |
2911 | cmdp->u.cache.BlockCnt = blockcnt; | |
2912 | } | |
2913 | ||
2914 | if (scp->use_sg) { | |
2915 | sl = (struct scatterlist *)scp->request_buffer; | |
2916 | sgcnt = scp->use_sg; | |
2917 | scp->SCp.Status = GDTH_MAP_SG; | |
2918 | scp->SCp.Message = (read_write == 1 ? | |
2919 | PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE); | |
2920 | sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message); | |
2921 | if (mode64) { | |
2922 | cmdp->u.cache64.DestAddr= (ulong64)-1; | |
2923 | cmdp->u.cache64.sg_canz = sgcnt; | |
2924 | for (i=0; i<sgcnt; ++i,++sl) { | |
2925 | cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl); | |
2926 | #ifdef GDTH_DMA_STATISTICS | |
2927 | if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff) | |
2928 | ha->dma64_cnt++; | |
2929 | else | |
2930 | ha->dma32_cnt++; | |
2931 | #endif | |
2932 | cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl); | |
2933 | } | |
2934 | } else { | |
2935 | cmdp->u.cache.DestAddr= 0xffffffff; | |
2936 | cmdp->u.cache.sg_canz = sgcnt; | |
2937 | for (i=0; i<sgcnt; ++i,++sl) { | |
2938 | cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl); | |
2939 | #ifdef GDTH_DMA_STATISTICS | |
2940 | ha->dma32_cnt++; | |
2941 | #endif | |
2942 | cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl); | |
2943 | } | |
2944 | } | |
2945 | ||
2946 | #ifdef GDTH_STATISTICS | |
2947 | if (max_sg < (ulong32)sgcnt) { | |
2948 | max_sg = (ulong32)sgcnt; | |
2949 | TRACE3(("GDT: max_sg = %d\n",max_sg)); | |
2950 | } | |
2951 | #endif | |
2952 | ||
40cdc840 | 2953 | } else if (scp->request_bufflen) { |
1da177e4 LT |
2954 | scp->SCp.Status = GDTH_MAP_SINGLE; |
2955 | scp->SCp.Message = (read_write == 1 ? | |
2956 | PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE); | |
2957 | page = virt_to_page(scp->request_buffer); | |
2958 | offset = (ulong)scp->request_buffer & ~PAGE_MASK; | |
2959 | phys_addr = pci_map_page(ha->pdev,page,offset, | |
2960 | scp->request_bufflen,scp->SCp.Message); | |
2961 | scp->SCp.dma_handle = phys_addr; | |
2962 | if (mode64) { | |
2963 | if (ha->cache_feat & SCATTER_GATHER) { | |
2964 | cmdp->u.cache64.DestAddr = (ulong64)-1; | |
2965 | cmdp->u.cache64.sg_canz = 1; | |
2966 | cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr; | |
2967 | cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen; | |
2968 | cmdp->u.cache64.sg_lst[1].sg_len = 0; | |
2969 | } else { | |
2970 | cmdp->u.cache64.DestAddr = phys_addr; | |
2971 | cmdp->u.cache64.sg_canz= 0; | |
2972 | } | |
2973 | } else { | |
2974 | if (ha->cache_feat & SCATTER_GATHER) { | |
2975 | cmdp->u.cache.DestAddr = 0xffffffff; | |
2976 | cmdp->u.cache.sg_canz = 1; | |
2977 | cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr; | |
2978 | cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen; | |
2979 | cmdp->u.cache.sg_lst[1].sg_len = 0; | |
2980 | } else { | |
2981 | cmdp->u.cache.DestAddr = phys_addr; | |
2982 | cmdp->u.cache.sg_canz= 0; | |
2983 | } | |
2984 | } | |
2985 | } | |
2986 | } | |
2987 | /* evaluate command size, check space */ | |
2988 | if (mode64) { | |
2989 | TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n", | |
2990 | cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz, | |
2991 | cmdp->u.cache64.sg_lst[0].sg_ptr, | |
2992 | cmdp->u.cache64.sg_lst[0].sg_len)); | |
2993 | TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n", | |
2994 | cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt)); | |
2995 | ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + | |
2996 | (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str); | |
2997 | } else { | |
2998 | TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n", | |
2999 | cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz, | |
3000 | cmdp->u.cache.sg_lst[0].sg_ptr, | |
3001 | cmdp->u.cache.sg_lst[0].sg_len)); | |
3002 | TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n", | |
3003 | cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt)); | |
3004 | ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + | |
3005 | (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str); | |
3006 | } | |
3007 | if (ha->cmd_len & 3) | |
3008 | ha->cmd_len += (4 - (ha->cmd_len & 3)); | |
3009 | ||
3010 | if (ha->cmd_cnt > 0) { | |
3011 | if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) > | |
3012 | ha->ic_all_size) { | |
3013 | TRACE2(("gdth_fill_cache() DPMEM overflow\n")); | |
3014 | ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND; | |
3015 | return 0; | |
3016 | } | |
3017 | } | |
3018 | ||
3019 | /* copy command */ | |
3020 | gdth_copy_command(hanum); | |
3021 | return cmd_index; | |
3022 | } | |
3023 | ||
3024 | static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b) | |
3025 | { | |
3026 | register gdth_ha_str *ha; | |
3027 | register gdth_cmd_str *cmdp; | |
3028 | struct scatterlist *sl; | |
3029 | ushort i; | |
3030 | dma_addr_t phys_addr, sense_paddr; | |
3031 | int cmd_index, sgcnt, mode64; | |
3032 | unchar t,l; | |
3033 | struct page *page; | |
3034 | ulong offset; | |
3035 | ||
3036 | ha = HADATA(gdth_ctr_tab[hanum]); | |
3037 | t = scp->device->id; | |
3038 | l = scp->device->lun; | |
3039 | cmdp = ha->pccb; | |
3040 | TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n", | |
3041 | scp->cmnd[0],b,t,l)); | |
3042 | ||
3043 | if (ha->type==GDT_EISA && ha->cmd_cnt>0) | |
3044 | return 0; | |
3045 | ||
3046 | mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE; | |
3047 | ||
3048 | cmdp->Service = SCSIRAWSERVICE; | |
3049 | cmdp->RequestBuffer = scp; | |
3050 | /* search free command index */ | |
3051 | if (!(cmd_index=gdth_get_cmd_index(hanum))) { | |
3052 | TRACE(("GDT: No free command index found\n")); | |
3053 | return 0; | |
3054 | } | |
3055 | /* if it's the first command, set command semaphore */ | |
3056 | if (ha->cmd_cnt == 0) | |
3057 | gdth_set_sema0(hanum); | |
3058 | ||
3059 | /* fill command */ | |
3060 | if (scp->SCp.sent_command != -1) { | |
3061 | cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */ | |
3062 | cmdp->BoardNode = LOCALBOARD; | |
3063 | if (mode64) { | |
3064 | cmdp->u.raw64.direction = (scp->SCp.phase >> 8); | |
3065 | TRACE2(("special raw cmd 0x%x param 0x%x\n", | |
3066 | cmdp->OpCode, cmdp->u.raw64.direction)); | |
3067 | /* evaluate command size */ | |
3068 | ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst); | |
3069 | } else { | |
3070 | cmdp->u.raw.direction = (scp->SCp.phase >> 8); | |
3071 | TRACE2(("special raw cmd 0x%x param 0x%x\n", | |
3072 | cmdp->OpCode, cmdp->u.raw.direction)); | |
3073 | /* evaluate command size */ | |
3074 | ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst); | |
3075 | } | |
3076 | ||
3077 | } else { | |
3078 | page = virt_to_page(scp->sense_buffer); | |
3079 | offset = (ulong)scp->sense_buffer & ~PAGE_MASK; | |
3080 | sense_paddr = pci_map_page(ha->pdev,page,offset, | |
3081 | 16,PCI_DMA_FROMDEVICE); | |
cbd5f69b | 3082 | *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr; |
1da177e4 | 3083 | /* high part, if 64bit */ |
cbd5f69b | 3084 | *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32); |
1da177e4 LT |
3085 | cmdp->OpCode = GDT_WRITE; /* always */ |
3086 | cmdp->BoardNode = LOCALBOARD; | |
3087 | if (mode64) { | |
3088 | cmdp->u.raw64.reserved = 0; | |
3089 | cmdp->u.raw64.mdisc_time = 0; | |
3090 | cmdp->u.raw64.mcon_time = 0; | |
3091 | cmdp->u.raw64.clen = scp->cmd_len; | |
3092 | cmdp->u.raw64.target = t; | |
3093 | cmdp->u.raw64.lun = l; | |
3094 | cmdp->u.raw64.bus = b; | |
3095 | cmdp->u.raw64.priority = 0; | |
3096 | cmdp->u.raw64.sdlen = scp->request_bufflen; | |
3097 | cmdp->u.raw64.sense_len = 16; | |
3098 | cmdp->u.raw64.sense_data = sense_paddr; | |
3099 | cmdp->u.raw64.direction = | |
3100 | gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN; | |
3101 | memcpy(cmdp->u.raw64.cmd,scp->cmnd,16); | |
bb9ba31c | 3102 | cmdp->u.raw64.sg_ranz = 0; |
1da177e4 LT |
3103 | } else { |
3104 | cmdp->u.raw.reserved = 0; | |
3105 | cmdp->u.raw.mdisc_time = 0; | |
3106 | cmdp->u.raw.mcon_time = 0; | |
3107 | cmdp->u.raw.clen = scp->cmd_len; | |
3108 | cmdp->u.raw.target = t; | |
3109 | cmdp->u.raw.lun = l; | |
3110 | cmdp->u.raw.bus = b; | |
3111 | cmdp->u.raw.priority = 0; | |
3112 | cmdp->u.raw.link_p = 0; | |
3113 | cmdp->u.raw.sdlen = scp->request_bufflen; | |
3114 | cmdp->u.raw.sense_len = 16; | |
3115 | cmdp->u.raw.sense_data = sense_paddr; | |
3116 | cmdp->u.raw.direction = | |
3117 | gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN; | |
3118 | memcpy(cmdp->u.raw.cmd,scp->cmnd,12); | |
bb9ba31c | 3119 | cmdp->u.raw.sg_ranz = 0; |
1da177e4 LT |
3120 | } |
3121 | ||
3122 | if (scp->use_sg) { | |
3123 | sl = (struct scatterlist *)scp->request_buffer; | |
3124 | sgcnt = scp->use_sg; | |
3125 | scp->SCp.Status = GDTH_MAP_SG; | |
3126 | scp->SCp.Message = PCI_DMA_BIDIRECTIONAL; | |
3127 | sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message); | |
3128 | if (mode64) { | |
3129 | cmdp->u.raw64.sdata = (ulong64)-1; | |
3130 | cmdp->u.raw64.sg_ranz = sgcnt; | |
3131 | for (i=0; i<sgcnt; ++i,++sl) { | |
3132 | cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl); | |
3133 | #ifdef GDTH_DMA_STATISTICS | |
3134 | if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff) | |
3135 | ha->dma64_cnt++; | |
3136 | else | |
3137 | ha->dma32_cnt++; | |
3138 | #endif | |
3139 | cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl); | |
3140 | } | |
3141 | } else { | |
3142 | cmdp->u.raw.sdata = 0xffffffff; | |
3143 | cmdp->u.raw.sg_ranz = sgcnt; | |
3144 | for (i=0; i<sgcnt; ++i,++sl) { | |
3145 | cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl); | |
3146 | #ifdef GDTH_DMA_STATISTICS | |
3147 | ha->dma32_cnt++; | |
3148 | #endif | |
3149 | cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl); | |
3150 | } | |
3151 | } | |
3152 | ||
3153 | #ifdef GDTH_STATISTICS | |
3154 | if (max_sg < sgcnt) { | |
3155 | max_sg = sgcnt; | |
3156 | TRACE3(("GDT: max_sg = %d\n",sgcnt)); | |
3157 | } | |
3158 | #endif | |
3159 | ||
cbd5f69b | 3160 | } else if (scp->request_bufflen) { |
1da177e4 LT |
3161 | scp->SCp.Status = GDTH_MAP_SINGLE; |
3162 | scp->SCp.Message = PCI_DMA_BIDIRECTIONAL; | |
3163 | page = virt_to_page(scp->request_buffer); | |
3164 | offset = (ulong)scp->request_buffer & ~PAGE_MASK; | |
3165 | phys_addr = pci_map_page(ha->pdev,page,offset, | |
3166 | scp->request_bufflen,scp->SCp.Message); | |
3167 | scp->SCp.dma_handle = phys_addr; | |
3168 | ||
3169 | if (mode64) { | |
3170 | if (ha->raw_feat & SCATTER_GATHER) { | |
3171 | cmdp->u.raw64.sdata = (ulong64)-1; | |
3172 | cmdp->u.raw64.sg_ranz= 1; | |
3173 | cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr; | |
3174 | cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen; | |
3175 | cmdp->u.raw64.sg_lst[1].sg_len = 0; | |
3176 | } else { | |
3177 | cmdp->u.raw64.sdata = phys_addr; | |
3178 | cmdp->u.raw64.sg_ranz= 0; | |
3179 | } | |
3180 | } else { | |
3181 | if (ha->raw_feat & SCATTER_GATHER) { | |
3182 | cmdp->u.raw.sdata = 0xffffffff; | |
3183 | cmdp->u.raw.sg_ranz= 1; | |
3184 | cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr; | |
3185 | cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen; | |
3186 | cmdp->u.raw.sg_lst[1].sg_len = 0; | |
3187 | } else { | |
3188 | cmdp->u.raw.sdata = phys_addr; | |
3189 | cmdp->u.raw.sg_ranz= 0; | |
3190 | } | |
3191 | } | |
3192 | } | |
3193 | if (mode64) { | |
3194 | TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n", | |
3195 | cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz, | |
3196 | cmdp->u.raw64.sg_lst[0].sg_ptr, | |
3197 | cmdp->u.raw64.sg_lst[0].sg_len)); | |
3198 | /* evaluate command size */ | |
3199 | ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + | |
3200 | (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str); | |
3201 | } else { | |
3202 | TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n", | |
3203 | cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz, | |
3204 | cmdp->u.raw.sg_lst[0].sg_ptr, | |
3205 | cmdp->u.raw.sg_lst[0].sg_len)); | |
3206 | /* evaluate command size */ | |
3207 | ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + | |
3208 | (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str); | |
3209 | } | |
3210 | } | |
3211 | /* check space */ | |
3212 | if (ha->cmd_len & 3) | |
3213 | ha->cmd_len += (4 - (ha->cmd_len & 3)); | |
3214 | ||
3215 | if (ha->cmd_cnt > 0) { | |
3216 | if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) > | |
3217 | ha->ic_all_size) { | |
3218 | TRACE2(("gdth_fill_raw() DPMEM overflow\n")); | |
3219 | ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND; | |
3220 | return 0; | |
3221 | } | |
3222 | } | |
3223 | ||
3224 | /* copy command */ | |
3225 | gdth_copy_command(hanum); | |
3226 | return cmd_index; | |
3227 | } | |
3228 | ||
3229 | static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp) | |
3230 | { | |
3231 | register gdth_ha_str *ha; | |
3232 | register gdth_cmd_str *cmdp; | |
3233 | int cmd_index; | |
3234 | ||
3235 | ha = HADATA(gdth_ctr_tab[hanum]); | |
3236 | cmdp= ha->pccb; | |
3237 | TRACE2(("gdth_special_cmd(): ")); | |
3238 | ||
3239 | if (ha->type==GDT_EISA && ha->cmd_cnt>0) | |
3240 | return 0; | |
3241 | ||
3242 | memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str)); | |
3243 | cmdp->RequestBuffer = scp; | |
3244 | ||
3245 | /* search free command index */ | |
3246 | if (!(cmd_index=gdth_get_cmd_index(hanum))) { | |
3247 | TRACE(("GDT: No free command index found\n")); | |
3248 | return 0; | |
3249 | } | |
3250 | ||
3251 | /* if it's the first command, set command semaphore */ | |
3252 | if (ha->cmd_cnt == 0) | |
3253 | gdth_set_sema0(hanum); | |
3254 | ||
3255 | /* evaluate command size, check space */ | |
3256 | if (cmdp->OpCode == GDT_IOCTL) { | |
3257 | TRACE2(("IOCTL\n")); | |
3258 | ha->cmd_len = | |
3259 | GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64); | |
3260 | } else if (cmdp->Service == CACHESERVICE) { | |
3261 | TRACE2(("cache command %d\n",cmdp->OpCode)); | |
3262 | if (ha->cache_feat & GDT_64BIT) | |
3263 | ha->cmd_len = | |
3264 | GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str); | |
3265 | else | |
3266 | ha->cmd_len = | |
3267 | GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str); | |
3268 | } else if (cmdp->Service == SCSIRAWSERVICE) { | |
3269 | TRACE2(("raw command %d\n",cmdp->OpCode)); | |
3270 | if (ha->raw_feat & GDT_64BIT) | |
3271 | ha->cmd_len = | |
3272 | GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str); | |
3273 | else | |
3274 | ha->cmd_len = | |
3275 | GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str); | |
3276 | } | |
3277 | ||
3278 | if (ha->cmd_len & 3) | |
3279 | ha->cmd_len += (4 - (ha->cmd_len & 3)); | |
3280 | ||
3281 | if (ha->cmd_cnt > 0) { | |
3282 | if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) > | |
3283 | ha->ic_all_size) { | |
3284 | TRACE2(("gdth_special_cmd() DPMEM overflow\n")); | |
3285 | ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND; | |
3286 | return 0; | |
3287 | } | |
3288 | } | |
3289 | ||
3290 | /* copy command */ | |
3291 | gdth_copy_command(hanum); | |
3292 | return cmd_index; | |
3293 | } | |
3294 | ||
3295 | ||
3296 | /* Controller event handling functions */ | |
3297 | static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source, | |
3298 | ushort idx, gdth_evt_data *evt) | |
3299 | { | |
3300 | gdth_evt_str *e; | |
3301 | struct timeval tv; | |
3302 | ||
3303 | /* no GDTH_LOCK_HA() ! */ | |
3304 | TRACE2(("gdth_store_event() source %d idx %d\n", source, idx)); | |
3305 | if (source == 0) /* no source -> no event */ | |
3306 | return NULL; | |
3307 | ||
3308 | if (ebuffer[elastidx].event_source == source && | |
3309 | ebuffer[elastidx].event_idx == idx && | |
3310 | ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 && | |
3311 | !memcmp((char *)&ebuffer[elastidx].event_data.eu, | |
3312 | (char *)&evt->eu, evt->size)) || | |
3313 | (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 && | |
3314 | !strcmp((char *)&ebuffer[elastidx].event_data.event_string, | |
3315 | (char *)&evt->event_string)))) { | |
3316 | e = &ebuffer[elastidx]; | |
3317 | do_gettimeofday(&tv); | |
3318 | e->last_stamp = tv.tv_sec; | |
3319 | ++e->same_count; | |
3320 | } else { | |
3321 | if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */ | |
3322 | ++elastidx; | |
3323 | if (elastidx == MAX_EVENTS) | |
3324 | elastidx = 0; | |
3325 | if (elastidx == eoldidx) { /* reached mark ? */ | |
3326 | ++eoldidx; | |
3327 | if (eoldidx == MAX_EVENTS) | |
3328 | eoldidx = 0; | |
3329 | } | |
3330 | } | |
3331 | e = &ebuffer[elastidx]; | |
3332 | e->event_source = source; | |
3333 | e->event_idx = idx; | |
3334 | do_gettimeofday(&tv); | |
3335 | e->first_stamp = e->last_stamp = tv.tv_sec; | |
3336 | e->same_count = 1; | |
3337 | e->event_data = *evt; | |
3338 | e->application = 0; | |
3339 | } | |
3340 | return e; | |
3341 | } | |
3342 | ||
3343 | static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr) | |
3344 | { | |
3345 | gdth_evt_str *e; | |
3346 | int eindex; | |
3347 | ulong flags; | |
3348 | ||
3349 | TRACE2(("gdth_read_event() handle %d\n", handle)); | |
3350 | spin_lock_irqsave(&ha->smp_lock, flags); | |
3351 | if (handle == -1) | |
3352 | eindex = eoldidx; | |
3353 | else | |
3354 | eindex = handle; | |
3355 | estr->event_source = 0; | |
3356 | ||
3357 | if (eindex >= MAX_EVENTS) { | |
3358 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
3359 | return eindex; | |
3360 | } | |
3361 | e = &ebuffer[eindex]; | |
3362 | if (e->event_source != 0) { | |
3363 | if (eindex != elastidx) { | |
3364 | if (++eindex == MAX_EVENTS) | |
3365 | eindex = 0; | |
3366 | } else { | |
3367 | eindex = -1; | |
3368 | } | |
3369 | memcpy(estr, e, sizeof(gdth_evt_str)); | |
3370 | } | |
3371 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
3372 | return eindex; | |
3373 | } | |
3374 | ||
3375 | static void gdth_readapp_event(gdth_ha_str *ha, | |
3376 | unchar application, gdth_evt_str *estr) | |
3377 | { | |
3378 | gdth_evt_str *e; | |
3379 | int eindex; | |
3380 | ulong flags; | |
3381 | unchar found = FALSE; | |
3382 | ||
3383 | TRACE2(("gdth_readapp_event() app. %d\n", application)); | |
3384 | spin_lock_irqsave(&ha->smp_lock, flags); | |
3385 | eindex = eoldidx; | |
3386 | for (;;) { | |
3387 | e = &ebuffer[eindex]; | |
3388 | if (e->event_source == 0) | |
3389 | break; | |
3390 | if ((e->application & application) == 0) { | |
3391 | e->application |= application; | |
3392 | found = TRUE; | |
3393 | break; | |
3394 | } | |
3395 | if (eindex == elastidx) | |
3396 | break; | |
3397 | if (++eindex == MAX_EVENTS) | |
3398 | eindex = 0; | |
3399 | } | |
3400 | if (found) | |
3401 | memcpy(estr, e, sizeof(gdth_evt_str)); | |
3402 | else | |
3403 | estr->event_source = 0; | |
3404 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
3405 | } | |
3406 | ||
3407 | static void gdth_clear_events(void) | |
3408 | { | |
3409 | TRACE(("gdth_clear_events()")); | |
3410 | ||
3411 | eoldidx = elastidx = 0; | |
3412 | ebuffer[0].event_source = 0; | |
3413 | } | |
3414 | ||
3415 | ||
3416 | /* SCSI interface functions */ | |
3417 | ||
7d12e780 | 3418 | static irqreturn_t gdth_interrupt(int irq,void *dev_id) |
1da177e4 LT |
3419 | { |
3420 | gdth_ha_str *ha2 = (gdth_ha_str *)dev_id; | |
3421 | register gdth_ha_str *ha; | |
3422 | gdt6m_dpram_str __iomem *dp6m_ptr = NULL; | |
3423 | gdt6_dpram_str __iomem *dp6_ptr; | |
3424 | gdt2_dpram_str __iomem *dp2_ptr; | |
3425 | Scsi_Cmnd *scp; | |
3426 | int hanum, rval, i; | |
3427 | unchar IStatus; | |
3428 | ushort Service; | |
3429 | ulong flags = 0; | |
3430 | #ifdef INT_COAL | |
3431 | int coalesced = FALSE; | |
3432 | int next = FALSE; | |
3433 | gdth_coal_status *pcs = NULL; | |
3434 | int act_int_coal = 0; | |
3435 | #endif | |
3436 | ||
3437 | TRACE(("gdth_interrupt() IRQ %d\n",irq)); | |
3438 | ||
3439 | /* if polling and not from gdth_wait() -> return */ | |
3440 | if (gdth_polling) { | |
3441 | if (!gdth_from_wait) { | |
3442 | return IRQ_HANDLED; | |
3443 | } | |
3444 | } | |
3445 | ||
3446 | if (!gdth_polling) | |
cbd5f69b | 3447 | spin_lock_irqsave(&ha2->smp_lock, flags); |
1da177e4 LT |
3448 | wait_index = 0; |
3449 | ||
3450 | /* search controller */ | |
3451 | if ((hanum = gdth_get_status(&IStatus,irq)) == -1) { | |
3452 | /* spurious interrupt */ | |
3453 | if (!gdth_polling) | |
3454 | spin_unlock_irqrestore(&ha2->smp_lock, flags); | |
3455 | return IRQ_HANDLED; | |
3456 | } | |
3457 | ha = HADATA(gdth_ctr_tab[hanum]); | |
3458 | ||
3459 | #ifdef GDTH_STATISTICS | |
3460 | ++act_ints; | |
3461 | #endif | |
3462 | ||
3463 | #ifdef INT_COAL | |
3464 | /* See if the fw is returning coalesced status */ | |
3465 | if (IStatus == COALINDEX) { | |
3466 | /* Coalesced status. Setup the initial status | |
3467 | buffer pointer and flags */ | |
3468 | pcs = ha->coal_stat; | |
3469 | coalesced = TRUE; | |
3470 | next = TRUE; | |
3471 | } | |
3472 | ||
3473 | do { | |
3474 | if (coalesced) { | |
3475 | /* For coalesced requests all status | |
3476 | information is found in the status buffer */ | |
3477 | IStatus = (unchar)(pcs->status & 0xff); | |
3478 | } | |
3479 | #endif | |
3480 | ||
3481 | if (ha->type == GDT_EISA) { | |
3482 | if (IStatus & 0x80) { /* error flag */ | |
3483 | IStatus &= ~0x80; | |
3484 | ha->status = inw(ha->bmic + MAILBOXREG+8); | |
3485 | TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status)); | |
3486 | } else /* no error */ | |
3487 | ha->status = S_OK; | |
3488 | ha->info = inl(ha->bmic + MAILBOXREG+12); | |
3489 | ha->service = inw(ha->bmic + MAILBOXREG+10); | |
3490 | ha->info2 = inl(ha->bmic + MAILBOXREG+4); | |
3491 | ||
3492 | outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */ | |
3493 | outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */ | |
3494 | } else if (ha->type == GDT_ISA) { | |
3495 | dp2_ptr = ha->brd; | |
3496 | if (IStatus & 0x80) { /* error flag */ | |
3497 | IStatus &= ~0x80; | |
3498 | ha->status = gdth_readw(&dp2_ptr->u.ic.Status); | |
3499 | TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status)); | |
3500 | } else /* no error */ | |
3501 | ha->status = S_OK; | |
3502 | ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]); | |
3503 | ha->service = gdth_readw(&dp2_ptr->u.ic.Service); | |
3504 | ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]); | |
3505 | ||
3506 | gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */ | |
3507 | gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */ | |
3508 | gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */ | |
3509 | } else if (ha->type == GDT_PCI) { | |
3510 | dp6_ptr = ha->brd; | |
3511 | if (IStatus & 0x80) { /* error flag */ | |
3512 | IStatus &= ~0x80; | |
3513 | ha->status = gdth_readw(&dp6_ptr->u.ic.Status); | |
3514 | TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status)); | |
3515 | } else /* no error */ | |
3516 | ha->status = S_OK; | |
3517 | ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]); | |
3518 | ha->service = gdth_readw(&dp6_ptr->u.ic.Service); | |
3519 | ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]); | |
3520 | ||
3521 | gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */ | |
3522 | gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */ | |
3523 | gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */ | |
3524 | } else if (ha->type == GDT_PCINEW) { | |
3525 | if (IStatus & 0x80) { /* error flag */ | |
3526 | IStatus &= ~0x80; | |
3527 | ha->status = inw(PTR2USHORT(&ha->plx->status)); | |
3528 | TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status)); | |
3529 | } else | |
3530 | ha->status = S_OK; | |
3531 | ha->info = inl(PTR2USHORT(&ha->plx->info[0])); | |
3532 | ha->service = inw(PTR2USHORT(&ha->plx->service)); | |
3533 | ha->info2 = inl(PTR2USHORT(&ha->plx->info[1])); | |
3534 | ||
3535 | outb(0xff, PTR2USHORT(&ha->plx->edoor_reg)); | |
3536 | outb(0x00, PTR2USHORT(&ha->plx->sema1_reg)); | |
3537 | } else if (ha->type == GDT_PCIMPR) { | |
3538 | dp6m_ptr = ha->brd; | |
3539 | if (IStatus & 0x80) { /* error flag */ | |
3540 | IStatus &= ~0x80; | |
3541 | #ifdef INT_COAL | |
3542 | if (coalesced) | |
107e716b | 3543 | ha->status = pcs->ext_status & 0xffff; |
1da177e4 LT |
3544 | else |
3545 | #endif | |
3546 | ha->status = gdth_readw(&dp6m_ptr->i960r.status); | |
3547 | TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status)); | |
3548 | } else /* no error */ | |
3549 | ha->status = S_OK; | |
3550 | #ifdef INT_COAL | |
3551 | /* get information */ | |
3552 | if (coalesced) { | |
3553 | ha->info = pcs->info0; | |
3554 | ha->info2 = pcs->info1; | |
107e716b | 3555 | ha->service = (pcs->ext_status >> 16) & 0xffff; |
1da177e4 LT |
3556 | } else |
3557 | #endif | |
3558 | { | |
3559 | ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]); | |
3560 | ha->service = gdth_readw(&dp6m_ptr->i960r.service); | |
3561 | ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]); | |
3562 | } | |
3563 | /* event string */ | |
3564 | if (IStatus == ASYNCINDEX) { | |
3565 | if (ha->service != SCREENSERVICE && | |
3566 | (ha->fw_vers & 0xff) >= 0x1a) { | |
3567 | ha->dvr.severity = gdth_readb | |
3568 | (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity); | |
3569 | for (i = 0; i < 256; ++i) { | |
3570 | ha->dvr.event_string[i] = gdth_readb | |
3571 | (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]); | |
3572 | if (ha->dvr.event_string[i] == 0) | |
3573 | break; | |
3574 | } | |
3575 | } | |
3576 | } | |
3577 | #ifdef INT_COAL | |
3578 | /* Make sure that non coalesced interrupts get cleared | |
3579 | before being handled by gdth_async_event/gdth_sync_event */ | |
3580 | if (!coalesced) | |
3581 | #endif | |
3582 | { | |
3583 | gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg); | |
3584 | gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg); | |
3585 | } | |
3586 | } else { | |
3587 | TRACE2(("gdth_interrupt() unknown controller type\n")); | |
3588 | if (!gdth_polling) | |
3589 | spin_unlock_irqrestore(&ha2->smp_lock, flags); | |
3590 | return IRQ_HANDLED; | |
3591 | } | |
3592 | ||
3593 | TRACE(("gdth_interrupt() index %d stat %d info %d\n", | |
3594 | IStatus,ha->status,ha->info)); | |
3595 | ||
3596 | if (gdth_from_wait) { | |
3597 | wait_hanum = hanum; | |
3598 | wait_index = (int)IStatus; | |
3599 | } | |
3600 | ||
3601 | if (IStatus == ASYNCINDEX) { | |
3602 | TRACE2(("gdth_interrupt() async. event\n")); | |
3603 | gdth_async_event(hanum); | |
3604 | if (!gdth_polling) | |
3605 | spin_unlock_irqrestore(&ha2->smp_lock, flags); | |
3606 | gdth_next(hanum); | |
3607 | return IRQ_HANDLED; | |
3608 | } | |
3609 | ||
3610 | if (IStatus == SPEZINDEX) { | |
3611 | TRACE2(("Service unknown or not initialized !\n")); | |
3612 | ha->dvr.size = sizeof(ha->dvr.eu.driver); | |
3613 | ha->dvr.eu.driver.ionode = hanum; | |
3614 | gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr); | |
3615 | if (!gdth_polling) | |
3616 | spin_unlock_irqrestore(&ha2->smp_lock, flags); | |
3617 | return IRQ_HANDLED; | |
3618 | } | |
3619 | scp = ha->cmd_tab[IStatus-2].cmnd; | |
3620 | Service = ha->cmd_tab[IStatus-2].service; | |
3621 | ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND; | |
3622 | if (scp == UNUSED_CMND) { | |
3623 | TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus)); | |
3624 | ha->dvr.size = sizeof(ha->dvr.eu.driver); | |
3625 | ha->dvr.eu.driver.ionode = hanum; | |
3626 | ha->dvr.eu.driver.index = IStatus; | |
3627 | gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr); | |
3628 | if (!gdth_polling) | |
3629 | spin_unlock_irqrestore(&ha2->smp_lock, flags); | |
3630 | return IRQ_HANDLED; | |
3631 | } | |
3632 | if (scp == INTERNAL_CMND) { | |
3633 | TRACE(("gdth_interrupt() answer to internal command\n")); | |
3634 | if (!gdth_polling) | |
3635 | spin_unlock_irqrestore(&ha2->smp_lock, flags); | |
3636 | return IRQ_HANDLED; | |
3637 | } | |
3638 | ||
3639 | TRACE(("gdth_interrupt() sync. status\n")); | |
3640 | rval = gdth_sync_event(hanum,Service,IStatus,scp); | |
3641 | if (!gdth_polling) | |
3642 | spin_unlock_irqrestore(&ha2->smp_lock, flags); | |
3643 | if (rval == 2) { | |
3644 | gdth_putq(hanum,scp,scp->SCp.this_residual); | |
3645 | } else if (rval == 1) { | |
b8bff2ae | 3646 | gdth_scsi_done(scp); |
1da177e4 LT |
3647 | } |
3648 | ||
3649 | #ifdef INT_COAL | |
3650 | if (coalesced) { | |
3651 | /* go to the next status in the status buffer */ | |
3652 | ++pcs; | |
3653 | #ifdef GDTH_STATISTICS | |
3654 | ++act_int_coal; | |
3655 | if (act_int_coal > max_int_coal) { | |
3656 | max_int_coal = act_int_coal; | |
3657 | printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal); | |
3658 | } | |
3659 | #endif | |
3660 | /* see if there is another status */ | |
3661 | if (pcs->status == 0) | |
3662 | /* Stop the coalesce loop */ | |
3663 | next = FALSE; | |
3664 | } | |
3665 | } while (next); | |
3666 | ||
3667 | /* coalescing only for new GDT_PCIMPR controllers available */ | |
3668 | if (ha->type == GDT_PCIMPR && coalesced) { | |
3669 | gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg); | |
3670 | gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg); | |
3671 | } | |
3672 | #endif | |
3673 | ||
3674 | gdth_next(hanum); | |
3675 | return IRQ_HANDLED; | |
3676 | } | |
3677 | ||
3678 | static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp) | |
3679 | { | |
3680 | register gdth_ha_str *ha; | |
3681 | gdth_msg_str *msg; | |
3682 | gdth_cmd_str *cmdp; | |
3683 | unchar b, t; | |
3684 | ||
3685 | ha = HADATA(gdth_ctr_tab[hanum]); | |
3686 | cmdp = ha->pccb; | |
3687 | TRACE(("gdth_sync_event() serv %d status %d\n", | |
3688 | service,ha->status)); | |
3689 | ||
3690 | if (service == SCREENSERVICE) { | |
3691 | msg = ha->pmsg; | |
3692 | TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n", | |
3693 | msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen)); | |
3694 | if (msg->msg_len > MSGLEN+1) | |
3695 | msg->msg_len = MSGLEN+1; | |
3696 | if (msg->msg_len) | |
3697 | if (!(msg->msg_answer && msg->msg_ext)) { | |
3698 | msg->msg_text[msg->msg_len] = '\0'; | |
3699 | printk("%s",msg->msg_text); | |
3700 | } | |
3701 | ||
3702 | if (msg->msg_ext && !msg->msg_answer) { | |
3703 | while (gdth_test_busy(hanum)) | |
3704 | gdth_delay(0); | |
3705 | cmdp->Service = SCREENSERVICE; | |
3706 | cmdp->RequestBuffer = SCREEN_CMND; | |
3707 | gdth_get_cmd_index(hanum); | |
3708 | gdth_set_sema0(hanum); | |
3709 | cmdp->OpCode = GDT_READ; | |
3710 | cmdp->BoardNode = LOCALBOARD; | |
3711 | cmdp->u.screen.reserved = 0; | |
3712 | cmdp->u.screen.su.msg.msg_handle= msg->msg_handle; | |
3713 | cmdp->u.screen.su.msg.msg_addr = ha->msg_phys; | |
3714 | ha->cmd_offs_dpmem = 0; | |
3715 | ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr) | |
3716 | + sizeof(ulong64); | |
3717 | ha->cmd_cnt = 0; | |
3718 | gdth_copy_command(hanum); | |
3719 | gdth_release_event(hanum); | |
3720 | return 0; | |
3721 | } | |
3722 | ||
3723 | if (msg->msg_answer && msg->msg_alen) { | |
3724 | /* default answers (getchar() not possible) */ | |
3725 | if (msg->msg_alen == 1) { | |
3726 | msg->msg_alen = 0; | |
3727 | msg->msg_len = 1; | |
3728 | msg->msg_text[0] = 0; | |
3729 | } else { | |
3730 | msg->msg_alen -= 2; | |
3731 | msg->msg_len = 2; | |
3732 | msg->msg_text[0] = 1; | |
3733 | msg->msg_text[1] = 0; | |
3734 | } | |
3735 | msg->msg_ext = 0; | |
3736 | msg->msg_answer = 0; | |
3737 | while (gdth_test_busy(hanum)) | |
3738 | gdth_delay(0); | |
3739 | cmdp->Service = SCREENSERVICE; | |
3740 | cmdp->RequestBuffer = SCREEN_CMND; | |
3741 | gdth_get_cmd_index(hanum); | |
3742 | gdth_set_sema0(hanum); | |
3743 | cmdp->OpCode = GDT_WRITE; | |
3744 | cmdp->BoardNode = LOCALBOARD; | |
3745 | cmdp->u.screen.reserved = 0; | |
3746 | cmdp->u.screen.su.msg.msg_handle= msg->msg_handle; | |
3747 | cmdp->u.screen.su.msg.msg_addr = ha->msg_phys; | |
3748 | ha->cmd_offs_dpmem = 0; | |
3749 | ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr) | |
3750 | + sizeof(ulong64); | |
3751 | ha->cmd_cnt = 0; | |
3752 | gdth_copy_command(hanum); | |
3753 | gdth_release_event(hanum); | |
3754 | return 0; | |
3755 | } | |
3756 | printk("\n"); | |
3757 | ||
3758 | } else { | |
3759 | b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel; | |
3760 | t = scp->device->id; | |
3761 | if (scp->SCp.sent_command == -1 && b != ha->virt_bus) { | |
3762 | ha->raw[BUS_L2P(ha,b)].io_cnt[t]--; | |
3763 | } | |
3764 | /* cache or raw service */ | |
3765 | if (ha->status == S_BSY) { | |
3766 | TRACE2(("Controller busy -> retry !\n")); | |
3767 | if (scp->SCp.sent_command == GDT_MOUNT) | |
3768 | scp->SCp.sent_command = GDT_CLUST_INFO; | |
3769 | /* retry */ | |
3770 | return 2; | |
3771 | } | |
3772 | if (scp->SCp.Status == GDTH_MAP_SG) | |
3773 | pci_unmap_sg(ha->pdev,scp->request_buffer, | |
3774 | scp->use_sg,scp->SCp.Message); | |
3775 | else if (scp->SCp.Status == GDTH_MAP_SINGLE) | |
3776 | pci_unmap_page(ha->pdev,scp->SCp.dma_handle, | |
3777 | scp->request_bufflen,scp->SCp.Message); | |
3778 | if (scp->SCp.buffer) { | |
3779 | dma_addr_t addr; | |
cbd5f69b | 3780 | addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer; |
1da177e4 | 3781 | if (scp->host_scribble) |
cbd5f69b LA |
3782 | addr += (dma_addr_t) |
3783 | ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32); | |
1da177e4 LT |
3784 | pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE); |
3785 | } | |
3786 | ||
3787 | if (ha->status == S_OK) { | |
3788 | scp->SCp.Status = S_OK; | |
3789 | scp->SCp.Message = ha->info; | |
3790 | if (scp->SCp.sent_command != -1) { | |
3791 | TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n", | |
3792 | scp->SCp.sent_command)); | |
3793 | /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */ | |
3794 | if (scp->SCp.sent_command == GDT_CLUST_INFO) { | |
3795 | ha->hdr[t].cluster_type = (unchar)ha->info; | |
3796 | if (!(ha->hdr[t].cluster_type & | |
3797 | CLUSTER_MOUNTED)) { | |
3798 | /* NOT MOUNTED -> MOUNT */ | |
3799 | scp->SCp.sent_command = GDT_MOUNT; | |
3800 | if (ha->hdr[t].cluster_type & | |
3801 | CLUSTER_RESERVED) { | |
3802 | /* cluster drive RESERVED (on the other node) */ | |
3803 | scp->SCp.phase = -2; /* reservation conflict */ | |
3804 | } | |
3805 | } else { | |
3806 | scp->SCp.sent_command = -1; | |
3807 | } | |
3808 | } else { | |
3809 | if (scp->SCp.sent_command == GDT_MOUNT) { | |
3810 | ha->hdr[t].cluster_type |= CLUSTER_MOUNTED; | |
3811 | ha->hdr[t].media_changed = TRUE; | |
3812 | } else if (scp->SCp.sent_command == GDT_UNMOUNT) { | |
3813 | ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED; | |
3814 | ha->hdr[t].media_changed = TRUE; | |
3815 | } | |
3816 | scp->SCp.sent_command = -1; | |
3817 | } | |
3818 | /* retry */ | |
3819 | scp->SCp.this_residual = HIGH_PRI; | |
3820 | return 2; | |
3821 | } else { | |
3822 | /* RESERVE/RELEASE ? */ | |
3823 | if (scp->cmnd[0] == RESERVE) { | |
3824 | ha->hdr[t].cluster_type |= CLUSTER_RESERVED; | |
3825 | } else if (scp->cmnd[0] == RELEASE) { | |
3826 | ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED; | |
3827 | } | |
3828 | scp->result = DID_OK << 16; | |
3829 | scp->sense_buffer[0] = 0; | |
3830 | } | |
3831 | } else { | |
3832 | scp->SCp.Status = ha->status; | |
3833 | scp->SCp.Message = ha->info; | |
3834 | ||
3835 | if (scp->SCp.sent_command != -1) { | |
3836 | TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n", | |
3837 | scp->SCp.sent_command, ha->status)); | |
3838 | if (scp->SCp.sent_command == GDT_SCAN_START || | |
3839 | scp->SCp.sent_command == GDT_SCAN_END) { | |
3840 | scp->SCp.sent_command = -1; | |
3841 | /* retry */ | |
3842 | scp->SCp.this_residual = HIGH_PRI; | |
3843 | return 2; | |
3844 | } | |
3845 | memset((char*)scp->sense_buffer,0,16); | |
3846 | scp->sense_buffer[0] = 0x70; | |
3847 | scp->sense_buffer[2] = NOT_READY; | |
3848 | scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1); | |
3849 | } else if (service == CACHESERVICE) { | |
3850 | if (ha->status == S_CACHE_UNKNOWN && | |
3851 | (ha->hdr[t].cluster_type & | |
3852 | CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) { | |
3853 | /* bus reset -> force GDT_CLUST_INFO */ | |
3854 | ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED; | |
3855 | } | |
3856 | memset((char*)scp->sense_buffer,0,16); | |
3857 | if (ha->status == (ushort)S_CACHE_RESERV) { | |
3858 | scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1); | |
3859 | } else { | |
3860 | scp->sense_buffer[0] = 0x70; | |
3861 | scp->sense_buffer[2] = NOT_READY; | |
3862 | scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1); | |
3863 | } | |
687d2bc4 | 3864 | if (!IS_GDTH_INTERNAL_CMD(scp)) { |
1da177e4 LT |
3865 | ha->dvr.size = sizeof(ha->dvr.eu.sync); |
3866 | ha->dvr.eu.sync.ionode = hanum; | |
3867 | ha->dvr.eu.sync.service = service; | |
3868 | ha->dvr.eu.sync.status = ha->status; | |
3869 | ha->dvr.eu.sync.info = ha->info; | |
3870 | ha->dvr.eu.sync.hostdrive = t; | |
3871 | if (ha->status >= 0x8000) | |
3872 | gdth_store_event(ha, ES_SYNC, 0, &ha->dvr); | |
3873 | else | |
3874 | gdth_store_event(ha, ES_SYNC, service, &ha->dvr); | |
3875 | } | |
3876 | } else { | |
3877 | /* sense buffer filled from controller firmware (DMA) */ | |
3878 | if (ha->status != S_RAW_SCSI || ha->info >= 0x100) { | |
3879 | scp->result = DID_BAD_TARGET << 16; | |
3880 | } else { | |
3881 | scp->result = (DID_OK << 16) | ha->info; | |
3882 | } | |
3883 | } | |
3884 | } | |
3885 | if (!scp->SCp.have_data_in) | |
3886 | scp->SCp.have_data_in++; | |
3887 | else | |
3888 | return 1; | |
3889 | } | |
3890 | ||
3891 | return 0; | |
3892 | } | |
3893 | ||
3894 | static char *async_cache_tab[] = { | |
3895 | /* 0*/ "\011\000\002\002\002\004\002\006\004" | |
3896 | "GDT HA %u, service %u, async. status %u/%lu unknown", | |
3897 | /* 1*/ "\011\000\002\002\002\004\002\006\004" | |
3898 | "GDT HA %u, service %u, async. status %u/%lu unknown", | |
3899 | /* 2*/ "\005\000\002\006\004" | |
3900 | "GDT HA %u, Host Drive %lu not ready", | |
3901 | /* 3*/ "\005\000\002\006\004" | |
3902 | "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced", | |
3903 | /* 4*/ "\005\000\002\006\004" | |
3904 | "GDT HA %u, mirror update on Host Drive %lu failed", | |
3905 | /* 5*/ "\005\000\002\006\004" | |
3906 | "GDT HA %u, Mirror Drive %lu failed", | |
3907 | /* 6*/ "\005\000\002\006\004" | |
3908 | "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced", | |
3909 | /* 7*/ "\005\000\002\006\004" | |
3910 | "GDT HA %u, Host Drive %lu write protected", | |
3911 | /* 8*/ "\005\000\002\006\004" | |
3912 | "GDT HA %u, media changed in Host Drive %lu", | |
3913 | /* 9*/ "\005\000\002\006\004" | |
3914 | "GDT HA %u, Host Drive %lu is offline", | |
3915 | /*10*/ "\005\000\002\006\004" | |
3916 | "GDT HA %u, media change of Mirror Drive %lu", | |
3917 | /*11*/ "\005\000\002\006\004" | |
3918 | "GDT HA %u, Mirror Drive %lu is write protected", | |
3919 | /*12*/ "\005\000\002\006\004" | |
3920 | "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!", | |
3921 | /*13*/ "\007\000\002\006\002\010\002" | |
3922 | "GDT HA %u, Array Drive %u: Cache Drive %u failed", | |
3923 | /*14*/ "\005\000\002\006\002" | |
3924 | "GDT HA %u, Array Drive %u: FAIL state entered", | |
3925 | /*15*/ "\005\000\002\006\002" | |
3926 | "GDT HA %u, Array Drive %u: error", | |
3927 | /*16*/ "\007\000\002\006\002\010\002" | |
3928 | "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u", | |
3929 | /*17*/ "\005\000\002\006\002" | |
3930 | "GDT HA %u, Array Drive %u: parity build failed", | |
3931 | /*18*/ "\005\000\002\006\002" | |
3932 | "GDT HA %u, Array Drive %u: drive rebuild failed", | |
3933 | /*19*/ "\005\000\002\010\002" | |
3934 | "GDT HA %u, Test of Hot Fix %u failed", | |
3935 | /*20*/ "\005\000\002\006\002" | |
3936 | "GDT HA %u, Array Drive %u: drive build finished successfully", | |
3937 | /*21*/ "\005\000\002\006\002" | |
3938 | "GDT HA %u, Array Drive %u: drive rebuild finished successfully", | |
3939 | /*22*/ "\007\000\002\006\002\010\002" | |
3940 | "GDT HA %u, Array Drive %u: Hot Fix %u activated", | |
3941 | /*23*/ "\005\000\002\006\002" | |
3942 | "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error", | |
3943 | /*24*/ "\005\000\002\010\002" | |
3944 | "GDT HA %u, mirror update on Cache Drive %u completed", | |
3945 | /*25*/ "\005\000\002\010\002" | |
3946 | "GDT HA %u, mirror update on Cache Drive %lu failed", | |
3947 | /*26*/ "\005\000\002\006\002" | |
3948 | "GDT HA %u, Array Drive %u: drive rebuild started", | |
3949 | /*27*/ "\005\000\002\012\001" | |
3950 | "GDT HA %u, Fault bus %u: SHELF OK detected", | |
3951 | /*28*/ "\005\000\002\012\001" | |
3952 | "GDT HA %u, Fault bus %u: SHELF not OK detected", | |
3953 | /*29*/ "\007\000\002\012\001\013\001" | |
3954 | "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started", | |
3955 | /*30*/ "\007\000\002\012\001\013\001" | |
3956 | "GDT HA %u, Fault bus %u, ID %u: new disk detected", | |
3957 | /*31*/ "\007\000\002\012\001\013\001" | |
3958 | "GDT HA %u, Fault bus %u, ID %u: old disk detected", | |
3959 | /*32*/ "\007\000\002\012\001\013\001" | |
3960 | "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid", | |
3961 | /*33*/ "\007\000\002\012\001\013\001" | |
3962 | "GDT HA %u, Fault bus %u, ID %u: invalid device detected", | |
3963 | /*34*/ "\011\000\002\012\001\013\001\006\004" | |
3964 | "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)", | |
3965 | /*35*/ "\007\000\002\012\001\013\001" | |
3966 | "GDT HA %u, Fault bus %u, ID %u: disk write protected", | |
3967 | /*36*/ "\007\000\002\012\001\013\001" | |
3968 | "GDT HA %u, Fault bus %u, ID %u: disk not available", | |
3969 | /*37*/ "\007\000\002\012\001\006\004" | |
3970 | "GDT HA %u, Fault bus %u: swap detected (%lu)", | |
3971 | /*38*/ "\007\000\002\012\001\013\001" | |
3972 | "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully", | |
3973 | /*39*/ "\007\000\002\012\001\013\001" | |
3974 | "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug", | |
3975 | /*40*/ "\007\000\002\012\001\013\001" | |
3976 | "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted", | |
3977 | /*41*/ "\007\000\002\012\001\013\001" | |
3978 | "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started", | |
3979 | /*42*/ "\005\000\002\006\002" | |
3980 | "GDT HA %u, Array Drive %u: drive build started", | |
3981 | /*43*/ "\003\000\002" | |
3982 | "GDT HA %u, DRAM parity error detected", | |
3983 | /*44*/ "\005\000\002\006\002" | |
3984 | "GDT HA %u, Mirror Drive %u: update started", | |
3985 | /*45*/ "\007\000\002\006\002\010\002" | |
3986 | "GDT HA %u, Mirror Drive %u: Hot Fix %u activated", | |
3987 | /*46*/ "\005\000\002\006\002" | |
3988 | "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available", | |
3989 | /*47*/ "\005\000\002\006\002" | |
3990 | "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available", | |
3991 | /*48*/ "\005\000\002\006\002" | |
3992 | "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available", | |
3993 | /*49*/ "\005\000\002\006\002" | |
3994 | "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available", | |
3995 | /*50*/ "\007\000\002\012\001\013\001" | |
3996 | "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received", | |
3997 | /*51*/ "\005\000\002\006\002" | |
3998 | "GDT HA %u, Array Drive %u: expand started", | |
3999 | /*52*/ "\005\000\002\006\002" | |
4000 | "GDT HA %u, Array Drive %u: expand finished successfully", | |
4001 | /*53*/ "\005\000\002\006\002" | |
4002 | "GDT HA %u, Array Drive %u: expand failed", | |
4003 | /*54*/ "\003\000\002" | |
4004 | "GDT HA %u, CPU temperature critical", | |
4005 | /*55*/ "\003\000\002" | |
4006 | "GDT HA %u, CPU temperature OK", | |
4007 | /*56*/ "\005\000\002\006\004" | |
4008 | "GDT HA %u, Host drive %lu created", | |
4009 | /*57*/ "\005\000\002\006\002" | |
4010 | "GDT HA %u, Array Drive %u: expand restarted", | |
4011 | /*58*/ "\005\000\002\006\002" | |
4012 | "GDT HA %u, Array Drive %u: expand stopped", | |
4013 | /*59*/ "\005\000\002\010\002" | |
4014 | "GDT HA %u, Mirror Drive %u: drive build quited", | |
4015 | /*60*/ "\005\000\002\006\002" | |
4016 | "GDT HA %u, Array Drive %u: parity build quited", | |
4017 | /*61*/ "\005\000\002\006\002" | |
4018 | "GDT HA %u, Array Drive %u: drive rebuild quited", | |
4019 | /*62*/ "\005\000\002\006\002" | |
4020 | "GDT HA %u, Array Drive %u: parity verify started", | |
4021 | /*63*/ "\005\000\002\006\002" | |
4022 | "GDT HA %u, Array Drive %u: parity verify done", | |
4023 | /*64*/ "\005\000\002\006\002" | |
4024 | "GDT HA %u, Array Drive %u: parity verify failed", | |
4025 | /*65*/ "\005\000\002\006\002" | |
4026 | "GDT HA %u, Array Drive %u: parity error detected", | |
4027 | /*66*/ "\005\000\002\006\002" | |
4028 | "GDT HA %u, Array Drive %u: parity verify quited", | |
4029 | /*67*/ "\005\000\002\006\002" | |
4030 | "GDT HA %u, Host Drive %u reserved", | |
4031 | /*68*/ "\005\000\002\006\002" | |
4032 | "GDT HA %u, Host Drive %u mounted and released", | |
4033 | /*69*/ "\005\000\002\006\002" | |
4034 | "GDT HA %u, Host Drive %u released", | |
4035 | /*70*/ "\003\000\002" | |
4036 | "GDT HA %u, DRAM error detected and corrected with ECC", | |
4037 | /*71*/ "\003\000\002" | |
4038 | "GDT HA %u, Uncorrectable DRAM error detected with ECC", | |
4039 | /*72*/ "\011\000\002\012\001\013\001\014\001" | |
4040 | "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block", | |
4041 | /*73*/ "\005\000\002\006\002" | |
4042 | "GDT HA %u, Host drive %u resetted locally", | |
4043 | /*74*/ "\005\000\002\006\002" | |
4044 | "GDT HA %u, Host drive %u resetted remotely", | |
4045 | /*75*/ "\003\000\002" | |
4046 | "GDT HA %u, async. status 75 unknown", | |
4047 | }; | |
4048 | ||
4049 | ||
4050 | static int gdth_async_event(int hanum) | |
4051 | { | |
4052 | gdth_ha_str *ha; | |
4053 | gdth_cmd_str *cmdp; | |
4054 | int cmd_index; | |
4055 | ||
4056 | ha = HADATA(gdth_ctr_tab[hanum]); | |
4057 | cmdp= ha->pccb; | |
4058 | TRACE2(("gdth_async_event() ha %d serv %d\n", | |
4059 | hanum,ha->service)); | |
4060 | ||
4061 | if (ha->service == SCREENSERVICE) { | |
4062 | if (ha->status == MSG_REQUEST) { | |
4063 | while (gdth_test_busy(hanum)) | |
4064 | gdth_delay(0); | |
4065 | cmdp->Service = SCREENSERVICE; | |
4066 | cmdp->RequestBuffer = SCREEN_CMND; | |
4067 | cmd_index = gdth_get_cmd_index(hanum); | |
4068 | gdth_set_sema0(hanum); | |
4069 | cmdp->OpCode = GDT_READ; | |
4070 | cmdp->BoardNode = LOCALBOARD; | |
4071 | cmdp->u.screen.reserved = 0; | |
4072 | cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE; | |
4073 | cmdp->u.screen.su.msg.msg_addr = ha->msg_phys; | |
4074 | ha->cmd_offs_dpmem = 0; | |
4075 | ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr) | |
4076 | + sizeof(ulong64); | |
4077 | ha->cmd_cnt = 0; | |
4078 | gdth_copy_command(hanum); | |
4079 | if (ha->type == GDT_EISA) | |
4080 | printk("[EISA slot %d] ",(ushort)ha->brd_phys); | |
4081 | else if (ha->type == GDT_ISA) | |
4082 | printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys); | |
4083 | else | |
4084 | printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8), | |
4085 | (ushort)((ha->brd_phys>>3)&0x1f)); | |
4086 | gdth_release_event(hanum); | |
4087 | } | |
4088 | ||
4089 | } else { | |
4090 | if (ha->type == GDT_PCIMPR && | |
4091 | (ha->fw_vers & 0xff) >= 0x1a) { | |
4092 | ha->dvr.size = 0; | |
4093 | ha->dvr.eu.async.ionode = hanum; | |
4094 | ha->dvr.eu.async.status = ha->status; | |
4095 | /* severity and event_string already set! */ | |
4096 | } else { | |
4097 | ha->dvr.size = sizeof(ha->dvr.eu.async); | |
4098 | ha->dvr.eu.async.ionode = hanum; | |
4099 | ha->dvr.eu.async.service = ha->service; | |
4100 | ha->dvr.eu.async.status = ha->status; | |
4101 | ha->dvr.eu.async.info = ha->info; | |
4102 | *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2; | |
4103 | } | |
4104 | gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr ); | |
4105 | gdth_log_event( &ha->dvr, NULL ); | |
4106 | ||
4107 | /* new host drive from expand? */ | |
4108 | if (ha->service == CACHESERVICE && ha->status == 56) { | |
4109 | TRACE2(("gdth_async_event(): new host drive %d created\n", | |
4110 | (ushort)ha->info)); | |
4111 | /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */ | |
4112 | } | |
4113 | } | |
4114 | return 1; | |
4115 | } | |
4116 | ||
4117 | static void gdth_log_event(gdth_evt_data *dvr, char *buffer) | |
4118 | { | |
4119 | gdth_stackframe stack; | |
4120 | char *f = NULL; | |
4121 | int i,j; | |
4122 | ||
4123 | TRACE2(("gdth_log_event()\n")); | |
4124 | if (dvr->size == 0) { | |
4125 | if (buffer == NULL) { | |
4126 | printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string); | |
4127 | } else { | |
4128 | sprintf(buffer,"Adapter %d: %s\n", | |
4129 | dvr->eu.async.ionode,dvr->event_string); | |
4130 | } | |
4131 | } else if (dvr->eu.async.service == CACHESERVICE && | |
4132 | INDEX_OK(dvr->eu.async.status, async_cache_tab)) { | |
4133 | TRACE2(("GDT: Async. event cache service, event no.: %d\n", | |
4134 | dvr->eu.async.status)); | |
4135 | ||
4136 | f = async_cache_tab[dvr->eu.async.status]; | |
4137 | ||
4138 | /* i: parameter to push, j: stack element to fill */ | |
4139 | for (j=0,i=1; i < f[0]; i+=2) { | |
4140 | switch (f[i+1]) { | |
4141 | case 4: | |
4142 | stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]]; | |
4143 | break; | |
4144 | case 2: | |
4145 | stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]]; | |
4146 | break; | |
4147 | case 1: | |
4148 | stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]]; | |
4149 | break; | |
4150 | default: | |
4151 | break; | |
4152 | } | |
4153 | } | |
4154 | ||
4155 | if (buffer == NULL) { | |
4156 | printk(&f[(int)f[0]],stack); | |
4157 | printk("\n"); | |
4158 | } else { | |
4159 | sprintf(buffer,&f[(int)f[0]],stack); | |
4160 | } | |
4161 | ||
4162 | } else { | |
4163 | if (buffer == NULL) { | |
4164 | printk("GDT HA %u, Unknown async. event service %d event no. %d\n", | |
4165 | dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status); | |
4166 | } else { | |
4167 | sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d", | |
4168 | dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status); | |
4169 | } | |
4170 | } | |
4171 | } | |
4172 | ||
4173 | #ifdef GDTH_STATISTICS | |
8e879041 | 4174 | static void gdth_timeout(ulong data) |
1da177e4 LT |
4175 | { |
4176 | ulong32 i; | |
4177 | Scsi_Cmnd *nscp; | |
4178 | gdth_ha_str *ha; | |
4179 | ulong flags; | |
4180 | int hanum = 0; | |
4181 | ||
4182 | ha = HADATA(gdth_ctr_tab[hanum]); | |
4183 | spin_lock_irqsave(&ha->smp_lock, flags); | |
4184 | ||
4185 | for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i) | |
4186 | if (ha->cmd_tab[i].cmnd != UNUSED_CMND) | |
4187 | ++act_stats; | |
4188 | ||
4189 | for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr) | |
4190 | ++act_rq; | |
4191 | ||
4192 | TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n", | |
4193 | act_ints, act_ios, act_stats, act_rq)); | |
4194 | act_ints = act_ios = 0; | |
4195 | ||
4196 | gdth_timer.expires = jiffies + 30 * HZ; | |
4197 | add_timer(&gdth_timer); | |
4198 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
4199 | } | |
4200 | #endif | |
4201 | ||
8e879041 | 4202 | static void __init internal_setup(char *str,int *ints) |
1da177e4 LT |
4203 | { |
4204 | int i, argc; | |
4205 | char *cur_str, *argv; | |
4206 | ||
4207 | TRACE2(("internal_setup() str %s ints[0] %d\n", | |
4208 | str ? str:"NULL", ints ? ints[0]:0)); | |
4209 | ||
4210 | /* read irq[] from ints[] */ | |
4211 | if (ints) { | |
4212 | argc = ints[0]; | |
4213 | if (argc > 0) { | |
4214 | if (argc > MAXHA) | |
4215 | argc = MAXHA; | |
4216 | for (i = 0; i < argc; ++i) | |
4217 | irq[i] = ints[i+1]; | |
4218 | } | |
4219 | } | |
4220 | ||
4221 | /* analyse string */ | |
4222 | argv = str; | |
4223 | while (argv && (cur_str = strchr(argv, ':'))) { | |
4224 | int val = 0, c = *++cur_str; | |
4225 | ||
4226 | if (c == 'n' || c == 'N') | |
4227 | val = 0; | |
4228 | else if (c == 'y' || c == 'Y') | |
4229 | val = 1; | |
4230 | else | |
4231 | val = (int)simple_strtoul(cur_str, NULL, 0); | |
4232 | ||
4233 | if (!strncmp(argv, "disable:", 8)) | |
4234 | disable = val; | |
4235 | else if (!strncmp(argv, "reserve_mode:", 13)) | |
4236 | reserve_mode = val; | |
4237 | else if (!strncmp(argv, "reverse_scan:", 13)) | |
4238 | reverse_scan = val; | |
4239 | else if (!strncmp(argv, "hdr_channel:", 12)) | |
4240 | hdr_channel = val; | |
4241 | else if (!strncmp(argv, "max_ids:", 8)) | |
4242 | max_ids = val; | |
4243 | else if (!strncmp(argv, "rescan:", 7)) | |
4244 | rescan = val; | |
4245 | else if (!strncmp(argv, "virt_ctr:", 9)) | |
4246 | virt_ctr = val; | |
4247 | else if (!strncmp(argv, "shared_access:", 14)) | |
4248 | shared_access = val; | |
4249 | else if (!strncmp(argv, "probe_eisa_isa:", 15)) | |
4250 | probe_eisa_isa = val; | |
4251 | else if (!strncmp(argv, "reserve_list:", 13)) { | |
4252 | reserve_list[0] = val; | |
4253 | for (i = 1; i < MAX_RES_ARGS; i++) { | |
4254 | cur_str = strchr(cur_str, ','); | |
4255 | if (!cur_str) | |
4256 | break; | |
4257 | if (!isdigit((int)*++cur_str)) { | |
4258 | --cur_str; | |
4259 | break; | |
4260 | } | |
4261 | reserve_list[i] = | |
4262 | (int)simple_strtoul(cur_str, NULL, 0); | |
4263 | } | |
4264 | if (!cur_str) | |
4265 | break; | |
4266 | argv = ++cur_str; | |
4267 | continue; | |
4268 | } | |
4269 | ||
4270 | if ((argv = strchr(argv, ','))) | |
4271 | ++argv; | |
4272 | } | |
4273 | } | |
4274 | ||
4275 | int __init option_setup(char *str) | |
4276 | { | |
4277 | int ints[MAXHA]; | |
4278 | char *cur = str; | |
4279 | int i = 1; | |
4280 | ||
4281 | TRACE2(("option_setup() str %s\n", str ? str:"NULL")); | |
4282 | ||
4283 | while (cur && isdigit(*cur) && i <= MAXHA) { | |
4284 | ints[i++] = simple_strtoul(cur, NULL, 0); | |
4285 | if ((cur = strchr(cur, ',')) != NULL) cur++; | |
4286 | } | |
4287 | ||
4288 | ints[0] = i - 1; | |
4289 | internal_setup(cur, ints); | |
4290 | return 1; | |
4291 | } | |
4292 | ||
aed91cb5 | 4293 | |
cbd5f69b | 4294 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) |
d0be4a7d | 4295 | static int __init gdth_detect(struct scsi_host_template *shtp) |
cbd5f69b LA |
4296 | #else |
4297 | static int __init gdth_detect(Scsi_Host_Template *shtp) | |
4298 | #endif | |
1da177e4 LT |
4299 | { |
4300 | struct Scsi_Host *shp; | |
4301 | gdth_pci_str pcistr[MAXHA]; | |
4302 | gdth_ha_str *ha; | |
1da177e4 LT |
4303 | int i,hanum,cnt,ctr,err; |
4304 | unchar b; | |
4305 | ||
4306 | ||
4307 | #ifdef DEBUG_GDTH | |
4308 | printk("GDT: This driver contains debugging information !! Trace level = %d\n", | |
4309 | DebugState); | |
4310 | printk(" Destination of debugging information: "); | |
4311 | #ifdef __SERIAL__ | |
4312 | #ifdef __COM2__ | |
4313 | printk("Serial port COM2\n"); | |
4314 | #else | |
4315 | printk("Serial port COM1\n"); | |
4316 | #endif | |
4317 | #else | |
4318 | printk("Console\n"); | |
4319 | #endif | |
4320 | gdth_delay(3000); | |
4321 | #endif | |
4322 | ||
4323 | TRACE(("gdth_detect()\n")); | |
4324 | ||
4325 | if (disable) { | |
4326 | printk("GDT-HA: Controller driver disabled from command line !\n"); | |
4327 | return 0; | |
4328 | } | |
4329 | ||
cbd5f69b | 4330 | printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR); |
1da177e4 LT |
4331 | /* initializations */ |
4332 | gdth_polling = TRUE; b = 0; | |
4333 | gdth_clear_events(); | |
4334 | ||
4335 | /* As default we do not probe for EISA or ISA controllers */ | |
4336 | if (probe_eisa_isa) { | |
4337 | /* scanning for controllers, at first: ISA controller */ | |
aed91cb5 CH |
4338 | #ifdef CONFIG_ISA |
4339 | ulong32 isa_bios; | |
4340 | for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL; | |
4341 | isa_bios += 0x8000UL) { | |
4342 | if (gdth_ctr_count >= MAXHA) | |
1da177e4 | 4343 | break; |
aed91cb5 | 4344 | gdth_isa_probe_one(shtp, isa_bios); |
1da177e4 | 4345 | } |
aed91cb5 | 4346 | #endif |
706a5d45 CH |
4347 | #ifdef CONFIG_EISA |
4348 | { | |
4349 | ushort eisa_slot; | |
4350 | for (eisa_slot = 0x1000; eisa_slot <= 0x8000; eisa_slot += 0x1000) { | |
4351 | if (gdth_ctr_count >= MAXHA) | |
1da177e4 | 4352 | break; |
706a5d45 | 4353 | gdth_eisa_probe_one(shtp, eisa_slot); |
1da177e4 | 4354 | } |
706a5d45 CH |
4355 | } |
4356 | #endif | |
1da177e4 LT |
4357 | } |
4358 | ||
4359 | /* scanning for PCI controllers */ | |
4360 | cnt = gdth_search_pci(pcistr); | |
4361 | printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt); | |
4362 | gdth_sort_pci(pcistr,cnt); | |
4363 | for (ctr = 0; ctr < cnt; ++ctr) { | |
4364 | dma_addr_t scratch_dma_handle; | |
4365 | scratch_dma_handle = 0; | |
4366 | ||
4367 | if (gdth_ctr_count >= MAXHA) | |
4368 | break; | |
4369 | shp = scsi_register(shtp,sizeof(gdth_ext_str)); | |
4370 | if (shp == NULL) | |
4371 | continue; | |
4372 | ||
4373 | ha = HADATA(shp); | |
4374 | if (!gdth_init_pci(&pcistr[ctr],ha)) { | |
4375 | scsi_unregister(shp); | |
4376 | continue; | |
4377 | } | |
4378 | /* controller found and initialized */ | |
4379 | printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n", | |
8e9a8a0d JG |
4380 | pcistr[ctr].pdev->bus->number, |
4381 | PCI_SLOT(pcistr[ctr].pdev->devfn), ha->irq); | |
1da177e4 LT |
4382 | |
4383 | if (request_irq(ha->irq, gdth_interrupt, | |
1d6f359a | 4384 | IRQF_DISABLED|IRQF_SHARED, "gdth", ha)) |
1da177e4 LT |
4385 | { |
4386 | printk("GDT-PCI: Unable to allocate IRQ\n"); | |
4387 | scsi_unregister(shp); | |
4388 | continue; | |
4389 | } | |
4390 | shp->unchecked_isa_dma = 0; | |
4391 | shp->irq = ha->irq; | |
4392 | shp->dma_channel = 0xff; | |
4393 | hanum = gdth_ctr_count; | |
4394 | gdth_ctr_tab[gdth_ctr_count++] = shp; | |
4395 | gdth_ctr_vtab[gdth_ctr_vcount++] = shp; | |
4396 | ||
4397 | NUMDATA(shp)->hanum = (ushort)hanum; | |
4398 | NUMDATA(shp)->busnum= 0; | |
4399 | ||
4400 | ha->pccb = CMDDATA(shp); | |
4401 | ha->ccb_phys = 0L; | |
4402 | ||
4403 | ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH, | |
4404 | &scratch_dma_handle); | |
4405 | ha->scratch_phys = scratch_dma_handle; | |
4406 | ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str), | |
4407 | &scratch_dma_handle); | |
4408 | ha->msg_phys = scratch_dma_handle; | |
4409 | #ifdef INT_COAL | |
4410 | ha->coal_stat = (gdth_coal_status *) | |
4411 | pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) * | |
4412 | MAXOFFSETS, &scratch_dma_handle); | |
4413 | ha->coal_stat_phys = scratch_dma_handle; | |
4414 | #endif | |
4415 | ha->scratch_busy = FALSE; | |
4416 | ha->req_first = NULL; | |
8e9a8a0d | 4417 | ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES; |
1da177e4 LT |
4418 | if (max_ids > 0 && max_ids < ha->tid_cnt) |
4419 | ha->tid_cnt = max_ids; | |
4420 | for (i=0; i<GDTH_MAXCMDS; ++i) | |
4421 | ha->cmd_tab[i].cmnd = UNUSED_CMND; | |
4422 | ha->scan_mode = rescan ? 0x10 : 0; | |
4423 | ||
4424 | err = FALSE; | |
4425 | if (ha->pscratch == NULL || ha->pmsg == NULL || | |
4426 | !gdth_search_drives(hanum)) { | |
4427 | err = TRUE; | |
4428 | } else { | |
4429 | if (hdr_channel < 0 || hdr_channel > ha->bus_cnt) | |
4430 | hdr_channel = ha->bus_cnt; | |
4431 | ha->virt_bus = hdr_channel; | |
4432 | ||
4433 | ||
12413197 | 4434 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) |
1da177e4 LT |
4435 | scsi_set_pci_device(shp, pcistr[ctr].pdev); |
4436 | #endif | |
4437 | if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)|| | |
4438 | /* 64-bit DMA only supported from FW >= x.43 */ | |
4439 | (!ha->dma64_support)) { | |
910638ae | 4440 | if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) { |
1da177e4 LT |
4441 | printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum); |
4442 | err = TRUE; | |
4443 | } | |
4444 | } else { | |
4445 | shp->max_cmd_len = 16; | |
910638ae | 4446 | if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) { |
1da177e4 | 4447 | printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum); |
910638ae | 4448 | } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) { |
1da177e4 LT |
4449 | printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum); |
4450 | err = TRUE; | |
4451 | } | |
4452 | } | |
4453 | } | |
4454 | ||
4455 | if (err) { | |
4456 | printk("GDT-PCI %d: Error during device scan\n", hanum); | |
4457 | --gdth_ctr_count; | |
4458 | --gdth_ctr_vcount; | |
4459 | #ifdef INT_COAL | |
4460 | if (ha->coal_stat) | |
4461 | pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * | |
4462 | MAXOFFSETS, ha->coal_stat, | |
4463 | ha->coal_stat_phys); | |
4464 | #endif | |
4465 | if (ha->pscratch) | |
4466 | pci_free_consistent(ha->pdev, GDTH_SCRATCH, | |
4467 | ha->pscratch, ha->scratch_phys); | |
4468 | if (ha->pmsg) | |
4469 | pci_free_consistent(ha->pdev, sizeof(gdth_msg_str), | |
4470 | ha->pmsg, ha->msg_phys); | |
4471 | free_irq(ha->irq,ha); | |
4472 | scsi_unregister(shp); | |
4473 | continue; | |
4474 | } | |
4475 | ||
4476 | shp->max_id = ha->tid_cnt; | |
4477 | shp->max_lun = MAXLUN; | |
4478 | shp->max_channel = virt_ctr ? 0 : ha->bus_cnt; | |
4479 | if (virt_ctr) { | |
4480 | virt_ctr = 1; | |
4481 | /* register addit. SCSI channels as virtual controllers */ | |
4482 | for (b = 1; b < ha->bus_cnt + 1; ++b) { | |
4483 | shp = scsi_register(shtp,sizeof(gdth_num_str)); | |
4484 | shp->unchecked_isa_dma = 0; | |
4485 | shp->irq = ha->irq; | |
4486 | shp->dma_channel = 0xff; | |
4487 | gdth_ctr_vtab[gdth_ctr_vcount++] = shp; | |
4488 | NUMDATA(shp)->hanum = (ushort)hanum; | |
4489 | NUMDATA(shp)->busnum = b; | |
4490 | } | |
4491 | } | |
4492 | ||
4493 | spin_lock_init(&ha->smp_lock); | |
4494 | gdth_enable_int(hanum); | |
4495 | } | |
4496 | ||
4497 | TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count)); | |
4498 | if (gdth_ctr_count > 0) { | |
4499 | #ifdef GDTH_STATISTICS | |
4500 | TRACE2(("gdth_detect(): Initializing timer !\n")); | |
4501 | init_timer(&gdth_timer); | |
4502 | gdth_timer.expires = jiffies + HZ; | |
4503 | gdth_timer.data = 0L; | |
4504 | gdth_timer.function = gdth_timeout; | |
4505 | add_timer(&gdth_timer); | |
4506 | #endif | |
4507 | major = register_chrdev(0,"gdth",&gdth_fops); | |
e041c683 | 4508 | notifier_disabled = 0; |
1da177e4 LT |
4509 | register_reboot_notifier(&gdth_notifier); |
4510 | } | |
4511 | gdth_polling = FALSE; | |
4512 | return gdth_ctr_vcount; | |
4513 | } | |
4514 | ||
8e879041 | 4515 | static int gdth_release(struct Scsi_Host *shp) |
1da177e4 LT |
4516 | { |
4517 | int hanum; | |
4518 | gdth_ha_str *ha; | |
4519 | ||
4520 | TRACE2(("gdth_release()\n")); | |
4521 | if (NUMDATA(shp)->busnum == 0) { | |
4522 | hanum = NUMDATA(shp)->hanum; | |
4523 | ha = HADATA(gdth_ctr_tab[hanum]); | |
4524 | if (ha->sdev) { | |
4525 | scsi_free_host_dev(ha->sdev); | |
4526 | ha->sdev = NULL; | |
4527 | } | |
4528 | gdth_flush(hanum); | |
4529 | ||
4530 | if (shp->irq) { | |
4531 | free_irq(shp->irq,ha); | |
4532 | } | |
aed91cb5 | 4533 | #ifdef CONFIG_ISA |
1da177e4 LT |
4534 | if (shp->dma_channel != 0xff) { |
4535 | free_dma(shp->dma_channel); | |
4536 | } | |
4537 | #endif | |
4538 | #ifdef INT_COAL | |
4539 | if (ha->coal_stat) | |
4540 | pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * | |
4541 | MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys); | |
4542 | #endif | |
4543 | if (ha->pscratch) | |
4544 | pci_free_consistent(ha->pdev, GDTH_SCRATCH, | |
4545 | ha->pscratch, ha->scratch_phys); | |
4546 | if (ha->pmsg) | |
4547 | pci_free_consistent(ha->pdev, sizeof(gdth_msg_str), | |
4548 | ha->pmsg, ha->msg_phys); | |
4549 | if (ha->ccb_phys) | |
4550 | pci_unmap_single(ha->pdev,ha->ccb_phys, | |
4551 | sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL); | |
4552 | gdth_ctr_released++; | |
4553 | TRACE2(("gdth_release(): HA %d of %d\n", | |
4554 | gdth_ctr_released, gdth_ctr_count)); | |
4555 | ||
4556 | if (gdth_ctr_released == gdth_ctr_count) { | |
4557 | #ifdef GDTH_STATISTICS | |
4558 | del_timer(&gdth_timer); | |
4559 | #endif | |
4560 | unregister_chrdev(major,"gdth"); | |
4561 | unregister_reboot_notifier(&gdth_notifier); | |
4562 | } | |
4563 | } | |
4564 | ||
4565 | scsi_unregister(shp); | |
4566 | return 0; | |
4567 | } | |
4568 | ||
4569 | ||
4570 | static const char *gdth_ctr_name(int hanum) | |
4571 | { | |
4572 | gdth_ha_str *ha; | |
4573 | ||
4574 | TRACE2(("gdth_ctr_name()\n")); | |
4575 | ||
4576 | ha = HADATA(gdth_ctr_tab[hanum]); | |
4577 | ||
4578 | if (ha->type == GDT_EISA) { | |
4579 | switch (ha->stype) { | |
4580 | case GDT3_ID: | |
4581 | return("GDT3000/3020"); | |
4582 | case GDT3A_ID: | |
4583 | return("GDT3000A/3020A/3050A"); | |
4584 | case GDT3B_ID: | |
4585 | return("GDT3000B/3010A"); | |
4586 | } | |
4587 | } else if (ha->type == GDT_ISA) { | |
4588 | return("GDT2000/2020"); | |
4589 | } else if (ha->type == GDT_PCI) { | |
8e9a8a0d | 4590 | switch (ha->pdev->device) { |
1da177e4 LT |
4591 | case PCI_DEVICE_ID_VORTEX_GDT60x0: |
4592 | return("GDT6000/6020/6050"); | |
4593 | case PCI_DEVICE_ID_VORTEX_GDT6000B: | |
4594 | return("GDT6000B/6010"); | |
4595 | } | |
4596 | } | |
4597 | /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */ | |
4598 | ||
4599 | return(""); | |
4600 | } | |
4601 | ||
8e879041 | 4602 | static const char *gdth_info(struct Scsi_Host *shp) |
1da177e4 LT |
4603 | { |
4604 | int hanum; | |
4605 | gdth_ha_str *ha; | |
4606 | ||
4607 | TRACE2(("gdth_info()\n")); | |
4608 | hanum = NUMDATA(shp)->hanum; | |
4609 | ha = HADATA(gdth_ctr_tab[hanum]); | |
4610 | ||
4611 | return ((const char *)ha->binfo.type_string); | |
4612 | } | |
4613 | ||
8e879041 | 4614 | static int gdth_eh_bus_reset(Scsi_Cmnd *scp) |
1da177e4 LT |
4615 | { |
4616 | int i, hanum; | |
4617 | gdth_ha_str *ha; | |
4618 | ulong flags; | |
4619 | Scsi_Cmnd *cmnd; | |
4620 | unchar b; | |
4621 | ||
4622 | TRACE2(("gdth_eh_bus_reset()\n")); | |
4623 | ||
4624 | hanum = NUMDATA(scp->device->host)->hanum; | |
4625 | b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel; | |
4626 | ha = HADATA(gdth_ctr_tab[hanum]); | |
4627 | ||
4628 | /* clear command tab */ | |
4629 | spin_lock_irqsave(&ha->smp_lock, flags); | |
4630 | for (i = 0; i < GDTH_MAXCMDS; ++i) { | |
4631 | cmnd = ha->cmd_tab[i].cmnd; | |
4632 | if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b) | |
4633 | ha->cmd_tab[i].cmnd = UNUSED_CMND; | |
4634 | } | |
4635 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
4636 | ||
4637 | if (b == ha->virt_bus) { | |
4638 | /* host drives */ | |
4639 | for (i = 0; i < MAX_HDRIVES; ++i) { | |
4640 | if (ha->hdr[i].present) { | |
4641 | spin_lock_irqsave(&ha->smp_lock, flags); | |
4642 | gdth_polling = TRUE; | |
4643 | while (gdth_test_busy(hanum)) | |
4644 | gdth_delay(0); | |
4645 | if (gdth_internal_cmd(hanum, CACHESERVICE, | |
4646 | GDT_CLUST_RESET, i, 0, 0)) | |
4647 | ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED; | |
4648 | gdth_polling = FALSE; | |
4649 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
4650 | } | |
4651 | } | |
4652 | } else { | |
4653 | /* raw devices */ | |
4654 | spin_lock_irqsave(&ha->smp_lock, flags); | |
4655 | for (i = 0; i < MAXID; ++i) | |
4656 | ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0; | |
4657 | gdth_polling = TRUE; | |
4658 | while (gdth_test_busy(hanum)) | |
4659 | gdth_delay(0); | |
4660 | gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS, | |
4661 | BUS_L2P(ha,b), 0, 0); | |
4662 | gdth_polling = FALSE; | |
cbd5f69b | 4663 | spin_unlock_irqrestore(&ha->smp_lock, flags); |
1da177e4 LT |
4664 | } |
4665 | return SUCCESS; | |
4666 | } | |
4667 | ||
1da177e4 | 4668 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) |
8e879041 | 4669 | static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip) |
1da177e4 | 4670 | #else |
8e879041 | 4671 | static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip) |
1da177e4 LT |
4672 | #endif |
4673 | { | |
4674 | unchar b, t; | |
4675 | int hanum; | |
4676 | gdth_ha_str *ha; | |
4677 | struct scsi_device *sd; | |
4678 | unsigned capacity; | |
4679 | ||
4680 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) | |
4681 | sd = sdev; | |
4682 | capacity = cap; | |
4683 | #else | |
4684 | sd = disk->device; | |
4685 | capacity = disk->capacity; | |
4686 | #endif | |
4687 | hanum = NUMDATA(sd->host)->hanum; | |
4688 | b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel; | |
4689 | t = sd->id; | |
4690 | TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t)); | |
4691 | ha = HADATA(gdth_ctr_tab[hanum]); | |
4692 | ||
4693 | if (b != ha->virt_bus || ha->hdr[t].heads == 0) { | |
4694 | /* raw device or host drive without mapping information */ | |
4695 | TRACE2(("Evaluate mapping\n")); | |
4696 | gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]); | |
4697 | } else { | |
4698 | ip[0] = ha->hdr[t].heads; | |
4699 | ip[1] = ha->hdr[t].secs; | |
4700 | ip[2] = capacity / ip[0] / ip[1]; | |
4701 | } | |
4702 | ||
4703 | TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n", | |
4704 | ip[0],ip[1],ip[2])); | |
4705 | return 0; | |
4706 | } | |
4707 | ||
4708 | ||
b8bff2ae MW |
4709 | static int gdth_queuecommand(struct scsi_cmnd *scp, |
4710 | void (*done)(struct scsi_cmnd *)) | |
1da177e4 LT |
4711 | { |
4712 | int hanum; | |
4713 | int priority; | |
4714 | ||
4715 | TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0])); | |
4716 | ||
b8bff2ae | 4717 | scp->scsi_done = done; |
1da177e4 LT |
4718 | scp->SCp.have_data_in = 1; |
4719 | scp->SCp.phase = -1; | |
4720 | scp->SCp.sent_command = -1; | |
4721 | scp->SCp.Status = GDTH_MAP_NONE; | |
4722 | scp->SCp.buffer = (struct scatterlist *)NULL; | |
4723 | ||
4724 | hanum = NUMDATA(scp->device->host)->hanum; | |
4725 | #ifdef GDTH_STATISTICS | |
4726 | ++act_ios; | |
4727 | #endif | |
4728 | ||
4729 | priority = DEFAULT_PRI; | |
687d2bc4 | 4730 | if (IS_GDTH_INTERNAL_CMD(scp)) |
1da177e4 | 4731 | priority = scp->SCp.this_residual; |
cbd5f69b LA |
4732 | else |
4733 | gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6); | |
4734 | ||
1da177e4 LT |
4735 | gdth_putq( hanum, scp, priority ); |
4736 | gdth_next( hanum ); | |
4737 | return 0; | |
4738 | } | |
4739 | ||
4740 | ||
4741 | static int gdth_open(struct inode *inode, struct file *filep) | |
4742 | { | |
4743 | gdth_ha_str *ha; | |
4744 | int i; | |
4745 | ||
4746 | for (i = 0; i < gdth_ctr_count; i++) { | |
4747 | ha = HADATA(gdth_ctr_tab[i]); | |
4748 | if (!ha->sdev) | |
4749 | ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]); | |
4750 | } | |
4751 | ||
4752 | TRACE(("gdth_open()\n")); | |
4753 | return 0; | |
4754 | } | |
4755 | ||
4756 | static int gdth_close(struct inode *inode, struct file *filep) | |
4757 | { | |
4758 | TRACE(("gdth_close()\n")); | |
4759 | return 0; | |
4760 | } | |
4761 | ||
4762 | static int ioc_event(void __user *arg) | |
4763 | { | |
4764 | gdth_ioctl_event evt; | |
4765 | gdth_ha_str *ha; | |
4766 | ulong flags; | |
4767 | ||
4768 | if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) || | |
4769 | evt.ionode >= gdth_ctr_count) | |
4770 | return -EFAULT; | |
4771 | ha = HADATA(gdth_ctr_tab[evt.ionode]); | |
4772 | ||
4773 | if (evt.erase == 0xff) { | |
4774 | if (evt.event.event_source == ES_TEST) | |
4775 | evt.event.event_data.size=sizeof(evt.event.event_data.eu.test); | |
4776 | else if (evt.event.event_source == ES_DRIVER) | |
4777 | evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver); | |
4778 | else if (evt.event.event_source == ES_SYNC) | |
4779 | evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync); | |
4780 | else | |
4781 | evt.event.event_data.size=sizeof(evt.event.event_data.eu.async); | |
4782 | spin_lock_irqsave(&ha->smp_lock, flags); | |
4783 | gdth_store_event(ha, evt.event.event_source, evt.event.event_idx, | |
4784 | &evt.event.event_data); | |
4785 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
4786 | } else if (evt.erase == 0xfe) { | |
4787 | gdth_clear_events(); | |
4788 | } else if (evt.erase == 0) { | |
4789 | evt.handle = gdth_read_event(ha, evt.handle, &evt.event); | |
4790 | } else { | |
4791 | gdth_readapp_event(ha, evt.erase, &evt.event); | |
4792 | } | |
4793 | if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event))) | |
4794 | return -EFAULT; | |
4795 | return 0; | |
4796 | } | |
4797 | ||
4798 | static int ioc_lockdrv(void __user *arg) | |
4799 | { | |
4800 | gdth_ioctl_lockdrv ldrv; | |
4801 | unchar i, j; | |
4802 | ulong flags; | |
4803 | gdth_ha_str *ha; | |
4804 | ||
4805 | if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) || | |
4806 | ldrv.ionode >= gdth_ctr_count) | |
4807 | return -EFAULT; | |
4808 | ha = HADATA(gdth_ctr_tab[ldrv.ionode]); | |
4809 | ||
4810 | for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) { | |
4811 | j = ldrv.drives[i]; | |
4812 | if (j >= MAX_HDRIVES || !ha->hdr[j].present) | |
4813 | continue; | |
4814 | if (ldrv.lock) { | |
4815 | spin_lock_irqsave(&ha->smp_lock, flags); | |
4816 | ha->hdr[j].lock = 1; | |
4817 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
4818 | gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j); | |
4819 | gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j); | |
4820 | } else { | |
4821 | spin_lock_irqsave(&ha->smp_lock, flags); | |
4822 | ha->hdr[j].lock = 0; | |
4823 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
4824 | gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j); | |
4825 | gdth_next(ldrv.ionode); | |
4826 | } | |
4827 | } | |
4828 | return 0; | |
4829 | } | |
4830 | ||
4831 | static int ioc_resetdrv(void __user *arg, char *cmnd) | |
4832 | { | |
4833 | gdth_ioctl_reset res; | |
4834 | gdth_cmd_str cmd; | |
4835 | int hanum; | |
4836 | gdth_ha_str *ha; | |
cbd5f69b | 4837 | int rval; |
1da177e4 LT |
4838 | |
4839 | if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) || | |
4840 | res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES) | |
4841 | return -EFAULT; | |
4842 | hanum = res.ionode; | |
4843 | ha = HADATA(gdth_ctr_tab[hanum]); | |
4844 | ||
4845 | if (!ha->hdr[res.number].present) | |
4846 | return 0; | |
4847 | memset(&cmd, 0, sizeof(gdth_cmd_str)); | |
4848 | cmd.Service = CACHESERVICE; | |
4849 | cmd.OpCode = GDT_CLUST_RESET; | |
4850 | if (ha->cache_feat & GDT_64BIT) | |
4851 | cmd.u.cache64.DeviceNo = res.number; | |
4852 | else | |
4853 | cmd.u.cache.DeviceNo = res.number; | |
cbd5f69b LA |
4854 | |
4855 | rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL); | |
4856 | if (rval < 0) | |
4857 | return rval; | |
4858 | res.status = rval; | |
1da177e4 LT |
4859 | |
4860 | if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset))) | |
4861 | return -EFAULT; | |
4862 | return 0; | |
4863 | } | |
4864 | ||
4865 | static int ioc_general(void __user *arg, char *cmnd) | |
4866 | { | |
4867 | gdth_ioctl_general gen; | |
4868 | char *buf = NULL; | |
4869 | ulong64 paddr; | |
4870 | int hanum; | |
cbd5f69b LA |
4871 | gdth_ha_str *ha; |
4872 | int rval; | |
1da177e4 LT |
4873 | |
4874 | if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) || | |
4875 | gen.ionode >= gdth_ctr_count) | |
4876 | return -EFAULT; | |
4877 | hanum = gen.ionode; | |
4878 | ha = HADATA(gdth_ctr_tab[hanum]); | |
4879 | if (gen.data_len + gen.sense_len != 0) { | |
4880 | if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len, | |
4881 | FALSE, &paddr))) | |
4882 | return -EFAULT; | |
4883 | if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general), | |
4884 | gen.data_len + gen.sense_len)) { | |
4885 | gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr); | |
4886 | return -EFAULT; | |
4887 | } | |
4888 | ||
4889 | if (gen.command.OpCode == GDT_IOCTL) { | |
4890 | gen.command.u.ioctl.p_param = paddr; | |
4891 | } else if (gen.command.Service == CACHESERVICE) { | |
4892 | if (ha->cache_feat & GDT_64BIT) { | |
4893 | /* copy elements from 32-bit IOCTL structure */ | |
4894 | gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt; | |
4895 | gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo; | |
4896 | gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo; | |
4897 | /* addresses */ | |
4898 | if (ha->cache_feat & SCATTER_GATHER) { | |
4899 | gen.command.u.cache64.DestAddr = (ulong64)-1; | |
4900 | gen.command.u.cache64.sg_canz = 1; | |
4901 | gen.command.u.cache64.sg_lst[0].sg_ptr = paddr; | |
4902 | gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len; | |
4903 | gen.command.u.cache64.sg_lst[1].sg_len = 0; | |
4904 | } else { | |
4905 | gen.command.u.cache64.DestAddr = paddr; | |
4906 | gen.command.u.cache64.sg_canz = 0; | |
4907 | } | |
4908 | } else { | |
4909 | if (ha->cache_feat & SCATTER_GATHER) { | |
4910 | gen.command.u.cache.DestAddr = 0xffffffff; | |
4911 | gen.command.u.cache.sg_canz = 1; | |
4912 | gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr; | |
4913 | gen.command.u.cache.sg_lst[0].sg_len = gen.data_len; | |
4914 | gen.command.u.cache.sg_lst[1].sg_len = 0; | |
4915 | } else { | |
4916 | gen.command.u.cache.DestAddr = paddr; | |
4917 | gen.command.u.cache.sg_canz = 0; | |
4918 | } | |
4919 | } | |
4920 | } else if (gen.command.Service == SCSIRAWSERVICE) { | |
4921 | if (ha->raw_feat & GDT_64BIT) { | |
4922 | /* copy elements from 32-bit IOCTL structure */ | |
4923 | char cmd[16]; | |
4924 | gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len; | |
4925 | gen.command.u.raw64.bus = gen.command.u.raw.bus; | |
4926 | gen.command.u.raw64.lun = gen.command.u.raw.lun; | |
4927 | gen.command.u.raw64.target = gen.command.u.raw.target; | |
4928 | memcpy(cmd, gen.command.u.raw.cmd, 16); | |
4929 | memcpy(gen.command.u.raw64.cmd, cmd, 16); | |
4930 | gen.command.u.raw64.clen = gen.command.u.raw.clen; | |
4931 | gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen; | |
4932 | gen.command.u.raw64.direction = gen.command.u.raw.direction; | |
4933 | /* addresses */ | |
4934 | if (ha->raw_feat & SCATTER_GATHER) { | |
4935 | gen.command.u.raw64.sdata = (ulong64)-1; | |
4936 | gen.command.u.raw64.sg_ranz = 1; | |
4937 | gen.command.u.raw64.sg_lst[0].sg_ptr = paddr; | |
4938 | gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len; | |
4939 | gen.command.u.raw64.sg_lst[1].sg_len = 0; | |
4940 | } else { | |
4941 | gen.command.u.raw64.sdata = paddr; | |
4942 | gen.command.u.raw64.sg_ranz = 0; | |
4943 | } | |
4944 | gen.command.u.raw64.sense_data = paddr + gen.data_len; | |
4945 | } else { | |
4946 | if (ha->raw_feat & SCATTER_GATHER) { | |
4947 | gen.command.u.raw.sdata = 0xffffffff; | |
4948 | gen.command.u.raw.sg_ranz = 1; | |
4949 | gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr; | |
4950 | gen.command.u.raw.sg_lst[0].sg_len = gen.data_len; | |
4951 | gen.command.u.raw.sg_lst[1].sg_len = 0; | |
4952 | } else { | |
4953 | gen.command.u.raw.sdata = paddr; | |
4954 | gen.command.u.raw.sg_ranz = 0; | |
4955 | } | |
4956 | gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len; | |
4957 | } | |
4958 | } else { | |
4959 | gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr); | |
4960 | return -EFAULT; | |
4961 | } | |
4962 | } | |
4963 | ||
cbd5f69b LA |
4964 | rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info); |
4965 | if (rval < 0) | |
4966 | return rval; | |
4967 | gen.status = rval; | |
1da177e4 LT |
4968 | |
4969 | if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf, | |
4970 | gen.data_len + gen.sense_len)) { | |
4971 | gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr); | |
4972 | return -EFAULT; | |
4973 | } | |
4974 | if (copy_to_user(arg, &gen, | |
4975 | sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) { | |
4976 | gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr); | |
4977 | return -EFAULT; | |
4978 | } | |
4979 | gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr); | |
4980 | return 0; | |
4981 | } | |
4982 | ||
4983 | static int ioc_hdrlist(void __user *arg, char *cmnd) | |
4984 | { | |
4985 | gdth_ioctl_rescan *rsc; | |
4986 | gdth_cmd_str *cmd; | |
4987 | gdth_ha_str *ha; | |
4988 | unchar i; | |
4989 | int hanum, rc = -ENOMEM; | |
cbd5f69b LA |
4990 | u32 cluster_type = 0; |
4991 | ||
1da177e4 LT |
4992 | rsc = kmalloc(sizeof(*rsc), GFP_KERNEL); |
4993 | cmd = kmalloc(sizeof(*cmd), GFP_KERNEL); | |
4994 | if (!rsc || !cmd) | |
cbd5f69b | 4995 | goto free_fail; |
1da177e4 LT |
4996 | |
4997 | if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) || | |
4998 | rsc->ionode >= gdth_ctr_count) { | |
4999 | rc = -EFAULT; | |
cbd5f69b | 5000 | goto free_fail; |
1da177e4 LT |
5001 | } |
5002 | hanum = rsc->ionode; | |
5003 | ha = HADATA(gdth_ctr_tab[hanum]); | |
5004 | memset(cmd, 0, sizeof(gdth_cmd_str)); | |
5005 | ||
1da177e4 LT |
5006 | for (i = 0; i < MAX_HDRIVES; ++i) { |
5007 | if (!ha->hdr[i].present) { | |
5008 | rsc->hdr_list[i].bus = 0xff; | |
5009 | continue; | |
5010 | } | |
5011 | rsc->hdr_list[i].bus = ha->virt_bus; | |
5012 | rsc->hdr_list[i].target = i; | |
5013 | rsc->hdr_list[i].lun = 0; | |
5014 | rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type; | |
5015 | if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) { | |
5016 | cmd->Service = CACHESERVICE; | |
5017 | cmd->OpCode = GDT_CLUST_INFO; | |
5018 | if (ha->cache_feat & GDT_64BIT) | |
5019 | cmd->u.cache64.DeviceNo = i; | |
5020 | else | |
5021 | cmd->u.cache.DeviceNo = i; | |
cbd5f69b LA |
5022 | if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK) |
5023 | rsc->hdr_list[i].cluster_type = cluster_type; | |
1da177e4 LT |
5024 | } |
5025 | } | |
cbd5f69b | 5026 | |
1da177e4 LT |
5027 | if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan))) |
5028 | rc = -EFAULT; | |
5029 | else | |
cbd5f69b | 5030 | rc = 0; |
1da177e4 LT |
5031 | |
5032 | free_fail: | |
5033 | kfree(rsc); | |
5034 | kfree(cmd); | |
5035 | return rc; | |
5036 | } | |
5037 | ||
5038 | static int ioc_rescan(void __user *arg, char *cmnd) | |
5039 | { | |
5040 | gdth_ioctl_rescan *rsc; | |
5041 | gdth_cmd_str *cmd; | |
5042 | ushort i, status, hdr_cnt; | |
5043 | ulong32 info; | |
5044 | int hanum, cyls, hds, secs; | |
5045 | int rc = -ENOMEM; | |
5046 | ulong flags; | |
5047 | gdth_ha_str *ha; | |
1da177e4 LT |
5048 | |
5049 | rsc = kmalloc(sizeof(*rsc), GFP_KERNEL); | |
5050 | cmd = kmalloc(sizeof(*cmd), GFP_KERNEL); | |
5051 | if (!cmd || !rsc) | |
cbd5f69b | 5052 | goto free_fail; |
1da177e4 LT |
5053 | |
5054 | if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) || | |
5055 | rsc->ionode >= gdth_ctr_count) { | |
cbd5f69b LA |
5056 | rc = -EFAULT; |
5057 | goto free_fail; | |
1da177e4 LT |
5058 | } |
5059 | hanum = rsc->ionode; | |
5060 | ha = HADATA(gdth_ctr_tab[hanum]); | |
5061 | memset(cmd, 0, sizeof(gdth_cmd_str)); | |
5062 | ||
1da177e4 LT |
5063 | if (rsc->flag == 0) { |
5064 | /* old method: re-init. cache service */ | |
5065 | cmd->Service = CACHESERVICE; | |
5066 | if (ha->cache_feat & GDT_64BIT) { | |
5067 | cmd->OpCode = GDT_X_INIT_HOST; | |
5068 | cmd->u.cache64.DeviceNo = LINUX_OS; | |
5069 | } else { | |
5070 | cmd->OpCode = GDT_INIT; | |
5071 | cmd->u.cache.DeviceNo = LINUX_OS; | |
5072 | } | |
cbd5f69b LA |
5073 | |
5074 | status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info); | |
1da177e4 LT |
5075 | i = 0; |
5076 | hdr_cnt = (status == S_OK ? (ushort)info : 0); | |
5077 | } else { | |
5078 | i = rsc->hdr_no; | |
5079 | hdr_cnt = i + 1; | |
5080 | } | |
5081 | ||
5082 | for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) { | |
5083 | cmd->Service = CACHESERVICE; | |
5084 | cmd->OpCode = GDT_INFO; | |
5085 | if (ha->cache_feat & GDT_64BIT) | |
5086 | cmd->u.cache64.DeviceNo = i; | |
5087 | else | |
5088 | cmd->u.cache.DeviceNo = i; | |
cbd5f69b LA |
5089 | |
5090 | status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info); | |
5091 | ||
1da177e4 LT |
5092 | spin_lock_irqsave(&ha->smp_lock, flags); |
5093 | rsc->hdr_list[i].bus = ha->virt_bus; | |
5094 | rsc->hdr_list[i].target = i; | |
5095 | rsc->hdr_list[i].lun = 0; | |
5096 | if (status != S_OK) { | |
5097 | ha->hdr[i].present = FALSE; | |
5098 | } else { | |
5099 | ha->hdr[i].present = TRUE; | |
5100 | ha->hdr[i].size = info; | |
5101 | /* evaluate mapping */ | |
5102 | ha->hdr[i].size &= ~SECS32; | |
5103 | gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs); | |
5104 | ha->hdr[i].heads = hds; | |
5105 | ha->hdr[i].secs = secs; | |
5106 | /* round size */ | |
5107 | ha->hdr[i].size = cyls * hds * secs; | |
5108 | } | |
5109 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
5110 | if (status != S_OK) | |
5111 | continue; | |
5112 | ||
5113 | /* extended info, if GDT_64BIT, for drives > 2 TB */ | |
5114 | /* but we need ha->info2, not yet stored in scp->SCp */ | |
5115 | ||
5116 | /* devtype, cluster info, R/W attribs */ | |
5117 | cmd->Service = CACHESERVICE; | |
5118 | cmd->OpCode = GDT_DEVTYPE; | |
5119 | if (ha->cache_feat & GDT_64BIT) | |
5120 | cmd->u.cache64.DeviceNo = i; | |
5121 | else | |
5122 | cmd->u.cache.DeviceNo = i; | |
cbd5f69b LA |
5123 | |
5124 | status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info); | |
5125 | ||
1da177e4 LT |
5126 | spin_lock_irqsave(&ha->smp_lock, flags); |
5127 | ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0); | |
5128 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
5129 | ||
5130 | cmd->Service = CACHESERVICE; | |
5131 | cmd->OpCode = GDT_CLUST_INFO; | |
5132 | if (ha->cache_feat & GDT_64BIT) | |
5133 | cmd->u.cache64.DeviceNo = i; | |
5134 | else | |
5135 | cmd->u.cache.DeviceNo = i; | |
cbd5f69b LA |
5136 | |
5137 | status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info); | |
5138 | ||
1da177e4 LT |
5139 | spin_lock_irqsave(&ha->smp_lock, flags); |
5140 | ha->hdr[i].cluster_type = | |
5141 | ((status == S_OK && !shared_access) ? (ushort)info : 0); | |
5142 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
5143 | rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type; | |
5144 | ||
5145 | cmd->Service = CACHESERVICE; | |
5146 | cmd->OpCode = GDT_RW_ATTRIBS; | |
5147 | if (ha->cache_feat & GDT_64BIT) | |
5148 | cmd->u.cache64.DeviceNo = i; | |
5149 | else | |
5150 | cmd->u.cache.DeviceNo = i; | |
cbd5f69b LA |
5151 | |
5152 | status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info); | |
5153 | ||
1da177e4 LT |
5154 | spin_lock_irqsave(&ha->smp_lock, flags); |
5155 | ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0); | |
5156 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
5157 | } | |
1da177e4 LT |
5158 | |
5159 | if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan))) | |
5160 | rc = -EFAULT; | |
5161 | else | |
cbd5f69b | 5162 | rc = 0; |
1da177e4 LT |
5163 | |
5164 | free_fail: | |
5165 | kfree(rsc); | |
5166 | kfree(cmd); | |
5167 | return rc; | |
5168 | } | |
5169 | ||
5170 | static int gdth_ioctl(struct inode *inode, struct file *filep, | |
5171 | unsigned int cmd, unsigned long arg) | |
5172 | { | |
5173 | gdth_ha_str *ha; | |
5174 | Scsi_Cmnd *scp; | |
5175 | ulong flags; | |
5176 | char cmnd[MAX_COMMAND_SIZE]; | |
5177 | void __user *argp = (void __user *)arg; | |
5178 | ||
5179 | memset(cmnd, 0xff, 12); | |
5180 | ||
5181 | TRACE(("gdth_ioctl() cmd 0x%x\n", cmd)); | |
5182 | ||
5183 | switch (cmd) { | |
5184 | case GDTIOCTL_CTRCNT: | |
5185 | { | |
5186 | int cnt = gdth_ctr_count; | |
5187 | if (put_user(cnt, (int __user *)argp)) | |
5188 | return -EFAULT; | |
5189 | break; | |
5190 | } | |
5191 | ||
5192 | case GDTIOCTL_DRVERS: | |
5193 | { | |
5194 | int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION; | |
5195 | if (put_user(ver, (int __user *)argp)) | |
5196 | return -EFAULT; | |
5197 | break; | |
5198 | } | |
5199 | ||
5200 | case GDTIOCTL_OSVERS: | |
5201 | { | |
5202 | gdth_ioctl_osvers osv; | |
5203 | ||
5204 | osv.version = (unchar)(LINUX_VERSION_CODE >> 16); | |
5205 | osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8); | |
5206 | osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff); | |
5207 | if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers))) | |
5208 | return -EFAULT; | |
5209 | break; | |
5210 | } | |
5211 | ||
5212 | case GDTIOCTL_CTRTYPE: | |
5213 | { | |
5214 | gdth_ioctl_ctrtype ctrt; | |
5215 | ||
5216 | if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) || | |
5217 | ctrt.ionode >= gdth_ctr_count) | |
5218 | return -EFAULT; | |
5219 | ha = HADATA(gdth_ctr_tab[ctrt.ionode]); | |
5220 | if (ha->type == GDT_ISA || ha->type == GDT_EISA) { | |
5221 | ctrt.type = (unchar)((ha->stype>>20) - 0x10); | |
5222 | } else { | |
5223 | if (ha->type != GDT_PCIMPR) { | |
5224 | ctrt.type = (unchar)((ha->stype<<4) + 6); | |
5225 | } else { | |
5226 | ctrt.type = | |
5227 | (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe); | |
5228 | if (ha->stype >= 0x300) | |
8e9a8a0d | 5229 | ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device; |
1da177e4 LT |
5230 | else |
5231 | ctrt.ext_type = 0x6000 | ha->stype; | |
5232 | } | |
8e9a8a0d JG |
5233 | ctrt.device_id = ha->pdev->device; |
5234 | ctrt.sub_device_id = ha->pdev->subsystem_device; | |
1da177e4 LT |
5235 | } |
5236 | ctrt.info = ha->brd_phys; | |
5237 | ctrt.oem_id = ha->oem_id; | |
5238 | if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype))) | |
5239 | return -EFAULT; | |
5240 | break; | |
5241 | } | |
5242 | ||
5243 | case GDTIOCTL_GENERAL: | |
5244 | return ioc_general(argp, cmnd); | |
5245 | ||
5246 | case GDTIOCTL_EVENT: | |
5247 | return ioc_event(argp); | |
5248 | ||
5249 | case GDTIOCTL_LOCKDRV: | |
5250 | return ioc_lockdrv(argp); | |
5251 | ||
5252 | case GDTIOCTL_LOCKCHN: | |
5253 | { | |
5254 | gdth_ioctl_lockchn lchn; | |
5255 | unchar i, j; | |
5256 | ||
5257 | if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) || | |
5258 | lchn.ionode >= gdth_ctr_count) | |
5259 | return -EFAULT; | |
5260 | ha = HADATA(gdth_ctr_tab[lchn.ionode]); | |
5261 | ||
5262 | i = lchn.channel; | |
5263 | if (i < ha->bus_cnt) { | |
5264 | if (lchn.lock) { | |
5265 | spin_lock_irqsave(&ha->smp_lock, flags); | |
5266 | ha->raw[i].lock = 1; | |
5267 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
5268 | for (j = 0; j < ha->tid_cnt; ++j) { | |
5269 | gdth_wait_completion(lchn.ionode, i, j); | |
5270 | gdth_stop_timeout(lchn.ionode, i, j); | |
5271 | } | |
5272 | } else { | |
5273 | spin_lock_irqsave(&ha->smp_lock, flags); | |
5274 | ha->raw[i].lock = 0; | |
5275 | spin_unlock_irqrestore(&ha->smp_lock, flags); | |
5276 | for (j = 0; j < ha->tid_cnt; ++j) { | |
5277 | gdth_start_timeout(lchn.ionode, i, j); | |
5278 | gdth_next(lchn.ionode); | |
5279 | } | |
5280 | } | |
5281 | } | |
5282 | break; | |
5283 | } | |
5284 | ||
5285 | case GDTIOCTL_RESCAN: | |
5286 | return ioc_rescan(argp, cmnd); | |
5287 | ||
5288 | case GDTIOCTL_HDRLIST: | |
5289 | return ioc_hdrlist(argp, cmnd); | |
5290 | ||
5291 | case GDTIOCTL_RESET_BUS: | |
5292 | { | |
5293 | gdth_ioctl_reset res; | |
5294 | int hanum, rval; | |
5295 | ||
5296 | if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) || | |
5297 | res.ionode >= gdth_ctr_count) | |
5298 | return -EFAULT; | |
5299 | hanum = res.ionode; | |
5300 | ha = HADATA(gdth_ctr_tab[hanum]); | |
5301 | ||
1da177e4 | 5302 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) |
bbfbbbc1 | 5303 | scp = kzalloc(sizeof(*scp), GFP_KERNEL); |
1da177e4 LT |
5304 | if (!scp) |
5305 | return -ENOMEM; | |
cbd5f69b | 5306 | scp->device = ha->sdev; |
1da177e4 LT |
5307 | scp->cmd_len = 12; |
5308 | scp->use_sg = 0; | |
5309 | scp->device->channel = virt_ctr ? 0 : res.number; | |
5310 | rval = gdth_eh_bus_reset(scp); | |
5311 | res.status = (rval == SUCCESS ? S_OK : S_GENERR); | |
cbd5f69b | 5312 | kfree(scp); |
1da177e4 LT |
5313 | #else |
5314 | scp = scsi_allocate_device(ha->sdev, 1, FALSE); | |
5315 | if (!scp) | |
5316 | return -ENOMEM; | |
5317 | scp->cmd_len = 12; | |
5318 | scp->use_sg = 0; | |
5319 | scp->channel = virt_ctr ? 0 : res.number; | |
5320 | rval = gdth_eh_bus_reset(scp); | |
5321 | res.status = (rval == SUCCESS ? S_OK : S_GENERR); | |
5322 | scsi_release_command(scp); | |
5323 | #endif | |
5324 | if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset))) | |
5325 | return -EFAULT; | |
5326 | break; | |
5327 | } | |
5328 | ||
5329 | case GDTIOCTL_RESET_DRV: | |
5330 | return ioc_resetdrv(argp, cmnd); | |
5331 | ||
5332 | default: | |
5333 | break; | |
5334 | } | |
5335 | return 0; | |
5336 | } | |
5337 | ||
5338 | ||
5339 | /* flush routine */ | |
5340 | static void gdth_flush(int hanum) | |
5341 | { | |
5342 | int i; | |
5343 | gdth_ha_str *ha; | |
5344 | gdth_cmd_str gdtcmd; | |
1da177e4 LT |
5345 | char cmnd[MAX_COMMAND_SIZE]; |
5346 | memset(cmnd, 0xff, MAX_COMMAND_SIZE); | |
5347 | ||
5348 | TRACE2(("gdth_flush() hanum %d\n",hanum)); | |
5349 | ha = HADATA(gdth_ctr_tab[hanum]); | |
5350 | ||
1da177e4 LT |
5351 | for (i = 0; i < MAX_HDRIVES; ++i) { |
5352 | if (ha->hdr[i].present) { | |
5353 | gdtcmd.BoardNode = LOCALBOARD; | |
5354 | gdtcmd.Service = CACHESERVICE; | |
5355 | gdtcmd.OpCode = GDT_FLUSH; | |
5356 | if (ha->cache_feat & GDT_64BIT) { | |
5357 | gdtcmd.u.cache64.DeviceNo = i; | |
5358 | gdtcmd.u.cache64.BlockNo = 1; | |
5359 | gdtcmd.u.cache64.sg_canz = 0; | |
5360 | } else { | |
5361 | gdtcmd.u.cache.DeviceNo = i; | |
5362 | gdtcmd.u.cache.BlockNo = 1; | |
5363 | gdtcmd.u.cache.sg_canz = 0; | |
5364 | } | |
5365 | TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i)); | |
cbd5f69b LA |
5366 | |
5367 | gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL); | |
1da177e4 LT |
5368 | } |
5369 | } | |
1da177e4 LT |
5370 | } |
5371 | ||
5372 | /* shutdown routine */ | |
5373 | static int gdth_halt(struct notifier_block *nb, ulong event, void *buf) | |
5374 | { | |
5375 | int hanum; | |
5376 | #ifndef __alpha__ | |
5377 | gdth_cmd_str gdtcmd; | |
1da177e4 LT |
5378 | char cmnd[MAX_COMMAND_SIZE]; |
5379 | #endif | |
5380 | ||
e041c683 | 5381 | if (notifier_disabled) |
cbd5f69b | 5382 | return NOTIFY_OK; |
e041c683 | 5383 | |
1da177e4 LT |
5384 | TRACE2(("gdth_halt() event %d\n",(int)event)); |
5385 | if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF) | |
5386 | return NOTIFY_DONE; | |
5387 | ||
e041c683 | 5388 | notifier_disabled = 1; |
1da177e4 LT |
5389 | printk("GDT-HA: Flushing all host drives .. "); |
5390 | for (hanum = 0; hanum < gdth_ctr_count; ++hanum) { | |
5391 | gdth_flush(hanum); | |
5392 | ||
5393 | #ifndef __alpha__ | |
5394 | /* controller reset */ | |
5395 | memset(cmnd, 0xff, MAX_COMMAND_SIZE); | |
5396 | gdtcmd.BoardNode = LOCALBOARD; | |
5397 | gdtcmd.Service = CACHESERVICE; | |
5398 | gdtcmd.OpCode = GDT_RESET; | |
5399 | TRACE2(("gdth_halt(): reset controller %d\n", hanum)); | |
cbd5f69b | 5400 | gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL); |
1da177e4 LT |
5401 | #endif |
5402 | } | |
5403 | printk("Done.\n"); | |
5404 | ||
5405 | #ifdef GDTH_STATISTICS | |
5406 | del_timer(&gdth_timer); | |
5407 | #endif | |
1da177e4 LT |
5408 | return NOTIFY_OK; |
5409 | } | |
5410 | ||
cbd5f69b LA |
5411 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) |
5412 | /* configure lun */ | |
5413 | static int gdth_slave_configure(struct scsi_device *sdev) | |
5414 | { | |
5415 | scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun); | |
5416 | sdev->skip_ms_page_3f = 1; | |
5417 | sdev->skip_ms_page_8 = 1; | |
5418 | return 0; | |
5419 | } | |
5420 | #endif | |
5421 | ||
5422 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) | |
d0be4a7d | 5423 | static struct scsi_host_template driver_template = { |
cbd5f69b LA |
5424 | #else |
5425 | static Scsi_Host_Template driver_template = { | |
5426 | #endif | |
1da177e4 LT |
5427 | .proc_name = "gdth", |
5428 | .proc_info = gdth_proc_info, | |
5429 | .name = "GDT SCSI Disk Array Controller", | |
5430 | .detect = gdth_detect, | |
5431 | .release = gdth_release, | |
5432 | .info = gdth_info, | |
5433 | .queuecommand = gdth_queuecommand, | |
1da177e4 | 5434 | .eh_bus_reset_handler = gdth_eh_bus_reset, |
1da177e4 LT |
5435 | .bios_param = gdth_bios_param, |
5436 | .can_queue = GDTH_MAXCMDS, | |
cbd5f69b LA |
5437 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) |
5438 | .slave_configure = gdth_slave_configure, | |
5439 | #endif | |
1da177e4 LT |
5440 | .this_id = -1, |
5441 | .sg_tablesize = GDTH_MAXSG, | |
5442 | .cmd_per_lun = GDTH_MAXC_P_L, | |
5443 | .unchecked_isa_dma = 1, | |
5444 | .use_clustering = ENABLE_CLUSTERING, | |
5445 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) | |
5446 | .use_new_eh_code = 1, | |
5447 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) | |
5448 | .highmem_io = 1, | |
5449 | #endif | |
5450 | #endif | |
5451 | }; | |
5452 | ||
aed91cb5 CH |
5453 | #ifdef CONFIG_ISA |
5454 | static int gdth_isa_probe_one(struct scsi_host_template *shtp, ulong32 isa_bios) | |
5455 | { | |
5456 | struct Scsi_Host *shp; | |
5457 | gdth_ha_str *ha; | |
5458 | dma_addr_t scratch_dma_handle = 0; | |
5459 | int error, hanum, i; | |
5460 | u8 b; | |
5461 | ||
5462 | if (!gdth_search_isa(isa_bios)) | |
5463 | return -ENXIO; | |
5464 | ||
5465 | shp = scsi_register(shtp, sizeof(gdth_ext_str)); | |
5466 | if (!shp) | |
5467 | return -ENOMEM; | |
5468 | ha = HADATA(shp); | |
5469 | ||
5470 | error = -ENODEV; | |
5471 | if (!gdth_init_isa(isa_bios,ha)) | |
5472 | goto out_host_put; | |
5473 | ||
5474 | /* controller found and initialized */ | |
5475 | printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n", | |
5476 | isa_bios, ha->irq, ha->drq); | |
5477 | ||
5478 | error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha); | |
5479 | if (error) { | |
5480 | printk("GDT-ISA: Unable to allocate IRQ\n"); | |
5481 | goto out_host_put; | |
5482 | } | |
5483 | ||
5484 | error = request_dma(ha->drq, "gdth"); | |
5485 | if (error) { | |
5486 | printk("GDT-ISA: Unable to allocate DMA channel\n"); | |
5487 | goto out_free_irq; | |
5488 | } | |
5489 | ||
5490 | set_dma_mode(ha->drq,DMA_MODE_CASCADE); | |
5491 | enable_dma(ha->drq); | |
5492 | shp->unchecked_isa_dma = 1; | |
5493 | shp->irq = ha->irq; | |
5494 | shp->dma_channel = ha->drq; | |
5495 | hanum = gdth_ctr_count; | |
5496 | gdth_ctr_tab[gdth_ctr_count++] = shp; | |
5497 | gdth_ctr_vtab[gdth_ctr_vcount++] = shp; | |
5498 | ||
5499 | NUMDATA(shp)->hanum = (ushort)hanum; | |
5500 | NUMDATA(shp)->busnum= 0; | |
5501 | ||
5502 | ha->pccb = CMDDATA(shp); | |
5503 | ha->ccb_phys = 0L; | |
5504 | ha->pdev = NULL; | |
5505 | ||
5506 | error = -ENOMEM; | |
5507 | ||
5508 | ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH, | |
5509 | &scratch_dma_handle); | |
5510 | if (!ha->pscratch) | |
5511 | goto out_dec_counters; | |
5512 | ha->scratch_phys = scratch_dma_handle; | |
5513 | ||
5514 | ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str), | |
5515 | &scratch_dma_handle); | |
5516 | if (!ha->pmsg) | |
5517 | goto out_free_pscratch; | |
5518 | ha->msg_phys = scratch_dma_handle; | |
5519 | ||
5520 | #ifdef INT_COAL | |
5521 | ha->coal_stat = pci_alloc_consistent(ha->pdev, | |
5522 | sizeof(gdth_coal_status) * MAXOFFSETS, | |
5523 | &scratch_dma_handle); | |
5524 | if (!ha->coal_stat) | |
5525 | goto out_free_pmsg; | |
5526 | ha->coal_stat_phys = scratch_dma_handle; | |
5527 | #endif | |
5528 | ||
5529 | ha->scratch_busy = FALSE; | |
5530 | ha->req_first = NULL; | |
5531 | ha->tid_cnt = MAX_HDRIVES; | |
5532 | if (max_ids > 0 && max_ids < ha->tid_cnt) | |
5533 | ha->tid_cnt = max_ids; | |
5534 | for (i = 0; i < GDTH_MAXCMDS; ++i) | |
5535 | ha->cmd_tab[i].cmnd = UNUSED_CMND; | |
5536 | ha->scan_mode = rescan ? 0x10 : 0; | |
5537 | ||
5538 | error = -ENODEV; | |
5539 | if (!gdth_search_drives(hanum)) { | |
5540 | printk("GDT-ISA: Error during device scan\n"); | |
5541 | goto out_free_coal_stat; | |
5542 | } | |
5543 | ||
5544 | if (hdr_channel < 0 || hdr_channel > ha->bus_cnt) | |
5545 | hdr_channel = ha->bus_cnt; | |
5546 | ha->virt_bus = hdr_channel; | |
5547 | ||
5548 | if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) | |
5549 | shp->max_cmd_len = 16; | |
5550 | ||
5551 | shp->max_id = ha->tid_cnt; | |
5552 | shp->max_lun = MAXLUN; | |
5553 | shp->max_channel = virt_ctr ? 0 : ha->bus_cnt; | |
5554 | if (virt_ctr) { | |
5555 | virt_ctr = 1; | |
5556 | /* register addit. SCSI channels as virtual controllers */ | |
5557 | for (b = 1; b < ha->bus_cnt + 1; ++b) { | |
5558 | shp = scsi_register(shtp,sizeof(gdth_num_str)); | |
5559 | shp->unchecked_isa_dma = 1; | |
5560 | shp->irq = ha->irq; | |
5561 | shp->dma_channel = ha->drq; | |
5562 | gdth_ctr_vtab[gdth_ctr_vcount++] = shp; | |
5563 | NUMDATA(shp)->hanum = (ushort)hanum; | |
5564 | NUMDATA(shp)->busnum = b; | |
5565 | } | |
5566 | } | |
5567 | ||
5568 | spin_lock_init(&ha->smp_lock); | |
5569 | gdth_enable_int(hanum); | |
5570 | ||
5571 | return 0; | |
5572 | ||
5573 | out_free_coal_stat: | |
5574 | #ifdef INT_COAL | |
5575 | pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS, | |
5576 | ha->coal_stat, ha->coal_stat_phys); | |
5577 | out_free_pmsg: | |
5578 | #endif | |
5579 | pci_free_consistent(ha->pdev, sizeof(gdth_msg_str), | |
5580 | ha->pmsg, ha->msg_phys); | |
5581 | out_free_pscratch: | |
5582 | pci_free_consistent(ha->pdev, GDTH_SCRATCH, | |
5583 | ha->pscratch, ha->scratch_phys); | |
5584 | out_dec_counters: | |
5585 | gdth_ctr_count--; | |
5586 | gdth_ctr_vcount--; | |
5587 | out_free_irq: | |
5588 | free_irq(ha->irq, ha); | |
5589 | out_host_put: | |
5590 | scsi_unregister(shp); | |
5591 | return error; | |
5592 | } | |
5593 | #endif /* CONFIG_ISA */ | |
5594 | ||
706a5d45 CH |
5595 | #ifdef CONFIG_EISA |
5596 | static int gdth_eisa_probe_one(struct scsi_host_template *shtp, | |
5597 | ushort eisa_slot) | |
5598 | { | |
5599 | struct Scsi_Host *shp; | |
5600 | gdth_ha_str *ha; | |
5601 | dma_addr_t scratch_dma_handle = 0; | |
5602 | int error, hanum, i; | |
5603 | u8 b; | |
5604 | ||
5605 | if (!gdth_search_eisa(eisa_slot)) | |
5606 | return -ENXIO; | |
5607 | ||
5608 | shp = scsi_register(shtp,sizeof(gdth_ext_str)); | |
5609 | if (!shp) | |
5610 | return -ENOMEM; | |
5611 | ha = HADATA(shp); | |
5612 | ||
5613 | error = -ENODEV; | |
5614 | if (!gdth_init_eisa(eisa_slot,ha)) | |
5615 | goto out_host_put; | |
5616 | ||
5617 | /* controller found and initialized */ | |
5618 | printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n", | |
5619 | eisa_slot >> 12, ha->irq); | |
5620 | ||
5621 | error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha); | |
5622 | if (error) { | |
5623 | printk("GDT-EISA: Unable to allocate IRQ\n"); | |
5624 | goto out_host_put; | |
5625 | } | |
5626 | ||
5627 | shp->unchecked_isa_dma = 0; | |
5628 | shp->irq = ha->irq; | |
5629 | shp->dma_channel = 0xff; | |
5630 | hanum = gdth_ctr_count; | |
5631 | gdth_ctr_tab[gdth_ctr_count++] = shp; | |
5632 | gdth_ctr_vtab[gdth_ctr_vcount++] = shp; | |
5633 | ||
5634 | NUMDATA(shp)->hanum = (ushort)hanum; | |
5635 | NUMDATA(shp)->busnum= 0; | |
5636 | TRACE2(("EISA detect Bus 0: hanum %d\n", | |
5637 | NUMDATA(shp)->hanum)); | |
5638 | ||
5639 | ha->pccb = CMDDATA(shp); | |
5640 | ha->ccb_phys = 0L; | |
5641 | ||
5642 | error = -ENOMEM; | |
5643 | ||
5644 | ha->pdev = NULL; | |
5645 | ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH, | |
5646 | &scratch_dma_handle); | |
5647 | if (!ha->pscratch) | |
5648 | goto out_free_irq; | |
5649 | ha->scratch_phys = scratch_dma_handle; | |
5650 | ||
5651 | ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str), | |
5652 | &scratch_dma_handle); | |
5653 | if (!ha->pmsg) | |
5654 | goto out_free_pscratch; | |
5655 | ha->msg_phys = scratch_dma_handle; | |
5656 | ||
5657 | #ifdef INT_COAL | |
5658 | ha->coal_stat = pci_alloc_consistent(ha->pdev, | |
5659 | sizeof(gdth_coal_status) * MAXOFFSETS, | |
5660 | &scratch_dma_handle); | |
5661 | if (!ha->coal_stat) | |
5662 | goto out_free_pmsg; | |
5663 | ha->coal_stat_phys = scratch_dma_handle; | |
5664 | #endif | |
5665 | ||
5666 | ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb, | |
5667 | sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL); | |
5668 | if (!ha->ccb_phys) | |
5669 | goto out_free_coal_stat; | |
5670 | ||
5671 | ha->scratch_busy = FALSE; | |
5672 | ha->req_first = NULL; | |
5673 | ha->tid_cnt = MAX_HDRIVES; | |
5674 | if (max_ids > 0 && max_ids < ha->tid_cnt) | |
5675 | ha->tid_cnt = max_ids; | |
5676 | for (i = 0; i < GDTH_MAXCMDS; ++i) | |
5677 | ha->cmd_tab[i].cmnd = UNUSED_CMND; | |
5678 | ha->scan_mode = rescan ? 0x10 : 0; | |
5679 | ||
5680 | if (!gdth_search_drives(hanum)) { | |
5681 | printk("GDT-EISA: Error during device scan\n"); | |
5682 | error = -ENODEV; | |
5683 | goto out_free_ccb_phys; | |
5684 | } | |
5685 | ||
5686 | if (hdr_channel < 0 || hdr_channel > ha->bus_cnt) | |
5687 | hdr_channel = ha->bus_cnt; | |
5688 | ha->virt_bus = hdr_channel; | |
5689 | ||
5690 | if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) | |
5691 | shp->max_cmd_len = 16; | |
5692 | ||
5693 | shp->max_id = ha->tid_cnt; | |
5694 | shp->max_lun = MAXLUN; | |
5695 | shp->max_channel = virt_ctr ? 0 : ha->bus_cnt; | |
5696 | if (virt_ctr) { | |
5697 | virt_ctr = 1; | |
5698 | /* register addit. SCSI channels as virtual controllers */ | |
5699 | for (b = 1; b < ha->bus_cnt + 1; ++b) { | |
5700 | shp = scsi_register(shtp,sizeof(gdth_num_str)); | |
5701 | shp->unchecked_isa_dma = 0; | |
5702 | shp->irq = ha->irq; | |
5703 | shp->dma_channel = 0xff; | |
5704 | gdth_ctr_vtab[gdth_ctr_vcount++] = shp; | |
5705 | NUMDATA(shp)->hanum = (ushort)hanum; | |
5706 | NUMDATA(shp)->busnum = b; | |
5707 | } | |
5708 | } | |
5709 | ||
5710 | spin_lock_init(&ha->smp_lock); | |
5711 | gdth_enable_int(hanum); | |
5712 | return 0; | |
5713 | ||
5714 | out_free_ccb_phys: | |
5715 | pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str), | |
5716 | PCI_DMA_BIDIRECTIONAL); | |
5717 | out_free_coal_stat: | |
5718 | #ifdef INT_COAL | |
5719 | pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS, | |
5720 | ha->coal_stat, ha->coal_stat_phys); | |
5721 | out_free_pmsg: | |
5722 | #endif | |
5723 | pci_free_consistent(ha->pdev, sizeof(gdth_msg_str), | |
5724 | ha->pmsg, ha->msg_phys); | |
5725 | out_free_pscratch: | |
5726 | pci_free_consistent(ha->pdev, GDTH_SCRATCH, | |
5727 | ha->pscratch, ha->scratch_phys); | |
5728 | out_free_irq: | |
5729 | free_irq(ha->irq, ha); | |
5730 | gdth_ctr_count--; | |
5731 | gdth_ctr_vcount--; | |
5732 | out_host_put: | |
5733 | scsi_unregister(shp); | |
5734 | return error; | |
5735 | } | |
5736 | #endif /* CONFIG_EISA */ | |
aed91cb5 | 5737 | |
1da177e4 LT |
5738 | #include "scsi_module.c" |
5739 | #ifndef MODULE | |
5740 | __setup("gdth=", option_setup); | |
5741 | #endif |