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[SCSI] gdth: Remove 2.4.x support, in-kernel changelog
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / gdth.c
CommitLineData
1da177e4
LT		 1/************************************************************************
2 * Linux driver for *
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
5 * *
6 * gdth.c *
cbd5f69b 7 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
1da177e4 8 * Copyright (C) 2002-04 Intel Corporation *
cbd5f69b 9 * Copyright (C) 2003-06 Adaptec Inc. *
1da177e4
LT		 10 * <achim_leubner@adaptec.com> *
11 * *
12 * Additions/Fixes: *
13 * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14 * Johannes Dinner <johannes_dinner@adaptec.com> *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
29 * *
8d7a5da4 30 * Linux kernel 2.6.x supported *
1da177e4 31 * *
1da177e4
LT		 32 ************************************************************************/
33
34/* All GDT Disk Array Controllers are fully supported by this driver.
35 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
36 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
37 * list of all controller types.
38 *
39 * If you have one or more GDT3000/3020 EISA controllers with
40 * controller BIOS disabled, you have to set the IRQ values with the
41 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
42 * the IRQ values for the EISA controllers.
43 *
44 * After the optional list of IRQ values, other possible
45 * command line options are:
46 * disable:Y disable driver
47 * disable:N enable driver
48 * reserve_mode:0 reserve no drives for the raw service
49 * reserve_mode:1 reserve all not init., removable drives
50 * reserve_mode:2 reserve all not init. drives
51 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
52 * h- controller no., b- channel no.,
53 * t- target ID, l- LUN
54 * reverse_scan:Y reverse scan order for PCI controllers
55 * reverse_scan:N scan PCI controllers like BIOS
56 * max_ids:x x - target ID count per channel (1..MAXID)
57 * rescan:Y rescan all channels/IDs
58 * rescan:N use all devices found until now
59 * virt_ctr:Y map every channel to a virtual controller
60 * virt_ctr:N use multi channel support
61 * hdr_channel:x x - number of virtual bus for host drives
62 * shared_access:Y disable driver reserve/release protocol to
63 * access a shared resource from several nodes,
575c9687 64 * appropriate controller firmware required
1da177e4
LT		 65 * shared_access:N enable driver reserve/release protocol
66 * probe_eisa_isa:Y scan for EISA/ISA controllers
67 * probe_eisa_isa:N do not scan for EISA/ISA controllers
68 * force_dma32:Y use only 32 bit DMA mode
69 * force_dma32:N use 64 bit DMA mode, if supported
70 *
71 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
72 * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
73 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
74 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
75 *
76 * When loading the gdth driver as a module, the same options are available.
77 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
78 * options changes slightly. You must replace all ',' between options
79 * with ' ' and all ':' with '=' and you must use
80 * '1' in place of 'Y' and '0' in place of 'N'.
81 *
82 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
83 * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
84 * probe_eisa_isa=0 force_dma32=0"
85 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
86 */
87
88/* The meaning of the Scsi_Pointer members in this driver is as follows:
89 * ptr: Chaining
90 * this_residual: Command priority
91 * buffer: phys. DMA sense buffer
92 * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
93 * buffers_residual: Timeout value
94 * Status: Command status (gdth_do_cmd()), DMA mem. mappings
95 * Message: Additional info (gdth_do_cmd()), DMA direction
96 * have_data_in: Flag for gdth_wait_completion()
97 * sent_command: Opcode special command
98 * phase: Service/parameter/return code special command
99 */
100
101
102/* interrupt coalescing */
103/* #define INT_COAL */
104
105/* statistics */
106#define GDTH_STATISTICS
107
108#include <linux/module.h>
109
110#include <linux/version.h>
111#include <linux/kernel.h>
112#include <linux/types.h>
113#include <linux/pci.h>
114#include <linux/string.h>
115#include <linux/ctype.h>
116#include <linux/ioport.h>
117#include <linux/delay.h>
1da177e4
LT		 118#include <linux/interrupt.h>
119#include <linux/in.h>
120#include <linux/proc_fs.h>
121#include <linux/time.h>
122#include <linux/timer.h>
910638ae 123#include <linux/dma-mapping.h>
cbd5f69b 124
1da177e4
LT		 125#ifdef GDTH_RTC
126#include <linux/mc146818rtc.h>
127#endif
128#include <linux/reboot.h>
129
130#include <asm/dma.h>
131#include <asm/system.h>
132#include <asm/io.h>
133#include <asm/uaccess.h>
134#include <linux/spinlock.h>
1da177e4 135#include <linux/blkdev.h>
1da177e4
LT		 136
137#include "scsi.h"
138#include <scsi/scsi_host.h>
cbd5f69b 139#include "gdth.h"
1da177e4
LT		 140
141static void gdth_delay(int milliseconds);
142static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
7d12e780 143static irqreturn_t gdth_interrupt(int irq, void *dev_id);
1da177e4
LT		 144static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
145static int gdth_async_event(int hanum);
146static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
147
148static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
149static void gdth_next(int hanum);
150static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
151static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
152static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
153 ushort idx, gdth_evt_data *evt);
154static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
155static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
156 gdth_evt_str *estr);
157static void gdth_clear_events(void);
158
159static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
160 char *buffer,ushort count);
161static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
162static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
163
1da177e4
LT		 164static void gdth_enable_int(int hanum);
165static int gdth_get_status(unchar *pIStatus,int irq);
166static int gdth_test_busy(int hanum);
167static int gdth_get_cmd_index(int hanum);
168static void gdth_release_event(int hanum);
169static int gdth_wait(int hanum,int index,ulong32 time);
170static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
171 ulong64 p2,ulong64 p3);
172static int gdth_search_drives(int hanum);
173static int gdth_analyse_hdrive(int hanum, ushort hdrive);
174
175static const char *gdth_ctr_name(int hanum);
176
177static int gdth_open(struct inode *inode, struct file *filep);
178static int gdth_close(struct inode *inode, struct file *filep);
179static int gdth_ioctl(struct inode *inode, struct file *filep,
180 unsigned int cmd, unsigned long arg);
181
182static void gdth_flush(int hanum);
183static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
cbd5f69b
LA		 184static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
185static void gdth_scsi_done(struct scsi_cmnd *scp);
aed91cb5
CH		 186#ifdef CONFIG_ISA
187static int gdth_isa_probe_one(struct scsi_host_template *, ulong32);
188#endif
706a5d45
CH		 189#ifdef CONFIG_EISA
190static int gdth_eisa_probe_one(struct scsi_host_template *, ushort);
191#endif
8514ef27
CH		 192#ifdef CONFIG_PCI
193static int gdth_pci_probe_one(struct scsi_host_template *, gdth_pci_str *, int);
194#endif
1da177e4
LT		 195
196#ifdef DEBUG_GDTH
197static unchar DebugState = DEBUG_GDTH;
198
199#ifdef __SERIAL__
200#define MAX_SERBUF 160
201static void ser_init(void);
202static void ser_puts(char *str);
203static void ser_putc(char c);
204static int ser_printk(const char *fmt, ...);
205static char strbuf[MAX_SERBUF+1];
206#ifdef __COM2__
207#define COM_BASE 0x2f8
208#else
209#define COM_BASE 0x3f8
210#endif
211static void ser_init()
212{
213 unsigned port=COM_BASE;
214
215 outb(0x80,port+3);
216 outb(0,port+1);
217 /* 19200 Baud, if 9600: outb(12,port) */
218 outb(6, port);
219 outb(3,port+3);
220 outb(0,port+1);
221 /*
222 ser_putc('I');
223 ser_putc(' ');
224 */
225}
226
227static void ser_puts(char *str)
228{
229 char *ptr;
230
231 ser_init();
232 for (ptr=str;*ptr;++ptr)
233 ser_putc(*ptr);
234}
235
236static void ser_putc(char c)
237{
238 unsigned port=COM_BASE;
239
240 while ((inb(port+5) & 0x20)==0);
241 outb(c,port);
242 if (c==0x0a)
243 {
244 while ((inb(port+5) & 0x20)==0);
245 outb(0x0d,port);
246 }
247}
248
249static int ser_printk(const char *fmt, ...)
250{
251 va_list args;
252 int i;
253
254 va_start(args,fmt);
255 i = vsprintf(strbuf,fmt,args);
256 ser_puts(strbuf);
257 va_end(args);
258 return i;
259}
260
261#define TRACE(a) {if (DebugState==1) {ser_printk a;}}
262#define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
263#define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
264
265#else /* !__SERIAL__ */
266#define TRACE(a) {if (DebugState==1) {printk a;}}
267#define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
268#define TRACE3(a) {if (DebugState!=0) {printk a;}}
269#endif
270
271#else /* !DEBUG */
272#define TRACE(a)
273#define TRACE2(a)
274#define TRACE3(a)
275#endif
276
277#ifdef GDTH_STATISTICS
278static ulong32 max_rq=0, max_index=0, max_sg=0;
279#ifdef INT_COAL
280static ulong32 max_int_coal=0;
281#endif
282static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
283static struct timer_list gdth_timer;
284#endif
285
286#define PTR2USHORT(a) (ushort)(ulong)(a)
6391a113
TK		 287#define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
288#define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
1da177e4
LT		 289
290#define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
291#define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
292#define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
293
294#define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
295
296#define gdth_readb(addr) readb(addr)
297#define gdth_readw(addr) readw(addr)
298#define gdth_readl(addr) readl(addr)
299#define gdth_writeb(b,addr) writeb((b),(addr))
300#define gdth_writew(b,addr) writew((b),(addr))
301#define gdth_writel(b,addr) writel((b),(addr))
302
aed91cb5 303#ifdef CONFIG_ISA
1da177e4 304static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
aed91cb5 305#endif
706a5d45 306#ifdef CONFIG_EISA
1da177e4 307static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
706a5d45 308#endif
1da177e4
LT		 309static unchar gdth_polling; /* polling if TRUE */
310static unchar gdth_from_wait = FALSE; /* gdth_wait() */
311static int wait_index,wait_hanum; /* gdth_wait() */
312static int gdth_ctr_count = 0; /* controller count */
313static int gdth_ctr_vcount = 0; /* virt. ctr. count */
314static int gdth_ctr_released = 0; /* gdth_release() */
315static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
316static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
317static unchar gdth_write_through = FALSE; /* write through */
318static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
319static int elastidx;
320static int eoldidx;
321static int major;
322
323#define DIN 1 /* IN data direction */
324#define DOU 2 /* OUT data direction */
325#define DNO DIN /* no data transfer */
326#define DUN DIN /* unknown data direction */
327static unchar gdth_direction_tab[0x100] = {
328 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
329 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
330 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
331 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
332 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
333 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
334 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
335 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
336 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
337 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
338 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
339 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
340 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
341 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
342 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
343 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
344};
345
346/* LILO and modprobe/insmod parameters */
347/* IRQ list for GDT3000/3020 EISA controllers */
348static int irq[MAXHA] __initdata =
349{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
350 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
351/* disable driver flag */
352static int disable __initdata = 0;
353/* reserve flag */
354static int reserve_mode = 1;
355/* reserve list */
356static int reserve_list[MAX_RES_ARGS] =
357{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
358 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
359 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
360/* scan order for PCI controllers */
361static int reverse_scan = 0;
362/* virtual channel for the host drives */
363static int hdr_channel = 0;
364/* max. IDs per channel */
365static int max_ids = MAXID;
366/* rescan all IDs */
367static int rescan = 0;
368/* map channels to virtual controllers */
369static int virt_ctr = 0;
370/* shared access */
371static int shared_access = 1;
372/* enable support for EISA and ISA controllers */
373static int probe_eisa_isa = 0;
374/* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
375static int force_dma32 = 0;
376
377/* parameters for modprobe/insmod */
378module_param_array(irq, int, NULL, 0);
379module_param(disable, int, 0);
380module_param(reserve_mode, int, 0);
381module_param_array(reserve_list, int, NULL, 0);
382module_param(reverse_scan, int, 0);
383module_param(hdr_channel, int, 0);
384module_param(max_ids, int, 0);
385module_param(rescan, int, 0);
386module_param(virt_ctr, int, 0);
387module_param(shared_access, int, 0);
388module_param(probe_eisa_isa, int, 0);
389module_param(force_dma32, int, 0);
390MODULE_AUTHOR("Achim Leubner");
391MODULE_LICENSE("GPL");
392
393/* ioctl interface */
00977a59 394static const struct file_operations gdth_fops = {
1da177e4
LT		 395 .ioctl = gdth_ioctl,
396 .open = gdth_open,
397 .release = gdth_close,
398};
399
687d2bc4
MW		 400#define GDTH_MAGIC 0xc2e7c389 /* I got it from /dev/urandom */
401#define IS_GDTH_INTERNAL_CMD(scp) (scp->underflow == GDTH_MAGIC)
402
1da177e4
LT		 403#include "gdth_proc.h"
404#include "gdth_proc.c"
405
406/* notifier block to get a notify on system shutdown/halt/reboot */
407static struct notifier_block gdth_notifier = {
408 gdth_halt, NULL, 0
409};
e041c683 410static int notifier_disabled = 0;
1da177e4
LT		 411
412static void gdth_delay(int milliseconds)
413{
414 if (milliseconds == 0) {
415 udelay(1);
416 } else {
417 mdelay(milliseconds);
418 }
419}
420
cbd5f69b
LA		 421static void gdth_scsi_done(struct scsi_cmnd *scp)
422{
b8bff2ae 423 TRACE2(("gdth_scsi_done()\n"));
cbd5f69b 424
b8bff2ae
MW		 425 if (IS_GDTH_INTERNAL_CMD(scp))
426 complete((struct completion *)scp->request);
427 else
428 scp->scsi_done(scp);
cbd5f69b
LA		 429}
430
431int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
432 int timeout, u32 *info)
433{
434 Scsi_Cmnd *scp;
6e9a4738 435 DECLARE_COMPLETION_ONSTACK(wait);
cbd5f69b
LA		 436 int rval;
437
bbfbbbc1 438 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
cbd5f69b
LA		 439 if (!scp)
440 return -ENOMEM;
bbfbbbc1 441
cbd5f69b 442 scp->device = sdev;
beb40487
CH		 443 /* use request field to save the ptr. to completion struct. */
444 scp->request = (struct request *)&wait;
cbd5f69b
LA		 445 scp->timeout_per_command = timeout*HZ;
446 scp->request_buffer = gdtcmd;
447 scp->cmd_len = 12;
448 memcpy(scp->cmnd, cmnd, 12);
449 scp->SCp.this_residual = IOCTL_PRI; /* priority */
687d2bc4 450 scp->underflow = GDTH_MAGIC;
b8bff2ae 451 gdth_queuecommand(scp, NULL);
cbd5f69b
LA		 452 wait_for_completion(&wait);
453
454 rval = scp->SCp.Status;
455 if (info)
456 *info = scp->SCp.Message;
457 kfree(scp);
458 return rval;
459}
cbd5f69b
LA		 460
461int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
462 int timeout, u32 *info)
463{
464 struct scsi_device *sdev = scsi_get_host_dev(shost);
465 int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
466
467 scsi_free_host_dev(sdev);
468 return rval;
469}
470
1da177e4
LT		 471static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
472{
473 *cyls = size /HEADS/SECS;
474 if (*cyls <= MAXCYLS) {
475 *heads = HEADS;
476 *secs = SECS;
477 } else { /* too high for 64*32 */
478 *cyls = size /MEDHEADS/MEDSECS;
479 if (*cyls <= MAXCYLS) {
480 *heads = MEDHEADS;
481 *secs = MEDSECS;
482 } else { /* too high for 127*63 */
483 *cyls = size /BIGHEADS/BIGSECS;
484 *heads = BIGHEADS;
485 *secs = BIGSECS;
486 }
487 }
488}
489
490/* controller search and initialization functions */
706a5d45 491#ifdef CONFIG_EISA
1da177e4
LT		 492static int __init gdth_search_eisa(ushort eisa_adr)
493{
494 ulong32 id;
495
496 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
497 id = inl(eisa_adr+ID0REG);
498 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
499 if ((inb(eisa_adr+EISAREG) & 8) == 0)
500 return 0; /* not EISA configured */
501 return 1;
502 }
503 if (id == GDT3_ID) /* GDT3000 */
504 return 1;
505
506 return 0;
507}
706a5d45 508#endif /* CONFIG_EISA */
1da177e4 509
aed91cb5 510#ifdef CONFIG_ISA
1da177e4
LT		 511static int __init gdth_search_isa(ulong32 bios_adr)
512{
513 void __iomem *addr;
514 ulong32 id;
515
516 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
517 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
518 id = gdth_readl(addr);
519 iounmap(addr);
520 if (id == GDT2_ID) /* GDT2000 */
521 return 1;
522 }
523 return 0;
524}
aed91cb5 525#endif /* CONFIG_ISA */
1da177e4 526
8514ef27
CH		 527#ifdef CONFIG_PCI
528static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
529 ushort vendor, ushort dev);
530
1da177e4
LT		 531static int __init gdth_search_pci(gdth_pci_str *pcistr)
532{
533 ushort device, cnt;
534
535 TRACE(("gdth_search_pci()\n"));
536
537 cnt = 0;
538 for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
539 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
540 for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
541 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
542 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
543 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
544 PCI_DEVICE_ID_VORTEX_GDTNEWRX);
545 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
546 PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
547 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
548 PCI_DEVICE_ID_INTEL_SRC);
549 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
550 PCI_DEVICE_ID_INTEL_SRC_XSCALE);
551 return cnt;
552}
553
554/* Vortex only makes RAID controllers.
555 * We do not really want to specify all 550 ids here, so wildcard match.
556 */
6c4b7e4f 557static struct pci_device_id gdthtable[] __maybe_unused = {
1da177e4
LT		 558 {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
559 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
560 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
561 {0}
562};
563MODULE_DEVICE_TABLE(pci,gdthtable);
564
565static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
cbd5f69b 566 ushort vendor, ushort device)
1da177e4
LT		 567{
568 ulong base0, base1, base2;
569 struct pci_dev *pdev;
570
571 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
572 *cnt, vendor, device));
573
574 pdev = NULL;
575 while ((pdev = pci_find_device(vendor, device, pdev))
576 != NULL) {
577 if (pci_enable_device(pdev))
578 continue;
579 if (*cnt >= MAXHA)
580 return;
581 /* GDT PCI controller found, resources are already in pdev */
582 pcistr[*cnt].pdev = pdev;
1da177e4
LT		 583 pcistr[*cnt].irq = pdev->irq;
584 base0 = pci_resource_flags(pdev, 0);
585 base1 = pci_resource_flags(pdev, 1);
586 base2 = pci_resource_flags(pdev, 2);
587 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
588 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
589 if (!(base0 & IORESOURCE_MEM))
590 continue;
591 pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
592 } else { /* GDT6110, GDT6120, .. */
593 if (!(base0 & IORESOURCE_MEM) ||
594 !(base2 & IORESOURCE_MEM) ||
595 !(base1 & IORESOURCE_IO))
596 continue;
597 pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
598 pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
599 pcistr[*cnt].io = pci_resource_start(pdev, 1);
600 }
601 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
8e9a8a0d
JG		 602 pcistr[*cnt].pdev->bus->number,
603 PCI_SLOT(pcistr[*cnt].pdev->devfn),
1da177e4
LT		 604 pcistr[*cnt].irq, pcistr[*cnt].dpmem));
605 (*cnt)++;
606 }
607}
608
1da177e4
LT		 609static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
610{
611 gdth_pci_str temp;
612 int i, changed;
613
614 TRACE(("gdth_sort_pci() cnt %d\n",cnt));
615 if (cnt == 0)
616 return;
617
618 do {
619 changed = FALSE;
620 for (i = 0; i < cnt-1; ++i) {
621 if (!reverse_scan) {
8e9a8a0d
JG		 622 if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
623 (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
624 PCI_SLOT(pcistr[i].pdev->devfn) >
625 PCI_SLOT(pcistr[i+1].pdev->devfn))) {
1da177e4
LT		 626 temp = pcistr[i];
627 pcistr[i] = pcistr[i+1];
628 pcistr[i+1] = temp;
629 changed = TRUE;
630 }
631 } else {
8e9a8a0d
JG		 632 if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
633 (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
634 PCI_SLOT(pcistr[i].pdev->devfn) <
635 PCI_SLOT(pcistr[i+1].pdev->devfn))) {
1da177e4
LT		 636 temp = pcistr[i];
637 pcistr[i] = pcistr[i+1];
638 pcistr[i+1] = temp;
639 changed = TRUE;
640 }
641 }
642 }
643 } while (changed);
644}
8514ef27 645#endif /* CONFIG_PCI */
1da177e4 646
706a5d45 647#ifdef CONFIG_EISA
1da177e4
LT		 648static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
649{
650 ulong32 retries,id;
651 unchar prot_ver,eisacf,i,irq_found;
652
653 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
654
655 /* disable board interrupts, deinitialize services */
656 outb(0xff,eisa_adr+EDOORREG);
657 outb(0x00,eisa_adr+EDENABREG);
658 outb(0x00,eisa_adr+EINTENABREG);
659
660 outb(0xff,eisa_adr+LDOORREG);
661 retries = INIT_RETRIES;
662 gdth_delay(20);
663 while (inb(eisa_adr+EDOORREG) != 0xff) {
664 if (--retries == 0) {
665 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
666 return 0;
667 }
668 gdth_delay(1);
669 TRACE2(("wait for DEINIT: retries=%d\n",retries));
670 }
671 prot_ver = inb(eisa_adr+MAILBOXREG);
672 outb(0xff,eisa_adr+EDOORREG);
673 if (prot_ver != PROTOCOL_VERSION) {
674 printk("GDT-EISA: Illegal protocol version\n");
675 return 0;
676 }
677 ha->bmic = eisa_adr;
678 ha->brd_phys = (ulong32)eisa_adr >> 12;
679
680 outl(0,eisa_adr+MAILBOXREG);
681 outl(0,eisa_adr+MAILBOXREG+4);
682 outl(0,eisa_adr+MAILBOXREG+8);
683 outl(0,eisa_adr+MAILBOXREG+12);
684
685 /* detect IRQ */
686 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
687 ha->oem_id = OEM_ID_ICP;
688 ha->type = GDT_EISA;
689 ha->stype = id;
690 outl(1,eisa_adr+MAILBOXREG+8);
691 outb(0xfe,eisa_adr+LDOORREG);
692 retries = INIT_RETRIES;
693 gdth_delay(20);
694 while (inb(eisa_adr+EDOORREG) != 0xfe) {
695 if (--retries == 0) {
696 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
697 return 0;
698 }
699 gdth_delay(1);
700 }
701 ha->irq = inb(eisa_adr+MAILBOXREG);
702 outb(0xff,eisa_adr+EDOORREG);
703 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
704 /* check the result */
705 if (ha->irq == 0) {
706 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
707 for (i = 0, irq_found = FALSE;
708 i < MAXHA && irq[i] != 0xff; ++i) {
709 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
710 irq_found = TRUE;
711 break;
712 }
713 }
714 if (irq_found) {
715 ha->irq = irq[i];
716 irq[i] = 0;
717 printk("GDT-EISA: Can not detect controller IRQ,\n");
718 printk("Use IRQ setting from command line (IRQ = %d)\n",
719 ha->irq);
720 } else {
721 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
722 printk("the controller BIOS or use command line parameters\n");
723 return 0;
724 }
725 }
726 } else {
727 eisacf = inb(eisa_adr+EISAREG) & 7;
728 if (eisacf > 4) /* level triggered */
729 eisacf -= 4;
730 ha->irq = gdth_irq_tab[eisacf];
731 ha->oem_id = OEM_ID_ICP;
732 ha->type = GDT_EISA;
733 ha->stype = id;
734 }
735
736 ha->dma64_support = 0;
737 return 1;
738}
706a5d45 739#endif /* CONFIG_EISA */
1da177e4 740
aed91cb5 741#ifdef CONFIG_ISA
1da177e4
LT		 742static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
743{
744 register gdt2_dpram_str __iomem *dp2_ptr;
745 int i;
746 unchar irq_drq,prot_ver;
747 ulong32 retries;
748
749 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
750
751 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
752 if (ha->brd == NULL) {
753 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
754 return 0;
755 }
756 dp2_ptr = ha->brd;
757 gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
758 /* reset interface area */
759 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
760 if (gdth_readl(&dp2_ptr->u) != 0) {
761 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
762 iounmap(ha->brd);
763 return 0;
764 }
765
766 /* disable board interrupts, read DRQ and IRQ */
767 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
768 gdth_writeb(0x00, &dp2_ptr->io.irqen);
769 gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
770 gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
771
772 irq_drq = gdth_readb(&dp2_ptr->io.rq);
773 for (i=0; i<3; ++i) {
774 if ((irq_drq & 1)==0)
775 break;
776 irq_drq >>= 1;
777 }
778 ha->drq = gdth_drq_tab[i];
779
780 irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
781 for (i=1; i<5; ++i) {
782 if ((irq_drq & 1)==0)
783 break;
784 irq_drq >>= 1;
785 }
786 ha->irq = gdth_irq_tab[i];
787
788 /* deinitialize services */
789 gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
790 gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
791 gdth_writeb(0, &dp2_ptr->io.event);
792 retries = INIT_RETRIES;
793 gdth_delay(20);
794 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
795 if (--retries == 0) {
796 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
797 iounmap(ha->brd);
798 return 0;
799 }
800 gdth_delay(1);
801 }
802 prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
803 gdth_writeb(0, &dp2_ptr->u.ic.Status);
804 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
805 if (prot_ver != PROTOCOL_VERSION) {
806 printk("GDT-ISA: Illegal protocol version\n");
807 iounmap(ha->brd);
808 return 0;
809 }
810
811 ha->oem_id = OEM_ID_ICP;
812 ha->type = GDT_ISA;
813 ha->ic_all_size = sizeof(dp2_ptr->u);
814 ha->stype= GDT2_ID;
815 ha->brd_phys = bios_adr >> 4;
816
817 /* special request to controller BIOS */
818 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
819 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
820 gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
821 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
822 gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
823 gdth_writeb(0, &dp2_ptr->io.event);
824 retries = INIT_RETRIES;
825 gdth_delay(20);
826 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
827 if (--retries == 0) {
828 printk("GDT-ISA: Initialization error\n");
829 iounmap(ha->brd);
830 return 0;
831 }
832 gdth_delay(1);
833 }
834 gdth_writeb(0, &dp2_ptr->u.ic.Status);
835 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
836
837 ha->dma64_support = 0;
838 return 1;
839}
aed91cb5 840#endif /* CONFIG_ISA */
1da177e4 841
8514ef27 842#ifdef CONFIG_PCI
1da177e4
LT		 843static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
844{
845 register gdt6_dpram_str __iomem *dp6_ptr;
846 register gdt6c_dpram_str __iomem *dp6c_ptr;
847 register gdt6m_dpram_str __iomem *dp6m_ptr;
848 ulong32 retries;
849 unchar prot_ver;
850 ushort command;
851 int i, found = FALSE;
852
853 TRACE(("gdth_init_pci()\n"));
854
8e9a8a0d 855 if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
1da177e4
LT		 856 ha->oem_id = OEM_ID_INTEL;
857 else
858 ha->oem_id = OEM_ID_ICP;
8e9a8a0d
JG		 859 ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
860 ha->stype = (ulong32)pcistr->pdev->device;
1da177e4
LT		 861 ha->irq = pcistr->irq;
862 ha->pdev = pcistr->pdev;
863
8e9a8a0d 864 if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
1da177e4
LT		 865 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
866 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
867 if (ha->brd == NULL) {
868 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
869 return 0;
870 }
871 /* check and reset interface area */
872 dp6_ptr = ha->brd;
873 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
874 if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
875 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
876 pcistr->dpmem);
877 found = FALSE;
878 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
879 iounmap(ha->brd);
880 ha->brd = ioremap(i, sizeof(ushort));
881 if (ha->brd == NULL) {
882 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
883 return 0;
884 }
885 if (gdth_readw(ha->brd) != 0xffff) {
886 TRACE2(("init_pci_old() address 0x%x busy\n", i));
887 continue;
888 }
889 iounmap(ha->brd);
890 pci_write_config_dword(pcistr->pdev,
891 PCI_BASE_ADDRESS_0, i);
892 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
893 if (ha->brd == NULL) {
894 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
895 return 0;
896 }
897 dp6_ptr = ha->brd;
898 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
899 if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
900 printk("GDT-PCI: Use free address at 0x%x\n", i);
901 found = TRUE;
902 break;
903 }
904 }
905 if (!found) {
906 printk("GDT-PCI: No free address found!\n");
907 iounmap(ha->brd);
908 return 0;
909 }
910 }
911 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
912 if (gdth_readl(&dp6_ptr->u) != 0) {
913 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
914 iounmap(ha->brd);
915 return 0;
916 }
917
918 /* disable board interrupts, deinit services */
919 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
920 gdth_writeb(0x00, &dp6_ptr->io.irqen);
921 gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
922 gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
923
924 gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
925 gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
926 gdth_writeb(0, &dp6_ptr->io.event);
927 retries = INIT_RETRIES;
928 gdth_delay(20);
929 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
930 if (--retries == 0) {
931 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
932 iounmap(ha->brd);
933 return 0;
934 }
935 gdth_delay(1);
936 }
937 prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
938 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
939 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
940 if (prot_ver != PROTOCOL_VERSION) {
941 printk("GDT-PCI: Illegal protocol version\n");
942 iounmap(ha->brd);
943 return 0;
944 }
945
946 ha->type = GDT_PCI;
947 ha->ic_all_size = sizeof(dp6_ptr->u);
948
949 /* special command to controller BIOS */
950 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
951 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
952 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
953 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
954 gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
955 gdth_writeb(0, &dp6_ptr->io.event);
956 retries = INIT_RETRIES;
957 gdth_delay(20);
958 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
959 if (--retries == 0) {
960 printk("GDT-PCI: Initialization error\n");
961 iounmap(ha->brd);
962 return 0;
963 }
964 gdth_delay(1);
965 }
966 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
967 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
968
969 ha->dma64_support = 0;
970
8e9a8a0d 971 } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
1da177e4
LT		 972 ha->plx = (gdt6c_plx_regs *)pcistr->io;
973 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
974 pcistr->dpmem,ha->irq));
975 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
976 if (ha->brd == NULL) {
977 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
978 iounmap(ha->brd);
979 return 0;
980 }
981 /* check and reset interface area */
982 dp6c_ptr = ha->brd;
983 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
984 if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
985 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
986 pcistr->dpmem);
987 found = FALSE;
988 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
989 iounmap(ha->brd);
990 ha->brd = ioremap(i, sizeof(ushort));
991 if (ha->brd == NULL) {
992 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
993 return 0;
994 }
995 if (gdth_readw(ha->brd) != 0xffff) {
996 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
997 continue;
998 }
999 iounmap(ha->brd);
1000 pci_write_config_dword(pcistr->pdev,
1001 PCI_BASE_ADDRESS_2, i);
1002 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
1003 if (ha->brd == NULL) {
1004 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1005 return 0;
1006 }
1007 dp6c_ptr = ha->brd;
1008 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
1009 if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1010 printk("GDT-PCI: Use free address at 0x%x\n", i);
1011 found = TRUE;
1012 break;
1013 }
1014 }
1015 if (!found) {
1016 printk("GDT-PCI: No free address found!\n");
1017 iounmap(ha->brd);
1018 return 0;
1019 }
1020 }
1021 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
1022 if (gdth_readl(&dp6c_ptr->u) != 0) {
1023 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1024 iounmap(ha->brd);
1025 return 0;
1026 }
1027
1028 /* disable board interrupts, deinit services */
1029 outb(0x00,PTR2USHORT(&ha->plx->control1));
1030 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1031
1032 gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1033 gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1034
1035 gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1036 gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1037
1038 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1039
1040 retries = INIT_RETRIES;
1041 gdth_delay(20);
1042 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1043 if (--retries == 0) {
1044 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1045 iounmap(ha->brd);
1046 return 0;
1047 }
1048 gdth_delay(1);
1049 }
1050 prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
1051 gdth_writeb(0, &dp6c_ptr->u.ic.Status);
1052 if (prot_ver != PROTOCOL_VERSION) {
1053 printk("GDT-PCI: Illegal protocol version\n");
1054 iounmap(ha->brd);
1055 return 0;
1056 }
1057
1058 ha->type = GDT_PCINEW;
1059 ha->ic_all_size = sizeof(dp6c_ptr->u);
1060
1061 /* special command to controller BIOS */
1062 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1063 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1064 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1065 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1066 gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1067
1068 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1069
1070 retries = INIT_RETRIES;
1071 gdth_delay(20);
1072 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1073 if (--retries == 0) {
1074 printk("GDT-PCI: Initialization error\n");
1075 iounmap(ha->brd);
1076 return 0;
1077 }
1078 gdth_delay(1);
1079 }
1080 gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
1081
1082 ha->dma64_support = 0;
1083
1084 } else { /* MPR */
1085 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1086 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1087 if (ha->brd == NULL) {
1088 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1089 return 0;
1090 }
1091
1092 /* manipulate config. space to enable DPMEM, start RP controller */
1093 pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
1094 command |= 6;
1095 pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
1096 if (pci_resource_start(pcistr->pdev, 8) == 1UL)
1097 pci_resource_start(pcistr->pdev, 8) = 0UL;
1098 i = 0xFEFF0001UL;
1099 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
1100 gdth_delay(1);
1101 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
1102 pci_resource_start(pcistr->pdev, 8));
1103
1104 dp6m_ptr = ha->brd;
1105
1106 /* Ensure that it is safe to access the non HW portions of DPMEM.
1107 * Aditional check needed for Xscale based RAID controllers */
1108 while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1109 gdth_delay(1);
1110
1111 /* check and reset interface area */
1112 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1113 if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1114 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1115 pcistr->dpmem);
1116 found = FALSE;
1117 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1118 iounmap(ha->brd);
1119 ha->brd = ioremap(i, sizeof(ushort));
1120 if (ha->brd == NULL) {
1121 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1122 return 0;
1123 }
1124 if (gdth_readw(ha->brd) != 0xffff) {
1125 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1126 continue;
1127 }
1128 iounmap(ha->brd);
1129 pci_write_config_dword(pcistr->pdev,
1130 PCI_BASE_ADDRESS_0, i);
1131 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1132 if (ha->brd == NULL) {
1133 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1134 return 0;
1135 }
1136 dp6m_ptr = ha->brd;
1137 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1138 if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1139 printk("GDT-PCI: Use free address at 0x%x\n", i);
1140 found = TRUE;
1141 break;
1142 }
1143 }
1144 if (!found) {
1145 printk("GDT-PCI: No free address found!\n");
1146 iounmap(ha->brd);
1147 return 0;
1148 }
1149 }
1150 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1151
1152 /* disable board interrupts, deinit services */
1153 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1154 &dp6m_ptr->i960r.edoor_en_reg);
1155 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1156 gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1157 gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1158
1159 gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1160 gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1161 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1162 retries = INIT_RETRIES;
1163 gdth_delay(20);
1164 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1165 if (--retries == 0) {
1166 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1167 iounmap(ha->brd);
1168 return 0;
1169 }
1170 gdth_delay(1);
1171 }
1172 prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
1173 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1174 if (prot_ver != PROTOCOL_VERSION) {
1175 printk("GDT-PCI: Illegal protocol version\n");
1176 iounmap(ha->brd);
1177 return 0;
1178 }
1179
1180 ha->type = GDT_PCIMPR;
1181 ha->ic_all_size = sizeof(dp6m_ptr->u);
1182
1183 /* special command to controller BIOS */
1184 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1185 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1186 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1187 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1188 gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1189 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1190 retries = INIT_RETRIES;
1191 gdth_delay(20);
1192 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1193 if (--retries == 0) {
1194 printk("GDT-PCI: Initialization error\n");
1195 iounmap(ha->brd);
1196 return 0;
1197 }
1198 gdth_delay(1);
1199 }
1200 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1201
1202 /* read FW version to detect 64-bit DMA support */
1203 gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1204 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1205 retries = INIT_RETRIES;
1206 gdth_delay(20);
1207 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1208 if (--retries == 0) {
1209 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1210 iounmap(ha->brd);
1211 return 0;
1212 }
1213 gdth_delay(1);
1214 }
1215 prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1216 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1217 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1218 ha->dma64_support = 0;
1219 else
1220 ha->dma64_support = 1;
1221 }
1222
1223 return 1;
1224}
8514ef27 1225#endif /* CONFIG_PCI */
1da177e4
LT		 1226
1227/* controller protocol functions */
1228
1229static void __init gdth_enable_int(int hanum)
1230{
1231 gdth_ha_str *ha;
1232 ulong flags;
1233 gdt2_dpram_str __iomem *dp2_ptr;
1234 gdt6_dpram_str __iomem *dp6_ptr;
1235 gdt6m_dpram_str __iomem *dp6m_ptr;
1236
1237 TRACE(("gdth_enable_int() hanum %d\n",hanum));
1238 ha = HADATA(gdth_ctr_tab[hanum]);
1239 spin_lock_irqsave(&ha->smp_lock, flags);
1240
1241 if (ha->type == GDT_EISA) {
1242 outb(0xff, ha->bmic + EDOORREG);
1243 outb(0xff, ha->bmic + EDENABREG);
1244 outb(0x01, ha->bmic + EINTENABREG);
1245 } else if (ha->type == GDT_ISA) {
1246 dp2_ptr = ha->brd;
1247 gdth_writeb(1, &dp2_ptr->io.irqdel);
1248 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1249 gdth_writeb(1, &dp2_ptr->io.irqen);
1250 } else if (ha->type == GDT_PCI) {
1251 dp6_ptr = ha->brd;
1252 gdth_writeb(1, &dp6_ptr->io.irqdel);
1253 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1254 gdth_writeb(1, &dp6_ptr->io.irqen);
1255 } else if (ha->type == GDT_PCINEW) {
1256 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1257 outb(0x03, PTR2USHORT(&ha->plx->control1));
1258 } else if (ha->type == GDT_PCIMPR) {
1259 dp6m_ptr = ha->brd;
1260 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1261 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1262 &dp6m_ptr->i960r.edoor_en_reg);
1263 }
1264 spin_unlock_irqrestore(&ha->smp_lock, flags);
1265}
1266
1267
1268static int gdth_get_status(unchar *pIStatus,int irq)
1269{
1270 register gdth_ha_str *ha;
1271 int i;
1272
1273 TRACE(("gdth_get_status() irq %d ctr_count %d\n",
1274 irq,gdth_ctr_count));
1275
1276 *pIStatus = 0;
1277 for (i=0; i<gdth_ctr_count; ++i) {
1278 ha = HADATA(gdth_ctr_tab[i]);
1279 if (ha->irq != (unchar)irq) /* check IRQ */
1280 continue;
1281 if (ha->type == GDT_EISA)
1282 *pIStatus = inb((ushort)ha->bmic + EDOORREG);
1283 else if (ha->type == GDT_ISA)
1284 *pIStatus =
1285 gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1286 else if (ha->type == GDT_PCI)
1287 *pIStatus =
1288 gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1289 else if (ha->type == GDT_PCINEW)
1290 *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1291 else if (ha->type == GDT_PCIMPR)
1292 *pIStatus =
1293 gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
1294
1295 if (*pIStatus)
1296 return i; /* board found */
1297 }
1298 return -1;
1299}
1300
1301
1302static int gdth_test_busy(int hanum)
1303{
1304 register gdth_ha_str *ha;
1305 register int gdtsema0 = 0;
1306
1307 TRACE(("gdth_test_busy() hanum %d\n",hanum));
1308
1309 ha = HADATA(gdth_ctr_tab[hanum]);
1310 if (ha->type == GDT_EISA)
1311 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1312 else if (ha->type == GDT_ISA)
1313 gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1314 else if (ha->type == GDT_PCI)
1315 gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1316 else if (ha->type == GDT_PCINEW)
1317 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1318 else if (ha->type == GDT_PCIMPR)
1319 gdtsema0 =
1320 (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1321
1322 return (gdtsema0 & 1);
1323}
1324
1325
1326static int gdth_get_cmd_index(int hanum)
1327{
1328 register gdth_ha_str *ha;
1329 int i;
1330
1331 TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
1332
1333 ha = HADATA(gdth_ctr_tab[hanum]);
1334 for (i=0; i<GDTH_MAXCMDS; ++i) {
1335 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1336 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1337 ha->cmd_tab[i].service = ha->pccb->Service;
1338 ha->pccb->CommandIndex = (ulong32)i+2;
1339 return (i+2);
1340 }
1341 }
1342 return 0;
1343}
1344
1345
1346static void gdth_set_sema0(int hanum)
1347{
1348 register gdth_ha_str *ha;
1349
1350 TRACE(("gdth_set_sema0() hanum %d\n",hanum));
1351
1352 ha = HADATA(gdth_ctr_tab[hanum]);
1353 if (ha->type == GDT_EISA) {
1354 outb(1, ha->bmic + SEMA0REG);
1355 } else if (ha->type == GDT_ISA) {
1356 gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1357 } else if (ha->type == GDT_PCI) {
1358 gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1359 } else if (ha->type == GDT_PCINEW) {
1360 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1361 } else if (ha->type == GDT_PCIMPR) {
1362 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1363 }
1364}
1365
1366
1367static void gdth_copy_command(int hanum)
1368{
1369 register gdth_ha_str *ha;
1370 register gdth_cmd_str *cmd_ptr;
1371 register gdt6m_dpram_str __iomem *dp6m_ptr;
1372 register gdt6c_dpram_str __iomem *dp6c_ptr;
1373 gdt6_dpram_str __iomem *dp6_ptr;
1374 gdt2_dpram_str __iomem *dp2_ptr;
1375 ushort cp_count,dp_offset,cmd_no;
1376
1377 TRACE(("gdth_copy_command() hanum %d\n",hanum));
1378
1379 ha = HADATA(gdth_ctr_tab[hanum]);
1380 cp_count = ha->cmd_len;
1381 dp_offset= ha->cmd_offs_dpmem;
1382 cmd_no = ha->cmd_cnt;
1383 cmd_ptr = ha->pccb;
1384
1385 ++ha->cmd_cnt;
1386 if (ha->type == GDT_EISA)
1387 return; /* no DPMEM, no copy */
1388
1389 /* set cpcount dword aligned */
1390 if (cp_count & 3)
1391 cp_count += (4 - (cp_count & 3));
1392
1393 ha->cmd_offs_dpmem += cp_count;
1394
1395 /* set offset and service, copy command to DPMEM */
1396 if (ha->type == GDT_ISA) {
1397 dp2_ptr = ha->brd;
1398 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1399 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1400 gdth_writew((ushort)cmd_ptr->Service,
1401 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1402 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1403 } else if (ha->type == GDT_PCI) {
1404 dp6_ptr = ha->brd;
1405 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1406 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
1407 gdth_writew((ushort)cmd_ptr->Service,
1408 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1409 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1410 } else if (ha->type == GDT_PCINEW) {
1411 dp6c_ptr = ha->brd;
1412 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1413 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
1414 gdth_writew((ushort)cmd_ptr->Service,
1415 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1416 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1417 } else if (ha->type == GDT_PCIMPR) {
1418 dp6m_ptr = ha->brd;
1419 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1420 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
1421 gdth_writew((ushort)cmd_ptr->Service,
1422 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1423 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1424 }
1425}
1426
1427
1428static void gdth_release_event(int hanum)
1429{
1430 register gdth_ha_str *ha;
1431
1432 TRACE(("gdth_release_event() hanum %d\n",hanum));
1433 ha = HADATA(gdth_ctr_tab[hanum]);
1434
1435#ifdef GDTH_STATISTICS
1436 {
1437 ulong32 i,j;
1438 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1439 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1440 ++i;
1441 }
1442 if (max_index < i) {
1443 max_index = i;
1444 TRACE3(("GDT: max_index = %d\n",(ushort)i));
1445 }
1446 }
1447#endif
1448
1449 if (ha->pccb->OpCode == GDT_INIT)
1450 ha->pccb->Service |= 0x80;
1451
1452 if (ha->type == GDT_EISA) {
1453 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1454 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1455 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1456 } else if (ha->type == GDT_ISA) {
1457 gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1458 } else if (ha->type == GDT_PCI) {
1459 gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1460 } else if (ha->type == GDT_PCINEW) {
1461 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1462 } else if (ha->type == GDT_PCIMPR) {
1463 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1464 }
1465}
1466
1467
1468static int gdth_wait(int hanum,int index,ulong32 time)
1469{
1470 gdth_ha_str *ha;
1471 int answer_found = FALSE;
1472
1473 TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
1474
1475 ha = HADATA(gdth_ctr_tab[hanum]);
1476 if (index == 0)
1477 return 1; /* no wait required */
1478
1479 gdth_from_wait = TRUE;
1480 do {
7d12e780 1481 gdth_interrupt((int)ha->irq,ha);
1da177e4
LT		 1482 if (wait_hanum==hanum && wait_index==index) {
1483 answer_found = TRUE;
1484 break;
1485 }
1486 gdth_delay(1);
1487 } while (--time);
1488 gdth_from_wait = FALSE;
1489
1490 while (gdth_test_busy(hanum))
1491 gdth_delay(0);
1492
1493 return (answer_found);
1494}
1495
1496
1497static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
1498 ulong64 p2,ulong64 p3)
1499{
1500 register gdth_ha_str *ha;
1501 register gdth_cmd_str *cmd_ptr;
1502 int retries,index;
1503
1504 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1505
1506 ha = HADATA(gdth_ctr_tab[hanum]);
1507 cmd_ptr = ha->pccb;
1508 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1509
1510 /* make command */
1511 for (retries = INIT_RETRIES;;) {
1512 cmd_ptr->Service = service;
1513 cmd_ptr->RequestBuffer = INTERNAL_CMND;
1514 if (!(index=gdth_get_cmd_index(hanum))) {
1515 TRACE(("GDT: No free command index found\n"));
1516 return 0;
1517 }
1518 gdth_set_sema0(hanum);
1519 cmd_ptr->OpCode = opcode;
1520 cmd_ptr->BoardNode = LOCALBOARD;
1521 if (service == CACHESERVICE) {
1522 if (opcode == GDT_IOCTL) {
1523 cmd_ptr->u.ioctl.subfunc = p1;
1524 cmd_ptr->u.ioctl.channel = (ulong32)p2;
1525 cmd_ptr->u.ioctl.param_size = (ushort)p3;
1526 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1527 } else {
1528 if (ha->cache_feat & GDT_64BIT) {
1529 cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
1530 cmd_ptr->u.cache64.BlockNo = p2;
1531 } else {
1532 cmd_ptr->u.cache.DeviceNo = (ushort)p1;
1533 cmd_ptr->u.cache.BlockNo = (ulong32)p2;
1534 }
1535 }
1536 } else if (service == SCSIRAWSERVICE) {
1537 if (ha->raw_feat & GDT_64BIT) {
1538 cmd_ptr->u.raw64.direction = p1;
1539 cmd_ptr->u.raw64.bus = (unchar)p2;
1540 cmd_ptr->u.raw64.target = (unchar)p3;
1541 cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
1542 } else {
1543 cmd_ptr->u.raw.direction = p1;
1544 cmd_ptr->u.raw.bus = (unchar)p2;
1545 cmd_ptr->u.raw.target = (unchar)p3;
1546 cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
1547 }
1548 } else if (service == SCREENSERVICE) {
1549 if (opcode == GDT_REALTIME) {
1550 *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1551 *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
1552 *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
1553 }
1554 }
1555 ha->cmd_len = sizeof(gdth_cmd_str);
1556 ha->cmd_offs_dpmem = 0;
1557 ha->cmd_cnt = 0;
1558 gdth_copy_command(hanum);
1559 gdth_release_event(hanum);
1560 gdth_delay(20);
1561 if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
1562 printk("GDT: Initialization error (timeout service %d)\n",service);
1563 return 0;
1564 }
1565 if (ha->status != S_BSY || --retries == 0)
1566 break;
1567 gdth_delay(1);
1568 }
1569
1570 return (ha->status != S_OK ? 0:1);
1571}
1572
1573
1574/* search for devices */
1575
1576static int __init gdth_search_drives(int hanum)
1577{
1578 register gdth_ha_str *ha;
1579 ushort cdev_cnt, i;
1580 int ok;
1581 ulong32 bus_no, drv_cnt, drv_no, j;
1582 gdth_getch_str *chn;
1583 gdth_drlist_str *drl;
1584 gdth_iochan_str *ioc;
1585 gdth_raw_iochan_str *iocr;
1586 gdth_arcdl_str *alst;
1587 gdth_alist_str *alst2;
1588 gdth_oem_str_ioctl *oemstr;
1589#ifdef INT_COAL
1590 gdth_perf_modes *pmod;
1591#endif
1592
1593#ifdef GDTH_RTC
1594 unchar rtc[12];
1595 ulong flags;
1596#endif
1597
1598 TRACE(("gdth_search_drives() hanum %d\n",hanum));
1599 ha = HADATA(gdth_ctr_tab[hanum]);
1600 ok = 0;
1601
1602 /* initialize controller services, at first: screen service */
1603 ha->screen_feat = 0;
1604 if (!force_dma32) {
1605 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
1606 if (ok)
1607 ha->screen_feat = GDT_64BIT;
1608 }
1609 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1610 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
1611 if (!ok) {
1612 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
1613 hanum, ha->status);
1614 return 0;
1615 }
1616 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1617
1618#ifdef GDTH_RTC
1619 /* read realtime clock info, send to controller */
1620 /* 1. wait for the falling edge of update flag */
1621 spin_lock_irqsave(&rtc_lock, flags);
1622 for (j = 0; j < 1000000; ++j)
1623 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1624 break;
1625 for (j = 0; j < 1000000; ++j)
1626 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1627 break;
1628 /* 2. read info */
1629 do {
1630 for (j = 0; j < 12; ++j)
1631 rtc[j] = CMOS_READ(j);
1632 } while (rtc[0] != CMOS_READ(0));
7a960b76 1633 spin_unlock_irqrestore(&rtc_lock, flags);
1da177e4
LT		 1634 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
1635 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
1636 /* 3. send to controller firmware */
1637 gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
1638 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
1639#endif
1640
1641 /* unfreeze all IOs */
1642 gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
1643
1644 /* initialize cache service */
1645 ha->cache_feat = 0;
1646 if (!force_dma32) {
1647 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
1648 if (ok)
1649 ha->cache_feat = GDT_64BIT;
1650 }
1651 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1652 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
1653 if (!ok) {
1654 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1655 hanum, ha->status);
1656 return 0;
1657 }
1658 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1659 cdev_cnt = (ushort)ha->info;
1660 ha->fw_vers = ha->service;
1661
1662#ifdef INT_COAL
1663 if (ha->type == GDT_PCIMPR) {
1664 /* set perf. modes */
1665 pmod = (gdth_perf_modes *)ha->pscratch;
1666 pmod->version = 1;
1667 pmod->st_mode = 1; /* enable one status buffer */
1668 *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1669 pmod->st_buff_indx1 = COALINDEX;
1670 pmod->st_buff_addr2 = 0;
1671 pmod->st_buff_u_addr2 = 0;
1672 pmod->st_buff_indx2 = 0;
1673 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
1674 pmod->cmd_mode = 0; // disable all cmd buffers
1675 pmod->cmd_buff_addr1 = 0;
1676 pmod->cmd_buff_u_addr1 = 0;
1677 pmod->cmd_buff_indx1 = 0;
1678 pmod->cmd_buff_addr2 = 0;
1679 pmod->cmd_buff_u_addr2 = 0;
1680 pmod->cmd_buff_indx2 = 0;
1681 pmod->cmd_buff_size = 0;
1682 pmod->reserved1 = 0;
1683 pmod->reserved2 = 0;
1684 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
1685 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
1686 printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
1687 }
1688 }
1689#endif
1690
1691 /* detect number of buses - try new IOCTL */
1692 iocr = (gdth_raw_iochan_str *)ha->pscratch;
1693 iocr->hdr.version = 0xffffffff;
1694 iocr->hdr.list_entries = MAXBUS;
1695 iocr->hdr.first_chan = 0;
1696 iocr->hdr.last_chan = MAXBUS-1;
1697 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
1698 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
1699 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
1700 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
1701 ha->bus_cnt = iocr->hdr.chan_count;
1702 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1703 if (iocr->list[bus_no].proc_id < MAXID)
1704 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
1705 else
1706 ha->bus_id[bus_no] = 0xff;
1707 }
1708 } else {
1709 /* old method */
1710 chn = (gdth_getch_str *)ha->pscratch;
1711 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
1712 chn->channel_no = bus_no;
1713 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
1714 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1715 IO_CHANNEL | INVALID_CHANNEL,
1716 sizeof(gdth_getch_str))) {
1717 if (bus_no == 0) {
1718 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
1719 hanum, ha->status);
1720 return 0;
1721 }
1722 break;
1723 }
1724 if (chn->siop_id < MAXID)
1725 ha->bus_id[bus_no] = chn->siop_id;
1726 else
1727 ha->bus_id[bus_no] = 0xff;
1728 }
1729 ha->bus_cnt = (unchar)bus_no;
1730 }
1731 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
1732
1733 /* read cache configuration */
1734 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
1735 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
1736 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1737 hanum, ha->status);
1738 return 0;
1739 }
1740 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
1741 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
1742 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
1743 ha->cpar.write_back,ha->cpar.block_size));
1744
1745 /* read board info and features */
1746 ha->more_proc = FALSE;
1747 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
1748 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
1749 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
1750 sizeof(gdth_binfo_str));
1751 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
1752 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
1753 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
1754 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
1755 ha->more_proc = TRUE;
1756 }
1757 } else {
1758 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
1759 strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
1760 }
1761 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
1762
1763 /* read more informations */
1764 if (ha->more_proc) {
1765 /* physical drives, channel addresses */
1766 ioc = (gdth_iochan_str *)ha->pscratch;
1767 ioc->hdr.version = 0xffffffff;
1768 ioc->hdr.list_entries = MAXBUS;
1769 ioc->hdr.first_chan = 0;
1770 ioc->hdr.last_chan = MAXBUS-1;
1771 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
1772 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
1773 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
1774 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1775 ha->raw[bus_no].address = ioc->list[bus_no].address;
1776 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
1777 }
1778 } else {
1779 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1780 ha->raw[bus_no].address = IO_CHANNEL;
1781 ha->raw[bus_no].local_no = bus_no;
1782 }
1783 }
1784 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1785 chn = (gdth_getch_str *)ha->pscratch;
1786 chn->channel_no = ha->raw[bus_no].local_no;
1787 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
1788 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1789 ha->raw[bus_no].address | INVALID_CHANNEL,
1790 sizeof(gdth_getch_str))) {
1791 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
1792 TRACE2(("Channel %d: %d phys. drives\n",
1793 bus_no,chn->drive_cnt));
1794 }
1795 if (ha->raw[bus_no].pdev_cnt > 0) {
1796 drl = (gdth_drlist_str *)ha->pscratch;
1797 drl->sc_no = ha->raw[bus_no].local_no;
1798 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
1799 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
1800 SCSI_DR_LIST | L_CTRL_PATTERN,
1801 ha->raw[bus_no].address | INVALID_CHANNEL,
1802 sizeof(gdth_drlist_str))) {
1803 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
1804 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
1805 } else {
1806 ha->raw[bus_no].pdev_cnt = 0;
1807 }
1808 }
1809 }
1810
1811 /* logical drives */
1812 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
1813 INVALID_CHANNEL,sizeof(ulong32))) {
1814 drv_cnt = *(ulong32 *)ha->pscratch;
1815 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
1816 INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
1817 for (j = 0; j < drv_cnt; ++j) {
1818 drv_no = ((ulong32 *)ha->pscratch)[j];
1819 if (drv_no < MAX_LDRIVES) {
1820 ha->hdr[drv_no].is_logdrv = TRUE;
1821 TRACE2(("Drive %d is log. drive\n",drv_no));
1822 }
1823 }
1824 }
1825 alst = (gdth_arcdl_str *)ha->pscratch;
1826 alst->entries_avail = MAX_LDRIVES;
1827 alst->first_entry = 0;
1828 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
1829 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
1830 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
1831 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
1832 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
1833 for (j = 0; j < alst->entries_init; ++j) {
1834 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
1835 ha->hdr[j].is_master = alst->list[j].is_master;
1836 ha->hdr[j].is_parity = alst->list[j].is_parity;
1837 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
1838 ha->hdr[j].master_no = alst->list[j].cd_handle;
1839 }
1840 } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
1841 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
1842 0, 35 * sizeof(gdth_alist_str))) {
1843 for (j = 0; j < 35; ++j) {
1844 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
1845 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
1846 ha->hdr[j].is_master = alst2->is_master;
1847 ha->hdr[j].is_parity = alst2->is_parity;
1848 ha->hdr[j].is_hotfix = alst2->is_hotfix;
1849 ha->hdr[j].master_no = alst2->cd_handle;
1850 }
1851 }
1852 }
1853 }
1854
1855 /* initialize raw service */
1856 ha->raw_feat = 0;
1857 if (!force_dma32) {
1858 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
1859 if (ok)
1860 ha->raw_feat = GDT_64BIT;
1861 }
1862 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1863 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
1864 if (!ok) {
1865 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
1866 hanum, ha->status);
1867 return 0;
1868 }
1869 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
1870
1871 /* set/get features raw service (scatter/gather) */
1872 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
1873 0,0)) {
1874 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
1875 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
1876 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
1877 ha->info));
1878 ha->raw_feat |= (ushort)ha->info;
1879 }
1880 }
1881
1882 /* set/get features cache service (equal to raw service) */
1883 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
1884 SCATTER_GATHER,0)) {
1885 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
1886 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
1887 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
1888 ha->info));
1889 ha->cache_feat |= (ushort)ha->info;
1890 }
1891 }
1892
1893 /* reserve drives for raw service */
1894 if (reserve_mode != 0) {
1895 gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
1896 reserve_mode == 1 ? 1 : 3, 0, 0);
1897 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
1898 ha->status));
1899 }
1900 for (i = 0; i < MAX_RES_ARGS; i += 4) {
1901 if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
1902 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
1903 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
1904 reserve_list[i], reserve_list[i+1],
1905 reserve_list[i+2], reserve_list[i+3]));
1906 if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
1907 reserve_list[i+1], reserve_list[i+2] |
1908 (reserve_list[i+3] << 8))) {
1909 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
1910 hanum, ha->status);
1911 }
1912 }
1913 }
1914
1915 /* Determine OEM string using IOCTL */
1916 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
1917 oemstr->params.ctl_version = 0x01;
1918 oemstr->params.buffer_size = sizeof(oemstr->text);
1919 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
1920 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
1921 sizeof(gdth_oem_str_ioctl))) {
1922 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
1923 printk("GDT-HA %d: Vendor: %s Name: %s\n",
1924 hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
1925 /* Save the Host Drive inquiry data */
1da177e4
LT		 1926 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
1927 sizeof(ha->oem_name));
1da177e4
LT		 1928 } else {
1929 /* Old method, based on PCI ID */
1930 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
1931 printk("GDT-HA %d: Name: %s\n",
1932 hanum,ha->binfo.type_string);
1da177e4
LT		 1933 if (ha->oem_id == OEM_ID_INTEL)
1934 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
1935 else
1936 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
1da177e4
LT		 1937 }
1938
1939 /* scanning for host drives */
1940 for (i = 0; i < cdev_cnt; ++i)
1941 gdth_analyse_hdrive(hanum,i);
1942
1943 TRACE(("gdth_search_drives() OK\n"));
1944 return 1;
1945}
1946
1947static int gdth_analyse_hdrive(int hanum,ushort hdrive)
1948{
1949 register gdth_ha_str *ha;
1950 ulong32 drv_cyls;
1951 int drv_hds, drv_secs;
1952
1953 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
1954 if (hdrive >= MAX_HDRIVES)
1955 return 0;
1956 ha = HADATA(gdth_ctr_tab[hanum]);
1957
1958 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
1959 return 0;
1960 ha->hdr[hdrive].present = TRUE;
1961 ha->hdr[hdrive].size = ha->info;
1962
1963 /* evaluate mapping (sectors per head, heads per cylinder) */
1964 ha->hdr[hdrive].size &= ~SECS32;
1965 if (ha->info2 == 0) {
1966 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
1967 } else {
1968 drv_hds = ha->info2 & 0xff;
1969 drv_secs = (ha->info2 >> 8) & 0xff;
1970 drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
1971 }
1972 ha->hdr[hdrive].heads = (unchar)drv_hds;
1973 ha->hdr[hdrive].secs = (unchar)drv_secs;
1974 /* round size */
1975 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
1976
1977 if (ha->cache_feat & GDT_64BIT) {
1978 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
1979 && ha->info2 != 0) {
1980 ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
1981 }
1982 }
1983 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
1984 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
1985
1986 /* get informations about device */
1987 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
1988 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
1989 hdrive,ha->info));
1990 ha->hdr[hdrive].devtype = (ushort)ha->info;
1991 }
1992
1993 /* cluster info */
1994 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
1995 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
1996 hdrive,ha->info));
1997 if (!shared_access)
1998 ha->hdr[hdrive].cluster_type = (unchar)ha->info;
1999 }
2000
2001 /* R/W attributes */
2002 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
2003 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
2004 hdrive,ha->info));
2005 ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
2006 }
2007
2008 return 1;
2009}
2010
2011
2012/* command queueing/sending functions */
2013
2014static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
2015{
2016 register gdth_ha_str *ha;
2017 register Scsi_Cmnd *pscp;
2018 register Scsi_Cmnd *nscp;
2019 ulong flags;
2020 unchar b, t;
2021
2022 TRACE(("gdth_putq() priority %d\n",priority));
2023 ha = HADATA(gdth_ctr_tab[hanum]);
2024 spin_lock_irqsave(&ha->smp_lock, flags);
2025
687d2bc4 2026 if (!IS_GDTH_INTERNAL_CMD(scp)) {
cbd5f69b
LA		 2027 scp->SCp.this_residual = (int)priority;
2028 b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel;
2029 t = scp->device->id;
2030 if (priority >= DEFAULT_PRI) {
2031 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2032 (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
2033 TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
2034 scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
2035 }
1da177e4
LT		 2036 }
2037 }
2038
2039 if (ha->req_first==NULL) {
2040 ha->req_first = scp; /* queue was empty */
2041 scp->SCp.ptr = NULL;
2042 } else { /* queue not empty */
2043 pscp = ha->req_first;
2044 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2045 /* priority: 0-highest,..,0xff-lowest */
2046 while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
2047 pscp = nscp;
2048 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2049 }
2050 pscp->SCp.ptr = (char *)scp;
2051 scp->SCp.ptr = (char *)nscp;
2052 }
2053 spin_unlock_irqrestore(&ha->smp_lock, flags);
2054
2055#ifdef GDTH_STATISTICS
2056 flags = 0;
2057 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2058 ++flags;
2059 if (max_rq < flags) {
2060 max_rq = flags;
2061 TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
2062 }
2063#endif
2064}
2065
2066static void gdth_next(int hanum)
2067{
2068 register gdth_ha_str *ha;
2069 register Scsi_Cmnd *pscp;
2070 register Scsi_Cmnd *nscp;
2071 unchar b, t, l, firsttime;
2072 unchar this_cmd, next_cmd;
2073 ulong flags = 0;
2074 int cmd_index;
2075
2076 TRACE(("gdth_next() hanum %d\n",hanum));
2077 ha = HADATA(gdth_ctr_tab[hanum]);
2078 if (!gdth_polling)
2079 spin_lock_irqsave(&ha->smp_lock, flags);
2080
2081 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2082 this_cmd = firsttime = TRUE;
2083 next_cmd = gdth_polling ? FALSE:TRUE;
2084 cmd_index = 0;
2085
2086 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2087 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2088 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
687d2bc4 2089 if (!IS_GDTH_INTERNAL_CMD(nscp)) {
cbd5f69b
LA		 2090 b = virt_ctr ?
2091 NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
2092 t = nscp->device->id;
2093 l = nscp->device->lun;
2094 if (nscp->SCp.this_residual >= DEFAULT_PRI) {
2095 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2096 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2097 continue;
2098 }
2099 } else
2100 b = t = l = 0;
1da177e4
LT		 2101
2102 if (firsttime) {
2103 if (gdth_test_busy(hanum)) { /* controller busy ? */
2104 TRACE(("gdth_next() controller %d busy !\n",hanum));
2105 if (!gdth_polling) {
2106 spin_unlock_irqrestore(&ha->smp_lock, flags);
2107 return;
2108 }
2109 while (gdth_test_busy(hanum))
2110 gdth_delay(1);
2111 }
2112 firsttime = FALSE;
2113 }
2114
687d2bc4 2115 if (!IS_GDTH_INTERNAL_CMD(nscp)) {
1da177e4
LT		 2116 if (nscp->SCp.phase == -1) {
2117 nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
2118 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2119 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2120 b, t, l));
2121 /* TEST_UNIT_READY -> set scan mode */
2122 if ((ha->scan_mode & 0x0f) == 0) {
2123 if (b == 0 && t == 0 && l == 0) {
2124 ha->scan_mode |= 1;
2125 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2126 }
2127 } else if ((ha->scan_mode & 0x0f) == 1) {
2128 if (b == 0 && ((t == 0 && l == 1) ||
2129 (t == 1 && l == 0))) {
2130 nscp->SCp.sent_command = GDT_SCAN_START;
2131 nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2132 | SCSIRAWSERVICE;
2133 ha->scan_mode = 0x12;
2134 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2135 ha->scan_mode));
2136 } else {
2137 ha->scan_mode &= 0x10;
2138 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2139 }
2140 } else if (ha->scan_mode == 0x12) {
2141 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2142 nscp->SCp.phase = SCSIRAWSERVICE;
2143 nscp->SCp.sent_command = GDT_SCAN_END;
2144 ha->scan_mode &= 0x10;
2145 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2146 ha->scan_mode));
2147 }
2148 }
2149 }
2150 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2151 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2152 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2153 /* always GDT_CLUST_INFO! */
2154 nscp->SCp.sent_command = GDT_CLUST_INFO;
2155 }
2156 }
2157 }
2158
2159 if (nscp->SCp.sent_command != -1) {
2160 if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
2161 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2162 this_cmd = FALSE;
2163 next_cmd = FALSE;
2164 } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
2165 if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2166 this_cmd = FALSE;
2167 next_cmd = FALSE;
2168 } else {
2169 memset((char*)nscp->sense_buffer,0,16);
2170 nscp->sense_buffer[0] = 0x70;
2171 nscp->sense_buffer[2] = NOT_READY;
2172 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2173 if (!nscp->SCp.have_data_in)
2174 nscp->SCp.have_data_in++;
2175 else
b8bff2ae 2176 gdth_scsi_done(nscp);
1da177e4 2177 }
687d2bc4 2178 } else if (IS_GDTH_INTERNAL_CMD(nscp)) {
1da177e4
LT		 2179 if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
2180 this_cmd = FALSE;
2181 next_cmd = FALSE;
2182 } else if (b != ha->virt_bus) {
2183 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
2184 !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2185 this_cmd = FALSE;
2186 else
2187 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2188 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2189 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2190 nscp->cmnd[0], b, t, l));
2191 nscp->result = DID_BAD_TARGET << 16;
2192 if (!nscp->SCp.have_data_in)
2193 nscp->SCp.have_data_in++;
2194 else
b8bff2ae 2195 gdth_scsi_done(nscp);
1da177e4
LT		 2196 } else {
2197 switch (nscp->cmnd[0]) {
2198 case TEST_UNIT_READY:
2199 case INQUIRY:
2200 case REQUEST_SENSE:
2201 case READ_CAPACITY:
2202 case VERIFY:
2203 case START_STOP:
2204 case MODE_SENSE:
2205 case SERVICE_ACTION_IN:
2206 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2207 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2208 nscp->cmnd[4],nscp->cmnd[5]));
2209 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2210 /* return UNIT_ATTENTION */
2211 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2212 nscp->cmnd[0], t));
2213 ha->hdr[t].media_changed = FALSE;
2214 memset((char*)nscp->sense_buffer,0,16);
2215 nscp->sense_buffer[0] = 0x70;
2216 nscp->sense_buffer[2] = UNIT_ATTENTION;
2217 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2218 if (!nscp->SCp.have_data_in)
2219 nscp->SCp.have_data_in++;
2220 else
b8bff2ae
MW		 2221 gdth_scsi_done(nscp);
2222 } else if (gdth_internal_cache_cmd(hanum, nscp))
2223 gdth_scsi_done(nscp);
1da177e4
LT		 2224 break;
2225
2226 case ALLOW_MEDIUM_REMOVAL:
2227 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2228 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2229 nscp->cmnd[4],nscp->cmnd[5]));
2230 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2231 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2232 nscp->result = DID_OK << 16;
2233 nscp->sense_buffer[0] = 0;
2234 if (!nscp->SCp.have_data_in)
2235 nscp->SCp.have_data_in++;
2236 else
b8bff2ae 2237 gdth_scsi_done(nscp);
1da177e4
LT		 2238 } else {
2239 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2240 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2241 nscp->cmnd[4],nscp->cmnd[3]));
2242 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2243 this_cmd = FALSE;
2244 }
2245 break;
2246
2247 case RESERVE:
2248 case RELEASE:
2249 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2250 "RESERVE" : "RELEASE"));
2251 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2252 this_cmd = FALSE;
2253 break;
2254
2255 case READ_6:
2256 case WRITE_6:
2257 case READ_10:
2258 case WRITE_10:
2259 case READ_16:
2260 case WRITE_16:
2261 if (ha->hdr[t].media_changed) {
2262 /* return UNIT_ATTENTION */
2263 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2264 nscp->cmnd[0], t));
2265 ha->hdr[t].media_changed = FALSE;
2266 memset((char*)nscp->sense_buffer,0,16);
2267 nscp->sense_buffer[0] = 0x70;
2268 nscp->sense_buffer[2] = UNIT_ATTENTION;
2269 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2270 if (!nscp->SCp.have_data_in)
2271 nscp->SCp.have_data_in++;
2272 else
b8bff2ae
MW		 2273 gdth_scsi_done(nscp);
2274 } else if (!(cmd_index=gdth_fill_cache_cmd(hanum, nscp, t)))
1da177e4
LT		 2275 this_cmd = FALSE;
2276 break;
2277
2278 default:
2279 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2280 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2281 nscp->cmnd[4],nscp->cmnd[5]));
2282 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
2283 hanum, nscp->cmnd[0]);
2284 nscp->result = DID_ABORT << 16;
2285 if (!nscp->SCp.have_data_in)
2286 nscp->SCp.have_data_in++;
2287 else
b8bff2ae 2288 gdth_scsi_done(nscp);
1da177e4
LT		 2289 break;
2290 }
2291 }
2292
2293 if (!this_cmd)
2294 break;
2295 if (nscp == ha->req_first)
2296 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2297 else
2298 pscp->SCp.ptr = nscp->SCp.ptr;
2299 if (!next_cmd)
2300 break;
2301 }
2302
2303 if (ha->cmd_cnt > 0) {
2304 gdth_release_event(hanum);
2305 }
2306
2307 if (!gdth_polling)
2308 spin_unlock_irqrestore(&ha->smp_lock, flags);
2309
2310 if (gdth_polling && ha->cmd_cnt > 0) {
2311 if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
2312 printk("GDT-HA %d: Command %d timed out !\n",
2313 hanum,cmd_index);
2314 }
2315}
2316
2317static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
2318 char *buffer,ushort count)
2319{
2320 ushort cpcount,i;
2321 ushort cpsum,cpnow;
2322 struct scatterlist *sl;
2323 gdth_ha_str *ha;
2324 char *address;
2325
5d5ff44f 2326 cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
1da177e4
LT		 2327 ha = HADATA(gdth_ctr_tab[hanum]);
2328
2329 if (scp->use_sg) {
2330 sl = (struct scatterlist *)scp->request_buffer;
2331 for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
cbd5f69b 2332 unsigned long flags;
1da177e4
LT		 2333 cpnow = (ushort)sl->length;
2334 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2335 cpnow,cpsum,cpcount,(ushort)scp->bufflen));
2336 if (cpsum+cpnow > cpcount)
2337 cpnow = cpcount - cpsum;
2338 cpsum += cpnow;
2339 if (!sl->page) {
2340 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
2341 hanum);
2342 return;
2343 }
cbd5f69b 2344 local_irq_save(flags);
cbd5f69b
LA		 2345 address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
2346 memcpy(address,buffer,cpnow);
2347 flush_dcache_page(sl->page);
2348 kunmap_atomic(address, KM_BIO_SRC_IRQ);
cbd5f69b 2349 local_irq_restore(flags);
1da177e4
LT		 2350 if (cpsum == cpcount)
2351 break;
2352 buffer += cpnow;
2353 }
2354 } else {
2355 TRACE(("copy_internal() count %d\n",cpcount));
2356 memcpy((char*)scp->request_buffer,buffer,cpcount);
2357 }
2358}
2359
2360static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
2361{
2362 register gdth_ha_str *ha;
2363 unchar t;
2364 gdth_inq_data inq;
2365 gdth_rdcap_data rdc;
2366 gdth_sense_data sd;
2367 gdth_modep_data mpd;
2368
2369 ha = HADATA(gdth_ctr_tab[hanum]);
2370 t = scp->device->id;
2371 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2372 scp->cmnd[0],t));
2373
2374 scp->result = DID_OK << 16;
2375 scp->sense_buffer[0] = 0;
2376
2377 switch (scp->cmnd[0]) {
2378 case TEST_UNIT_READY:
2379 case VERIFY:
2380 case START_STOP:
2381 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2382 break;
2383
2384 case INQUIRY:
2385 TRACE2(("Inquiry hdrive %d devtype %d\n",
2386 t,ha->hdr[t].devtype));
2387 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2388 /* you can here set all disks to removable, if you want to do
2389 a flush using the ALLOW_MEDIUM_REMOVAL command */
2390 inq.modif_rmb = 0x00;
2391 if ((ha->hdr[t].devtype & 1) ||
2392 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2393 inq.modif_rmb = 0x80;
2394 inq.version = 2;
2395 inq.resp_aenc = 2;
2396 inq.add_length= 32;
2397 strcpy(inq.vendor,ha->oem_name);
2398 sprintf(inq.product,"Host Drive #%02d",t);
2399 strcpy(inq.revision," ");
2400 gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
2401 break;
2402
2403 case REQUEST_SENSE:
2404 TRACE2(("Request sense hdrive %d\n",t));
2405 sd.errorcode = 0x70;
2406 sd.segno = 0x00;
2407 sd.key = NO_SENSE;
2408 sd.info = 0;
2409 sd.add_length= 0;
2410 gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
2411 break;
2412
2413 case MODE_SENSE:
2414 TRACE2(("Mode sense hdrive %d\n",t));
2415 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2416 mpd.hd.data_length = sizeof(gdth_modep_data);
2417 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2418 mpd.hd.bd_length = sizeof(mpd.bd);
2419 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2420 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2421 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
2422 gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
2423 break;
2424
2425 case READ_CAPACITY:
2426 TRACE2(("Read capacity hdrive %d\n",t));
2427 if (ha->hdr[t].size > (ulong64)0xffffffff)
2428 rdc.last_block_no = 0xffffffff;
2429 else
2430 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2431 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
2432 gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
2433 break;
2434
2435 case SERVICE_ACTION_IN:
2436 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2437 (ha->cache_feat & GDT_64BIT)) {
2438 gdth_rdcap16_data rdc16;
2439
2440 TRACE2(("Read capacity (16) hdrive %d\n",t));
2441 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2442 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
2443 gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
2444 } else {
2445 scp->result = DID_ABORT << 16;
2446 }
2447 break;
2448
2449 default:
2450 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2451 break;
2452 }
2453
2454 if (!scp->SCp.have_data_in)
2455 scp->SCp.have_data_in++;
2456 else
2457 return 1;
2458
2459 return 0;
2460}
2461
2462static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
2463{
2464 register gdth_ha_str *ha;
2465 register gdth_cmd_str *cmdp;
2466 struct scatterlist *sl;
2467 ulong32 cnt, blockcnt;
2468 ulong64 no, blockno;
2469 dma_addr_t phys_addr;
2470 int i, cmd_index, read_write, sgcnt, mode64;
2471 struct page *page;
2472 ulong offset;
2473
2474 ha = HADATA(gdth_ctr_tab[hanum]);
2475 cmdp = ha->pccb;
2476 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2477 scp->cmnd[0],scp->cmd_len,hdrive));
2478
2479 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2480 return 0;
2481
2482 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2483 /* test for READ_16, WRITE_16 if !mode64 ? ---
2484 not required, should not occur due to error return on
2485 READ_CAPACITY_16 */
2486
2487 cmdp->Service = CACHESERVICE;
2488 cmdp->RequestBuffer = scp;
2489 /* search free command index */
2490 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
2491 TRACE(("GDT: No free command index found\n"));
2492 return 0;
2493 }
2494 /* if it's the first command, set command semaphore */
2495 if (ha->cmd_cnt == 0)
2496 gdth_set_sema0(hanum);
2497
2498 /* fill command */
2499 read_write = 0;
2500 if (scp->SCp.sent_command != -1)
2501 cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
2502 else if (scp->cmnd[0] == RESERVE)
2503 cmdp->OpCode = GDT_RESERVE_DRV;
2504 else if (scp->cmnd[0] == RELEASE)
2505 cmdp->OpCode = GDT_RELEASE_DRV;
2506 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2507 if (scp->cmnd[4] & 1) /* prevent ? */
2508 cmdp->OpCode = GDT_MOUNT;
2509 else if (scp->cmnd[3] & 1) /* removable drive ? */
2510 cmdp->OpCode = GDT_UNMOUNT;
2511 else
2512 cmdp->OpCode = GDT_FLUSH;
2513 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2514 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2515 ) {
2516 read_write = 1;
2517 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2518 (ha->cache_feat & GDT_WR_THROUGH)))
2519 cmdp->OpCode = GDT_WRITE_THR;
2520 else
2521 cmdp->OpCode = GDT_WRITE;
2522 } else {
2523 read_write = 2;
2524 cmdp->OpCode = GDT_READ;
2525 }
2526
2527 cmdp->BoardNode = LOCALBOARD;
2528 if (mode64) {
2529 cmdp->u.cache64.DeviceNo = hdrive;
2530 cmdp->u.cache64.BlockNo = 1;
2531 cmdp->u.cache64.sg_canz = 0;
2532 } else {
2533 cmdp->u.cache.DeviceNo = hdrive;
2534 cmdp->u.cache.BlockNo = 1;
2535 cmdp->u.cache.sg_canz = 0;
2536 }
2537
2538 if (read_write) {
2539 if (scp->cmd_len == 16) {
2540 memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
2541 blockno = be64_to_cpu(no);
2542 memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
2543 blockcnt = be32_to_cpu(cnt);
2544 } else if (scp->cmd_len == 10) {
2545 memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
2546 blockno = be32_to_cpu(no);
2547 memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
2548 blockcnt = be16_to_cpu(cnt);
2549 } else {
2550 memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
2551 blockno = be32_to_cpu(no) & 0x001fffffUL;
2552 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2553 }
2554 if (mode64) {
2555 cmdp->u.cache64.BlockNo = blockno;
2556 cmdp->u.cache64.BlockCnt = blockcnt;
2557 } else {
2558 cmdp->u.cache.BlockNo = (ulong32)blockno;
2559 cmdp->u.cache.BlockCnt = blockcnt;
2560 }
2561
2562 if (scp->use_sg) {
2563 sl = (struct scatterlist *)scp->request_buffer;
2564 sgcnt = scp->use_sg;
2565 scp->SCp.Status = GDTH_MAP_SG;
2566 scp->SCp.Message = (read_write == 1 ?
2567 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2568 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
2569 if (mode64) {
2570 cmdp->u.cache64.DestAddr= (ulong64)-1;
2571 cmdp->u.cache64.sg_canz = sgcnt;
2572 for (i=0; i<sgcnt; ++i,++sl) {
2573 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2574#ifdef GDTH_DMA_STATISTICS
2575 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2576 ha->dma64_cnt++;
2577 else
2578 ha->dma32_cnt++;
2579#endif
2580 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2581 }
2582 } else {
2583 cmdp->u.cache.DestAddr= 0xffffffff;
2584 cmdp->u.cache.sg_canz = sgcnt;
2585 for (i=0; i<sgcnt; ++i,++sl) {
2586 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2587#ifdef GDTH_DMA_STATISTICS
2588 ha->dma32_cnt++;
2589#endif
2590 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2591 }
2592 }
2593
2594#ifdef GDTH_STATISTICS
2595 if (max_sg < (ulong32)sgcnt) {
2596 max_sg = (ulong32)sgcnt;
2597 TRACE3(("GDT: max_sg = %d\n",max_sg));
2598 }
2599#endif
2600
40cdc840 2601 } else if (scp->request_bufflen) {
1da177e4
LT		 2602 scp->SCp.Status = GDTH_MAP_SINGLE;
2603 scp->SCp.Message = (read_write == 1 ?
2604 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2605 page = virt_to_page(scp->request_buffer);
2606 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
2607 phys_addr = pci_map_page(ha->pdev,page,offset,
2608 scp->request_bufflen,scp->SCp.Message);
2609 scp->SCp.dma_handle = phys_addr;
2610 if (mode64) {
2611 if (ha->cache_feat & SCATTER_GATHER) {
2612 cmdp->u.cache64.DestAddr = (ulong64)-1;
2613 cmdp->u.cache64.sg_canz = 1;
2614 cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
2615 cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
2616 cmdp->u.cache64.sg_lst[1].sg_len = 0;
2617 } else {
2618 cmdp->u.cache64.DestAddr = phys_addr;
2619 cmdp->u.cache64.sg_canz= 0;
2620 }
2621 } else {
2622 if (ha->cache_feat & SCATTER_GATHER) {
2623 cmdp->u.cache.DestAddr = 0xffffffff;
2624 cmdp->u.cache.sg_canz = 1;
2625 cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
2626 cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
2627 cmdp->u.cache.sg_lst[1].sg_len = 0;
2628 } else {
2629 cmdp->u.cache.DestAddr = phys_addr;
2630 cmdp->u.cache.sg_canz= 0;
2631 }
2632 }
2633 }
2634 }
2635 /* evaluate command size, check space */
2636 if (mode64) {
2637 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2638 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2639 cmdp->u.cache64.sg_lst[0].sg_ptr,
2640 cmdp->u.cache64.sg_lst[0].sg_len));
2641 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2642 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2643 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2644 (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2645 } else {
2646 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2647 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2648 cmdp->u.cache.sg_lst[0].sg_ptr,
2649 cmdp->u.cache.sg_lst[0].sg_len));
2650 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2651 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
2652 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
2653 (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
2654 }
2655 if (ha->cmd_len & 3)
2656 ha->cmd_len += (4 - (ha->cmd_len & 3));
2657
2658 if (ha->cmd_cnt > 0) {
2659 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2660 ha->ic_all_size) {
2661 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
2662 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2663 return 0;
2664 }
2665 }
2666
2667 /* copy command */
2668 gdth_copy_command(hanum);
2669 return cmd_index;
2670}
2671
2672static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
2673{
2674 register gdth_ha_str *ha;
2675 register gdth_cmd_str *cmdp;
2676 struct scatterlist *sl;
2677 ushort i;
2678 dma_addr_t phys_addr, sense_paddr;
2679 int cmd_index, sgcnt, mode64;
2680 unchar t,l;
2681 struct page *page;
2682 ulong offset;
2683
2684 ha = HADATA(gdth_ctr_tab[hanum]);
2685 t = scp->device->id;
2686 l = scp->device->lun;
2687 cmdp = ha->pccb;
2688 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
2689 scp->cmnd[0],b,t,l));
2690
2691 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2692 return 0;
2693
2694 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
2695
2696 cmdp->Service = SCSIRAWSERVICE;
2697 cmdp->RequestBuffer = scp;
2698 /* search free command index */
2699 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
2700 TRACE(("GDT: No free command index found\n"));
2701 return 0;
2702 }
2703 /* if it's the first command, set command semaphore */
2704 if (ha->cmd_cnt == 0)
2705 gdth_set_sema0(hanum);
2706
2707 /* fill command */
2708 if (scp->SCp.sent_command != -1) {
2709 cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
2710 cmdp->BoardNode = LOCALBOARD;
2711 if (mode64) {
2712 cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
2713 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2714 cmdp->OpCode, cmdp->u.raw64.direction));
2715 /* evaluate command size */
2716 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
2717 } else {
2718 cmdp->u.raw.direction = (scp->SCp.phase >> 8);
2719 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2720 cmdp->OpCode, cmdp->u.raw.direction));
2721 /* evaluate command size */
2722 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
2723 }
2724
2725 } else {
2726 page = virt_to_page(scp->sense_buffer);
2727 offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
2728 sense_paddr = pci_map_page(ha->pdev,page,offset,
2729 16,PCI_DMA_FROMDEVICE);
cbd5f69b 2730 *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
1da177e4 2731 /* high part, if 64bit */
cbd5f69b 2732 *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
1da177e4
LT		 2733 cmdp->OpCode = GDT_WRITE; /* always */
2734 cmdp->BoardNode = LOCALBOARD;
2735 if (mode64) {
2736 cmdp->u.raw64.reserved = 0;
2737 cmdp->u.raw64.mdisc_time = 0;
2738 cmdp->u.raw64.mcon_time = 0;
2739 cmdp->u.raw64.clen = scp->cmd_len;
2740 cmdp->u.raw64.target = t;
2741 cmdp->u.raw64.lun = l;
2742 cmdp->u.raw64.bus = b;
2743 cmdp->u.raw64.priority = 0;
2744 cmdp->u.raw64.sdlen = scp->request_bufflen;
2745 cmdp->u.raw64.sense_len = 16;
2746 cmdp->u.raw64.sense_data = sense_paddr;
2747 cmdp->u.raw64.direction =
2748 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2749 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
bb9ba31c 2750 cmdp->u.raw64.sg_ranz = 0;
1da177e4
LT		 2751 } else {
2752 cmdp->u.raw.reserved = 0;
2753 cmdp->u.raw.mdisc_time = 0;
2754 cmdp->u.raw.mcon_time = 0;
2755 cmdp->u.raw.clen = scp->cmd_len;
2756 cmdp->u.raw.target = t;
2757 cmdp->u.raw.lun = l;
2758 cmdp->u.raw.bus = b;
2759 cmdp->u.raw.priority = 0;
2760 cmdp->u.raw.link_p = 0;
2761 cmdp->u.raw.sdlen = scp->request_bufflen;
2762 cmdp->u.raw.sense_len = 16;
2763 cmdp->u.raw.sense_data = sense_paddr;
2764 cmdp->u.raw.direction =
2765 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2766 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
bb9ba31c 2767 cmdp->u.raw.sg_ranz = 0;
1da177e4
LT		 2768 }
2769
2770 if (scp->use_sg) {
2771 sl = (struct scatterlist *)scp->request_buffer;
2772 sgcnt = scp->use_sg;
2773 scp->SCp.Status = GDTH_MAP_SG;
2774 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
2775 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
2776 if (mode64) {
2777 cmdp->u.raw64.sdata = (ulong64)-1;
2778 cmdp->u.raw64.sg_ranz = sgcnt;
2779 for (i=0; i<sgcnt; ++i,++sl) {
2780 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2781#ifdef GDTH_DMA_STATISTICS
2782 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2783 ha->dma64_cnt++;
2784 else
2785 ha->dma32_cnt++;
2786#endif
2787 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
2788 }
2789 } else {
2790 cmdp->u.raw.sdata = 0xffffffff;
2791 cmdp->u.raw.sg_ranz = sgcnt;
2792 for (i=0; i<sgcnt; ++i,++sl) {
2793 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
2794#ifdef GDTH_DMA_STATISTICS
2795 ha->dma32_cnt++;
2796#endif
2797 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
2798 }
2799 }
2800
2801#ifdef GDTH_STATISTICS
2802 if (max_sg < sgcnt) {
2803 max_sg = sgcnt;
2804 TRACE3(("GDT: max_sg = %d\n",sgcnt));
2805 }
2806#endif
2807
cbd5f69b 2808 } else if (scp->request_bufflen) {
1da177e4
LT		 2809 scp->SCp.Status = GDTH_MAP_SINGLE;
2810 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
2811 page = virt_to_page(scp->request_buffer);
2812 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
2813 phys_addr = pci_map_page(ha->pdev,page,offset,
2814 scp->request_bufflen,scp->SCp.Message);
2815 scp->SCp.dma_handle = phys_addr;
2816
2817 if (mode64) {
2818 if (ha->raw_feat & SCATTER_GATHER) {
2819 cmdp->u.raw64.sdata = (ulong64)-1;
2820 cmdp->u.raw64.sg_ranz= 1;
2821 cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
2822 cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
2823 cmdp->u.raw64.sg_lst[1].sg_len = 0;
2824 } else {
2825 cmdp->u.raw64.sdata = phys_addr;
2826 cmdp->u.raw64.sg_ranz= 0;
2827 }
2828 } else {
2829 if (ha->raw_feat & SCATTER_GATHER) {
2830 cmdp->u.raw.sdata = 0xffffffff;
2831 cmdp->u.raw.sg_ranz= 1;
2832 cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
2833 cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
2834 cmdp->u.raw.sg_lst[1].sg_len = 0;
2835 } else {
2836 cmdp->u.raw.sdata = phys_addr;
2837 cmdp->u.raw.sg_ranz= 0;
2838 }
2839 }
2840 }
2841 if (mode64) {
2842 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2843 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
2844 cmdp->u.raw64.sg_lst[0].sg_ptr,
2845 cmdp->u.raw64.sg_lst[0].sg_len));
2846 /* evaluate command size */
2847 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
2848 (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
2849 } else {
2850 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2851 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
2852 cmdp->u.raw.sg_lst[0].sg_ptr,
2853 cmdp->u.raw.sg_lst[0].sg_len));
2854 /* evaluate command size */
2855 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
2856 (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
2857 }
2858 }
2859 /* check space */
2860 if (ha->cmd_len & 3)
2861 ha->cmd_len += (4 - (ha->cmd_len & 3));
2862
2863 if (ha->cmd_cnt > 0) {
2864 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2865 ha->ic_all_size) {
2866 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
2867 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2868 return 0;
2869 }
2870 }
2871
2872 /* copy command */
2873 gdth_copy_command(hanum);
2874 return cmd_index;
2875}
2876
2877static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
2878{
2879 register gdth_ha_str *ha;
2880 register gdth_cmd_str *cmdp;
2881 int cmd_index;
2882
2883 ha = HADATA(gdth_ctr_tab[hanum]);
2884 cmdp= ha->pccb;
2885 TRACE2(("gdth_special_cmd(): "));
2886
2887 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2888 return 0;
2889
2890 memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
2891 cmdp->RequestBuffer = scp;
2892
2893 /* search free command index */
2894 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
2895 TRACE(("GDT: No free command index found\n"));
2896 return 0;
2897 }
2898
2899 /* if it's the first command, set command semaphore */
2900 if (ha->cmd_cnt == 0)
2901 gdth_set_sema0(hanum);
2902
2903 /* evaluate command size, check space */
2904 if (cmdp->OpCode == GDT_IOCTL) {
2905 TRACE2(("IOCTL\n"));
2906 ha->cmd_len =
2907 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
2908 } else if (cmdp->Service == CACHESERVICE) {
2909 TRACE2(("cache command %d\n",cmdp->OpCode));
2910 if (ha->cache_feat & GDT_64BIT)
2911 ha->cmd_len =
2912 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
2913 else
2914 ha->cmd_len =
2915 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
2916 } else if (cmdp->Service == SCSIRAWSERVICE) {
2917 TRACE2(("raw command %d\n",cmdp->OpCode));
2918 if (ha->raw_feat & GDT_64BIT)
2919 ha->cmd_len =
2920 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
2921 else
2922 ha->cmd_len =
2923 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
2924 }
2925
2926 if (ha->cmd_len & 3)
2927 ha->cmd_len += (4 - (ha->cmd_len & 3));
2928
2929 if (ha->cmd_cnt > 0) {
2930 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2931 ha->ic_all_size) {
2932 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
2933 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2934 return 0;
2935 }
2936 }
2937
2938 /* copy command */
2939 gdth_copy_command(hanum);
2940 return cmd_index;
2941}
2942
2943
2944/* Controller event handling functions */
2945static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
2946 ushort idx, gdth_evt_data *evt)
2947{
2948 gdth_evt_str *e;
2949 struct timeval tv;
2950
2951 /* no GDTH_LOCK_HA() ! */
2952 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
2953 if (source == 0) /* no source -> no event */
2954 return NULL;
2955
2956 if (ebuffer[elastidx].event_source == source &&
2957 ebuffer[elastidx].event_idx == idx &&
2958 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
2959 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
2960 (char *)&evt->eu, evt->size)) ||
2961 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
2962 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
2963 (char *)&evt->event_string)))) {
2964 e = &ebuffer[elastidx];
2965 do_gettimeofday(&tv);
2966 e->last_stamp = tv.tv_sec;
2967 ++e->same_count;
2968 } else {
2969 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
2970 ++elastidx;
2971 if (elastidx == MAX_EVENTS)
2972 elastidx = 0;
2973 if (elastidx == eoldidx) { /* reached mark ? */
2974 ++eoldidx;
2975 if (eoldidx == MAX_EVENTS)
2976 eoldidx = 0;
2977 }
2978 }
2979 e = &ebuffer[elastidx];
2980 e->event_source = source;
2981 e->event_idx = idx;
2982 do_gettimeofday(&tv);
2983 e->first_stamp = e->last_stamp = tv.tv_sec;
2984 e->same_count = 1;
2985 e->event_data = *evt;
2986 e->application = 0;
2987 }
2988 return e;
2989}
2990
2991static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
2992{
2993 gdth_evt_str *e;
2994 int eindex;
2995 ulong flags;
2996
2997 TRACE2(("gdth_read_event() handle %d\n", handle));
2998 spin_lock_irqsave(&ha->smp_lock, flags);
2999 if (handle == -1)
3000 eindex = eoldidx;
3001 else
3002 eindex = handle;
3003 estr->event_source = 0;
3004
3005 if (eindex >= MAX_EVENTS) {
3006 spin_unlock_irqrestore(&ha->smp_lock, flags);
3007 return eindex;
3008 }
3009 e = &ebuffer[eindex];
3010 if (e->event_source != 0) {
3011 if (eindex != elastidx) {
3012 if (++eindex == MAX_EVENTS)
3013 eindex = 0;
3014 } else {
3015 eindex = -1;
3016 }
3017 memcpy(estr, e, sizeof(gdth_evt_str));
3018 }
3019 spin_unlock_irqrestore(&ha->smp_lock, flags);
3020 return eindex;
3021}
3022
3023static void gdth_readapp_event(gdth_ha_str *ha,
3024 unchar application, gdth_evt_str *estr)
3025{
3026 gdth_evt_str *e;
3027 int eindex;
3028 ulong flags;
3029 unchar found = FALSE;
3030
3031 TRACE2(("gdth_readapp_event() app. %d\n", application));
3032 spin_lock_irqsave(&ha->smp_lock, flags);
3033 eindex = eoldidx;
3034 for (;;) {
3035 e = &ebuffer[eindex];
3036 if (e->event_source == 0)
3037 break;
3038 if ((e->application & application) == 0) {
3039 e->application |= application;
3040 found = TRUE;
3041 break;
3042 }
3043 if (eindex == elastidx)
3044 break;
3045 if (++eindex == MAX_EVENTS)
3046 eindex = 0;
3047 }
3048 if (found)
3049 memcpy(estr, e, sizeof(gdth_evt_str));
3050 else
3051 estr->event_source = 0;
3052 spin_unlock_irqrestore(&ha->smp_lock, flags);
3053}
3054
3055static void gdth_clear_events(void)
3056{
3057 TRACE(("gdth_clear_events()"));
3058
3059 eoldidx = elastidx = 0;
3060 ebuffer[0].event_source = 0;
3061}
3062
3063
3064/* SCSI interface functions */
3065
7d12e780 3066static irqreturn_t gdth_interrupt(int irq,void *dev_id)
1da177e4
LT		 3067{
3068 gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
3069 register gdth_ha_str *ha;
3070 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
3071 gdt6_dpram_str __iomem *dp6_ptr;
3072 gdt2_dpram_str __iomem *dp2_ptr;
3073 Scsi_Cmnd *scp;
3074 int hanum, rval, i;
3075 unchar IStatus;
3076 ushort Service;
3077 ulong flags = 0;
3078#ifdef INT_COAL
3079 int coalesced = FALSE;
3080 int next = FALSE;
3081 gdth_coal_status *pcs = NULL;
3082 int act_int_coal = 0;
3083#endif
3084
3085 TRACE(("gdth_interrupt() IRQ %d\n",irq));
3086
3087 /* if polling and not from gdth_wait() -> return */
3088 if (gdth_polling) {
3089 if (!gdth_from_wait) {
3090 return IRQ_HANDLED;
3091 }
3092 }
3093
3094 if (!gdth_polling)
cbd5f69b 3095 spin_lock_irqsave(&ha2->smp_lock, flags);
1da177e4
LT		 3096 wait_index = 0;
3097
3098 /* search controller */
3099 if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
3100 /* spurious interrupt */
3101 if (!gdth_polling)
3102 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3103 return IRQ_HANDLED;
3104 }
3105 ha = HADATA(gdth_ctr_tab[hanum]);
3106
3107#ifdef GDTH_STATISTICS
3108 ++act_ints;
3109#endif
3110
3111#ifdef INT_COAL
3112 /* See if the fw is returning coalesced status */
3113 if (IStatus == COALINDEX) {
3114 /* Coalesced status. Setup the initial status
3115 buffer pointer and flags */
3116 pcs = ha->coal_stat;
3117 coalesced = TRUE;
3118 next = TRUE;
3119 }
3120
3121 do {
3122 if (coalesced) {
3123 /* For coalesced requests all status
3124 information is found in the status buffer */
3125 IStatus = (unchar)(pcs->status & 0xff);
3126 }
3127#endif
3128
3129 if (ha->type == GDT_EISA) {
3130 if (IStatus & 0x80) { /* error flag */
3131 IStatus &= ~0x80;
3132 ha->status = inw(ha->bmic + MAILBOXREG+8);
3133 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3134 } else /* no error */
3135 ha->status = S_OK;
3136 ha->info = inl(ha->bmic + MAILBOXREG+12);
3137 ha->service = inw(ha->bmic + MAILBOXREG+10);
3138 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3139
3140 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3141 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3142 } else if (ha->type == GDT_ISA) {
3143 dp2_ptr = ha->brd;
3144 if (IStatus & 0x80) { /* error flag */
3145 IStatus &= ~0x80;
3146 ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
3147 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3148 } else /* no error */
3149 ha->status = S_OK;
3150 ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
3151 ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
3152 ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
3153
3154 gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3155 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3156 gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3157 } else if (ha->type == GDT_PCI) {
3158 dp6_ptr = ha->brd;
3159 if (IStatus & 0x80) { /* error flag */
3160 IStatus &= ~0x80;
3161 ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
3162 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3163 } else /* no error */
3164 ha->status = S_OK;
3165 ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
3166 ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
3167 ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
3168
3169 gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3170 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3171 gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
3172 } else if (ha->type == GDT_PCINEW) {
3173 if (IStatus & 0x80) { /* error flag */
3174 IStatus &= ~0x80;
3175 ha->status = inw(PTR2USHORT(&ha->plx->status));
3176 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3177 } else
3178 ha->status = S_OK;
3179 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3180 ha->service = inw(PTR2USHORT(&ha->plx->service));
3181 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3182
3183 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3184 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3185 } else if (ha->type == GDT_PCIMPR) {
3186 dp6m_ptr = ha->brd;
3187 if (IStatus & 0x80) { /* error flag */
3188 IStatus &= ~0x80;
3189#ifdef INT_COAL
3190 if (coalesced)
107e716b 3191 ha->status = pcs->ext_status & 0xffff;
1da177e4
LT		 3192 else
3193#endif
3194 ha->status = gdth_readw(&dp6m_ptr->i960r.status);
3195 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3196 } else /* no error */
3197 ha->status = S_OK;
3198#ifdef INT_COAL
3199 /* get information */
3200 if (coalesced) {
3201 ha->info = pcs->info0;
3202 ha->info2 = pcs->info1;
107e716b 3203 ha->service = (pcs->ext_status >> 16) & 0xffff;
1da177e4
LT		 3204 } else
3205#endif
3206 {
3207 ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
3208 ha->service = gdth_readw(&dp6m_ptr->i960r.service);
3209 ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
3210 }
3211 /* event string */
3212 if (IStatus == ASYNCINDEX) {
3213 if (ha->service != SCREENSERVICE &&
3214 (ha->fw_vers & 0xff) >= 0x1a) {
3215 ha->dvr.severity = gdth_readb
3216 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3217 for (i = 0; i < 256; ++i) {
3218 ha->dvr.event_string[i] = gdth_readb
3219 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3220 if (ha->dvr.event_string[i] == 0)
3221 break;
3222 }
3223 }
3224 }
3225#ifdef INT_COAL
3226 /* Make sure that non coalesced interrupts get cleared
3227 before being handled by gdth_async_event/gdth_sync_event */
3228 if (!coalesced)
3229#endif
3230 {
3231 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3232 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3233 }
3234 } else {
3235 TRACE2(("gdth_interrupt() unknown controller type\n"));
3236 if (!gdth_polling)
3237 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3238 return IRQ_HANDLED;
3239 }
3240
3241 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3242 IStatus,ha->status,ha->info));
3243
3244 if (gdth_from_wait) {
3245 wait_hanum = hanum;
3246 wait_index = (int)IStatus;
3247 }
3248
3249 if (IStatus == ASYNCINDEX) {
3250 TRACE2(("gdth_interrupt() async. event\n"));
3251 gdth_async_event(hanum);
3252 if (!gdth_polling)
3253 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3254 gdth_next(hanum);
3255 return IRQ_HANDLED;
3256 }
3257
3258 if (IStatus == SPEZINDEX) {
3259 TRACE2(("Service unknown or not initialized !\n"));
3260 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3261 ha->dvr.eu.driver.ionode = hanum;
3262 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3263 if (!gdth_polling)
3264 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3265 return IRQ_HANDLED;
3266 }
3267 scp = ha->cmd_tab[IStatus-2].cmnd;
3268 Service = ha->cmd_tab[IStatus-2].service;
3269 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3270 if (scp == UNUSED_CMND) {
3271 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3272 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3273 ha->dvr.eu.driver.ionode = hanum;
3274 ha->dvr.eu.driver.index = IStatus;
3275 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3276 if (!gdth_polling)
3277 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3278 return IRQ_HANDLED;
3279 }
3280 if (scp == INTERNAL_CMND) {
3281 TRACE(("gdth_interrupt() answer to internal command\n"));
3282 if (!gdth_polling)
3283 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3284 return IRQ_HANDLED;
3285 }
3286
3287 TRACE(("gdth_interrupt() sync. status\n"));
3288 rval = gdth_sync_event(hanum,Service,IStatus,scp);
3289 if (!gdth_polling)
3290 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3291 if (rval == 2) {
3292 gdth_putq(hanum,scp,scp->SCp.this_residual);
3293 } else if (rval == 1) {
b8bff2ae 3294 gdth_scsi_done(scp);
1da177e4
LT		 3295 }
3296
3297#ifdef INT_COAL
3298 if (coalesced) {
3299 /* go to the next status in the status buffer */
3300 ++pcs;
3301#ifdef GDTH_STATISTICS
3302 ++act_int_coal;
3303 if (act_int_coal > max_int_coal) {
3304 max_int_coal = act_int_coal;
3305 printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
3306 }
3307#endif
3308 /* see if there is another status */
3309 if (pcs->status == 0)
3310 /* Stop the coalesce loop */
3311 next = FALSE;
3312 }
3313 } while (next);
3314
3315 /* coalescing only for new GDT_PCIMPR controllers available */
3316 if (ha->type == GDT_PCIMPR && coalesced) {
3317 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3318 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3319 }
3320#endif
3321
3322 gdth_next(hanum);
3323 return IRQ_HANDLED;
3324}
3325
3326static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
3327{
3328 register gdth_ha_str *ha;
3329 gdth_msg_str *msg;
3330 gdth_cmd_str *cmdp;
3331 unchar b, t;
3332
3333 ha = HADATA(gdth_ctr_tab[hanum]);
3334 cmdp = ha->pccb;
3335 TRACE(("gdth_sync_event() serv %d status %d\n",
3336 service,ha->status));
3337
3338 if (service == SCREENSERVICE) {
3339 msg = ha->pmsg;
3340 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3341 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3342 if (msg->msg_len > MSGLEN+1)
3343 msg->msg_len = MSGLEN+1;
3344 if (msg->msg_len)
3345 if (!(msg->msg_answer && msg->msg_ext)) {
3346 msg->msg_text[msg->msg_len] = '\0';
3347 printk("%s",msg->msg_text);
3348 }
3349
3350 if (msg->msg_ext && !msg->msg_answer) {
3351 while (gdth_test_busy(hanum))
3352 gdth_delay(0);
3353 cmdp->Service = SCREENSERVICE;
3354 cmdp->RequestBuffer = SCREEN_CMND;
3355 gdth_get_cmd_index(hanum);
3356 gdth_set_sema0(hanum);
3357 cmdp->OpCode = GDT_READ;
3358 cmdp->BoardNode = LOCALBOARD;
3359 cmdp->u.screen.reserved = 0;
3360 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3361 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3362 ha->cmd_offs_dpmem = 0;
3363 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3364 + sizeof(ulong64);
3365 ha->cmd_cnt = 0;
3366 gdth_copy_command(hanum);
3367 gdth_release_event(hanum);
3368 return 0;
3369 }
3370
3371 if (msg->msg_answer && msg->msg_alen) {
3372 /* default answers (getchar() not possible) */
3373 if (msg->msg_alen == 1) {
3374 msg->msg_alen = 0;
3375 msg->msg_len = 1;
3376 msg->msg_text[0] = 0;
3377 } else {
3378 msg->msg_alen -= 2;
3379 msg->msg_len = 2;
3380 msg->msg_text[0] = 1;
3381 msg->msg_text[1] = 0;
3382 }
3383 msg->msg_ext = 0;
3384 msg->msg_answer = 0;
3385 while (gdth_test_busy(hanum))
3386 gdth_delay(0);
3387 cmdp->Service = SCREENSERVICE;
3388 cmdp->RequestBuffer = SCREEN_CMND;
3389 gdth_get_cmd_index(hanum);
3390 gdth_set_sema0(hanum);
3391 cmdp->OpCode = GDT_WRITE;
3392 cmdp->BoardNode = LOCALBOARD;
3393 cmdp->u.screen.reserved = 0;
3394 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3395 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3396 ha->cmd_offs_dpmem = 0;
3397 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3398 + sizeof(ulong64);
3399 ha->cmd_cnt = 0;
3400 gdth_copy_command(hanum);
3401 gdth_release_event(hanum);
3402 return 0;
3403 }
3404 printk("\n");
3405
3406 } else {
3407 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
3408 t = scp->device->id;
3409 if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
3410 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3411 }
3412 /* cache or raw service */
3413 if (ha->status == S_BSY) {
3414 TRACE2(("Controller busy -> retry !\n"));
3415 if (scp->SCp.sent_command == GDT_MOUNT)
3416 scp->SCp.sent_command = GDT_CLUST_INFO;
3417 /* retry */
3418 return 2;
3419 }
3420 if (scp->SCp.Status == GDTH_MAP_SG)
3421 pci_unmap_sg(ha->pdev,scp->request_buffer,
3422 scp->use_sg,scp->SCp.Message);
3423 else if (scp->SCp.Status == GDTH_MAP_SINGLE)
3424 pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
3425 scp->request_bufflen,scp->SCp.Message);
3426 if (scp->SCp.buffer) {
3427 dma_addr_t addr;
cbd5f69b 3428 addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
1da177e4 3429 if (scp->host_scribble)
cbd5f69b
LA		 3430 addr += (dma_addr_t)
3431 ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
1da177e4
LT		 3432 pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
3433 }
3434
3435 if (ha->status == S_OK) {
3436 scp->SCp.Status = S_OK;
3437 scp->SCp.Message = ha->info;
3438 if (scp->SCp.sent_command != -1) {
3439 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3440 scp->SCp.sent_command));
3441 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3442 if (scp->SCp.sent_command == GDT_CLUST_INFO) {
3443 ha->hdr[t].cluster_type = (unchar)ha->info;
3444 if (!(ha->hdr[t].cluster_type &
3445 CLUSTER_MOUNTED)) {
3446 /* NOT MOUNTED -> MOUNT */
3447 scp->SCp.sent_command = GDT_MOUNT;
3448 if (ha->hdr[t].cluster_type &
3449 CLUSTER_RESERVED) {
3450 /* cluster drive RESERVED (on the other node) */
3451 scp->SCp.phase = -2; /* reservation conflict */
3452 }
3453 } else {
3454 scp->SCp.sent_command = -1;
3455 }
3456 } else {
3457 if (scp->SCp.sent_command == GDT_MOUNT) {
3458 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3459 ha->hdr[t].media_changed = TRUE;
3460 } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
3461 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3462 ha->hdr[t].media_changed = TRUE;
3463 }
3464 scp->SCp.sent_command = -1;
3465 }
3466 /* retry */
3467 scp->SCp.this_residual = HIGH_PRI;
3468 return 2;
3469 } else {
3470 /* RESERVE/RELEASE ? */
3471 if (scp->cmnd[0] == RESERVE) {
3472 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3473 } else if (scp->cmnd[0] == RELEASE) {
3474 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3475 }
3476 scp->result = DID_OK << 16;
3477 scp->sense_buffer[0] = 0;
3478 }
3479 } else {
3480 scp->SCp.Status = ha->status;
3481 scp->SCp.Message = ha->info;
3482
3483 if (scp->SCp.sent_command != -1) {
3484 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3485 scp->SCp.sent_command, ha->status));
3486 if (scp->SCp.sent_command == GDT_SCAN_START ||
3487 scp->SCp.sent_command == GDT_SCAN_END) {
3488 scp->SCp.sent_command = -1;
3489 /* retry */
3490 scp->SCp.this_residual = HIGH_PRI;
3491 return 2;
3492 }
3493 memset((char*)scp->sense_buffer,0,16);
3494 scp->sense_buffer[0] = 0x70;
3495 scp->sense_buffer[2] = NOT_READY;
3496 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3497 } else if (service == CACHESERVICE) {
3498 if (ha->status == S_CACHE_UNKNOWN &&
3499 (ha->hdr[t].cluster_type &
3500 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3501 /* bus reset -> force GDT_CLUST_INFO */
3502 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3503 }
3504 memset((char*)scp->sense_buffer,0,16);
3505 if (ha->status == (ushort)S_CACHE_RESERV) {
3506 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3507 } else {
3508 scp->sense_buffer[0] = 0x70;
3509 scp->sense_buffer[2] = NOT_READY;
3510 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3511 }
687d2bc4 3512 if (!IS_GDTH_INTERNAL_CMD(scp)) {
1da177e4
LT		 3513 ha->dvr.size = sizeof(ha->dvr.eu.sync);
3514 ha->dvr.eu.sync.ionode = hanum;
3515 ha->dvr.eu.sync.service = service;
3516 ha->dvr.eu.sync.status = ha->status;
3517 ha->dvr.eu.sync.info = ha->info;
3518 ha->dvr.eu.sync.hostdrive = t;
3519 if (ha->status >= 0x8000)
3520 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3521 else
3522 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3523 }
3524 } else {
3525 /* sense buffer filled from controller firmware (DMA) */
3526 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3527 scp->result = DID_BAD_TARGET << 16;
3528 } else {
3529 scp->result = (DID_OK << 16) | ha->info;
3530 }
3531 }
3532 }
3533 if (!scp->SCp.have_data_in)
3534 scp->SCp.have_data_in++;
3535 else
3536 return 1;
3537 }
3538
3539 return 0;
3540}
3541
3542static char *async_cache_tab[] = {
3543/* 0*/ "\011\000\002\002\002\004\002\006\004"
3544 "GDT HA %u, service %u, async. status %u/%lu unknown",
3545/* 1*/ "\011\000\002\002\002\004\002\006\004"
3546 "GDT HA %u, service %u, async. status %u/%lu unknown",
3547/* 2*/ "\005\000\002\006\004"
3548 "GDT HA %u, Host Drive %lu not ready",
3549/* 3*/ "\005\000\002\006\004"
3550 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3551/* 4*/ "\005\000\002\006\004"
3552 "GDT HA %u, mirror update on Host Drive %lu failed",
3553/* 5*/ "\005\000\002\006\004"
3554 "GDT HA %u, Mirror Drive %lu failed",
3555/* 6*/ "\005\000\002\006\004"
3556 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3557/* 7*/ "\005\000\002\006\004"
3558 "GDT HA %u, Host Drive %lu write protected",
3559/* 8*/ "\005\000\002\006\004"
3560 "GDT HA %u, media changed in Host Drive %lu",
3561/* 9*/ "\005\000\002\006\004"
3562 "GDT HA %u, Host Drive %lu is offline",
3563/*10*/ "\005\000\002\006\004"
3564 "GDT HA %u, media change of Mirror Drive %lu",
3565/*11*/ "\005\000\002\006\004"
3566 "GDT HA %u, Mirror Drive %lu is write protected",
3567/*12*/ "\005\000\002\006\004"
3568 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3569/*13*/ "\007\000\002\006\002\010\002"
3570 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3571/*14*/ "\005\000\002\006\002"
3572 "GDT HA %u, Array Drive %u: FAIL state entered",
3573/*15*/ "\005\000\002\006\002"
3574 "GDT HA %u, Array Drive %u: error",
3575/*16*/ "\007\000\002\006\002\010\002"
3576 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3577/*17*/ "\005\000\002\006\002"
3578 "GDT HA %u, Array Drive %u: parity build failed",
3579/*18*/ "\005\000\002\006\002"
3580 "GDT HA %u, Array Drive %u: drive rebuild failed",
3581/*19*/ "\005\000\002\010\002"
3582 "GDT HA %u, Test of Hot Fix %u failed",
3583/*20*/ "\005\000\002\006\002"
3584 "GDT HA %u, Array Drive %u: drive build finished successfully",
3585/*21*/ "\005\000\002\006\002"
3586 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3587/*22*/ "\007\000\002\006\002\010\002"
3588 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3589/*23*/ "\005\000\002\006\002"
3590 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3591/*24*/ "\005\000\002\010\002"
3592 "GDT HA %u, mirror update on Cache Drive %u completed",
3593/*25*/ "\005\000\002\010\002"
3594 "GDT HA %u, mirror update on Cache Drive %lu failed",
3595/*26*/ "\005\000\002\006\002"
3596 "GDT HA %u, Array Drive %u: drive rebuild started",
3597/*27*/ "\005\000\002\012\001"
3598 "GDT HA %u, Fault bus %u: SHELF OK detected",
3599/*28*/ "\005\000\002\012\001"
3600 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3601/*29*/ "\007\000\002\012\001\013\001"
3602 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3603/*30*/ "\007\000\002\012\001\013\001"
3604 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3605/*31*/ "\007\000\002\012\001\013\001"
3606 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3607/*32*/ "\007\000\002\012\001\013\001"
3608 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3609/*33*/ "\007\000\002\012\001\013\001"
3610 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3611/*34*/ "\011\000\002\012\001\013\001\006\004"
3612 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3613/*35*/ "\007\000\002\012\001\013\001"
3614 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3615/*36*/ "\007\000\002\012\001\013\001"
3616 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3617/*37*/ "\007\000\002\012\001\006\004"
3618 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3619/*38*/ "\007\000\002\012\001\013\001"
3620 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3621/*39*/ "\007\000\002\012\001\013\001"
3622 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3623/*40*/ "\007\000\002\012\001\013\001"
3624 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3625/*41*/ "\007\000\002\012\001\013\001"
3626 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3627/*42*/ "\005\000\002\006\002"
3628 "GDT HA %u, Array Drive %u: drive build started",
3629/*43*/ "\003\000\002"
3630 "GDT HA %u, DRAM parity error detected",
3631/*44*/ "\005\000\002\006\002"
3632 "GDT HA %u, Mirror Drive %u: update started",
3633/*45*/ "\007\000\002\006\002\010\002"
3634 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3635/*46*/ "\005\000\002\006\002"
3636 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3637/*47*/ "\005\000\002\006\002"
3638 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3639/*48*/ "\005\000\002\006\002"
3640 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3641/*49*/ "\005\000\002\006\002"
3642 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3643/*50*/ "\007\000\002\012\001\013\001"
3644 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3645/*51*/ "\005\000\002\006\002"
3646 "GDT HA %u, Array Drive %u: expand started",
3647/*52*/ "\005\000\002\006\002"
3648 "GDT HA %u, Array Drive %u: expand finished successfully",
3649/*53*/ "\005\000\002\006\002"
3650 "GDT HA %u, Array Drive %u: expand failed",
3651/*54*/ "\003\000\002"
3652 "GDT HA %u, CPU temperature critical",
3653/*55*/ "\003\000\002"
3654 "GDT HA %u, CPU temperature OK",
3655/*56*/ "\005\000\002\006\004"
3656 "GDT HA %u, Host drive %lu created",
3657/*57*/ "\005\000\002\006\002"
3658 "GDT HA %u, Array Drive %u: expand restarted",
3659/*58*/ "\005\000\002\006\002"
3660 "GDT HA %u, Array Drive %u: expand stopped",
3661/*59*/ "\005\000\002\010\002"
3662 "GDT HA %u, Mirror Drive %u: drive build quited",
3663/*60*/ "\005\000\002\006\002"
3664 "GDT HA %u, Array Drive %u: parity build quited",
3665/*61*/ "\005\000\002\006\002"
3666 "GDT HA %u, Array Drive %u: drive rebuild quited",
3667/*62*/ "\005\000\002\006\002"
3668 "GDT HA %u, Array Drive %u: parity verify started",
3669/*63*/ "\005\000\002\006\002"
3670 "GDT HA %u, Array Drive %u: parity verify done",
3671/*64*/ "\005\000\002\006\002"
3672 "GDT HA %u, Array Drive %u: parity verify failed",
3673/*65*/ "\005\000\002\006\002"
3674 "GDT HA %u, Array Drive %u: parity error detected",
3675/*66*/ "\005\000\002\006\002"
3676 "GDT HA %u, Array Drive %u: parity verify quited",
3677/*67*/ "\005\000\002\006\002"
3678 "GDT HA %u, Host Drive %u reserved",
3679/*68*/ "\005\000\002\006\002"
3680 "GDT HA %u, Host Drive %u mounted and released",
3681/*69*/ "\005\000\002\006\002"
3682 "GDT HA %u, Host Drive %u released",
3683/*70*/ "\003\000\002"
3684 "GDT HA %u, DRAM error detected and corrected with ECC",
3685/*71*/ "\003\000\002"
3686 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
3687/*72*/ "\011\000\002\012\001\013\001\014\001"
3688 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
3689/*73*/ "\005\000\002\006\002"
3690 "GDT HA %u, Host drive %u resetted locally",
3691/*74*/ "\005\000\002\006\002"
3692 "GDT HA %u, Host drive %u resetted remotely",
3693/*75*/ "\003\000\002"
3694 "GDT HA %u, async. status 75 unknown",
3695};
3696
3697
3698static int gdth_async_event(int hanum)
3699{
3700 gdth_ha_str *ha;
3701 gdth_cmd_str *cmdp;
3702 int cmd_index;
3703
3704 ha = HADATA(gdth_ctr_tab[hanum]);
3705 cmdp= ha->pccb;
3706 TRACE2(("gdth_async_event() ha %d serv %d\n",
3707 hanum,ha->service));
3708
3709 if (ha->service == SCREENSERVICE) {
3710 if (ha->status == MSG_REQUEST) {
3711 while (gdth_test_busy(hanum))
3712 gdth_delay(0);
3713 cmdp->Service = SCREENSERVICE;
3714 cmdp->RequestBuffer = SCREEN_CMND;
3715 cmd_index = gdth_get_cmd_index(hanum);
3716 gdth_set_sema0(hanum);
3717 cmdp->OpCode = GDT_READ;
3718 cmdp->BoardNode = LOCALBOARD;
3719 cmdp->u.screen.reserved = 0;
3720 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
3721 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3722 ha->cmd_offs_dpmem = 0;
3723 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3724 + sizeof(ulong64);
3725 ha->cmd_cnt = 0;
3726 gdth_copy_command(hanum);
3727 if (ha->type == GDT_EISA)
3728 printk("[EISA slot %d] ",(ushort)ha->brd_phys);
3729 else if (ha->type == GDT_ISA)
3730 printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
3731 else
3732 printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
3733 (ushort)((ha->brd_phys>>3)&0x1f));
3734 gdth_release_event(hanum);
3735 }
3736
3737 } else {
3738 if (ha->type == GDT_PCIMPR &&
3739 (ha->fw_vers & 0xff) >= 0x1a) {
3740 ha->dvr.size = 0;
3741 ha->dvr.eu.async.ionode = hanum;
3742 ha->dvr.eu.async.status = ha->status;
3743 /* severity and event_string already set! */
3744 } else {
3745 ha->dvr.size = sizeof(ha->dvr.eu.async);
3746 ha->dvr.eu.async.ionode = hanum;
3747 ha->dvr.eu.async.service = ha->service;
3748 ha->dvr.eu.async.status = ha->status;
3749 ha->dvr.eu.async.info = ha->info;
3750 *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
3751 }
3752 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
3753 gdth_log_event( &ha->dvr, NULL );
3754
3755 /* new host drive from expand? */
3756 if (ha->service == CACHESERVICE && ha->status == 56) {
3757 TRACE2(("gdth_async_event(): new host drive %d created\n",
3758 (ushort)ha->info));
3759 /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
3760 }
3761 }
3762 return 1;
3763}
3764
3765static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
3766{
3767 gdth_stackframe stack;
3768 char *f = NULL;
3769 int i,j;
3770
3771 TRACE2(("gdth_log_event()\n"));
3772 if (dvr->size == 0) {
3773 if (buffer == NULL) {
3774 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
3775 } else {
3776 sprintf(buffer,"Adapter %d: %s\n",
3777 dvr->eu.async.ionode,dvr->event_string);
3778 }
3779 } else if (dvr->eu.async.service == CACHESERVICE &&
3780 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
3781 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
3782 dvr->eu.async.status));
3783
3784 f = async_cache_tab[dvr->eu.async.status];
3785
3786 /* i: parameter to push, j: stack element to fill */
3787 for (j=0,i=1; i < f[0]; i+=2) {
3788 switch (f[i+1]) {
3789 case 4:
3790 stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
3791 break;
3792 case 2:
3793 stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
3794 break;
3795 case 1:
3796 stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
3797 break;
3798 default:
3799 break;
3800 }
3801 }
3802
3803 if (buffer == NULL) {
3804 printk(&f[(int)f[0]],stack);
3805 printk("\n");
3806 } else {
3807 sprintf(buffer,&f[(int)f[0]],stack);
3808 }
3809
3810 } else {
3811 if (buffer == NULL) {
3812 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
3813 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3814 } else {
3815 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
3816 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3817 }
3818 }
3819}
3820
3821#ifdef GDTH_STATISTICS
8e879041 3822static void gdth_timeout(ulong data)
1da177e4
LT		 3823{
3824 ulong32 i;
3825 Scsi_Cmnd *nscp;
3826 gdth_ha_str *ha;
3827 ulong flags;
3828 int hanum = 0;
3829
3830 ha = HADATA(gdth_ctr_tab[hanum]);
3831 spin_lock_irqsave(&ha->smp_lock, flags);
3832
3833 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
3834 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
3835 ++act_stats;
3836
3837 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
3838 ++act_rq;
3839
3840 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
3841 act_ints, act_ios, act_stats, act_rq));
3842 act_ints = act_ios = 0;
3843
3844 gdth_timer.expires = jiffies + 30 * HZ;
3845 add_timer(&gdth_timer);
3846 spin_unlock_irqrestore(&ha->smp_lock, flags);
3847}
3848#endif
3849
8e879041 3850static void __init internal_setup(char *str,int *ints)
1da177e4
LT		 3851{
3852 int i, argc;
3853 char *cur_str, *argv;
3854
3855 TRACE2(("internal_setup() str %s ints[0] %d\n",
3856 str ? str:"NULL", ints ? ints[0]:0));
3857
3858 /* read irq[] from ints[] */
3859 if (ints) {
3860 argc = ints[0];
3861 if (argc > 0) {
3862 if (argc > MAXHA)
3863 argc = MAXHA;
3864 for (i = 0; i < argc; ++i)
3865 irq[i] = ints[i+1];
3866 }
3867 }
3868
3869 /* analyse string */
3870 argv = str;
3871 while (argv && (cur_str = strchr(argv, ':'))) {
3872 int val = 0, c = *++cur_str;
3873
3874 if (c == 'n' || c == 'N')
3875 val = 0;
3876 else if (c == 'y' || c == 'Y')
3877 val = 1;
3878 else
3879 val = (int)simple_strtoul(cur_str, NULL, 0);
3880
3881 if (!strncmp(argv, "disable:", 8))
3882 disable = val;
3883 else if (!strncmp(argv, "reserve_mode:", 13))
3884 reserve_mode = val;
3885 else if (!strncmp(argv, "reverse_scan:", 13))
3886 reverse_scan = val;
3887 else if (!strncmp(argv, "hdr_channel:", 12))
3888 hdr_channel = val;
3889 else if (!strncmp(argv, "max_ids:", 8))
3890 max_ids = val;
3891 else if (!strncmp(argv, "rescan:", 7))
3892 rescan = val;
3893 else if (!strncmp(argv, "virt_ctr:", 9))
3894 virt_ctr = val;
3895 else if (!strncmp(argv, "shared_access:", 14))
3896 shared_access = val;
3897 else if (!strncmp(argv, "probe_eisa_isa:", 15))
3898 probe_eisa_isa = val;
3899 else if (!strncmp(argv, "reserve_list:", 13)) {
3900 reserve_list[0] = val;
3901 for (i = 1; i < MAX_RES_ARGS; i++) {
3902 cur_str = strchr(cur_str, ',');
3903 if (!cur_str)
3904 break;
3905 if (!isdigit((int)*++cur_str)) {
3906 --cur_str;
3907 break;
3908 }
3909 reserve_list[i] =
3910 (int)simple_strtoul(cur_str, NULL, 0);
3911 }
3912 if (!cur_str)
3913 break;
3914 argv = ++cur_str;
3915 continue;
3916 }
3917
3918 if ((argv = strchr(argv, ',')))
3919 ++argv;
3920 }
3921}
3922
3923int __init option_setup(char *str)
3924{
3925 int ints[MAXHA];
3926 char *cur = str;
3927 int i = 1;
3928
3929 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
3930
3931 while (cur && isdigit(*cur) && i <= MAXHA) {
3932 ints[i++] = simple_strtoul(cur, NULL, 0);
3933 if ((cur = strchr(cur, ',')) != NULL) cur++;
3934 }
3935
3936 ints[0] = i - 1;
3937 internal_setup(cur, ints);
3938 return 1;
3939}
3940
aed91cb5 3941
d0be4a7d 3942static int __init gdth_detect(struct scsi_host_template *shtp)
1da177e4 3943{
1da177e4
LT		 3944#ifdef DEBUG_GDTH
3945 printk("GDT: This driver contains debugging information !! Trace level = %d\n",
3946 DebugState);
3947 printk(" Destination of debugging information: ");
3948#ifdef __SERIAL__
3949#ifdef __COM2__
3950 printk("Serial port COM2\n");
3951#else
3952 printk("Serial port COM1\n");
3953#endif
3954#else
3955 printk("Console\n");
3956#endif
3957 gdth_delay(3000);
3958#endif
3959
3960 TRACE(("gdth_detect()\n"));
3961
3962 if (disable) {
3963 printk("GDT-HA: Controller driver disabled from command line !\n");
3964 return 0;
3965 }
3966
cbd5f69b 3967 printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
1da177e4 3968 /* initializations */
8514ef27 3969 gdth_polling = TRUE;
1da177e4
LT		 3970 gdth_clear_events();
3971
3972 /* As default we do not probe for EISA or ISA controllers */
3973 if (probe_eisa_isa) {
3974 /* scanning for controllers, at first: ISA controller */
aed91cb5
CH		 3975#ifdef CONFIG_ISA
3976 ulong32 isa_bios;
3977 for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
3978 isa_bios += 0x8000UL) {
3979 if (gdth_ctr_count >= MAXHA)
1da177e4 3980 break;
aed91cb5 3981 gdth_isa_probe_one(shtp, isa_bios);
1da177e4 3982 }
aed91cb5 3983#endif
706a5d45
CH		 3984#ifdef CONFIG_EISA
3985 {
3986 ushort eisa_slot;
3987 for (eisa_slot = 0x1000; eisa_slot <= 0x8000; eisa_slot += 0x1000) {
3988 if (gdth_ctr_count >= MAXHA)
1da177e4 3989 break;
706a5d45 3990 gdth_eisa_probe_one(shtp, eisa_slot);
1da177e4 3991 }
706a5d45
CH		 3992 }
3993#endif
1da177e4
LT		 3994 }
3995
8514ef27 3996#ifdef CONFIG_PCI
1da177e4 3997 /* scanning for PCI controllers */
8514ef27
CH		 3998 {
3999 gdth_pci_str pcistr[MAXHA];
4000 int cnt,ctr;
4001
1da177e4
LT		 4002 cnt = gdth_search_pci(pcistr);
4003 printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
4004 gdth_sort_pci(pcistr,cnt);
4005 for (ctr = 0; ctr < cnt; ++ctr) {
1da177e4
LT		 4006 if (gdth_ctr_count >= MAXHA)
4007 break;
8514ef27 4008 gdth_pci_probe_one(shtp, pcistr, ctr);
1da177e4 4009 }
8514ef27
CH		 4010 }
4011#endif /* CONFIG_PCI */
1da177e4
LT		 4012
4013 TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
4014 if (gdth_ctr_count > 0) {
4015#ifdef GDTH_STATISTICS
4016 TRACE2(("gdth_detect(): Initializing timer !\n"));
4017 init_timer(&gdth_timer);
4018 gdth_timer.expires = jiffies + HZ;
4019 gdth_timer.data = 0L;
4020 gdth_timer.function = gdth_timeout;
4021 add_timer(&gdth_timer);
4022#endif
4023 major = register_chrdev(0,"gdth",&gdth_fops);
e041c683 4024 notifier_disabled = 0;
1da177e4
LT		 4025 register_reboot_notifier(&gdth_notifier);
4026 }
4027 gdth_polling = FALSE;
4028 return gdth_ctr_vcount;
4029}
4030
8e879041 4031static int gdth_release(struct Scsi_Host *shp)
1da177e4
LT		 4032{
4033 int hanum;
4034 gdth_ha_str *ha;
4035
4036 TRACE2(("gdth_release()\n"));
4037 if (NUMDATA(shp)->busnum == 0) {
4038 hanum = NUMDATA(shp)->hanum;
4039 ha = HADATA(gdth_ctr_tab[hanum]);
4040 if (ha->sdev) {
4041 scsi_free_host_dev(ha->sdev);
4042 ha->sdev = NULL;
4043 }
4044 gdth_flush(hanum);
4045
4046 if (shp->irq) {
4047 free_irq(shp->irq,ha);
4048 }
aed91cb5 4049#ifdef CONFIG_ISA
1da177e4
LT		 4050 if (shp->dma_channel != 0xff) {
4051 free_dma(shp->dma_channel);
4052 }
4053#endif
4054#ifdef INT_COAL
4055 if (ha->coal_stat)
4056 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4057 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
4058#endif
4059 if (ha->pscratch)
4060 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4061 ha->pscratch, ha->scratch_phys);
4062 if (ha->pmsg)
4063 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4064 ha->pmsg, ha->msg_phys);
4065 if (ha->ccb_phys)
4066 pci_unmap_single(ha->pdev,ha->ccb_phys,
4067 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4068 gdth_ctr_released++;
4069 TRACE2(("gdth_release(): HA %d of %d\n",
4070 gdth_ctr_released, gdth_ctr_count));
4071
4072 if (gdth_ctr_released == gdth_ctr_count) {
4073#ifdef GDTH_STATISTICS
4074 del_timer(&gdth_timer);
4075#endif
4076 unregister_chrdev(major,"gdth");
4077 unregister_reboot_notifier(&gdth_notifier);
4078 }
4079 }
4080
4081 scsi_unregister(shp);
4082 return 0;
4083}
4084
4085
4086static const char *gdth_ctr_name(int hanum)
4087{
4088 gdth_ha_str *ha;
4089
4090 TRACE2(("gdth_ctr_name()\n"));
4091
4092 ha = HADATA(gdth_ctr_tab[hanum]);
4093
4094 if (ha->type == GDT_EISA) {
4095 switch (ha->stype) {
4096 case GDT3_ID:
4097 return("GDT3000/3020");
4098 case GDT3A_ID:
4099 return("GDT3000A/3020A/3050A");
4100 case GDT3B_ID:
4101 return("GDT3000B/3010A");
4102 }
4103 } else if (ha->type == GDT_ISA) {
4104 return("GDT2000/2020");
4105 } else if (ha->type == GDT_PCI) {
8e9a8a0d 4106 switch (ha->pdev->device) {
1da177e4
LT		 4107 case PCI_DEVICE_ID_VORTEX_GDT60x0:
4108 return("GDT6000/6020/6050");
4109 case PCI_DEVICE_ID_VORTEX_GDT6000B:
4110 return("GDT6000B/6010");
4111 }
4112 }
4113 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
4114
4115 return("");
4116}
4117
8e879041 4118static const char *gdth_info(struct Scsi_Host *shp)
1da177e4
LT		 4119{
4120 int hanum;
4121 gdth_ha_str *ha;
4122
4123 TRACE2(("gdth_info()\n"));
4124 hanum = NUMDATA(shp)->hanum;
4125 ha = HADATA(gdth_ctr_tab[hanum]);
4126
4127 return ((const char *)ha->binfo.type_string);
4128}
4129
8e879041 4130static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
1da177e4
LT		 4131{
4132 int i, hanum;
4133 gdth_ha_str *ha;
4134 ulong flags;
4135 Scsi_Cmnd *cmnd;
4136 unchar b;
4137
4138 TRACE2(("gdth_eh_bus_reset()\n"));
4139
4140 hanum = NUMDATA(scp->device->host)->hanum;
4141 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
4142 ha = HADATA(gdth_ctr_tab[hanum]);
4143
4144 /* clear command tab */
4145 spin_lock_irqsave(&ha->smp_lock, flags);
4146 for (i = 0; i < GDTH_MAXCMDS; ++i) {
4147 cmnd = ha->cmd_tab[i].cmnd;
4148 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
4149 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4150 }
4151 spin_unlock_irqrestore(&ha->smp_lock, flags);
4152
4153 if (b == ha->virt_bus) {
4154 /* host drives */
4155 for (i = 0; i < MAX_HDRIVES; ++i) {
4156 if (ha->hdr[i].present) {
4157 spin_lock_irqsave(&ha->smp_lock, flags);
4158 gdth_polling = TRUE;
4159 while (gdth_test_busy(hanum))
4160 gdth_delay(0);
4161 if (gdth_internal_cmd(hanum, CACHESERVICE,
4162 GDT_CLUST_RESET, i, 0, 0))
4163 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
4164 gdth_polling = FALSE;
4165 spin_unlock_irqrestore(&ha->smp_lock, flags);
4166 }
4167 }
4168 } else {
4169 /* raw devices */
4170 spin_lock_irqsave(&ha->smp_lock, flags);
4171 for (i = 0; i < MAXID; ++i)
4172 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
4173 gdth_polling = TRUE;
4174 while (gdth_test_busy(hanum))
4175 gdth_delay(0);
4176 gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
4177 BUS_L2P(ha,b), 0, 0);
4178 gdth_polling = FALSE;
cbd5f69b 4179 spin_unlock_irqrestore(&ha->smp_lock, flags);
1da177e4
LT		 4180 }
4181 return SUCCESS;
4182}
4183
8e879041 4184static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
1da177e4
LT		 4185{
4186 unchar b, t;
4187 int hanum;
4188 gdth_ha_str *ha;
4189 struct scsi_device *sd;
4190 unsigned capacity;
4191
1da177e4
LT		 4192 sd = sdev;
4193 capacity = cap;
1da177e4
LT		 4194 hanum = NUMDATA(sd->host)->hanum;
4195 b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
4196 t = sd->id;
4197 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
4198 ha = HADATA(gdth_ctr_tab[hanum]);
4199
4200 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
4201 /* raw device or host drive without mapping information */
4202 TRACE2(("Evaluate mapping\n"));
4203 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
4204 } else {
4205 ip[0] = ha->hdr[t].heads;
4206 ip[1] = ha->hdr[t].secs;
4207 ip[2] = capacity / ip[0] / ip[1];
4208 }
4209
4210 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
4211 ip[0],ip[1],ip[2]));
4212 return 0;
4213}
4214
4215
b8bff2ae
MW		 4216static int gdth_queuecommand(struct scsi_cmnd *scp,
4217 void (*done)(struct scsi_cmnd *))
1da177e4
LT		 4218{
4219 int hanum;
4220 int priority;
4221
4222 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
4223
b8bff2ae 4224 scp->scsi_done = done;
1da177e4
LT		 4225 scp->SCp.have_data_in = 1;
4226 scp->SCp.phase = -1;
4227 scp->SCp.sent_command = -1;
4228 scp->SCp.Status = GDTH_MAP_NONE;
4229 scp->SCp.buffer = (struct scatterlist *)NULL;
4230
4231 hanum = NUMDATA(scp->device->host)->hanum;
4232#ifdef GDTH_STATISTICS
4233 ++act_ios;
4234#endif
4235
4236 priority = DEFAULT_PRI;
687d2bc4 4237 if (IS_GDTH_INTERNAL_CMD(scp))
1da177e4 4238 priority = scp->SCp.this_residual;
cbd5f69b
LA		 4239 else
4240 gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
4241
1da177e4
LT		 4242 gdth_putq( hanum, scp, priority );
4243 gdth_next( hanum );
4244 return 0;
4245}
4246
4247
4248static int gdth_open(struct inode *inode, struct file *filep)
4249{
4250 gdth_ha_str *ha;
4251 int i;
4252
4253 for (i = 0; i < gdth_ctr_count; i++) {
4254 ha = HADATA(gdth_ctr_tab[i]);
4255 if (!ha->sdev)
4256 ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
4257 }
4258
4259 TRACE(("gdth_open()\n"));
4260 return 0;
4261}
4262
4263static int gdth_close(struct inode *inode, struct file *filep)
4264{
4265 TRACE(("gdth_close()\n"));
4266 return 0;
4267}
4268
4269static int ioc_event(void __user *arg)
4270{
4271 gdth_ioctl_event evt;
4272 gdth_ha_str *ha;
4273 ulong flags;
4274
4275 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
4276 evt.ionode >= gdth_ctr_count)
4277 return -EFAULT;
4278 ha = HADATA(gdth_ctr_tab[evt.ionode]);
4279
4280 if (evt.erase == 0xff) {
4281 if (evt.event.event_source == ES_TEST)
4282 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4283 else if (evt.event.event_source == ES_DRIVER)
4284 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
4285 else if (evt.event.event_source == ES_SYNC)
4286 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
4287 else
4288 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
4289 spin_lock_irqsave(&ha->smp_lock, flags);
4290 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
4291 &evt.event.event_data);
4292 spin_unlock_irqrestore(&ha->smp_lock, flags);
4293 } else if (evt.erase == 0xfe) {
4294 gdth_clear_events();
4295 } else if (evt.erase == 0) {
4296 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
4297 } else {
4298 gdth_readapp_event(ha, evt.erase, &evt.event);
4299 }
4300 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
4301 return -EFAULT;
4302 return 0;
4303}
4304
4305static int ioc_lockdrv(void __user *arg)
4306{
4307 gdth_ioctl_lockdrv ldrv;
4308 unchar i, j;
4309 ulong flags;
4310 gdth_ha_str *ha;
4311
4312 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
4313 ldrv.ionode >= gdth_ctr_count)
4314 return -EFAULT;
4315 ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
4316
4317 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
4318 j = ldrv.drives[i];
4319 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
4320 continue;
4321 if (ldrv.lock) {
4322 spin_lock_irqsave(&ha->smp_lock, flags);
4323 ha->hdr[j].lock = 1;
4324 spin_unlock_irqrestore(&ha->smp_lock, flags);
4325 gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
4326 gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
4327 } else {
4328 spin_lock_irqsave(&ha->smp_lock, flags);
4329 ha->hdr[j].lock = 0;
4330 spin_unlock_irqrestore(&ha->smp_lock, flags);
4331 gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
4332 gdth_next(ldrv.ionode);
4333 }
4334 }
4335 return 0;
4336}
4337
4338static int ioc_resetdrv(void __user *arg, char *cmnd)
4339{
4340 gdth_ioctl_reset res;
4341 gdth_cmd_str cmd;
4342 int hanum;
4343 gdth_ha_str *ha;
cbd5f69b 4344 int rval;
1da177e4
LT		 4345
4346 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
4347 res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
4348 return -EFAULT;
4349 hanum = res.ionode;
4350 ha = HADATA(gdth_ctr_tab[hanum]);
4351
4352 if (!ha->hdr[res.number].present)
4353 return 0;
4354 memset(&cmd, 0, sizeof(gdth_cmd_str));
4355 cmd.Service = CACHESERVICE;
4356 cmd.OpCode = GDT_CLUST_RESET;
4357 if (ha->cache_feat & GDT_64BIT)
4358 cmd.u.cache64.DeviceNo = res.number;
4359 else
4360 cmd.u.cache.DeviceNo = res.number;
cbd5f69b
LA		 4361
4362 rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
4363 if (rval < 0)
4364 return rval;
4365 res.status = rval;
1da177e4
LT		 4366
4367 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
4368 return -EFAULT;
4369 return 0;
4370}
4371
4372static int ioc_general(void __user *arg, char *cmnd)
4373{
4374 gdth_ioctl_general gen;
4375 char *buf = NULL;
4376 ulong64 paddr;
4377 int hanum;
cbd5f69b
LA		 4378 gdth_ha_str *ha;
4379 int rval;
1da177e4
LT		 4380
4381 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
4382 gen.ionode >= gdth_ctr_count)
4383 return -EFAULT;
4384 hanum = gen.ionode;
4385 ha = HADATA(gdth_ctr_tab[hanum]);
4386 if (gen.data_len + gen.sense_len != 0) {
4387 if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
4388 FALSE, &paddr)))
4389 return -EFAULT;
4390 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
4391 gen.data_len + gen.sense_len)) {
4392 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
4393 return -EFAULT;
4394 }
4395
4396 if (gen.command.OpCode == GDT_IOCTL) {
4397 gen.command.u.ioctl.p_param = paddr;
4398 } else if (gen.command.Service == CACHESERVICE) {
4399 if (ha->cache_feat & GDT_64BIT) {
4400 /* copy elements from 32-bit IOCTL structure */
4401 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
4402 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
4403 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
4404 /* addresses */
4405 if (ha->cache_feat & SCATTER_GATHER) {
4406 gen.command.u.cache64.DestAddr = (ulong64)-1;
4407 gen.command.u.cache64.sg_canz = 1;
4408 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
4409 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
4410 gen.command.u.cache64.sg_lst[1].sg_len = 0;
4411 } else {
4412 gen.command.u.cache64.DestAddr = paddr;
4413 gen.command.u.cache64.sg_canz = 0;
4414 }
4415 } else {
4416 if (ha->cache_feat & SCATTER_GATHER) {
4417 gen.command.u.cache.DestAddr = 0xffffffff;
4418 gen.command.u.cache.sg_canz = 1;
4419 gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
4420 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
4421 gen.command.u.cache.sg_lst[1].sg_len = 0;
4422 } else {
4423 gen.command.u.cache.DestAddr = paddr;
4424 gen.command.u.cache.sg_canz = 0;
4425 }
4426 }
4427 } else if (gen.command.Service == SCSIRAWSERVICE) {
4428 if (ha->raw_feat & GDT_64BIT) {
4429 /* copy elements from 32-bit IOCTL structure */
4430 char cmd[16];
4431 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
4432 gen.command.u.raw64.bus = gen.command.u.raw.bus;
4433 gen.command.u.raw64.lun = gen.command.u.raw.lun;
4434 gen.command.u.raw64.target = gen.command.u.raw.target;
4435 memcpy(cmd, gen.command.u.raw.cmd, 16);
4436 memcpy(gen.command.u.raw64.cmd, cmd, 16);
4437 gen.command.u.raw64.clen = gen.command.u.raw.clen;
4438 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
4439 gen.command.u.raw64.direction = gen.command.u.raw.direction;
4440 /* addresses */
4441 if (ha->raw_feat & SCATTER_GATHER) {
4442 gen.command.u.raw64.sdata = (ulong64)-1;
4443 gen.command.u.raw64.sg_ranz = 1;
4444 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
4445 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
4446 gen.command.u.raw64.sg_lst[1].sg_len = 0;
4447 } else {
4448 gen.command.u.raw64.sdata = paddr;
4449 gen.command.u.raw64.sg_ranz = 0;
4450 }
4451 gen.command.u.raw64.sense_data = paddr + gen.data_len;
4452 } else {
4453 if (ha->raw_feat & SCATTER_GATHER) {
4454 gen.command.u.raw.sdata = 0xffffffff;
4455 gen.command.u.raw.sg_ranz = 1;
4456 gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
4457 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
4458 gen.command.u.raw.sg_lst[1].sg_len = 0;
4459 } else {
4460 gen.command.u.raw.sdata = paddr;
4461 gen.command.u.raw.sg_ranz = 0;
4462 }
4463 gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
4464 }
4465 } else {
4466 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
4467 return -EFAULT;
4468 }
4469 }
4470
cbd5f69b
LA		 4471 rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
4472 if (rval < 0)
4473 return rval;
4474 gen.status = rval;
1da177e4
LT		 4475
4476 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
4477 gen.data_len + gen.sense_len)) {
4478 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
4479 return -EFAULT;
4480 }
4481 if (copy_to_user(arg, &gen,
4482 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
4483 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
4484 return -EFAULT;
4485 }
4486 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
4487 return 0;
4488}
4489
4490static int ioc_hdrlist(void __user *arg, char *cmnd)
4491{
4492 gdth_ioctl_rescan *rsc;
4493 gdth_cmd_str *cmd;
4494 gdth_ha_str *ha;
4495 unchar i;
4496 int hanum, rc = -ENOMEM;
cbd5f69b
LA		 4497 u32 cluster_type = 0;
4498
1da177e4
LT		 4499 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4500 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4501 if (!rsc || !cmd)
cbd5f69b 4502 goto free_fail;
1da177e4
LT		 4503
4504 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4505 rsc->ionode >= gdth_ctr_count) {
4506 rc = -EFAULT;
cbd5f69b 4507 goto free_fail;
1da177e4
LT		 4508 }
4509 hanum = rsc->ionode;
4510 ha = HADATA(gdth_ctr_tab[hanum]);
4511 memset(cmd, 0, sizeof(gdth_cmd_str));
4512
1da177e4
LT		 4513 for (i = 0; i < MAX_HDRIVES; ++i) {
4514 if (!ha->hdr[i].present) {
4515 rsc->hdr_list[i].bus = 0xff;
4516 continue;
4517 }
4518 rsc->hdr_list[i].bus = ha->virt_bus;
4519 rsc->hdr_list[i].target = i;
4520 rsc->hdr_list[i].lun = 0;
4521 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4522 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
4523 cmd->Service = CACHESERVICE;
4524 cmd->OpCode = GDT_CLUST_INFO;
4525 if (ha->cache_feat & GDT_64BIT)
4526 cmd->u.cache64.DeviceNo = i;
4527 else
4528 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 4529 if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
4530 rsc->hdr_list[i].cluster_type = cluster_type;
1da177e4
LT		 4531 }
4532 }
cbd5f69b 4533
1da177e4
LT		 4534 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4535 rc = -EFAULT;
4536 else
cbd5f69b 4537 rc = 0;
1da177e4
LT		 4538
4539free_fail:
4540 kfree(rsc);
4541 kfree(cmd);
4542 return rc;
4543}
4544
4545static int ioc_rescan(void __user *arg, char *cmnd)
4546{
4547 gdth_ioctl_rescan *rsc;
4548 gdth_cmd_str *cmd;
4549 ushort i, status, hdr_cnt;
4550 ulong32 info;
4551 int hanum, cyls, hds, secs;
4552 int rc = -ENOMEM;
4553 ulong flags;
4554 gdth_ha_str *ha;
1da177e4
LT		 4555
4556 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4557 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4558 if (!cmd || !rsc)
cbd5f69b 4559 goto free_fail;
1da177e4
LT		 4560
4561 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4562 rsc->ionode >= gdth_ctr_count) {
cbd5f69b
LA		 4563 rc = -EFAULT;
4564 goto free_fail;
1da177e4
LT		 4565 }
4566 hanum = rsc->ionode;
4567 ha = HADATA(gdth_ctr_tab[hanum]);
4568 memset(cmd, 0, sizeof(gdth_cmd_str));
4569
1da177e4
LT		 4570 if (rsc->flag == 0) {
4571 /* old method: re-init. cache service */
4572 cmd->Service = CACHESERVICE;
4573 if (ha->cache_feat & GDT_64BIT) {
4574 cmd->OpCode = GDT_X_INIT_HOST;
4575 cmd->u.cache64.DeviceNo = LINUX_OS;
4576 } else {
4577 cmd->OpCode = GDT_INIT;
4578 cmd->u.cache.DeviceNo = LINUX_OS;
4579 }
cbd5f69b
LA		 4580
4581 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
1da177e4
LT		 4582 i = 0;
4583 hdr_cnt = (status == S_OK ? (ushort)info : 0);
4584 } else {
4585 i = rsc->hdr_no;
4586 hdr_cnt = i + 1;
4587 }
4588
4589 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
4590 cmd->Service = CACHESERVICE;
4591 cmd->OpCode = GDT_INFO;
4592 if (ha->cache_feat & GDT_64BIT)
4593 cmd->u.cache64.DeviceNo = i;
4594 else
4595 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 4596
4597 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4598
1da177e4
LT		 4599 spin_lock_irqsave(&ha->smp_lock, flags);
4600 rsc->hdr_list[i].bus = ha->virt_bus;
4601 rsc->hdr_list[i].target = i;
4602 rsc->hdr_list[i].lun = 0;
4603 if (status != S_OK) {
4604 ha->hdr[i].present = FALSE;
4605 } else {
4606 ha->hdr[i].present = TRUE;
4607 ha->hdr[i].size = info;
4608 /* evaluate mapping */
4609 ha->hdr[i].size &= ~SECS32;
4610 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
4611 ha->hdr[i].heads = hds;
4612 ha->hdr[i].secs = secs;
4613 /* round size */
4614 ha->hdr[i].size = cyls * hds * secs;
4615 }
4616 spin_unlock_irqrestore(&ha->smp_lock, flags);
4617 if (status != S_OK)
4618 continue;
4619
4620 /* extended info, if GDT_64BIT, for drives > 2 TB */
4621 /* but we need ha->info2, not yet stored in scp->SCp */
4622
4623 /* devtype, cluster info, R/W attribs */
4624 cmd->Service = CACHESERVICE;
4625 cmd->OpCode = GDT_DEVTYPE;
4626 if (ha->cache_feat & GDT_64BIT)
4627 cmd->u.cache64.DeviceNo = i;
4628 else
4629 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 4630
4631 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4632
1da177e4
LT		 4633 spin_lock_irqsave(&ha->smp_lock, flags);
4634 ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
4635 spin_unlock_irqrestore(&ha->smp_lock, flags);
4636
4637 cmd->Service = CACHESERVICE;
4638 cmd->OpCode = GDT_CLUST_INFO;
4639 if (ha->cache_feat & GDT_64BIT)
4640 cmd->u.cache64.DeviceNo = i;
4641 else
4642 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 4643
4644 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4645
1da177e4
LT		 4646 spin_lock_irqsave(&ha->smp_lock, flags);
4647 ha->hdr[i].cluster_type =
4648 ((status == S_OK && !shared_access) ? (ushort)info : 0);
4649 spin_unlock_irqrestore(&ha->smp_lock, flags);
4650 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4651
4652 cmd->Service = CACHESERVICE;
4653 cmd->OpCode = GDT_RW_ATTRIBS;
4654 if (ha->cache_feat & GDT_64BIT)
4655 cmd->u.cache64.DeviceNo = i;
4656 else
4657 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 4658
4659 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4660
1da177e4
LT		 4661 spin_lock_irqsave(&ha->smp_lock, flags);
4662 ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
4663 spin_unlock_irqrestore(&ha->smp_lock, flags);
4664 }
1da177e4
LT		 4665
4666 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4667 rc = -EFAULT;
4668 else
cbd5f69b 4669 rc = 0;
1da177e4
LT		 4670
4671free_fail:
4672 kfree(rsc);
4673 kfree(cmd);
4674 return rc;
4675}
4676
4677static int gdth_ioctl(struct inode *inode, struct file *filep,
4678 unsigned int cmd, unsigned long arg)
4679{
4680 gdth_ha_str *ha;
4681 Scsi_Cmnd *scp;
4682 ulong flags;
4683 char cmnd[MAX_COMMAND_SIZE];
4684 void __user *argp = (void __user *)arg;
4685
4686 memset(cmnd, 0xff, 12);
4687
4688 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
4689
4690 switch (cmd) {
4691 case GDTIOCTL_CTRCNT:
4692 {
4693 int cnt = gdth_ctr_count;
4694 if (put_user(cnt, (int __user *)argp))
4695 return -EFAULT;
4696 break;
4697 }
4698
4699 case GDTIOCTL_DRVERS:
4700 {
4701 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
4702 if (put_user(ver, (int __user *)argp))
4703 return -EFAULT;
4704 break;
4705 }
4706
4707 case GDTIOCTL_OSVERS:
4708 {
4709 gdth_ioctl_osvers osv;
4710
4711 osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
4712 osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
4713 osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
4714 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
4715 return -EFAULT;
4716 break;
4717 }
4718
4719 case GDTIOCTL_CTRTYPE:
4720 {
4721 gdth_ioctl_ctrtype ctrt;
4722
4723 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
4724 ctrt.ionode >= gdth_ctr_count)
4725 return -EFAULT;
4726 ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
4727 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
4728 ctrt.type = (unchar)((ha->stype>>20) - 0x10);
4729 } else {
4730 if (ha->type != GDT_PCIMPR) {
4731 ctrt.type = (unchar)((ha->stype<<4) + 6);
4732 } else {
4733 ctrt.type =
4734 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
4735 if (ha->stype >= 0x300)
8e9a8a0d 4736 ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
1da177e4
LT		 4737 else
4738 ctrt.ext_type = 0x6000 | ha->stype;
4739 }
8e9a8a0d
JG		 4740 ctrt.device_id = ha->pdev->device;
4741 ctrt.sub_device_id = ha->pdev->subsystem_device;
1da177e4
LT		 4742 }
4743 ctrt.info = ha->brd_phys;
4744 ctrt.oem_id = ha->oem_id;
4745 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
4746 return -EFAULT;
4747 break;
4748 }
4749
4750 case GDTIOCTL_GENERAL:
4751 return ioc_general(argp, cmnd);
4752
4753 case GDTIOCTL_EVENT:
4754 return ioc_event(argp);
4755
4756 case GDTIOCTL_LOCKDRV:
4757 return ioc_lockdrv(argp);
4758
4759 case GDTIOCTL_LOCKCHN:
4760 {
4761 gdth_ioctl_lockchn lchn;
4762 unchar i, j;
4763
4764 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
4765 lchn.ionode >= gdth_ctr_count)
4766 return -EFAULT;
4767 ha = HADATA(gdth_ctr_tab[lchn.ionode]);
4768
4769 i = lchn.channel;
4770 if (i < ha->bus_cnt) {
4771 if (lchn.lock) {
4772 spin_lock_irqsave(&ha->smp_lock, flags);
4773 ha->raw[i].lock = 1;
4774 spin_unlock_irqrestore(&ha->smp_lock, flags);
4775 for (j = 0; j < ha->tid_cnt; ++j) {
4776 gdth_wait_completion(lchn.ionode, i, j);
4777 gdth_stop_timeout(lchn.ionode, i, j);
4778 }
4779 } else {
4780 spin_lock_irqsave(&ha->smp_lock, flags);
4781 ha->raw[i].lock = 0;
4782 spin_unlock_irqrestore(&ha->smp_lock, flags);
4783 for (j = 0; j < ha->tid_cnt; ++j) {
4784 gdth_start_timeout(lchn.ionode, i, j);
4785 gdth_next(lchn.ionode);
4786 }
4787 }
4788 }
4789 break;
4790 }
4791
4792 case GDTIOCTL_RESCAN:
4793 return ioc_rescan(argp, cmnd);
4794
4795 case GDTIOCTL_HDRLIST:
4796 return ioc_hdrlist(argp, cmnd);
4797
4798 case GDTIOCTL_RESET_BUS:
4799 {
4800 gdth_ioctl_reset res;
4801 int hanum, rval;
4802
4803 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
4804 res.ionode >= gdth_ctr_count)
4805 return -EFAULT;
4806 hanum = res.ionode;
4807 ha = HADATA(gdth_ctr_tab[hanum]);
4808
bbfbbbc1 4809 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
1da177e4
LT		 4810 if (!scp)
4811 return -ENOMEM;
cbd5f69b 4812 scp->device = ha->sdev;
1da177e4
LT		 4813 scp->cmd_len = 12;
4814 scp->use_sg = 0;
4815 scp->device->channel = virt_ctr ? 0 : res.number;
4816 rval = gdth_eh_bus_reset(scp);
4817 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
cbd5f69b 4818 kfree(scp);
8d7a5da4 4819
1da177e4
LT		 4820 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
4821 return -EFAULT;
4822 break;
4823 }
4824
4825 case GDTIOCTL_RESET_DRV:
4826 return ioc_resetdrv(argp, cmnd);
4827
4828 default:
4829 break;
4830 }
4831 return 0;
4832}
4833
4834
4835/* flush routine */
4836static void gdth_flush(int hanum)
4837{
4838 int i;
4839 gdth_ha_str *ha;
4840 gdth_cmd_str gdtcmd;
1da177e4
LT		 4841 char cmnd[MAX_COMMAND_SIZE];
4842 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
4843
4844 TRACE2(("gdth_flush() hanum %d\n",hanum));
4845 ha = HADATA(gdth_ctr_tab[hanum]);
4846
1da177e4
LT		 4847 for (i = 0; i < MAX_HDRIVES; ++i) {
4848 if (ha->hdr[i].present) {
4849 gdtcmd.BoardNode = LOCALBOARD;
4850 gdtcmd.Service = CACHESERVICE;
4851 gdtcmd.OpCode = GDT_FLUSH;
4852 if (ha->cache_feat & GDT_64BIT) {
4853 gdtcmd.u.cache64.DeviceNo = i;
4854 gdtcmd.u.cache64.BlockNo = 1;
4855 gdtcmd.u.cache64.sg_canz = 0;
4856 } else {
4857 gdtcmd.u.cache.DeviceNo = i;
4858 gdtcmd.u.cache.BlockNo = 1;
4859 gdtcmd.u.cache.sg_canz = 0;
4860 }
4861 TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
cbd5f69b
LA		 4862
4863 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
1da177e4
LT		 4864 }
4865 }
1da177e4
LT		 4866}
4867
4868/* shutdown routine */
4869static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
4870{
4871 int hanum;
4872#ifndef __alpha__
4873 gdth_cmd_str gdtcmd;
1da177e4
LT		 4874 char cmnd[MAX_COMMAND_SIZE];
4875#endif
4876
e041c683 4877 if (notifier_disabled)
cbd5f69b 4878 return NOTIFY_OK;
e041c683 4879
1da177e4
LT		 4880 TRACE2(("gdth_halt() event %d\n",(int)event));
4881 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
4882 return NOTIFY_DONE;
4883
e041c683 4884 notifier_disabled = 1;
1da177e4
LT		 4885 printk("GDT-HA: Flushing all host drives .. ");
4886 for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
4887 gdth_flush(hanum);
4888
4889#ifndef __alpha__
4890 /* controller reset */
4891 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
4892 gdtcmd.BoardNode = LOCALBOARD;
4893 gdtcmd.Service = CACHESERVICE;
4894 gdtcmd.OpCode = GDT_RESET;
4895 TRACE2(("gdth_halt(): reset controller %d\n", hanum));
cbd5f69b 4896 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
1da177e4
LT		 4897#endif
4898 }
4899 printk("Done.\n");
4900
4901#ifdef GDTH_STATISTICS
4902 del_timer(&gdth_timer);
4903#endif
1da177e4
LT		 4904 return NOTIFY_OK;
4905}
4906
cbd5f69b
LA		 4907/* configure lun */
4908static int gdth_slave_configure(struct scsi_device *sdev)
4909{
4910 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
4911 sdev->skip_ms_page_3f = 1;
4912 sdev->skip_ms_page_8 = 1;
4913 return 0;
4914}
cbd5f69b 4915
d0be4a7d 4916static struct scsi_host_template driver_template = {
1da177e4
LT		 4917 .proc_name = "gdth",
4918 .proc_info = gdth_proc_info,
4919 .name = "GDT SCSI Disk Array Controller",
4920 .detect = gdth_detect,
4921 .release = gdth_release,
4922 .info = gdth_info,
4923 .queuecommand = gdth_queuecommand,
1da177e4 4924 .eh_bus_reset_handler = gdth_eh_bus_reset,
1da177e4
LT		 4925 .bios_param = gdth_bios_param,
4926 .can_queue = GDTH_MAXCMDS,
cbd5f69b 4927 .slave_configure = gdth_slave_configure,
1da177e4
LT		 4928 .this_id = -1,
4929 .sg_tablesize = GDTH_MAXSG,
4930 .cmd_per_lun = GDTH_MAXC_P_L,
4931 .unchecked_isa_dma = 1,
4932 .use_clustering = ENABLE_CLUSTERING,
1da177e4
LT		 4933};
4934
aed91cb5
CH		 4935#ifdef CONFIG_ISA
4936static int gdth_isa_probe_one(struct scsi_host_template *shtp, ulong32 isa_bios)
4937{
4938 struct Scsi_Host *shp;
4939 gdth_ha_str *ha;
4940 dma_addr_t scratch_dma_handle = 0;
4941 int error, hanum, i;
4942 u8 b;
4943
4944 if (!gdth_search_isa(isa_bios))
4945 return -ENXIO;
4946
4947 shp = scsi_register(shtp, sizeof(gdth_ext_str));
4948 if (!shp)
4949 return -ENOMEM;
4950 ha = HADATA(shp);
4951
4952 error = -ENODEV;
4953 if (!gdth_init_isa(isa_bios,ha))
4954 goto out_host_put;
4955
4956 /* controller found and initialized */
4957 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4958 isa_bios, ha->irq, ha->drq);
4959
4960 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
4961 if (error) {
4962 printk("GDT-ISA: Unable to allocate IRQ\n");
4963 goto out_host_put;
4964 }
4965
4966 error = request_dma(ha->drq, "gdth");
4967 if (error) {
4968 printk("GDT-ISA: Unable to allocate DMA channel\n");
4969 goto out_free_irq;
4970 }
4971
4972 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4973 enable_dma(ha->drq);
4974 shp->unchecked_isa_dma = 1;
4975 shp->irq = ha->irq;
4976 shp->dma_channel = ha->drq;
4977 hanum = gdth_ctr_count;
4978 gdth_ctr_tab[gdth_ctr_count++] = shp;
4979 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4980
4981 NUMDATA(shp)->hanum = (ushort)hanum;
4982 NUMDATA(shp)->busnum= 0;
4983
4984 ha->pccb = CMDDATA(shp);
4985 ha->ccb_phys = 0L;
4986 ha->pdev = NULL;
4987
4988 error = -ENOMEM;
4989
4990 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4991 &scratch_dma_handle);
4992 if (!ha->pscratch)
4993 goto out_dec_counters;
4994 ha->scratch_phys = scratch_dma_handle;
4995
4996 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4997 &scratch_dma_handle);
4998 if (!ha->pmsg)
4999 goto out_free_pscratch;
5000 ha->msg_phys = scratch_dma_handle;
5001
5002#ifdef INT_COAL
5003 ha->coal_stat = pci_alloc_consistent(ha->pdev,
5004 sizeof(gdth_coal_status) * MAXOFFSETS,
5005 &scratch_dma_handle);
5006 if (!ha->coal_stat)
5007 goto out_free_pmsg;
5008 ha->coal_stat_phys = scratch_dma_handle;
5009#endif
5010
5011 ha->scratch_busy = FALSE;
5012 ha->req_first = NULL;
5013 ha->tid_cnt = MAX_HDRIVES;
5014 if (max_ids > 0 && max_ids < ha->tid_cnt)
5015 ha->tid_cnt = max_ids;
5016 for (i = 0; i < GDTH_MAXCMDS; ++i)
5017 ha->cmd_tab[i].cmnd = UNUSED_CMND;
5018 ha->scan_mode = rescan ? 0x10 : 0;
5019
5020 error = -ENODEV;
5021 if (!gdth_search_drives(hanum)) {
5022 printk("GDT-ISA: Error during device scan\n");
5023 goto out_free_coal_stat;
5024 }
5025
5026 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
5027 hdr_channel = ha->bus_cnt;
5028 ha->virt_bus = hdr_channel;
5029
5030 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
5031 shp->max_cmd_len = 16;
5032
5033 shp->max_id = ha->tid_cnt;
5034 shp->max_lun = MAXLUN;
5035 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
5036 if (virt_ctr) {
5037 virt_ctr = 1;
5038 /* register addit. SCSI channels as virtual controllers */
5039 for (b = 1; b < ha->bus_cnt + 1; ++b) {
5040 shp = scsi_register(shtp,sizeof(gdth_num_str));
5041 shp->unchecked_isa_dma = 1;
5042 shp->irq = ha->irq;
5043 shp->dma_channel = ha->drq;
5044 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
5045 NUMDATA(shp)->hanum = (ushort)hanum;
5046 NUMDATA(shp)->busnum = b;
5047 }
5048 }
5049
5050 spin_lock_init(&ha->smp_lock);
5051 gdth_enable_int(hanum);
5052
5053 return 0;
5054
5055 out_free_coal_stat:
5056#ifdef INT_COAL
5057 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5058 ha->coal_stat, ha->coal_stat_phys);
5059 out_free_pmsg:
5060#endif
5061 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5062 ha->pmsg, ha->msg_phys);
5063 out_free_pscratch:
5064 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5065 ha->pscratch, ha->scratch_phys);
5066 out_dec_counters:
5067 gdth_ctr_count--;
5068 gdth_ctr_vcount--;
5069 out_free_irq:
5070 free_irq(ha->irq, ha);
5071 out_host_put:
5072 scsi_unregister(shp);
5073 return error;
5074}
5075#endif /* CONFIG_ISA */
5076
706a5d45
CH		 5077#ifdef CONFIG_EISA
5078static int gdth_eisa_probe_one(struct scsi_host_template *shtp,
5079 ushort eisa_slot)
5080{
5081 struct Scsi_Host *shp;
5082 gdth_ha_str *ha;
5083 dma_addr_t scratch_dma_handle = 0;
5084 int error, hanum, i;
5085 u8 b;
5086
5087 if (!gdth_search_eisa(eisa_slot))
5088 return -ENXIO;
5089
5090 shp = scsi_register(shtp,sizeof(gdth_ext_str));
5091 if (!shp)
5092 return -ENOMEM;
5093 ha = HADATA(shp);
5094
5095 error = -ENODEV;
5096 if (!gdth_init_eisa(eisa_slot,ha))
5097 goto out_host_put;
5098
5099 /* controller found and initialized */
5100 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
5101 eisa_slot >> 12, ha->irq);
5102
5103 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
5104 if (error) {
5105 printk("GDT-EISA: Unable to allocate IRQ\n");
5106 goto out_host_put;
5107 }
5108
5109 shp->unchecked_isa_dma = 0;
5110 shp->irq = ha->irq;
5111 shp->dma_channel = 0xff;
5112 hanum = gdth_ctr_count;
5113 gdth_ctr_tab[gdth_ctr_count++] = shp;
5114 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
5115
5116 NUMDATA(shp)->hanum = (ushort)hanum;
5117 NUMDATA(shp)->busnum= 0;
5118 TRACE2(("EISA detect Bus 0: hanum %d\n",
5119 NUMDATA(shp)->hanum));
5120
5121 ha->pccb = CMDDATA(shp);
5122 ha->ccb_phys = 0L;
5123
5124 error = -ENOMEM;
5125
5126 ha->pdev = NULL;
5127 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
5128 &scratch_dma_handle);
5129 if (!ha->pscratch)
5130 goto out_free_irq;
5131 ha->scratch_phys = scratch_dma_handle;
5132
5133 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
5134 &scratch_dma_handle);
5135 if (!ha->pmsg)
5136 goto out_free_pscratch;
5137 ha->msg_phys = scratch_dma_handle;
5138
5139#ifdef INT_COAL
5140 ha->coal_stat = pci_alloc_consistent(ha->pdev,
5141 sizeof(gdth_coal_status) * MAXOFFSETS,
5142 &scratch_dma_handle);
5143 if (!ha->coal_stat)
5144 goto out_free_pmsg;
5145 ha->coal_stat_phys = scratch_dma_handle;
5146#endif
5147
5148 ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
5149 sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
5150 if (!ha->ccb_phys)
5151 goto out_free_coal_stat;
5152
5153 ha->scratch_busy = FALSE;
5154 ha->req_first = NULL;
5155 ha->tid_cnt = MAX_HDRIVES;
5156 if (max_ids > 0 && max_ids < ha->tid_cnt)
5157 ha->tid_cnt = max_ids;
5158 for (i = 0; i < GDTH_MAXCMDS; ++i)
5159 ha->cmd_tab[i].cmnd = UNUSED_CMND;
5160 ha->scan_mode = rescan ? 0x10 : 0;
5161
5162 if (!gdth_search_drives(hanum)) {
5163 printk("GDT-EISA: Error during device scan\n");
5164 error = -ENODEV;
5165 goto out_free_ccb_phys;
5166 }
5167
5168 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
5169 hdr_channel = ha->bus_cnt;
5170 ha->virt_bus = hdr_channel;
5171
5172 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
5173 shp->max_cmd_len = 16;
5174
5175 shp->max_id = ha->tid_cnt;
5176 shp->max_lun = MAXLUN;
5177 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
5178 if (virt_ctr) {
5179 virt_ctr = 1;
5180 /* register addit. SCSI channels as virtual controllers */
5181 for (b = 1; b < ha->bus_cnt + 1; ++b) {
5182 shp = scsi_register(shtp,sizeof(gdth_num_str));
5183 shp->unchecked_isa_dma = 0;
5184 shp->irq = ha->irq;
5185 shp->dma_channel = 0xff;
5186 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
5187 NUMDATA(shp)->hanum = (ushort)hanum;
5188 NUMDATA(shp)->busnum = b;
5189 }
5190 }
5191
5192 spin_lock_init(&ha->smp_lock);
5193 gdth_enable_int(hanum);
5194 return 0;
5195
5196 out_free_ccb_phys:
5197 pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
5198 PCI_DMA_BIDIRECTIONAL);
5199 out_free_coal_stat:
5200#ifdef INT_COAL
5201 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5202 ha->coal_stat, ha->coal_stat_phys);
5203 out_free_pmsg:
5204#endif
5205 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5206 ha->pmsg, ha->msg_phys);
5207 out_free_pscratch:
5208 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5209 ha->pscratch, ha->scratch_phys);
5210 out_free_irq:
5211 free_irq(ha->irq, ha);
5212 gdth_ctr_count--;
5213 gdth_ctr_vcount--;
5214 out_host_put:
5215 scsi_unregister(shp);
5216 return error;
5217}
5218#endif /* CONFIG_EISA */
aed91cb5 5219
8514ef27
CH		 5220#ifdef CONFIG_PCI
5221static int gdth_pci_probe_one(struct scsi_host_template *shtp,
5222 gdth_pci_str *pcistr, int ctr)
5223{
5224 struct Scsi_Host *shp;
5225 gdth_ha_str *ha;
5226 dma_addr_t scratch_dma_handle = 0;
5227 int error, hanum, i;
5228 u8 b;
5229
5230 shp = scsi_register(shtp,sizeof(gdth_ext_str));
5231 if (!shp)
5232 return -ENOMEM;
5233 ha = HADATA(shp);
5234
5235 error = -ENODEV;
5236 if (!gdth_init_pci(&pcistr[ctr],ha))
5237 goto out_host_put;
5238
5239 /* controller found and initialized */
5240 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
5241 pcistr[ctr].pdev->bus->number,
5242 PCI_SLOT(pcistr[ctr].pdev->devfn),
5243 ha->irq);
5244
5245 error = request_irq(ha->irq, gdth_interrupt,
5246 IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
5247 if (error) {
5248 printk("GDT-PCI: Unable to allocate IRQ\n");
5249 goto out_host_put;
5250 }
5251
5252 shp->unchecked_isa_dma = 0;
5253 shp->irq = ha->irq;
5254 shp->dma_channel = 0xff;
5255 hanum = gdth_ctr_count;
5256 gdth_ctr_tab[gdth_ctr_count++] = shp;
5257 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
5258
5259 NUMDATA(shp)->hanum = (ushort)hanum;
5260 NUMDATA(shp)->busnum= 0;
5261
5262 ha->pccb = CMDDATA(shp);
5263 ha->ccb_phys = 0L;
5264
5265 error = -ENOMEM;
5266
5267 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
5268 &scratch_dma_handle);
5269 if (!ha->pscratch)
5270 goto out_free_irq;
5271 ha->scratch_phys = scratch_dma_handle;
5272
5273 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
5274 &scratch_dma_handle);
5275 if (!ha->pmsg)
5276 goto out_free_pscratch;
5277 ha->msg_phys = scratch_dma_handle;
5278
5279#ifdef INT_COAL
5280 ha->coal_stat = pci_alloc_consistent(ha->pdev,
5281 sizeof(gdth_coal_status) * MAXOFFSETS,
5282 &scratch_dma_handle);
5283 if (!ha->coal_stat)
5284 goto out_free_pmsg;
5285 ha->coal_stat_phys = scratch_dma_handle;
5286#endif
5287
5288 ha->scratch_busy = FALSE;
5289 ha->req_first = NULL;
5290 ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
5291 if (max_ids > 0 && max_ids < ha->tid_cnt)
5292 ha->tid_cnt = max_ids;
5293 for (i = 0; i < GDTH_MAXCMDS; ++i)
5294 ha->cmd_tab[i].cmnd = UNUSED_CMND;
5295 ha->scan_mode = rescan ? 0x10 : 0;
5296
5297 error = -ENODEV;
5298 if (!gdth_search_drives(hanum)) {
5299 printk("GDT-PCI %d: Error during device scan\n", hanum);
5300 goto out_free_coal_stat;
5301 }
5302
5303 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
5304 hdr_channel = ha->bus_cnt;
5305 ha->virt_bus = hdr_channel;
5306
5307 /* 64-bit DMA only supported from FW >= x.43 */
5308 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
5309 !ha->dma64_support) {
5310 if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
5311 printk(KERN_WARNING "GDT-PCI %d: "
5312 "Unable to set 32-bit DMA\n", hanum);
5313 goto out_free_coal_stat;
5314 }
5315 } else {
5316 shp->max_cmd_len = 16;
5317 if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
5318 printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
5319 } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
5320 printk(KERN_WARNING "GDT-PCI %d: "
5321 "Unable to set 64/32-bit DMA\n", hanum);
5322 goto out_free_coal_stat;
5323 }
5324 }
5325
5326 shp->max_id = ha->tid_cnt;
5327 shp->max_lun = MAXLUN;
5328 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
5329 if (virt_ctr) {
5330 virt_ctr = 1;
5331 /* register addit. SCSI channels as virtual controllers */
5332 for (b = 1; b < ha->bus_cnt + 1; ++b) {
5333 shp = scsi_register(shtp,sizeof(gdth_num_str));
5334 shp->unchecked_isa_dma = 0;
5335 shp->irq = ha->irq;
5336 shp->dma_channel = 0xff;
5337 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
5338 NUMDATA(shp)->hanum = (ushort)hanum;
5339 NUMDATA(shp)->busnum = b;
5340 }
5341 }
5342
5343 spin_lock_init(&ha->smp_lock);
5344 gdth_enable_int(hanum);
5345 return 0;
5346
5347 out_free_coal_stat:
5348#ifdef INT_COAL
5349 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5350 ha->coal_stat, ha->coal_stat_phys);
5351 out_free_pmsg:
5352#endif
5353 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5354 ha->pmsg, ha->msg_phys);
5355 out_free_pscratch:
5356 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5357 ha->pscratch, ha->scratch_phys);
5358 out_free_irq:
5359 free_irq(ha->irq, ha);
5360 gdth_ctr_count--;
5361 gdth_ctr_vcount--;
5362 out_host_put:
5363 scsi_unregister(shp);
5364 return error;
5365}
5366#endif /* CONFIG_PCI */
5367
1da177e4
LT		 5368#include "scsi_module.c"
5369#ifndef MODULE
5370__setup("gdth=", option_setup);
5371#endif
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