]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | #include <linux/types.h> |
1da177e4 LT |
2 | #include <linux/init.h> |
3 | #include <linux/interrupt.h> | |
c1d288a5 GU |
4 | #include <linux/mm.h> |
5 | #include <linux/slab.h> | |
6 | #include <linux/spinlock.h> | |
7 | #include <linux/zorro.h> | |
1da177e4 | 8 | |
1da177e4 LT |
9 | #include <asm/page.h> |
10 | #include <asm/pgtable.h> | |
11 | #include <asm/amigaints.h> | |
12 | #include <asm/amigahw.h> | |
1da177e4 LT |
13 | |
14 | #include "scsi.h" | |
1da177e4 LT |
15 | #include "wd33c93.h" |
16 | #include "gvp11.h" | |
17 | ||
1da177e4 | 18 | |
11ca46ea GU |
19 | #define CHECK_WD33C93 |
20 | ||
cf2ed279 GU |
21 | struct gvp11_hostdata { |
22 | struct WD33C93_hostdata wh; | |
23 | struct gvp11_scsiregs *regs; | |
24 | }; | |
25 | ||
6869b15e | 26 | static irqreturn_t gvp11_intr(int irq, void *data) |
1da177e4 | 27 | { |
6869b15e | 28 | struct Scsi_Host *instance = data; |
cf2ed279 GU |
29 | struct gvp11_hostdata *hdata = shost_priv(instance); |
30 | unsigned int status = hdata->regs->CNTR; | |
bb17b787 | 31 | unsigned long flags; |
bb17b787 | 32 | |
bb17b787 GU |
33 | if (!(status & GVP11_DMAC_INT_PENDING)) |
34 | return IRQ_NONE; | |
35 | ||
36 | spin_lock_irqsave(instance->host_lock, flags); | |
37 | wd33c93_intr(instance); | |
38 | spin_unlock_irqrestore(instance->host_lock, flags); | |
39 | return IRQ_HANDLED; | |
1da177e4 LT |
40 | } |
41 | ||
42 | static int gvp11_xfer_mask = 0; | |
43 | ||
bb17b787 | 44 | void gvp11_setup(char *str, int *ints) |
1da177e4 | 45 | { |
bb17b787 | 46 | gvp11_xfer_mask = ints[1]; |
1da177e4 LT |
47 | } |
48 | ||
65396410 | 49 | static int dma_setup(struct scsi_cmnd *cmd, int dir_in) |
1da177e4 | 50 | { |
52c3d8a6 | 51 | struct Scsi_Host *instance = cmd->device->host; |
cf2ed279 GU |
52 | struct gvp11_hostdata *hdata = shost_priv(instance); |
53 | struct WD33C93_hostdata *wh = &hdata->wh; | |
54 | struct gvp11_scsiregs *regs = hdata->regs; | |
bb17b787 GU |
55 | unsigned short cntr = GVP11_DMAC_INT_ENABLE; |
56 | unsigned long addr = virt_to_bus(cmd->SCp.ptr); | |
57 | int bank_mask; | |
58 | static int scsi_alloc_out_of_range = 0; | |
1da177e4 | 59 | |
bb17b787 | 60 | /* use bounce buffer if the physical address is bad */ |
cf2ed279 GU |
61 | if (addr & wh->dma_xfer_mask) { |
62 | wh->dma_bounce_len = (cmd->SCp.this_residual + 511) & ~0x1ff; | |
bb17b787 GU |
63 | |
64 | if (!scsi_alloc_out_of_range) { | |
cf2ed279 GU |
65 | wh->dma_bounce_buffer = |
66 | kmalloc(wh->dma_bounce_len, GFP_KERNEL); | |
67 | wh->dma_buffer_pool = BUF_SCSI_ALLOCED; | |
bb17b787 | 68 | } |
1da177e4 | 69 | |
bb17b787 | 70 | if (scsi_alloc_out_of_range || |
cf2ed279 GU |
71 | !wh->dma_bounce_buffer) { |
72 | wh->dma_bounce_buffer = | |
73 | amiga_chip_alloc(wh->dma_bounce_len, | |
bb17b787 | 74 | "GVP II SCSI Bounce Buffer"); |
1da177e4 | 75 | |
cf2ed279 GU |
76 | if (!wh->dma_bounce_buffer) { |
77 | wh->dma_bounce_len = 0; | |
bb17b787 GU |
78 | return 1; |
79 | } | |
1da177e4 | 80 | |
cf2ed279 | 81 | wh->dma_buffer_pool = BUF_CHIP_ALLOCED; |
bb17b787 | 82 | } |
1da177e4 | 83 | |
bb17b787 | 84 | /* check if the address of the bounce buffer is OK */ |
cf2ed279 | 85 | addr = virt_to_bus(wh->dma_bounce_buffer); |
bb17b787 | 86 | |
cf2ed279 | 87 | if (addr & wh->dma_xfer_mask) { |
bb17b787 | 88 | /* fall back to Chip RAM if address out of range */ |
cf2ed279 GU |
89 | if (wh->dma_buffer_pool == BUF_SCSI_ALLOCED) { |
90 | kfree(wh->dma_bounce_buffer); | |
bb17b787 GU |
91 | scsi_alloc_out_of_range = 1; |
92 | } else { | |
cf2ed279 | 93 | amiga_chip_free(wh->dma_bounce_buffer); |
bb17b787 GU |
94 | } |
95 | ||
cf2ed279 GU |
96 | wh->dma_bounce_buffer = |
97 | amiga_chip_alloc(wh->dma_bounce_len, | |
bb17b787 GU |
98 | "GVP II SCSI Bounce Buffer"); |
99 | ||
cf2ed279 GU |
100 | if (!wh->dma_bounce_buffer) { |
101 | wh->dma_bounce_len = 0; | |
bb17b787 GU |
102 | return 1; |
103 | } | |
104 | ||
cf2ed279 GU |
105 | addr = virt_to_bus(wh->dma_bounce_buffer); |
106 | wh->dma_buffer_pool = BUF_CHIP_ALLOCED; | |
bb17b787 GU |
107 | } |
108 | ||
109 | if (!dir_in) { | |
110 | /* copy to bounce buffer for a write */ | |
cf2ed279 | 111 | memcpy(wh->dma_bounce_buffer, cmd->SCp.ptr, |
52c3d8a6 | 112 | cmd->SCp.this_residual); |
bb17b787 | 113 | } |
1da177e4 | 114 | } |
1da177e4 | 115 | |
bb17b787 GU |
116 | /* setup dma direction */ |
117 | if (!dir_in) | |
118 | cntr |= GVP11_DMAC_DIR_WRITE; | |
1da177e4 | 119 | |
cf2ed279 | 120 | wh->dma_dir = dir_in; |
6869b15e | 121 | regs->CNTR = cntr; |
1da177e4 | 122 | |
bb17b787 | 123 | /* setup DMA *physical* address */ |
6869b15e | 124 | regs->ACR = addr; |
1da177e4 | 125 | |
bb17b787 GU |
126 | if (dir_in) { |
127 | /* invalidate any cache */ | |
128 | cache_clear(addr, cmd->SCp.this_residual); | |
129 | } else { | |
130 | /* push any dirty cache */ | |
131 | cache_push(addr, cmd->SCp.this_residual); | |
132 | } | |
1da177e4 | 133 | |
cf2ed279 | 134 | bank_mask = (~wh->dma_xfer_mask >> 18) & 0x01c0; |
52c3d8a6 | 135 | if (bank_mask) |
6869b15e | 136 | regs->BANK = bank_mask & (addr >> 18); |
1da177e4 | 137 | |
bb17b787 | 138 | /* start DMA */ |
6869b15e | 139 | regs->ST_DMA = 1; |
1da177e4 | 140 | |
bb17b787 GU |
141 | /* return success */ |
142 | return 0; | |
1da177e4 LT |
143 | } |
144 | ||
65396410 HK |
145 | static void dma_stop(struct Scsi_Host *instance, struct scsi_cmnd *SCpnt, |
146 | int status) | |
1da177e4 | 147 | { |
cf2ed279 GU |
148 | struct gvp11_hostdata *hdata = shost_priv(instance); |
149 | struct WD33C93_hostdata *wh = &hdata->wh; | |
150 | struct gvp11_scsiregs *regs = hdata->regs; | |
52c3d8a6 | 151 | |
bb17b787 | 152 | /* stop DMA */ |
6869b15e | 153 | regs->SP_DMA = 1; |
bb17b787 | 154 | /* remove write bit from CONTROL bits */ |
6869b15e | 155 | regs->CNTR = GVP11_DMAC_INT_ENABLE; |
bb17b787 GU |
156 | |
157 | /* copy from a bounce buffer, if necessary */ | |
cf2ed279 GU |
158 | if (status && wh->dma_bounce_buffer) { |
159 | if (wh->dma_dir && SCpnt) | |
160 | memcpy(SCpnt->SCp.ptr, wh->dma_bounce_buffer, | |
bb17b787 GU |
161 | SCpnt->SCp.this_residual); |
162 | ||
cf2ed279 GU |
163 | if (wh->dma_buffer_pool == BUF_SCSI_ALLOCED) |
164 | kfree(wh->dma_bounce_buffer); | |
bb17b787 | 165 | else |
cf2ed279 | 166 | amiga_chip_free(wh->dma_bounce_buffer); |
bb17b787 | 167 | |
cf2ed279 GU |
168 | wh->dma_bounce_buffer = NULL; |
169 | wh->dma_bounce_len = 0; | |
bb17b787 | 170 | } |
1da177e4 LT |
171 | } |
172 | ||
c1d288a5 GU |
173 | static int gvp11_bus_reset(struct scsi_cmnd *cmd) |
174 | { | |
175 | struct Scsi_Host *instance = cmd->device->host; | |
176 | ||
177 | /* FIXME perform bus-specific reset */ | |
178 | ||
179 | /* FIXME 2: shouldn't we no-op this function (return | |
180 | FAILED), and fall back to host reset function, | |
181 | wd33c93_host_reset ? */ | |
182 | ||
183 | spin_lock_irq(instance->host_lock); | |
184 | wd33c93_host_reset(cmd); | |
185 | spin_unlock_irq(instance->host_lock); | |
186 | ||
187 | return SUCCESS; | |
188 | } | |
189 | ||
190 | static struct scsi_host_template gvp11_scsi_template = { | |
191 | .module = THIS_MODULE, | |
192 | .name = "GVP Series II SCSI", | |
193 | .proc_info = wd33c93_proc_info, | |
194 | .proc_name = "GVP11", | |
195 | .queuecommand = wd33c93_queuecommand, | |
196 | .eh_abort_handler = wd33c93_abort, | |
197 | .eh_bus_reset_handler = gvp11_bus_reset, | |
198 | .eh_host_reset_handler = wd33c93_host_reset, | |
199 | .can_queue = CAN_QUEUE, | |
200 | .this_id = 7, | |
201 | .sg_tablesize = SG_ALL, | |
202 | .cmd_per_lun = CMD_PER_LUN, | |
203 | .use_clustering = DISABLE_CLUSTERING | |
204 | }; | |
205 | ||
206 | static int __devinit check_wd33c93(struct gvp11_scsiregs *regs) | |
11ca46ea GU |
207 | { |
208 | #ifdef CHECK_WD33C93 | |
209 | volatile unsigned char *sasr_3393, *scmd_3393; | |
210 | unsigned char save_sasr; | |
211 | unsigned char q, qq; | |
212 | ||
213 | /* | |
214 | * These darn GVP boards are a problem - it can be tough to tell | |
215 | * whether or not they include a SCSI controller. This is the | |
216 | * ultimate Yet-Another-GVP-Detection-Hack in that it actually | |
217 | * probes for a WD33c93 chip: If we find one, it's extremely | |
218 | * likely that this card supports SCSI, regardless of Product_ | |
219 | * Code, Board_Size, etc. | |
220 | */ | |
221 | ||
222 | /* Get pointers to the presumed register locations and save contents */ | |
223 | ||
224 | sasr_3393 = ®s->SASR; | |
225 | scmd_3393 = ®s->SCMD; | |
226 | save_sasr = *sasr_3393; | |
227 | ||
228 | /* First test the AuxStatus Reg */ | |
229 | ||
230 | q = *sasr_3393; /* read it */ | |
231 | if (q & 0x08) /* bit 3 should always be clear */ | |
232 | return -ENODEV; | |
233 | *sasr_3393 = WD_AUXILIARY_STATUS; /* setup indirect address */ | |
234 | if (*sasr_3393 == WD_AUXILIARY_STATUS) { /* shouldn't retain the write */ | |
235 | *sasr_3393 = save_sasr; /* Oops - restore this byte */ | |
236 | return -ENODEV; | |
237 | } | |
238 | if (*sasr_3393 != q) { /* should still read the same */ | |
239 | *sasr_3393 = save_sasr; /* Oops - restore this byte */ | |
240 | return -ENODEV; | |
241 | } | |
242 | if (*scmd_3393 != q) /* and so should the image at 0x1f */ | |
243 | return -ENODEV; | |
244 | ||
245 | /* | |
246 | * Ok, we probably have a wd33c93, but let's check a few other places | |
247 | * for good measure. Make sure that this works for both 'A and 'B | |
248 | * chip versions. | |
249 | */ | |
250 | ||
251 | *sasr_3393 = WD_SCSI_STATUS; | |
252 | q = *scmd_3393; | |
253 | *sasr_3393 = WD_SCSI_STATUS; | |
254 | *scmd_3393 = ~q; | |
255 | *sasr_3393 = WD_SCSI_STATUS; | |
256 | qq = *scmd_3393; | |
257 | *sasr_3393 = WD_SCSI_STATUS; | |
258 | *scmd_3393 = q; | |
259 | if (qq != q) /* should be read only */ | |
260 | return -ENODEV; | |
261 | *sasr_3393 = 0x1e; /* this register is unimplemented */ | |
262 | q = *scmd_3393; | |
263 | *sasr_3393 = 0x1e; | |
264 | *scmd_3393 = ~q; | |
265 | *sasr_3393 = 0x1e; | |
266 | qq = *scmd_3393; | |
267 | *sasr_3393 = 0x1e; | |
268 | *scmd_3393 = q; | |
269 | if (qq != q || qq != 0xff) /* should be read only, all 1's */ | |
270 | return -ENODEV; | |
271 | *sasr_3393 = WD_TIMEOUT_PERIOD; | |
272 | q = *scmd_3393; | |
273 | *sasr_3393 = WD_TIMEOUT_PERIOD; | |
274 | *scmd_3393 = ~q; | |
275 | *sasr_3393 = WD_TIMEOUT_PERIOD; | |
276 | qq = *scmd_3393; | |
277 | *sasr_3393 = WD_TIMEOUT_PERIOD; | |
278 | *scmd_3393 = q; | |
279 | if (qq != (~q & 0xff)) /* should be read/write */ | |
280 | return -ENODEV; | |
281 | #endif /* CHECK_WD33C93 */ | |
282 | ||
283 | return 0; | |
284 | } | |
1da177e4 | 285 | |
c1d288a5 GU |
286 | static int __devinit gvp11_probe(struct zorro_dev *z, |
287 | const struct zorro_device_id *ent) | |
1da177e4 | 288 | { |
bb17b787 GU |
289 | struct Scsi_Host *instance; |
290 | unsigned long address; | |
c1d288a5 | 291 | int error; |
bb17b787 | 292 | unsigned int epc; |
bb17b787 | 293 | unsigned int default_dma_xfer_mask; |
cf2ed279 | 294 | struct gvp11_hostdata *hdata; |
349d65fd | 295 | struct gvp11_scsiregs *regs; |
6869b15e | 296 | wd33c93_regs wdregs; |
c1d288a5 GU |
297 | |
298 | default_dma_xfer_mask = ent->driver_data; | |
299 | ||
300 | /* | |
301 | * Rumors state that some GVP ram boards use the same product | |
302 | * code as the SCSI controllers. Therefore if the board-size | |
25985edc | 303 | * is not 64KB we assume it is a ram board and bail out. |
c1d288a5 GU |
304 | */ |
305 | if (zorro_resource_len(z) != 0x10000) | |
306 | return -ENODEV; | |
307 | ||
308 | address = z->resource.start; | |
309 | if (!request_mem_region(address, 256, "wd33c93")) | |
310 | return -EBUSY; | |
311 | ||
312 | regs = (struct gvp11_scsiregs *)(ZTWO_VADDR(address)); | |
313 | ||
314 | error = check_wd33c93(regs); | |
315 | if (error) | |
316 | goto fail_check_or_alloc; | |
317 | ||
318 | instance = scsi_host_alloc(&gvp11_scsi_template, | |
cf2ed279 | 319 | sizeof(struct gvp11_hostdata)); |
c1d288a5 GU |
320 | if (!instance) { |
321 | error = -ENOMEM; | |
322 | goto fail_check_or_alloc; | |
bb17b787 | 323 | } |
1da177e4 | 324 | |
c1d288a5 GU |
325 | instance->irq = IRQ_AMIGA_PORTS; |
326 | instance->unique_id = z->slotaddr; | |
1da177e4 | 327 | |
c1d288a5 GU |
328 | regs->secret2 = 1; |
329 | regs->secret1 = 0; | |
330 | regs->secret3 = 15; | |
331 | while (regs->CNTR & GVP11_DMAC_BUSY) | |
332 | ; | |
333 | regs->CNTR = 0; | |
334 | regs->BANK = 0; | |
68b3aa7c | 335 | |
c1d288a5 GU |
336 | wdregs.SASR = ®s->SASR; |
337 | wdregs.SCMD = ®s->SCMD; | |
df0ae249 | 338 | |
c1d288a5 GU |
339 | hdata = shost_priv(instance); |
340 | if (gvp11_xfer_mask) | |
cf2ed279 | 341 | hdata->wh.dma_xfer_mask = gvp11_xfer_mask; |
c1d288a5 | 342 | else |
cf2ed279 | 343 | hdata->wh.dma_xfer_mask = default_dma_xfer_mask; |
68b3aa7c | 344 | |
cf2ed279 GU |
345 | hdata->wh.no_sync = 0xff; |
346 | hdata->wh.fast = 0; | |
347 | hdata->wh.dma_mode = CTRL_DMA; | |
348 | hdata->regs = regs; | |
1da177e4 | 349 | |
c1d288a5 GU |
350 | /* |
351 | * Check for 14MHz SCSI clock | |
352 | */ | |
353 | epc = *(unsigned short *)(ZTWO_VADDR(address) + 0x8000); | |
354 | wd33c93_init(instance, wdregs, dma_setup, dma_stop, | |
355 | (epc & GVP_SCSICLKMASK) ? WD33C93_FS_8_10 | |
356 | : WD33C93_FS_12_15); | |
1da177e4 | 357 | |
c1d288a5 GU |
358 | error = request_irq(IRQ_AMIGA_PORTS, gvp11_intr, IRQF_SHARED, |
359 | "GVP11 SCSI", instance); | |
360 | if (error) | |
361 | goto fail_irq; | |
1da177e4 | 362 | |
c1d288a5 | 363 | regs->CNTR = GVP11_DMAC_INT_ENABLE; |
1da177e4 | 364 | |
c1d288a5 GU |
365 | error = scsi_add_host(instance, NULL); |
366 | if (error) | |
367 | goto fail_host; | |
1da177e4 | 368 | |
c1d288a5 GU |
369 | zorro_set_drvdata(z, instance); |
370 | scsi_scan_host(instance); | |
371 | return 0; | |
1da177e4 | 372 | |
c1d288a5 GU |
373 | fail_host: |
374 | free_irq(IRQ_AMIGA_PORTS, instance); | |
375 | fail_irq: | |
376 | scsi_host_put(instance); | |
377 | fail_check_or_alloc: | |
378 | release_mem_region(address, 256); | |
379 | return error; | |
380 | } | |
1da177e4 | 381 | |
c1d288a5 | 382 | static void __devexit gvp11_remove(struct zorro_dev *z) |
1da177e4 | 383 | { |
c1d288a5 | 384 | struct Scsi_Host *instance = zorro_get_drvdata(z); |
cf2ed279 | 385 | struct gvp11_hostdata *hdata = shost_priv(instance); |
6869b15e | 386 | |
cf2ed279 | 387 | hdata->regs->CNTR = 0; |
c1d288a5 | 388 | scsi_remove_host(instance); |
bb17b787 | 389 | free_irq(IRQ_AMIGA_PORTS, instance); |
c1d288a5 GU |
390 | scsi_host_put(instance); |
391 | release_mem_region(z->resource.start, 256); | |
392 | } | |
393 | ||
394 | /* | |
395 | * This should (hopefully) be the correct way to identify | |
396 | * all the different GVP SCSI controllers (except for the | |
397 | * SERIES I though). | |
398 | */ | |
399 | ||
400 | static struct zorro_device_id gvp11_zorro_tbl[] __devinitdata = { | |
401 | { ZORRO_PROD_GVP_COMBO_030_R3_SCSI, ~0x00ffffff }, | |
402 | { ZORRO_PROD_GVP_SERIES_II, ~0x00ffffff }, | |
403 | { ZORRO_PROD_GVP_GFORCE_030_SCSI, ~0x01ffffff }, | |
404 | { ZORRO_PROD_GVP_A530_SCSI, ~0x01ffffff }, | |
405 | { ZORRO_PROD_GVP_COMBO_030_R4_SCSI, ~0x01ffffff }, | |
406 | { ZORRO_PROD_GVP_A1291, ~0x07ffffff }, | |
407 | { ZORRO_PROD_GVP_GFORCE_040_SCSI_1, ~0x07ffffff }, | |
408 | { 0 } | |
409 | }; | |
410 | MODULE_DEVICE_TABLE(zorro, gvp11_zorro_tbl); | |
411 | ||
412 | static struct zorro_driver gvp11_driver = { | |
413 | .name = "gvp11", | |
414 | .id_table = gvp11_zorro_tbl, | |
415 | .probe = gvp11_probe, | |
416 | .remove = __devexit_p(gvp11_remove), | |
417 | }; | |
418 | ||
419 | static int __init gvp11_init(void) | |
420 | { | |
421 | return zorro_register_driver(&gvp11_driver); | |
422 | } | |
423 | module_init(gvp11_init); | |
424 | ||
425 | static void __exit gvp11_exit(void) | |
426 | { | |
427 | zorro_unregister_driver(&gvp11_driver); | |
1da177e4 | 428 | } |
c1d288a5 | 429 | module_exit(gvp11_exit); |
1da177e4 | 430 | |
c1d288a5 | 431 | MODULE_DESCRIPTION("GVP Series II SCSI"); |
1da177e4 | 432 | MODULE_LICENSE("GPL"); |