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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 | 2 | #include <linux/types.h> |
1da177e4 LT |
3 | #include <linux/init.h> |
4 | #include <linux/interrupt.h> | |
c1d288a5 GU |
5 | #include <linux/mm.h> |
6 | #include <linux/slab.h> | |
7 | #include <linux/spinlock.h> | |
8 | #include <linux/zorro.h> | |
acf3368f | 9 | #include <linux/module.h> |
1da177e4 | 10 | |
1da177e4 LT |
11 | #include <asm/page.h> |
12 | #include <asm/pgtable.h> | |
13 | #include <asm/amigaints.h> | |
14 | #include <asm/amigahw.h> | |
1da177e4 LT |
15 | |
16 | #include "scsi.h" | |
1da177e4 LT |
17 | #include "wd33c93.h" |
18 | #include "gvp11.h" | |
19 | ||
1da177e4 | 20 | |
11ca46ea GU |
21 | #define CHECK_WD33C93 |
22 | ||
cf2ed279 GU |
23 | struct gvp11_hostdata { |
24 | struct WD33C93_hostdata wh; | |
25 | struct gvp11_scsiregs *regs; | |
26 | }; | |
27 | ||
6869b15e | 28 | static irqreturn_t gvp11_intr(int irq, void *data) |
1da177e4 | 29 | { |
6869b15e | 30 | struct Scsi_Host *instance = data; |
cf2ed279 GU |
31 | struct gvp11_hostdata *hdata = shost_priv(instance); |
32 | unsigned int status = hdata->regs->CNTR; | |
bb17b787 | 33 | unsigned long flags; |
bb17b787 | 34 | |
bb17b787 GU |
35 | if (!(status & GVP11_DMAC_INT_PENDING)) |
36 | return IRQ_NONE; | |
37 | ||
38 | spin_lock_irqsave(instance->host_lock, flags); | |
39 | wd33c93_intr(instance); | |
40 | spin_unlock_irqrestore(instance->host_lock, flags); | |
41 | return IRQ_HANDLED; | |
1da177e4 LT |
42 | } |
43 | ||
44 | static int gvp11_xfer_mask = 0; | |
45 | ||
bb17b787 | 46 | void gvp11_setup(char *str, int *ints) |
1da177e4 | 47 | { |
bb17b787 | 48 | gvp11_xfer_mask = ints[1]; |
1da177e4 LT |
49 | } |
50 | ||
65396410 | 51 | static int dma_setup(struct scsi_cmnd *cmd, int dir_in) |
1da177e4 | 52 | { |
52c3d8a6 | 53 | struct Scsi_Host *instance = cmd->device->host; |
cf2ed279 GU |
54 | struct gvp11_hostdata *hdata = shost_priv(instance); |
55 | struct WD33C93_hostdata *wh = &hdata->wh; | |
56 | struct gvp11_scsiregs *regs = hdata->regs; | |
bb17b787 GU |
57 | unsigned short cntr = GVP11_DMAC_INT_ENABLE; |
58 | unsigned long addr = virt_to_bus(cmd->SCp.ptr); | |
59 | int bank_mask; | |
60 | static int scsi_alloc_out_of_range = 0; | |
1da177e4 | 61 | |
bb17b787 | 62 | /* use bounce buffer if the physical address is bad */ |
cf2ed279 GU |
63 | if (addr & wh->dma_xfer_mask) { |
64 | wh->dma_bounce_len = (cmd->SCp.this_residual + 511) & ~0x1ff; | |
bb17b787 GU |
65 | |
66 | if (!scsi_alloc_out_of_range) { | |
cf2ed279 GU |
67 | wh->dma_bounce_buffer = |
68 | kmalloc(wh->dma_bounce_len, GFP_KERNEL); | |
69 | wh->dma_buffer_pool = BUF_SCSI_ALLOCED; | |
bb17b787 | 70 | } |
1da177e4 | 71 | |
bb17b787 | 72 | if (scsi_alloc_out_of_range || |
cf2ed279 GU |
73 | !wh->dma_bounce_buffer) { |
74 | wh->dma_bounce_buffer = | |
75 | amiga_chip_alloc(wh->dma_bounce_len, | |
bb17b787 | 76 | "GVP II SCSI Bounce Buffer"); |
1da177e4 | 77 | |
cf2ed279 GU |
78 | if (!wh->dma_bounce_buffer) { |
79 | wh->dma_bounce_len = 0; | |
bb17b787 GU |
80 | return 1; |
81 | } | |
1da177e4 | 82 | |
cf2ed279 | 83 | wh->dma_buffer_pool = BUF_CHIP_ALLOCED; |
bb17b787 | 84 | } |
1da177e4 | 85 | |
bb17b787 | 86 | /* check if the address of the bounce buffer is OK */ |
cf2ed279 | 87 | addr = virt_to_bus(wh->dma_bounce_buffer); |
bb17b787 | 88 | |
cf2ed279 | 89 | if (addr & wh->dma_xfer_mask) { |
bb17b787 | 90 | /* fall back to Chip RAM if address out of range */ |
cf2ed279 GU |
91 | if (wh->dma_buffer_pool == BUF_SCSI_ALLOCED) { |
92 | kfree(wh->dma_bounce_buffer); | |
bb17b787 GU |
93 | scsi_alloc_out_of_range = 1; |
94 | } else { | |
cf2ed279 | 95 | amiga_chip_free(wh->dma_bounce_buffer); |
bb17b787 GU |
96 | } |
97 | ||
cf2ed279 GU |
98 | wh->dma_bounce_buffer = |
99 | amiga_chip_alloc(wh->dma_bounce_len, | |
bb17b787 GU |
100 | "GVP II SCSI Bounce Buffer"); |
101 | ||
cf2ed279 GU |
102 | if (!wh->dma_bounce_buffer) { |
103 | wh->dma_bounce_len = 0; | |
bb17b787 GU |
104 | return 1; |
105 | } | |
106 | ||
cf2ed279 GU |
107 | addr = virt_to_bus(wh->dma_bounce_buffer); |
108 | wh->dma_buffer_pool = BUF_CHIP_ALLOCED; | |
bb17b787 GU |
109 | } |
110 | ||
111 | if (!dir_in) { | |
112 | /* copy to bounce buffer for a write */ | |
cf2ed279 | 113 | memcpy(wh->dma_bounce_buffer, cmd->SCp.ptr, |
52c3d8a6 | 114 | cmd->SCp.this_residual); |
bb17b787 | 115 | } |
1da177e4 | 116 | } |
1da177e4 | 117 | |
bb17b787 GU |
118 | /* setup dma direction */ |
119 | if (!dir_in) | |
120 | cntr |= GVP11_DMAC_DIR_WRITE; | |
1da177e4 | 121 | |
cf2ed279 | 122 | wh->dma_dir = dir_in; |
6869b15e | 123 | regs->CNTR = cntr; |
1da177e4 | 124 | |
bb17b787 | 125 | /* setup DMA *physical* address */ |
6869b15e | 126 | regs->ACR = addr; |
1da177e4 | 127 | |
bb17b787 GU |
128 | if (dir_in) { |
129 | /* invalidate any cache */ | |
130 | cache_clear(addr, cmd->SCp.this_residual); | |
131 | } else { | |
132 | /* push any dirty cache */ | |
133 | cache_push(addr, cmd->SCp.this_residual); | |
134 | } | |
1da177e4 | 135 | |
cf2ed279 | 136 | bank_mask = (~wh->dma_xfer_mask >> 18) & 0x01c0; |
52c3d8a6 | 137 | if (bank_mask) |
6869b15e | 138 | regs->BANK = bank_mask & (addr >> 18); |
1da177e4 | 139 | |
bb17b787 | 140 | /* start DMA */ |
6869b15e | 141 | regs->ST_DMA = 1; |
1da177e4 | 142 | |
bb17b787 GU |
143 | /* return success */ |
144 | return 0; | |
1da177e4 LT |
145 | } |
146 | ||
65396410 HK |
147 | static void dma_stop(struct Scsi_Host *instance, struct scsi_cmnd *SCpnt, |
148 | int status) | |
1da177e4 | 149 | { |
cf2ed279 GU |
150 | struct gvp11_hostdata *hdata = shost_priv(instance); |
151 | struct WD33C93_hostdata *wh = &hdata->wh; | |
152 | struct gvp11_scsiregs *regs = hdata->regs; | |
52c3d8a6 | 153 | |
bb17b787 | 154 | /* stop DMA */ |
6869b15e | 155 | regs->SP_DMA = 1; |
bb17b787 | 156 | /* remove write bit from CONTROL bits */ |
6869b15e | 157 | regs->CNTR = GVP11_DMAC_INT_ENABLE; |
bb17b787 GU |
158 | |
159 | /* copy from a bounce buffer, if necessary */ | |
cf2ed279 GU |
160 | if (status && wh->dma_bounce_buffer) { |
161 | if (wh->dma_dir && SCpnt) | |
162 | memcpy(SCpnt->SCp.ptr, wh->dma_bounce_buffer, | |
bb17b787 GU |
163 | SCpnt->SCp.this_residual); |
164 | ||
cf2ed279 GU |
165 | if (wh->dma_buffer_pool == BUF_SCSI_ALLOCED) |
166 | kfree(wh->dma_bounce_buffer); | |
bb17b787 | 167 | else |
cf2ed279 | 168 | amiga_chip_free(wh->dma_bounce_buffer); |
bb17b787 | 169 | |
cf2ed279 GU |
170 | wh->dma_bounce_buffer = NULL; |
171 | wh->dma_bounce_len = 0; | |
bb17b787 | 172 | } |
1da177e4 LT |
173 | } |
174 | ||
c1d288a5 GU |
175 | static struct scsi_host_template gvp11_scsi_template = { |
176 | .module = THIS_MODULE, | |
177 | .name = "GVP Series II SCSI", | |
408bb25b AV |
178 | .show_info = wd33c93_show_info, |
179 | .write_info = wd33c93_write_info, | |
c1d288a5 GU |
180 | .proc_name = "GVP11", |
181 | .queuecommand = wd33c93_queuecommand, | |
182 | .eh_abort_handler = wd33c93_abort, | |
c1d288a5 GU |
183 | .eh_host_reset_handler = wd33c93_host_reset, |
184 | .can_queue = CAN_QUEUE, | |
185 | .this_id = 7, | |
186 | .sg_tablesize = SG_ALL, | |
187 | .cmd_per_lun = CMD_PER_LUN, | |
4af14d11 | 188 | .dma_boundary = PAGE_SIZE - 1, |
c1d288a5 GU |
189 | }; |
190 | ||
6f039790 | 191 | static int check_wd33c93(struct gvp11_scsiregs *regs) |
11ca46ea GU |
192 | { |
193 | #ifdef CHECK_WD33C93 | |
194 | volatile unsigned char *sasr_3393, *scmd_3393; | |
195 | unsigned char save_sasr; | |
196 | unsigned char q, qq; | |
197 | ||
198 | /* | |
199 | * These darn GVP boards are a problem - it can be tough to tell | |
200 | * whether or not they include a SCSI controller. This is the | |
201 | * ultimate Yet-Another-GVP-Detection-Hack in that it actually | |
202 | * probes for a WD33c93 chip: If we find one, it's extremely | |
203 | * likely that this card supports SCSI, regardless of Product_ | |
204 | * Code, Board_Size, etc. | |
205 | */ | |
206 | ||
207 | /* Get pointers to the presumed register locations and save contents */ | |
208 | ||
209 | sasr_3393 = ®s->SASR; | |
210 | scmd_3393 = ®s->SCMD; | |
211 | save_sasr = *sasr_3393; | |
212 | ||
213 | /* First test the AuxStatus Reg */ | |
214 | ||
215 | q = *sasr_3393; /* read it */ | |
216 | if (q & 0x08) /* bit 3 should always be clear */ | |
217 | return -ENODEV; | |
218 | *sasr_3393 = WD_AUXILIARY_STATUS; /* setup indirect address */ | |
219 | if (*sasr_3393 == WD_AUXILIARY_STATUS) { /* shouldn't retain the write */ | |
220 | *sasr_3393 = save_sasr; /* Oops - restore this byte */ | |
221 | return -ENODEV; | |
222 | } | |
223 | if (*sasr_3393 != q) { /* should still read the same */ | |
224 | *sasr_3393 = save_sasr; /* Oops - restore this byte */ | |
225 | return -ENODEV; | |
226 | } | |
227 | if (*scmd_3393 != q) /* and so should the image at 0x1f */ | |
228 | return -ENODEV; | |
229 | ||
230 | /* | |
231 | * Ok, we probably have a wd33c93, but let's check a few other places | |
232 | * for good measure. Make sure that this works for both 'A and 'B | |
233 | * chip versions. | |
234 | */ | |
235 | ||
236 | *sasr_3393 = WD_SCSI_STATUS; | |
237 | q = *scmd_3393; | |
238 | *sasr_3393 = WD_SCSI_STATUS; | |
239 | *scmd_3393 = ~q; | |
240 | *sasr_3393 = WD_SCSI_STATUS; | |
241 | qq = *scmd_3393; | |
242 | *sasr_3393 = WD_SCSI_STATUS; | |
243 | *scmd_3393 = q; | |
244 | if (qq != q) /* should be read only */ | |
245 | return -ENODEV; | |
246 | *sasr_3393 = 0x1e; /* this register is unimplemented */ | |
247 | q = *scmd_3393; | |
248 | *sasr_3393 = 0x1e; | |
249 | *scmd_3393 = ~q; | |
250 | *sasr_3393 = 0x1e; | |
251 | qq = *scmd_3393; | |
252 | *sasr_3393 = 0x1e; | |
253 | *scmd_3393 = q; | |
254 | if (qq != q || qq != 0xff) /* should be read only, all 1's */ | |
255 | return -ENODEV; | |
256 | *sasr_3393 = WD_TIMEOUT_PERIOD; | |
257 | q = *scmd_3393; | |
258 | *sasr_3393 = WD_TIMEOUT_PERIOD; | |
259 | *scmd_3393 = ~q; | |
260 | *sasr_3393 = WD_TIMEOUT_PERIOD; | |
261 | qq = *scmd_3393; | |
262 | *sasr_3393 = WD_TIMEOUT_PERIOD; | |
263 | *scmd_3393 = q; | |
264 | if (qq != (~q & 0xff)) /* should be read/write */ | |
265 | return -ENODEV; | |
266 | #endif /* CHECK_WD33C93 */ | |
267 | ||
268 | return 0; | |
269 | } | |
1da177e4 | 270 | |
6f039790 | 271 | static int gvp11_probe(struct zorro_dev *z, const struct zorro_device_id *ent) |
1da177e4 | 272 | { |
bb17b787 GU |
273 | struct Scsi_Host *instance; |
274 | unsigned long address; | |
c1d288a5 | 275 | int error; |
bb17b787 | 276 | unsigned int epc; |
bb17b787 | 277 | unsigned int default_dma_xfer_mask; |
cf2ed279 | 278 | struct gvp11_hostdata *hdata; |
349d65fd | 279 | struct gvp11_scsiregs *regs; |
6869b15e | 280 | wd33c93_regs wdregs; |
c1d288a5 GU |
281 | |
282 | default_dma_xfer_mask = ent->driver_data; | |
283 | ||
284 | /* | |
285 | * Rumors state that some GVP ram boards use the same product | |
286 | * code as the SCSI controllers. Therefore if the board-size | |
25985edc | 287 | * is not 64KB we assume it is a ram board and bail out. |
c1d288a5 GU |
288 | */ |
289 | if (zorro_resource_len(z) != 0x10000) | |
290 | return -ENODEV; | |
291 | ||
292 | address = z->resource.start; | |
293 | if (!request_mem_region(address, 256, "wd33c93")) | |
294 | return -EBUSY; | |
295 | ||
6112ea08 | 296 | regs = ZTWO_VADDR(address); |
c1d288a5 GU |
297 | |
298 | error = check_wd33c93(regs); | |
299 | if (error) | |
300 | goto fail_check_or_alloc; | |
301 | ||
302 | instance = scsi_host_alloc(&gvp11_scsi_template, | |
cf2ed279 | 303 | sizeof(struct gvp11_hostdata)); |
c1d288a5 GU |
304 | if (!instance) { |
305 | error = -ENOMEM; | |
306 | goto fail_check_or_alloc; | |
bb17b787 | 307 | } |
1da177e4 | 308 | |
c1d288a5 GU |
309 | instance->irq = IRQ_AMIGA_PORTS; |
310 | instance->unique_id = z->slotaddr; | |
1da177e4 | 311 | |
c1d288a5 GU |
312 | regs->secret2 = 1; |
313 | regs->secret1 = 0; | |
314 | regs->secret3 = 15; | |
315 | while (regs->CNTR & GVP11_DMAC_BUSY) | |
316 | ; | |
317 | regs->CNTR = 0; | |
318 | regs->BANK = 0; | |
68b3aa7c | 319 | |
c1d288a5 GU |
320 | wdregs.SASR = ®s->SASR; |
321 | wdregs.SCMD = ®s->SCMD; | |
df0ae249 | 322 | |
c1d288a5 GU |
323 | hdata = shost_priv(instance); |
324 | if (gvp11_xfer_mask) | |
cf2ed279 | 325 | hdata->wh.dma_xfer_mask = gvp11_xfer_mask; |
c1d288a5 | 326 | else |
cf2ed279 | 327 | hdata->wh.dma_xfer_mask = default_dma_xfer_mask; |
68b3aa7c | 328 | |
cf2ed279 GU |
329 | hdata->wh.no_sync = 0xff; |
330 | hdata->wh.fast = 0; | |
331 | hdata->wh.dma_mode = CTRL_DMA; | |
332 | hdata->regs = regs; | |
1da177e4 | 333 | |
c1d288a5 GU |
334 | /* |
335 | * Check for 14MHz SCSI clock | |
336 | */ | |
337 | epc = *(unsigned short *)(ZTWO_VADDR(address) + 0x8000); | |
338 | wd33c93_init(instance, wdregs, dma_setup, dma_stop, | |
339 | (epc & GVP_SCSICLKMASK) ? WD33C93_FS_8_10 | |
340 | : WD33C93_FS_12_15); | |
1da177e4 | 341 | |
c1d288a5 GU |
342 | error = request_irq(IRQ_AMIGA_PORTS, gvp11_intr, IRQF_SHARED, |
343 | "GVP11 SCSI", instance); | |
344 | if (error) | |
345 | goto fail_irq; | |
1da177e4 | 346 | |
c1d288a5 | 347 | regs->CNTR = GVP11_DMAC_INT_ENABLE; |
1da177e4 | 348 | |
c1d288a5 GU |
349 | error = scsi_add_host(instance, NULL); |
350 | if (error) | |
351 | goto fail_host; | |
1da177e4 | 352 | |
c1d288a5 GU |
353 | zorro_set_drvdata(z, instance); |
354 | scsi_scan_host(instance); | |
355 | return 0; | |
1da177e4 | 356 | |
c1d288a5 GU |
357 | fail_host: |
358 | free_irq(IRQ_AMIGA_PORTS, instance); | |
359 | fail_irq: | |
360 | scsi_host_put(instance); | |
361 | fail_check_or_alloc: | |
362 | release_mem_region(address, 256); | |
363 | return error; | |
364 | } | |
1da177e4 | 365 | |
6f039790 | 366 | static void gvp11_remove(struct zorro_dev *z) |
1da177e4 | 367 | { |
c1d288a5 | 368 | struct Scsi_Host *instance = zorro_get_drvdata(z); |
cf2ed279 | 369 | struct gvp11_hostdata *hdata = shost_priv(instance); |
6869b15e | 370 | |
cf2ed279 | 371 | hdata->regs->CNTR = 0; |
c1d288a5 | 372 | scsi_remove_host(instance); |
bb17b787 | 373 | free_irq(IRQ_AMIGA_PORTS, instance); |
c1d288a5 GU |
374 | scsi_host_put(instance); |
375 | release_mem_region(z->resource.start, 256); | |
376 | } | |
377 | ||
378 | /* | |
379 | * This should (hopefully) be the correct way to identify | |
380 | * all the different GVP SCSI controllers (except for the | |
381 | * SERIES I though). | |
382 | */ | |
383 | ||
6f039790 | 384 | static struct zorro_device_id gvp11_zorro_tbl[] = { |
c1d288a5 GU |
385 | { ZORRO_PROD_GVP_COMBO_030_R3_SCSI, ~0x00ffffff }, |
386 | { ZORRO_PROD_GVP_SERIES_II, ~0x00ffffff }, | |
387 | { ZORRO_PROD_GVP_GFORCE_030_SCSI, ~0x01ffffff }, | |
388 | { ZORRO_PROD_GVP_A530_SCSI, ~0x01ffffff }, | |
389 | { ZORRO_PROD_GVP_COMBO_030_R4_SCSI, ~0x01ffffff }, | |
390 | { ZORRO_PROD_GVP_A1291, ~0x07ffffff }, | |
391 | { ZORRO_PROD_GVP_GFORCE_040_SCSI_1, ~0x07ffffff }, | |
392 | { 0 } | |
393 | }; | |
394 | MODULE_DEVICE_TABLE(zorro, gvp11_zorro_tbl); | |
395 | ||
396 | static struct zorro_driver gvp11_driver = { | |
397 | .name = "gvp11", | |
398 | .id_table = gvp11_zorro_tbl, | |
399 | .probe = gvp11_probe, | |
6f039790 | 400 | .remove = gvp11_remove, |
c1d288a5 GU |
401 | }; |
402 | ||
403 | static int __init gvp11_init(void) | |
404 | { | |
405 | return zorro_register_driver(&gvp11_driver); | |
406 | } | |
407 | module_init(gvp11_init); | |
408 | ||
409 | static void __exit gvp11_exit(void) | |
410 | { | |
411 | zorro_unregister_driver(&gvp11_driver); | |
1da177e4 | 412 | } |
c1d288a5 | 413 | module_exit(gvp11_exit); |
1da177e4 | 414 | |
c1d288a5 | 415 | MODULE_DESCRIPTION("GVP Series II SCSI"); |
1da177e4 | 416 | MODULE_LICENSE("GPL"); |