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scsi: hisi_sas: Pre-allocate slot DMA buffers
[mirror_ubuntu-eoan-kernel.git] / drivers / scsi / hisi_sas / hisi_sas.h
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1/*
2 * Copyright (c) 2015 Linaro Ltd.
3 * Copyright (c) 2015 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12#ifndef _HISI_SAS_H_
13#define _HISI_SAS_H_
14
4d558c77 15#include <linux/acpi.h>
3bc45af8 16#include <linux/clk.h>
e8899fad 17#include <linux/dmapool.h>
a25d0d3d 18#include <linux/iopoll.h>
2ba5afb6 19#include <linux/lcm.h>
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20#include <linux/mfd/syscon.h>
21#include <linux/module.h>
22#include <linux/of_address.h>
11b75249 23#include <linux/pci.h>
e8899fad 24#include <linux/platform_device.h>
4d558c77 25#include <linux/property.h>
e8899fad 26#include <linux/regmap.h>
6f2ff1a1 27#include <scsi/sas_ata.h>
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28#include <scsi/libsas.h>
29
7eb7869f 30#define HISI_SAS_MAX_PHYS 9
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31#define HISI_SAS_MAX_QUEUES 32
32#define HISI_SAS_QUEUE_SLOTS 512
3297ded1 33#define HISI_SAS_MAX_ITCT_ENTRIES 1024
7eb7869f 34#define HISI_SAS_MAX_DEVICES HISI_SAS_MAX_ITCT_ENTRIES
06ec0fb9 35#define HISI_SAS_RESET_BIT 0
917d3bda 36#define HISI_SAS_REJECT_CMD_BIT 1
7eb7869f 37
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38#define HISI_SAS_STATUS_BUF_SZ (sizeof(struct hisi_sas_status_buffer))
39#define HISI_SAS_COMMAND_TABLE_SZ (sizeof(union hisi_sas_command_table))
40
41#define hisi_sas_status_buf_addr(buf) \
42 (buf + offsetof(struct hisi_sas_slot_buf_table, status_buffer))
43#define hisi_sas_status_buf_addr_mem(slot) hisi_sas_status_buf_addr(slot->buf)
44#define hisi_sas_status_buf_addr_dma(slot) \
45 hisi_sas_status_buf_addr(slot->buf_dma)
46
47#define hisi_sas_cmd_hdr_addr(buf) \
48 (buf + offsetof(struct hisi_sas_slot_buf_table, command_header))
49#define hisi_sas_cmd_hdr_addr_mem(slot) hisi_sas_cmd_hdr_addr(slot->buf)
50#define hisi_sas_cmd_hdr_addr_dma(slot) hisi_sas_cmd_hdr_addr(slot->buf_dma)
51
52#define hisi_sas_sge_addr(buf) \
53 (buf + offsetof(struct hisi_sas_slot_buf_table, sge_page))
54#define hisi_sas_sge_addr_mem(slot) hisi_sas_sge_addr(slot->buf)
55#define hisi_sas_sge_addr_dma(slot) hisi_sas_sge_addr(slot->buf_dma)
6be6de18 56
42e7a693 57#define HISI_SAS_MAX_SSP_RESP_SZ (sizeof(struct ssp_frame_hdr) + 1024)
66ee999b 58#define HISI_SAS_MAX_SMP_RESP_SZ 1028
6f2ff1a1 59#define HISI_SAS_MAX_STP_RESP_SZ 28
42e7a693 60
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61#define DEV_IS_EXPANDER(type) \
62 ((type == SAS_EDGE_EXPANDER_DEVICE) || \
63 (type == SAS_FANOUT_EXPANDER_DEVICE))
64
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65#define HISI_SAS_SATA_PROTOCOL_NONDATA 0x1
66#define HISI_SAS_SATA_PROTOCOL_PIO 0x2
67#define HISI_SAS_SATA_PROTOCOL_DMA 0x4
68#define HISI_SAS_SATA_PROTOCOL_FPDMA 0x8
69#define HISI_SAS_SATA_PROTOCOL_ATAPI 0x10
70
abda97c2 71struct hisi_hba;
af740dbe 72
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73enum {
74 PORT_TYPE_SAS = (1U << 1),
75 PORT_TYPE_SATA = (1U << 0),
76};
77
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78enum dev_status {
79 HISI_SAS_DEV_NORMAL,
80 HISI_SAS_DEV_EH,
81};
abda97c2 82
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83enum {
84 HISI_SAS_INT_ABT_CMD = 0,
85 HISI_SAS_INT_ABT_DEV = 1,
86};
87
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88enum hisi_sas_dev_type {
89 HISI_SAS_DEV_TYPE_STP = 0,
90 HISI_SAS_DEV_TYPE_SSP,
91 HISI_SAS_DEV_TYPE_SATA,
92};
93
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94struct hisi_sas_hw_error {
95 u32 irq_msk;
96 u32 msk;
97 int shift;
98 const char *msg;
99 int reg;
729428ca 100 const struct hisi_sas_hw_error *sub;
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101};
102
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103struct hisi_sas_rst {
104 struct hisi_hba *hisi_hba;
105 struct completion *completion;
106 struct work_struct work;
107 bool done;
108};
109
110#define HISI_SAS_RST_WORK_INIT(r, c) \
111 { .hisi_hba = hisi_hba, \
112 .completion = &c, \
113 .work = __WORK_INITIALIZER(r.work, \
114 hisi_sas_sync_rst_work_handler), \
115 .done = false, \
116 }
117
118#define HISI_SAS_DECLARE_RST_WORK_ON_STACK(r) \
119 DECLARE_COMPLETION_ONSTACK(c); \
120 DECLARE_WORK(w, hisi_sas_sync_rst_work_handler); \
121 struct hisi_sas_rst r = HISI_SAS_RST_WORK_INIT(r, c)
122
123enum hisi_sas_bit_err_type {
124 HISI_SAS_ERR_SINGLE_BIT_ECC = 0x0,
125 HISI_SAS_ERR_MULTI_BIT_ECC = 0x1,
126};
127
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128enum hisi_sas_phy_event {
129 HISI_PHYE_PHY_UP = 0U,
057c3d1f 130 HISI_PHYE_LINK_RESET,
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131 HISI_PHYES_NUM,
132};
133
7eb7869f 134struct hisi_sas_phy {
e537b62b 135 struct work_struct works[HISI_PHYES_NUM];
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136 struct hisi_hba *hisi_hba;
137 struct hisi_sas_port *port;
7eb7869f 138 struct asd_sas_phy sas_phy;
976867e6 139 struct sas_identify identify;
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140 struct completion *reset_completion;
141 spinlock_t lock;
976867e6 142 u64 port_id; /* from hw */
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143 u64 frame_rcvd_size;
144 u8 frame_rcvd[32];
145 u8 phy_attached;
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146 u8 in_reset;
147 u8 reserved[2];
d0ef10c9 148 u32 phy_type;
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149 enum sas_linkrate minimum_linkrate;
150 enum sas_linkrate maximum_linkrate;
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151};
152
153struct hisi_sas_port {
154 struct asd_sas_port sas_port;
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155 u8 port_attached;
156 u8 id; /* from hw */
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157};
158
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159struct hisi_sas_cq {
160 struct hisi_hba *hisi_hba;
d177c408 161 struct tasklet_struct tasklet;
e6c346f3 162 int rd_point;
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163 int id;
164};
165
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166struct hisi_sas_dq {
167 struct hisi_hba *hisi_hba;
fa222db0 168 struct list_head list;
b1a49412 169 spinlock_t lock;
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170 int wr_point;
171 int id;
172};
173
af740dbe 174struct hisi_sas_device {
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175 struct hisi_hba *hisi_hba;
176 struct domain_device *sas_device;
640acc9a 177 struct completion *completion;
b1a49412 178 struct hisi_sas_dq *dq;
ad604832 179 struct list_head list;
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180 enum sas_device_type dev_type;
181 int device_id;
32ccba52 182 int sata_idx;
ad604832 183 u8 dev_status;
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184};
185
78bd2b4f 186struct hisi_sas_tmf_task {
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187 int force_phy;
188 int phy_id;
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189 u8 tmf;
190 u16 tag_of_task_to_be_managed;
191};
192
6be6de18 193struct hisi_sas_slot {
42e7a693 194 struct list_head entry;
fa222db0 195 struct list_head delivery;
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196 struct sas_task *task;
197 struct hisi_sas_port *port;
198 u64 n_elem;
199 int dlvry_queue;
200 int dlvry_queue_slot;
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201 int cmplt_queue;
202 int cmplt_queue_slot;
cac9b2a2 203 int abort;
fa222db0 204 int ready;
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205 void *cmd_hdr;
206 dma_addr_t cmd_hdr_dma;
cac9b2a2 207 struct work_struct abort_slot;
0844a3ff 208 struct timer_list internal_abort_timer;
cd938e53 209 bool is_internal;
78bd2b4f 210 struct hisi_sas_tmf_task *tmf;
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211 /* Do not reorder/change members after here */
212 void *buf;
213 dma_addr_t buf_dma;
214 int idx;
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215};
216
7eb7869f 217struct hisi_sas_hw {
8ff1d571 218 int (*hw_init)(struct hisi_hba *hisi_hba);
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219 void (*setup_itct)(struct hisi_hba *hisi_hba,
220 struct hisi_sas_device *device);
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221 int (*slot_index_alloc)(struct hisi_hba *hisi_hba, int *slot_idx,
222 struct domain_device *device);
223 struct hisi_sas_device *(*alloc_dev)(struct domain_device *device);
66139921 224 void (*sl_notify)(struct hisi_hba *hisi_hba, int phy_no);
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225 int (*get_free_slot)(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq);
226 void (*start_delivery)(struct hisi_sas_dq *dq);
a2b3820b 227 void (*prep_ssp)(struct hisi_hba *hisi_hba,
78bd2b4f 228 struct hisi_sas_slot *slot);
a2b3820b 229 void (*prep_smp)(struct hisi_hba *hisi_hba,
66ee999b 230 struct hisi_sas_slot *slot);
a2b3820b 231 void (*prep_stp)(struct hisi_hba *hisi_hba,
6f2ff1a1 232 struct hisi_sas_slot *slot);
a2b3820b 233 void (*prep_abort)(struct hisi_hba *hisi_hba,
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234 struct hisi_sas_slot *slot,
235 int device_id, int abort_flag, int tag_to_abort);
27a3f229 236 int (*slot_complete)(struct hisi_hba *hisi_hba,
405314df 237 struct hisi_sas_slot *slot);
396b8044 238 void (*phys_init)(struct hisi_hba *hisi_hba);
1eb8eeac 239 void (*phy_start)(struct hisi_hba *hisi_hba, int phy_no);
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240 void (*phy_disable)(struct hisi_hba *hisi_hba, int phy_no);
241 void (*phy_hard_reset)(struct hisi_hba *hisi_hba, int phy_no);
c52108c6 242 void (*get_events)(struct hisi_hba *hisi_hba, int phy_no);
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243 void (*phy_set_linkrate)(struct hisi_hba *hisi_hba, int phy_no,
244 struct sas_phy_linkrates *linkrates);
245 enum sas_linkrate (*phy_get_max_linkrate)(void);
0258141a 246 void (*clear_itct)(struct hisi_hba *hisi_hba,
27a3f229 247 struct hisi_sas_device *dev);
0258141a 248 void (*free_device)(struct hisi_sas_device *sas_dev);
184a4635 249 int (*get_wideport_bitmap)(struct hisi_hba *hisi_hba, int port_id);
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250 void (*dereg_device)(struct hisi_hba *hisi_hba,
251 struct domain_device *device);
06ec0fb9 252 int (*soft_reset)(struct hisi_hba *hisi_hba);
917d3bda 253 u32 (*get_phys_state)(struct hisi_hba *hisi_hba);
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254 int (*write_gpio)(struct hisi_hba *hisi_hba, u8 reg_type,
255 u8 reg_index, u8 reg_count, u8 *write_data);
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256 void (*wait_cmds_complete_timeout)(struct hisi_hba *hisi_hba,
257 int delay_ms, int timeout_ms);
a8d547bd 258 int max_command_entries;
6be6de18 259 int complete_hdr_size;
235bfc7f 260 struct scsi_host_template *sht;
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261};
262
263struct hisi_hba {
264 /* This must be the first element, used by SHOST_TO_SAS_HA */
265 struct sas_ha_struct *p;
266
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267 struct platform_device *platform_dev;
268 struct pci_dev *pci_dev;
269 struct device *dev;
270
e26b2f40 271 void __iomem *regs;
6379c560 272 void __iomem *sgpio_regs;
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273 struct regmap *ctrl;
274 u32 ctrl_reset_reg;
275 u32 ctrl_reset_sts_reg;
276 u32 ctrl_clock_ena_reg;
3bc45af8 277 u32 refclk_frequency_mhz;
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278 u8 sas_addr[SAS_ADDR_SIZE];
279
280 int n_phy;
fa42d80d 281 spinlock_t lock;
d2fc401e 282 struct semaphore sem;
7eb7869f 283
fa42d80d 284 struct timer_list timer;
7e9080e1 285 struct workqueue_struct *wq;
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286
287 int slot_index_count;
fa3be0f2 288 int last_slot_index;
1b865185 289 int last_dev_id;
257efd1f 290 unsigned long *slot_index_tags;
c7b9d369 291 unsigned long reject_stp_links_msk;
257efd1f 292
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293 /* SCSI/SAS glue */
294 struct sas_ha_struct sha;
295 struct Scsi_Host *shost;
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296
297 struct hisi_sas_cq cq[HISI_SAS_MAX_QUEUES];
4fde02ad 298 struct hisi_sas_dq dq[HISI_SAS_MAX_QUEUES];
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299 struct hisi_sas_phy phy[HISI_SAS_MAX_PHYS];
300 struct hisi_sas_port port[HISI_SAS_MAX_PHYS];
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301
302 int queue_count;
6be6de18 303
af740dbe 304 struct hisi_sas_device devices[HISI_SAS_MAX_DEVICES];
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305 struct hisi_sas_cmd_hdr *cmd_hdr[HISI_SAS_MAX_QUEUES];
306 dma_addr_t cmd_hdr_dma[HISI_SAS_MAX_QUEUES];
307 void *complete_hdr[HISI_SAS_MAX_QUEUES];
308 dma_addr_t complete_hdr_dma[HISI_SAS_MAX_QUEUES];
309 struct hisi_sas_initial_fis *initial_fis;
310 dma_addr_t initial_fis_dma;
311 struct hisi_sas_itct *itct;
312 dma_addr_t itct_dma;
313 struct hisi_sas_iost *iost;
314 dma_addr_t iost_dma;
315 struct hisi_sas_breakpoint *breakpoint;
316 dma_addr_t breakpoint_dma;
317 struct hisi_sas_breakpoint *sata_breakpoint;
318 dma_addr_t sata_breakpoint_dma;
319 struct hisi_sas_slot *slot_info;
06ec0fb9 320 unsigned long flags;
7eb7869f 321 const struct hisi_sas_hw *hw; /* Low level hw interface */
32ccba52 322 unsigned long sata_dev_bitmap[BITS_TO_LONGS(HISI_SAS_MAX_DEVICES)];
06ec0fb9 323 struct work_struct rst_work;
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324};
325
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326/* Generic HW DMA host memory structures */
327/* Delivery queue header */
328struct hisi_sas_cmd_hdr {
329 /* dw0 */
330 __le32 dw0;
331
332 /* dw1 */
333 __le32 dw1;
334
335 /* dw2 */
336 __le32 dw2;
337
338 /* dw3 */
339 __le32 transfer_tags;
340
341 /* dw4 */
342 __le32 data_transfer_len;
343
344 /* dw5 */
345 __le32 first_burst_num;
346
347 /* dw6 */
348 __le32 sg_len;
349
350 /* dw7 */
351 __le32 dw7;
352
353 /* dw8-9 */
354 __le64 cmd_table_addr;
355
356 /* dw10-11 */
357 __le64 sts_buffer_addr;
358
359 /* dw12-13 */
360 __le64 prd_table_addr;
361
362 /* dw14-15 */
363 __le64 dif_prd_table_addr;
364};
365
366struct hisi_sas_itct {
367 __le64 qw0;
368 __le64 sas_addr;
369 __le64 qw2;
370 __le64 qw3;
281e3bf6 371 __le64 qw4_15[12];
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372};
373
374struct hisi_sas_iost {
375 __le64 qw0;
376 __le64 qw1;
377 __le64 qw2;
378 __le64 qw3;
379};
380
381struct hisi_sas_err_record {
8d1eee7d 382 u32 data[4];
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383};
384
385struct hisi_sas_initial_fis {
386 struct hisi_sas_err_record err_record;
387 struct dev_to_host_fis fis;
388 u32 rsvd[3];
389};
390
391struct hisi_sas_breakpoint {
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392 u8 data[128];
393};
394
395struct hisi_sas_sata_breakpoint {
396 struct hisi_sas_breakpoint tag[32];
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397};
398
399struct hisi_sas_sge {
400 __le64 addr;
401 __le32 page_ctrl_0;
402 __le32 page_ctrl_1;
403 __le32 data_len;
404 __le32 data_off;
405};
406
407struct hisi_sas_command_table_smp {
408 u8 bytes[44];
409};
410
411struct hisi_sas_command_table_stp {
412 struct host_to_dev_fis command_fis;
413 u8 dummy[12];
414 u8 atapi_cdb[ATAPI_CDB_LEN];
415};
416
65e8617f 417#define HISI_SAS_SGE_PAGE_CNT SG_CHUNK_SIZE
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418struct hisi_sas_sge_page {
419 struct hisi_sas_sge sge[HISI_SAS_SGE_PAGE_CNT];
f557e32c 420} __aligned(16);
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421
422struct hisi_sas_command_table_ssp {
423 struct ssp_frame_hdr hdr;
424 union {
425 struct {
426 struct ssp_command_iu task;
a14da7a2 427 u32 prot[7];
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428 };
429 struct ssp_tmf_iu ssp_task;
430 struct xfer_rdy_iu xfer_rdy;
431 struct ssp_response_iu ssp_res;
432 } u;
433};
434
435union hisi_sas_command_table {
436 struct hisi_sas_command_table_ssp ssp;
437 struct hisi_sas_command_table_smp smp;
438 struct hisi_sas_command_table_stp stp;
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439} __aligned(16);
440
441struct hisi_sas_status_buffer {
442 struct hisi_sas_err_record err;
443 u8 iu[1024];
444} __aligned(16);
445
446struct hisi_sas_slot_buf_table {
447 struct hisi_sas_status_buffer status_buffer;
448 union hisi_sas_command_table command_header;
449 struct hisi_sas_sge_page sge_page;
c799d6bd 450};
2e244f0f 451
e21fe3a5 452extern struct scsi_transport_template *hisi_sas_stt;
a25d0d3d 453extern void hisi_sas_stop_phys(struct hisi_hba *hisi_hba);
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454extern int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost);
455extern void hisi_sas_free(struct hisi_hba *hisi_hba);
468f4b8d 456extern u8 hisi_sas_get_ata_protocol(struct host_to_dev_fis *fis,
457 int direction);
2e244f0f 458extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
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459extern void hisi_sas_sata_done(struct sas_task *task,
460 struct hisi_sas_slot *slot);
318913c6 461extern int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag);
0fa24c19 462extern int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba);
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463extern int hisi_sas_probe(struct platform_device *pdev,
464 const struct hisi_sas_hw *ops);
465extern int hisi_sas_remove(struct platform_device *pdev);
c799d6bd 466
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467extern int hisi_sas_slave_configure(struct scsi_device *sdev);
468extern int hisi_sas_scan_finished(struct Scsi_Host *shost, unsigned long time);
469extern void hisi_sas_scan_start(struct Scsi_Host *shost);
470extern struct device_attribute *host_attrs[];
471extern int hisi_sas_host_reset(struct Scsi_Host *shost, int reset_type);
184a4635 472extern void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy);
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473extern void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba,
474 struct sas_task *task,
475 struct hisi_sas_slot *slot);
06ec0fb9 476extern void hisi_sas_init_mem(struct hisi_hba *hisi_hba);
b4241f0f 477extern void hisi_sas_rst_work_handler(struct work_struct *work);
e402acdb 478extern void hisi_sas_sync_rst_work_handler(struct work_struct *work);
571295f8 479extern void hisi_sas_kill_tasklets(struct hisi_hba *hisi_hba);
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480extern bool hisi_sas_notify_phy_event(struct hisi_sas_phy *phy,
481 enum hisi_sas_phy_event event);
4d0951ee 482extern void hisi_sas_release_tasks(struct hisi_hba *hisi_hba);
c2c1d9de 483extern u8 hisi_sas_get_prog_phy_linkrate_mask(enum sas_linkrate max);
e8899fad 484#endif