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scsi: hisi_sas: Rename hisi_sas_cq.pci_irq_mask
[mirror_ubuntu-focal-kernel.git] / drivers / scsi / hisi_sas / hisi_sas.h
CommitLineData
2874c5fd 1/* SPDX-License-Identifier: GPL-2.0-or-later */
e8899fad
JG		 2/*
3 * Copyright (c) 2015 Linaro Ltd.
4 * Copyright (c) 2015 Hisilicon Limited.
e8899fad
JG		 5 */
6
7#ifndef _HISI_SAS_H_
8#define _HISI_SAS_H_
9
4d558c77 10#include <linux/acpi.h>
3bc45af8 11#include <linux/clk.h>
ef63464b 12#include <linux/debugfs.h>
e8899fad 13#include <linux/dmapool.h>
a25d0d3d 14#include <linux/iopoll.h>
2ba5afb6 15#include <linux/lcm.h>
57dbb2b2 16#include <linux/libata.h>
e8899fad
JG		 17#include <linux/mfd/syscon.h>
18#include <linux/module.h>
19#include <linux/of_address.h>
11b75249 20#include <linux/pci.h>
e8899fad 21#include <linux/platform_device.h>
4d558c77 22#include <linux/property.h>
e8899fad 23#include <linux/regmap.h>
7c8f89cf 24#include <linux/timer.h>
6f2ff1a1 25#include <scsi/sas_ata.h>
e8899fad
JG		 26#include <scsi/libsas.h>
27
7eb7869f 28#define HISI_SAS_MAX_PHYS 9
6be6de18 29#define HISI_SAS_MAX_QUEUES 32
1273d65f 30#define HISI_SAS_QUEUE_SLOTS 4096
3297ded1 31#define HISI_SAS_MAX_ITCT_ENTRIES 1024
7eb7869f 32#define HISI_SAS_MAX_DEVICES HISI_SAS_MAX_ITCT_ENTRIES
06ec0fb9 33#define HISI_SAS_RESET_BIT 0
917d3bda 34#define HISI_SAS_REJECT_CMD_BIT 1
93352abc
JG		 35#define HISI_SAS_MAX_COMMANDS (HISI_SAS_QUEUE_SLOTS)
36#define HISI_SAS_RESERVED_IPTT 96
37#define HISI_SAS_UNRESERVED_IPTT \
38 (HISI_SAS_MAX_COMMANDS - HISI_SAS_RESERVED_IPTT)
7eb7869f 39
bbe0a7b3
LJ		 40#define HISI_SAS_IOST_ITCT_CACHE_NUM 64
41#define HISI_SAS_IOST_ITCT_CACHE_DW_SZ 10
42
f557e32c
XT		 43#define HISI_SAS_STATUS_BUF_SZ (sizeof(struct hisi_sas_status_buffer))
44#define HISI_SAS_COMMAND_TABLE_SZ (sizeof(union hisi_sas_command_table))
45
46#define hisi_sas_status_buf_addr(buf) \
b3cce125
XC		 47 ((buf) + offsetof(struct hisi_sas_slot_buf_table, status_buffer))
48#define hisi_sas_status_buf_addr_mem(slot) hisi_sas_status_buf_addr((slot)->buf)
f557e32c 49#define hisi_sas_status_buf_addr_dma(slot) \
b3cce125 50 hisi_sas_status_buf_addr((slot)->buf_dma)
f557e32c
XT		 51
52#define hisi_sas_cmd_hdr_addr(buf) \
b3cce125
XC		 53 ((buf) + offsetof(struct hisi_sas_slot_buf_table, command_header))
54#define hisi_sas_cmd_hdr_addr_mem(slot) hisi_sas_cmd_hdr_addr((slot)->buf)
55#define hisi_sas_cmd_hdr_addr_dma(slot) hisi_sas_cmd_hdr_addr((slot)->buf_dma)
f557e32c
XT		 56
57#define hisi_sas_sge_addr(buf) \
b3cce125
XC		 58 ((buf) + offsetof(struct hisi_sas_slot_buf_table, sge_page))
59#define hisi_sas_sge_addr_mem(slot) hisi_sas_sge_addr((slot)->buf)
60#define hisi_sas_sge_addr_dma(slot) hisi_sas_sge_addr((slot)->buf_dma)
61
62#define hisi_sas_sge_dif_addr(buf) \
63 ((buf) + offsetof(struct hisi_sas_slot_dif_buf_table, sge_dif_page))
64#define hisi_sas_sge_dif_addr_mem(slot) hisi_sas_sge_dif_addr((slot)->buf)
65#define hisi_sas_sge_dif_addr_dma(slot) hisi_sas_sge_dif_addr((slot)->buf_dma)
6be6de18 66
42e7a693 67#define HISI_SAS_MAX_SSP_RESP_SZ (sizeof(struct ssp_frame_hdr) + 1024)
66ee999b 68#define HISI_SAS_MAX_SMP_RESP_SZ 1028
6f2ff1a1 69#define HISI_SAS_MAX_STP_RESP_SZ 28
42e7a693 70
6c7bb8a1
XC		 71#define HISI_SAS_SATA_PROTOCOL_NONDATA 0x1
72#define HISI_SAS_SATA_PROTOCOL_PIO 0x2
73#define HISI_SAS_SATA_PROTOCOL_DMA 0x4
74#define HISI_SAS_SATA_PROTOCOL_FPDMA 0x8
75#define HISI_SAS_SATA_PROTOCOL_ATAPI 0x10
76
d6a9000b
XC		 77#define HISI_SAS_DIF_PROT_MASK (SHOST_DIF_TYPE1_PROTECTION | \
78 SHOST_DIF_TYPE2_PROTECTION | \
79 SHOST_DIF_TYPE3_PROTECTION)
80
b3cce125
XC		 81#define HISI_SAS_DIX_PROT_MASK (SHOST_DIX_TYPE1_PROTECTION | \
82 SHOST_DIX_TYPE2_PROTECTION | \
83 SHOST_DIX_TYPE3_PROTECTION)
84
85#define HISI_SAS_PROT_MASK (HISI_SAS_DIF_PROT_MASK | HISI_SAS_DIX_PROT_MASK)
d6a9000b 86
b6c9b15e 87#define HISI_SAS_WAIT_PHYUP_TIMEOUT 20
6a79e8ce 88#define CLEAR_ITCT_TIMEOUT 20
b6c9b15e 89
abda97c2 90struct hisi_hba;
af740dbe 91
07d78592
JG		 92enum {
93 PORT_TYPE_SAS = (1U << 1),
94 PORT_TYPE_SATA = (1U << 0),
95};
96
57dbb2b2
XC		 97enum dev_status {
98 HISI_SAS_DEV_INIT,
99 HISI_SAS_DEV_NORMAL,
100};
101
441c2740
JG		 102enum {
103 HISI_SAS_INT_ABT_CMD = 0,
104 HISI_SAS_INT_ABT_DEV = 1,
105};
106
abda97c2
JG		 107enum hisi_sas_dev_type {
108 HISI_SAS_DEV_TYPE_STP = 0,
109 HISI_SAS_DEV_TYPE_SSP,
110 HISI_SAS_DEV_TYPE_SATA,
111};
112
2b383351
JG		 113struct hisi_sas_hw_error {
114 u32 irq_msk;
115 u32 msk;
116 int shift;
117 const char *msg;
118 int reg;
729428ca 119 const struct hisi_sas_hw_error *sub;
2b383351
JG		 120};
121
e402acdb
XT		 122struct hisi_sas_rst {
123 struct hisi_hba *hisi_hba;
124 struct completion *completion;
125 struct work_struct work;
126 bool done;
127};
128
129#define HISI_SAS_RST_WORK_INIT(r, c) \
130 { .hisi_hba = hisi_hba, \
131 .completion = &c, \
132 .work = __WORK_INITIALIZER(r.work, \
133 hisi_sas_sync_rst_work_handler), \
134 .done = false, \
135 }
136
137#define HISI_SAS_DECLARE_RST_WORK_ON_STACK(r) \
138 DECLARE_COMPLETION_ONSTACK(c); \
e402acdb
XT		 139 struct hisi_sas_rst r = HISI_SAS_RST_WORK_INIT(r, c)
140
141enum hisi_sas_bit_err_type {
142 HISI_SAS_ERR_SINGLE_BIT_ECC = 0x0,
143 HISI_SAS_ERR_MULTI_BIT_ECC = 0x1,
144};
145
e537b62b
XT		 146enum hisi_sas_phy_event {
147 HISI_PHYE_PHY_UP = 0U,
057c3d1f 148 HISI_PHYE_LINK_RESET,
e537b62b
XT		 149 HISI_PHYES_NUM,
150};
151
7eb7869f 152struct hisi_sas_phy {
e537b62b 153 struct work_struct works[HISI_PHYES_NUM];
976867e6
JG		 154 struct hisi_hba *hisi_hba;
155 struct hisi_sas_port *port;
7eb7869f 156 struct asd_sas_phy sas_phy;
976867e6 157 struct sas_identify identify;
3e1fb1b8 158 struct completion *reset_completion;
b6c9b15e 159 struct timer_list timer;
3e1fb1b8 160 spinlock_t lock;
976867e6 161 u64 port_id; /* from hw */
976867e6
JG		 162 u64 frame_rcvd_size;
163 u8 frame_rcvd[32];
164 u8 phy_attached;
3e1fb1b8
XC		 165 u8 in_reset;
166 u8 reserved[2];
d0ef10c9 167 u32 phy_type;
aaeb8232 168 u32 code_violation_err_count;
976867e6
JG		 169 enum sas_linkrate minimum_linkrate;
170 enum sas_linkrate maximum_linkrate;
c63b88cc 171 int enable;
95f554e0 172 atomic_t down_cnt;
7eb7869f
JG		 173};
174
175struct hisi_sas_port {
176 struct asd_sas_port sas_port;
976867e6
JG		 177 u8 port_attached;
178 u8 id; /* from hw */
7eb7869f
JG		 179};
180
9101a079
JG		 181struct hisi_sas_cq {
182 struct hisi_hba *hisi_hba;
b79c1224 183 const struct cpumask *irq_mask;
e6c346f3 184 int rd_point;
9101a079 185 int id;
1c45ed44 186 int irq_no;
9101a079
JG		 187};
188
4fde02ad
JG		 189struct hisi_sas_dq {
190 struct hisi_hba *hisi_hba;
fa222db0 191 struct list_head list;
b1a49412 192 spinlock_t lock;
4fde02ad
JG		 193 int wr_point;
194 int id;
195};
196
af740dbe 197struct hisi_sas_device {
abda97c2
JG		 198 struct hisi_hba *hisi_hba;
199 struct domain_device *sas_device;
640acc9a 200 struct completion *completion;
b1a49412 201 struct hisi_sas_dq *dq;
ad604832 202 struct list_head list;
ad604832 203 enum sas_device_type dev_type;
57dbb2b2 204 enum dev_status dev_status;
ad604832 205 int device_id;
32ccba52 206 int sata_idx;
4fefe5bb 207 spinlock_t lock; /* For protecting slots */
af740dbe
JG		 208};
209
78bd2b4f 210struct hisi_sas_tmf_task {
b09fcd09
XT		 211 int force_phy;
212 int phy_id;
78bd2b4f
XT		 213 u8 tmf;
214 u16 tag_of_task_to_be_managed;
215};
216
6be6de18 217struct hisi_sas_slot {
42e7a693 218 struct list_head entry;
fa222db0 219 struct list_head delivery;
42e7a693
JG		 220 struct sas_task *task;
221 struct hisi_sas_port *port;
222 u64 n_elem;
b3cce125 223 u64 n_elem_dif;
42e7a693
JG		 224 int dlvry_queue;
225 int dlvry_queue_slot;
27a3f229
JG		 226 int cmplt_queue;
227 int cmplt_queue_slot;
cac9b2a2 228 int abort;
fa222db0 229 int ready;
4fefe5bb 230 int device_id;
42e7a693
JG		 231 void *cmd_hdr;
232 dma_addr_t cmd_hdr_dma;
0844a3ff 233 struct timer_list internal_abort_timer;
cd938e53 234 bool is_internal;
78bd2b4f 235 struct hisi_sas_tmf_task *tmf;
2ba5afb6
XC		 236 /* Do not reorder/change members after here */
237 void *buf;
238 dma_addr_t buf_dma;
735bcc77 239 u16 idx;
6be6de18
JG		 240};
241
caefac19
LJ		 242#define HISI_SAS_DEBUGFS_REG(x) {#x, x}
243
244struct hisi_sas_debugfs_reg_lu {
245 char *name;
246 int off;
247};
248
eb1c2b72 249struct hisi_sas_debugfs_reg {
caefac19 250 const struct hisi_sas_debugfs_reg_lu *lu;
eb1c2b72 251 int count;
49159a5e
LJ		 252 int base_off;
253 union {
254 u32 (*read_global_reg)(struct hisi_hba *hisi_hba, u32 off);
255 u32 (*read_port_reg)(struct hisi_hba *hisi_hba, int port,
256 u32 off);
257 };
eb1c2b72
LJ		 258};
259
bbe0a7b3
LJ		 260struct hisi_sas_iost_itct_cache {
261 u32 data[HISI_SAS_IOST_ITCT_CACHE_DW_SZ];
262};
263
b0b3e429
LJ		 264enum hisi_sas_debugfs_reg_array_member {
265 DEBUGFS_GLOBAL = 0,
266 DEBUGFS_AXI,
267 DEBUGFS_RAS,
268 DEBUGFS_REGS_NUM
269};
270
bbe0a7b3
LJ		 271enum hisi_sas_debugfs_cache_type {
272 HISI_SAS_ITCT_CACHE,
273 HISI_SAS_IOST_CACHE,
274};
275
7eb7869f 276struct hisi_sas_hw {
8ff1d571 277 int (*hw_init)(struct hisi_hba *hisi_hba);
abda97c2
JG		 278 void (*setup_itct)(struct hisi_hba *hisi_hba,
279 struct hisi_sas_device *device);
784b46b7 280 int (*slot_index_alloc)(struct hisi_hba *hisi_hba,
685b6d6e
JG		 281 struct domain_device *device);
282 struct hisi_sas_device *(*alloc_dev)(struct domain_device *device);
569eddcf 283 void (*sl_notify_ssp)(struct hisi_hba *hisi_hba, int phy_no);
b1a49412 284 void (*start_delivery)(struct hisi_sas_dq *dq);
a2b3820b 285 void (*prep_ssp)(struct hisi_hba *hisi_hba,
78bd2b4f 286 struct hisi_sas_slot *slot);
a2b3820b 287 void (*prep_smp)(struct hisi_hba *hisi_hba,
66ee999b 288 struct hisi_sas_slot *slot);
a2b3820b 289 void (*prep_stp)(struct hisi_hba *hisi_hba,
6f2ff1a1 290 struct hisi_sas_slot *slot);
a2b3820b 291 void (*prep_abort)(struct hisi_hba *hisi_hba,
441c2740
JG		 292 struct hisi_sas_slot *slot,
293 int device_id, int abort_flag, int tag_to_abort);
396b8044 294 void (*phys_init)(struct hisi_hba *hisi_hba);
1eb8eeac 295 void (*phy_start)(struct hisi_hba *hisi_hba, int phy_no);
e4189d53
JG		 296 void (*phy_disable)(struct hisi_hba *hisi_hba, int phy_no);
297 void (*phy_hard_reset)(struct hisi_hba *hisi_hba, int phy_no);
c52108c6 298 void (*get_events)(struct hisi_hba *hisi_hba, int phy_no);
2ae75787
XC		 299 void (*phy_set_linkrate)(struct hisi_hba *hisi_hba, int phy_no,
300 struct sas_phy_linkrates *linkrates);
301 enum sas_linkrate (*phy_get_max_linkrate)(void);
6a79e8ce
XC		 302 int (*clear_itct)(struct hisi_hba *hisi_hba,
303 struct hisi_sas_device *dev);
0258141a 304 void (*free_device)(struct hisi_sas_device *sas_dev);
184a4635 305 int (*get_wideport_bitmap)(struct hisi_hba *hisi_hba, int port_id);
d30ff263
XC		 306 void (*dereg_device)(struct hisi_hba *hisi_hba,
307 struct domain_device *device);
06ec0fb9 308 int (*soft_reset)(struct hisi_hba *hisi_hba);
917d3bda 309 u32 (*get_phys_state)(struct hisi_hba *hisi_hba);
6379c560
XT		 310 int (*write_gpio)(struct hisi_hba *hisi_hba, u8 reg_type,
311 u8 reg_index, u8 reg_count, u8 *write_data);
4bc05809
LJ		 312 void (*wait_cmds_complete_timeout)(struct hisi_hba *hisi_hba,
313 int delay_ms, int timeout_ms);
49159a5e
LJ		 314 void (*snapshot_prepare)(struct hisi_hba *hisi_hba);
315 void (*snapshot_restore)(struct hisi_hba *hisi_hba);
97b151e7 316 int (*set_bist)(struct hisi_hba *hisi_hba, bool enable);
bbe0a7b3
LJ		 317 void (*read_iost_itct_cache)(struct hisi_hba *hisi_hba,
318 enum hisi_sas_debugfs_cache_type type,
319 u32 *cache);
6be6de18 320 int complete_hdr_size;
235bfc7f 321 struct scsi_host_template *sht;
eb1c2b72 322
b0b3e429 323 const struct hisi_sas_debugfs_reg *debugfs_reg_array[DEBUGFS_REGS_NUM];
eb1c2b72 324 const struct hisi_sas_debugfs_reg *debugfs_reg_port;
7eb7869f
JG		 325};
326
10103602
LJ		 327#define HISI_SAS_MAX_DEBUGFS_DUMP (50)
328
570f39a0
LJ		 329struct hisi_sas_debugfs_cq {
330 struct hisi_sas_cq *cq;
331 void *complete_hdr;
332};
333
b3c8cc24
LJ		 334struct hisi_sas_debugfs_dq {
335 struct hisi_sas_dq *dq;
336 struct hisi_sas_cmd_hdr *hdr;
337};
338
0e85dbd6
LJ		 339struct hisi_sas_debugfs_regs {
340 struct hisi_hba *hisi_hba;
341 u32 *data;
342};
343
dbb7ed88
LJ		 344struct hisi_sas_debugfs_port {
345 struct hisi_sas_phy *phy;
346 u32 *data;
347};
348
e676a50c
LJ		 349struct hisi_sas_debugfs_iost {
350 struct hisi_sas_iost *iost;
351};
352
f5e7a0a1
LJ		 353struct hisi_sas_debugfs_itct {
354 struct hisi_sas_itct *itct;
355};
356
ceace9d5
LJ		 357struct hisi_sas_debugfs_iost_cache {
358 struct hisi_sas_iost_itct_cache *cache;
359};
360
39b96d66
LJ		 361struct hisi_sas_debugfs_itct_cache {
362 struct hisi_sas_iost_itct_cache *cache;
363};
364
7eb7869f
JG		 365struct hisi_hba {
366 /* This must be the first element, used by SHOST_TO_SAS_HA */
367 struct sas_ha_struct *p;
368
11b75249
JG		 369 struct platform_device *platform_dev;
370 struct pci_dev *pci_dev;
371 struct device *dev;
372
d6a9000b
XC		 373 int prot_mask;
374
e26b2f40 375 void __iomem *regs;
6379c560 376 void __iomem *sgpio_regs;
e26b2f40
JG		 377 struct regmap *ctrl;
378 u32 ctrl_reset_reg;
379 u32 ctrl_reset_sts_reg;
380 u32 ctrl_clock_ena_reg;
3bc45af8 381 u32 refclk_frequency_mhz;
7eb7869f
JG		 382 u8 sas_addr[SAS_ADDR_SIZE];
383
384 int n_phy;
fa42d80d 385 spinlock_t lock;
d2fc401e 386 struct semaphore sem;
7eb7869f 387
fa42d80d 388 struct timer_list timer;
7e9080e1 389 struct workqueue_struct *wq;
257efd1f
JG		 390
391 int slot_index_count;
fa3be0f2 392 int last_slot_index;
1b865185 393 int last_dev_id;
257efd1f 394 unsigned long *slot_index_tags;
c7b9d369 395 unsigned long reject_stp_links_msk;
257efd1f 396
7eb7869f
JG		 397 /* SCSI/SAS glue */
398 struct sas_ha_struct sha;
399 struct Scsi_Host *shost;
9101a079
JG		 400
401 struct hisi_sas_cq cq[HISI_SAS_MAX_QUEUES];
4fde02ad 402 struct hisi_sas_dq dq[HISI_SAS_MAX_QUEUES];
7eb7869f
JG		 403 struct hisi_sas_phy phy[HISI_SAS_MAX_PHYS];
404 struct hisi_sas_port port[HISI_SAS_MAX_PHYS];
e26b2f40
JG		 405
406 int queue_count;
6be6de18 407
af740dbe 408 struct hisi_sas_device devices[HISI_SAS_MAX_DEVICES];
6be6de18
JG		 409 struct hisi_sas_cmd_hdr *cmd_hdr[HISI_SAS_MAX_QUEUES];
410 dma_addr_t cmd_hdr_dma[HISI_SAS_MAX_QUEUES];
411 void *complete_hdr[HISI_SAS_MAX_QUEUES];
412 dma_addr_t complete_hdr_dma[HISI_SAS_MAX_QUEUES];
413 struct hisi_sas_initial_fis *initial_fis;
414 dma_addr_t initial_fis_dma;
415 struct hisi_sas_itct *itct;
416 dma_addr_t itct_dma;
417 struct hisi_sas_iost *iost;
418 dma_addr_t iost_dma;
419 struct hisi_sas_breakpoint *breakpoint;
420 dma_addr_t breakpoint_dma;
421 struct hisi_sas_breakpoint *sata_breakpoint;
422 dma_addr_t sata_breakpoint_dma;
423 struct hisi_sas_slot *slot_info;
06ec0fb9 424 unsigned long flags;
7eb7869f 425 const struct hisi_sas_hw *hw; /* Low level hw interface */
32ccba52 426 unsigned long sata_dev_bitmap[BITS_TO_LONGS(HISI_SAS_MAX_DEVICES)];
06ec0fb9 427 struct work_struct rst_work;
49159a5e 428 struct work_struct debugfs_work;
4522204a 429 u32 phy_state;
37359798
XC		 430 u32 intr_coal_ticks; /* Time of interrupt coalesce in us */
431 u32 intr_coal_count; /* Interrupt count to coalesce */
ef63464b 432
795f25a3 433 int cq_nvecs;
4fefe5bb 434 unsigned int *reply_map;
795f25a3 435
97b151e7
XC		 436 /* bist */
437 enum sas_linkrate debugfs_bist_linkrate;
438 int debugfs_bist_code_mode;
439 int debugfs_bist_phy_no;
440 int debugfs_bist_mode;
441 u32 debugfs_bist_cnt;
442 int debugfs_bist_enable;
443
eb1c2b72 444 /* debugfs memories */
b0b3e429 445 /* Put Global AXI and RAS Register into register array */
10103602
LJ		 446 struct hisi_sas_debugfs_regs debugfs_regs[HISI_SAS_MAX_DEBUGFS_DUMP][DEBUGFS_REGS_NUM];
447 struct hisi_sas_debugfs_port debugfs_port_reg[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_PHYS];
448 struct hisi_sas_debugfs_cq debugfs_cq[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_QUEUES];
449 struct hisi_sas_debugfs_dq debugfs_dq[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_QUEUES];
450 struct hisi_sas_debugfs_iost debugfs_iost[HISI_SAS_MAX_DEBUGFS_DUMP];
451 struct hisi_sas_debugfs_itct debugfs_itct[HISI_SAS_MAX_DEBUGFS_DUMP];
452 struct hisi_sas_debugfs_iost_cache debugfs_iost_cache[HISI_SAS_MAX_DEBUGFS_DUMP];
453 struct hisi_sas_debugfs_itct_cache debugfs_itct_cache[HISI_SAS_MAX_DEBUGFS_DUMP];
454
7b6e9606
LJ		 455 u64 debugfs_timestamp[HISI_SAS_MAX_DEBUGFS_DUMP];
456 int debugfs_dump_index;
ef63464b 457 struct dentry *debugfs_dir;
49159a5e 458 struct dentry *debugfs_dump_dentry;
97b151e7 459 struct dentry *debugfs_bist_dentry;
7eb7869f
JG		 460};
461
c799d6bd
JG		 462/* Generic HW DMA host memory structures */
463/* Delivery queue header */
464struct hisi_sas_cmd_hdr {
465 /* dw0 */
466 __le32 dw0;
467
468 /* dw1 */
469 __le32 dw1;
470
471 /* dw2 */
472 __le32 dw2;
473
474 /* dw3 */
475 __le32 transfer_tags;
476
477 /* dw4 */
478 __le32 data_transfer_len;
479
480 /* dw5 */
481 __le32 first_burst_num;
482
483 /* dw6 */
484 __le32 sg_len;
485
486 /* dw7 */
487 __le32 dw7;
488
489 /* dw8-9 */
490 __le64 cmd_table_addr;
491
492 /* dw10-11 */
493 __le64 sts_buffer_addr;
494
495 /* dw12-13 */
496 __le64 prd_table_addr;
497
498 /* dw14-15 */
499 __le64 dif_prd_table_addr;
500};
501
502struct hisi_sas_itct {
503 __le64 qw0;
504 __le64 sas_addr;
505 __le64 qw2;
506 __le64 qw3;
281e3bf6 507 __le64 qw4_15[12];
c799d6bd
JG		 508};
509
510struct hisi_sas_iost {
511 __le64 qw0;
512 __le64 qw1;
513 __le64 qw2;
514 __le64 qw3;
515};
516
517struct hisi_sas_err_record {
8d1eee7d 518 u32 data[4];
c799d6bd
JG		 519};
520
521struct hisi_sas_initial_fis {
522 struct hisi_sas_err_record err_record;
523 struct dev_to_host_fis fis;
524 u32 rsvd[3];
525};
526
527struct hisi_sas_breakpoint {
3297ded1
XC		 528 u8 data[128];
529};
530
531struct hisi_sas_sata_breakpoint {
532 struct hisi_sas_breakpoint tag[32];
c799d6bd
JG		 533};
534
535struct hisi_sas_sge {
536 __le64 addr;
537 __le32 page_ctrl_0;
538 __le32 page_ctrl_1;
539 __le32 data_len;
540 __le32 data_off;
541};
542
543struct hisi_sas_command_table_smp {
544 u8 bytes[44];
545};
546
547struct hisi_sas_command_table_stp {
548 struct host_to_dev_fis command_fis;
549 u8 dummy[12];
550 u8 atapi_cdb[ATAPI_CDB_LEN];
551};
552
c7669f50 553#define HISI_SAS_SGE_PAGE_CNT (124)
c799d6bd
JG		 554struct hisi_sas_sge_page {
555 struct hisi_sas_sge sge[HISI_SAS_SGE_PAGE_CNT];
f557e32c 556} __aligned(16);
c799d6bd 557
c7669f50 558#define HISI_SAS_SGE_DIF_PAGE_CNT HISI_SAS_SGE_PAGE_CNT
b3cce125
XC		 559struct hisi_sas_sge_dif_page {
560 struct hisi_sas_sge sge[HISI_SAS_SGE_DIF_PAGE_CNT];
561} __aligned(16);
562
c799d6bd
JG		 563struct hisi_sas_command_table_ssp {
564 struct ssp_frame_hdr hdr;
565 union {
566 struct {
567 struct ssp_command_iu task;
a14da7a2 568 u32 prot[7];
c799d6bd
JG		 569 };
570 struct ssp_tmf_iu ssp_task;
571 struct xfer_rdy_iu xfer_rdy;
572 struct ssp_response_iu ssp_res;
573 } u;
574};
575
576union hisi_sas_command_table {
577 struct hisi_sas_command_table_ssp ssp;
578 struct hisi_sas_command_table_smp smp;
579 struct hisi_sas_command_table_stp stp;
f557e32c
XT		 580} __aligned(16);
581
582struct hisi_sas_status_buffer {
583 struct hisi_sas_err_record err;
584 u8 iu[1024];
585} __aligned(16);
586
587struct hisi_sas_slot_buf_table {
588 struct hisi_sas_status_buffer status_buffer;
589 union hisi_sas_command_table command_header;
590 struct hisi_sas_sge_page sge_page;
c799d6bd 591};
2e244f0f 592
b3cce125
XC		 593struct hisi_sas_slot_dif_buf_table {
594 struct hisi_sas_slot_buf_table slot_buf;
595 struct hisi_sas_sge_dif_page sge_dif_page;
596};
597
e21fe3a5 598extern struct scsi_transport_template *hisi_sas_stt;
ef63464b
LJ		 599
600extern bool hisi_sas_debugfs_enable;
42efdfd0 601extern u32 hisi_sas_debugfs_dump_count;
ef63464b
LJ		 602extern struct dentry *hisi_sas_debugfs_dir;
603
a25d0d3d 604extern void hisi_sas_stop_phys(struct hisi_hba *hisi_hba);
ae68b566 605extern int hisi_sas_alloc(struct hisi_hba *hisi_hba);
e21fe3a5 606extern void hisi_sas_free(struct hisi_hba *hisi_hba);
468f4b8d 607extern u8 hisi_sas_get_ata_protocol(struct host_to_dev_fis *fis,
608 int direction);
2e244f0f 609extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
75904077
XC		 610extern void hisi_sas_sata_done(struct sas_task *task,
611 struct hisi_sas_slot *slot);
0fa24c19 612extern int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba);
9fb10b54
JG		 613extern int hisi_sas_probe(struct platform_device *pdev,
614 const struct hisi_sas_hw *ops);
615extern int hisi_sas_remove(struct platform_device *pdev);
c799d6bd 616
235bfc7f
XC		 617extern int hisi_sas_slave_configure(struct scsi_device *sdev);
618extern int hisi_sas_scan_finished(struct Scsi_Host *shost, unsigned long time);
619extern void hisi_sas_scan_start(struct Scsi_Host *shost);
235bfc7f 620extern int hisi_sas_host_reset(struct Scsi_Host *shost, int reset_type);
c63b88cc
JG		 621extern void hisi_sas_phy_enable(struct hisi_hba *hisi_hba, int phy_no,
622 int enable);
184a4635 623extern void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy);
27a3f229
JG		 624extern void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba,
625 struct sas_task *task,
626 struct hisi_sas_slot *slot);
06ec0fb9 627extern void hisi_sas_init_mem(struct hisi_hba *hisi_hba);
b4241f0f 628extern void hisi_sas_rst_work_handler(struct work_struct *work);
e402acdb 629extern void hisi_sas_sync_rst_work_handler(struct work_struct *work);
1c45ed44 630extern void hisi_sas_sync_irqs(struct hisi_hba *hisi_hba);
b6c9b15e 631extern void hisi_sas_phy_oob_ready(struct hisi_hba *hisi_hba, int phy_no);
e537b62b
XT		 632extern bool hisi_sas_notify_phy_event(struct hisi_sas_phy *phy,
633 enum hisi_sas_phy_event event);
4d0951ee 634extern void hisi_sas_release_tasks(struct hisi_hba *hisi_hba);
c2c1d9de 635extern u8 hisi_sas_get_prog_phy_linkrate_mask(enum sas_linkrate max);
4522204a
XT		 636extern void hisi_sas_controller_reset_prepare(struct hisi_hba *hisi_hba);
637extern void hisi_sas_controller_reset_done(struct hisi_hba *hisi_hba);
ef63464b
LJ		 638extern void hisi_sas_debugfs_init(struct hisi_hba *hisi_hba);
639extern void hisi_sas_debugfs_exit(struct hisi_hba *hisi_hba);
49159a5e 640extern void hisi_sas_debugfs_work_handler(struct work_struct *work);
e8899fad 641#endif
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